--- dmp_ceff_elmore with varying loads --- No paths found. PASS: dmp_ceff_elmore tiny load Library: NangateOpenCellLibrary Cell: BUF_X1 Arc sense: positive_unate Arc type: combinational A ^ -> Z ^ P = 1.00 V = 1.10 T = 25.00 ------- input_net_transition = 0.01 | total_output_net_capacitance = 1.70 | 0.37 1.90 v -------------------- 0.00 | 0.02 0.02 0.02 | 0.02 0.03 Table value = 0.02 PVT scale factor = 1.00 Delay = 0.02 ------- input_net_transition = 0.01 | total_output_net_capacitance = 1.70 | 0.37 1.90 v -------------------- 0.00 | 0.00 0.01 0.02 | 0.00 0.01 Table value = 0.01 PVT scale factor = 1.00 Slew = 0.01 Driver waveform slew = 0.01 ............................................. A v -> Z v P = 1.00 V = 1.10 T = 25.00 ------- input_net_transition = 0.01 | total_output_net_capacitance = 1.55 | 0.37 1.90 v -------------------- 0.00 | 0.02 0.03 0.02 | 0.03 0.03 Table value = 0.03 PVT scale factor = 1.00 Delay = 0.03 ------- input_net_transition = 0.01 | total_output_net_capacitance = 1.55 | 0.37 1.90 v -------------------- 0.00 | 0.00 0.01 0.02 | 0.00 0.01 Table value = 0.01 PVT scale factor = 1.00 Slew = 0.01 Driver waveform slew = 0.01 ............................................. tiny load dcalc: No paths found. PASS: dmp_ceff_elmore small load Library: NangateOpenCellLibrary Cell: BUF_X1 Arc sense: positive_unate Arc type: combinational A ^ -> Z ^ P = 1.00 V = 1.10 T = 25.00 ------- input_net_transition = 0.05 | total_output_net_capacitance = 1.70 | 0.37 1.90 v -------------------- 0.04 | 0.03 0.03 0.08 | 0.03 0.03 Table value = 0.03 PVT scale factor = 1.00 Delay = 0.03 ------- input_net_transition = 0.05 | total_output_net_capacitance = 1.70 | 0.37 1.90 v -------------------- 0.04 | 0.01 0.01 0.08 | 0.01 0.01 Table value = 0.01 PVT scale factor = 1.00 Slew = 0.01 Driver waveform slew = 0.01 ............................................. A v -> Z v P = 1.00 V = 1.10 T = 25.00 ------- input_net_transition = 0.05 | total_output_net_capacitance = 1.55 | 0.37 1.90 v -------------------- 0.04 | 0.04 0.04 0.08 | 0.05 0.05 Table value = 0.04 PVT scale factor = 1.00 Delay = 0.04 ------- input_net_transition = 0.05 | total_output_net_capacitance = 1.55 | 0.37 1.90 v -------------------- 0.04 | 0.01 0.01 0.08 | 0.01 0.01 Table value = 0.01 PVT scale factor = 1.00 Slew = 0.01 Driver waveform slew = 0.01 ............................................. small load dcalc: No paths found. PASS: dmp_ceff_elmore medium load Library: NangateOpenCellLibrary Cell: BUF_X1 Arc sense: positive_unate Arc type: combinational A ^ -> Z ^ P = 1.00 V = 1.10 T = 25.00 ------- input_net_transition = 0.10 | total_output_net_capacitance = 1.70 | 0.37 1.90 v -------------------- 0.08 | 0.03 0.03 0.13 | 0.03 0.04 Table value = 0.03 PVT scale factor = 1.00 Delay = 0.03 ------- input_net_transition = 0.10 | total_output_net_capacitance = 1.70 | 0.37 1.90 v -------------------- 0.08 | 0.01 0.01 0.13 | 0.01 0.01 Table value = 0.01 PVT scale factor = 1.00 Slew = 0.01 Driver waveform slew = 0.01 ............................................. A v -> Z v P = 1.00 V = 1.10 T = 25.00 ------- input_net_transition = 0.10 | total_output_net_capacitance = 1.55 | 0.37 1.90 v -------------------- 0.08 | 0.05 0.05 0.13 | 0.06 0.07 Table value = 0.06 PVT scale factor = 1.00 Delay = 0.06 ------- input_net_transition = 0.10 | total_output_net_capacitance = 1.55 | 0.37 1.90 v -------------------- 0.08 | 0.01 0.01 0.13 | 0.01 0.01 Table value = 0.01 PVT scale factor = 1.00 Slew = 0.01 Driver waveform slew = 0.01 ............................................. medium load dcalc: No paths found. PASS: dmp_ceff_elmore large load Library: NangateOpenCellLibrary Cell: BUF_X1 Arc sense: positive_unate Arc type: combinational A ^ -> Z ^ P = 1.00 V = 1.10 T = 25.00 ------- input_net_transition = 0.50 | total_output_net_capacitance = 1.70 | 0.37 1.90 v -------------------- 0.13 | 0.03 0.04 0.20 | 0.03 0.03 Table value = 0.03 PVT scale factor = 1.00 Delay = 0.03 ------- input_net_transition = 0.50 | total_output_net_capacitance = 1.70 | 0.37 1.90 v -------------------- 0.13 | 0.01 0.01 0.20 | 0.01 0.01 Table value = 0.02 PVT scale factor = 1.00 Slew = 0.02 Driver waveform slew = 0.02 ............................................. A v -> Z v P = 1.00 V = 1.10 T = 25.00 ------- input_net_transition = 0.50 | total_output_net_capacitance = 1.55 | 0.37 1.90 v -------------------- 0.13 | 0.06 0.07 0.20 | 0.08 0.08 Table value = 0.14 PVT scale factor = 1.00 Delay = 0.14 ------- input_net_transition = 0.50 | total_output_net_capacitance = 1.55 | 0.37 1.90 v -------------------- 0.13 | 0.01 0.01 0.20 | 0.01 0.01 Table value = 0.02 PVT scale factor = 1.00 Slew = 0.02 Driver waveform slew = 0.02 ............................................. large load dcalc: No paths found. PASS: dmp_ceff_elmore very large load Library: NangateOpenCellLibrary Cell: BUF_X1 Arc sense: positive_unate Arc type: combinational A ^ -> Z ^ P = 1.00 V = 1.10 T = 25.00 ------- input_net_transition = 1.00 | total_output_net_capacitance = 1.70 | 0.37 1.90 v -------------------- 0.13 | 0.03 0.04 0.20 | 0.03 0.03 Table value = 0.02 PVT scale factor = 1.00 Delay = 0.02 ------- input_net_transition = 1.00 | total_output_net_capacitance = 1.70 | 0.37 1.90 v -------------------- 0.13 | 0.01 0.01 0.20 | 0.01 0.01 Table value = 0.04 PVT scale factor = 1.00 Slew = 0.04 Driver waveform slew = 0.04 ............................................. A v -> Z v P = 1.00 V = 1.10 T = 25.00 ------- input_net_transition = 1.00 | total_output_net_capacitance = 1.55 | 0.37 1.90 v -------------------- 0.13 | 0.06 0.07 0.20 | 0.08 0.08 Table value = 0.24 PVT scale factor = 1.00 Delay = 0.24 ------- input_net_transition = 1.00 | total_output_net_capacitance = 1.55 | 0.37 1.90 v -------------------- 0.13 | 0.01 0.01 0.20 | 0.01 0.01 Table value = 0.04 PVT scale factor = 1.00 Slew = 0.04 Driver waveform slew = 0.04 ............................................. very large load dcalc: --- dmp_ceff_two_pole with varying loads --- Startpoint: reg1 (rising edge-triggered flip-flop clocked by clk) Endpoint: out1 (output port clocked by clk) Path Group: clk Path Type: max Delay Time Description --------------------------------------------------------- 0.00 0.00 clock clk (rise edge) 0.00 0.00 clock network delay (ideal) 0.00 0.00 ^ reg1/CK (DFF_X1) 0.08 0.08 ^ reg1/Q (DFF_X1) 0.00 0.08 ^ out1 (out) 0.08 data arrival time 10.00 10.00 clock clk (rise edge) 0.00 10.00 clock network delay (ideal) 0.00 10.00 clock reconvergence pessimism 0.00 10.00 output external delay 10.00 data required time --------------------------------------------------------- 10.00 data required time -0.08 data arrival time --------------------------------------------------------- 9.92 slack (MET) dmp_two_pole out1 load=0.001: done Startpoint: reg1 (rising edge-triggered flip-flop clocked by clk) Endpoint: out1 (output port clocked by clk) Path Group: clk Path Type: max Delay Time Description --------------------------------------------------------- 0.00 0.00 clock clk (rise edge) 0.00 0.00 clock network delay (ideal) 0.00 0.00 ^ reg1/CK (DFF_X1) 0.08 0.08 ^ reg1/Q (DFF_X1) 0.00 0.08 ^ out1 (out) 0.08 data arrival time 10.00 10.00 clock clk (rise edge) 0.00 10.00 clock network delay (ideal) 0.00 10.00 clock reconvergence pessimism 0.00 10.00 output external delay 10.00 data required time --------------------------------------------------------- 10.00 data required time -0.08 data arrival time --------------------------------------------------------- 9.92 slack (MET) dmp_two_pole out1 load=0.01: done Startpoint: reg1 (rising edge-triggered flip-flop clocked by clk) Endpoint: out1 (output port clocked by clk) Path Group: clk Path Type: max Delay Time Description --------------------------------------------------------- 0.00 0.00 clock clk (rise edge) 0.00 0.00 clock network delay (ideal) 0.00 0.00 ^ reg1/CK (DFF_X1) 0.08 0.08 ^ reg1/Q (DFF_X1) 0.00 0.08 ^ out1 (out) 0.08 data arrival time 10.00 10.00 clock clk (rise edge) 0.00 10.00 clock network delay (ideal) 0.00 10.00 clock reconvergence pessimism 0.00 10.00 output external delay 10.00 data required time --------------------------------------------------------- 10.00 data required time -0.08 data arrival time --------------------------------------------------------- 9.92 slack (MET) dmp_two_pole out1 load=0.05: done Startpoint: reg1 (rising edge-triggered flip-flop clocked by clk) Endpoint: out1 (output port clocked by clk) Path Group: clk Path Type: max Delay Time Description --------------------------------------------------------- 0.00 0.00 clock clk (rise edge) 0.00 0.00 clock network delay (ideal) 0.00 0.00 ^ reg1/CK (DFF_X1) 0.08 0.08 ^ reg1/Q (DFF_X1) 0.00 0.08 ^ out1 (out) 0.08 data arrival time 10.00 10.00 clock clk (rise edge) 0.00 10.00 clock network delay (ideal) 0.00 10.00 clock reconvergence pessimism 0.00 10.00 output external delay 10.00 data required time --------------------------------------------------------- 10.00 data required time -0.08 data arrival time --------------------------------------------------------- 9.92 slack (MET) dmp_two_pole out1 load=0.1: done Startpoint: reg2 (rising edge-triggered flip-flop clocked by clk) Endpoint: out2 (output port clocked by clk) Path Group: clk Path Type: max Delay Time Description --------------------------------------------------------- 0.00 0.00 clock clk (rise edge) 0.00 0.00 clock network delay (ideal) 0.00 0.00 ^ reg2/CK (DFF_X1) 0.08 0.08 ^ reg2/Q (DFF_X1) 0.00 0.08 ^ out2 (out) 0.08 data arrival time 10.00 10.00 clock clk (rise edge) 0.00 10.00 clock network delay (ideal) 0.00 10.00 clock reconvergence pessimism 0.00 10.00 output external delay 10.00 data required time --------------------------------------------------------- 10.00 data required time -0.08 data arrival time --------------------------------------------------------- 9.92 slack (MET) dmp_two_pole out2 load=0.001: done Startpoint: reg2 (rising edge-triggered flip-flop clocked by clk) Endpoint: out2 (output port clocked by clk) Path Group: clk Path Type: max Delay Time Description --------------------------------------------------------- 0.00 0.00 clock clk (rise edge) 0.00 0.00 clock network delay (ideal) 0.00 0.00 ^ reg2/CK (DFF_X1) 0.08 0.08 ^ reg2/Q (DFF_X1) 0.00 0.08 ^ out2 (out) 0.08 data arrival time 10.00 10.00 clock clk (rise edge) 0.00 10.00 clock network delay (ideal) 0.00 10.00 clock reconvergence pessimism 0.00 10.00 output external delay 10.00 data required time --------------------------------------------------------- 10.00 data required time -0.08 data arrival time --------------------------------------------------------- 9.92 slack (MET) dmp_two_pole out2 load=0.01: done Startpoint: reg2 (rising edge-triggered flip-flop clocked by clk) Endpoint: out2 (output port clocked by clk) Path Group: clk Path Type: max Delay Time Description --------------------------------------------------------- 0.00 0.00 clock clk (rise edge) 0.00 0.00 clock network delay (ideal) 0.00 0.00 ^ reg2/CK (DFF_X1) 0.08 0.08 ^ reg2/Q (DFF_X1) 0.00 0.08 ^ out2 (out) 0.08 data arrival time 10.00 10.00 clock clk (rise edge) 0.00 10.00 clock network delay (ideal) 0.00 10.00 clock reconvergence pessimism 0.00 10.00 output external delay 10.00 data required time --------------------------------------------------------- 10.00 data required time -0.08 data arrival time --------------------------------------------------------- 9.92 slack (MET) dmp_two_pole out2 load=0.05: done Startpoint: reg2 (rising edge-triggered flip-flop clocked by clk) Endpoint: out2 (output port clocked by clk) Path Group: clk Path Type: max Delay Time Description --------------------------------------------------------- 0.00 0.00 clock clk (rise edge) 0.00 0.00 clock network delay (ideal) 0.00 0.00 ^ reg2/CK (DFF_X1) 0.08 0.08 ^ reg2/Q (DFF_X1) 0.00 0.08 ^ out2 (out) 0.08 data arrival time 10.00 10.00 clock clk (rise edge) 0.00 10.00 clock network delay (ideal) 0.00 10.00 clock reconvergence pessimism 0.00 10.00 output external delay 10.00 data required time --------------------------------------------------------- 10.00 data required time -0.08 data arrival time --------------------------------------------------------- 9.92 slack (MET) dmp_two_pole out2 load=0.1: done Startpoint: in1 (input port clocked by clk) Endpoint: out3 (output port clocked by clk) Path Group: clk Path Type: max Delay Time Description --------------------------------------------------------- 0.00 0.00 clock clk (rise edge) 0.00 0.00 clock network delay (ideal) 0.00 0.00 v input external delay 0.00 0.00 v in1 (in) 0.06 0.06 v buf1/Z (BUF_X1) 0.01 0.07 ^ inv1/ZN (INV_X1) 0.02 0.09 ^ buf2/Z (BUF_X2) 0.03 0.12 ^ or1/ZN (OR2_X1) 0.02 0.13 ^ buf_out/Z (BUF_X1) 0.00 0.13 ^ out3 (out) 0.13 data arrival time 10.00 10.00 clock clk (rise edge) 0.00 10.00 clock network delay (ideal) 0.00 10.00 clock reconvergence pessimism 0.00 10.00 output external delay 10.00 data required time --------------------------------------------------------- 10.00 data required time -0.13 data arrival time --------------------------------------------------------- 9.87 slack (MET) dmp_two_pole out3 load=0.001: done Startpoint: in1 (input port clocked by clk) Endpoint: out3 (output port clocked by clk) Path Group: clk Path Type: max Delay Time Description --------------------------------------------------------- 0.00 0.00 clock clk (rise edge) 0.00 0.00 clock network delay (ideal) 0.00 0.00 v input external delay 0.00 0.00 v in1 (in) 0.06 0.06 v buf1/Z (BUF_X1) 0.01 0.07 ^ inv1/ZN (INV_X1) 0.02 0.09 ^ buf2/Z (BUF_X2) 0.03 0.12 ^ or1/ZN (OR2_X1) 0.02 0.13 ^ buf_out/Z (BUF_X1) 0.00 0.13 ^ out3 (out) 0.13 data arrival time 10.00 10.00 clock clk (rise edge) 0.00 10.00 clock network delay (ideal) 0.00 10.00 clock reconvergence pessimism 0.00 10.00 output external delay 10.00 data required time --------------------------------------------------------- 10.00 data required time -0.13 data arrival time --------------------------------------------------------- 9.87 slack (MET) dmp_two_pole out3 load=0.01: done Startpoint: in1 (input port clocked by clk) Endpoint: out3 (output port clocked by clk) Path Group: clk Path Type: max Delay Time Description --------------------------------------------------------- 0.00 0.00 clock clk (rise edge) 0.00 0.00 clock network delay (ideal) 0.00 0.00 v input external delay 0.00 0.00 v in1 (in) 0.06 0.06 v buf1/Z (BUF_X1) 0.01 0.07 ^ inv1/ZN (INV_X1) 0.02 0.09 ^ buf2/Z (BUF_X2) 0.03 0.12 ^ or1/ZN (OR2_X1) 0.02 0.14 ^ buf_out/Z (BUF_X1) 0.00 0.14 ^ out3 (out) 0.14 data arrival time 10.00 10.00 clock clk (rise edge) 0.00 10.00 clock network delay (ideal) 0.00 10.00 clock reconvergence pessimism 0.00 10.00 output external delay 10.00 data required time --------------------------------------------------------- 10.00 data required time -0.14 data arrival time --------------------------------------------------------- 9.86 slack (MET) dmp_two_pole out3 load=0.05: done Startpoint: in1 (input port clocked by clk) Endpoint: out3 (output port clocked by clk) Path Group: clk Path Type: max Delay Time Description --------------------------------------------------------- 0.00 0.00 clock clk (rise edge) 0.00 0.00 clock network delay (ideal) 0.00 0.00 v input external delay 0.00 0.00 v in1 (in) 0.06 0.06 v buf1/Z (BUF_X1) 0.01 0.07 ^ inv1/ZN (INV_X1) 0.02 0.09 ^ buf2/Z (BUF_X2) 0.03 0.12 ^ or1/ZN (OR2_X1) 0.02 0.14 ^ buf_out/Z (BUF_X1) 0.00 0.14 ^ out3 (out) 0.14 data arrival time 10.00 10.00 clock clk (rise edge) 0.00 10.00 clock network delay (ideal) 0.00 10.00 clock reconvergence pessimism 0.00 10.00 output external delay 10.00 data required time --------------------------------------------------------- 10.00 data required time -0.14 data arrival time --------------------------------------------------------- 9.86 slack (MET) dmp_two_pole out3 load=0.1: done Library: NangateOpenCellLibrary Cell: BUF_X1 Arc sense: positive_unate Arc type: combinational A ^ -> Z ^ P = 1.00 V = 1.10 T = 25.00 ------- input_net_transition = 0.10 | total_output_net_capacitance = 1.70 | 0.37 1.90 v -------------------- 0.08 | 0.03 0.03 0.13 | 0.03 0.04 Table value = 0.03 PVT scale factor = 1.00 Delay = 0.03 ------- input_net_transition = 0.10 | total_output_net_capacitance = 1.70 | 0.37 1.90 v -------------------- 0.08 | 0.01 0.01 0.13 | 0.01 0.01 Table value = 0.01 PVT scale factor = 1.00 Slew = 0.01 Driver waveform slew = 0.01 ............................................. A v -> Z v P = 1.00 V = 1.10 T = 25.00 ------- input_net_transition = 0.10 | total_output_net_capacitance = 1.55 | 0.37 1.90 v -------------------- 0.08 | 0.05 0.05 0.13 | 0.06 0.07 Table value = 0.06 PVT scale factor = 1.00 Delay = 0.06 ------- input_net_transition = 0.10 | total_output_net_capacitance = 1.55 | 0.37 1.90 v -------------------- 0.08 | 0.01 0.01 0.13 | 0.01 0.01 Table value = 0.01 PVT scale factor = 1.00 Slew = 0.01 Driver waveform slew = 0.01 ............................................. dmp_two_pole buf1: Library: NangateOpenCellLibrary Cell: INV_X1 Arc sense: negative_unate Arc type: combinational A ^ -> ZN v P = 1.00 V = 1.10 T = 25.00 ------- input_net_transition = 0.01 | total_output_net_capacitance = 1.59 | 0.37 1.90 v -------------------- 0.00 | 0.00 0.01 0.02 | 0.01 0.01 Table value = 0.01 PVT scale factor = 1.00 Delay = 0.01 ------- input_net_transition = 0.01 | total_output_net_capacitance = 1.59 | 0.37 1.90 v -------------------- 0.00 | 0.00 0.00 0.02 | 0.00 0.01 Table value = 0.00 PVT scale factor = 1.00 Slew = 0.00 Driver waveform slew = 0.00 ............................................. A v -> ZN ^ P = 1.00 V = 1.10 T = 25.00 ------- input_net_transition = 0.01 | total_output_net_capacitance = 1.78 | 0.37 1.90 v -------------------- 0.00 | 0.01 0.01 0.02 | 0.01 0.02 Table value = 0.01 PVT scale factor = 1.00 Delay = 0.01 ------- input_net_transition = 0.01 | total_output_net_capacitance = 1.78 | 0.37 1.90 v -------------------- 0.00 | 0.00 0.01 0.02 | 0.01 0.01 Table value = 0.01 PVT scale factor = 1.00 Slew = 0.01 Driver waveform slew = 0.01 ............................................. dmp_two_pole inv1: Library: NangateOpenCellLibrary Cell: AND2_X1 Arc sense: positive_unate Arc type: combinational A1 ^ -> ZN ^ P = 1.00 V = 1.10 T = 25.00 ------- input_net_transition = 0.00 | total_output_net_capacitance = 0.94 | 0.37 1.89 v -------------------- 0.00 | 0.02 0.03 0.00 | 0.02 0.03 Table value = 0.03 PVT scale factor = 1.00 Delay = 0.03 ------- input_net_transition = 0.00 | total_output_net_capacitance = 0.94 | 0.37 1.89 v -------------------- 0.00 | 0.01 0.01 0.00 | 0.01 0.01 Table value = 0.01 PVT scale factor = 1.00 Slew = 0.01 Driver waveform slew = 0.01 ............................................. A1 v -> ZN v P = 1.00 V = 1.10 T = 25.00 ------- input_net_transition = 0.00 | total_output_net_capacitance = 0.90 | 0.37 1.89 v -------------------- 0.00 | 0.02 0.03 0.00 | 0.02 0.03 Table value = 0.02 PVT scale factor = 1.00 Delay = 0.02 ------- input_net_transition = 0.00 | total_output_net_capacitance = 0.90 | 0.37 1.89 v -------------------- 0.00 | 0.00 0.01 0.00 | 0.00 0.01 Table value = 0.01 PVT scale factor = 1.00 Slew = 0.01 Driver waveform slew = 0.01 ............................................. dmp_two_pole and1 A1: Library: NangateOpenCellLibrary Cell: OR2_X1 Arc sense: positive_unate Arc type: combinational A1 ^ -> ZN ^ P = 1.00 V = 1.10 T = 25.00 ------- input_net_transition = 0.00 | total_output_net_capacitance = 4.29 | 3.79 7.57 v -------------------- 0.00 | 0.02 0.03 0.00 | 0.03 0.04 Table value = 0.03 PVT scale factor = 1.00 Delay = 0.03 ------- input_net_transition = 0.00 | total_output_net_capacitance = 4.29 | 3.79 7.57 v -------------------- 0.00 | 0.01 0.02 0.00 | 0.01 0.02 Table value = 0.01 PVT scale factor = 1.00 Slew = 0.01 Driver waveform slew = 0.01 ............................................. A1 v -> ZN v P = 1.00 V = 1.10 T = 25.00 ------- input_net_transition = 0.00 | total_output_net_capacitance = 3.82 | 3.79 7.57 v -------------------- 0.00 | 0.05 0.05 0.00 | 0.05 0.06 Table value = 0.05 PVT scale factor = 1.00 Delay = 0.05 ------- input_net_transition = 0.00 | total_output_net_capacitance = 3.82 | 3.79 7.57 v -------------------- 0.00 | 0.01 0.02 0.00 | 0.01 0.02 Table value = 0.01 PVT scale factor = 1.00 Slew = 0.01 Driver waveform slew = 0.01 ............................................. dmp_two_pole or1 A1: Library: NangateOpenCellLibrary Cell: NAND2_X1 Arc sense: negative_unate Arc type: combinational A1 ^ -> ZN v P = 1.00 V = 1.10 T = 25.00 ------- input_net_transition = 0.01 | total_output_net_capacitance = 1.06 | 0.37 1.85 v -------------------- 0.00 | 0.01 0.01 0.02 | 0.01 0.02 Table value = 0.01 PVT scale factor = 1.00 Delay = 0.01 ------- input_net_transition = 0.01 | total_output_net_capacitance = 1.06 | 0.37 1.85 v -------------------- 0.00 | 0.00 0.01 0.02 | 0.01 0.01 Table value = 0.01 PVT scale factor = 1.00 Slew = 0.01 Driver waveform slew = 0.01 ............................................. A1 v -> ZN ^ P = 1.00 V = 1.10 T = 25.00 ------- input_net_transition = 0.01 | total_output_net_capacitance = 1.14 | 0.37 1.85 v -------------------- 0.00 | 0.01 0.01 0.02 | 0.01 0.02 Table value = 0.01 PVT scale factor = 1.00 Delay = 0.01 ------- input_net_transition = 0.01 | total_output_net_capacitance = 1.14 | 0.37 1.85 v -------------------- 0.00 | 0.00 0.01 0.02 | 0.01 0.01 Table value = 0.01 PVT scale factor = 1.00 Slew = 0.01 Driver waveform slew = 0.01 ............................................. dmp_two_pole nand1 A1: Library: NangateOpenCellLibrary Cell: NOR2_X1 Arc sense: negative_unate Arc type: combinational A1 ^ -> ZN v P = 1.00 V = 1.10 T = 25.00 ------- input_net_transition = 0.01 | total_output_net_capacitance = 1.06 | 0.83 1.67 v -------------------- 0.00 | 0.01 0.01 0.02 | 0.01 0.01 Table value = 0.01 PVT scale factor = 1.00 Delay = 0.01 ------- input_net_transition = 0.01 | total_output_net_capacitance = 1.06 | 0.83 1.67 v -------------------- 0.00 | 0.00 0.00 0.02 | 0.01 0.01 Table value = 0.00 PVT scale factor = 1.00 Slew = 0.00 Driver waveform slew = 0.00 ............................................. A1 v -> ZN ^ P = 1.00 V = 1.10 T = 25.00 ------- input_net_transition = 0.01 | total_output_net_capacitance = 1.14 | 0.83 1.67 v -------------------- 0.00 | 0.02 0.02 0.02 | 0.02 0.03 Table value = 0.02 PVT scale factor = 1.00 Delay = 0.02 ------- input_net_transition = 0.01 | total_output_net_capacitance = 1.14 | 0.83 1.67 v -------------------- 0.00 | 0.01 0.02 0.02 | 0.01 0.02 Table value = 0.01 PVT scale factor = 1.00 Slew = 0.01 Driver waveform slew = 0.01 ............................................. dmp_two_pole nor1 A1: Library: NangateOpenCellLibrary Cell: DFF_X1 Arc sense: non_unate Arc type: Reg Clk to Q CK ^ -> Q ^ P = 1.00 V = 1.10 T = 25.00 ------- input_net_transition = 0.00 | total_output_net_capacitance = 0.00 | 0.37 1.90 v -------------------- 0.00 | 0.08 0.09 0.00 | 0.08 0.09 Table value = 0.08 PVT scale factor = 1.00 Delay = 0.08 ------- input_net_transition = 0.00 | total_output_net_capacitance = 0.00 | 0.37 1.90 v -------------------- 0.00 | 0.01 0.01 0.00 | 0.01 0.01 Table value = 0.01 PVT scale factor = 1.00 Slew = 0.01 Driver waveform slew = 0.01 ............................................. CK ^ -> Q v P = 1.00 V = 1.10 T = 25.00 ------- input_net_transition = 0.00 | total_output_net_capacitance = 0.00 | 0.37 1.90 v -------------------- 0.00 | 0.08 0.08 0.00 | 0.08 0.08 Table value = 0.08 PVT scale factor = 1.00 Delay = 0.08 ------- input_net_transition = 0.00 | total_output_net_capacitance = 0.00 | 0.37 1.90 v -------------------- 0.00 | 0.01 0.01 0.00 | 0.01 0.01 Table value = 0.00 PVT scale factor = 1.00 Slew = 0.00 Driver waveform slew = 0.00 ............................................. dmp_two_pole reg1 CK->Q: Library: NangateOpenCellLibrary Cell: DFF_X1 Arc type: setup CK ^ -> D ^ P = 1.00 V = 1.10 T = 25.00 ------- constrained_pin_transition = 0.01 (ideal clock) | related_pin_transition = 0.00 | 0.00 0.04 v -------------------- 0.00 | 0.03 0.02 0.04 | 0.04 0.03 Table value = 0.03 PVT scale factor = 1.00 Check = 0.03 ............................................. CK ^ -> D v P = 1.00 V = 1.10 T = 25.00 ------- constrained_pin_transition = 0.01 (ideal clock) | related_pin_transition = 0.00 | 0.00 0.04 v -------------------- 0.00 | 0.04 0.02 0.04 | 0.05 0.04 Table value = 0.04 PVT scale factor = 1.00 Check = 0.04 ............................................. dmp_two_pole reg1 setup: Library: NangateOpenCellLibrary Cell: DFF_X1 Arc type: hold CK ^ -> D ^ P = 1.00 V = 1.10 T = 25.00 ------- constrained_pin_transition = 0.01 (ideal clock) | related_pin_transition = 0.00 | 0.00 0.04 v -------------------- 0.00 | 0.00 0.02 0.04 | 0.02 0.03 Table value = 0.01 PVT scale factor = 1.00 Check = 0.01 ............................................. CK ^ -> D v P = 1.00 V = 1.10 T = 25.00 ------- constrained_pin_transition = 0.01 (ideal clock) | related_pin_transition = 0.00 | 0.00 0.04 v -------------------- 0.00 | 0.00 0.01 0.04 | 0.00 0.01 Table value = 0.00 PVT scale factor = 1.00 Check = 0.00 ............................................. dmp_two_pole reg1 hold: --- varying input transitions --- No paths found. slew=0.001: done No paths found. slew=0.01: done No paths found. slew=0.05: done No paths found. slew=0.1: done No paths found. slew=0.2: done No paths found. slew=0.5: done No paths found. slew=1.0: done --- ccs_ceff on larger design --- set_delay_calculator ccs_ceff: Startpoint: in2 (input port clocked by clk) Endpoint: reg2 (rising edge-triggered flip-flop clocked by clk) Path Group: clk Path Type: max Delay Time Description --------------------------------------------------------- 0.00 0.00 clock clk (rise edge) 0.00 0.00 clock network delay (ideal) 0.00 0.00 v input external delay 0.00 0.00 v in2 (in) 0.05 0.05 v buf3/Z (BUF_X4) 0.03 0.08 v and1/ZN (AND2_X1) 0.05 0.13 v or1/ZN (OR2_X1) 0.02 0.15 ^ nor1/ZN (NOR2_X1) 0.00 0.15 ^ reg2/D (DFF_X1) 0.15 data arrival time 10.00 10.00 clock clk (rise edge) 0.00 10.00 clock network delay (ideal) 0.00 10.00 clock reconvergence pessimism 10.00 ^ reg2/CK (DFF_X1) -0.04 9.96 library setup time 9.96 data required time --------------------------------------------------------- 9.96 data required time -0.15 data arrival time --------------------------------------------------------- 9.81 slack (MET) PASS: ccs_ceff on larger design No paths found. ccs_ceff load=0.001: done No paths found. ccs_ceff load=0.01: done No paths found. ccs_ceff load=0.1: done Library: NangateOpenCellLibrary Cell: NAND2_X1 Arc sense: negative_unate Arc type: combinational A1 ^ -> ZN v P = 1.00 V = 1.10 T = 25.00 ------- input_net_transition = 0.01 | total_output_net_capacitance = 1.06 | 0.37 1.85 v -------------------- 0.00 | 0.01 0.01 0.02 | 0.01 0.02 Table value = 0.01 PVT scale factor = 1.00 Delay = 0.01 ------- input_net_transition = 0.01 | total_output_net_capacitance = 1.06 | 0.37 1.85 v -------------------- 0.00 | 0.00 0.01 0.02 | 0.01 0.01 Table value = 0.01 PVT scale factor = 1.00 Slew = 0.01 Driver waveform slew = 0.01 ............................................. A1 v -> ZN ^ P = 1.00 V = 1.10 T = 25.00 ------- input_net_transition = 0.01 | total_output_net_capacitance = 1.14 | 0.37 1.85 v -------------------- 0.00 | 0.01 0.01 0.02 | 0.01 0.02 Table value = 0.01 PVT scale factor = 1.00 Delay = 0.01 ------- input_net_transition = 0.01 | total_output_net_capacitance = 1.14 | 0.37 1.85 v -------------------- 0.00 | 0.00 0.01 0.02 | 0.01 0.01 Table value = 0.01 PVT scale factor = 1.00 Slew = 0.01 Driver waveform slew = 0.01 ............................................. ccs_ceff nand1 A1: Library: NangateOpenCellLibrary Cell: NOR2_X1 Arc sense: negative_unate Arc type: combinational A1 ^ -> ZN v P = 1.00 V = 1.10 T = 25.00 ------- input_net_transition = 0.01 | total_output_net_capacitance = 1.06 | 0.83 1.67 v -------------------- 0.00 | 0.01 0.01 0.02 | 0.01 0.01 Table value = 0.01 PVT scale factor = 1.00 Delay = 0.01 ------- input_net_transition = 0.01 | total_output_net_capacitance = 1.06 | 0.83 1.67 v -------------------- 0.00 | 0.00 0.00 0.02 | 0.01 0.01 Table value = 0.00 PVT scale factor = 1.00 Slew = 0.00 Driver waveform slew = 0.00 ............................................. A1 v -> ZN ^ P = 1.00 V = 1.10 T = 25.00 ------- input_net_transition = 0.01 | total_output_net_capacitance = 1.14 | 0.83 1.67 v -------------------- 0.00 | 0.02 0.02 0.02 | 0.02 0.03 Table value = 0.02 PVT scale factor = 1.00 Delay = 0.02 ------- input_net_transition = 0.01 | total_output_net_capacitance = 1.14 | 0.83 1.67 v -------------------- 0.00 | 0.01 0.02 0.02 | 0.01 0.02 Table value = 0.01 PVT scale factor = 1.00 Slew = 0.01 Driver waveform slew = 0.01 ............................................. ccs_ceff nor1 A1: Library: NangateOpenCellLibrary Cell: BUF_X2 Arc sense: positive_unate Arc type: combinational A ^ -> Z ^ P = 1.00 V = 1.10 T = 25.00 ------- input_net_transition = 0.01 | total_output_net_capacitance = 0.95 | 0.37 3.79 v -------------------- 0.00 | 0.02 0.02 0.02 | 0.02 0.02 Table value = 0.02 PVT scale factor = 1.00 Delay = 0.02 ------- input_net_transition = 0.01 | total_output_net_capacitance = 0.95 | 0.37 3.79 v -------------------- 0.00 | 0.00 0.01 0.02 | 0.00 0.01 Table value = 0.00 PVT scale factor = 1.00 Slew = 0.00 Driver waveform slew = 0.00 ............................................. A v -> Z v P = 1.00 V = 1.10 T = 25.00 ------- input_net_transition = 0.00 | total_output_net_capacitance = 0.79 | 0.37 3.79 v -------------------- 0.00 | 0.02 0.02 0.00 | 0.02 0.02 Table value = 0.02 PVT scale factor = 1.00 Delay = 0.02 ------- input_net_transition = 0.00 | total_output_net_capacitance = 0.79 | 0.37 3.79 v -------------------- 0.00 | 0.00 0.01 0.00 | 0.00 0.01 Table value = 0.00 PVT scale factor = 1.00 Slew = 0.00 Driver waveform slew = 0.00 ............................................. ccs_ceff buf2 A->Z: Library: NangateOpenCellLibrary Cell: BUF_X4 Arc sense: positive_unate Arc type: combinational A ^ -> Z ^ P = 1.00 V = 1.10 T = 25.00 ------- input_net_transition = 0.10 | total_output_net_capacitance = 0.92 | 0.37 7.57 v -------------------- 0.08 | 0.03 0.03 0.13 | 0.03 0.03 Table value = 0.03 PVT scale factor = 1.00 Delay = 0.03 ------- input_net_transition = 0.10 | total_output_net_capacitance = 0.92 | 0.37 7.57 v -------------------- 0.08 | 0.01 0.01 0.13 | 0.01 0.01 Table value = 0.01 PVT scale factor = 1.00 Slew = 0.01 Driver waveform slew = 0.01 ............................................. A v -> Z v P = 1.00 V = 1.10 T = 25.00 ------- input_net_transition = 0.10 | total_output_net_capacitance = 0.87 | 0.37 7.57 v -------------------- 0.08 | 0.05 0.05 0.13 | 0.06 0.06 Table value = 0.05 PVT scale factor = 1.00 Delay = 0.05 ------- input_net_transition = 0.10 | total_output_net_capacitance = 0.87 | 0.37 7.57 v -------------------- 0.08 | 0.01 0.01 0.13 | 0.01 0.01 Table value = 0.01 PVT scale factor = 1.00 Slew = 0.01 Driver waveform slew = 0.01 ............................................. ccs_ceff buf3 A->Z: --- rapid calculator switching --- Startpoint: in1 (input port clocked by clk) Endpoint: out3 (output port clocked by clk) Path Group: clk Path Type: max Delay Time Description --------------------------------------------------------- 0.00 0.00 clock clk (rise edge) 0.00 0.00 clock network delay (ideal) 0.00 0.00 v input external delay 0.00 0.00 v in1 (in) 1.00 1.00 v buf1/Z (BUF_X1) 1.00 2.00 ^ inv1/ZN (INV_X1) 1.00 3.00 ^ buf2/Z (BUF_X2) 1.00 4.00 ^ or1/ZN (OR2_X1) 1.00 5.00 ^ buf_out/Z (BUF_X1) 0.00 5.00 ^ out3 (out) 5.00 data arrival time 10.00 10.00 clock clk (rise edge) 0.00 10.00 clock network delay (ideal) 0.00 10.00 clock reconvergence pessimism 0.00 10.00 output external delay 10.00 data required time --------------------------------------------------------- 10.00 data required time -5.00 data arrival time --------------------------------------------------------- 5.00 slack (MET) Startpoint: in1 (input port clocked by clk) Endpoint: out3 (output port clocked by clk) Path Group: clk Path Type: max Delay Time Description --------------------------------------------------------- 0.00 0.00 clock clk (rise edge) 0.00 0.00 clock network delay (ideal) 0.00 0.00 v input external delay 0.00 0.00 v in1 (in) 0.06 0.06 v buf1/Z (BUF_X1) 0.01 0.07 ^ inv1/ZN (INV_X1) 0.02 0.09 ^ buf2/Z (BUF_X2) 0.03 0.12 ^ or1/ZN (OR2_X1) 0.02 0.13 ^ buf_out/Z (BUF_X1) 0.00 0.13 ^ out3 (out) 0.13 data arrival time 10.00 10.00 clock clk (rise edge) 0.00 10.00 clock network delay (ideal) 0.00 10.00 clock reconvergence pessimism 0.00 10.00 output external delay 10.00 data required time --------------------------------------------------------- 10.00 data required time -0.13 data arrival time --------------------------------------------------------- 9.87 slack (MET) Startpoint: in1 (input port clocked by clk) Endpoint: out3 (output port clocked by clk) Path Group: clk Path Type: max Delay Time Description --------------------------------------------------------- 0.00 0.00 clock clk (rise edge) 0.00 0.00 clock network delay (ideal) 0.00 0.00 v input external delay 0.00 0.00 v in1 (in) 0.06 0.06 v buf1/Z (BUF_X1) 0.01 0.07 ^ inv1/ZN (INV_X1) 0.02 0.09 ^ buf2/Z (BUF_X2) 0.03 0.12 ^ or1/ZN (OR2_X1) 0.02 0.13 ^ buf_out/Z (BUF_X1) 0.00 0.13 ^ out3 (out) 0.13 data arrival time 10.00 10.00 clock clk (rise edge) 0.00 10.00 clock network delay (ideal) 0.00 10.00 clock reconvergence pessimism 0.00 10.00 output external delay 10.00 data required time --------------------------------------------------------- 10.00 data required time -0.13 data arrival time --------------------------------------------------------- 9.87 slack (MET) Startpoint: in1 (input port clocked by clk) Endpoint: out3 (output port clocked by clk) Path Group: clk Path Type: max Delay Time Description --------------------------------------------------------- 0.00 0.00 clock clk (rise edge) 0.00 0.00 clock network delay (ideal) 0.00 0.00 v input external delay 0.00 0.00 v in1 (in) 0.06 0.06 v buf1/Z (BUF_X1) 0.01 0.07 ^ inv1/ZN (INV_X1) 0.02 0.09 ^ buf2/Z (BUF_X2) 0.03 0.12 ^ or1/ZN (OR2_X1) 0.02 0.13 ^ buf_out/Z (BUF_X1) 0.00 0.13 ^ out3 (out) 0.13 data arrival time 10.00 10.00 clock clk (rise edge) 0.00 10.00 clock network delay (ideal) 0.00 10.00 clock reconvergence pessimism 0.00 10.00 output external delay 10.00 data required time --------------------------------------------------------- 10.00 data required time -0.13 data arrival time --------------------------------------------------------- 9.87 slack (MET) Startpoint: in1 (input port clocked by clk) Endpoint: out3 (output port clocked by clk) Path Group: clk Path Type: max Delay Time Description --------------------------------------------------------- 0.00 0.00 clock clk (rise edge) 0.00 0.00 clock network delay (ideal) 0.00 0.00 v input external delay 0.00 0.00 v in1 (in) 0.06 0.06 v buf1/Z (BUF_X1) 0.01 0.07 ^ inv1/ZN (INV_X1) 0.02 0.09 ^ buf2/Z (BUF_X2) 0.03 0.12 ^ or1/ZN (OR2_X1) 0.02 0.13 ^ buf_out/Z (BUF_X1) 0.00 0.13 ^ out3 (out) 0.13 data arrival time 10.00 10.00 clock clk (rise edge) 0.00 10.00 clock network delay (ideal) 0.00 10.00 clock reconvergence pessimism 0.00 10.00 output external delay 10.00 data required time --------------------------------------------------------- 10.00 data required time -0.13 data arrival time --------------------------------------------------------- 9.87 slack (MET) Startpoint: in1 (input port clocked by clk) Endpoint: out3 (output port clocked by clk) Path Group: clk Path Type: max Delay Time Description --------------------------------------------------------- 0.00 0.00 clock clk (rise edge) 0.00 0.00 clock network delay (ideal) 0.00 0.00 v input external delay 0.00 0.00 v in1 (in) 0.06 0.06 v buf1/Z (BUF_X1) 0.01 0.07 ^ inv1/ZN (INV_X1) 0.02 0.09 ^ buf2/Z (BUF_X2) 0.03 0.12 ^ or1/ZN (OR2_X1) 0.02 0.13 ^ buf_out/Z (BUF_X1) 0.00 0.13 ^ out3 (out) 0.13 data arrival time 10.00 10.00 clock clk (rise edge) 0.00 10.00 clock network delay (ideal) 0.00 10.00 clock reconvergence pessimism 0.00 10.00 output external delay 10.00 data required time --------------------------------------------------------- 10.00 data required time -0.13 data arrival time --------------------------------------------------------- 9.87 slack (MET) PASS: rapid switching --- report_checks formatting --- Warning: dcalc_dmp_ceff.tcl line 1, unknown field nets. Startpoint: in2 (input port clocked by clk) Endpoint: reg2 (rising edge-triggered flip-flop clocked by clk) Path Group: clk Path Type: max Fanout Cap Slew Delay Time Description ----------------------------------------------------------------------------- 0.00 0.00 0.00 clock clk (rise edge) 0.00 0.00 clock network delay (ideal) 0.00 0.00 v input external delay 1 3.00 0.10 0.00 0.00 v in2 (in) 0.10 0.00 0.00 v buf3/A (BUF_X4) 1 0.87 0.01 0.05 0.05 v buf3/Z (BUF_X4) 0.01 0.00 0.05 v and1/A1 (AND2_X1) 1 0.90 0.01 0.03 0.08 v and1/ZN (AND2_X1) 0.01 0.00 0.08 v or1/A2 (OR2_X1) 3 3.82 0.01 0.05 0.13 v or1/ZN (OR2_X1) 0.01 0.00 0.13 v nor1/A1 (NOR2_X1) 1 1.14 0.02 0.02 0.15 ^ nor1/ZN (NOR2_X1) 0.02 0.00 0.15 ^ reg2/D (DFF_X1) 0.15 data arrival time 0.00 10.00 10.00 clock clk (rise edge) 0.00 10.00 clock network delay (ideal) 0.00 10.00 clock reconvergence pessimism 10.00 ^ reg2/CK (DFF_X1) -0.04 9.96 library setup time 9.96 data required time ----------------------------------------------------------------------------- 9.96 data required time -0.15 data arrival time ----------------------------------------------------------------------------- 9.81 slack (MET) PASS: all fields Startpoint: in2 (input port clocked by clk) Endpoint: reg2 (rising edge-triggered flip-flop clocked by clk) Path Group: clk Path Type: max Delay Time Description --------------------------------------------------------- 0.00 0.00 clock clk (rise edge) 0.00 0.00 clock network delay (ideal) 0.00 0.00 v input external delay 0.00 0.00 v in2 (in) 0.05 0.05 v buf3/Z (BUF_X4) 0.03 0.08 v and1/ZN (AND2_X1) 0.05 0.13 v or1/ZN (OR2_X1) 0.02 0.15 ^ nor1/ZN (NOR2_X1) 0.00 0.15 ^ reg2/D (DFF_X1) 0.15 data arrival time 10.00 10.00 clock clk (rise edge) 0.00 10.00 clock network delay (ideal) 0.00 10.00 clock reconvergence pessimism 10.00 ^ reg2/CK (DFF_X1) -0.04 9.96 library setup time 9.96 data required time --------------------------------------------------------- 9.96 data required time -0.15 data arrival time --------------------------------------------------------- 9.81 slack (MET) PASS: full_clock Startpoint: in2 (input port clocked by clk) Endpoint: reg2 (rising edge-triggered flip-flop clocked by clk) Path Group: clk Path Type: max Delay Time Description --------------------------------------------------------- 0.00 0.00 clock clk (rise edge) 0.00 0.00 clock network delay (ideal) 0.00 0.00 v input external delay 0.00 0.00 v in2 (in) 0.05 0.05 v buf3/Z (BUF_X4) 0.03 0.08 v and1/ZN (AND2_X1) 0.05 0.13 v or1/ZN (OR2_X1) 0.02 0.15 ^ nor1/ZN (NOR2_X1) 0.00 0.15 ^ reg2/D (DFF_X1) 0.15 data arrival time 10.00 10.00 clock clk (rise edge) 0.00 10.00 clock network delay (ideal) 0.00 10.00 clock reconvergence pessimism 10.00 ^ reg2/CK (DFF_X1) -0.04 9.96 library setup time 9.96 data required time --------------------------------------------------------- 9.96 data required time -0.15 data arrival time --------------------------------------------------------- 9.81 slack (MET) PASS: full_clock_expanded ALL PASSED