--- Fast corner timing --- Startpoint: reg1 (rising edge-triggered flip-flop clocked by clk) Endpoint: out1 (output port clocked by clk) Path Group: clk Path Type: max Corner: fast Delay Time Description --------------------------------------------------------- 0.00 0.00 clock clk (rise edge) 0.00 0.00 clock network delay (ideal) 0.00 0.00 ^ reg1/CK (DFF_X1) 0.05 0.05 v reg1/Q (DFF_X1) 0.00 0.05 v out1 (out) 0.05 data arrival time 10.00 10.00 clock clk (rise edge) 0.00 10.00 clock network delay (ideal) 0.00 10.00 clock reconvergence pessimism 0.00 10.00 output external delay 10.00 data required time --------------------------------------------------------- 10.00 data required time -0.05 data arrival time --------------------------------------------------------- 9.95 slack (MET) PASS: report_checks fast corner Startpoint: in1 (input port clocked by clk) Endpoint: reg1 (rising edge-triggered flip-flop clocked by clk) Path Group: clk Path Type: min Corner: fast Delay Time Description --------------------------------------------------------- 0.00 0.00 clock clk (rise edge) 0.00 0.00 clock network delay (ideal) 0.00 0.00 ^ input external delay 0.00 0.00 ^ in1 (in) 0.01 0.01 ^ buf1/Z (BUF_X1) 0.00 0.02 v inv1/ZN (INV_X1) 0.00 0.02 v reg1/D (DFF_X1) 0.02 data arrival time 0.00 0.00 clock clk (rise edge) 0.00 0.00 clock network delay (ideal) 0.00 0.00 clock reconvergence pessimism 0.00 ^ reg1/CK (DFF_X1) 0.00 0.00 library hold time 0.00 data required time --------------------------------------------------------- 0.00 data required time -0.02 data arrival time --------------------------------------------------------- 0.01 slack (MET) PASS: report_checks fast corner min path Startpoint: reg1 (rising edge-triggered flip-flop clocked by clk) Endpoint: out1 (output port clocked by clk) Path Group: clk Path Type: max Corner: fast Delay Time Description --------------------------------------------------------- 0.00 0.00 clock clk (rise edge) 0.00 0.00 clock network delay (ideal) 0.00 0.00 ^ reg1/CK (DFF_X1) 0.05 0.05 v reg1/Q (DFF_X1) 0.00 0.05 v out1 (out) 0.05 data arrival time 10.00 10.00 clock clk (rise edge) 0.00 10.00 clock network delay (ideal) 0.00 10.00 clock reconvergence pessimism 0.00 10.00 output external delay 10.00 data required time --------------------------------------------------------- 10.00 data required time -0.05 data arrival time --------------------------------------------------------- 9.95 slack (MET) PASS: report_checks fast corner max path --- Slow corner timing --- Startpoint: reg1 (rising edge-triggered flip-flop clocked by clk) Endpoint: out1 (output port clocked by clk) Path Group: clk Path Type: max Corner: slow Delay Time Description --------------------------------------------------------- 0.00 0.00 clock clk (rise edge) 0.00 0.00 clock network delay (ideal) 0.00 0.00 ^ reg1/CK (DFF_X1) 0.29 0.29 ^ reg1/Q (DFF_X1) 0.00 0.29 ^ out1 (out) 0.29 data arrival time 10.00 10.00 clock clk (rise edge) 0.00 10.00 clock network delay (ideal) 0.00 10.00 clock reconvergence pessimism 0.00 10.00 output external delay 10.00 data required time --------------------------------------------------------- 10.00 data required time -0.29 data arrival time --------------------------------------------------------- 9.71 slack (MET) PASS: report_checks slow corner Startpoint: in1 (input port clocked by clk) Endpoint: reg1 (rising edge-triggered flip-flop clocked by clk) Path Group: clk Path Type: min Corner: slow Delay Time Description --------------------------------------------------------- 0.00 0.00 clock clk (rise edge) 0.00 0.00 clock network delay (ideal) 0.00 0.00 ^ input external delay 0.00 0.00 ^ in1 (in) 0.05 0.05 ^ buf1/Z (BUF_X1) 0.02 0.07 v inv1/ZN (INV_X1) 0.00 0.07 v reg1/D (DFF_X1) 0.07 data arrival time 0.00 0.00 clock clk (rise edge) 0.00 0.00 clock network delay (ideal) 0.00 0.00 clock reconvergence pessimism 0.00 ^ reg1/CK (DFF_X1) 0.00 0.00 library hold time 0.00 data required time --------------------------------------------------------- 0.00 data required time -0.07 data arrival time --------------------------------------------------------- 0.07 slack (MET) PASS: report_checks slow corner min path Startpoint: reg1 (rising edge-triggered flip-flop clocked by clk) Endpoint: out1 (output port clocked by clk) Path Group: clk Path Type: max Corner: slow Delay Time Description --------------------------------------------------------- 0.00 0.00 clock clk (rise edge) 0.00 0.00 clock network delay (ideal) 0.00 0.00 ^ reg1/CK (DFF_X1) 0.29 0.29 ^ reg1/Q (DFF_X1) 0.00 0.29 ^ out1 (out) 0.29 data arrival time 10.00 10.00 clock clk (rise edge) 0.00 10.00 clock network delay (ideal) 0.00 10.00 clock reconvergence pessimism 0.00 10.00 output external delay 10.00 data required time --------------------------------------------------------- 10.00 data required time -0.29 data arrival time --------------------------------------------------------- 9.71 slack (MET) PASS: report_checks slow corner max path --- report_dcalc per corner --- Library: NangateOpenCellLibrary_fast Cell: BUF_X1 Arc sense: positive_unate Arc type: combinational A ^ -> Z ^ P = 1.00 V = 1.25 T = 0.00 ------- input_net_transition = 0.00 | total_output_net_capacitance = 1.72 | 0.37 1.90 v -------------------- 0.00 | 0.01 0.01 0.00 | 0.01 0.01 Table value = 0.01 PVT scale factor = 1.00 Delay = 0.01 ------- input_net_transition = 0.00 | total_output_net_capacitance = 1.72 | 0.37 1.90 v -------------------- 0.00 | 0.00 0.00 0.00 | 0.00 0.00 Table value = 0.00 PVT scale factor = 1.00 Slew = 0.00 Driver waveform slew = 0.00 ............................................. A v -> Z v P = 1.00 V = 1.25 T = 0.00 ------- input_net_transition = 0.00 | total_output_net_capacitance = 1.60 | 0.37 1.90 v -------------------- 0.00 | 0.01 0.01 0.00 | 0.01 0.01 Table value = 0.01 PVT scale factor = 1.00 Delay = 0.01 ------- input_net_transition = 0.00 | total_output_net_capacitance = 1.60 | 0.37 1.90 v -------------------- 0.00 | 0.00 0.00 0.00 | 0.00 0.00 Table value = 0.00 PVT scale factor = 1.00 Slew = 0.00 Driver waveform slew = 0.00 ............................................. PASS: report_dcalc fast corner buf1 Library: NangateOpenCellLibrary_fast Cell: BUF_X1 Arc sense: positive_unate Arc type: combinational A ^ -> Z ^ P = 1.00 V = 0.95 T = 125.00 ------- input_net_transition = 0.00 | total_output_net_capacitance = 1.64 | 0.37 1.90 v -------------------- 0.00 | 0.04 0.05 0.01 | 0.04 0.06 Table value = 0.05 PVT scale factor = 1.00 Delay = 0.05 ------- input_net_transition = 0.00 | total_output_net_capacitance = 1.64 | 0.37 1.90 v -------------------- 0.00 | 0.01 0.03 0.01 | 0.01 0.03 Table value = 0.02 PVT scale factor = 1.00 Slew = 0.02 Driver waveform slew = 0.02 ............................................. A v -> Z v P = 1.00 V = 0.95 T = 125.00 ------- input_net_transition = 0.00 | total_output_net_capacitance = 1.48 | 0.37 1.90 v -------------------- 0.00 | 0.07 0.08 0.01 | 0.08 0.08 Table value = 0.08 PVT scale factor = 1.00 Delay = 0.08 ------- input_net_transition = 0.00 | total_output_net_capacitance = 1.48 | 0.37 1.90 v -------------------- 0.00 | 0.01 0.02 0.01 | 0.01 0.02 Table value = 0.02 PVT scale factor = 1.00 Slew = 0.02 Driver waveform slew = 0.02 ............................................. PASS: report_dcalc slow corner buf1 Library: NangateOpenCellLibrary_fast Cell: INV_X1 Arc sense: negative_unate Arc type: combinational A ^ -> ZN v P = 1.00 V = 1.25 T = 0.00 ------- input_net_transition = 0.00 | total_output_net_capacitance = 1.10 | 0.37 1.90 v -------------------- 0.00 | 0.00 0.00 0.01 | 0.00 0.01 Table value = 0.00 PVT scale factor = 1.00 Delay = 0.00 ------- input_net_transition = 0.00 | total_output_net_capacitance = 1.10 | 0.37 1.90 v -------------------- 0.00 | 0.00 0.00 0.01 | 0.00 0.00 Table value = 0.00 PVT scale factor = 1.00 Slew = 0.00 Driver waveform slew = 0.00 ............................................. A v -> ZN ^ P = 1.00 V = 1.25 T = 0.00 ------- input_net_transition = 0.00 | total_output_net_capacitance = 1.16 | 0.37 1.90 v -------------------- 0.00 | 0.00 0.01 0.01 | 0.01 0.01 Table value = 0.01 PVT scale factor = 1.00 Delay = 0.01 ------- input_net_transition = 0.00 | total_output_net_capacitance = 1.16 | 0.37 1.90 v -------------------- 0.00 | 0.00 0.00 0.01 | 0.00 0.01 Table value = 0.00 PVT scale factor = 1.00 Slew = 0.00 Driver waveform slew = 0.00 ............................................. PASS: report_dcalc fast corner inv1 Library: NangateOpenCellLibrary_fast Cell: INV_X1 Arc sense: negative_unate Arc type: combinational A ^ -> ZN v P = 1.00 V = 0.95 T = 125.00 ------- input_net_transition = 0.02 | total_output_net_capacitance = 1.03 | 0.37 1.90 v -------------------- 0.01 | 0.01 0.02 0.04 | 0.02 0.03 Table value = 0.02 PVT scale factor = 1.00 Delay = 0.02 ------- input_net_transition = 0.02 | total_output_net_capacitance = 1.03 | 0.37 1.90 v -------------------- 0.01 | 0.00 0.01 0.04 | 0.01 0.01 Table value = 0.01 PVT scale factor = 1.00 Slew = 0.01 Driver waveform slew = 0.01 ............................................. A v -> ZN ^ P = 1.00 V = 0.95 T = 125.00 ------- input_net_transition = 0.02 | total_output_net_capacitance = 1.11 | 0.37 1.90 v -------------------- 0.01 | 0.02 0.04 0.04 | 0.04 0.06 Table value = 0.03 PVT scale factor = 1.00 Delay = 0.03 ------- input_net_transition = 0.02 | total_output_net_capacitance = 1.11 | 0.37 1.90 v -------------------- 0.01 | 0.01 0.02 0.04 | 0.02 0.03 Table value = 0.02 PVT scale factor = 1.00 Slew = 0.02 Driver waveform slew = 0.02 ............................................. PASS: report_dcalc slow corner inv1 Library: NangateOpenCellLibrary_fast Cell: DFF_X1 Arc sense: non_unate Arc type: Reg Clk to Q CK ^ -> Q ^ P = 1.00 V = 1.25 T = 0.00 ------- input_net_transition = 0.00 | total_output_net_capacitance = 0.00 | 0.37 1.90 v -------------------- 0.00 | 0.05 0.05 0.00 | 0.05 0.05 Table value = 0.05 PVT scale factor = 1.00 Delay = 0.05 ------- input_net_transition = 0.00 | total_output_net_capacitance = 0.00 | 0.37 1.90 v -------------------- 0.00 | 0.00 0.01 0.00 | 0.00 0.01 Table value = 0.00 PVT scale factor = 1.00 Slew = 0.00 Driver waveform slew = 0.00 ............................................. CK ^ -> Q v P = 1.00 V = 1.25 T = 0.00 ------- input_net_transition = 0.00 | total_output_net_capacitance = 0.00 | 0.37 1.90 v -------------------- 0.00 | 0.05 0.05 0.00 | 0.05 0.05 Table value = 0.05 PVT scale factor = 1.00 Delay = 0.05 ------- input_net_transition = 0.00 | total_output_net_capacitance = 0.00 | 0.37 1.90 v -------------------- 0.00 | 0.00 0.00 0.00 | 0.00 0.00 Table value = 0.00 PVT scale factor = 1.00 Slew = 0.00 Driver waveform slew = 0.00 ............................................. PASS: report_dcalc fast corner DFF CK->Q Library: NangateOpenCellLibrary_fast Cell: DFF_X1 Arc sense: non_unate Arc type: Reg Clk to Q CK ^ -> Q ^ P = 1.00 V = 0.95 T = 125.00 ------- input_net_transition = 0.00 | total_output_net_capacitance = 0.00 | 0.37 1.90 v -------------------- 0.00 | 0.29 0.30 0.01 | 0.30 0.31 Table value = 0.29 PVT scale factor = 1.00 Delay = 0.29 ------- input_net_transition = 0.00 | total_output_net_capacitance = 0.00 | 0.37 1.90 v -------------------- 0.00 | 0.02 0.03 0.01 | 0.02 0.03 Table value = 0.02 PVT scale factor = 1.00 Slew = 0.02 Driver waveform slew = 0.02 ............................................. CK ^ -> Q v P = 1.00 V = 0.95 T = 125.00 ------- input_net_transition = 0.00 | total_output_net_capacitance = 0.00 | 0.37 1.90 v -------------------- 0.00 | 0.23 0.24 0.01 | 0.24 0.25 Table value = 0.23 PVT scale factor = 1.00 Delay = 0.23 ------- input_net_transition = 0.00 | total_output_net_capacitance = 0.00 | 0.37 1.90 v -------------------- 0.00 | 0.02 0.02 0.01 | 0.02 0.02 Table value = 0.01 PVT scale factor = 1.00 Slew = 0.01 Driver waveform slew = 0.01 ............................................. PASS: report_dcalc slow corner DFF CK->Q Library: NangateOpenCellLibrary_fast Cell: DFF_X1 Arc type: hold CK ^ -> D ^ P = 1.00 V = 1.25 T = 0.00 ------- constrained_pin_transition = 0.00 (ideal clock) | related_pin_transition = 0.00 | 0.00 0.03 v -------------------- 0.00 | 0.00 0.01 0.03 | 0.01 0.01 Table value = 0.00 PVT scale factor = 1.00 Check = 0.00 ............................................. CK ^ -> D v P = 1.00 V = 1.25 T = 0.00 ------- constrained_pin_transition = 0.00 (ideal clock) | related_pin_transition = 0.00 | 0.00 0.03 v -------------------- 0.00 | 0.00 0.01 0.03 | 0.01 0.01 Table value = 0.00 PVT scale factor = 1.00 Check = 0.00 ............................................. PASS: report_dcalc fast corner DFF hold check Library: NangateOpenCellLibrary_fast Cell: DFF_X1 Arc type: setup CK ^ -> D ^ P = 1.00 V = 0.95 T = 125.00 ------- constrained_pin_transition = 0.02 (ideal clock) | related_pin_transition = 0.00 | 0.00 0.11 v -------------------- 0.00 | 0.06 0.04 0.11 | 0.11 0.08 Table value = 0.07 PVT scale factor = 1.00 Check = 0.07 ............................................. CK ^ -> D v P = 1.00 V = 0.95 T = 125.00 ------- constrained_pin_transition = 0.01 (ideal clock) | related_pin_transition = 0.00 | 0.00 0.11 v -------------------- 0.00 | 0.15 0.09 0.11 | 0.21 0.15 Table value = 0.15 PVT scale factor = 1.00 Check = 0.15 ............................................. PASS: report_dcalc slow corner DFF setup check --- report_checks with fields --- Startpoint: reg1 (rising edge-triggered flip-flop clocked by clk) Endpoint: out1 (output port clocked by clk) Path Group: clk Path Type: max Corner: fast Cap Slew Delay Time Description ----------------------------------------------------------------------- 0.00 0.00 0.00 clock clk (rise edge) 0.00 0.00 clock network delay (ideal) 0.00 0.00 0.00 ^ reg1/CK (DFF_X1) 0.00 0.00 0.05 0.05 v reg1/Q (DFF_X1) 0.00 0.00 0.05 v out1 (out) 0.05 data arrival time 0.00 10.00 10.00 clock clk (rise edge) 0.00 10.00 clock network delay (ideal) 0.00 10.00 clock reconvergence pessimism 0.00 10.00 output external delay 10.00 data required time ----------------------------------------------------------------------- 10.00 data required time -0.05 data arrival time ----------------------------------------------------------------------- 9.95 slack (MET) PASS: report_checks fast with fields Startpoint: reg1 (rising edge-triggered flip-flop clocked by clk) Endpoint: out1 (output port clocked by clk) Path Group: clk Path Type: max Corner: slow Cap Slew Delay Time Description ----------------------------------------------------------------------- 0.00 0.00 0.00 clock clk (rise edge) 0.00 0.00 clock network delay (ideal) 0.00 0.00 0.00 ^ reg1/CK (DFF_X1) 0.00 0.02 0.29 0.29 ^ reg1/Q (DFF_X1) 0.02 0.00 0.29 ^ out1 (out) 0.29 data arrival time 0.00 10.00 10.00 clock clk (rise edge) 0.00 10.00 clock network delay (ideal) 0.00 10.00 clock reconvergence pessimism 0.00 10.00 output external delay 10.00 data required time ----------------------------------------------------------------------- 10.00 data required time -0.29 data arrival time ----------------------------------------------------------------------- 9.71 slack (MET) PASS: report_checks slow with fields --- set_load and recheck corners --- Startpoint: reg1 (rising edge-triggered flip-flop clocked by clk) Endpoint: out1 (output port clocked by clk) Path Group: clk Path Type: max Corner: fast Delay Time Description --------------------------------------------------------- 0.00 0.00 clock clk (rise edge) 0.00 0.00 clock network delay (ideal) 0.00 0.00 ^ reg1/CK (DFF_X1) 0.05 0.05 v reg1/Q (DFF_X1) 0.00 0.05 v out1 (out) 0.05 data arrival time 10.00 10.00 clock clk (rise edge) 0.00 10.00 clock network delay (ideal) 0.00 10.00 clock reconvergence pessimism 0.00 10.00 output external delay 10.00 data required time --------------------------------------------------------- 10.00 data required time -0.05 data arrival time --------------------------------------------------------- 9.95 slack (MET) PASS: report_checks fast after set_load Startpoint: reg1 (rising edge-triggered flip-flop clocked by clk) Endpoint: out1 (output port clocked by clk) Path Group: clk Path Type: max Corner: slow Delay Time Description --------------------------------------------------------- 0.00 0.00 clock clk (rise edge) 0.00 0.00 clock network delay (ideal) 0.00 0.00 ^ reg1/CK (DFF_X1) 0.29 0.29 ^ reg1/Q (DFF_X1) 0.00 0.29 ^ out1 (out) 0.29 data arrival time 10.00 10.00 clock clk (rise edge) 0.00 10.00 clock network delay (ideal) 0.00 10.00 clock reconvergence pessimism 0.00 10.00 output external delay 10.00 data required time --------------------------------------------------------- 10.00 data required time -0.29 data arrival time --------------------------------------------------------- 9.71 slack (MET) PASS: report_checks slow after set_load ALL PASSED