--- baseline timing --- Startpoint: in1 (input port clocked by clk) Endpoint: reg1 (rising edge-triggered flip-flop clocked by clk) Path Group: clk Path Type: max Delay Time Description --------------------------------------------------------- 0.00 0.00 clock clk (rise edge) 0.00 0.00 clock network delay (ideal) 0.00 0.00 v input external delay 0.00 0.00 v in1 (in) 0.06 0.06 v buf1/Z (BUF_X1) 0.01 0.07 ^ inv1/ZN (INV_X1) 0.00 0.07 ^ reg1/D (DFF_X1) 0.07 data arrival time 10.00 10.00 clock clk (rise edge) 0.00 10.00 clock network delay (ideal) 0.00 10.00 clock reconvergence pessimism 10.00 ^ reg1/CK (DFF_X1) -0.03 9.97 library setup time 9.97 data required time --------------------------------------------------------- 9.97 data required time -0.07 data arrival time --------------------------------------------------------- 9.90 slack (MET) PASS: baseline Startpoint: in1 (input port clocked by clk) Endpoint: reg1 (rising edge-triggered flip-flop clocked by clk) Path Group: clk Path Type: min Delay Time Description --------------------------------------------------------- 0.00 0.00 clock clk (rise edge) 0.00 0.00 clock network delay (ideal) 0.00 0.00 ^ input external delay 0.00 0.00 ^ in1 (in) 0.03 0.03 ^ buf1/Z (BUF_X1) 0.01 0.04 v inv1/ZN (INV_X1) 0.00 0.04 v reg1/D (DFF_X1) 0.04 data arrival time 0.00 0.00 clock clk (rise edge) 0.00 0.00 clock network delay (ideal) 0.00 0.00 clock reconvergence pessimism 0.00 ^ reg1/CK (DFF_X1) 0.00 0.00 library hold time 0.00 data required time --------------------------------------------------------- 0.00 data required time -0.04 data arrival time --------------------------------------------------------- 0.04 slack (MET) PASS: baseline min Startpoint: in1 (input port clocked by clk) Endpoint: reg1 (rising edge-triggered flip-flop clocked by clk) Path Group: clk Path Type: max Delay Time Description --------------------------------------------------------- 0.00 0.00 clock clk (rise edge) 0.00 0.00 clock network delay (ideal) 0.00 0.00 v input external delay 0.00 0.00 v in1 (in) 0.06 0.06 v buf1/Z (BUF_X1) 0.01 0.07 ^ inv1/ZN (INV_X1) 0.00 0.07 ^ reg1/D (DFF_X1) 0.07 data arrival time 10.00 10.00 clock clk (rise edge) 0.00 10.00 clock network delay (ideal) 0.00 10.00 clock reconvergence pessimism 10.00 ^ reg1/CK (DFF_X1) -0.03 9.97 library setup time 9.97 data required time --------------------------------------------------------- 9.97 data required time -0.07 data arrival time --------------------------------------------------------- 9.90 slack (MET) PASS: baseline max --- report_dcalc all arcs --- Library: NangateOpenCellLibrary Cell: BUF_X1 Arc sense: positive_unate Arc type: combinational A ^ -> Z ^ P = 1.00 V = 1.10 T = 25.00 ------- input_net_transition = 0.10 | total_output_net_capacitance = 1.70 | 0.37 1.90 v -------------------- 0.08 | 0.03 0.03 0.13 | 0.03 0.04 Table value = 0.03 PVT scale factor = 1.00 Delay = 0.03 ------- input_net_transition = 0.10 | total_output_net_capacitance = 1.70 | 0.37 1.90 v -------------------- 0.08 | 0.01 0.01 0.13 | 0.01 0.01 Table value = 0.01 PVT scale factor = 1.00 Slew = 0.01 Driver waveform slew = 0.01 ............................................. A v -> Z v P = 1.00 V = 1.10 T = 25.00 ------- input_net_transition = 0.10 | total_output_net_capacitance = 1.55 | 0.37 1.90 v -------------------- 0.08 | 0.05 0.05 0.13 | 0.06 0.07 Table value = 0.06 PVT scale factor = 1.00 Delay = 0.06 ------- input_net_transition = 0.10 | total_output_net_capacitance = 1.55 | 0.37 1.90 v -------------------- 0.08 | 0.01 0.01 0.13 | 0.01 0.01 Table value = 0.01 PVT scale factor = 1.00 Slew = 0.01 Driver waveform slew = 0.01 ............................................. buf1 A->Z max: done Library: NangateOpenCellLibrary Cell: BUF_X1 Arc sense: positive_unate Arc type: combinational A ^ -> Z ^ P = 1.00 V = 1.10 T = 25.00 ------- input_net_transition = 0.10 | total_output_net_capacitance = 1.70 | 0.37 1.90 v -------------------- 0.08 | 0.03 0.03 0.13 | 0.03 0.04 Table value = 0.03 PVT scale factor = 1.00 Delay = 0.03 ------- input_net_transition = 0.10 | total_output_net_capacitance = 1.70 | 0.37 1.90 v -------------------- 0.08 | 0.01 0.01 0.13 | 0.01 0.01 Table value = 0.01 PVT scale factor = 1.00 Slew = 0.01 Driver waveform slew = 0.01 ............................................. A v -> Z v P = 1.00 V = 1.10 T = 25.00 ------- input_net_transition = 0.10 | total_output_net_capacitance = 1.55 | 0.37 1.90 v -------------------- 0.08 | 0.05 0.05 0.13 | 0.06 0.07 Table value = 0.06 PVT scale factor = 1.00 Delay = 0.06 ------- input_net_transition = 0.10 | total_output_net_capacitance = 1.55 | 0.37 1.90 v -------------------- 0.08 | 0.01 0.01 0.13 | 0.01 0.01 Table value = 0.01 PVT scale factor = 1.00 Slew = 0.01 Driver waveform slew = 0.01 ............................................. buf1 A->Z min: done Library: NangateOpenCellLibrary Cell: INV_X1 Arc sense: negative_unate Arc type: combinational A ^ -> ZN v P = 1.00 V = 1.10 T = 25.00 ------- input_net_transition = 0.01 | total_output_net_capacitance = 1.06 | 0.37 1.90 v -------------------- 0.00 | 0.00 0.01 0.02 | 0.01 0.01 Table value = 0.01 PVT scale factor = 1.00 Delay = 0.01 ------- input_net_transition = 0.01 | total_output_net_capacitance = 1.06 | 0.37 1.90 v -------------------- 0.00 | 0.00 0.00 0.02 | 0.00 0.01 Table value = 0.00 PVT scale factor = 1.00 Slew = 0.00 Driver waveform slew = 0.00 ............................................. A v -> ZN ^ P = 1.00 V = 1.10 T = 25.00 ------- input_net_transition = 0.01 | total_output_net_capacitance = 1.14 | 0.37 1.90 v -------------------- 0.00 | 0.01 0.01 0.02 | 0.01 0.02 Table value = 0.01 PVT scale factor = 1.00 Delay = 0.01 ------- input_net_transition = 0.01 | total_output_net_capacitance = 1.14 | 0.37 1.90 v -------------------- 0.00 | 0.00 0.01 0.02 | 0.01 0.01 Table value = 0.01 PVT scale factor = 1.00 Slew = 0.01 Driver waveform slew = 0.01 ............................................. inv1 A->ZN max: done Library: NangateOpenCellLibrary Cell: INV_X1 Arc sense: negative_unate Arc type: combinational A ^ -> ZN v P = 1.00 V = 1.10 T = 25.00 ------- input_net_transition = 0.01 | total_output_net_capacitance = 1.06 | 0.37 1.90 v -------------------- 0.00 | 0.00 0.01 0.02 | 0.01 0.01 Table value = 0.01 PVT scale factor = 1.00 Delay = 0.01 ------- input_net_transition = 0.01 | total_output_net_capacitance = 1.06 | 0.37 1.90 v -------------------- 0.00 | 0.00 0.00 0.02 | 0.00 0.01 Table value = 0.00 PVT scale factor = 1.00 Slew = 0.00 Driver waveform slew = 0.00 ............................................. A v -> ZN ^ P = 1.00 V = 1.10 T = 25.00 ------- input_net_transition = 0.01 | total_output_net_capacitance = 1.14 | 0.37 1.90 v -------------------- 0.00 | 0.01 0.01 0.02 | 0.01 0.02 Table value = 0.01 PVT scale factor = 1.00 Delay = 0.01 ------- input_net_transition = 0.01 | total_output_net_capacitance = 1.14 | 0.37 1.90 v -------------------- 0.00 | 0.00 0.01 0.02 | 0.01 0.01 Table value = 0.01 PVT scale factor = 1.00 Slew = 0.01 Driver waveform slew = 0.01 ............................................. inv1 A->ZN min: done Library: NangateOpenCellLibrary Cell: DFF_X1 Arc sense: non_unate Arc type: Reg Clk to Q CK ^ -> Q ^ P = 1.00 V = 1.10 T = 25.00 ------- input_net_transition = 0.00 | total_output_net_capacitance = 0.00 | 0.37 1.90 v -------------------- 0.00 | 0.08 0.09 0.00 | 0.08 0.09 Table value = 0.08 PVT scale factor = 1.00 Delay = 0.08 ------- input_net_transition = 0.00 | total_output_net_capacitance = 0.00 | 0.37 1.90 v -------------------- 0.00 | 0.01 0.01 0.00 | 0.01 0.01 Table value = 0.01 PVT scale factor = 1.00 Slew = 0.01 Driver waveform slew = 0.01 ............................................. CK ^ -> Q v P = 1.00 V = 1.10 T = 25.00 ------- input_net_transition = 0.00 | total_output_net_capacitance = 0.00 | 0.37 1.90 v -------------------- 0.00 | 0.08 0.08 0.00 | 0.08 0.08 Table value = 0.08 PVT scale factor = 1.00 Delay = 0.08 ------- input_net_transition = 0.00 | total_output_net_capacitance = 0.00 | 0.37 1.90 v -------------------- 0.00 | 0.01 0.01 0.00 | 0.01 0.01 Table value = 0.00 PVT scale factor = 1.00 Slew = 0.00 Driver waveform slew = 0.00 ............................................. reg1 CK->Q max: done Library: NangateOpenCellLibrary Cell: DFF_X1 Arc sense: non_unate Arc type: Reg Clk to Q CK ^ -> Q ^ P = 1.00 V = 1.10 T = 25.00 ------- input_net_transition = 0.00 | total_output_net_capacitance = 0.00 | 0.37 1.90 v -------------------- 0.00 | 0.08 0.09 0.00 | 0.08 0.09 Table value = 0.08 PVT scale factor = 1.00 Delay = 0.08 ------- input_net_transition = 0.00 | total_output_net_capacitance = 0.00 | 0.37 1.90 v -------------------- 0.00 | 0.01 0.01 0.00 | 0.01 0.01 Table value = 0.01 PVT scale factor = 1.00 Slew = 0.01 Driver waveform slew = 0.01 ............................................. CK ^ -> Q v P = 1.00 V = 1.10 T = 25.00 ------- input_net_transition = 0.00 | total_output_net_capacitance = 0.00 | 0.37 1.90 v -------------------- 0.00 | 0.08 0.08 0.00 | 0.08 0.08 Table value = 0.08 PVT scale factor = 1.00 Delay = 0.08 ------- input_net_transition = 0.00 | total_output_net_capacitance = 0.00 | 0.37 1.90 v -------------------- 0.00 | 0.01 0.01 0.00 | 0.01 0.01 Table value = 0.00 PVT scale factor = 1.00 Slew = 0.00 Driver waveform slew = 0.00 ............................................. reg1 CK->Q min: done Library: NangateOpenCellLibrary Cell: DFF_X1 Arc type: setup CK ^ -> D ^ P = 1.00 V = 1.10 T = 25.00 ------- constrained_pin_transition = 0.01 (ideal clock) | related_pin_transition = 0.00 | 0.00 0.04 v -------------------- 0.00 | 0.03 0.02 0.04 | 0.04 0.03 Table value = 0.03 PVT scale factor = 1.00 Check = 0.03 ............................................. CK ^ -> D v P = 1.00 V = 1.10 T = 25.00 ------- constrained_pin_transition = 0.00 (ideal clock) | related_pin_transition = 0.00 | 0.00 0.04 v -------------------- 0.00 | 0.04 0.02 0.04 | 0.05 0.04 Table value = 0.04 PVT scale factor = 1.00 Check = 0.04 ............................................. reg1 setup max: done Library: NangateOpenCellLibrary Cell: DFF_X1 Arc type: hold CK ^ -> D ^ P = 1.00 V = 1.10 T = 25.00 ------- constrained_pin_transition = 0.01 (ideal clock) | related_pin_transition = 0.00 | 0.00 0.04 v -------------------- 0.00 | 0.00 0.02 0.04 | 0.02 0.03 Table value = 0.00 PVT scale factor = 1.00 Check = 0.00 ............................................. CK ^ -> D v P = 1.00 V = 1.10 T = 25.00 ------- constrained_pin_transition = 0.00 (ideal clock) | related_pin_transition = 0.00 | 0.00 0.04 v -------------------- 0.00 | 0.00 0.01 0.04 | 0.00 0.01 Table value = 0.00 PVT scale factor = 1.00 Check = 0.00 ............................................. reg1 hold min: done PASS: report_dcalc all arcs --- delay calculator engines --- Startpoint: in1 (input port clocked by clk) Endpoint: reg1 (rising edge-triggered flip-flop clocked by clk) Path Group: clk Path Type: max Delay Time Description --------------------------------------------------------- 0.00 0.00 clock clk (rise edge) 0.00 0.00 clock network delay (ideal) 0.00 0.00 v input external delay 0.00 0.00 v in1 (in) 1.00 1.00 v buf1/Z (BUF_X1) 1.00 2.00 ^ inv1/ZN (INV_X1) 0.00 2.00 ^ reg1/D (DFF_X1) 2.00 data arrival time 10.00 10.00 clock clk (rise edge) 0.00 10.00 clock network delay (ideal) 0.00 10.00 clock reconvergence pessimism 10.00 ^ reg1/CK (DFF_X1) -1.00 9.00 library setup time 9.00 data required time --------------------------------------------------------- 9.00 data required time -2.00 data arrival time --------------------------------------------------------- 7.00 slack (MET) PASS: unit calculator Library: NangateOpenCellLibrary Cell: BUF_X1 Arc sense: positive_unate Arc type: combinational A ^ -> Z ^ Delay = 1.0 Slew = 0.0 ............................................. A v -> Z v Delay = 1.0 Slew = 0.0 ............................................. unit buf1: done Startpoint: in1 (input port clocked by clk) Endpoint: reg1 (rising edge-triggered flip-flop clocked by clk) Path Group: clk Path Type: max Delay Time Description --------------------------------------------------------- 0.00 0.00 clock clk (rise edge) 0.00 0.00 clock network delay (ideal) 0.00 0.00 v input external delay 0.00 0.00 v in1 (in) 0.06 0.06 v buf1/Z (BUF_X1) 0.01 0.07 ^ inv1/ZN (INV_X1) 0.00 0.07 ^ reg1/D (DFF_X1) 0.07 data arrival time 10.00 10.00 clock clk (rise edge) 0.00 10.00 clock network delay (ideal) 0.00 10.00 clock reconvergence pessimism 10.00 ^ reg1/CK (DFF_X1) -0.03 9.97 library setup time 9.97 data required time --------------------------------------------------------- 9.97 data required time -0.07 data arrival time --------------------------------------------------------- 9.90 slack (MET) PASS: lumped_cap calculator Library: NangateOpenCellLibrary Cell: BUF_X1 Arc sense: positive_unate Arc type: combinational A ^ -> Z ^ P = 1.00 V = 1.10 T = 25.00 ------- input_net_transition = 0.10 | total_output_net_capacitance = 1.70 | 0.37 1.90 v -------------------- 0.08 | 0.03 0.03 0.13 | 0.03 0.04 Table value = 0.03 PVT scale factor = 1.00 Delay = 0.03 ------- input_net_transition = 0.10 | total_output_net_capacitance = 1.70 | 0.37 1.90 v -------------------- 0.08 | 0.01 0.01 0.13 | 0.01 0.01 Table value = 0.01 PVT scale factor = 1.00 Slew = 0.01 ............................................. A v -> Z v P = 1.00 V = 1.10 T = 25.00 ------- input_net_transition = 0.10 | total_output_net_capacitance = 1.55 | 0.37 1.90 v -------------------- 0.08 | 0.05 0.05 0.13 | 0.06 0.07 Table value = 0.06 PVT scale factor = 1.00 Delay = 0.06 ------- input_net_transition = 0.10 | total_output_net_capacitance = 1.55 | 0.37 1.90 v -------------------- 0.08 | 0.01 0.01 0.13 | 0.01 0.01 Table value = 0.01 PVT scale factor = 1.00 Slew = 0.01 ............................................. lumped_cap buf1: done Startpoint: in1 (input port clocked by clk) Endpoint: reg1 (rising edge-triggered flip-flop clocked by clk) Path Group: clk Path Type: max Delay Time Description --------------------------------------------------------- 0.00 0.00 clock clk (rise edge) 0.00 0.00 clock network delay (ideal) 0.00 0.00 v input external delay 0.00 0.00 v in1 (in) 0.06 0.06 v buf1/Z (BUF_X1) 0.01 0.07 ^ inv1/ZN (INV_X1) 0.00 0.07 ^ reg1/D (DFF_X1) 0.07 data arrival time 10.00 10.00 clock clk (rise edge) 0.00 10.00 clock network delay (ideal) 0.00 10.00 clock reconvergence pessimism 10.00 ^ reg1/CK (DFF_X1) -0.03 9.97 library setup time 9.97 data required time --------------------------------------------------------- 9.97 data required time -0.07 data arrival time --------------------------------------------------------- 9.90 slack (MET) PASS: dmp_ceff_elmore calculator Library: NangateOpenCellLibrary Cell: BUF_X1 Arc sense: positive_unate Arc type: combinational A ^ -> Z ^ P = 1.00 V = 1.10 T = 25.00 ------- input_net_transition = 0.10 | total_output_net_capacitance = 1.70 | 0.37 1.90 v -------------------- 0.08 | 0.03 0.03 0.13 | 0.03 0.04 Table value = 0.03 PVT scale factor = 1.00 Delay = 0.03 ------- input_net_transition = 0.10 | total_output_net_capacitance = 1.70 | 0.37 1.90 v -------------------- 0.08 | 0.01 0.01 0.13 | 0.01 0.01 Table value = 0.01 PVT scale factor = 1.00 Slew = 0.01 Driver waveform slew = 0.01 ............................................. A v -> Z v P = 1.00 V = 1.10 T = 25.00 ------- input_net_transition = 0.10 | total_output_net_capacitance = 1.55 | 0.37 1.90 v -------------------- 0.08 | 0.05 0.05 0.13 | 0.06 0.07 Table value = 0.06 PVT scale factor = 1.00 Delay = 0.06 ------- input_net_transition = 0.10 | total_output_net_capacitance = 1.55 | 0.37 1.90 v -------------------- 0.08 | 0.01 0.01 0.13 | 0.01 0.01 Table value = 0.01 PVT scale factor = 1.00 Slew = 0.01 Driver waveform slew = 0.01 ............................................. dmp_elmore buf1: done Startpoint: in1 (input port clocked by clk) Endpoint: reg1 (rising edge-triggered flip-flop clocked by clk) Path Group: clk Path Type: max Delay Time Description --------------------------------------------------------- 0.00 0.00 clock clk (rise edge) 0.00 0.00 clock network delay (ideal) 0.00 0.00 v input external delay 0.00 0.00 v in1 (in) 0.06 0.06 v buf1/Z (BUF_X1) 0.01 0.07 ^ inv1/ZN (INV_X1) 0.00 0.07 ^ reg1/D (DFF_X1) 0.07 data arrival time 10.00 10.00 clock clk (rise edge) 0.00 10.00 clock network delay (ideal) 0.00 10.00 clock reconvergence pessimism 10.00 ^ reg1/CK (DFF_X1) -0.03 9.97 library setup time 9.97 data required time --------------------------------------------------------- 9.97 data required time -0.07 data arrival time --------------------------------------------------------- 9.90 slack (MET) PASS: dmp_ceff_two_pole calculator Library: NangateOpenCellLibrary Cell: BUF_X1 Arc sense: positive_unate Arc type: combinational A ^ -> Z ^ P = 1.00 V = 1.10 T = 25.00 ------- input_net_transition = 0.10 | total_output_net_capacitance = 1.70 | 0.37 1.90 v -------------------- 0.08 | 0.03 0.03 0.13 | 0.03 0.04 Table value = 0.03 PVT scale factor = 1.00 Delay = 0.03 ------- input_net_transition = 0.10 | total_output_net_capacitance = 1.70 | 0.37 1.90 v -------------------- 0.08 | 0.01 0.01 0.13 | 0.01 0.01 Table value = 0.01 PVT scale factor = 1.00 Slew = 0.01 Driver waveform slew = 0.01 ............................................. A v -> Z v P = 1.00 V = 1.10 T = 25.00 ------- input_net_transition = 0.10 | total_output_net_capacitance = 1.55 | 0.37 1.90 v -------------------- 0.08 | 0.05 0.05 0.13 | 0.06 0.07 Table value = 0.06 PVT scale factor = 1.00 Delay = 0.06 ------- input_net_transition = 0.10 | total_output_net_capacitance = 1.55 | 0.37 1.90 v -------------------- 0.08 | 0.01 0.01 0.13 | 0.01 0.01 Table value = 0.01 PVT scale factor = 1.00 Slew = 0.01 Driver waveform slew = 0.01 ............................................. dmp_two_pole buf1: done Startpoint: in1 (input port clocked by clk) Endpoint: reg1 (rising edge-triggered flip-flop clocked by clk) Path Group: clk Path Type: max Delay Time Description --------------------------------------------------------- 0.00 0.00 clock clk (rise edge) 0.00 0.00 clock network delay (ideal) 0.00 0.00 v input external delay 0.00 0.00 v in1 (in) 0.06 0.06 v buf1/Z (BUF_X1) 0.01 0.07 ^ inv1/ZN (INV_X1) 0.00 0.07 ^ reg1/D (DFF_X1) 0.07 data arrival time 10.00 10.00 clock clk (rise edge) 0.00 10.00 clock network delay (ideal) 0.00 10.00 clock reconvergence pessimism 10.00 ^ reg1/CK (DFF_X1) -0.03 9.97 library setup time 9.97 data required time --------------------------------------------------------- 9.97 data required time -0.07 data arrival time --------------------------------------------------------- 9.90 slack (MET) PASS: ccs_ceff calculator --- load variation --- No paths found. load=0.00001: done No paths found. load=0.0001: done No paths found. load=0.001: done No paths found. load=0.005: done No paths found. load=0.01: done No paths found. load=0.05: done No paths found. load=0.1: done No paths found. load=0.5: done No paths found. load=1.0: done No paths found. load=5.0: done PASS: load variation --- slew variation --- No paths found. slew=0.001: done No paths found. slew=0.005: done No paths found. slew=0.01: done No paths found. slew=0.05: done No paths found. slew=0.1: done No paths found. slew=0.2: done No paths found. slew=0.5: done No paths found. slew=1.0: done No paths found. slew=2.0: done PASS: slew variation --- incremental delay calc --- Startpoint: in1 (input port clocked by clk) Endpoint: reg1 (rising edge-triggered flip-flop clocked by clk) Path Group: clk Path Type: max Delay Time Description --------------------------------------------------------- 0.00 0.00 clock clk (rise edge) 0.00 0.00 clock network delay (ideal) 0.00 0.00 v input external delay 0.00 0.00 v in1 (in) 0.06 0.06 v buf1/Z (BUF_X1) 0.01 0.07 ^ inv1/ZN (INV_X1) 0.00 0.07 ^ reg1/D (DFF_X1) 0.07 data arrival time 5.00 5.00 clock clk (rise edge) 0.00 5.00 clock network delay (ideal) 0.00 5.00 clock reconvergence pessimism 5.00 ^ reg1/CK (DFF_X1) -0.03 4.97 library setup time 4.97 data required time --------------------------------------------------------- 4.97 data required time -0.07 data arrival time --------------------------------------------------------- 4.90 slack (MET) PASS: incremental after clock change Startpoint: in1 (input port clocked by clk) Endpoint: reg1 (rising edge-triggered flip-flop clocked by clk) Path Group: clk Path Type: max Delay Time Description --------------------------------------------------------- 0.00 0.00 clock clk (rise edge) 0.00 0.00 clock network delay (ideal) 2.00 2.00 v input external delay 0.00 2.00 v in1 (in) 0.06 2.06 v buf1/Z (BUF_X1) 0.01 2.07 ^ inv1/ZN (INV_X1) 0.00 2.07 ^ reg1/D (DFF_X1) 2.07 data arrival time 5.00 5.00 clock clk (rise edge) 0.00 5.00 clock network delay (ideal) 0.00 5.00 clock reconvergence pessimism 5.00 ^ reg1/CK (DFF_X1) -0.03 4.97 library setup time 4.97 data required time --------------------------------------------------------- 4.97 data required time -2.07 data arrival time --------------------------------------------------------- 2.90 slack (MET) PASS: incremental after input delay change Startpoint: reg1 (rising edge-triggered flip-flop clocked by clk) Endpoint: out1 (output port clocked by clk) Path Group: clk Path Type: max Delay Time Description --------------------------------------------------------- 0.00 0.00 clock clk (rise edge) 0.00 0.00 clock network delay (ideal) 0.00 0.00 ^ reg1/CK (DFF_X1) 0.08 0.08 ^ reg1/Q (DFF_X1) 0.00 0.08 ^ out1 (out) 0.08 data arrival time 5.00 5.00 clock clk (rise edge) 0.00 5.00 clock network delay (ideal) 0.00 5.00 clock reconvergence pessimism -3.00 2.00 output external delay 2.00 data required time --------------------------------------------------------- 2.00 data required time -0.08 data arrival time --------------------------------------------------------- 1.92 slack (MET) PASS: incremental after output delay change Startpoint: in1 (input port clocked by clk) Endpoint: reg1 (rising edge-triggered flip-flop clocked by clk) Path Group: clk Path Type: max Delay Time Description --------------------------------------------------------- 0.00 0.00 clock clk (rise edge) 0.00 0.00 clock network delay (ideal) 0.00 0.00 v input external delay 0.00 0.00 v in1 (in) 0.06 0.06 v buf1/Z (BUF_X1) 0.01 0.07 ^ inv1/ZN (INV_X1) 0.00 0.07 ^ reg1/D (DFF_X1) 0.07 data arrival time 10.00 10.00 clock clk (rise edge) 0.00 10.00 clock network delay (ideal) 0.00 10.00 clock reconvergence pessimism 10.00 ^ reg1/CK (DFF_X1) -0.03 9.97 library setup time 9.97 data required time --------------------------------------------------------- 9.97 data required time -0.07 data arrival time --------------------------------------------------------- 9.90 slack (MET) PASS: incremental after reset --- report formatting --- Warning: dcalc_annotate_slew.tcl line 1, unknown field nets. Startpoint: in1 (input port clocked by clk) Endpoint: reg1 (rising edge-triggered flip-flop clocked by clk) Path Group: clk Path Type: max Fanout Cap Slew Delay Time Description ----------------------------------------------------------------------------- 0.00 0.00 0.00 clock clk (rise edge) 0.00 0.00 clock network delay (ideal) 0.00 0.00 v input external delay 1 0.88 0.10 0.00 0.00 v in1 (in) 0.10 0.00 0.00 v buf1/A (BUF_X1) 1 1.55 0.01 0.06 0.06 v buf1/Z (BUF_X1) 0.01 0.00 0.06 v inv1/A (INV_X1) 1 1.14 0.01 0.01 0.07 ^ inv1/ZN (INV_X1) 0.01 0.00 0.07 ^ reg1/D (DFF_X1) 0.07 data arrival time 0.00 10.00 10.00 clock clk (rise edge) 0.00 10.00 clock network delay (ideal) 0.00 10.00 clock reconvergence pessimism 10.00 ^ reg1/CK (DFF_X1) -0.03 9.97 library setup time 9.97 data required time ----------------------------------------------------------------------------- 9.97 data required time -0.07 data arrival time ----------------------------------------------------------------------------- 9.90 slack (MET) PASS: fields Startpoint: in1 (input port clocked by clk) Endpoint: reg1 (rising edge-triggered flip-flop clocked by clk) Path Group: clk Path Type: max Delay Time Description --------------------------------------------------------- 0.00 0.00 clock clk (rise edge) 0.00 0.00 clock network delay (ideal) 0.00 0.00 v input external delay 0.00 0.00 v in1 (in) 0.06 0.06 v buf1/Z (BUF_X1) 0.01 0.07 ^ inv1/ZN (INV_X1) 0.00 0.07 ^ reg1/D (DFF_X1) 0.07 data arrival time 10.00 10.00 clock clk (rise edge) 0.00 10.00 clock network delay (ideal) 0.00 10.00 clock reconvergence pessimism 10.00 ^ reg1/CK (DFF_X1) -0.03 9.97 library setup time 9.97 data required time --------------------------------------------------------- 9.97 data required time -0.07 data arrival time --------------------------------------------------------- 9.90 slack (MET) PASS: full_clock Startpoint: in1 (input port clocked by clk) Endpoint: reg1 (rising edge-triggered flip-flop clocked by clk) Path Group: clk Path Type: max Delay Time Description --------------------------------------------------------- 0.00 0.00 clock clk (rise edge) 0.00 0.00 clock network delay (ideal) 0.00 0.00 v input external delay 0.00 0.00 v in1 (in) 0.06 0.06 v buf1/Z (BUF_X1) 0.01 0.07 ^ inv1/ZN (INV_X1) 0.00 0.07 ^ reg1/D (DFF_X1) 0.07 data arrival time 10.00 10.00 clock clk (rise edge) 0.00 10.00 clock network delay (ideal) 0.00 10.00 clock reconvergence pessimism 10.00 ^ reg1/CK (DFF_X1) -0.03 9.97 library setup time 9.97 data required time --------------------------------------------------------- 9.97 data required time -0.07 data arrival time --------------------------------------------------------- 9.90 slack (MET) PASS: full_clock_expanded Warning: dcalc_annotate_slew.tcl line 1, report_checks -endpoint_count is deprecated. Use -endpoint_path_count instead. Startpoint: in1 (input port clocked by clk) Endpoint: reg1 (rising edge-triggered flip-flop clocked by clk) Path Group: clk Path Type: max Delay Time Description --------------------------------------------------------- 0.00 0.00 clock clk (rise edge) 0.00 0.00 clock network delay (ideal) 0.00 0.00 v input external delay 0.00 0.00 v in1 (in) 0.06 0.06 v buf1/Z (BUF_X1) 0.01 0.07 ^ inv1/ZN (INV_X1) 0.00 0.07 ^ reg1/D (DFF_X1) 0.07 data arrival time 10.00 10.00 clock clk (rise edge) 0.00 10.00 clock network delay (ideal) 0.00 10.00 clock reconvergence pessimism 10.00 ^ reg1/CK (DFF_X1) -0.03 9.97 library setup time 9.97 data required time --------------------------------------------------------- 9.97 data required time -0.07 data arrival time --------------------------------------------------------- 9.90 slack (MET) Startpoint: reg1 (rising edge-triggered flip-flop clocked by clk) Endpoint: out1 (output port clocked by clk) Path Group: clk Path Type: max Delay Time Description --------------------------------------------------------- 0.00 0.00 clock clk (rise edge) 0.00 0.00 clock network delay (ideal) 0.00 0.00 ^ reg1/CK (DFF_X1) 0.08 0.08 ^ reg1/Q (DFF_X1) 0.00 0.08 ^ out1 (out) 0.08 data arrival time 10.00 10.00 clock clk (rise edge) 0.00 10.00 clock network delay (ideal) 0.00 10.00 clock reconvergence pessimism 0.00 10.00 output external delay 10.00 data required time --------------------------------------------------------- 10.00 data required time -0.08 data arrival time --------------------------------------------------------- 9.92 slack (MET) Startpoint: in1 (input port clocked by clk) Endpoint: reg1 (rising edge-triggered flip-flop clocked by clk) Path Group: clk Path Type: max Delay Time Description --------------------------------------------------------- 0.00 0.00 clock clk (rise edge) 0.00 0.00 clock network delay (ideal) 0.00 0.00 ^ input external delay 0.00 0.00 ^ in1 (in) 0.03 0.03 ^ buf1/Z (BUF_X1) 0.01 0.04 v inv1/ZN (INV_X1) 0.00 0.04 v reg1/D (DFF_X1) 0.04 data arrival time 10.00 10.00 clock clk (rise edge) 0.00 10.00 clock network delay (ideal) 0.00 10.00 clock reconvergence pessimism 10.00 ^ reg1/CK (DFF_X1) -0.04 9.96 library setup time 9.96 data required time --------------------------------------------------------- 9.96 data required time -0.04 data arrival time --------------------------------------------------------- 9.92 slack (MET) PASS: endpoint_count Startpoint: in1 (input port clocked by clk) Endpoint: reg1 (rising edge-triggered flip-flop clocked by clk) Path Group: clk Path Type: max Delay Time Description --------------------------------------------------------- 0.00 0.00 clock clk (rise edge) 0.00 0.00 clock network delay (ideal) 0.00 0.00 v input external delay 0.00 0.00 v in1 (in) 0.06 0.06 v buf1/Z (BUF_X1) 0.01 0.07 ^ inv1/ZN (INV_X1) 0.00 0.07 ^ reg1/D (DFF_X1) 0.07 data arrival time 10.00 10.00 clock clk (rise edge) 0.00 10.00 clock network delay (ideal) 0.00 10.00 clock reconvergence pessimism 10.00 ^ reg1/CK (DFF_X1) -0.03 9.97 library setup time 9.97 data required time --------------------------------------------------------- 9.97 data required time -0.07 data arrival time --------------------------------------------------------- 9.90 slack (MET) PASS: unconstrained Startpoint: in1 (input port clocked by clk) Endpoint: reg1 (rising edge-triggered flip-flop clocked by clk) Path Group: clk Path Type: max Delay Time Description --------------------------------------------------------- 0.00 0.00 clock clk (rise edge) 0.00 0.00 clock network delay (ideal) 0.00 0.00 v input external delay 0.00 0.00 v in1 (in) 0.06 0.06 v buf1/Z (BUF_X1) 0.01 0.07 ^ inv1/ZN (INV_X1) 0.00 0.07 ^ reg1/D (DFF_X1) 0.07 data arrival time 10.00 10.00 clock clk (rise edge) 0.00 10.00 clock network delay (ideal) 0.00 10.00 clock reconvergence pessimism 10.00 ^ reg1/CK (DFF_X1) -0.03 9.97 library setup time 9.97 data required time --------------------------------------------------------- 9.97 data required time -0.07 data arrival time --------------------------------------------------------- 9.90 slack (MET) PASS: sort_by_slack --- report_check_types --- Startpoint: in1 (input port clocked by clk) Endpoint: reg1 (rising edge-triggered flip-flop clocked by clk) Path Group: clk Path Type: max Delay Time Description --------------------------------------------------------- 0.00 0.00 clock clk (rise edge) 0.00 0.00 clock network delay (ideal) 0.00 0.00 v input external delay 0.00 0.00 v in1 (in) 0.06 0.06 v buf1/Z (BUF_X1) 0.01 0.07 ^ inv1/ZN (INV_X1) 0.00 0.07 ^ reg1/D (DFF_X1) 0.07 data arrival time 10.00 10.00 clock clk (rise edge) 0.00 10.00 clock network delay (ideal) 0.00 10.00 clock reconvergence pessimism 10.00 ^ reg1/CK (DFF_X1) -0.03 9.97 library setup time 9.97 data required time --------------------------------------------------------- 9.97 data required time -0.07 data arrival time --------------------------------------------------------- 9.90 slack (MET) PASS: check_types max Startpoint: in1 (input port clocked by clk) Endpoint: reg1 (rising edge-triggered flip-flop clocked by clk) Path Group: clk Path Type: min Delay Time Description --------------------------------------------------------- 0.00 0.00 clock clk (rise edge) 0.00 0.00 clock network delay (ideal) 0.00 0.00 ^ input external delay 0.00 0.00 ^ in1 (in) 0.03 0.03 ^ buf1/Z (BUF_X1) 0.01 0.04 v inv1/ZN (INV_X1) 0.00 0.04 v reg1/D (DFF_X1) 0.04 data arrival time 0.00 0.00 clock clk (rise edge) 0.00 0.00 clock network delay (ideal) 0.00 0.00 clock reconvergence pessimism 0.00 ^ reg1/CK (DFF_X1) 0.00 0.00 library hold time 0.00 data required time --------------------------------------------------------- 0.00 data required time -0.04 data arrival time --------------------------------------------------------- 0.04 slack (MET) PASS: check_types min --- report_slews --- in1 ^ 0.10:0.10 v 0.10:0.10 out1 ^ 0.01:0.01 v 0.00:0.00 buf1/A ^ 0.10:0.10 v 0.10:0.10 buf1/Z ^ 0.01:0.01 v 0.01:0.01 inv1/A ^ 0.01:0.01 v 0.01:0.01 inv1/ZN ^ 0.01:0.01 v 0.00:0.00 reg1/D ^ 0.01:0.01 v 0.00:0.00 reg1/CK ^ 0.10:0.10 v 0.10:0.10 reg1/Q ^ 0.01:0.01 v 0.00:0.00 PASS: report_slews ALL PASSED