--- set_load variations --- Startpoint: reg1 (rising edge-triggered flip-flop clocked by clk) Endpoint: out1 (output port clocked by clk) Path Group: clk Path Type: max Delay Time Description --------------------------------------------------------- 0.00 0.00 clock clk (rise edge) 0.00 0.00 clock network delay (ideal) 0.00 0.00 ^ reg1/CK (DFF_X1) 0.08 0.08 ^ reg1/Q (DFF_X1) 0.00 0.08 ^ out1 (out) 0.08 data arrival time 10.00 10.00 clock clk (rise edge) 0.00 10.00 clock network delay (ideal) 0.00 10.00 clock reconvergence pessimism 0.00 10.00 output external delay 10.00 data required time --------------------------------------------------------- 10.00 data required time -0.08 data arrival time --------------------------------------------------------- 9.92 slack (MET) PASS: report_checks with 1fF load Startpoint: reg1 (rising edge-triggered flip-flop clocked by clk) Endpoint: out1 (output port clocked by clk) Path Group: clk Path Type: max Delay Time Description --------------------------------------------------------- 0.00 0.00 clock clk (rise edge) 0.00 0.00 clock network delay (ideal) 0.00 0.00 ^ reg1/CK (DFF_X1) 0.08 0.08 ^ reg1/Q (DFF_X1) 0.00 0.08 ^ out1 (out) 0.08 data arrival time 10.00 10.00 clock clk (rise edge) 0.00 10.00 clock network delay (ideal) 0.00 10.00 clock reconvergence pessimism 0.00 10.00 output external delay 10.00 data required time --------------------------------------------------------- 10.00 data required time -0.08 data arrival time --------------------------------------------------------- 9.92 slack (MET) PASS: report_checks with 100fF load Startpoint: reg1 (rising edge-triggered flip-flop clocked by clk) Endpoint: out1 (output port clocked by clk) Path Group: clk Path Type: max Delay Time Description --------------------------------------------------------- 0.00 0.00 clock clk (rise edge) 0.00 0.00 clock network delay (ideal) 0.00 0.00 ^ reg1/CK (DFF_X1) 0.08 0.08 ^ reg1/Q (DFF_X1) 0.00 0.08 ^ out1 (out) 0.08 data arrival time 10.00 10.00 clock clk (rise edge) 0.00 10.00 clock network delay (ideal) 0.00 10.00 clock reconvergence pessimism 0.00 10.00 output external delay 10.00 data required time --------------------------------------------------------- 10.00 data required time -0.08 data arrival time --------------------------------------------------------- 9.92 slack (MET) PASS: report_checks with 1pF load --- set_input_transition --- Startpoint: reg1 (rising edge-triggered flip-flop clocked by clk) Endpoint: out1 (output port clocked by clk) Path Group: clk Path Type: max Delay Time Description --------------------------------------------------------- 0.00 0.00 clock clk (rise edge) 0.00 0.00 clock network delay (ideal) 0.00 0.00 ^ reg1/CK (DFF_X1) 0.08 0.08 ^ reg1/Q (DFF_X1) 0.00 0.08 ^ out1 (out) 0.08 data arrival time 10.00 10.00 clock clk (rise edge) 0.00 10.00 clock network delay (ideal) 0.00 10.00 clock reconvergence pessimism 0.00 10.00 output external delay 10.00 data required time --------------------------------------------------------- 10.00 data required time -0.08 data arrival time --------------------------------------------------------- 9.92 slack (MET) PASS: report_checks with 10ps input transition Startpoint: in1 (input port clocked by clk) Endpoint: reg1 (rising edge-triggered flip-flop clocked by clk) Path Group: clk Path Type: max Delay Time Description --------------------------------------------------------- 0.00 0.00 clock clk (rise edge) 0.00 0.00 clock network delay (ideal) 0.00 0.00 v input external delay 0.00 0.00 v in1 (in) 0.14 0.14 v buf1/Z (BUF_X1) 0.02 0.16 ^ inv1/ZN (INV_X1) 0.00 0.16 ^ reg1/D (DFF_X1) 0.16 data arrival time 10.00 10.00 clock clk (rise edge) 0.00 10.00 clock network delay (ideal) 0.00 10.00 clock reconvergence pessimism 10.00 ^ reg1/CK (DFF_X1) -0.03 9.97 library setup time 9.97 data required time --------------------------------------------------------- 9.97 data required time -0.16 data arrival time --------------------------------------------------------- 9.81 slack (MET) PASS: report_checks with 500ps input transition --- report_dcalc all arcs --- Library: NangateOpenCellLibrary Cell: BUF_X1 Arc sense: positive_unate Arc type: combinational A ^ -> Z ^ P = 1.00 V = 1.10 T = 25.00 ------- input_net_transition = 0.10 | total_output_net_capacitance = 1.70 | 0.37 1.90 v -------------------- 0.08 | 0.03 0.03 0.13 | 0.03 0.04 Table value = 0.03 PVT scale factor = 1.00 Delay = 0.03 ------- input_net_transition = 0.10 | total_output_net_capacitance = 1.70 | 0.37 1.90 v -------------------- 0.08 | 0.01 0.01 0.13 | 0.01 0.01 Table value = 0.01 PVT scale factor = 1.00 Slew = 0.01 Driver waveform slew = 0.01 ............................................. A v -> Z v P = 1.00 V = 1.10 T = 25.00 ------- input_net_transition = 0.10 | total_output_net_capacitance = 1.55 | 0.37 1.90 v -------------------- 0.08 | 0.05 0.05 0.13 | 0.06 0.07 Table value = 0.06 PVT scale factor = 1.00 Delay = 0.06 ------- input_net_transition = 0.10 | total_output_net_capacitance = 1.55 | 0.37 1.90 v -------------------- 0.08 | 0.01 0.01 0.13 | 0.01 0.01 Table value = 0.01 PVT scale factor = 1.00 Slew = 0.01 Driver waveform slew = 0.01 ............................................. dcalc buf1 A->Z max: Library: NangateOpenCellLibrary Cell: BUF_X1 Arc sense: positive_unate Arc type: combinational A ^ -> Z ^ P = 1.00 V = 1.10 T = 25.00 ------- input_net_transition = 0.10 | total_output_net_capacitance = 1.70 | 0.37 1.90 v -------------------- 0.08 | 0.03 0.03 0.13 | 0.03 0.04 Table value = 0.03 PVT scale factor = 1.00 Delay = 0.03 ------- input_net_transition = 0.10 | total_output_net_capacitance = 1.70 | 0.37 1.90 v -------------------- 0.08 | 0.01 0.01 0.13 | 0.01 0.01 Table value = 0.01 PVT scale factor = 1.00 Slew = 0.01 Driver waveform slew = 0.01 ............................................. A v -> Z v P = 1.00 V = 1.10 T = 25.00 ------- input_net_transition = 0.10 | total_output_net_capacitance = 1.55 | 0.37 1.90 v -------------------- 0.08 | 0.05 0.05 0.13 | 0.06 0.07 Table value = 0.06 PVT scale factor = 1.00 Delay = 0.06 ------- input_net_transition = 0.10 | total_output_net_capacitance = 1.55 | 0.37 1.90 v -------------------- 0.08 | 0.01 0.01 0.13 | 0.01 0.01 Table value = 0.01 PVT scale factor = 1.00 Slew = 0.01 Driver waveform slew = 0.01 ............................................. dcalc buf1 A->Z min: Library: NangateOpenCellLibrary Cell: INV_X1 Arc sense: negative_unate Arc type: combinational A ^ -> ZN v P = 1.00 V = 1.10 T = 25.00 ------- input_net_transition = 0.01 | total_output_net_capacitance = 1.06 | 0.37 1.90 v -------------------- 0.00 | 0.00 0.01 0.02 | 0.01 0.01 Table value = 0.01 PVT scale factor = 1.00 Delay = 0.01 ------- input_net_transition = 0.01 | total_output_net_capacitance = 1.06 | 0.37 1.90 v -------------------- 0.00 | 0.00 0.00 0.02 | 0.00 0.01 Table value = 0.00 PVT scale factor = 1.00 Slew = 0.00 Driver waveform slew = 0.00 ............................................. A v -> ZN ^ P = 1.00 V = 1.10 T = 25.00 ------- input_net_transition = 0.01 | total_output_net_capacitance = 1.14 | 0.37 1.90 v -------------------- 0.00 | 0.01 0.01 0.02 | 0.01 0.02 Table value = 0.01 PVT scale factor = 1.00 Delay = 0.01 ------- input_net_transition = 0.01 | total_output_net_capacitance = 1.14 | 0.37 1.90 v -------------------- 0.00 | 0.00 0.01 0.02 | 0.01 0.01 Table value = 0.01 PVT scale factor = 1.00 Slew = 0.01 Driver waveform slew = 0.01 ............................................. dcalc inv1 A->ZN max: Library: NangateOpenCellLibrary Cell: INV_X1 Arc sense: negative_unate Arc type: combinational A ^ -> ZN v P = 1.00 V = 1.10 T = 25.00 ------- input_net_transition = 0.01 | total_output_net_capacitance = 1.06 | 0.37 1.90 v -------------------- 0.00 | 0.00 0.01 0.02 | 0.01 0.01 Table value = 0.01 PVT scale factor = 1.00 Delay = 0.01 ------- input_net_transition = 0.01 | total_output_net_capacitance = 1.06 | 0.37 1.90 v -------------------- 0.00 | 0.00 0.00 0.02 | 0.00 0.01 Table value = 0.00 PVT scale factor = 1.00 Slew = 0.00 Driver waveform slew = 0.00 ............................................. A v -> ZN ^ P = 1.00 V = 1.10 T = 25.00 ------- input_net_transition = 0.01 | total_output_net_capacitance = 1.14 | 0.37 1.90 v -------------------- 0.00 | 0.01 0.01 0.02 | 0.01 0.02 Table value = 0.01 PVT scale factor = 1.00 Delay = 0.01 ------- input_net_transition = 0.01 | total_output_net_capacitance = 1.14 | 0.37 1.90 v -------------------- 0.00 | 0.00 0.01 0.02 | 0.01 0.01 Table value = 0.01 PVT scale factor = 1.00 Slew = 0.01 Driver waveform slew = 0.01 ............................................. dcalc inv1 A->ZN min: Library: NangateOpenCellLibrary Cell: DFF_X1 Arc sense: non_unate Arc type: Reg Clk to Q CK ^ -> Q ^ P = 1.00 V = 1.10 T = 25.00 ------- input_net_transition = 0.00 | total_output_net_capacitance = 0.00 | 0.37 1.90 v -------------------- 0.00 | 0.08 0.09 0.00 | 0.08 0.09 Table value = 0.08 PVT scale factor = 1.00 Delay = 0.08 ------- input_net_transition = 0.00 | total_output_net_capacitance = 0.00 | 0.37 1.90 v -------------------- 0.00 | 0.01 0.01 0.00 | 0.01 0.01 Table value = 0.01 PVT scale factor = 1.00 Slew = 0.01 Driver waveform slew = 0.01 ............................................. CK ^ -> Q v P = 1.00 V = 1.10 T = 25.00 ------- input_net_transition = 0.00 | total_output_net_capacitance = 0.00 | 0.37 1.90 v -------------------- 0.00 | 0.08 0.08 0.00 | 0.08 0.08 Table value = 0.08 PVT scale factor = 1.00 Delay = 0.08 ------- input_net_transition = 0.00 | total_output_net_capacitance = 0.00 | 0.37 1.90 v -------------------- 0.00 | 0.01 0.01 0.00 | 0.01 0.01 Table value = 0.00 PVT scale factor = 1.00 Slew = 0.00 Driver waveform slew = 0.00 ............................................. dcalc reg1 CK->Q max: Library: NangateOpenCellLibrary Cell: DFF_X1 Arc sense: non_unate Arc type: Reg Clk to Q CK ^ -> Q ^ P = 1.00 V = 1.10 T = 25.00 ------- input_net_transition = 0.00 | total_output_net_capacitance = 0.00 | 0.37 1.90 v -------------------- 0.00 | 0.08 0.09 0.00 | 0.08 0.09 Table value = 0.08 PVT scale factor = 1.00 Delay = 0.08 ------- input_net_transition = 0.00 | total_output_net_capacitance = 0.00 | 0.37 1.90 v -------------------- 0.00 | 0.01 0.01 0.00 | 0.01 0.01 Table value = 0.01 PVT scale factor = 1.00 Slew = 0.01 Driver waveform slew = 0.01 ............................................. CK ^ -> Q v P = 1.00 V = 1.10 T = 25.00 ------- input_net_transition = 0.00 | total_output_net_capacitance = 0.00 | 0.37 1.90 v -------------------- 0.00 | 0.08 0.08 0.00 | 0.08 0.08 Table value = 0.08 PVT scale factor = 1.00 Delay = 0.08 ------- input_net_transition = 0.00 | total_output_net_capacitance = 0.00 | 0.37 1.90 v -------------------- 0.00 | 0.01 0.01 0.00 | 0.01 0.01 Table value = 0.00 PVT scale factor = 1.00 Slew = 0.00 Driver waveform slew = 0.00 ............................................. dcalc reg1 CK->Q min: Library: NangateOpenCellLibrary Cell: DFF_X1 Arc type: setup CK ^ -> D ^ P = 1.00 V = 1.10 T = 25.00 ------- constrained_pin_transition = 0.01 (ideal clock) | related_pin_transition = 0.00 | 0.00 0.04 v -------------------- 0.00 | 0.03 0.02 0.04 | 0.04 0.03 Table value = 0.03 PVT scale factor = 1.00 Check = 0.03 ............................................. CK ^ -> D v P = 1.00 V = 1.10 T = 25.00 ------- constrained_pin_transition = 0.00 (ideal clock) | related_pin_transition = 0.00 | 0.00 0.04 v -------------------- 0.00 | 0.04 0.02 0.04 | 0.05 0.04 Table value = 0.04 PVT scale factor = 1.00 Check = 0.04 ............................................. dcalc reg1 setup max: Library: NangateOpenCellLibrary Cell: DFF_X1 Arc type: hold CK ^ -> D ^ P = 1.00 V = 1.10 T = 25.00 ------- constrained_pin_transition = 0.01 (ideal clock) | related_pin_transition = 0.00 | 0.00 0.04 v -------------------- 0.00 | 0.00 0.02 0.04 | 0.02 0.03 Table value = 0.00 PVT scale factor = 1.00 Check = 0.00 ............................................. CK ^ -> D v P = 1.00 V = 1.10 T = 25.00 ------- constrained_pin_transition = 0.00 (ideal clock) | related_pin_transition = 0.00 | 0.00 0.04 v -------------------- 0.00 | 0.00 0.01 0.04 | 0.00 0.01 Table value = 0.00 PVT scale factor = 1.00 Check = 0.00 ............................................. dcalc reg1 hold min: Library: NangateOpenCellLibrary Cell: BUF_X1 Arc sense: positive_unate Arc type: combinational A ^ -> Z ^ P = 1.00000000 V = 1.10000002 T = 25.00000000 ------- input_net_transition = 0.09999999 | total_output_net_capacitance = 1.70023000 | 0.36561599 1.89542997 v -------------------- 0.07805960 | 0.02866950 0.03386810 0.13008100 | 0.02927760 0.03516290 Table value = 0.03371391 PVT scale factor = 1.00000000 Delay = 0.03371391 ------- input_net_transition = 0.09999999 | total_output_net_capacitance = 1.70023000 | 0.36561599 1.89542997 v -------------------- 0.07805960 | 0.00727015 0.00982049 0.13008100 | 0.00896521 0.01183550 Table value = 0.01032770 PVT scale factor = 1.00000000 Slew = 0.01032770 Driver waveform slew = 0.01032770 ............................................. A v -> Z v P = 1.00000000 V = 1.10000002 T = 25.00000000 ------- input_net_transition = 0.09999999 | total_output_net_capacitance = 1.54936004 | 0.36561599 1.89542997 v -------------------- 0.07805960 | 0.04971580 0.05386010 0.13008100 | 0.06178680 0.06635160 Table value = 0.05815085 PVT scale factor = 1.00000000 Delay = 0.05815085 ------- input_net_transition = 0.09999999 | total_output_net_capacitance = 1.54936004 | 0.36561599 1.89542997 v -------------------- 0.07805960 | 0.00743478 0.00888423 0.13008100 | 0.00930028 0.01081060 Table value = 0.00936299 PVT scale factor = 1.00000000 Slew = 0.00936299 Driver waveform slew = 0.00936299 ............................................. dcalc buf1 A->Z 8 digits: --- unit delay calculator --- No paths found. PASS: unit report_checks Startpoint: reg1 (rising edge-triggered flip-flop clocked by clk) Endpoint: out1 (output port clocked by clk) Path Group: clk Path Type: min Delay Time Description --------------------------------------------------------- 0.00 0.00 clock clk (rise edge) 0.00 0.00 clock network delay (ideal) 0.00 0.00 ^ reg1/CK (DFF_X1) 1.00 1.00 ^ reg1/Q (DFF_X1) 0.00 1.00 ^ out1 (out) 1.00 data arrival time 0.00 0.00 clock clk (rise edge) 0.00 0.00 clock network delay (ideal) 0.00 0.00 clock reconvergence pessimism 0.00 0.00 output external delay 0.00 data required time --------------------------------------------------------- 0.00 data required time -1.00 data arrival time --------------------------------------------------------- 1.00 slack (MET) PASS: unit min path Startpoint: in1 (input port clocked by clk) Endpoint: reg1 (rising edge-triggered flip-flop clocked by clk) Path Group: clk Path Type: max Delay Time Description --------------------------------------------------------- 0.00 0.00 clock clk (rise edge) 0.00 0.00 clock network delay (ideal) 0.00 0.00 v input external delay 0.00 0.00 v in1 (in) 1.00 1.00 v buf1/Z (BUF_X1) 1.00 2.00 ^ inv1/ZN (INV_X1) 0.00 2.00 ^ reg1/D (DFF_X1) 2.00 data arrival time 10.00 10.00 clock clk (rise edge) 0.00 10.00 clock network delay (ideal) 0.00 10.00 clock reconvergence pessimism 10.00 ^ reg1/CK (DFF_X1) -1.00 9.00 library setup time 9.00 data required time --------------------------------------------------------- 9.00 data required time -2.00 data arrival time --------------------------------------------------------- 7.00 slack (MET) PASS: unit max path Library: NangateOpenCellLibrary Cell: BUF_X1 Arc sense: positive_unate Arc type: combinational A ^ -> Z ^ Delay = 1.0 Slew = 0.0 ............................................. A v -> Z v Delay = 1.0 Slew = 0.0 ............................................. unit dcalc buf1: Library: NangateOpenCellLibrary Cell: INV_X1 Arc sense: negative_unate Arc type: combinational A ^ -> ZN v Delay = 1.0 Slew = 0.0 ............................................. A v -> ZN ^ Delay = 1.0 Slew = 0.0 ............................................. unit dcalc inv1: Library: NangateOpenCellLibrary Cell: DFF_X1 Arc sense: non_unate Arc type: Reg Clk to Q CK ^ -> Q ^ Delay = 1.0 Slew = 0.0 ............................................. CK ^ -> Q v Delay = 1.0 Slew = 0.0 ............................................. unit dcalc reg1 CK->Q: Library: NangateOpenCellLibrary Cell: DFF_X1 Arc type: setup CK ^ -> D ^ Check = 1.0 ............................................. CK ^ -> D v Check = 1.0 ............................................. unit dcalc reg1 setup: Startpoint: in1 (input port clocked by clk) Endpoint: reg1 (rising edge-triggered flip-flop clocked by clk) Path Group: clk Path Type: max Cap Slew Delay Time Description ----------------------------------------------------------------------- 0.00 0.00 0.00 clock clk (rise edge) 0.00 0.00 clock network delay (ideal) 0.00 0.00 v input external delay 0.88 0.10 0.00 0.00 v in1 (in) 1.55 0.00 1.00 1.00 v buf1/Z (BUF_X1) 1.14 0.00 1.00 2.00 ^ inv1/ZN (INV_X1) 0.00 0.00 2.00 ^ reg1/D (DFF_X1) 2.00 data arrival time 0.00 10.00 10.00 clock clk (rise edge) 0.00 10.00 clock network delay (ideal) 0.00 10.00 clock reconvergence pessimism 10.00 ^ reg1/CK (DFF_X1) -1.00 9.00 library setup time 9.00 data required time ----------------------------------------------------------------------- 9.00 data required time -2.00 data arrival time ----------------------------------------------------------------------- 7.00 slack (MET) PASS: unit with fields --- lumped_cap delay calculator --- No paths found. PASS: lumped_cap report_checks Library: NangateOpenCellLibrary Cell: BUF_X1 Arc sense: positive_unate Arc type: combinational A ^ -> Z ^ P = 1.00 V = 1.10 T = 25.00 ------- input_net_transition = 0.10 | total_output_net_capacitance = 1.70 | 0.37 1.90 v -------------------- 0.08 | 0.03 0.03 0.13 | 0.03 0.04 Table value = 0.03 PVT scale factor = 1.00 Delay = 0.03 ------- input_net_transition = 0.10 | total_output_net_capacitance = 1.70 | 0.37 1.90 v -------------------- 0.08 | 0.01 0.01 0.13 | 0.01 0.01 Table value = 0.01 PVT scale factor = 1.00 Slew = 0.01 ............................................. A v -> Z v P = 1.00 V = 1.10 T = 25.00 ------- input_net_transition = 0.10 | total_output_net_capacitance = 1.55 | 0.37 1.90 v -------------------- 0.08 | 0.05 0.05 0.13 | 0.06 0.07 Table value = 0.06 PVT scale factor = 1.00 Delay = 0.06 ------- input_net_transition = 0.10 | total_output_net_capacitance = 1.55 | 0.37 1.90 v -------------------- 0.08 | 0.01 0.01 0.13 | 0.01 0.01 Table value = 0.01 PVT scale factor = 1.00 Slew = 0.01 ............................................. lumped_cap dcalc buf1: Library: NangateOpenCellLibrary Cell: INV_X1 Arc sense: negative_unate Arc type: combinational A ^ -> ZN v P = 1.00 V = 1.10 T = 25.00 ------- input_net_transition = 0.01 | total_output_net_capacitance = 1.06 | 0.37 1.90 v -------------------- 0.00 | 0.00 0.01 0.02 | 0.01 0.01 Table value = 0.01 PVT scale factor = 1.00 Delay = 0.01 ------- input_net_transition = 0.01 | total_output_net_capacitance = 1.06 | 0.37 1.90 v -------------------- 0.00 | 0.00 0.00 0.02 | 0.00 0.01 Table value = 0.00 PVT scale factor = 1.00 Slew = 0.00 ............................................. A v -> ZN ^ P = 1.00 V = 1.10 T = 25.00 ------- input_net_transition = 0.01 | total_output_net_capacitance = 1.14 | 0.37 1.90 v -------------------- 0.00 | 0.01 0.01 0.02 | 0.01 0.02 Table value = 0.01 PVT scale factor = 1.00 Delay = 0.01 ------- input_net_transition = 0.01 | total_output_net_capacitance = 1.14 | 0.37 1.90 v -------------------- 0.00 | 0.00 0.01 0.02 | 0.01 0.01 Table value = 0.01 PVT scale factor = 1.00 Slew = 0.01 ............................................. lumped_cap dcalc inv1: Library: NangateOpenCellLibrary Cell: DFF_X1 Arc sense: non_unate Arc type: Reg Clk to Q CK ^ -> Q ^ P = 1.00 V = 1.10 T = 25.00 ------- input_net_transition = 0.00 | total_output_net_capacitance = 0.00 | 0.37 1.90 v -------------------- 0.00 | 0.08 0.09 0.00 | 0.08 0.09 Table value = 0.08 PVT scale factor = 1.00 Delay = 0.08 ------- input_net_transition = 0.00 | total_output_net_capacitance = 0.00 | 0.37 1.90 v -------------------- 0.00 | 0.01 0.01 0.00 | 0.01 0.01 Table value = 0.01 PVT scale factor = 1.00 Slew = 0.01 ............................................. CK ^ -> Q v P = 1.00 V = 1.10 T = 25.00 ------- input_net_transition = 0.00 | total_output_net_capacitance = 0.00 | 0.37 1.90 v -------------------- 0.00 | 0.08 0.08 0.00 | 0.08 0.08 Table value = 0.08 PVT scale factor = 1.00 Delay = 0.08 ------- input_net_transition = 0.00 | total_output_net_capacitance = 0.00 | 0.37 1.90 v -------------------- 0.00 | 0.01 0.01 0.00 | 0.01 0.01 Table value = 0.00 PVT scale factor = 1.00 Slew = 0.00 ............................................. lumped_cap dcalc reg1: Startpoint: in1 (input port clocked by clk) Endpoint: reg1 (rising edge-triggered flip-flop clocked by clk) Path Group: clk Path Type: max Cap Slew Delay Time Description ----------------------------------------------------------------------- 0.00 0.00 0.00 clock clk (rise edge) 0.00 0.00 clock network delay (ideal) 0.00 0.00 v input external delay 0.88 0.10 0.00 0.00 v in1 (in) 0.10 0.00 0.00 v buf1/A (BUF_X1) 1.55 0.01 0.06 0.06 v buf1/Z (BUF_X1) 0.01 0.00 0.06 v inv1/A (INV_X1) 1.14 0.01 0.01 0.07 ^ inv1/ZN (INV_X1) 0.01 0.00 0.07 ^ reg1/D (DFF_X1) 0.07 data arrival time 0.00 10.00 10.00 clock clk (rise edge) 0.00 10.00 clock network delay (ideal) 0.00 10.00 clock reconvergence pessimism 10.00 ^ reg1/CK (DFF_X1) -0.03 9.97 library setup time 9.97 data required time ----------------------------------------------------------------------- 9.97 data required time -0.07 data arrival time ----------------------------------------------------------------------- 9.90 slack (MET) PASS: lumped_cap with fields --- dmp_ceff_elmore delay calculator --- No paths found. PASS: dmp_ceff_elmore report_checks Library: NangateOpenCellLibrary Cell: BUF_X1 Arc sense: positive_unate Arc type: combinational A ^ -> Z ^ P = 1.00 V = 1.10 T = 25.00 ------- input_net_transition = 0.10 | total_output_net_capacitance = 1.70 | 0.37 1.90 v -------------------- 0.08 | 0.03 0.03 0.13 | 0.03 0.04 Table value = 0.03 PVT scale factor = 1.00 Delay = 0.03 ------- input_net_transition = 0.10 | total_output_net_capacitance = 1.70 | 0.37 1.90 v -------------------- 0.08 | 0.01 0.01 0.13 | 0.01 0.01 Table value = 0.01 PVT scale factor = 1.00 Slew = 0.01 Driver waveform slew = 0.01 ............................................. A v -> Z v P = 1.00 V = 1.10 T = 25.00 ------- input_net_transition = 0.10 | total_output_net_capacitance = 1.55 | 0.37 1.90 v -------------------- 0.08 | 0.05 0.05 0.13 | 0.06 0.07 Table value = 0.06 PVT scale factor = 1.00 Delay = 0.06 ------- input_net_transition = 0.10 | total_output_net_capacitance = 1.55 | 0.37 1.90 v -------------------- 0.08 | 0.01 0.01 0.13 | 0.01 0.01 Table value = 0.01 PVT scale factor = 1.00 Slew = 0.01 Driver waveform slew = 0.01 ............................................. dmp_ceff_elmore dcalc buf1: --- dmp_ceff_two_pole delay calculator --- No paths found. PASS: dmp_ceff_two_pole report_checks Startpoint: in1 (input port clocked by clk) Endpoint: reg1 (rising edge-triggered flip-flop clocked by clk) Path Group: clk Path Type: min Delay Time Description --------------------------------------------------------- 0.00 0.00 clock clk (rise edge) 0.00 0.00 clock network delay (ideal) 0.00 0.00 ^ input external delay 0.00 0.00 ^ in1 (in) 0.03 0.03 ^ buf1/Z (BUF_X1) 0.01 0.04 v inv1/ZN (INV_X1) 0.00 0.04 v reg1/D (DFF_X1) 0.04 data arrival time 0.00 0.00 clock clk (rise edge) 0.00 0.00 clock network delay (ideal) 0.00 0.00 clock reconvergence pessimism 0.00 ^ reg1/CK (DFF_X1) 0.00 0.00 library hold time 0.00 data required time --------------------------------------------------------- 0.00 data required time -0.04 data arrival time --------------------------------------------------------- 0.04 slack (MET) PASS: dmp_ceff_two_pole min path Startpoint: in1 (input port clocked by clk) Endpoint: reg1 (rising edge-triggered flip-flop clocked by clk) Path Group: clk Path Type: max Delay Time Description --------------------------------------------------------- 0.00 0.00 clock clk (rise edge) 0.00 0.00 clock network delay (ideal) 0.00 0.00 v input external delay 0.00 0.00 v in1 (in) 0.06 0.06 v buf1/Z (BUF_X1) 0.01 0.07 ^ inv1/ZN (INV_X1) 0.00 0.07 ^ reg1/D (DFF_X1) 0.07 data arrival time 10.00 10.00 clock clk (rise edge) 0.00 10.00 clock network delay (ideal) 0.00 10.00 clock reconvergence pessimism 10.00 ^ reg1/CK (DFF_X1) -0.03 9.97 library setup time 9.97 data required time --------------------------------------------------------- 9.97 data required time -0.07 data arrival time --------------------------------------------------------- 9.90 slack (MET) PASS: dmp_ceff_two_pole max path Library: NangateOpenCellLibrary Cell: BUF_X1 Arc sense: positive_unate Arc type: combinational A ^ -> Z ^ P = 1.00 V = 1.10 T = 25.00 ------- input_net_transition = 0.10 | total_output_net_capacitance = 1.70 | 0.37 1.90 v -------------------- 0.08 | 0.03 0.03 0.13 | 0.03 0.04 Table value = 0.03 PVT scale factor = 1.00 Delay = 0.03 ------- input_net_transition = 0.10 | total_output_net_capacitance = 1.70 | 0.37 1.90 v -------------------- 0.08 | 0.01 0.01 0.13 | 0.01 0.01 Table value = 0.01 PVT scale factor = 1.00 Slew = 0.01 Driver waveform slew = 0.01 ............................................. A v -> Z v P = 1.00 V = 1.10 T = 25.00 ------- input_net_transition = 0.10 | total_output_net_capacitance = 1.55 | 0.37 1.90 v -------------------- 0.08 | 0.05 0.05 0.13 | 0.06 0.07 Table value = 0.06 PVT scale factor = 1.00 Delay = 0.06 ------- input_net_transition = 0.10 | total_output_net_capacitance = 1.55 | 0.37 1.90 v -------------------- 0.08 | 0.01 0.01 0.13 | 0.01 0.01 Table value = 0.01 PVT scale factor = 1.00 Slew = 0.01 Driver waveform slew = 0.01 ............................................. dmp_ceff_two_pole dcalc buf1 max: Library: NangateOpenCellLibrary Cell: BUF_X1 Arc sense: positive_unate Arc type: combinational A ^ -> Z ^ P = 1.00 V = 1.10 T = 25.00 ------- input_net_transition = 0.10 | total_output_net_capacitance = 1.70 | 0.37 1.90 v -------------------- 0.08 | 0.03 0.03 0.13 | 0.03 0.04 Table value = 0.03 PVT scale factor = 1.00 Delay = 0.03 ------- input_net_transition = 0.10 | total_output_net_capacitance = 1.70 | 0.37 1.90 v -------------------- 0.08 | 0.01 0.01 0.13 | 0.01 0.01 Table value = 0.01 PVT scale factor = 1.00 Slew = 0.01 Driver waveform slew = 0.01 ............................................. A v -> Z v P = 1.00 V = 1.10 T = 25.00 ------- input_net_transition = 0.10 | total_output_net_capacitance = 1.55 | 0.37 1.90 v -------------------- 0.08 | 0.05 0.05 0.13 | 0.06 0.07 Table value = 0.06 PVT scale factor = 1.00 Delay = 0.06 ------- input_net_transition = 0.10 | total_output_net_capacitance = 1.55 | 0.37 1.90 v -------------------- 0.08 | 0.01 0.01 0.13 | 0.01 0.01 Table value = 0.01 PVT scale factor = 1.00 Slew = 0.01 Driver waveform slew = 0.01 ............................................. dmp_ceff_two_pole dcalc buf1 min: Library: NangateOpenCellLibrary Cell: INV_X1 Arc sense: negative_unate Arc type: combinational A ^ -> ZN v P = 1.00 V = 1.10 T = 25.00 ------- input_net_transition = 0.01 | total_output_net_capacitance = 1.06 | 0.37 1.90 v -------------------- 0.00 | 0.00 0.01 0.02 | 0.01 0.01 Table value = 0.01 PVT scale factor = 1.00 Delay = 0.01 ------- input_net_transition = 0.01 | total_output_net_capacitance = 1.06 | 0.37 1.90 v -------------------- 0.00 | 0.00 0.00 0.02 | 0.00 0.01 Table value = 0.00 PVT scale factor = 1.00 Slew = 0.00 Driver waveform slew = 0.00 ............................................. A v -> ZN ^ P = 1.00 V = 1.10 T = 25.00 ------- input_net_transition = 0.01 | total_output_net_capacitance = 1.14 | 0.37 1.90 v -------------------- 0.00 | 0.01 0.01 0.02 | 0.01 0.02 Table value = 0.01 PVT scale factor = 1.00 Delay = 0.01 ------- input_net_transition = 0.01 | total_output_net_capacitance = 1.14 | 0.37 1.90 v -------------------- 0.00 | 0.00 0.01 0.02 | 0.01 0.01 Table value = 0.01 PVT scale factor = 1.00 Slew = 0.01 Driver waveform slew = 0.01 ............................................. dmp_ceff_two_pole dcalc inv1: Library: NangateOpenCellLibrary Cell: DFF_X1 Arc sense: non_unate Arc type: Reg Clk to Q CK ^ -> Q ^ P = 1.00 V = 1.10 T = 25.00 ------- input_net_transition = 0.00 | total_output_net_capacitance = 0.00 | 0.37 1.90 v -------------------- 0.00 | 0.08 0.09 0.00 | 0.08 0.09 Table value = 0.08 PVT scale factor = 1.00 Delay = 0.08 ------- input_net_transition = 0.00 | total_output_net_capacitance = 0.00 | 0.37 1.90 v -------------------- 0.00 | 0.01 0.01 0.00 | 0.01 0.01 Table value = 0.01 PVT scale factor = 1.00 Slew = 0.01 Driver waveform slew = 0.01 ............................................. CK ^ -> Q v P = 1.00 V = 1.10 T = 25.00 ------- input_net_transition = 0.00 | total_output_net_capacitance = 0.00 | 0.37 1.90 v -------------------- 0.00 | 0.08 0.08 0.00 | 0.08 0.08 Table value = 0.08 PVT scale factor = 1.00 Delay = 0.08 ------- input_net_transition = 0.00 | total_output_net_capacitance = 0.00 | 0.37 1.90 v -------------------- 0.00 | 0.01 0.01 0.00 | 0.01 0.01 Table value = 0.00 PVT scale factor = 1.00 Slew = 0.00 Driver waveform slew = 0.00 ............................................. dmp_ceff_two_pole dcalc reg1 CK->Q: Library: NangateOpenCellLibrary Cell: DFF_X1 Arc type: setup CK ^ -> D ^ P = 1.00 V = 1.10 T = 25.00 ------- constrained_pin_transition = 0.01 (ideal clock) | related_pin_transition = 0.00 | 0.00 0.04 v -------------------- 0.00 | 0.03 0.02 0.04 | 0.04 0.03 Table value = 0.03 PVT scale factor = 1.00 Check = 0.03 ............................................. CK ^ -> D v P = 1.00 V = 1.10 T = 25.00 ------- constrained_pin_transition = 0.00 (ideal clock) | related_pin_transition = 0.00 | 0.00 0.04 v -------------------- 0.00 | 0.04 0.02 0.04 | 0.05 0.04 Table value = 0.04 PVT scale factor = 1.00 Check = 0.04 ............................................. dmp_ceff_two_pole dcalc reg1 setup: Startpoint: in1 (input port clocked by clk) Endpoint: reg1 (rising edge-triggered flip-flop clocked by clk) Path Group: clk Path Type: max Cap Slew Delay Time Description ----------------------------------------------------------------------- 0.00 0.00 0.00 clock clk (rise edge) 0.00 0.00 clock network delay (ideal) 0.00 0.00 v input external delay 0.88 0.10 0.00 0.00 v in1 (in) 0.10 0.00 0.00 v buf1/A (BUF_X1) 1.55 0.01 0.06 0.06 v buf1/Z (BUF_X1) 0.01 0.00 0.06 v inv1/A (INV_X1) 1.14 0.01 0.01 0.07 ^ inv1/ZN (INV_X1) 0.01 0.00 0.07 ^ reg1/D (DFF_X1) 0.07 data arrival time 0.00 10.00 10.00 clock clk (rise edge) 0.00 10.00 clock network delay (ideal) 0.00 10.00 clock reconvergence pessimism 10.00 ^ reg1/CK (DFF_X1) -0.03 9.97 library setup time 9.97 data required time ----------------------------------------------------------------------- 9.97 data required time -0.07 data arrival time ----------------------------------------------------------------------- 9.90 slack (MET) PASS: dmp_ceff_two_pole with fields ALL PASSED