--- report_checks baseline ---
Startpoint: in1 (input port clocked by clk)
Endpoint: reg2 (rising edge-triggered flip-flop clocked by clk)
Path Group: clk
Path Type: max

  Delay    Time   Description
---------------------------------------------------------
   0.00    0.00   clock clk (rise edge)
   0.00    0.00   clock network delay (ideal)
   1.00    1.00 v input external delay
   0.00    1.00 v in1 (in)
   0.06    1.06 v buf1/Z (BUF_X1)
   0.04    1.10 v or1/ZN (OR2_X1)
   0.00    1.10 v reg2/D (DFF_X1)
           1.10   data arrival time

  10.00   10.00   clock clk (rise edge)
   0.00   10.00   clock network delay (ideal)
   0.00   10.00   clock reconvergence pessimism
          10.00 ^ reg2/CK (DFF_X1)
  -0.04    9.96   library setup time
           9.96   data required time
---------------------------------------------------------
           9.96   data required time
          -1.10   data arrival time
---------------------------------------------------------
           8.86   slack (MET)