=== Part 1: Latch paths === --- Latch report -format json --- {"checks": [ { "type": "latch_check", "path_group": "clk", "path_type": "max", "startpoint": "latch1/Q", "endpoint": "latch2/D", "source_clock": "clk", "source_clock_edge": "rise", "source_clock_path": [ { "instance": "", "cell": "search_latch", "verilog_src": "", "pin": "clk", "arrival": 0.000e+00, "capacitance": 2.921e-15, "slew": 0.000e+00 }, { "instance": "latch1", "cell": "DLH_X1", "verilog_src": "", "pin": "latch1/G", "net": "clk", "arrival": 0.000e+00, "slew": 0.000e+00 } ], "source_path": [ { "instance": "latch1", "cell": "DLH_X1", "verilog_src": "", "pin": "latch1/Q", "net": "n3", "arrival": 1.106e-09, "capacitance": 1.932e-15, "slew": 1.074e-11 }, { "instance": "latch2", "cell": "DLH_X1", "verilog_src": "", "pin": "latch2/D", "net": "n3", "arrival": 1.106e-09, "slew": 1.074e-11 } ], "target_clock": "clk", "target_clock_edge": "rise", "target_clock_path": [ { "instance": "", "cell": "search_latch", "verilog_src": "", "pin": "clk", "arrival": 0.000e+00, "capacitance": 2.921e-15, "slew": 0.000e+00 }, { "instance": "latch2", "cell": "DLH_X1", "verilog_src": "", "pin": "latch2/G", "net": "clk", "arrival": 0.000e+00, "slew": 0.000e+00 } ], "data_arrival_time": 1.106e-09, "crpr": 0.000e+00, "margin": 5.497e-11, "required_time": 1.106e-09, "slack": 0.000e+00 } ] } {"checks": [ { "type": "check", "path_group": "clk", "path_type": "min", "startpoint": "latch1/Q", "endpoint": "reg1/D", "source_clock": "clk", "source_clock_edge": "rise", "source_clock_path": [ { "instance": "", "cell": "search_latch", "verilog_src": "", "pin": "clk", "arrival": 0.000e+00, "capacitance": 2.921e-15, "slew": 0.000e+00 }, { "instance": "latch1", "cell": "DLH_X1", "verilog_src": "", "pin": "latch1/G", "net": "clk", "arrival": 0.000e+00, "slew": 0.000e+00 } ], "source_path": [ { "instance": "latch1", "cell": "DLH_X1", "verilog_src": "", "pin": "latch1/Q", "net": "n3", "arrival": 5.291e-11, "capacitance": 2.054e-15, "slew": 9.761e-12 }, { "instance": "reg1", "cell": "DFF_X1", "verilog_src": "", "pin": "reg1/D", "net": "n3", "arrival": 5.291e-11, "slew": 9.761e-12 } ], "target_clock": "clk", "target_clock_edge": "rise", "target_clock_path": [ { "instance": "", "cell": "search_latch", "verilog_src": "", "pin": "clk", "arrival": 0.000e+00, "capacitance": 2.921e-15, "slew": 0.000e+00 }, { "instance": "reg1", "cell": "DFF_X1", "verilog_src": "", "pin": "reg1/CK", "net": "clk", "arrival": 0.000e+00, "slew": 0.000e+00 } ], "data_arrival_time": 5.291e-11, "crpr": 0.000e+00, "margin": 6.024e-12, "required_time": 6.024e-12, "slack": 4.688e-11 } ] } --- Latch report -format full_clock_expanded --- Startpoint: latch1 (positive level-sensitive latch clocked by clk) Endpoint: latch2 (positive level-sensitive latch clocked by clk) Path Group: clk Path Type: max Delay Time Description --------------------------------------------------------- 0.00 0.00 clock clk (rise edge) 0.00 0.00 clock network delay (ideal) 1.05 1.05 time given to startpoint 0.00 1.05 v latch1/D (DLH_X1) 0.06 1.11 v latch1/Q (DLH_X1) 0.00 1.11 v latch2/D (DLH_X1) 1.11 data arrival time 0.00 0.00 clock clk (rise edge) 0.00 0.00 clock network delay (ideal) 0.00 0.00 clock reconvergence pessimism 0.00 ^ latch2/G (DLH_X1) 1.11 1.11 time borrowed from endpoint 1.11 data required time --------------------------------------------------------- 1.11 data required time -1.11 data arrival time --------------------------------------------------------- 0.00 slack (MET) Time Borrowing Information -------------------------------------------- clk pulse width 5.00 library setup time -0.05 -------------------------------------------- max time borrow 4.95 actual time borrow 1.11 -------------------------------------------- Startpoint: latch1 (positive level-sensitive latch clocked by clk) Endpoint: reg1 (rising edge-triggered flip-flop clocked by clk) Path Group: clk Path Type: min Delay Time Description --------------------------------------------------------- 0.00 0.00 clock clk (rise edge) 0.00 0.00 clock network delay (ideal) 0.00 0.00 ^ latch1/G (DLH_X1) 0.05 0.05 ^ latch1/Q (DLH_X1) 0.00 0.05 ^ reg1/D (DFF_X1) 0.05 data arrival time 0.00 0.00 clock clk (rise edge) 0.00 0.00 clock network delay (ideal) 0.00 0.00 clock reconvergence pessimism 0.00 ^ reg1/CK (DFF_X1) 0.01 0.01 library hold time 0.01 data required time --------------------------------------------------------- 0.01 data required time -0.05 data arrival time --------------------------------------------------------- 0.05 slack (MET) --- Latch report -format full_clock --- Startpoint: latch1 (positive level-sensitive latch clocked by clk) Endpoint: latch2 (positive level-sensitive latch clocked by clk) Path Group: clk Path Type: max Delay Time Description --------------------------------------------------------- 0.00 0.00 clock clk (rise edge) 0.00 0.00 clock network delay (ideal) 1.05 1.05 time given to startpoint 0.00 1.05 v latch1/D (DLH_X1) 0.06 1.11 v latch1/Q (DLH_X1) 0.00 1.11 v latch2/D (DLH_X1) 1.11 data arrival time 0.00 0.00 clock clk (rise edge) 0.00 0.00 clock network delay (ideal) 0.00 0.00 clock reconvergence pessimism 0.00 ^ latch2/G (DLH_X1) 1.11 1.11 time borrowed from endpoint 1.11 data required time --------------------------------------------------------- 1.11 data required time -1.11 data arrival time --------------------------------------------------------- 0.00 slack (MET) Time Borrowing Information -------------------------------------------- clk pulse width 5.00 library setup time -0.05 -------------------------------------------- max time borrow 4.95 actual time borrow 1.11 -------------------------------------------- Startpoint: latch1 (positive level-sensitive latch clocked by clk) Endpoint: reg1 (rising edge-triggered flip-flop clocked by clk) Path Group: clk Path Type: min Delay Time Description --------------------------------------------------------- 0.00 0.00 clock clk (rise edge) 0.00 0.00 clock network delay (ideal) 0.00 0.00 ^ latch1/G (DLH_X1) 0.05 0.05 ^ latch1/Q (DLH_X1) 0.00 0.05 ^ reg1/D (DFF_X1) 0.05 data arrival time 0.00 0.00 clock clk (rise edge) 0.00 0.00 clock network delay (ideal) 0.00 0.00 clock reconvergence pessimism 0.00 ^ reg1/CK (DFF_X1) 0.01 0.01 library hold time 0.01 data required time --------------------------------------------------------- 0.01 data required time -0.05 data arrival time --------------------------------------------------------- 0.05 slack (MET) --- Latch report -format full --- Startpoint: latch1 (positive level-sensitive latch clocked by clk) Endpoint: latch2 (positive level-sensitive latch clocked by clk) Path Group: clk Path Type: max Delay Time Description --------------------------------------------------------- 0.00 0.00 clock clk (rise edge) 0.00 0.00 clock network delay (ideal) 1.05 1.05 time given to startpoint 0.00 1.05 v latch1/D (DLH_X1) 0.06 1.11 v latch1/Q (DLH_X1) 0.00 1.11 v latch2/D (DLH_X1) 1.11 data arrival time 0.00 0.00 clock clk (rise edge) 0.00 0.00 clock network delay (ideal) 0.00 0.00 clock reconvergence pessimism 0.00 ^ latch2/G (DLH_X1) 1.11 1.11 time borrowed from endpoint 1.11 data required time --------------------------------------------------------- 1.11 data required time -1.11 data arrival time --------------------------------------------------------- 0.00 slack (MET) Time Borrowing Information -------------------------------------------- clk pulse width 5.00 library setup time -0.05 -------------------------------------------- max time borrow 4.95 actual time borrow 1.11 -------------------------------------------- --- Latch report -format short --- Startpoint: latch1 (positive level-sensitive latch clocked by clk) Endpoint: latch2 (positive level-sensitive latch clocked by clk) Path Group: clk Path Type: max --- Latch report -format end --- max_delay/setup group clk Required Actual Endpoint Delay Delay Slack ------------------------------------------------------------ latch2/D (DLH_X1) 1.11 1.11 0.00 (MET) min_delay/hold group clk Required Actual Endpoint Delay Delay Slack ------------------------------------------------------------ reg1/D (DFF_X1) 0.01 0.05 0.05 (MET) --- Latch report -format summary --- Startpoint Endpoint Slack -------------------------------------------------------------------------------- latch1/Q (DLH_X1) latch2/D (DLH_X1) 0.00 Startpoint Endpoint Slack -------------------------------------------------------------------------------- latch1/Q (DFF_X1) reg1/D (DFF_X1) 0.05 --- Latch report -format slack_only --- Group Slack -------------------------------------------- clk 0.00 Group Slack -------------------------------------------- clk 0.05 --- Latch find_timing_paths PathEnd queries --- Warning 502: search_report_json_formats.tcl line 1, find_timing_paths -endpoint_count is deprecated. Use -endpoint_path_count instead. Found 10 max paths check=0 latch=1 out=0 gated=0 data=0 unconst=0 role=latch setup margin=5.49663405069456e-11 req=1.106064906331028e-9 arr=1.106064906331028e-9 target_clk=clk target_clk_delay=0.0 clk_skew=0.0 check=0 latch=1 out=0 gated=0 data=0 unconst=0 role=latch setup margin=1.631178005168099e-11 req=1.081046252515705e-9 arr=1.081046252515705e-9 target_clk=clk target_clk_delay=0.0 clk_skew=0.0 check=0 latch=1 out=0 gated=0 data=0 unconst=0 role=latch setup margin=5.264827462880817e-11 req=1.0477667622410536e-9 arr=1.0477667622410536e-9 target_clk=clk target_clk_delay=0.0 clk_skew=0.0 check=0 latch=1 out=0 gated=0 data=0 unconst=0 role=latch setup margin=5.264827462880817e-11 req=1.0455454280133836e-9 arr=1.0455454280133836e-9 target_clk=clk target_clk_delay=0.0 clk_skew=0.0 check=0 latch=1 out=0 gated=0 data=0 unconst=0 role=latch setup margin=1.5100346320573443e-11 req=1.044742847788882e-9 arr=1.044742847788882e-9 target_clk=clk target_clk_delay=0.0 clk_skew=0.0 check=0 latch=1 out=0 gated=0 data=0 unconst=0 role=latch setup margin=1.5100346320573443e-11 req=1.0434519914781504e-9 arr=1.0434519914781504e-9 target_clk=clk target_clk_delay=0.0 clk_skew=0.0 check=0 latch=1 out=0 gated=0 data=0 unconst=0 role=latch setup margin=5.49663405069456e-11 req=5.6313842478061815e-11 arr=5.6313842478061815e-11 target_clk=clk target_clk_delay=0.0 clk_skew=0.0 check=0 latch=1 out=0 gated=0 data=0 unconst=0 role=latch setup margin=1.631178005168099e-11 req=5.290530860624365e-11 arr=5.290530860624365e-11 target_clk=clk target_clk_delay=0.0 clk_skew=0.0 check=0 latch=0 out=1 gated=0 data=0 unconst=0 role=output setup margin=1.999999943436137e-9 req=7.999999773744548e-9 arr=1.1867781202212768e-9 target_clk=clk target_clk_delay=0.0 clk_skew=0.0 check=0 latch=0 out=1 gated=0 data=0 unconst=0 role=output setup margin=1.999999943436137e-9 req=7.999999773744548e-9 arr=1.1316151349305414e-9 target_clk=clk target_clk_delay=0.0 clk_skew=0.0 --- Latch report with fields --- Startpoint: latch1 (positive level-sensitive latch clocked by clk) Endpoint: latch2 (positive level-sensitive latch clocked by clk) Path Group: clk Path Type: max Fanout Cap Slew Delay Time Description ----------------------------------------------------------------------------- 0.00 0.00 0.00 clock clk (rise edge) 0.00 0.00 clock network delay (ideal) 1.05 1.05 time given to startpoint 0.00 0.00 1.05 v latch1/D (DLH_X1) 2 1.93 0.01 0.06 1.11 v latch1/Q (DLH_X1) 0.01 0.00 1.11 v latch2/D (DLH_X1) 1.11 data arrival time 0.00 0.00 0.00 clock clk (rise edge) 0.00 0.00 clock network delay (ideal) 0.00 0.00 clock reconvergence pessimism 0.00 ^ latch2/G (DLH_X1) 1.11 1.11 time borrowed from endpoint 1.11 data required time ----------------------------------------------------------------------------- 1.11 data required time -1.11 data arrival time ----------------------------------------------------------------------------- 0.00 slack (MET) Time Borrowing Information -------------------------------------------- clk pulse width 5.00 library setup time -0.05 -------------------------------------------- max time borrow 4.95 actual time borrow 1.11 -------------------------------------------- --- Latch to specific endpoints --- Startpoint: latch2 (positive level-sensitive latch clocked by clk) Endpoint: out1 (output port clocked by clk) Path Group: clk Path Type: max Delay Time Description --------------------------------------------------------- 0.00 0.00 clock clk (rise edge) 0.00 0.00 clock network delay (ideal) 1.11 1.11 time given to startpoint 0.00 1.11 v latch2/D (DLH_X1) 0.06 1.16 v latch2/Q (DLH_X1) 0.02 1.19 v buf2/Z (BUF_X1) 0.00 1.19 v out1 (out) 1.19 data arrival time 10.00 10.00 clock clk (rise edge) 0.00 10.00 clock network delay (ideal) 0.00 10.00 clock reconvergence pessimism -2.00 8.00 output external delay 8.00 data required time --------------------------------------------------------- 8.00 data required time -1.19 data arrival time --------------------------------------------------------- 6.81 slack (MET) Startpoint: reg1 (rising edge-triggered flip-flop clocked by clk) Endpoint: out2 (output port clocked by clk) Path Group: clk Path Type: max Delay Time Description --------------------------------------------------------- 0.00 0.00 clock clk (rise edge) 0.00 0.00 clock network delay (ideal) 0.00 0.00 ^ reg1/CK (DFF_X1) 0.08 0.08 ^ reg1/Q (DFF_X1) 0.02 0.10 ^ buf3/Z (BUF_X1) 0.00 0.10 ^ out2 (out) 0.10 data arrival time 10.00 10.00 clock clk (rise edge) 0.00 10.00 clock network delay (ideal) 0.00 10.00 clock reconvergence pessimism -2.00 8.00 output external delay 8.00 data required time --------------------------------------------------------- 8.00 data required time -0.10 data arrival time --------------------------------------------------------- 7.90 slack (MET) === Part 2: Gated clock paths === --- Gated clock report -format json --- {"checks": [ { "type": "gated_clk", "path_group": "gated clock", "path_type": "max", "startpoint": "en", "endpoint": "clk_gate/A2", "source_clock": "clk", "source_clock_edge": "rise", "source_path": [ { "instance": "", "cell": "search_gated_clk", "verilog_src": "", "pin": "en", "arrival": 5.000e-10, "capacitance": 9.746e-16, "slew": 0.000e+00 }, { "instance": "clk_gate", "cell": "AND2_X1", "verilog_src": "", "pin": "clk_gate/A2", "net": "en", "arrival": 5.000e-10, "slew": 0.000e+00 } ], "target_clock": "clk", "target_clock_edge": "rise", "target_clock_path": [ { "instance": "", "cell": "search_gated_clk", "verilog_src": "", "pin": "clk", "arrival": 0.000e+00, "capacitance": 9.181e-16, "slew": 0.000e+00 }, { "instance": "clk_gate", "cell": "AND2_X1", "verilog_src": "", "pin": "clk_gate/A1", "net": "clk", "arrival": 0.000e+00, "slew": 0.000e+00 } ], "data_arrival_time": 5.000e-10, "crpr": 0.000e+00, "margin": 0.000e+00, "required_time": 1.000e-08, "slack": 9.500e-09 }, { "type": "output_delay", "path_group": "clk", "path_type": "max", "startpoint": "reg1/Q", "endpoint": "out1", "source_clock": "clk", "source_clock_edge": "rise", "source_clock_path": [ { "instance": "", "cell": "search_gated_clk", "verilog_src": "", "pin": "clk", "arrival": 0.000e+00, "capacitance": 9.181e-16, "slew": 0.000e+00 }, { "instance": "clk_gate", "cell": "AND2_X1", "verilog_src": "", "pin": "clk_gate/A1", "net": "clk", "arrival": 0.000e+00, "slew": 0.000e+00 }, { "instance": "clk_gate", "cell": "AND2_X1", "verilog_src": "", "pin": "clk_gate/ZN", "net": "gated_clk", "arrival": 2.441e-11, "capacitance": 9.497e-16, "slew": 6.948e-12 }, { "instance": "reg1", "cell": "DFF_X1", "verilog_src": "", "pin": "reg1/CK", "net": "gated_clk", "arrival": 2.441e-11, "slew": 6.948e-12 } ], "source_path": [ { "instance": "reg1", "cell": "DFF_X1", "verilog_src": "", "pin": "reg1/Q", "net": "n2", "arrival": 8.371e-11, "capacitance": 9.747e-16, "slew": 7.314e-12 }, { "instance": "buf2", "cell": "BUF_X1", "verilog_src": "", "pin": "buf2/A", "net": "n2", "arrival": 8.371e-11, "slew": 7.314e-12 }, { "instance": "buf2", "cell": "BUF_X1", "verilog_src": "", "pin": "buf2/Z", "net": "out1", "arrival": 1.003e-10, "capacitance": 0.000e+00, "slew": 3.638e-12 }, { "instance": "", "cell": "search_gated_clk", "verilog_src": "", "pin": "out1", "arrival": 1.003e-10, "slew": 3.638e-12 } ], "target_clock": "clk", "target_clock_edge": "rise", "data_arrival_time": 1.003e-10, "crpr": 0.000e+00, "margin": 2.000e-09, "required_time": 8.000e-09, "slack": 7.900e-09 } ] } {"checks": [ { "type": "gated_clk", "path_group": "gated clock", "path_type": "min", "startpoint": "en", "endpoint": "clk_gate/A2", "source_clock": "clk", "source_clock_edge": "rise", "source_path": [ { "instance": "", "cell": "search_gated_clk", "verilog_src": "", "pin": "en", "arrival": 5.000e-10, "capacitance": 9.746e-16, "slew": 0.000e+00 }, { "instance": "clk_gate", "cell": "AND2_X1", "verilog_src": "", "pin": "clk_gate/A2", "net": "en", "arrival": 5.000e-10, "slew": 0.000e+00 } ], "target_clock": "clk", "target_clock_edge": "fall", "target_clock_path": [ { "instance": "", "cell": "search_gated_clk", "verilog_src": "", "pin": "clk", "arrival": 5.000e-09, "capacitance": 8.748e-16, "slew": 0.000e+00 }, { "instance": "clk_gate", "cell": "AND2_X1", "verilog_src": "", "pin": "clk_gate/A1", "net": "clk", "arrival": 5.000e-09, "slew": 0.000e+00 } ], "data_arrival_time": 5.000e-10, "crpr": 0.000e+00, "margin": 0.000e+00, "required_time": 5.000e-09, "slack": -4.500e-09 }, { "type": "check", "path_group": "clk", "path_type": "min", "startpoint": "in1", "endpoint": "reg1/D", "source_clock": "clk", "source_clock_edge": "rise", "source_path": [ { "instance": "", "cell": "search_gated_clk", "verilog_src": "", "pin": "in1", "arrival": 1.000e-09, "capacitance": 9.747e-16, "slew": 0.000e+00 }, { "instance": "buf1", "cell": "BUF_X1", "verilog_src": "", "pin": "buf1/A", "net": "in1", "arrival": 1.000e-09, "slew": 0.000e+00 }, { "instance": "buf1", "cell": "BUF_X1", "verilog_src": "", "pin": "buf1/Z", "net": "n1", "arrival": 1.017e-09, "capacitance": 1.140e-15, "slew": 5.905e-12 }, { "instance": "reg1", "cell": "DFF_X1", "verilog_src": "", "pin": "reg1/D", "net": "n1", "arrival": 1.017e-09, "slew": 5.905e-12 } ], "target_clock": "clk", "target_clock_edge": "rise", "target_clock_path": [ { "instance": "", "cell": "search_gated_clk", "verilog_src": "", "pin": "clk", "arrival": 0.000e+00, "capacitance": 9.181e-16, "slew": 0.000e+00 }, { "instance": "clk_gate", "cell": "AND2_X1", "verilog_src": "", "pin": "clk_gate/A1", "net": "clk", "arrival": 0.000e+00, "slew": 0.000e+00 }, { "instance": "clk_gate", "cell": "AND2_X1", "verilog_src": "", "pin": "clk_gate/ZN", "net": "gated_clk", "arrival": 2.441e-11, "capacitance": 9.497e-16, "slew": 6.948e-12 }, { "instance": "reg1", "cell": "DFF_X1", "verilog_src": "", "pin": "reg1/CK", "net": "gated_clk", "arrival": 2.441e-11, "slew": 6.948e-12 } ], "data_arrival_time": 1.017e-09, "crpr": 0.000e+00, "margin": 4.881e-12, "required_time": 4.881e-12, "slack": 1.012e-09 } ] } --- Gated clock report -format full_clock_expanded --- Startpoint: en (input port clocked by clk) Endpoint: clk_gate (rising clock gating-check end-point clocked by clk) Path Group: gated clock Path Type: max Delay Time Description --------------------------------------------------------- 0.00 0.00 clock clk (rise edge) 0.00 0.00 clock network delay (ideal) 0.50 0.50 ^ input external delay 0.00 0.50 ^ en (in) 0.00 0.50 ^ clk_gate/A2 (AND2_X1) 0.50 data arrival time 10.00 10.00 clock clk (rise edge) 0.00 10.00 clock network delay (ideal) 0.00 10.00 clock reconvergence pessimism 10.00 ^ clk_gate/A1 (AND2_X1) 0.00 10.00 clock gating setup time 10.00 data required time --------------------------------------------------------- 10.00 data required time -0.50 data arrival time --------------------------------------------------------- 9.50 slack (MET) Startpoint: reg1 (rising edge-triggered flip-flop clocked by clk) Endpoint: out1 (output port clocked by clk) Path Group: clk Path Type: max Delay Time Description --------------------------------------------------------- 0.00 0.00 clock clk (rise edge) 0.00 0.00 clock network delay (ideal) 0.00 0.00 ^ reg1/CK (DFF_X1) 0.08 0.08 ^ reg1/Q (DFF_X1) 0.02 0.10 ^ buf2/Z (BUF_X1) 0.00 0.10 ^ out1 (out) 0.10 data arrival time 10.00 10.00 clock clk (rise edge) 0.00 10.00 clock network delay (ideal) 0.00 10.00 clock reconvergence pessimism -2.00 8.00 output external delay 8.00 data required time --------------------------------------------------------- 8.00 data required time -0.10 data arrival time --------------------------------------------------------- 7.90 slack (MET) Startpoint: en (input port clocked by clk) Endpoint: clk_gate (rising clock gating-check end-point clocked by clk) Path Group: gated clock Path Type: min Delay Time Description --------------------------------------------------------- 0.00 0.00 clock clk (rise edge) 0.00 0.00 clock network delay (ideal) 0.50 0.50 ^ input external delay 0.00 0.50 ^ en (in) 0.00 0.50 ^ clk_gate/A2 (AND2_X1) 0.50 data arrival time 5.00 5.00 clock clk (fall edge) 0.00 5.00 clock network delay (ideal) 0.00 5.00 clock reconvergence pessimism 5.00 v clk_gate/A1 (AND2_X1) 0.00 5.00 clock gating hold time 5.00 data required time --------------------------------------------------------- 5.00 data required time -0.50 data arrival time --------------------------------------------------------- -4.50 slack (VIOLATED) Startpoint: in1 (input port clocked by clk) Endpoint: reg1 (rising edge-triggered flip-flop clocked by clk) Path Group: clk Path Type: min Delay Time Description --------------------------------------------------------- 0.00 0.00 clock clk (rise edge) 0.00 0.00 clock network delay (ideal) 1.00 1.00 ^ input external delay 0.00 1.00 ^ in1 (in) 0.02 1.02 ^ buf1/Z (BUF_X1) 0.00 1.02 ^ reg1/D (DFF_X1) 1.02 data arrival time 0.00 0.00 clock clk (rise edge) 0.00 0.00 clock network delay (ideal) 0.00 0.00 clock reconvergence pessimism 0.00 ^ reg1/CK (DFF_X1) 0.00 0.00 library hold time 0.00 data required time --------------------------------------------------------- 0.00 data required time -1.02 data arrival time --------------------------------------------------------- 1.01 slack (MET) --- Gated clock find_timing_paths --- Warning 502: search_report_json_formats.tcl line 1, find_timing_paths -endpoint_count is deprecated. Use -endpoint_path_count instead. Found 6 gated paths gated=1 check=0 role=clock gating setup slack=9.499999897855105e-9 margin=0.0 target_clk_delay=0.0 gated=1 check=0 role=clock gating setup slack=9.499999897855105e-9 margin=0.0 target_clk_delay=0.0 gated=0 check=0 role=output setup slack=7.899713772019368e-9 margin=1.999999943436137e-9 target_clk_delay=0.0 gated=0 check=0 role=output setup slack=7.901434173618327e-9 margin=1.999999943436137e-9 target_clk_delay=0.0 gated=0 check=1 role=setup slack=8.939980311595264e-9 margin=3.877912227445712e-11 target_clk_delay=0.0 gated=0 check=1 role=setup slack=8.952572017051352e-9 margin=3.072002721649092e-11 target_clk_delay=0.0 --- Gated clock report all formats --- Startpoint: en (input port clocked by clk) Endpoint: clk_gate (rising clock gating-check end-point clocked by clk) Path Group: gated clock Path Type: max Delay Time Description --------------------------------------------------------- 0.00 0.00 clock clk (rise edge) 0.00 0.00 clock network delay (ideal) 0.50 0.50 ^ input external delay 0.00 0.50 ^ en (in) 0.00 0.50 ^ clk_gate/A2 (AND2_X1) 0.50 data arrival time 10.00 10.00 clock clk (rise edge) 0.00 10.00 clock network delay (ideal) 0.00 10.00 clock reconvergence pessimism 10.00 ^ clk_gate/A1 (AND2_X1) 0.00 10.00 clock gating setup time 10.00 data required time --------------------------------------------------------- 10.00 data required time -0.50 data arrival time --------------------------------------------------------- 9.50 slack (MET) Startpoint: reg1 (rising edge-triggered flip-flop clocked by clk) Endpoint: out1 (output port clocked by clk) Path Group: clk Path Type: max Delay Time Description --------------------------------------------------------- 0.00 0.00 clock clk (rise edge) 0.00 0.00 clock network delay (ideal) 0.00 0.00 ^ reg1/CK (DFF_X1) 0.08 0.08 ^ reg1/Q (DFF_X1) 0.02 0.10 ^ buf2/Z (BUF_X1) 0.00 0.10 ^ out1 (out) 0.10 data arrival time 10.00 10.00 clock clk (rise edge) 0.00 10.00 clock network delay (ideal) 0.00 10.00 clock reconvergence pessimism -2.00 8.00 output external delay 8.00 data required time --------------------------------------------------------- 8.00 data required time -0.10 data arrival time --------------------------------------------------------- 7.90 slack (MET) Startpoint: en (input port clocked by clk) Endpoint: clk_gate (rising clock gating-check end-point clocked by clk) Path Group: gated clock Path Type: max Startpoint: reg1 (rising edge-triggered flip-flop clocked by clk) Endpoint: out1 (output port clocked by clk) Path Group: clk Path Type: max max_delay/setup group gated clock Required Actual Endpoint Delay Delay Slack ------------------------------------------------------------ clk_gate/A2 (AND2_X1) 10.00 0.50 9.50 (MET) max_delay/setup group clk Required Actual Endpoint Delay Delay Slack ------------------------------------------------------------ out1 (output) 8.00 0.10 7.90 (MET) Startpoint Endpoint Slack -------------------------------------------------------------------------------- en (input) clk_gate/A2 (AND2_X1) 9.50 reg1/Q (search_gated_clk) out1 (output) 7.90 Group Slack -------------------------------------------- gated clock 9.50 clk 7.90 === Part 3: Output delay paths === --- Output delay report -format json --- {"checks": [ { "type": "output_delay", "path_group": "clk", "path_type": "max", "startpoint": "reg1/Q", "endpoint": "out1", "source_clock": "clk", "source_clock_edge": "rise", "source_clock_path": [ { "instance": "", "cell": "search_test1", "verilog_src": "", "pin": "clk", "arrival": 0.000e+00, "capacitance": 9.497e-16, "slew": 0.000e+00 }, { "instance": "reg1", "cell": "DFF_X1", "verilog_src": "", "pin": "reg1/CK", "net": "clk", "arrival": 0.000e+00, "slew": 0.000e+00 } ], "source_path": [ { "instance": "reg1", "cell": "DFF_X1", "verilog_src": "", "pin": "reg1/Q", "net": "n3", "arrival": 8.371e-11, "capacitance": 9.747e-16, "slew": 7.314e-12 }, { "instance": "buf2", "cell": "BUF_X1", "verilog_src": "", "pin": "buf2/A", "net": "n3", "arrival": 8.371e-11, "slew": 7.314e-12 }, { "instance": "buf2", "cell": "BUF_X1", "verilog_src": "", "pin": "buf2/Z", "net": "out1", "arrival": 1.003e-10, "capacitance": 0.000e+00, "slew": 3.638e-12 }, { "instance": "", "cell": "search_test1", "verilog_src": "", "pin": "out1", "arrival": 1.003e-10, "slew": 3.638e-12 } ], "target_clock": "clk", "target_clock_edge": "rise", "data_arrival_time": 1.003e-10, "crpr": 0.000e+00, "margin": 8.000e-09, "required_time": 2.000e-09, "slack": 1.900e-09 } ] } {"checks": [ { "type": "output_delay", "path_group": "clk", "path_type": "min", "startpoint": "reg1/Q", "endpoint": "out1", "source_clock": "clk", "source_clock_edge": "rise", "source_clock_path": [ { "instance": "", "cell": "search_test1", "verilog_src": "", "pin": "clk", "arrival": 0.000e+00, "capacitance": 9.497e-16, "slew": 0.000e+00 }, { "instance": "reg1", "cell": "DFF_X1", "verilog_src": "", "pin": "reg1/CK", "net": "clk", "arrival": 0.000e+00, "slew": 0.000e+00 } ], "source_path": [ { "instance": "reg1", "cell": "DFF_X1", "verilog_src": "", "pin": "reg1/Q", "net": "n3", "arrival": 7.722e-11, "capacitance": 8.752e-16, "slew": 5.624e-12 }, { "instance": "buf2", "cell": "BUF_X1", "verilog_src": "", "pin": "buf2/A", "net": "n3", "arrival": 7.722e-11, "slew": 5.624e-12 }, { "instance": "buf2", "cell": "BUF_X1", "verilog_src": "", "pin": "buf2/Z", "net": "out1", "arrival": 9.857e-11, "capacitance": 0.000e+00, "slew": 3.903e-12 }, { "instance": "", "cell": "search_test1", "verilog_src": "", "pin": "out1", "arrival": 9.857e-11, "slew": 3.903e-12 } ], "target_clock": "clk", "target_clock_edge": "rise", "data_arrival_time": 9.857e-11, "crpr": 0.000e+00, "margin": -8.000e-09, "required_time": -8.000e-09, "slack": 8.099e-09 } ] } --- Output delay report -format full_clock_expanded --- Startpoint: reg1 (rising edge-triggered flip-flop clocked by clk) Endpoint: out1 (output port clocked by clk) Path Group: clk Path Type: max Delay Time Description --------------------------------------------------------- 0.00 0.00 clock clk (rise edge) 0.00 0.00 clock network delay (ideal) 0.00 0.00 ^ reg1/CK (DFF_X1) 0.08 0.08 ^ reg1/Q (DFF_X1) 0.02 0.10 ^ buf2/Z (BUF_X1) 0.00 0.10 ^ out1 (out) 0.10 data arrival time 10.00 10.00 clock clk (rise edge) 0.00 10.00 clock network delay (ideal) 0.00 10.00 clock reconvergence pessimism -8.00 2.00 output external delay 2.00 data required time --------------------------------------------------------- 2.00 data required time -0.10 data arrival time --------------------------------------------------------- 1.90 slack (MET) Startpoint: reg1 (rising edge-triggered flip-flop clocked by clk) Endpoint: out1 (output port clocked by clk) Path Group: clk Path Type: min Delay Time Description --------------------------------------------------------- 0.00 0.00 clock clk (rise edge) 0.00 0.00 clock network delay (ideal) 0.00 0.00 ^ reg1/CK (DFF_X1) 0.08 0.08 v reg1/Q (DFF_X1) 0.02 0.10 v buf2/Z (BUF_X1) 0.00 0.10 v out1 (out) 0.10 data arrival time 0.00 0.00 clock clk (rise edge) 0.00 0.00 clock network delay (ideal) 0.00 0.00 clock reconvergence pessimism -8.00 -8.00 output external delay -8.00 data required time --------------------------------------------------------- -8.00 data required time -0.10 data arrival time --------------------------------------------------------- 8.10 slack (MET) --- Output delay find_timing_paths --- Warning 502: search_report_json_formats.tcl line 1, find_timing_paths -endpoint_count is deprecated. Use -endpoint_path_count instead. Found 2 output delay paths out=1 check=0 role=output setup slack=1.8997141637555615e-9 margin=7.999999773744548e-9 req=2.000000165480742e-9 target_clk_delay=0.0 out=1 check=0 role=output setup slack=1.9014345653545206e-9 margin=7.999999773744548e-9 req=2.000000165480742e-9 target_clk_delay=0.0 --- Output delay report all formats --- Startpoint: reg1 (rising edge-triggered flip-flop clocked by clk) Endpoint: out1 (output port clocked by clk) Path Group: clk Path Type: max Delay Time Description --------------------------------------------------------- 0.00 0.00 clock clk (rise edge) 0.00 0.00 clock network delay (ideal) 0.00 0.00 ^ reg1/CK (DFF_X1) 0.08 0.08 ^ reg1/Q (DFF_X1) 0.02 0.10 ^ buf2/Z (BUF_X1) 0.00 0.10 ^ out1 (out) 0.10 data arrival time 10.00 10.00 clock clk (rise edge) 0.00 10.00 clock network delay (ideal) 0.00 10.00 clock reconvergence pessimism -8.00 2.00 output external delay 2.00 data required time --------------------------------------------------------- 2.00 data required time -0.10 data arrival time --------------------------------------------------------- 1.90 slack (MET) Startpoint: reg1 (rising edge-triggered flip-flop clocked by clk) Endpoint: out1 (output port clocked by clk) Path Group: clk Path Type: max Delay Time Description --------------------------------------------------------- 0.00 0.00 clock clk (rise edge) 0.00 0.00 clock network delay (ideal) 0.00 0.00 ^ reg1/CK (DFF_X1) 0.08 0.08 ^ reg1/Q (DFF_X1) 0.02 0.10 ^ buf2/Z (BUF_X1) 0.00 0.10 ^ out1 (out) 0.10 data arrival time 10.00 10.00 clock clk (rise edge) 0.00 10.00 clock network delay (ideal) 0.00 10.00 clock reconvergence pessimism -8.00 2.00 output external delay 2.00 data required time --------------------------------------------------------- 2.00 data required time -0.10 data arrival time --------------------------------------------------------- 1.90 slack (MET) Startpoint: reg1 (rising edge-triggered flip-flop clocked by clk) Endpoint: out1 (output port clocked by clk) Path Group: clk Path Type: max max_delay/setup group clk Required Actual Endpoint Delay Delay Slack ------------------------------------------------------------ out1 (output) 2.00 0.10 1.90 (MET) Startpoint Endpoint Slack -------------------------------------------------------------------------------- reg1/Q (search_test1) out1 (output) 1.90 Group Slack -------------------------------------------- clk 1.90 === Part 4: Data check paths === --- Data check report -format json --- {"checks": [ { "type": "check", "path_group": "asynchronous", "path_type": "max", "startpoint": "rst", "endpoint": "reg1/RN", "source_clock": "clk", "source_clock_edge": "rise", "source_path": [ { "instance": "", "cell": "search_data_check_gated", "verilog_src": "", "pin": "rst", "arrival": 5.000e-10, "capacitance": 3.557e-15, "slew": 0.000e+00 }, { "instance": "reg1", "cell": "DFFR_X1", "verilog_src": "", "pin": "reg1/RN", "net": "rst", "arrival": 5.000e-10, "slew": 0.000e+00 } ], "target_clock": "clk", "target_clock_edge": "rise", "target_clock_path": [ { "instance": "", "cell": "search_data_check_gated", "verilog_src": "", "pin": "clk", "arrival": 0.000e+00, "capacitance": 1.895e-15, "slew": 0.000e+00 }, { "instance": "clk_gate", "cell": "AND2_X1", "verilog_src": "", "pin": "clk_gate/A1", "net": "clk", "arrival": 0.000e+00, "slew": 0.000e+00 }, { "instance": "clk_gate", "cell": "AND2_X1", "verilog_src": "", "pin": "clk_gate/ZN", "net": "gated_clk", "arrival": 2.450e-11, "capacitance": 9.766e-16, "slew": 7.004e-12 }, { "instance": "reg1", "cell": "DFFR_X1", "verilog_src": "", "pin": "reg1/CK", "net": "gated_clk", "arrival": 2.450e-11, "slew": 7.004e-12 } ], "data_arrival_time": 5.000e-10, "crpr": 0.000e+00, "margin": -5.373e-11, "required_time": 1.005e-08, "slack": 9.554e-09 }, { "type": "data_check", "path_group": "clk", "path_type": "max", "startpoint": "reg1/Q", "endpoint": "reg2/D", "source_clock": "clk", "source_clock_edge": "rise", "source_clock_path": [ { "instance": "", "cell": "search_data_check_gated", "verilog_src": "", "pin": "clk", "arrival": 0.000e+00, "capacitance": 1.895e-15, "slew": 0.000e+00 }, { "instance": "clk_gate", "cell": "AND2_X1", "verilog_src": "", "pin": "clk_gate/A1", "net": "clk", "arrival": 0.000e+00, "slew": 0.000e+00 }, { "instance": "clk_gate", "cell": "AND2_X1", "verilog_src": "", "pin": "clk_gate/ZN", "net": "gated_clk", "arrival": 2.450e-11, "capacitance": 9.766e-16, "slew": 7.005e-12 }, { "instance": "reg1", "cell": "DFFR_X1", "verilog_src": "", "pin": "reg1/CK", "net": "gated_clk", "arrival": 2.450e-11, "slew": 7.005e-12 } ], "source_path": [ { "instance": "reg1", "cell": "DFFR_X1", "verilog_src": "", "pin": "reg1/Q", "net": "n4", "arrival": 1.006e-10, "capacitance": 2.103e-15, "slew": 1.079e-11 }, { "instance": "reg2", "cell": "DFFR_X1", "verilog_src": "", "pin": "reg2/D", "net": "n4", "arrival": 1.006e-10, "slew": 1.079e-11 } ], "target_clock": "clk", "target_clock_edge": "fall", "target_clock_path": [ { "instance": "", "cell": "search_data_check_gated", "verilog_src": "", "pin": "clk", "arrival": 5.000e-09, "capacitance": 1.756e-15, "slew": 0.000e+00 }, { "instance": "clk_gate", "cell": "AND2_X1", "verilog_src": "", "pin": "clk_gate/A1", "net": "clk", "arrival": 5.000e-09, "slew": 0.000e+00 }, { "instance": "clk_gate", "cell": "AND2_X1", "verilog_src": "", "pin": "clk_gate/ZN", "net": "gated_clk", "arrival": 5.022e-09, "capacitance": 8.807e-16, "slew": 5.048e-12 }, { "instance": "reg1", "cell": "DFFR_X1", "verilog_src": "", "pin": "reg1/CK", "net": "gated_clk", "arrival": 5.022e-09, "slew": 5.048e-12 } ], "data_arrival_time": 1.010e-08, "crpr": 0.000e+00, "margin": 2.000e-10, "required_time": 4.822e-09, "slack": -5.278e-09 } ] } {"checks": [ { "type": "check", "path_group": "asynchronous", "path_type": "min", "startpoint": "rst", "endpoint": "reg1/RN", "source_clock": "clk", "source_clock_edge": "rise", "source_path": [ { "instance": "", "cell": "search_data_check_gated", "verilog_src": "", "pin": "rst", "arrival": 5.000e-10, "capacitance": 3.557e-15, "slew": 0.000e+00 }, { "instance": "reg1", "cell": "DFFR_X1", "verilog_src": "", "pin": "reg1/RN", "net": "rst", "arrival": 5.000e-10, "slew": 0.000e+00 } ], "target_clock": "clk", "target_clock_edge": "rise", "target_clock_path": [ { "instance": "", "cell": "search_data_check_gated", "verilog_src": "", "pin": "clk", "arrival": 0.000e+00, "capacitance": 1.895e-15, "slew": 0.000e+00 }, { "instance": "clk_gate", "cell": "AND2_X1", "verilog_src": "", "pin": "clk_gate/A1", "net": "clk", "arrival": 0.000e+00, "slew": 0.000e+00 }, { "instance": "clk_gate", "cell": "AND2_X1", "verilog_src": "", "pin": "clk_gate/ZN", "net": "gated_clk", "arrival": 2.450e-11, "capacitance": 9.766e-16, "slew": 7.005e-12 }, { "instance": "reg1", "cell": "DFFR_X1", "verilog_src": "", "pin": "reg1/CK", "net": "gated_clk", "arrival": 2.450e-11, "slew": 7.005e-12 } ], "data_arrival_time": 5.000e-10, "crpr": 0.000e+00, "margin": 1.814e-10, "required_time": 1.814e-10, "slack": 3.186e-10 }, { "type": "check", "path_group": "clk", "path_type": "min", "startpoint": "reg1/Q", "endpoint": "reg2/D", "source_clock": "clk", "source_clock_edge": "rise", "source_clock_path": [ { "instance": "", "cell": "search_data_check_gated", "verilog_src": "", "pin": "clk", "arrival": 0.000e+00, "capacitance": 1.895e-15, "slew": 0.000e+00 }, { "instance": "clk_gate", "cell": "AND2_X1", "verilog_src": "", "pin": "clk_gate/A1", "net": "clk", "arrival": 0.000e+00, "slew": 0.000e+00 }, { "instance": "clk_gate", "cell": "AND2_X1", "verilog_src": "", "pin": "clk_gate/ZN", "net": "gated_clk", "arrival": 2.450e-11, "capacitance": 9.766e-16, "slew": 7.004e-12 }, { "instance": "reg1", "cell": "DFFR_X1", "verilog_src": "", "pin": "reg1/CK", "net": "gated_clk", "arrival": 2.450e-11, "slew": 7.004e-12 } ], "source_path": [ { "instance": "reg1", "cell": "DFFR_X1", "verilog_src": "", "pin": "reg1/Q", "net": "n4", "arrival": 8.488e-11, "capacitance": 1.928e-15, "slew": 7.095e-12 }, { "instance": "reg2", "cell": "DFFR_X1", "verilog_src": "", "pin": "reg2/D", "net": "n4", "arrival": 8.488e-11, "slew": 7.095e-12 } ], "target_clock": "clk", "target_clock_edge": "rise", "target_clock_path": [ { "instance": "", "cell": "search_data_check_gated", "verilog_src": "", "pin": "clk", "arrival": 0.000e+00, "capacitance": 1.895e-15, "slew": 0.000e+00 }, { "instance": "reg2", "cell": "DFFR_X1", "verilog_src": "", "pin": "reg2/CK", "net": "clk", "arrival": 0.000e+00, "slew": 0.000e+00 } ], "data_arrival_time": 8.488e-11, "crpr": 0.000e+00, "margin": 2.672e-12, "required_time": 2.672e-12, "slack": 8.221e-11 } ] } --- Data check report -format full_clock_expanded --- Startpoint: rst (input port clocked by clk) Endpoint: reg1 (recovery check against rising-edge clock clk) Path Group: asynchronous Path Type: max Delay Time Description --------------------------------------------------------- 0.00 0.00 clock clk (rise edge) 0.00 0.00 clock network delay (ideal) 0.50 0.50 ^ input external delay 0.00 0.50 ^ rst (in) 0.00 0.50 ^ reg1/RN (DFFR_X1) 0.50 data arrival time 10.00 10.00 clock clk (rise edge) 0.00 10.00 clock network delay (ideal) 0.00 10.00 clock reconvergence pessimism 10.00 ^ reg1/CK (DFFR_X1) 0.05 10.05 library recovery time 10.05 data required time --------------------------------------------------------- 10.05 data required time -0.50 data arrival time --------------------------------------------------------- 9.55 slack (MET) Startpoint: reg1 (rising edge-triggered flip-flop clocked by clk) Endpoint: reg2 (falling edge-triggered data to data check clocked by clk) Path Group: clk Path Type: max Delay Time Description --------------------------------------------------------- 10.00 10.00 clock clk (rise edge) 0.00 10.00 clock network delay (ideal) 0.00 10.00 ^ reg1/CK (DFFR_X1) 0.10 10.10 ^ reg1/Q (DFFR_X1) 0.00 10.10 ^ reg2/D (DFFR_X1) 10.10 data arrival time 5.00 5.00 clock clk (fall edge) 0.00 5.00 clock source latency 0.00 5.00 v clk (in) 0.02 5.02 v clk_gate/ZN (AND2_X1) 0.00 5.02 v reg1/CK (DFFR_X1) 0.00 5.02 clock reconvergence pessimism -0.20 4.82 data check setup time 4.82 data required time --------------------------------------------------------- 4.82 data required time -10.10 data arrival time --------------------------------------------------------- -5.28 slack (VIOLATED) Startpoint: rst (input port clocked by clk) Endpoint: reg1 (removal check against rising-edge clock clk) Path Group: asynchronous Path Type: min Delay Time Description --------------------------------------------------------- 0.00 0.00 clock clk (rise edge) 0.00 0.00 clock network delay (ideal) 0.50 0.50 ^ input external delay 0.00 0.50 ^ rst (in) 0.00 0.50 ^ reg1/RN (DFFR_X1) 0.50 data arrival time 0.00 0.00 clock clk (rise edge) 0.00 0.00 clock network delay (ideal) 0.00 0.00 clock reconvergence pessimism 0.00 ^ reg1/CK (DFFR_X1) 0.18 0.18 library removal time 0.18 data required time --------------------------------------------------------- 0.18 data required time -0.50 data arrival time --------------------------------------------------------- 0.32 slack (MET) Startpoint: reg1 (rising edge-triggered flip-flop clocked by clk) Endpoint: reg2 (rising edge-triggered flip-flop clocked by clk) Path Group: clk Path Type: min Delay Time Description --------------------------------------------------------- 0.00 0.00 clock clk (rise edge) 0.00 0.00 clock network delay (ideal) 0.00 0.00 ^ reg1/CK (DFFR_X1) 0.08 0.08 v reg1/Q (DFFR_X1) 0.00 0.08 v reg2/D (DFFR_X1) 0.08 data arrival time 0.00 0.00 clock clk (rise edge) 0.00 0.00 clock network delay (ideal) 0.00 0.00 clock reconvergence pessimism 0.00 ^ reg2/CK (DFFR_X1) 0.00 0.00 library hold time 0.00 data required time --------------------------------------------------------- 0.00 data required time -0.08 data arrival time --------------------------------------------------------- 0.08 slack (MET) --- Data check find_timing_paths --- Warning 502: search_report_json_formats.tcl line 1, find_timing_paths -endpoint_count is deprecated. Use -endpoint_path_count instead. Found 20 data check paths data=0 check=1 role=recovery slack=9.553728474998024e-9 margin=-5.372824407601229e-11 target_clk_delay=0.0 data=0 check=1 role=recovery slack=9.553728474998024e-9 margin=-5.372824407601229e-11 target_clk_delay=0.0 data=1 check=0 role=data check setup slack=-5.278119719065444e-9 margin=1.9999998879249858e-10 target_clk_delay=2.2468693572363918e-11 data=1 check=0 role=data check setup slack=-5.262408730999368e-9 margin=1.9999998879249858e-10 target_clk_delay=2.2468693572363918e-11 data=1 check=0 role=data check setup slack=-2.760924822098332e-10 margin=1.9999998879249858e-10 target_clk_delay=2.4496025000098065e-11 data=1 check=0 role=data check setup slack=-2.6038149414375766e-10 margin=1.9999998879249858e-10 target_clk_delay=2.4496025000098065e-11 data=1 check=0 role=data check setup slack=2.2410170941178365e-10 margin=1.9999998879249858e-10 target_clk_delay=0.0 data=1 check=0 role=data check setup slack=2.3981269747785916e-10 margin=1.9999998879249858e-10 target_clk_delay=0.0 data=0 check=0 role=output setup slack=7.881454600067173e-9 margin=1.999999943436137e-9 target_clk_delay=0.0 data=0 check=0 role=output setup slack=7.885596176038234e-9 margin=1.999999943436137e-9 target_clk_delay=0.0 data=0 check=0 role=output setup slack=7.892997366809595e-9 margin=1.999999943436137e-9 target_clk_delay=0.0 data=0 check=0 role=output setup slack=7.895866183105227e-9 margin=1.999999943436137e-9 target_clk_delay=0.0 data=0 check=0 role=output setup slack=7.914771948946964e-9 margin=1.999999943436137e-9 target_clk_delay=0.0 data=0 check=0 role=output setup slack=7.92035237395794e-9 margin=1.999999943436137e-9 target_clk_delay=0.0 data=0 check=1 role=setup slack=8.908846105271095e-9 margin=3.831846298596453e-11 target_clk_delay=0.0 data=0 check=1 role=setup slack=8.909343485186128e-9 margin=3.18987544711824e-11 target_clk_delay=0.0 data=0 check=1 role=setup slack=8.91013662851492e-9 margin=3.831846298596453e-11 target_clk_delay=0.0 data=0 check=1 role=setup slack=8.911564819413798e-9 margin=3.18987544711824e-11 target_clk_delay=0.0 data=0 check=1 role=setup slack=9.865935624020494e-9 margin=3.3475701377572165e-11 target_clk_delay=0.0 data=0 check=1 role=setup slack=9.875192219510609e-9 margin=3.9929969053442704e-11 target_clk_delay=0.0 --- Data check report all formats --- Startpoint: rst (input port clocked by clk) Endpoint: reg1 (recovery check against rising-edge clock clk) Path Group: asynchronous Path Type: max Delay Time Description --------------------------------------------------------- 0.00 0.00 clock clk (rise edge) 0.00 0.00 clock network delay (ideal) 0.50 0.50 ^ input external delay 0.00 0.50 ^ rst (in) 0.00 0.50 ^ reg1/RN (DFFR_X1) 0.50 data arrival time 10.00 10.00 clock clk (rise edge) 0.00 10.00 clock network delay (ideal) 0.00 10.00 clock reconvergence pessimism 10.00 ^ reg1/CK (DFFR_X1) 0.05 10.05 library recovery time 10.05 data required time --------------------------------------------------------- 10.05 data required time -0.50 data arrival time --------------------------------------------------------- 9.55 slack (MET) Startpoint: reg1 (rising edge-triggered flip-flop clocked by clk) Endpoint: reg2 (falling edge-triggered data to data check clocked by clk) Path Group: clk Path Type: max Delay Time Description --------------------------------------------------------- 10.00 10.00 clock clk (rise edge) 0.00 10.00 clock network delay (ideal) 0.00 10.00 ^ reg1/CK (DFFR_X1) 0.10 10.10 ^ reg1/Q (DFFR_X1) 0.00 10.10 ^ reg2/D (DFFR_X1) 10.10 data arrival time 5.00 5.00 clock clk (fall edge) 0.02 5.02 clock network delay (propagated) 0.00 5.02 clock reconvergence pessimism 5.02 v reg1/CK (DFFR_X1) -0.20 4.82 data check setup time 4.82 data required time --------------------------------------------------------- 4.82 data required time -10.10 data arrival time --------------------------------------------------------- -5.28 slack (VIOLATED) Startpoint: rst (input port clocked by clk) Endpoint: reg1 (recovery check against rising-edge clock clk) Path Group: asynchronous Path Type: max Delay Time Description --------------------------------------------------------- 0.00 0.00 clock clk (rise edge) 0.00 0.00 clock network delay (ideal) 0.50 0.50 ^ input external delay 0.00 0.50 ^ rst (in) 0.00 0.50 ^ reg1/RN (DFFR_X1) 0.50 data arrival time 10.00 10.00 clock clk (rise edge) 0.00 10.00 clock network delay (ideal) 0.00 10.00 clock reconvergence pessimism 10.00 ^ reg1/CK (DFFR_X1) 0.05 10.05 library recovery time 10.05 data required time --------------------------------------------------------- 10.05 data required time -0.50 data arrival time --------------------------------------------------------- 9.55 slack (MET) Startpoint: reg1 (rising edge-triggered flip-flop clocked by clk) Endpoint: reg2 (falling edge-triggered data to data check clocked by clk) Path Group: clk Path Type: max Delay Time Description --------------------------------------------------------- 10.00 10.00 clock clk (rise edge) 0.00 10.00 clock network delay (ideal) 0.00 10.00 ^ reg1/CK (DFFR_X1) 0.10 10.10 ^ reg1/Q (DFFR_X1) 0.00 10.10 ^ reg2/D (DFFR_X1) 10.10 data arrival time 5.00 5.00 clock clk (fall edge) 0.00 5.00 clock source latency 0.00 5.00 v clk (in) 0.02 5.02 v clk_gate/ZN (AND2_X1) 0.00 5.02 v reg1/CK (DFFR_X1) 0.00 5.02 clock reconvergence pessimism -0.20 4.82 data check setup time 4.82 data required time --------------------------------------------------------- 4.82 data required time -10.10 data arrival time --------------------------------------------------------- -5.28 slack (VIOLATED) Startpoint: rst (input port clocked by clk) Endpoint: reg1 (recovery check against rising-edge clock clk) Path Group: asynchronous Path Type: max Startpoint: reg1 (rising edge-triggered flip-flop clocked by clk) Endpoint: reg2 (falling edge-triggered data to data check clocked by clk) Path Group: clk Path Type: max max_delay/setup group asynchronous Required Actual Endpoint Delay Delay Slack ------------------------------------------------------------ reg1/RN (DFFR_X1) 10.05 0.50 9.55 (MET) max_delay/setup group clk Required Actual Endpoint Delay Delay Slack ------------------------------------------------------------ reg2/D (DFFR_X1) 4.82 10.10 -5.28 (VIOLATED) Startpoint Endpoint Slack -------------------------------------------------------------------------------- rst (input) reg1/RN (DFFR_X1) 9.55 reg1/Q (DFFR_X1) reg2/D (DFFR_X1) -5.28 Group Slack -------------------------------------------- asynchronous 9.55 clk -5.28 --- Data check with -digits 6 --- Startpoint: rst (input port clocked by clk) Endpoint: reg1 (recovery check against rising-edge clock clk) Path Group: asynchronous Path Type: max Delay Time Description ----------------------------------------------------------------- 0.000000 0.000000 clock clk (rise edge) 0.000000 0.000000 clock network delay (ideal) 0.500000 0.500000 ^ input external delay 0.000000 0.500000 ^ rst (in) 0.000000 0.500000 ^ reg1/RN (DFFR_X1) 0.500000 data arrival time 10.000000 10.000000 clock clk (rise edge) 0.000000 10.000000 clock network delay (ideal) 0.000000 10.000000 clock reconvergence pessimism 10.000000 ^ reg1/CK (DFFR_X1) 0.053728 10.053729 library recovery time 10.053729 data required time ----------------------------------------------------------------- 10.053729 data required time -0.500000 data arrival time ----------------------------------------------------------------- 9.553729 slack (MET) Startpoint: reg1 (rising edge-triggered flip-flop clocked by clk) Endpoint: reg2 (falling edge-triggered data to data check clocked by clk) Path Group: clk Path Type: max Delay Time Description ----------------------------------------------------------------- 10.000000 10.000000 clock clk (rise edge) 0.000000 10.000000 clock network delay (ideal) 0.000000 10.000000 ^ reg1/CK (DFFR_X1) 0.100589 10.100589 ^ reg1/Q (DFFR_X1) 0.000000 10.100589 ^ reg2/D (DFFR_X1) 10.100589 data arrival time 5.000000 5.000000 clock clk (fall edge) 0.000000 5.000000 clock source latency 0.000000 5.000000 v clk (in) 0.022469 5.022469 v clk_gate/ZN (AND2_X1) 0.000000 5.022469 v reg1/CK (DFFR_X1) 0.000000 5.022469 clock reconvergence pessimism -0.200000 4.822469 data check setup time 4.822469 data required time ----------------------------------------------------------------- 4.822469 data required time -10.100589 data arrival time ----------------------------------------------------------------- -5.278120 slack (VIOLATED) --- Data check with -no_line_splits --- Startpoint: rst (input port clocked by clk) Endpoint: reg1 (recovery check against rising-edge clock clk) Path Group: asynchronous Path Type: max Delay Time Description --------------------------------------------------------- 0.00 0.00 clock clk (rise edge) 0.00 0.00 clock network delay (ideal) 0.50 0.50 ^ input external delay 0.00 0.50 ^ rst (in) 0.00 0.50 ^ reg1/RN (DFFR_X1) 0.50 data arrival time 10.00 10.00 clock clk (rise edge) 0.00 10.00 clock network delay (ideal) 0.00 10.00 clock reconvergence pessimism 10.00 ^ reg1/CK (DFFR_X1) 0.05 10.05 library recovery time 10.05 data required time --------------------------------------------------------- 10.05 data required time -0.50 data arrival time --------------------------------------------------------- 9.55 slack (MET) Startpoint: reg1 (rising edge-triggered flip-flop clocked by clk) Endpoint: reg2 (falling edge-triggered data to data check clocked by clk) Path Group: clk Path Type: max Delay Time Description --------------------------------------------------------- 10.00 10.00 clock clk (rise edge) 0.00 10.00 clock network delay (ideal) 0.00 10.00 ^ reg1/CK (DFFR_X1) 0.10 10.10 ^ reg1/Q (DFFR_X1) 0.00 10.10 ^ reg2/D (DFFR_X1) 10.10 data arrival time 5.00 5.00 clock clk (fall edge) 0.02 5.02 clock network delay (propagated) 0.00 5.02 clock reconvergence pessimism 5.02 v reg1/CK (DFFR_X1) -0.20 4.82 data check setup time 4.82 data required time --------------------------------------------------------- 4.82 data required time -10.10 data arrival time --------------------------------------------------------- -5.28 slack (VIOLATED) === Part 5: Unconstrained JSON === {"checks": [ { "type": "unconstrained", "path_group": "unconstrained", "path_type": "max", "startpoint": "reg1/Q", "endpoint": "out1", "source_clock_path": [ { "instance": "reg1", "cell": "DFF_X1", "verilog_src": "", "pin": "reg1/CK", "net": "clk", "arrival": 0.000e+00, "slew": 0.000e+00 } ], "source_path": [ { "instance": "reg1", "cell": "DFF_X1", "verilog_src": "", "pin": "reg1/Q", "net": "n3", "arrival": 8.371e-11, "capacitance": 9.747e-16, "slew": 7.314e-12 }, { "instance": "buf2", "cell": "BUF_X1", "verilog_src": "", "pin": "buf2/A", "net": "n3", "arrival": 8.371e-11, "slew": 7.314e-12 }, { "instance": "buf2", "cell": "BUF_X1", "verilog_src": "", "pin": "buf2/Z", "net": "out1", "arrival": 1.003e-10, "capacitance": 0.000e+00, "slew": 3.638e-12 }, { "instance": "", "cell": "search_test1", "verilog_src": "", "pin": "out1", "arrival": 1.003e-10, "slew": 3.638e-12 } ] } ] } Startpoint: reg1 (rising edge-triggered flip-flop) Endpoint: out1 (output port) Path Group: unconstrained Path Type: max Delay Time Description --------------------------------------------------------- 0.00 0.00 ^ reg1/CK (DFF_X1) 0.08 0.08 ^ reg1/Q (DFF_X1) 0.02 0.10 ^ buf2/Z (BUF_X1) 0.00 0.10 ^ out1 (out) 0.10 data arrival time --------------------------------------------------------- (Path is unconstrained) Startpoint Endpoint Slack -------------------------------------------------------------------------------- reg1/Q (search_test1) out1 (output) 0.10 max_delay/setup group unconstrained Required Actual Endpoint Delay Delay Slack ------------------------------------------------------------ out1 (output) INF 0.10 INF (MET) Group Slack -------------------------------------------- unconstrained 0.10