--- Latch timing max --- Startpoint: latch1 (positive level-sensitive latch clocked by clk) Endpoint: latch2 (positive level-sensitive latch clocked by clk) Path Group: clk Path Type: max Delay Time Description --------------------------------------------------------- 0.00 0.00 clock clk (rise edge) 0.00 0.00 clock network delay (ideal) 1.05 1.05 time given to startpoint 0.00 1.05 v latch1/D (DLH_X1) 0.06 1.11 v latch1/Q (DLH_X1) 0.00 1.11 v latch2/D (DLH_X1) 1.11 data arrival time 0.00 0.00 clock clk (rise edge) 0.00 0.00 clock network delay (ideal) 0.00 0.00 clock reconvergence pessimism 0.00 ^ latch2/G (DLH_X1) 1.11 1.11 time borrowed from endpoint 1.11 data required time --------------------------------------------------------- 1.11 data required time -1.11 data arrival time --------------------------------------------------------- 0.00 slack (MET) Time Borrowing Information -------------------------------------------- clk pulse width 5.00 library setup time -0.05 -------------------------------------------- max time borrow 4.95 actual time borrow 1.11 -------------------------------------------- --- Latch timing min --- Startpoint: latch1 (positive level-sensitive latch clocked by clk) Endpoint: reg1 (rising edge-triggered flip-flop clocked by clk) Path Group: clk Path Type: min Delay Time Description --------------------------------------------------------- 0.00 0.00 clock clk (rise edge) 0.00 0.00 clock network delay (ideal) 0.00 0.00 ^ latch1/G (DLH_X1) 0.05 0.05 ^ latch1/Q (DLH_X1) 0.00 0.05 ^ reg1/D (DFF_X1) 0.05 data arrival time 0.00 0.00 clock clk (rise edge) 0.00 0.00 clock network delay (ideal) 0.00 0.00 clock reconvergence pessimism 0.00 ^ reg1/CK (DFF_X1) 0.01 0.01 library hold time 0.01 data required time --------------------------------------------------------- 0.01 data required time -0.05 data arrival time --------------------------------------------------------- 0.05 slack (MET) --- report_checks to latch output --- Startpoint: latch2 (positive level-sensitive latch clocked by clk) Endpoint: out1 (output port clocked by clk) Path Group: clk Path Type: max Delay Time Description --------------------------------------------------------- 0.00 0.00 clock clk (rise edge) 0.00 0.00 clock network delay (ideal) 1.11 1.11 time given to startpoint 0.00 1.11 v latch2/D (DLH_X1) 0.06 1.16 v latch2/Q (DLH_X1) 0.02 1.19 v buf2/Z (BUF_X1) 0.00 1.19 v out1 (out) 1.19 data arrival time 10.00 10.00 clock clk (rise edge) 0.00 10.00 clock network delay (ideal) 0.00 10.00 clock reconvergence pessimism -2.00 8.00 output external delay 8.00 data required time --------------------------------------------------------- 8.00 data required time -1.19 data arrival time --------------------------------------------------------- 6.81 slack (MET) Startpoint: latch2 (positive level-sensitive latch clocked by clk) Endpoint: out1 (output port clocked by clk) Path Group: clk Path Type: min Delay Time Description --------------------------------------------------------- 0.00 0.00 clock clk (rise edge) 0.00 0.00 clock network delay (ideal) 0.00 0.00 ^ latch2/G (DLH_X1) 0.05 0.05 ^ latch2/Q (DLH_X1) 0.02 0.07 ^ buf2/Z (BUF_X1) 0.00 0.07 ^ out1 (out) 0.07 data arrival time 0.00 0.00 clock clk (rise edge) 0.00 0.00 clock network delay (ideal) 0.00 0.00 clock reconvergence pessimism -2.00 -2.00 output external delay -2.00 data required time --------------------------------------------------------- -2.00 data required time -0.07 data arrival time --------------------------------------------------------- 2.07 slack (MET) --- report_checks to reg output --- Startpoint: reg1 (rising edge-triggered flip-flop clocked by clk) Endpoint: out2 (output port clocked by clk) Path Group: clk Path Type: max Delay Time Description --------------------------------------------------------- 0.00 0.00 clock clk (rise edge) 0.00 0.00 clock network delay (ideal) 0.00 0.00 ^ reg1/CK (DFF_X1) 0.08 0.08 ^ reg1/Q (DFF_X1) 0.02 0.10 ^ buf3/Z (BUF_X1) 0.00 0.10 ^ out2 (out) 0.10 data arrival time 10.00 10.00 clock clk (rise edge) 0.00 10.00 clock network delay (ideal) 0.00 10.00 clock reconvergence pessimism -2.00 8.00 output external delay 8.00 data required time --------------------------------------------------------- 8.00 data required time -0.10 data arrival time --------------------------------------------------------- 7.90 slack (MET) Startpoint: reg1 (rising edge-triggered flip-flop clocked by clk) Endpoint: out2 (output port clocked by clk) Path Group: clk Path Type: min Delay Time Description --------------------------------------------------------- 0.00 0.00 clock clk (rise edge) 0.00 0.00 clock network delay (ideal) 0.00 0.00 ^ reg1/CK (DFF_X1) 0.08 0.08 v reg1/Q (DFF_X1) 0.02 0.10 v buf3/Z (BUF_X1) 0.00 0.10 v out2 (out) 0.10 data arrival time 0.00 0.00 clock clk (rise edge) 0.00 0.00 clock network delay (ideal) 0.00 0.00 clock reconvergence pessimism -2.00 -2.00 output external delay -2.00 data required time --------------------------------------------------------- -2.00 data required time -0.10 data arrival time --------------------------------------------------------- 2.10 slack (MET) --- report_checks format full_clock --- Startpoint: latch1 (positive level-sensitive latch clocked by clk) Endpoint: latch2 (positive level-sensitive latch clocked by clk) Path Group: clk Path Type: max Delay Time Description --------------------------------------------------------- 0.00 0.00 clock clk (rise edge) 0.00 0.00 clock network delay (ideal) 1.05 1.05 time given to startpoint 0.00 1.05 v latch1/D (DLH_X1) 0.06 1.11 v latch1/Q (DLH_X1) 0.00 1.11 v latch2/D (DLH_X1) 1.11 data arrival time 0.00 0.00 clock clk (rise edge) 0.00 0.00 clock network delay (ideal) 0.00 0.00 clock reconvergence pessimism 0.00 ^ latch2/G (DLH_X1) 1.11 1.11 time borrowed from endpoint 1.11 data required time --------------------------------------------------------- 1.11 data required time -1.11 data arrival time --------------------------------------------------------- 0.00 slack (MET) Time Borrowing Information -------------------------------------------- clk pulse width 5.00 library setup time -0.05 -------------------------------------------- max time borrow 4.95 actual time borrow 1.11 -------------------------------------------- Startpoint: latch1 (positive level-sensitive latch clocked by clk) Endpoint: reg1 (rising edge-triggered flip-flop clocked by clk) Path Group: clk Path Type: min Delay Time Description --------------------------------------------------------- 0.00 0.00 clock clk (rise edge) 0.00 0.00 clock network delay (ideal) 0.00 0.00 ^ latch1/G (DLH_X1) 0.05 0.05 ^ latch1/Q (DLH_X1) 0.00 0.05 ^ reg1/D (DFF_X1) 0.05 data arrival time 0.00 0.00 clock clk (rise edge) 0.00 0.00 clock network delay (ideal) 0.00 0.00 clock reconvergence pessimism 0.00 ^ reg1/CK (DFF_X1) 0.01 0.01 library hold time 0.01 data required time --------------------------------------------------------- 0.01 data required time -0.05 data arrival time --------------------------------------------------------- 0.05 slack (MET) --- report_checks format short --- Startpoint: latch1 (positive level-sensitive latch clocked by clk) Endpoint: latch2 (positive level-sensitive latch clocked by clk) Path Group: clk Path Type: max Startpoint: latch1 (positive level-sensitive latch clocked by clk) Endpoint: reg1 (rising edge-triggered flip-flop clocked by clk) Path Group: clk Path Type: min --- report_checks format end --- max_delay/setup group clk Required Actual Endpoint Delay Delay Slack ------------------------------------------------------------ latch2/D (DLH_X1) 1.11 1.11 0.00 (MET) min_delay/hold group clk Required Actual Endpoint Delay Delay Slack ------------------------------------------------------------ reg1/D (DFF_X1) 0.01 0.05 0.05 (MET) --- report_checks format summary --- Startpoint Endpoint Slack -------------------------------------------------------------------------------- latch1/Q (DLH_X1) latch2/D (DLH_X1) 0.00 Startpoint Endpoint Slack -------------------------------------------------------------------------------- latch1/Q (DFF_X1) reg1/D (DFF_X1) 0.05 --- report_checks format json --- {"checks": [ { "type": "latch_check", "path_group": "clk", "path_type": "max", "startpoint": "latch1/Q", "endpoint": "latch2/D", "source_clock": "clk", "source_clock_edge": "rise", "source_clock_path": [ { "instance": "", "cell": "search_latch", "verilog_src": "", "pin": "clk", "arrival": 0.000e+00, "capacitance": 2.921e-15, "slew": 0.000e+00 }, { "instance": "latch1", "cell": "DLH_X1", "verilog_src": "", "pin": "latch1/G", "net": "clk", "arrival": 0.000e+00, "slew": 0.000e+00 } ], "source_path": [ { "instance": "latch1", "cell": "DLH_X1", "verilog_src": "", "pin": "latch1/Q", "net": "n3", "arrival": 1.106e-09, "capacitance": 1.932e-15, "slew": 1.074e-11 }, { "instance": "latch2", "cell": "DLH_X1", "verilog_src": "", "pin": "latch2/D", "net": "n3", "arrival": 1.106e-09, "slew": 1.074e-11 } ], "target_clock": "clk", "target_clock_edge": "rise", "target_clock_path": [ { "instance": "", "cell": "search_latch", "verilog_src": "", "pin": "clk", "arrival": 0.000e+00, "capacitance": 2.921e-15, "slew": 0.000e+00 }, { "instance": "latch2", "cell": "DLH_X1", "verilog_src": "", "pin": "latch2/G", "net": "clk", "arrival": 0.000e+00, "slew": 0.000e+00 } ], "data_arrival_time": 1.106e-09, "crpr": 0.000e+00, "margin": 5.497e-11, "required_time": 1.106e-09, "slack": 0.000e+00 } ] } {"checks": [ { "type": "check", "path_group": "clk", "path_type": "min", "startpoint": "latch1/Q", "endpoint": "reg1/D", "source_clock": "clk", "source_clock_edge": "rise", "source_clock_path": [ { "instance": "", "cell": "search_latch", "verilog_src": "", "pin": "clk", "arrival": 0.000e+00, "capacitance": 2.921e-15, "slew": 0.000e+00 }, { "instance": "latch1", "cell": "DLH_X1", "verilog_src": "", "pin": "latch1/G", "net": "clk", "arrival": 0.000e+00, "slew": 0.000e+00 } ], "source_path": [ { "instance": "latch1", "cell": "DLH_X1", "verilog_src": "", "pin": "latch1/Q", "net": "n3", "arrival": 5.291e-11, "capacitance": 2.054e-15, "slew": 9.761e-12 }, { "instance": "reg1", "cell": "DFF_X1", "verilog_src": "", "pin": "reg1/D", "net": "n3", "arrival": 5.291e-11, "slew": 9.761e-12 } ], "target_clock": "clk", "target_clock_edge": "rise", "target_clock_path": [ { "instance": "", "cell": "search_latch", "verilog_src": "", "pin": "clk", "arrival": 0.000e+00, "capacitance": 2.921e-15, "slew": 0.000e+00 }, { "instance": "reg1", "cell": "DFF_X1", "verilog_src": "", "pin": "reg1/CK", "net": "clk", "arrival": 0.000e+00, "slew": 0.000e+00 } ], "data_arrival_time": 5.291e-11, "crpr": 0.000e+00, "margin": 6.024e-12, "required_time": 6.024e-12, "slack": 4.688e-11 } ] } --- report_checks format slack_only --- Group Slack -------------------------------------------- clk 0.00 Group Slack -------------------------------------------- clk 0.05 --- find_timing_paths latch check --- Warning 502: search_latch_timing.tcl line 1, find_timing_paths -endpoint_count is deprecated. Use -endpoint_path_count instead. Found 18 max paths is_latch_check: 1 is_check: 0 pin=latch2/D slack=0.0 is_latch_check: 1 is_check: 0 pin=latch2/D slack=0.0 is_latch_check: 1 is_check: 0 pin=latch1/D slack=0.0 is_latch_check: 1 is_check: 0 pin=latch1/D slack=0.0 is_latch_check: 1 is_check: 0 pin=latch1/D slack=0.0 is_latch_check: 1 is_check: 0 pin=latch1/D slack=0.0 is_latch_check: 1 is_check: 0 pin=latch2/D slack=0.0 is_latch_check: 1 is_check: 0 pin=latch2/D slack=0.0 is_latch_check: 0 is_check: 0 pin=out1 slack=6.813221542500969e-9 is_latch_check: 0 is_check: 0 pin=out1 slack=6.868384527791704e-9 is_latch_check: 0 is_check: 0 pin=out2 slack=7.899713772019368e-9 is_latch_check: 0 is_check: 0 pin=out2 slack=7.901434173618327e-9 is_latch_check: 0 is_check: 0 pin=out1 slack=7.923797618047956e-9 is_latch_check: 0 is_check: 0 pin=out1 slack=7.934120027641711e-9 is_latch_check: 0 is_check: 1 pin=reg1/D slack=8.852826915983769e-9 is_latch_check: 0 is_check: 1 pin=reg1/D slack=8.88718165725777e-9 is_latch_check: 0 is_check: 1 pin=reg1/D slack=9.902577424725223e-9 is_latch_check: 0 is_check: 1 pin=reg1/D slack=9.91532278504792e-9 --- find_timing_paths min latch --- Warning 502: search_latch_timing.tcl line 1, find_timing_paths -endpoint_count is deprecated. Use -endpoint_path_count instead. Found 12 min paths is_latch_check: 0 is_check: 1 pin=reg1/D slack=4.688082214099332e-11 is_latch_check: 0 is_check: 1 pin=reg1/D slack=5.435544375709256e-11 is_latch_check: 0 is_check: 0 pin=out1 slack=2.065880133628184e-9 is_latch_check: 0 is_check: 0 pin=out1 slack=2.076201877088124e-9 is_latch_check: 0 is_check: 0 pin=out2 slack=2.0985655435623585e-9 is_latch_check: 0 is_check: 0 pin=out2 slack=2.1002859451613176e-9 is_latch_check: 0 is_check: 1 pin=latch2/D slack=5.041872697120198e-9 is_latch_check: 0 is_check: 1 pin=latch2/D slack=5.044073603244215e-9 is_latch_check: 0 is_check: 1 pin=latch1/D slack=6.033108235214968e-9 is_latch_check: 0 is_check: 1 pin=latch1/D slack=6.034398758458792e-9 is_latch_check: 0 is_check: 1 pin=latch1/D slack=6.034420962919285e-9 is_latch_check: 0 is_check: 1 pin=latch1/D slack=6.036642297146955e-9 --- Latch path reports with fields --- Startpoint: latch1 (positive level-sensitive latch clocked by clk) Endpoint: latch2 (positive level-sensitive latch clocked by clk) Path Group: clk Path Type: max Fanout Cap Slew Delay Time Description ----------------------------------------------------------------------------- 0.00 0.00 0.00 clock clk (rise edge) 0.00 0.00 clock network delay (ideal) 1.05 1.05 time given to startpoint 0.00 0.00 1.05 v latch1/D (DLH_X1) 2 1.93 0.01 0.06 1.11 v latch1/Q (DLH_X1) n3 (net) 0.01 0.00 1.11 v latch2/D (DLH_X1) 1.11 data arrival time 0.00 0.00 0.00 clock clk (rise edge) 0.00 0.00 clock network delay (ideal) 0.00 0.00 clock reconvergence pessimism 0.00 ^ latch2/G (DLH_X1) 1.11 1.11 time borrowed from endpoint 1.11 data required time ----------------------------------------------------------------------------- 1.11 data required time -1.11 data arrival time ----------------------------------------------------------------------------- 0.00 slack (MET) Time Borrowing Information -------------------------------------------- clk pulse width 5.00 library setup time -0.05 -------------------------------------------- max time borrow 4.95 actual time borrow 1.11 -------------------------------------------- Startpoint: latch1 (positive level-sensitive latch clocked by clk) Endpoint: reg1 (rising edge-triggered flip-flop clocked by clk) Path Group: clk Path Type: min Fanout Cap Slew Delay Time Description ----------------------------------------------------------------------------- 0.00 0.00 0.00 clock clk (rise edge) 0.00 0.00 clock network delay (ideal) 0.00 0.00 0.00 ^ latch1/G (DLH_X1) 2 2.05 0.01 0.05 0.05 ^ latch1/Q (DLH_X1) n3 (net) 0.01 0.00 0.05 ^ reg1/D (DFF_X1) 0.05 data arrival time 0.00 0.00 0.00 clock clk (rise edge) 0.00 0.00 clock network delay (ideal) 0.00 0.00 clock reconvergence pessimism 0.00 ^ reg1/CK (DFF_X1) 0.01 0.01 library hold time 0.01 data required time ----------------------------------------------------------------------------- 0.01 data required time -0.05 data arrival time ----------------------------------------------------------------------------- 0.05 slack (MET) --- set_max_time_borrow --- Startpoint: latch1 (positive level-sensitive latch clocked by clk) Endpoint: latch2 (positive level-sensitive latch clocked by clk) Path Group: clk Path Type: max Delay Time Description --------------------------------------------------------- 0.00 0.00 clock clk (rise edge) 0.00 0.00 clock network delay (ideal) 1.05 1.05 time given to startpoint 0.00 1.05 v latch1/D (DLH_X1) 0.06 1.11 v latch1/Q (DLH_X1) 0.00 1.11 v latch2/D (DLH_X1) 1.11 data arrival time 0.00 0.00 clock clk (rise edge) 0.00 0.00 clock network delay (ideal) 0.00 0.00 clock reconvergence pessimism 0.00 ^ latch2/G (DLH_X1) 1.11 1.11 time borrowed from endpoint 1.11 data required time --------------------------------------------------------- 1.11 data required time -1.11 data arrival time --------------------------------------------------------- 0.00 slack (MET) Time Borrowing Information -------------------------------------------- clk pulse width 5.00 library setup time -0.05 -------------------------------------------- max time borrow 4.95 actual time borrow 1.11 -------------------------------------------- Startpoint: latch1 (positive level-sensitive latch clocked by clk) Endpoint: latch2 (positive level-sensitive latch clocked by clk) Path Group: clk Path Type: max Delay Time Description --------------------------------------------------------- 0.00 0.00 clock clk (rise edge) 0.00 0.00 clock network delay (ideal) 1.05 1.05 time given to startpoint 0.00 1.05 v latch1/D (DLH_X1) 0.06 1.11 v latch1/Q (DLH_X1) 0.00 1.11 v latch2/D (DLH_X1) 1.11 data arrival time 0.00 0.00 clock clk (rise edge) 0.00 0.00 clock network delay (ideal) 0.00 0.00 clock reconvergence pessimism 0.00 ^ latch2/G (DLH_X1) 1.11 1.11 time borrowed from endpoint 1.11 data required time --------------------------------------------------------- 1.11 data required time -1.11 data arrival time --------------------------------------------------------- 0.00 slack (MET) Time Borrowing Information -------------------------------------------- clk pulse width 5.00 library setup time -0.05 -------------------------------------------- max time borrow 4.95 actual time borrow 1.11 -------------------------------------------- Startpoint: latch1 (positive level-sensitive latch clocked by clk) Endpoint: latch2 (positive level-sensitive latch clocked by clk) Path Group: clk Path Type: max Delay Time Description --------------------------------------------------------- 0.00 0.00 clock clk (rise edge) 0.00 0.00 clock network delay (ideal) 1.05 1.05 time given to startpoint 0.00 1.05 v latch1/D (DLH_X1) 0.06 1.11 v latch1/Q (DLH_X1) 0.00 1.11 v latch2/D (DLH_X1) 1.11 data arrival time 0.00 0.00 clock clk (rise edge) 0.00 0.00 clock network delay (ideal) 0.00 0.00 clock reconvergence pessimism 0.00 ^ latch2/G (DLH_X1) 1.11 1.11 time borrowed from endpoint 1.11 data required time --------------------------------------------------------- 1.11 data required time -1.11 data arrival time --------------------------------------------------------- 0.00 slack (MET) Time Borrowing Information -------------------------------------------- user max time borrow 4.00 actual time borrow 1.11 -------------------------------------------- --- report_clock_properties --- Clock Period Waveform ---------------------------------------------------- clk 10.00 0.00 5.00 --- report_clock_skew --- Clock clk 0.00 source latency latch1/G ^ 0.00 target latency latch2/G v 0.00 CRPR -------------- 0.00 setup skew Clock clk 0.00 source latency latch1/G ^ 0.00 target latency latch2/G v 0.00 CRPR -------------- 0.00 hold skew --- all_registers -level_sensitive --- Level-sensitive cells: 2 latch1 latch2 Level-sensitive data pins: 2 latch1/D latch2/D Level-sensitive clock pins: 2 latch1/G latch2/G Level-sensitive output pins: 2 latch1/Q latch2/Q --- all_registers -edge_triggered --- Edge-triggered cells: 1 reg1 --- pulse width checks --- Required Actual Pin Width Width Slack ------------------------------------------------------------ reg1/CK (high) 0.05 5.00 4.95 (MET) Pin: reg1/CK Check: sequential_clock_pulse_width Delay Time Description --------------------------------------------------------- 0.00 0.00 clock clk (rise edge) 0.00 0.00 clock network delay (ideal) 0.00 0.00 reg1/CK 0.00 open edge arrival time 5.00 5.00 clock clk (fall edge) 0.00 5.00 clock network delay (ideal) 0.00 5.00 reg1/CK 0.00 5.00 clock reconvergence pessimism 5.00 close edge arrival time --------------------------------------------------------- 0.05 required pulse width (high) 5.00 actual pulse width --------------------------------------------------------- 4.95 slack (MET) --- min period --- clk period_min = 1.15 fmax = 871.71 clk period_min = 3.19 fmax = 313.80