sta_module_tests("search"
  TESTS
    analysis
    annotated_write_verilog
    assigned_delays
    check_timing
    check_types_deep
    clk_skew_interclk
    clk_skew_multiclock
    corner_skew
    crpr
    crpr_data_checks
    data_check_gated
    exception_paths
    fanin_fanout
    fanin_fanout_deep
    gated_clk
    genclk
    genclk_latch_deep
    genclk_property_report
    json_unconstrained
    latch
    latch_timing
    levelize_loop_disabled
    levelize_sim
    limit_violations
    limits_verbose
    min_period_max_skew
    min_period_short
    multiclock
    multicorner_analysis
    network_edit_deep
    network_edit_replace
    network_sta_deep
    path_delay_output
    path_end_types
    path_enum_deep
    path_enum_groups
    path_enum_nworst
    port_pin_properties
    power_activity
    property
    property_deep
    property_extra
    property_inst_cell
    property_libport_deep
    pvt_analysis
    register
    register_deep
    register_filter_combos
    register_latch_sim
    report_fields_formats
    report_formats
    report_gated_datacheck
    report_json_formats
    report_path_detail
    report_path_expanded
    report_path_latch_expanded
    report_path_pvt_cap
    report_path_types
    sdc_advanced
    search_arrival_required
    sim_const_prop
    sim_logic_clk_network
    spef_parasitics
    sta_bidirect_extcap
    sta_cmds
    sta_extra
    tag_path_analysis
    timing
    timing_model
    timing_model_clktree
    timing_model_deep
    timing_model_readback
    worst_slack_sta
    write_sdf_model
)

add_subdirectory(cpp)