--- LibertyPort drive_resistance properties --- BUF_X1/Z drive_resistance: 2.327937 BUF_X1/Z drive_resistance_min_rise: 2.327937 BUF_X1/Z drive_resistance_max_rise: 2.327937 BUF_X1/Z drive_resistance_min_fall: 1.083897 BUF_X1/Z drive_resistance_max_fall: 1.083897 --- More drive_resistance on different cells --- AND2_X1/ZN drive_resistance: 2.333555 AND2_X1/ZN drive_resistance_min_rise: 2.333449 AND2_X1/ZN drive_resistance_max_fall: 1.085789 INV_X1/ZN drive_resistance: 2.322186 INV_X1/ZN drive_resistance_min_rise: 2.322186 INV_X1/ZN drive_resistance_max_fall: 1.071745 --- LibertyPort intrinsic_delay properties --- BUF_X1/Z intrinsic_delay: 0.018876 BUF_X1/Z intrinsic_delay_min_rise: 0.013565 BUF_X1/Z intrinsic_delay_max_rise: 0.013565 BUF_X1/Z intrinsic_delay_min_fall: 0.018876 BUF_X1/Z intrinsic_delay_max_fall: 0.018876 --- intrinsic_delay on AND --- AND2_X1/ZN intrinsic_delay: 0.022618 AND2_X1/ZN intrinsic_delay_min_rise: 0.021327 AND2_X1/ZN intrinsic_delay_max_rise: 0.022618 AND2_X1/ZN intrinsic_delay_min_fall: 0.020427 AND2_X1/ZN intrinsic_delay_max_fall: 0.022613 --- intrinsic_delay on INV --- INV_X1/ZN intrinsic_delay: 0.004075 INV_X1/ZN intrinsic_delay_min_rise: 0.004075 INV_X1/ZN intrinsic_delay_max_fall: 0.002482 --- LibertyPort lib_cell and clock properties --- BUF_X1/A capacitance: 0.974659 BUF_X1/A lib_cell: BUF_X1 BUF_X1/A is_clock: 0 BUF_X1/A is_register_clock: 0 DFF_X1/CK is_clock: 1 DFF_X1/CK is_register_clock: 1 DFF_X1/CK capacitance: 0.949653 DFF_X1/CK lib_cell: DFF_X1 DFF_X1/D is_clock: 0 DFF_X1/D is_register_clock: 0 DFF_X1/D capacitance: 1.140290 --- Instance is_* properties --- buf1 is_buffer: 1 buf1 is_inverter: 0 buf1 is_clock_gate: 0 buf1 is_macro: 0 buf1 is_memory: 0 buf1 is_hierarchical: 0 inv1 is_buffer: 0 inv1 is_inverter: 1 inv1 is_clock_gate: 0 and1 is_buffer: 0 and1 is_inverter: 0 reg1 is_buffer: 0 reg1 is_inverter: 0 reg1 is_macro: 0 reg1 is_memory: 0 --- LibertyCell area and leakage --- DFF_X1 area: 4.522000 BUF_X1 area: 0.798000 INV_X1 area: 0.532000 AND2_X1 area: 1.064000 --- group_path matching --- --- report_checks with groups --- Startpoint: in2 (input port clocked by clk) Endpoint: reg1 (rising edge-triggered flip-flop clocked by clk) Path Group: input_grp Path Type: max Delay Time Description --------------------------------------------------------- 0.00 0.00 clock clk (rise edge) 0.00 0.00 clock network delay (ideal) 1.50 1.50 v input external delay 0.00 1.50 v in2 (in) 0.02 1.52 v and1/ZN (AND2_X1) 0.04 1.57 v or1/ZN (OR2_X1) 0.03 1.59 v buf1/Z (BUF_X1) 0.01 1.60 ^ inv1/ZN (INV_X1) 0.02 1.62 ^ buf2/Z (BUF_X2) 0.00 1.62 ^ reg1/D (DFF_X1) 1.62 data arrival time 10.00 10.00 clock clk (rise edge) 0.00 10.00 clock network delay (ideal) 0.00 10.00 clock reconvergence pessimism 10.00 ^ reg1/CK (DFF_X1) -0.03 9.97 library setup time 9.97 data required time --------------------------------------------------------- 9.97 data required time -1.62 data arrival time --------------------------------------------------------- 8.35 slack (MET) Startpoint: reg2 (rising edge-triggered flip-flop clocked by clk) Endpoint: out1 (output port clocked by clk) Path Group: output_grp Path Type: max Delay Time Description --------------------------------------------------------- 0.00 0.00 clock clk (rise edge) 0.00 0.00 clock network delay (ideal) 0.00 0.00 ^ reg2/CK (DFF_X1) 0.08 0.08 ^ reg2/Q (DFF_X1) 0.00 0.08 ^ out1 (out) 0.08 data arrival time 10.00 10.00 clock clk (rise edge) 0.00 10.00 clock network delay (ideal) 0.00 10.00 clock reconvergence pessimism -2.00 8.00 output external delay 8.00 data required time --------------------------------------------------------- 8.00 data required time -0.08 data arrival time --------------------------------------------------------- 7.92 slack (MET) Startpoint: reg1 (rising edge-triggered flip-flop clocked by clk) Endpoint: reg2 (rising edge-triggered flip-flop clocked by clk) Path Group: reg2reg_grp Path Type: max Delay Time Description --------------------------------------------------------- 0.00 0.00 clock clk (rise edge) 0.00 0.00 clock network delay (ideal) 0.00 0.00 ^ reg1/CK (DFF_X1) 0.08 0.08 v reg1/Q (DFF_X1) 0.03 0.11 v buf3/Z (BUF_X1) 0.00 0.11 v reg2/D (DFF_X1) 0.11 data arrival time 10.00 10.00 clock clk (rise edge) 0.00 10.00 clock network delay (ideal) 0.00 10.00 clock reconvergence pessimism 10.00 ^ reg2/CK (DFF_X1) -0.04 9.96 library setup time 9.96 data required time --------------------------------------------------------- 9.96 data required time -0.11 data arrival time --------------------------------------------------------- 9.85 slack (MET) Startpoint: in2 (input port clocked by clk) Endpoint: reg1 (rising edge-triggered flip-flop clocked by clk) Path Group: through_grp Path Type: max Delay Time Description --------------------------------------------------------- 0.00 0.00 clock clk (rise edge) 0.00 0.00 clock network delay (ideal) 1.50 1.50 v input external delay 0.00 1.50 v in2 (in) 0.02 1.52 v and1/ZN (AND2_X1) 0.04 1.57 v or1/ZN (OR2_X1) 0.03 1.59 v buf1/Z (BUF_X1) 0.01 1.60 ^ inv1/ZN (INV_X1) 0.02 1.62 ^ buf2/Z (BUF_X2) 0.00 1.62 ^ reg1/D (DFF_X1) 1.62 data arrival time 10.00 10.00 clock clk (rise edge) 0.00 10.00 clock network delay (ideal) 0.00 10.00 clock reconvergence pessimism 10.00 ^ reg1/CK (DFF_X1) -0.03 9.97 library setup time 9.97 data required time --------------------------------------------------------- 9.97 data required time -1.62 data arrival time --------------------------------------------------------- 8.35 slack (MET) --- find_timing_paths with group_path --- Warning 502: search_property_libport_deep.tcl line 1, find_timing_paths -endpoint_count is deprecated. Use -endpoint_path_count instead. Found 18 paths with groups --- find_timing_paths with min paths and groups --- Warning 502: search_property_libport_deep.tcl line 1, find_timing_paths -endpoint_count is deprecated. Use -endpoint_path_count instead. Found 18 min paths with groups --- path_group_names --- Path group names: clk input_grp output_grp reg2reg_grp through_grp asynchronous {path delay} {gated clock} unconstrained input_grp is group: 1 nonexistent is group: 0 --- TimingArcSet properties on DFF_X1 --- DFF_X1 arc: DFF_X1 CK -> D / DFF_X1 CK -> D DFF_X1 arc: DFF_X1 CK -> D / DFF_X1 CK -> D DFF_X1 arc: DFF_X1 CK -> CK / DFF_X1 CK -> CK DFF_X1 arc: DFF_X1 CK -> Q / DFF_X1 CK -> Q DFF_X1 arc: DFF_X1 CK -> QN / DFF_X1 CK -> QN --- TimingArcSet properties on DFFR_X1 --- DFFR_X1 arc: DFFR_X1 CK -> D DFFR_X1 arc: DFFR_X1 CK -> D DFFR_X1 arc: DFFR_X1 CK -> RN DFFR_X1 arc: DFFR_X1 CK -> RN DFFR_X1 arc: DFFR_X1 RN -> RN DFFR_X1 arc: DFFR_X1 CK -> CK DFFR_X1 arc: DFFR_X1 CK -> Q DFFR_X1 arc: DFFR_X1 RN -> Q DFFR_X1 arc: DFFR_X1 RN -> Q DFFR_X1 arc: DFFR_X1 RN -> Q DFFR_X1 arc: DFFR_X1 RN -> Q DFFR_X1 arc: DFFR_X1 CK -> QN DFFR_X1 arc: DFFR_X1 RN -> QN DFFR_X1 arc: DFFR_X1 RN -> QN DFFR_X1 arc: DFFR_X1 RN -> QN DFFR_X1 arc: DFFR_X1 RN -> QN --- TimingArcSet properties on OR2_X1 --- OR2_X1 arc: OR2_X1 A1 -> ZN / OR2_X1 A1 -> ZN OR2_X1 arc: OR2_X1 A2 -> ZN / OR2_X1 A2 -> ZN --- Pin is_hierarchical/is_port --- reg1/D is_hierarchical: 0 reg1/D is_port: 0 --- LibertyPort direction varieties --- DFF_X1/Q direction: output DFF_X1/D direction: input DFF_X1/CK direction: input --- Unknown property errors --- LibertyPort BUF_X1/Z full_name: Z Instance reg1 ref_name: DFF_X1 Clock clk period: 10.000000 LibertyCell BUF_X1 area: 0.798000 Library NangateOpenCellLibrary filename: ../../test/nangate45/Nangate45_typ.lib