--- write_sdf ---
No differences found.
--- write_sdf with options ---
No differences found.
--- write_sdf with digits ---
No differences found.
--- write_sdf with include_typ ---
No differences found.
--- write_timing_model ---
--- write_timing_model with cell_name ---
--- write_timing_model with library_name ---
--- Network edit: make_instance ---
make_instance new_buf1 done
--- Network edit: make_net ---
make_net new_net1 done
--- Network edit: connect_pin ---
connect_pin done
--- Network edit: disconnect_pin ---
disconnect_pin done
--- Network edit: delete_net ---
delete_net done
--- Network edit: delete_instance ---
delete_instance done
--- Network edit: replace_cell ---
Startpoint: reg1 (rising edge-triggered flip-flop clocked by clk)
Endpoint: out1 (output port clocked by clk)
Path Group: clk
Path Type: max

  Delay    Time   Description
---------------------------------------------------------
   0.00    0.00   clock clk (rise edge)
   0.00    0.00   clock network delay (ideal)
   0.00    0.00 ^ reg1/CK (DFF_X1)
   0.08    0.08 ^ reg1/Q (DFF_X1)
   0.02    0.10 ^ buf2/Z (BUF_X1)
   0.00    0.10 ^ out1 (out)
           0.10   data arrival time

  10.00   10.00   clock clk (rise edge)
   0.00   10.00   clock network delay (ideal)
   0.00   10.00   clock reconvergence pessimism
  -2.00    8.00   output external delay
           8.00   data required time
---------------------------------------------------------
           8.00   data required time
          -0.10   data arrival time
---------------------------------------------------------
           7.90   slack (MET)


replace_cell done
--- report_checks after edits ---
Startpoint: reg1 (rising edge-triggered flip-flop clocked by clk)
Endpoint: out1 (output port clocked by clk)
Path Group: clk
Path Type: max

  Delay    Time   Description
---------------------------------------------------------
   0.00    0.00   clock clk (rise edge)
   0.00    0.00   clock network delay (ideal)
   0.00    0.00 ^ reg1/CK (DFF_X1)
   0.08    0.08 ^ reg1/Q (DFF_X1)
   0.02    0.10 ^ buf2/Z (BUF_X1)
   0.00    0.10 ^ out1 (out)
           0.10   data arrival time

  10.00   10.00   clock clk (rise edge)
   0.00   10.00   clock network delay (ideal)
   0.00   10.00   clock reconvergence pessimism
  -2.00    8.00   output external delay
           8.00   data required time
---------------------------------------------------------
           8.00   data required time
          -0.10   data arrival time
---------------------------------------------------------
           7.90   slack (MET)


Startpoint: in1 (input port clocked by clk)
Endpoint: reg1 (rising edge-triggered flip-flop clocked by clk)
Path Group: clk
Path Type: min

  Delay    Time   Description
---------------------------------------------------------
   0.00    0.00   clock clk (rise edge)
   0.00    0.00   clock network delay (ideal)
   1.00    1.00 ^ input external delay
   0.00    1.00 ^ in1 (in)
   0.03    1.03 ^ and1/ZN (AND2_X1)
   0.02    1.05 ^ buf1/Z (BUF_X2)
   0.00    1.05 ^ reg1/D (DFF_X1)
           1.05   data arrival time

   0.00    0.00   clock clk (rise edge)
   0.00    0.00   clock network delay (ideal)
   0.00    0.00   clock reconvergence pessimism
           0.00 ^ reg1/CK (DFF_X1)
   0.00    0.00   library hold time
           0.00   data required time
---------------------------------------------------------
           0.00   data required time
          -1.05   data arrival time
---------------------------------------------------------
           1.04   slack (MET)


--- write_timing_model after edits ---
--- write_sdf after edits ---
No differences found.