--- report_path_cmd on a path --- Delay Time Description --------------------------------------------------------- 0.00 0.00 clock clk (rise edge) 0.00 0.00 clock network delay (ideal) 0.00 0.00 ^ reg1/CK (DFF_X1) 0.08 0.08 ^ reg1/Q (DFF_X1) 0.02 0.10 ^ buf2/Z (BUF_X1) 0.00 0.10 ^ out1 (out) --- report_path with json format --- { "path": [ { "instance": "reg1", "cell": "DFF_X1", "verilog_src": "", "pin": "reg1/Q", "net": "n3", "arrival": 8.371e-11, "capacitance": 9.747e-16, "slew": 7.314e-12 }, { "instance": "buf2", "cell": "BUF_X1", "verilog_src": "", "pin": "buf2/A", "net": "n3", "arrival": 8.371e-11, "slew": 7.314e-12 }, { "instance": "buf2", "cell": "BUF_X1", "verilog_src": "", "pin": "buf2/Z", "net": "out1", "arrival": 1.003e-10, "capacitance": 0.000e+00, "slew": 3.638e-12 }, { "instance": "", "cell": "search_test1", "verilog_src": "", "pin": "out1", "arrival": 1.003e-10, "slew": 3.638e-12 } ] } --- worstSlack single-arg form --- worst_slack: 7.899713772019368e-9 --- checkFanout via report_check_types --- max fanout Pin in1 max fanout 2 fanout 1 ----------------- Slack 1 (MET) --- report_checks with -fields and various combos --- Startpoint: reg1 (rising edge-triggered flip-flop clocked by clk) Endpoint: out1 (output port clocked by clk) Path Group: clk Path Type: max Fanout Cap Slew Delay Time Description ----------------------------------------------------------------------------- 0.00 0.00 0.00 clock clk (rise edge) 0.00 0.00 clock network delay (ideal) 0.00 0.00 0.00 ^ reg1/CK (DFF_X1) 1 0.97 0.01 0.08 0.08 ^ reg1/Q (DFF_X1) 1 0.00 0.00 0.02 0.10 ^ buf2/Z (BUF_X1) 0.00 0.00 0.10 ^ out1 (out) 0.10 data arrival time 0.00 10.00 10.00 clock clk (rise edge) 0.00 10.00 clock network delay (ideal) 0.00 10.00 clock reconvergence pessimism -2.00 8.00 output external delay 8.00 data required time ----------------------------------------------------------------------------- 8.00 data required time -0.10 data arrival time ----------------------------------------------------------------------------- 7.90 slack (MET) Startpoint: reg1 (rising edge-triggered flip-flop clocked by clk) Endpoint: out1 (output port clocked by clk) Path Group: clk Path Type: max Delay Time Description --------------------------------------------------------- 0.00 0.00 clock clk (rise edge) 0.00 0.00 clock network delay (ideal) 0.00 0.00 ^ reg1/CK (DFF_X1) 0.08 0.08 ^ reg1/Q (DFF_X1) n3 (net) 0.00 0.08 ^ buf2/A (BUF_X1) 0.02 0.10 ^ buf2/Z (BUF_X1) out1 (net) 0.00 0.10 ^ out1 (out) 0.10 data arrival time 10.00 10.00 clock clk (rise edge) 0.00 10.00 clock network delay (ideal) 0.00 10.00 clock reconvergence pessimism -2.00 8.00 output external delay 8.00 data required time --------------------------------------------------------- 8.00 data required time -0.10 data arrival time --------------------------------------------------------- 7.90 slack (MET) Startpoint: reg1 (rising edge-triggered flip-flop clocked by clk) Endpoint: out1 (output port clocked by clk) Path Group: clk Path Type: max Fanout Cap Slew Delay Time Description Src Attr --------------------------------------------------------------------------------------------------------------------- 0.00 0.00 0.00 clock clk (rise edge) 0.00 0.00 clock network delay (ideal) 0.00 0.00 0.00 ^ reg1/CK (DFF_X1) 1 0.97 0.01 0.08 0.08 ^ reg1/Q (DFF_X1) n3 (net) 0.01 0.00 0.08 ^ buf2/A (BUF_X1) 1 0.00 0.00 0.02 0.10 ^ buf2/Z (BUF_X1) out1 (net) 0.00 0.00 0.10 ^ out1 (out) 0.10 data arrival time 0.00 10.00 10.00 clock clk (rise edge) 0.00 10.00 clock network delay (ideal) 0.00 10.00 clock reconvergence pessimism -2.00 8.00 output external delay 8.00 data required time --------------------------------------------------------------------------------------------------------------------- 8.00 data required time -0.10 data arrival time --------------------------------------------------------------------------------------------------------------------- 7.90 slack (MET) Startpoint: reg1 (rising edge-triggered flip-flop clocked by clk) Endpoint: out1 (output port clocked by clk) Path Group: clk Path Type: max Fanout Cap Slew Delay Time Description Src Attr --------------------------------------------------------------------------------------------------------------------- 0.00 0.00 0.00 clock clk (rise edge) 0.00 0.00 clock network delay (ideal) 0.00 0.00 0.00 ^ reg1/CK (DFF_X1) 1 0.97 0.01 0.08 0.08 ^ reg1/Q (DFF_X1) n3 (net) 0.01 0.00 0.08 ^ buf2/A (BUF_X1) 1 0.00 0.00 0.02 0.10 ^ buf2/Z (BUF_X1) out1 (net) 0.00 0.00 0.10 ^ out1 (out) 0.10 data arrival time 0.00 10.00 10.00 clock clk (rise edge) 0.00 10.00 clock network delay (ideal) 0.00 10.00 clock reconvergence pessimism -2.00 8.00 output external delay 8.00 data required time --------------------------------------------------------------------------------------------------------------------- 8.00 data required time -0.10 data arrival time --------------------------------------------------------------------------------------------------------------------- 7.90 slack (MET) Startpoint: reg1 (rising edge-triggered flip-flop clocked by clk) Endpoint: out1 (output port clocked by clk) Path Group: clk Path Type: max max_delay/setup group clk Required Actual Endpoint Delay Delay Slack ------------------------------------------------------------ out1 (output) 8.00 0.10 7.90 (MET) --- report_checks with -slack_min and -slack_max --- No paths found. Startpoint: reg1 (rising edge-triggered flip-flop clocked by clk) Endpoint: out1 (output port clocked by clk) Path Group: clk Path Type: max Delay Time Description --------------------------------------------------------- 0.00 0.00 clock clk (rise edge) 0.00 0.00 clock network delay (ideal) 0.00 0.00 ^ reg1/CK (DFF_X1) 0.08 0.08 ^ reg1/Q (DFF_X1) 0.02 0.10 ^ buf2/Z (BUF_X1) 0.00 0.10 ^ out1 (out) 0.10 data arrival time 10.00 10.00 clock clk (rise edge) 0.00 10.00 clock network delay (ideal) 0.00 10.00 clock reconvergence pessimism -2.00 8.00 output external delay 8.00 data required time --------------------------------------------------------- 8.00 data required time -0.10 data arrival time --------------------------------------------------------- 7.90 slack (MET) Startpoint: reg1 (rising edge-triggered flip-flop clocked by clk) Endpoint: out1 (output port clocked by clk) Path Group: clk Path Type: max Delay Time Description --------------------------------------------------------- 0.00 0.00 clock clk (rise edge) 0.00 0.00 clock network delay (ideal) 0.00 0.00 ^ reg1/CK (DFF_X1) 0.08 0.08 ^ reg1/Q (DFF_X1) 0.02 0.10 ^ buf2/Z (BUF_X1) 0.00 0.10 ^ out1 (out) 0.10 data arrival time 10.00 10.00 clock clk (rise edge) 0.00 10.00 clock network delay (ideal) 0.00 10.00 clock reconvergence pessimism -2.00 8.00 output external delay 8.00 data required time --------------------------------------------------------- 8.00 data required time -0.10 data arrival time --------------------------------------------------------- 7.90 slack (MET) --- set_report_path_field_properties --- Warning 1575: unknown report path field delay Startpoint: reg1 (rising edge-triggered flip-flop clocked by clk) Endpoint: out1 (output port clocked by clk) Path Group: clk Path Type: max Delay Time Description --------------------------------------------------------- 0.00 0.00 clock clk (rise edge) 0.00 0.00 clock network delay (ideal) 0.00 0.00 ^ reg1/CK (DFF_X1) 0.08 0.08 ^ reg1/Q (DFF_X1) 0.02 0.10 ^ buf2/Z (BUF_X1) 0.00 0.10 ^ out1 (out) 0.10 data arrival time 10.00 10.00 clock clk (rise edge) 0.00 10.00 clock network delay (ideal) 0.00 10.00 clock reconvergence pessimism -2.00 8.00 output external delay 8.00 data required time --------------------------------------------------------- 8.00 data required time -0.10 data arrival time --------------------------------------------------------- 7.90 slack (MET) --- find_timing_paths with recovery/removal/gating_setup/gating_hold --- Warning 502: search_sta_extra.tcl line 1, find_timing_paths -endpoint_count is deprecated. Use -endpoint_path_count instead. Paths: 5 --- report_annotated_delay --- Not Delay type Total Annotated Annotated ---------------------------------------------------------------- cell arcs 6 0 6 internal net arcs 3 0 3 net arcs from primary inputs 3 0 3 net arcs to primary outputs 1 0 1 ---------------------------------------------------------------- 13 0 13 --- report_annotated_check --- Not Check type Total Annotated Annotated ---------------------------------------------------------------- cell setup arcs 1 0 1 cell hold arcs 1 0 1 cell width arcs 1 0 1 ---------------------------------------------------------------- 3 0 3 --- report_checks with -path_delay max_rise/max_fall/min_rise/min_fall --- max_delay/setup group clk Required Actual Endpoint Delay Delay Slack ------------------------------------------------------------ out1 (output) 8.00 0.10 7.90 (MET) max_delay/setup group clk Required Actual Endpoint Delay Delay Slack ------------------------------------------------------------ out1 (output) 8.00 0.10 7.90 (MET) min_delay/hold group clk Required Actual Endpoint Delay Delay Slack ------------------------------------------------------------ reg1/D (DFF_X1) 0.00 1.04 1.04 (MET) min_delay/hold group clk Required Actual Endpoint Delay Delay Slack ------------------------------------------------------------ reg1/D (DFF_X1) 0.00 1.05 1.04 (MET) --- report_checks with -corner --- Startpoint: reg1 (rising edge-triggered flip-flop clocked by clk) Endpoint: out1 (output port clocked by clk) Path Group: clk Path Type: max Delay Time Description --------------------------------------------------------- 0.00 0.00 clock clk (rise edge) 0.00 0.00 clock network delay (ideal) 0.00 0.00 ^ reg1/CK (DFF_X1) 0.08 0.08 ^ reg1/Q (DFF_X1) 0.02 0.10 ^ buf2/Z (BUF_X1) 0.00 0.10 ^ out1 (out) 0.10 data arrival time 10.00 10.00 clock clk (rise edge) 0.00 10.00 clock network delay (ideal) 0.00 10.00 clock reconvergence pessimism -2.00 8.00 output external delay 8.00 data required time --------------------------------------------------------- 8.00 data required time -0.10 data arrival time --------------------------------------------------------- 7.90 slack (MET) --- set_report_path_no_split --- Startpoint: reg1 (rising edge-triggered flip-flop clocked by clk) Endpoint: out1 (output port clocked by clk) Path Group: clk Path Type: max Delay Time Description --------------------------------------------------------- 0.00 0.00 clock clk (rise edge) 0.00 0.00 clock network delay (ideal) 0.00 0.00 ^ reg1/CK (DFF_X1) 0.08 0.08 ^ reg1/Q (DFF_X1) 0.02 0.10 ^ buf2/Z (BUF_X1) 0.00 0.10 ^ out1 (out) 0.10 data arrival time 10.00 10.00 clock clk (rise edge) 0.00 10.00 clock network delay (ideal) 0.00 10.00 clock reconvergence pessimism -2.00 8.00 output external delay 8.00 data required time --------------------------------------------------------- 8.00 data required time -0.10 data arrival time --------------------------------------------------------- 7.90 slack (MET) --- Edge detailed methods --- sim_timing_sense: positive_unate cond: mode_name: mode_value: is_disabled_loop: 0 is_disabled_constraint: 0 is_disabled_constant: 0 is_disabled_cond_default: 0 is_disabled_bidirect_inst_path: 0 is_disabled_bidirect_net_path: skipped (API removed) is_disabled_preset_clear: 0 disabled_constant_pins count: 0 arc_delays count: 2 arc_delay_strings count: 2 delay_annotated: 0 --- Vertex methods via worst_slack_vertex --- worst_slack_vertex is_clock: skipped (API removed) worst_slack_vertex has_downstream_clk_pin: skipped (API removed) worst_slack_vertex is_disabled_constraint: skipped (API removed) --- Vertex from PathEnd --- pathend vertex is_clock: skipped (API removed) pathend vertex has_downstream_clk_pin: skipped (API removed) --- vertex_worst_arrival_path --- worst_arrival_path pin: out1 --- vertex_worst_slack_path --- worst_slack_path pin: out1 --- report_path_end with prev_end --- --- make_instance --- make_instance: done --- pocv_mode --- pocv_mode: scalar --- report_checks -summary format --- Startpoint Endpoint Slack -------------------------------------------------------------------------------- reg1/Q (search_test1) out1 (output) 7.90 --- clear_sta ---