--- Output delay path formats --- Startpoint: reg1 (rising edge-triggered flip-flop clocked by clk) Endpoint: out1 (output port clocked by clk) Path Group: clk Path Type: max Delay Time Description --------------------------------------------------------- 0.00 0.00 clock clk (rise edge) 0.00 0.00 clock network delay (ideal) 0.00 0.00 ^ reg1/CK (DFF_X1) 0.08 0.08 ^ reg1/Q (DFF_X1) 0.02 0.10 ^ buf2/Z (BUF_X1) 0.00 0.10 ^ out1 (out) 0.10 data arrival time 10.00 10.00 clock clk (rise edge) 0.00 10.00 clock network delay (ideal) 0.00 10.00 clock reconvergence pessimism -2.00 8.00 output external delay 8.00 data required time --------------------------------------------------------- 8.00 data required time -0.10 data arrival time --------------------------------------------------------- 7.90 slack (MET) Startpoint: reg1 (rising edge-triggered flip-flop clocked by clk) Endpoint: out1 (output port clocked by clk) Path Group: clk Path Type: max Delay Time Description --------------------------------------------------------- 0.00 0.00 clock clk (rise edge) 0.00 0.00 clock network delay (ideal) 0.00 0.00 ^ reg1/CK (DFF_X1) 0.08 0.08 ^ reg1/Q (DFF_X1) 0.02 0.10 ^ buf2/Z (BUF_X1) 0.00 0.10 ^ out1 (out) 0.10 data arrival time 10.00 10.00 clock clk (rise edge) 0.00 10.00 clock network delay (ideal) 0.00 10.00 clock reconvergence pessimism -2.00 8.00 output external delay 8.00 data required time --------------------------------------------------------- 8.00 data required time -0.10 data arrival time --------------------------------------------------------- 7.90 slack (MET) Startpoint: reg1 (rising edge-triggered flip-flop clocked by clk) Endpoint: out1 (output port clocked by clk) Path Group: clk Path Type: max Delay Time Description --------------------------------------------------------- 0.00 0.00 clock clk (rise edge) 0.00 0.00 clock network delay (ideal) 0.00 0.00 ^ reg1/CK (DFF_X1) 0.08 0.08 ^ reg1/Q (DFF_X1) 0.02 0.10 ^ buf2/Z (BUF_X1) 0.00 0.10 ^ out1 (out) 0.10 data arrival time 10.00 10.00 clock clk (rise edge) 0.00 10.00 clock network delay (ideal) 0.00 10.00 clock reconvergence pessimism -2.00 8.00 output external delay 8.00 data required time --------------------------------------------------------- 8.00 data required time -0.10 data arrival time --------------------------------------------------------- 7.90 slack (MET) Startpoint: reg1 (rising edge-triggered flip-flop clocked by clk) Endpoint: out1 (output port clocked by clk) Path Group: clk Path Type: max max_delay/setup group clk Required Actual Endpoint Delay Delay Slack ------------------------------------------------------------ out1 (output) 8.00 0.10 7.90 (MET) Startpoint Endpoint Slack -------------------------------------------------------------------------------- reg1/Q (search_test1) out1 (output) 7.90 Group Slack -------------------------------------------- clk 7.90 {"checks": [ { "type": "output_delay", "path_group": "clk", "path_type": "max", "startpoint": "reg1/Q", "endpoint": "out1", "source_clock": "clk", "source_clock_edge": "rise", "source_clock_path": [ { "instance": "", "cell": "search_test1", "verilog_src": "", "pin": "clk", "arrival": 0.000e+00, "capacitance": 9.497e-16, "slew": 0.000e+00 }, { "instance": "reg1", "cell": "DFF_X1", "verilog_src": "", "pin": "reg1/CK", "net": "clk", "arrival": 0.000e+00, "slew": 0.000e+00 } ], "source_path": [ { "instance": "reg1", "cell": "DFF_X1", "verilog_src": "", "pin": "reg1/Q", "net": "n3", "arrival": 8.371e-11, "capacitance": 9.747e-16, "slew": 7.314e-12 }, { "instance": "buf2", "cell": "BUF_X1", "verilog_src": "", "pin": "buf2/A", "net": "n3", "arrival": 8.371e-11, "slew": 7.314e-12 }, { "instance": "buf2", "cell": "BUF_X1", "verilog_src": "", "pin": "buf2/Z", "net": "out1", "arrival": 1.003e-10, "capacitance": 0.000e+00, "slew": 3.638e-12 }, { "instance": "", "cell": "search_test1", "verilog_src": "", "pin": "out1", "arrival": 1.003e-10, "slew": 3.638e-12 } ], "target_clock": "clk", "target_clock_edge": "rise", "data_arrival_time": 1.003e-10, "crpr": 0.000e+00, "margin": 2.000e-09, "required_time": 8.000e-09, "slack": 7.900e-09 } ] } --- Output delay min formats --- Startpoint: reg1 (rising edge-triggered flip-flop clocked by clk) Endpoint: out1 (output port clocked by clk) Path Group: clk Path Type: min Delay Time Description --------------------------------------------------------- 0.00 0.00 clock clk (rise edge) 0.00 0.00 clock network delay (ideal) 0.00 0.00 ^ reg1/CK (DFF_X1) 0.08 0.08 v reg1/Q (DFF_X1) 0.02 0.10 v buf2/Z (BUF_X1) 0.00 0.10 v out1 (out) 0.10 data arrival time 0.00 0.00 clock clk (rise edge) 0.00 0.00 clock network delay (ideal) 0.00 0.00 clock reconvergence pessimism -2.00 -2.00 output external delay -2.00 data required time --------------------------------------------------------- -2.00 data required time -0.10 data arrival time --------------------------------------------------------- 2.10 slack (MET) Startpoint: reg1 (rising edge-triggered flip-flop clocked by clk) Endpoint: out1 (output port clocked by clk) Path Group: clk Path Type: min Delay Time Description --------------------------------------------------------- 0.00 0.00 clock clk (rise edge) 0.00 0.00 clock network delay (ideal) 0.00 0.00 ^ reg1/CK (DFF_X1) 0.08 0.08 v reg1/Q (DFF_X1) 0.02 0.10 v buf2/Z (BUF_X1) 0.00 0.10 v out1 (out) 0.10 data arrival time 0.00 0.00 clock clk (rise edge) 0.00 0.00 clock network delay (ideal) 0.00 0.00 clock reconvergence pessimism -2.00 -2.00 output external delay -2.00 data required time --------------------------------------------------------- -2.00 data required time -0.10 data arrival time --------------------------------------------------------- 2.10 slack (MET) Startpoint: reg1 (rising edge-triggered flip-flop clocked by clk) Endpoint: out1 (output port clocked by clk) Path Group: clk Path Type: min Delay Time Description --------------------------------------------------------- 0.00 0.00 clock clk (rise edge) 0.00 0.00 clock network delay (ideal) 0.00 0.00 ^ reg1/CK (DFF_X1) 0.08 0.08 v reg1/Q (DFF_X1) 0.02 0.10 v buf2/Z (BUF_X1) 0.00 0.10 v out1 (out) 0.10 data arrival time 0.00 0.00 clock clk (rise edge) 0.00 0.00 clock network delay (ideal) 0.00 0.00 clock reconvergence pessimism -2.00 -2.00 output external delay -2.00 data required time --------------------------------------------------------- -2.00 data required time -0.10 data arrival time --------------------------------------------------------- 2.10 slack (MET) Startpoint: reg1 (rising edge-triggered flip-flop clocked by clk) Endpoint: out1 (output port clocked by clk) Path Group: clk Path Type: min min_delay/hold group clk Required Actual Endpoint Delay Delay Slack ------------------------------------------------------------ out1 (output) -2.00 0.10 2.10 (MET) {"checks": [ { "type": "output_delay", "path_group": "clk", "path_type": "min", "startpoint": "reg1/Q", "endpoint": "out1", "source_clock": "clk", "source_clock_edge": "rise", "source_clock_path": [ { "instance": "", "cell": "search_test1", "verilog_src": "", "pin": "clk", "arrival": 0.000e+00, "capacitance": 9.497e-16, "slew": 0.000e+00 }, { "instance": "reg1", "cell": "DFF_X1", "verilog_src": "", "pin": "reg1/CK", "net": "clk", "arrival": 0.000e+00, "slew": 0.000e+00 } ], "source_path": [ { "instance": "reg1", "cell": "DFF_X1", "verilog_src": "", "pin": "reg1/Q", "net": "n3", "arrival": 7.722e-11, "capacitance": 8.752e-16, "slew": 5.624e-12 }, { "instance": "buf2", "cell": "BUF_X1", "verilog_src": "", "pin": "buf2/A", "net": "n3", "arrival": 7.722e-11, "slew": 5.624e-12 }, { "instance": "buf2", "cell": "BUF_X1", "verilog_src": "", "pin": "buf2/Z", "net": "out1", "arrival": 9.857e-11, "capacitance": 0.000e+00, "slew": 3.903e-12 }, { "instance": "", "cell": "search_test1", "verilog_src": "", "pin": "out1", "arrival": 9.857e-11, "slew": 3.903e-12 } ], "target_clock": "clk", "target_clock_edge": "rise", "data_arrival_time": 9.857e-11, "crpr": 0.000e+00, "margin": -2.000e-09, "required_time": -2.000e-09, "slack": 2.099e-09 } ] } --- Output delay with fields --- Startpoint: reg1 (rising edge-triggered flip-flop clocked by clk) Endpoint: out1 (output port clocked by clk) Path Group: clk Path Type: max Fanout Cap Slew Delay Time Description Src Attr --------------------------------------------------------------------------------------------------------------------- 0.00 0.00 0.00 clock clk (rise edge) 0.00 0.00 clock network delay (ideal) 0.00 0.00 0.00 ^ reg1/CK (DFF_X1) 1 0.97 0.01 0.08 0.08 ^ reg1/Q (DFF_X1) n3 (net) 0.01 0.00 0.08 ^ buf2/A (BUF_X1) 1 0.00 0.00 0.02 0.10 ^ buf2/Z (BUF_X1) out1 (net) 0.00 0.00 0.10 ^ out1 (out) 0.10 data arrival time 0.00 10.00 10.00 clock clk (rise edge) 0.00 10.00 clock network delay (ideal) 0.00 10.00 clock reconvergence pessimism -2.00 8.00 output external delay 8.00 data required time --------------------------------------------------------------------------------------------------------------------- 8.00 data required time -0.10 data arrival time --------------------------------------------------------------------------------------------------------------------- 7.90 slack (MET) Startpoint: reg1 (rising edge-triggered flip-flop clocked by clk) Endpoint: out1 (output port clocked by clk) Path Group: clk Path Type: min Fanout Cap Slew Delay Time Description Src Attr --------------------------------------------------------------------------------------------------------------------- 0.00 0.00 0.00 clock clk (rise edge) 0.00 0.00 clock network delay (ideal) 0.00 0.00 0.00 ^ reg1/CK (DFF_X1) 1 0.88 0.01 0.08 0.08 v reg1/Q (DFF_X1) n3 (net) 0.01 0.00 0.08 v buf2/A (BUF_X1) 1 0.00 0.00 0.02 0.10 v buf2/Z (BUF_X1) out1 (net) 0.00 0.00 0.10 v out1 (out) 0.10 data arrival time 0.00 0.00 0.00 clock clk (rise edge) 0.00 0.00 clock network delay (ideal) 0.00 0.00 clock reconvergence pessimism -2.00 -2.00 output external delay -2.00 data required time --------------------------------------------------------------------------------------------------------------------- -2.00 data required time -0.10 data arrival time --------------------------------------------------------------------------------------------------------------------- 2.10 slack (MET) --- set_max_delay --- Startpoint: reg1 (rising edge-triggered flip-flop clocked by clk) Endpoint: out1 (output port clocked by clk) Path Group: clk Path Type: max Delay Time Description --------------------------------------------------------- 0.00 0.00 clock clk (rise edge) 0.00 0.00 clock network delay (ideal) 0.00 0.00 ^ reg1/CK (DFF_X1) 0.08 0.08 ^ reg1/Q (DFF_X1) 0.02 0.10 ^ buf2/Z (BUF_X1) 0.00 0.10 ^ out1 (out) 0.10 data arrival time 10.00 10.00 clock clk (rise edge) 0.00 10.00 clock network delay (ideal) 0.00 10.00 clock reconvergence pessimism -2.00 8.00 output external delay 8.00 data required time --------------------------------------------------------- 8.00 data required time -0.10 data arrival time --------------------------------------------------------- 7.90 slack (MET) Startpoint: reg1 (rising edge-triggered flip-flop clocked by clk) Endpoint: out1 (output port clocked by clk) Path Group: clk Path Type: max Delay Time Description --------------------------------------------------------- 0.00 0.00 clock clk (rise edge) 0.00 0.00 clock network delay (ideal) 0.00 0.00 ^ reg1/CK (DFF_X1) 0.08 0.08 ^ reg1/Q (DFF_X1) 0.02 0.10 ^ buf2/Z (BUF_X1) 0.00 0.10 ^ out1 (out) 0.10 data arrival time 10.00 10.00 clock clk (rise edge) 0.00 10.00 clock network delay (ideal) 0.00 10.00 clock reconvergence pessimism -2.00 8.00 output external delay 8.00 data required time --------------------------------------------------------- 8.00 data required time -0.10 data arrival time --------------------------------------------------------- 7.90 slack (MET) Startpoint: reg1 (rising edge-triggered flip-flop clocked by clk) Endpoint: out1 (output port clocked by clk) Path Group: clk Path Type: max Delay Time Description --------------------------------------------------------- 0.00 0.00 clock clk (rise edge) 0.00 0.00 clock network delay (ideal) 0.00 0.00 ^ reg1/CK (DFF_X1) 0.08 0.08 ^ reg1/Q (DFF_X1) 0.02 0.10 ^ buf2/Z (BUF_X1) 0.00 0.10 ^ out1 (out) 0.10 data arrival time 10.00 10.00 clock clk (rise edge) 0.00 10.00 clock network delay (ideal) 0.00 10.00 clock reconvergence pessimism -2.00 8.00 output external delay 8.00 data required time --------------------------------------------------------- 8.00 data required time -0.10 data arrival time --------------------------------------------------------- 7.90 slack (MET) Startpoint: reg1 (rising edge-triggered flip-flop clocked by clk) Endpoint: out1 (output port clocked by clk) Path Group: clk Path Type: max max_delay/setup group clk Required Actual Endpoint Delay Delay Slack ------------------------------------------------------------ out1 (output) 8.00 0.10 7.90 (MET) Startpoint Endpoint Slack -------------------------------------------------------------------------------- reg1/Q (search_test1) out1 (output) 7.90 {"checks": [ { "type": "output_delay", "path_group": "clk", "path_type": "max", "startpoint": "reg1/Q", "endpoint": "out1", "source_clock": "clk", "source_clock_edge": "rise", "source_clock_path": [ { "instance": "", "cell": "search_test1", "verilog_src": "", "pin": "clk", "arrival": 0.000e+00, "capacitance": 9.497e-16, "slew": 0.000e+00 }, { "instance": "reg1", "cell": "DFF_X1", "verilog_src": "", "pin": "reg1/CK", "net": "clk", "arrival": 0.000e+00, "slew": 0.000e+00 } ], "source_path": [ { "instance": "reg1", "cell": "DFF_X1", "verilog_src": "", "pin": "reg1/Q", "net": "n3", "arrival": 8.371e-11, "capacitance": 9.747e-16, "slew": 7.314e-12 }, { "instance": "buf2", "cell": "BUF_X1", "verilog_src": "", "pin": "buf2/A", "net": "n3", "arrival": 8.371e-11, "slew": 7.314e-12 }, { "instance": "buf2", "cell": "BUF_X1", "verilog_src": "", "pin": "buf2/Z", "net": "out1", "arrival": 1.003e-10, "capacitance": 0.000e+00, "slew": 3.638e-12 }, { "instance": "", "cell": "search_test1", "verilog_src": "", "pin": "out1", "arrival": 1.003e-10, "slew": 3.638e-12 } ], "target_clock": "clk", "target_clock_edge": "rise", "data_arrival_time": 1.003e-10, "crpr": 0.000e+00, "margin": 2.000e-09, "required_time": 8.000e-09, "slack": 7.900e-09 } ] } Startpoint: reg1 (rising edge-triggered flip-flop clocked by clk) Endpoint: out1 (output port clocked by clk) Path Group: clk Path Type: max Fanout Cap Slew Delay Time Description ----------------------------------------------------------------------------- 0.00 0.00 0.00 clock clk (rise edge) 0.00 0.00 clock network delay (ideal) 0.00 0.00 0.00 ^ reg1/CK (DFF_X1) 1 0.97 0.01 0.08 0.08 ^ reg1/Q (DFF_X1) n3 (net) 0.01 0.00 0.08 ^ buf2/A (BUF_X1) 1 0.00 0.00 0.02 0.10 ^ buf2/Z (BUF_X1) out1 (net) 0.00 0.00 0.10 ^ out1 (out) 0.10 data arrival time 0.00 10.00 10.00 clock clk (rise edge) 0.00 10.00 clock network delay (ideal) 0.00 10.00 clock reconvergence pessimism -2.00 8.00 output external delay 8.00 data required time ----------------------------------------------------------------------------- 8.00 data required time -0.10 data arrival time ----------------------------------------------------------------------------- 7.90 slack (MET) --- set_min_delay --- Startpoint: in1 (input port clocked by clk) Endpoint: reg1 (rising edge-triggered flip-flop clocked by clk) Path Group: clk Path Type: min Delay Time Description --------------------------------------------------------- 0.00 0.00 clock clk (rise edge) 0.00 0.00 clock network delay (ideal) 1.00 1.00 ^ input external delay 0.00 1.00 ^ in1 (in) 0.02 1.02 ^ and1/ZN (AND2_X1) 0.02 1.04 ^ buf1/Z (BUF_X1) 0.00 1.04 ^ reg1/D (DFF_X1) 1.04 data arrival time 0.00 0.00 clock clk (rise edge) 0.00 0.00 clock network delay (ideal) 0.00 0.00 clock reconvergence pessimism 0.00 ^ reg1/CK (DFF_X1) 0.00 0.00 library hold time 0.00 data required time --------------------------------------------------------- 0.00 data required time -1.04 data arrival time --------------------------------------------------------- 1.04 slack (MET) Startpoint: in1 (input port clocked by clk) Endpoint: reg1 (rising edge-triggered flip-flop clocked by clk) Path Group: clk Path Type: min Delay Time Description --------------------------------------------------------- 0.00 0.00 clock clk (rise edge) 0.00 0.00 clock network delay (ideal) 1.00 1.00 ^ input external delay 0.00 1.00 ^ in1 (in) 0.02 1.02 ^ and1/ZN (AND2_X1) 0.02 1.04 ^ buf1/Z (BUF_X1) 0.00 1.04 ^ reg1/D (DFF_X1) 1.04 data arrival time 0.00 0.00 clock clk (rise edge) 0.00 0.00 clock network delay (ideal) 0.00 0.00 clock reconvergence pessimism 0.00 ^ reg1/CK (DFF_X1) 0.00 0.00 library hold time 0.00 data required time --------------------------------------------------------- 0.00 data required time -1.04 data arrival time --------------------------------------------------------- 1.04 slack (MET) Startpoint: in1 (input port clocked by clk) Endpoint: reg1 (rising edge-triggered flip-flop clocked by clk) Path Group: clk Path Type: min Delay Time Description --------------------------------------------------------- 0.00 0.00 clock clk (rise edge) 0.00 0.00 clock network delay (ideal) 1.00 1.00 ^ input external delay 0.00 1.00 ^ in1 (in) 0.02 1.02 ^ and1/ZN (AND2_X1) 0.02 1.04 ^ buf1/Z (BUF_X1) 0.00 1.04 ^ reg1/D (DFF_X1) 1.04 data arrival time 0.00 0.00 clock clk (rise edge) 0.00 0.00 clock network delay (ideal) 0.00 0.00 clock reconvergence pessimism 0.00 ^ reg1/CK (DFF_X1) 0.00 0.00 library hold time 0.00 data required time --------------------------------------------------------- 0.00 data required time -1.04 data arrival time --------------------------------------------------------- 1.04 slack (MET) Startpoint: in1 (input port clocked by clk) Endpoint: reg1 (rising edge-triggered flip-flop clocked by clk) Path Group: clk Path Type: min min_delay/hold group clk Required Actual Endpoint Delay Delay Slack ------------------------------------------------------------ reg1/D (DFF_X1) 0.00 1.04 1.04 (MET) {"checks": [ { "type": "check", "path_group": "clk", "path_type": "min", "startpoint": "in1", "endpoint": "reg1/D", "source_clock": "clk", "source_clock_edge": "rise", "source_path": [ { "instance": "", "cell": "search_test1", "verilog_src": "", "pin": "in1", "arrival": 1.000e-09, "capacitance": 9.181e-16, "slew": 0.000e+00 }, { "instance": "and1", "cell": "AND2_X1", "verilog_src": "", "pin": "and1/A1", "net": "in1", "arrival": 1.000e-09, "slew": 0.000e+00 }, { "instance": "and1", "cell": "AND2_X1", "verilog_src": "", "pin": "and1/ZN", "net": "n1", "arrival": 1.024e-09, "capacitance": 9.747e-16, "slew": 7.000e-12 }, { "instance": "buf1", "cell": "BUF_X1", "verilog_src": "", "pin": "buf1/A", "net": "n1", "arrival": 1.024e-09, "slew": 7.000e-12 }, { "instance": "buf1", "cell": "BUF_X1", "verilog_src": "", "pin": "buf1/Z", "net": "n2", "arrival": 1.044e-09, "capacitance": 1.140e-15, "slew": 5.947e-12 }, { "instance": "reg1", "cell": "DFF_X1", "verilog_src": "", "pin": "reg1/D", "net": "n2", "arrival": 1.044e-09, "slew": 5.947e-12 } ], "target_clock": "clk", "target_clock_edge": "rise", "target_clock_path": [ { "instance": "", "cell": "search_test1", "verilog_src": "", "pin": "clk", "arrival": 0.000e+00, "capacitance": 9.497e-16, "slew": 0.000e+00 }, { "instance": "reg1", "cell": "DFF_X1", "verilog_src": "", "pin": "reg1/CK", "net": "clk", "arrival": 0.000e+00, "slew": 0.000e+00 } ], "data_arrival_time": 1.044e-09, "crpr": 0.000e+00, "margin": 4.894e-12, "required_time": 4.894e-12, "slack": 1.039e-09 } ] } Startpoint: in1 (input port clocked by clk) Endpoint: reg1 (rising edge-triggered flip-flop clocked by clk) Path Group: clk Path Type: min Fanout Cap Slew Delay Time Description ----------------------------------------------------------------------------- 0.00 0.00 0.00 clock clk (rise edge) 0.00 0.00 clock network delay (ideal) 1.00 1.00 ^ input external delay 1 0.92 0.00 0.00 1.00 ^ in1 (in) 1 0.97 0.01 0.02 1.02 ^ and1/ZN (AND2_X1) 1 1.14 0.01 0.02 1.04 ^ buf1/Z (BUF_X1) 0.01 0.00 1.04 ^ reg1/D (DFF_X1) 1.04 data arrival time 0.00 0.00 0.00 clock clk (rise edge) 0.00 0.00 clock network delay (ideal) 0.00 0.00 clock reconvergence pessimism 0.00 ^ reg1/CK (DFF_X1) 0.00 0.00 library hold time 0.00 data required time ----------------------------------------------------------------------------- 0.00 data required time -1.04 data arrival time ----------------------------------------------------------------------------- 1.04 slack (MET) --- find_timing_paths with path delay --- Warning 502: search_path_delay_output.tcl line 1, find_timing_paths -endpoint_count is deprecated. Use -endpoint_path_count instead. Max paths: 6 is_path_delay: 0 is_output: 1 is_check: 0 pin=out1 slack=7.899713772019368e-9 is_path_delay: 0 is_output: 1 is_check: 0 pin=out1 slack=7.901434173618327e-9 is_path_delay: 0 is_output: 0 is_check: 1 pin=reg1/D slack=8.913024096557365e-9 is_path_delay: 0 is_output: 0 is_check: 1 pin=reg1/D slack=8.915245430785035e-9 is_path_delay: 0 is_output: 0 is_check: 1 pin=reg1/D slack=8.923905170377111e-9 is_path_delay: 0 is_output: 0 is_check: 1 pin=reg1/D slack=8.925195693620935e-9 --- find_timing_paths min with path delay --- Warning 502: search_path_delay_output.tcl line 1, find_timing_paths -endpoint_count is deprecated. Use -endpoint_path_count instead. Min paths: 6 is_path_delay: 0 is_output: 0 pin=reg1/D slack=1.0391780769225534e-9 is_path_delay: 0 is_output: 0 pin=reg1/D slack=1.040468933233285e-9 is_path_delay: 0 is_output: 0 pin=reg1/D slack=1.0442366971119554e-9 is_path_delay: 0 is_output: 0 pin=reg1/D slack=1.0464580313396254e-9 is_path_delay: 0 is_output: 1 pin=out1 slack=2.0985655435623585e-9 is_path_delay: 0 is_output: 1 pin=out1 slack=2.1002859451613176e-9 --- Remove path delay --- Startpoint: reg1 (rising edge-triggered flip-flop clocked by clk) Endpoint: out1 (output port clocked by clk) Path Group: clk Path Type: max Delay Time Description --------------------------------------------------------- 0.00 0.00 clock clk (rise edge) 0.00 0.00 clock network delay (ideal) 0.00 0.00 ^ reg1/CK (DFF_X1) 0.08 0.08 ^ reg1/Q (DFF_X1) 0.02 0.10 ^ buf2/Z (BUF_X1) 0.00 0.10 ^ out1 (out) 0.10 data arrival time 10.00 10.00 clock clk (rise edge) 0.00 10.00 clock network delay (ideal) 0.00 10.00 clock reconvergence pessimism -2.00 8.00 output external delay 8.00 data required time --------------------------------------------------------- 8.00 data required time -0.10 data arrival time --------------------------------------------------------- 7.90 slack (MET) --- set_false_path --- Startpoint: reg1 (rising edge-triggered flip-flop clocked by clk) Endpoint: out1 (output port clocked by clk) Path Group: clk Path Type: max Delay Time Description --------------------------------------------------------- 0.00 0.00 clock clk (rise edge) 0.00 0.00 clock network delay (ideal) 0.00 0.00 ^ reg1/CK (DFF_X1) 0.08 0.08 ^ reg1/Q (DFF_X1) 0.02 0.10 ^ buf2/Z (BUF_X1) 0.00 0.10 ^ out1 (out) 0.10 data arrival time 10.00 10.00 clock clk (rise edge) 0.00 10.00 clock network delay (ideal) 0.00 10.00 clock reconvergence pessimism -2.00 8.00 output external delay 8.00 data required time --------------------------------------------------------- 8.00 data required time -0.10 data arrival time --------------------------------------------------------- 7.90 slack (MET) Startpoint: reg1 (rising edge-triggered flip-flop clocked by clk) Endpoint: out1 (output port clocked by clk) Path Group: clk Path Type: max Delay Time Description --------------------------------------------------------- 0.00 0.00 clock clk (rise edge) 0.00 0.00 clock network delay (ideal) 0.00 0.00 ^ reg1/CK (DFF_X1) 0.08 0.08 ^ reg1/Q (DFF_X1) 0.02 0.10 ^ buf2/Z (BUF_X1) 0.00 0.10 ^ out1 (out) 0.10 data arrival time 10.00 10.00 clock clk (rise edge) 0.00 10.00 clock network delay (ideal) 0.00 10.00 clock reconvergence pessimism -2.00 8.00 output external delay 8.00 data required time --------------------------------------------------------- 8.00 data required time -0.10 data arrival time --------------------------------------------------------- 7.90 slack (MET) Startpoint: reg1 (rising edge-triggered flip-flop clocked by clk) Endpoint: out1 (output port clocked by clk) Path Group: clk Path Type: max Delay Time Description --------------------------------------------------------- 0.00 0.00 clock clk (rise edge) 0.00 0.00 clock network delay (ideal) 0.00 0.00 ^ reg1/CK (DFF_X1) 0.08 0.08 ^ reg1/Q (DFF_X1) 0.02 0.10 ^ buf2/Z (BUF_X1) 0.00 0.10 ^ out1 (out) 0.10 data arrival time 10.00 10.00 clock clk (rise edge) 0.00 10.00 clock network delay (ideal) 0.00 10.00 clock reconvergence pessimism -2.00 8.00 output external delay 8.00 data required time --------------------------------------------------------- 8.00 data required time -0.10 data arrival time --------------------------------------------------------- 7.90 slack (MET) --- set_multicycle_path --- Startpoint: reg1 (rising edge-triggered flip-flop clocked by clk) Endpoint: out1 (output port clocked by clk) Path Group: clk Path Type: max Delay Time Description --------------------------------------------------------- 0.00 0.00 clock clk (rise edge) 0.00 0.00 clock network delay (ideal) 0.00 0.00 ^ reg1/CK (DFF_X1) 0.08 0.08 ^ reg1/Q (DFF_X1) 0.02 0.10 ^ buf2/Z (BUF_X1) 0.00 0.10 ^ out1 (out) 0.10 data arrival time 10.00 10.00 clock clk (rise edge) 0.00 10.00 clock network delay (ideal) 0.00 10.00 clock reconvergence pessimism -2.00 8.00 output external delay 8.00 data required time --------------------------------------------------------- 8.00 data required time -0.10 data arrival time --------------------------------------------------------- 7.90 slack (MET) Startpoint: in1 (input port clocked by clk) Endpoint: reg1 (rising edge-triggered flip-flop clocked by clk) Path Group: clk Path Type: min Delay Time Description --------------------------------------------------------- 0.00 0.00 clock clk (rise edge) 0.00 0.00 clock network delay (ideal) 1.00 1.00 ^ input external delay 0.00 1.00 ^ in1 (in) 0.02 1.02 ^ and1/ZN (AND2_X1) 0.02 1.04 ^ buf1/Z (BUF_X1) 0.00 1.04 ^ reg1/D (DFF_X1) 1.04 data arrival time 0.00 0.00 clock clk (rise edge) 0.00 0.00 clock network delay (ideal) 0.00 0.00 clock reconvergence pessimism 0.00 ^ reg1/CK (DFF_X1) 0.00 0.00 library hold time 0.00 data required time --------------------------------------------------------- 0.00 data required time -1.04 data arrival time --------------------------------------------------------- 1.04 slack (MET) --- Propagated clock output delay --- Startpoint: reg1 (rising edge-triggered flip-flop clocked by clk) Endpoint: out1 (output port clocked by clk) Path Group: clk Path Type: max Cap Slew Delay Time Description ----------------------------------------------------------------------- 0.00 0.00 clock clk (rise edge) 0.00 0.00 clock source latency 0.95 0.00 0.00 0.00 ^ clk (in) 0.00 0.00 0.00 ^ reg1/CK (DFF_X1) 0.97 0.01 0.08 0.08 ^ reg1/Q (DFF_X1) 0.00 0.00 0.02 0.10 ^ buf2/Z (BUF_X1) 0.00 0.00 0.10 ^ out1 (out) 0.10 data arrival time 10.00 10.00 clock clk (rise edge) 0.00 10.00 clock network delay (propagated) 0.00 10.00 clock reconvergence pessimism -2.00 8.00 output external delay 8.00 data required time ----------------------------------------------------------------------- 8.00 data required time -0.10 data arrival time ----------------------------------------------------------------------- 7.90 slack (MET) Startpoint: reg1 (rising edge-triggered flip-flop clocked by clk) Endpoint: out1 (output port clocked by clk) Path Group: clk Path Type: min Cap Slew Delay Time Description ----------------------------------------------------------------------- 0.00 0.00 clock clk (rise edge) 0.00 0.00 clock source latency 0.95 0.00 0.00 0.00 ^ clk (in) 0.00 0.00 0.00 ^ reg1/CK (DFF_X1) 0.88 0.01 0.08 0.08 v reg1/Q (DFF_X1) 0.00 0.00 0.02 0.10 v buf2/Z (BUF_X1) 0.00 0.00 0.10 v out1 (out) 0.10 data arrival time 0.00 0.00 clock clk (rise edge) 0.00 0.00 clock network delay (propagated) 0.00 0.00 clock reconvergence pessimism -2.00 -2.00 output external delay -2.00 data required time ----------------------------------------------------------------------- -2.00 data required time -0.10 data arrival time ----------------------------------------------------------------------- 2.10 slack (MET) --- Output delay variation --- output_delay 1.0: worst_slack=8.899713854759739e-9 output_delay 5.0: worst_slack=4.899713967887465e-9 output_delay 9.0: worst_slack=8.997141365263417e-10 --- Output delay digits/no_split --- Startpoint: reg1 (rising edge-triggered flip-flop clocked by clk) Endpoint: out1 (output port clocked by clk) Path Group: clk Path Type: max Delay Time Description ----------------------------------------------------------------- 0.000000 0.000000 clock clk (rise edge) 0.000000 0.000000 clock network delay (ideal) 0.000000 0.000000 ^ reg1/CK (DFF_X1) 0.083707 0.083707 ^ reg1/Q (DFF_X1) 0.016579 0.100286 ^ buf2/Z (BUF_X1) 0.000000 0.100286 ^ out1 (out) 0.100286 data arrival time 10.000000 10.000000 clock clk (rise edge) 0.000000 10.000000 clock network delay (ideal) 0.000000 10.000000 clock reconvergence pessimism -2.000000 8.000000 output external delay 8.000000 data required time ----------------------------------------------------------------- 8.000000 data required time -0.100286 data arrival time ----------------------------------------------------------------- 7.899714 slack (MET) Startpoint: reg1 (rising edge-triggered flip-flop clocked by clk) Endpoint: out1 (output port clocked by clk) Path Group: clk Path Type: max Delay Time Description --------------------------------------------------------- 0.00 0.00 clock clk (rise edge) 0.00 0.00 clock network delay (ideal) 0.00 0.00 ^ reg1/CK (DFF_X1) 0.08 0.08 ^ reg1/Q (DFF_X1) 0.02 0.10 ^ buf2/Z (BUF_X1) 0.00 0.10 ^ out1 (out) 0.10 data arrival time 10.00 10.00 clock clk (rise edge) 0.00 10.00 clock network delay (ideal) 0.00 10.00 clock reconvergence pessimism -2.00 8.00 output external delay 8.00 data required time --------------------------------------------------------- 8.00 data required time -0.10 data arrival time --------------------------------------------------------- 7.90 slack (MET) --- PathEnd detail for output delay --- is_output_delay: 1 is_check: 0 is_path_delay: 0 margin: 1.999999943436137e-9 data_arrival: 1.0028596009181712e-10 data_required: 7.999999773744548e-9 target_clk: clk