--- first read_sdf --- Startpoint: d (input port clocked by clk) Endpoint: reg1 (rising edge-triggered flip-flop clocked by clk) Path Group: clk Path Type: max Delay Time Description --------------------------------------------------------- 0.00 0.00 clock clk (rise edge) 0.00 0.00 clock network delay (ideal) 0.00 0.00 ^ input external delay 0.00 0.00 ^ d (in) 0.15 0.15 ^ buf1/Z (BUF_X1) 0.12 0.27 ^ buf2/Z (BUF_X2) 0.15 0.42 ^ and1/ZN (AND2_X1) 0.03 0.45 ^ reg1/D (DFF_X1) 0.45 data arrival time 10.00 10.00 clock clk (rise edge) 0.00 10.00 clock network delay (ideal) 0.00 10.00 clock reconvergence pessimism 10.00 ^ reg1/CK (DFF_X1) -0.10 9.90 library setup time 9.90 data required time --------------------------------------------------------- 9.90 data required time -0.45 data arrival time --------------------------------------------------------- 9.45 slack (MET) --- report_annotated before re-read --- Not Delay type Total Annotated Annotated ---------------------------------------------------------------- cell arcs 6 6 0 ---------------------------------------------------------------- 6 6 0 Annotated Arcs delay and1/A1 -> and1/ZN delay and1/A2 -> and1/ZN delay buf1/A -> buf1/Z delay buf2/A -> buf2/Z delay reg1/CK -> reg1/QN delay reg1/CK -> reg1/Q Not Check type Total Annotated Annotated ---------------------------------------------------------------- cell setup arcs 1 1 0 ---------------------------------------------------------------- 1 1 0 Annotated Arcs setup reg1/CK -> reg1/D Not Delay type Total Annotated Annotated ---------------------------------------------------------------- cell arcs 6 6 0 internal net arcs 3 3 0 net arcs from primary inputs 3 0 3 net arcs to primary outputs 1 0 1 ---------------------------------------------------------------- 13 9 4 Unannotated Arcs primary input net clk -> reg1/CK primary input net d -> buf1/A primary input net en -> and1/A2 primary output net reg1/Q -> q Not Check type Total Annotated Annotated ---------------------------------------------------------------- cell setup arcs 1 1 0 cell hold arcs 1 1 0 cell width arcs 1 1 0 ---------------------------------------------------------------- 3 3 0 Unannotated Arcs --- write_sdf before re-read --- --- re-read_sdf --- Startpoint: d (input port clocked by clk) Endpoint: reg1 (rising edge-triggered flip-flop clocked by clk) Path Group: clk Path Type: max Delay Time Description --------------------------------------------------------- 0.00 0.00 clock clk (rise edge) 0.00 0.00 clock network delay (ideal) 0.00 0.00 ^ input external delay 0.00 0.00 ^ d (in) 0.15 0.15 ^ buf1/Z (BUF_X1) 0.12 0.27 ^ buf2/Z (BUF_X2) 0.15 0.42 ^ and1/ZN (AND2_X1) 0.03 0.45 ^ reg1/D (DFF_X1) 0.45 data arrival time 10.00 10.00 clock clk (rise edge) 0.00 10.00 clock network delay (ideal) 0.00 10.00 clock reconvergence pessimism 10.00 ^ reg1/CK (DFF_X1) -0.10 9.90 library setup time 9.90 data required time --------------------------------------------------------- 9.90 data required time -0.45 data arrival time --------------------------------------------------------- 9.45 slack (MET) Not Delay type Total Annotated Annotated ---------------------------------------------------------------- cell arcs 6 6 0 internal net arcs 3 3 0 net arcs from primary inputs 3 0 3 net arcs to primary outputs 1 0 1 ---------------------------------------------------------------- 13 9 4 Not Check type Total Annotated Annotated ---------------------------------------------------------------- cell setup arcs 1 1 0 cell hold arcs 1 1 0 cell width arcs 1 1 0 ---------------------------------------------------------------- 3 3 0 --- write-read roundtrip --- Startpoint: reg1 (rising edge-triggered flip-flop clocked by clk) Endpoint: q (output port clocked by clk) Path Group: clk Path Type: max Delay Time Description --------------------------------------------------------- 0.00 0.00 clock clk (rise edge) 0.00 0.00 clock network delay (ideal) 0.00 0.00 ^ reg1/CK (DFF_X1) 0.35 0.35 ^ reg1/Q (DFF_X1) 0.00 0.35 ^ q (out) 0.35 data arrival time 5.00 5.00 clock clk (rise edge) 0.00 5.00 clock network delay (ideal) 0.00 5.00 clock reconvergence pessimism -2.00 3.00 output external delay 3.00 data required time --------------------------------------------------------- 3.00 data required time -0.35 data arrival time --------------------------------------------------------- 2.65 slack (MET) Not Delay type Total Annotated Annotated ---------------------------------------------------------------- cell arcs 6 6 0 ---------------------------------------------------------------- 6 6 0 Not Check type Total Annotated Annotated ---------------------------------------------------------------- cell setup arcs 1 1 0 cell hold arcs 1 1 0 ---------------------------------------------------------------- 2 2 0 --- write with dot divider --- --- report_annotated_delay max_lines variations --- Not Delay type Total Annotated Annotated ---------------------------------------------------------------- cell arcs 6 6 0 internal net arcs 3 3 0 net arcs from primary inputs 3 3 0 net arcs to primary outputs 1 1 0 ---------------------------------------------------------------- 13 13 0 Not Delay type Total Annotated Annotated ---------------------------------------------------------------- cell arcs 6 6 0 internal net arcs 3 3 0 net arcs from primary inputs 3 3 0 net arcs to primary outputs 1 1 0 ---------------------------------------------------------------- 13 13 0 Not Delay type Total Annotated Annotated ---------------------------------------------------------------- cell arcs 6 6 0 internal net arcs 3 3 0 net arcs from primary inputs 3 3 0 net arcs to primary outputs 1 1 0 ---------------------------------------------------------------- 13 13 0 Not Delay type Total Annotated Annotated ---------------------------------------------------------------- cell arcs 6 6 0 internal net arcs 3 3 0 net arcs from primary inputs 3 3 0 net arcs to primary outputs 1 1 0 ---------------------------------------------------------------- 13 13 0 --- report_annotated_check max_lines variations --- Not Check type Total Annotated Annotated ---------------------------------------------------------------- cell setup arcs 1 1 0 cell hold arcs 1 1 0 cell width arcs 1 1 0 ---------------------------------------------------------------- 3 3 0 Not Check type Total Annotated Annotated ---------------------------------------------------------------- cell setup arcs 1 1 0 cell hold arcs 1 1 0 cell width arcs 1 1 0 ---------------------------------------------------------------- 3 3 0 --- gzip write-read roundtrip --- Startpoint: reg1 (rising edge-triggered flip-flop clocked by clk) Endpoint: q (output port clocked by clk) Path Group: clk Path Type: max Delay Time Description --------------------------------------------------------- 0.00 0.00 clock clk (rise edge) 0.00 0.00 clock network delay (ideal) 0.00 0.00 ^ reg1/CK (DFF_X1) 0.35 0.35 ^ reg1/Q (DFF_X1) 0.00 0.35 ^ q (out) 0.35 data arrival time 5.00 5.00 clock clk (rise edge) 0.00 5.00 clock network delay (ideal) 0.00 5.00 clock reconvergence pessimism -2.00 3.00 output external delay 3.00 data required time --------------------------------------------------------- 3.00 data required time -0.35 data arrival time --------------------------------------------------------- 2.65 slack (MET)