--- Test 1: read SDF with DEVICE/edge checks --- Warning 192: sdf_test5.sdf line 106, cell DFF_X1 CK -> D skew check not found. --- Test 2: timing paths --- Startpoint: d1 (input port clocked by clk) Endpoint: reg2 (rising edge-triggered flip-flop clocked by clk) Path Group: clk Path Type: max Delay Time Description --------------------------------------------------------- 0.00 0.00 clock clk (rise edge) 0.00 0.00 clock network delay (ideal) 0.00 0.00 ^ input external delay 0.00 0.00 ^ d1 (in) 0.15 0.15 ^ buf1/Z (BUF_X1) 0.12 0.27 v inv1/ZN (INV_X1) 0.05 0.32 v or1/ZN (OR2_X1) 0.13 0.45 ^ nand1/ZN (NAND2_X1) 0.02 0.47 ^ reg2/D (DFF_X1) 0.47 data arrival time 10.00 10.00 clock clk (rise edge) 0.00 10.00 clock network delay (ideal) 0.00 10.00 clock reconvergence pessimism 10.00 ^ reg2/CK (DFF_X1) -0.11 9.89 library setup time 9.89 data required time --------------------------------------------------------- 9.89 data required time -0.47 data arrival time --------------------------------------------------------- 9.42 slack (MET) Startpoint: en (input port clocked by clk) Endpoint: reg2 (rising edge-triggered flip-flop clocked by clk) Path Group: clk Path Type: min Delay Time Description --------------------------------------------------------- 0.00 0.00 clock clk (rise edge) 0.00 0.00 clock network delay (ideal) 0.00 0.00 ^ input external delay 0.00 0.00 ^ en (in) 0.02 0.02 v nand1/ZN (NAND2_X1) 0.01 0.03 v reg2/D (DFF_X1) 0.03 data arrival time 0.00 0.00 clock clk (rise edge) 0.00 0.00 clock network delay (ideal) 0.00 0.00 clock reconvergence pessimism 0.00 ^ reg2/CK (DFF_X1) 0.05 0.05 library hold time 0.05 data required time --------------------------------------------------------- 0.05 data required time -0.03 data arrival time --------------------------------------------------------- -0.02 slack (VIOLATED) No paths found. No paths found. No paths found. No paths found. --- Test 3: annotated reports --- Not Delay type Total Annotated Annotated ---------------------------------------------------------------- cell arcs 15 13 2 internal net arcs 9 9 0 net arcs from primary inputs 6 0 6 net arcs to primary outputs 3 0 3 ---------------------------------------------------------------- 33 22 11 Not Delay type Total Annotated Annotated ---------------------------------------------------------------- cell arcs 15 13 2 ---------------------------------------------------------------- 15 13 2 Not Delay type Total Annotated Annotated ---------------------------------------------------------------- internal net arcs 9 9 0 ---------------------------------------------------------------- 9 9 0 Not Delay type Total Annotated Annotated ---------------------------------------------------------------- net arcs from primary inputs 6 0 6 ---------------------------------------------------------------- 6 0 6 Not Delay type Total Annotated Annotated ---------------------------------------------------------------- net arcs to primary outputs 3 0 3 ---------------------------------------------------------------- 3 0 3 Not Delay type Total Annotated Annotated ---------------------------------------------------------------- cell arcs 15 13 2 internal net arcs 9 9 0 net arcs from primary inputs 6 0 6 net arcs to primary outputs 3 0 3 ---------------------------------------------------------------- 33 22 11 Annotated Arcs delay and1/A1 -> and1/ZN delay and1/A2 -> and1/ZN internal net and1/ZN -> or1/A2 internal net and1/ZN -> reg3/D delay buf1/A -> buf1/Z internal net buf1/Z -> inv1/A internal net buf1/Z -> and1/A1 delay buf2/A -> buf2/Z internal net buf2/Z -> and1/A2 delay inv1/A -> inv1/ZN internal net inv1/ZN -> or1/A1 delay nand1/A1 -> nand1/ZN delay nand1/A2 -> nand1/ZN internal net nand1/ZN -> reg2/D delay or1/A1 -> or1/ZN delay or1/A2 -> or1/ZN internal net or1/ZN -> nand1/A1 internal net or1/ZN -> reg1/D delay reg1/CK -> reg1/QN delay reg1/CK -> reg1/Q delay reg2/CK -> reg2/Q delay reg3/CK -> reg3/Q Not Delay type Total Annotated Annotated ---------------------------------------------------------------- cell arcs 15 13 2 internal net arcs 9 9 0 net arcs from primary inputs 6 0 6 net arcs to primary outputs 3 0 3 ---------------------------------------------------------------- 33 22 11 Unannotated Arcs primary input net clk -> reg1/CK primary input net clk -> reg2/CK primary input net clk -> reg3/CK primary input net d1 -> buf1/A primary input net d2 -> buf2/A primary input net en -> nand1/A2 primary output net reg1/Q -> q1 delay reg2/CK -> reg2/QN primary output net reg2/Q -> q2 delay reg3/CK -> reg3/QN primary output net reg3/Q -> q3 Not Check type Total Annotated Annotated ---------------------------------------------------------------- cell setup arcs 3 3 0 ---------------------------------------------------------------- 3 3 0 Not Check type Total Annotated Annotated ---------------------------------------------------------------- cell hold arcs 3 3 0 ---------------------------------------------------------------- 3 3 0 Not Check type Total Annotated Annotated ---------------------------------------------------------------- ---------------------------------------------------------------- 0 0 0 Not Check type Total Annotated Annotated ---------------------------------------------------------------- ---------------------------------------------------------------- 0 0 0 Not Check type Total Annotated Annotated ---------------------------------------------------------------- cell width arcs 3 1 2 ---------------------------------------------------------------- 3 1 2 Not Check type Total Annotated Annotated ---------------------------------------------------------------- ---------------------------------------------------------------- 0 0 0 Not Check type Total Annotated Annotated ---------------------------------------------------------------- ---------------------------------------------------------------- 0 0 0 Not Check type Total Annotated Annotated ---------------------------------------------------------------- ---------------------------------------------------------------- 0 0 0 Not Check type Total Annotated Annotated ---------------------------------------------------------------- cell setup arcs 3 3 0 cell hold arcs 3 3 0 cell width arcs 3 1 2 ---------------------------------------------------------------- 9 7 2 --- Test 4: write SDF --- --- Test 5: incremental SDF --- Startpoint: d1 (input port clocked by clk) Endpoint: reg2 (rising edge-triggered flip-flop clocked by clk) Path Group: clk Path Type: max Delay Time Description --------------------------------------------------------- 0.00 0.00 clock clk (rise edge) 0.00 0.00 clock network delay (ideal) 0.00 0.00 ^ input external delay 0.00 0.00 ^ d1 (in) 0.15 0.15 ^ buf1/Z (BUF_X1) 0.12 0.27 v inv1/ZN (INV_X1) 0.05 0.32 v or1/ZN (OR2_X1) 0.13 0.45 ^ nand1/ZN (NAND2_X1) 0.02 0.47 ^ reg2/D (DFF_X1) 0.47 data arrival time 10.00 10.00 clock clk (rise edge) 0.00 10.00 clock network delay (ideal) 0.00 10.00 clock reconvergence pessimism 10.00 ^ reg2/CK (DFF_X1) -0.11 9.89 library setup time 9.89 data required time --------------------------------------------------------- 9.89 data required time -0.47 data arrival time --------------------------------------------------------- 9.42 slack (MET) Not Delay type Total Annotated Annotated ---------------------------------------------------------------- cell arcs 15 13 2 internal net arcs 9 9 0 net arcs from primary inputs 6 0 6 net arcs to primary outputs 3 0 3 ---------------------------------------------------------------- 33 22 11 Not Delay type Total Annotated Annotated ---------------------------------------------------------------- cell arcs 15 13 2 internal net arcs 9 9 0 net arcs from primary inputs 6 0 6 net arcs to primary outputs 3 0 3 ---------------------------------------------------------------- 33 22 11 Annotated Arcs delay and1/A1 -> and1/ZN delay and1/A2 -> and1/ZN internal net and1/ZN -> or1/A2 internal net and1/ZN -> reg3/D delay buf1/A -> buf1/Z internal net buf1/Z -> inv1/A internal net buf1/Z -> and1/A1 delay buf2/A -> buf2/Z internal net buf2/Z -> and1/A2 delay inv1/A -> inv1/ZN internal net inv1/ZN -> or1/A1 delay nand1/A1 -> nand1/ZN delay nand1/A2 -> nand1/ZN internal net nand1/ZN -> reg2/D delay or1/A1 -> or1/ZN delay or1/A2 -> or1/ZN internal net or1/ZN -> nand1/A1 internal net or1/ZN -> reg1/D delay reg1/CK -> reg1/QN delay reg1/CK -> reg1/Q delay reg2/CK -> reg2/Q delay reg3/CK -> reg3/Q --- Test 6: re-read absolute SDF --- Warning 192: sdf_test5.sdf line 106, cell DFF_X1 CK -> D skew check not found. Startpoint: d1 (input port clocked by clk) Endpoint: reg2 (rising edge-triggered flip-flop clocked by clk) Path Group: clk Path Type: max Delay Time Description --------------------------------------------------------- 0.00 0.00 clock clk (rise edge) 0.00 0.00 clock network delay (ideal) 0.00 0.00 ^ input external delay 0.00 0.00 ^ d1 (in) 0.15 0.15 ^ buf1/Z (BUF_X1) 0.12 0.27 v inv1/ZN (INV_X1) 0.05 0.32 v or1/ZN (OR2_X1) 0.13 0.45 ^ nand1/ZN (NAND2_X1) 0.02 0.47 ^ reg2/D (DFF_X1) 0.47 data arrival time 10.00 10.00 clock clk (rise edge) 0.00 10.00 clock network delay (ideal) 0.00 10.00 clock reconvergence pessimism 10.00 ^ reg2/CK (DFF_X1) -0.11 9.89 library setup time 9.89 data required time --------------------------------------------------------- 9.89 data required time -0.47 data arrival time --------------------------------------------------------- 9.42 slack (MET) Not Check type Total Annotated Annotated ---------------------------------------------------------------- cell setup arcs 3 3 0 cell hold arcs 3 3 0 ---------------------------------------------------------------- 6 6 0 --- Test 7: detailed reports --- Warning 168: sdf_device_cond.tcl line 1, unknown field nets. Startpoint: d1 (input port clocked by clk) Endpoint: reg2 (rising edge-triggered flip-flop clocked by clk) Path Group: clk Path Type: max Fanout Cap Slew Delay Time Description ----------------------------------------------------------------------------- 0.00 0.00 0.00 clock clk (rise edge) 0.00 0.00 clock network delay (ideal) 0.00 0.00 ^ input external delay 1 0.97 0.10 0.00 0.00 ^ d1 (in) 0.10 0.00 0.00 ^ buf1/A (BUF_X1) 2 2.62 0.01 0.15 0.15 ^ buf1/Z (BUF_X1) 0.01 0.03 0.18 ^ inv1/A (INV_X1) 1 0.79 0.00 0.09 0.27 v inv1/ZN (INV_X1) 0.00 0.02 0.29 v or1/A1 (OR2_X1) 2 2.59 0.01 0.03 0.32 v or1/ZN (OR2_X1) 0.01 0.03 0.35 v nand1/A1 (NAND2_X1) 1 1.14 0.02 0.10 0.45 ^ nand1/ZN (NAND2_X1) 0.02 0.02 0.47 ^ reg2/D (DFF_X1) 0.47 data arrival time 0.00 10.00 10.00 clock clk (rise edge) 0.00 10.00 clock network delay (ideal) 0.00 10.00 clock reconvergence pessimism 10.00 ^ reg2/CK (DFF_X1) -0.11 9.89 library setup time 9.89 data required time ----------------------------------------------------------------------------- 9.89 data required time -0.47 data arrival time ----------------------------------------------------------------------------- 9.42 slack (MET) Startpoint: d1 (input port clocked by clk) Endpoint: reg2 (rising edge-triggered flip-flop clocked by clk) Path Group: clk Path Type: max Delay Time Description --------------------------------------------------------- 0.00 0.00 clock clk (rise edge) 0.00 0.00 clock network delay (ideal) 0.00 0.00 ^ input external delay 0.00 0.00 ^ d1 (in) 0.15 0.15 ^ buf1/Z (BUF_X1) 0.12 0.27 v inv1/ZN (INV_X1) 0.05 0.32 v or1/ZN (OR2_X1) 0.13 0.45 ^ nand1/ZN (NAND2_X1) 0.02 0.47 ^ reg2/D (DFF_X1) 0.47 data arrival time 10.00 10.00 clock clk (rise edge) 0.00 10.00 clock network delay (ideal) 0.00 10.00 clock reconvergence pessimism 10.00 ^ reg2/CK (DFF_X1) -0.11 9.89 library setup time 9.89 data required time --------------------------------------------------------- 9.89 data required time -0.47 data arrival time --------------------------------------------------------- 9.42 slack (MET) Startpoint: d1 (input port clocked by clk) Endpoint: reg2 (rising edge-triggered flip-flop clocked by clk) Path Group: clk Path Type: max Delay Time Description ----------------------------------------------------------------- 0.000000 0.000000 clock clk (rise edge) 0.000000 0.000000 clock network delay (ideal) 0.000000 0.000000 ^ input external delay 0.000000 0.000000 ^ d1 (in) 0.150000 0.150000 ^ buf1/Z (BUF_X1) 0.120000 0.270000 v inv1/ZN (INV_X1) 0.050000 0.320000 v or1/ZN (OR2_X1) 0.130000 0.450000 ^ nand1/ZN (NAND2_X1) 0.020000 0.470000 ^ reg2/D (DFF_X1) 0.470000 data arrival time 10.000000 10.000000 clock clk (rise edge) 0.000000 10.000000 clock network delay (ideal) 0.000000 10.000000 clock reconvergence pessimism 10.000000 ^ reg2/CK (DFF_X1) -0.110000 9.890000 library setup time 9.890000 data required time ----------------------------------------------------------------- 9.890000 data required time -0.470000 data arrival time ----------------------------------------------------------------- 9.420000 slack (MET) Startpoint: d1 (input port clocked by clk) Endpoint: reg2 (rising edge-triggered flip-flop clocked by clk) Path Group: clk Path Type: max Delay Time Description --------------------------------------------------------- 0.00 0.00 clock clk (rise edge) 0.00 0.00 clock network delay (ideal) 0.00 0.00 ^ input external delay 0.00 0.00 ^ d1 (in) 0.15 0.15 ^ buf1/Z (BUF_X1) 0.12 0.27 v inv1/ZN (INV_X1) 0.05 0.32 v or1/ZN (OR2_X1) 0.13 0.45 ^ nand1/ZN (NAND2_X1) 0.02 0.47 ^ reg2/D (DFF_X1) 0.47 data arrival time 10.00 10.00 clock clk (rise edge) 0.00 10.00 clock network delay (ideal) 0.00 10.00 clock reconvergence pessimism 10.00 ^ reg2/CK (DFF_X1) -0.11 9.89 library setup time 9.89 data required time --------------------------------------------------------- 9.89 data required time -0.47 data arrival time --------------------------------------------------------- 9.42 slack (MET) Startpoint: en (input port clocked by clk) Endpoint: reg2 (rising edge-triggered flip-flop clocked by clk) Path Group: clk Path Type: min Delay Time Description --------------------------------------------------------- 0.00 0.00 clock clk (rise edge) 0.00 0.00 clock network delay (ideal) 0.00 0.00 ^ input external delay 0.00 0.00 ^ en (in) 0.02 0.02 v nand1/ZN (NAND2_X1) 0.01 0.03 v reg2/D (DFF_X1) 0.03 data arrival time 0.00 0.00 clock clk (rise edge) 0.00 0.00 clock network delay (ideal) 0.00 0.00 clock reconvergence pessimism 0.00 ^ reg2/CK (DFF_X1) 0.05 0.05 library hold time 0.05 data required time --------------------------------------------------------- 0.05 data required time -0.03 data arrival time --------------------------------------------------------- -0.02 slack (VIOLATED)