--- read_sdf test2 (with timing checks/interconnects) --- --- report_annotated_delay -cell --- Not Delay type Total Annotated Annotated ---------------------------------------------------------------- cell arcs 6 6 0 ---------------------------------------------------------------- 6 6 0 --- report_annotated_delay -net --- Not Delay type Total Annotated Annotated ---------------------------------------------------------------- internal net arcs 3 3 0 ---------------------------------------------------------------- 3 3 0 --- report_annotated_delay -from_in_ports --- Not Delay type Total Annotated Annotated ---------------------------------------------------------------- net arcs from primary inputs 3 0 3 ---------------------------------------------------------------- 3 0 3 --- report_annotated_delay -to_out_ports --- Not Delay type Total Annotated Annotated ---------------------------------------------------------------- net arcs to primary outputs 1 0 1 ---------------------------------------------------------------- 1 0 1 --- report_annotated_delay -cell -net combined --- Not Delay type Total Annotated Annotated ---------------------------------------------------------------- cell arcs 6 6 0 internal net arcs 3 3 0 ---------------------------------------------------------------- 9 9 0 --- report_annotated_delay -report_annotated --- Not Delay type Total Annotated Annotated ---------------------------------------------------------------- cell arcs 6 6 0 internal net arcs 3 3 0 net arcs from primary inputs 3 0 3 net arcs to primary outputs 1 0 1 ---------------------------------------------------------------- 13 9 4 Annotated Arcs delay and1/A1 -> and1/ZN delay and1/A2 -> and1/ZN internal net and1/ZN -> reg1/D delay buf1/A -> buf1/Z internal net buf1/Z -> buf2/A delay buf2/A -> buf2/Z internal net buf2/Z -> and1/A1 delay reg1/CK -> reg1/QN delay reg1/CK -> reg1/Q --- report_annotated_delay -report_unannotated --- Not Delay type Total Annotated Annotated ---------------------------------------------------------------- cell arcs 6 6 0 internal net arcs 3 3 0 net arcs from primary inputs 3 0 3 net arcs to primary outputs 1 0 1 ---------------------------------------------------------------- 13 9 4 Unannotated Arcs primary input net clk -> reg1/CK primary input net d -> buf1/A primary input net en -> and1/A2 primary output net reg1/Q -> q --- report_annotated_delay -constant_arcs --- Not Delay type Total Annotated Annotated ---------------------------------------------------------------- cell arcs 6 6 0 constant arcs 0 0 internal net arcs 3 3 0 constant arcs 0 0 net arcs from primary inputs 3 0 3 constant arcs 0 0 net arcs to primary outputs 1 0 1 constant arcs 0 0 ---------------------------------------------------------------- 13 9 4 --- report_annotated_delay -max_lines 2 --- Not Delay type Total Annotated Annotated ---------------------------------------------------------------- cell arcs 6 6 0 internal net arcs 3 3 0 net arcs from primary inputs 3 0 3 net arcs to primary outputs 1 0 1 ---------------------------------------------------------------- 13 9 4 --- report_annotated_check -setup --- Not Check type Total Annotated Annotated ---------------------------------------------------------------- cell setup arcs 1 1 0 ---------------------------------------------------------------- 1 1 0 --- report_annotated_check -hold --- Not Check type Total Annotated Annotated ---------------------------------------------------------------- cell hold arcs 1 1 0 ---------------------------------------------------------------- 1 1 0 --- report_annotated_check -recovery --- Not Check type Total Annotated Annotated ---------------------------------------------------------------- ---------------------------------------------------------------- 0 0 0 --- report_annotated_check -removal --- Not Check type Total Annotated Annotated ---------------------------------------------------------------- ---------------------------------------------------------------- 0 0 0 --- report_annotated_check -width --- Not Check type Total Annotated Annotated ---------------------------------------------------------------- cell width arcs 1 1 0 ---------------------------------------------------------------- 1 1 0 --- report_annotated_check -period --- Not Check type Total Annotated Annotated ---------------------------------------------------------------- ---------------------------------------------------------------- 0 0 0 --- report_annotated_check -nochange --- Not Check type Total Annotated Annotated ---------------------------------------------------------------- ---------------------------------------------------------------- 0 0 0 --- report_annotated_check -max_skew --- Not Check type Total Annotated Annotated ---------------------------------------------------------------- ---------------------------------------------------------------- 0 0 0 --- report_annotated_check -setup -report_annotated --- Not Check type Total Annotated Annotated ---------------------------------------------------------------- cell setup arcs 1 1 0 ---------------------------------------------------------------- 1 1 0 Annotated Arcs setup reg1/CK -> reg1/D --- report_annotated_check -setup -report_unannotated --- Not Check type Total Annotated Annotated ---------------------------------------------------------------- cell setup arcs 1 1 0 ---------------------------------------------------------------- 1 1 0 Unannotated Arcs --- report_annotated_check -setup -hold combined --- Not Check type Total Annotated Annotated ---------------------------------------------------------------- cell setup arcs 1 1 0 cell hold arcs 1 1 0 ---------------------------------------------------------------- 2 2 0 --- report_annotated_check all types --- Not Check type Total Annotated Annotated ---------------------------------------------------------------- cell setup arcs 1 1 0 cell hold arcs 1 1 0 cell width arcs 1 1 0 ---------------------------------------------------------------- 3 3 0 --- report_annotated_check -constant_arcs --- Not Check type Total Annotated Annotated ---------------------------------------------------------------- cell setup arcs 1 1 0 constant arcs 0 0 cell hold arcs 1 1 0 constant arcs 0 0 cell width arcs 1 1 0 constant arcs 0 0 ---------------------------------------------------------------- 3 3 0 --- report_annotated_check -max_lines 3 --- Not Check type Total Annotated Annotated ---------------------------------------------------------------- cell setup arcs 1 1 0 cell hold arcs 1 1 0 cell width arcs 1 1 0 ---------------------------------------------------------------- 3 3 0 --- write_sdf default --- --- write_sdf -divider . --- --- write_sdf -digits 6 --- --- write_sdf -include_typ --- --- write_sdf -no_timestamp --- --- write_sdf -no_version --- --- write_sdf -gzip --- --- write_sdf combined options --- --- report_checks (SDF annotated) --- Startpoint: d (input port clocked by clk) Endpoint: reg1 (rising edge-triggered flip-flop clocked by clk) Path Group: clk Path Type: max Delay Time Description --------------------------------------------------------- 0.00 0.00 clock clk (rise edge) 0.00 0.00 clock network delay (ideal) 0.00 0.00 ^ input external delay 0.00 0.00 ^ d (in) 0.15 0.15 ^ buf1/Z (BUF_X1) 0.12 0.27 ^ buf2/Z (BUF_X2) 0.15 0.42 ^ and1/ZN (AND2_X1) 0.03 0.45 ^ reg1/D (DFF_X1) 0.45 data arrival time 10.00 10.00 clock clk (rise edge) 0.00 10.00 clock network delay (ideal) 0.00 10.00 clock reconvergence pessimism 10.00 ^ reg1/CK (DFF_X1) -0.10 9.90 library setup time 9.90 data required time --------------------------------------------------------- 9.90 data required time -0.45 data arrival time --------------------------------------------------------- 9.45 slack (MET) Startpoint: en (input port clocked by clk) Endpoint: reg1 (rising edge-triggered flip-flop clocked by clk) Path Group: clk Path Type: min Delay Time Description --------------------------------------------------------- 0.00 0.00 clock clk (rise edge) 0.00 0.00 clock network delay (ideal) 0.00 0.00 ^ input external delay 0.00 0.00 ^ en (in) 0.04 0.04 ^ and1/ZN (AND2_X1) 0.01 0.05 ^ reg1/D (DFF_X1) 0.05 data arrival time 0.00 0.00 clock clk (rise edge) 0.00 0.00 clock network delay (ideal) 0.00 0.00 clock reconvergence pessimism 0.00 ^ reg1/CK (DFF_X1) 0.05 0.05 library hold time 0.05 data required time --------------------------------------------------------- 0.05 data required time -0.05 data arrival time --------------------------------------------------------- 0.00 slack (VIOLATED) Startpoint: d (input port clocked by clk) Endpoint: reg1 (rising edge-triggered flip-flop clocked by clk) Path Group: clk Path Type: max Delay Time Description --------------------------------------------------------- 0.00 0.00 clock clk (rise edge) 0.00 0.00 clock network delay (ideal) 0.00 0.00 ^ input external delay 0.00 0.00 ^ d (in) 0.15 0.15 ^ buf1/Z (BUF_X1) 0.12 0.27 ^ buf2/Z (BUF_X2) 0.15 0.42 ^ and1/ZN (AND2_X1) 0.03 0.45 ^ reg1/D (DFF_X1) 0.45 data arrival time 10.00 10.00 clock clk (rise edge) 0.00 10.00 clock network delay (ideal) 0.00 10.00 clock reconvergence pessimism 10.00 ^ reg1/CK (DFF_X1) -0.10 9.90 library setup time 9.90 data required time --------------------------------------------------------- 9.90 data required time -0.45 data arrival time --------------------------------------------------------- 9.45 slack (MET)