--- false path clock to clock --- Startpoint: reg2 (rising edge-triggered flip-flop clocked by clk1) Endpoint: out1 (output port clocked by clk1) Path Group: clk1 Path Type: max Delay Time Description --------------------------------------------------------- 0.00 0.00 clock clk1 (rise edge) 0.00 0.00 clock network delay (ideal) 0.00 0.00 ^ reg2/CK (DFF_X1) 0.08 0.08 ^ reg2/Q (DFF_X1) 0.00 0.08 ^ out1 (out) 0.08 data arrival time 10.00 10.00 clock clk1 (rise edge) 0.00 10.00 clock network delay (ideal) 0.00 10.00 clock reconvergence pessimism -3.00 7.00 output external delay 7.00 data required time --------------------------------------------------------- 7.00 data required time -0.08 data arrival time --------------------------------------------------------- 6.92 slack (MET) Startpoint: reg3 (rising edge-triggered flip-flop clocked by clk2) Endpoint: out2 (output port clocked by clk2) Path Group: clk2 Path Type: max Delay Time Description --------------------------------------------------------- 0.00 0.00 clock clk2 (rise edge) 0.00 0.00 clock network delay (ideal) 0.00 0.00 ^ reg3/CK (DFF_X1) 0.08 0.08 ^ reg3/Q (DFF_X1) 0.00 0.08 ^ out2 (out) 0.08 data arrival time 20.00 20.00 clock clk2 (rise edge) 0.00 20.00 clock network delay (ideal) 0.00 20.00 clock reconvergence pessimism -3.00 17.00 output external delay 17.00 data required time --------------------------------------------------------- 17.00 data required time -0.08 data arrival time --------------------------------------------------------- 16.92 slack (MET) --- false path rise_from/fall_to --- Startpoint: reg2 (rising edge-triggered flip-flop clocked by clk1) Endpoint: out1 (output port clocked by clk1) Path Group: clk1 Path Type: max Delay Time Description --------------------------------------------------------- 0.00 0.00 clock clk1 (rise edge) 0.00 0.00 clock network delay (ideal) 0.00 0.00 ^ reg2/CK (DFF_X1) 0.08 0.08 ^ reg2/Q (DFF_X1) 0.00 0.08 ^ out1 (out) 0.08 data arrival time 10.00 10.00 clock clk1 (rise edge) 0.00 10.00 clock network delay (ideal) 0.00 10.00 clock reconvergence pessimism -3.00 7.00 output external delay 7.00 data required time --------------------------------------------------------- 7.00 data required time -0.08 data arrival time --------------------------------------------------------- 6.92 slack (MET) Startpoint: reg3 (rising edge-triggered flip-flop clocked by clk2) Endpoint: out2 (output port clocked by clk2) Path Group: clk2 Path Type: max Delay Time Description --------------------------------------------------------- 0.00 0.00 clock clk2 (rise edge) 0.00 0.00 clock network delay (ideal) 0.00 0.00 ^ reg3/CK (DFF_X1) 0.08 0.08 ^ reg3/Q (DFF_X1) 0.00 0.08 ^ out2 (out) 0.08 data arrival time 20.00 20.00 clock clk2 (rise edge) 0.00 20.00 clock network delay (ideal) 0.00 20.00 clock reconvergence pessimism -3.00 17.00 output external delay 17.00 data required time --------------------------------------------------------- 17.00 data required time -0.08 data arrival time --------------------------------------------------------- 16.92 slack (MET) --- false path fall_from/rise_to --- Startpoint: reg2 (rising edge-triggered flip-flop clocked by clk1) Endpoint: out1 (output port clocked by clk1) Path Group: clk1 Path Type: max Delay Time Description --------------------------------------------------------- 0.00 0.00 clock clk1 (rise edge) 0.00 0.00 clock network delay (ideal) 0.00 0.00 ^ reg2/CK (DFF_X1) 0.08 0.08 ^ reg2/Q (DFF_X1) 0.00 0.08 ^ out1 (out) 0.08 data arrival time 10.00 10.00 clock clk1 (rise edge) 0.00 10.00 clock network delay (ideal) 0.00 10.00 clock reconvergence pessimism -3.00 7.00 output external delay 7.00 data required time --------------------------------------------------------- 7.00 data required time -0.08 data arrival time --------------------------------------------------------- 6.92 slack (MET) Startpoint: reg3 (rising edge-triggered flip-flop clocked by clk2) Endpoint: out2 (output port clocked by clk2) Path Group: clk2 Path Type: max Delay Time Description --------------------------------------------------------- 0.00 0.00 clock clk2 (rise edge) 0.00 0.00 clock network delay (ideal) 0.00 0.00 ^ reg3/CK (DFF_X1) 0.08 0.08 ^ reg3/Q (DFF_X1) 0.00 0.08 ^ out2 (out) 0.08 data arrival time 20.00 20.00 clock clk2 (rise edge) 0.00 20.00 clock network delay (ideal) 0.00 20.00 clock reconvergence pessimism -3.00 17.00 output external delay 17.00 data required time --------------------------------------------------------- 17.00 data required time -0.08 data arrival time --------------------------------------------------------- 16.92 slack (MET) --- false path through single pin --- Startpoint: reg2 (rising edge-triggered flip-flop clocked by clk1) Endpoint: out1 (output port clocked by clk1) Path Group: clk1 Path Type: max Delay Time Description --------------------------------------------------------- 0.00 0.00 clock clk1 (rise edge) 0.00 0.00 clock network delay (ideal) 0.00 0.00 ^ reg2/CK (DFF_X1) 0.08 0.08 ^ reg2/Q (DFF_X1) 0.00 0.08 ^ out1 (out) 0.08 data arrival time 10.00 10.00 clock clk1 (rise edge) 0.00 10.00 clock network delay (ideal) 0.00 10.00 clock reconvergence pessimism -3.00 7.00 output external delay 7.00 data required time --------------------------------------------------------- 7.00 data required time -0.08 data arrival time --------------------------------------------------------- 6.92 slack (MET) Startpoint: reg3 (rising edge-triggered flip-flop clocked by clk2) Endpoint: out2 (output port clocked by clk2) Path Group: clk2 Path Type: max Delay Time Description --------------------------------------------------------- 0.00 0.00 clock clk2 (rise edge) 0.00 0.00 clock network delay (ideal) 0.00 0.00 ^ reg3/CK (DFF_X1) 0.08 0.08 ^ reg3/Q (DFF_X1) 0.00 0.08 ^ out2 (out) 0.08 data arrival time 20.00 20.00 clock clk2 (rise edge) 0.00 20.00 clock network delay (ideal) 0.00 20.00 clock reconvergence pessimism -3.00 17.00 output external delay 17.00 data required time --------------------------------------------------------- 17.00 data required time -0.08 data arrival time --------------------------------------------------------- 16.92 slack (MET) --- false path through instance pin --- Startpoint: reg2 (rising edge-triggered flip-flop clocked by clk1) Endpoint: out1 (output port clocked by clk1) Path Group: clk1 Path Type: max Delay Time Description --------------------------------------------------------- 0.00 0.00 clock clk1 (rise edge) 0.00 0.00 clock network delay (ideal) 0.00 0.00 ^ reg2/CK (DFF_X1) 0.08 0.08 ^ reg2/Q (DFF_X1) 0.00 0.08 ^ out1 (out) 0.08 data arrival time 10.00 10.00 clock clk1 (rise edge) 0.00 10.00 clock network delay (ideal) 0.00 10.00 clock reconvergence pessimism -3.00 7.00 output external delay 7.00 data required time --------------------------------------------------------- 7.00 data required time -0.08 data arrival time --------------------------------------------------------- 6.92 slack (MET) Startpoint: reg3 (rising edge-triggered flip-flop clocked by clk2) Endpoint: out2 (output port clocked by clk2) Path Group: clk2 Path Type: max Delay Time Description --------------------------------------------------------- 0.00 0.00 clock clk2 (rise edge) 0.00 0.00 clock network delay (ideal) 0.00 0.00 ^ reg3/CK (DFF_X1) 0.08 0.08 ^ reg3/Q (DFF_X1) 0.00 0.08 ^ out2 (out) 0.08 data arrival time 20.00 20.00 clock clk2 (rise edge) 0.00 20.00 clock network delay (ideal) 0.00 20.00 clock reconvergence pessimism -3.00 17.00 output external delay 17.00 data required time --------------------------------------------------------- 17.00 data required time -0.08 data arrival time --------------------------------------------------------- 16.92 slack (MET) --- false path through second pin --- Startpoint: reg2 (rising edge-triggered flip-flop clocked by clk1) Endpoint: out1 (output port clocked by clk1) Path Group: clk1 Path Type: max Delay Time Description --------------------------------------------------------- 0.00 0.00 clock clk1 (rise edge) 0.00 0.00 clock network delay (ideal) 0.00 0.00 ^ reg2/CK (DFF_X1) 0.08 0.08 ^ reg2/Q (DFF_X1) 0.00 0.08 ^ out1 (out) 0.08 data arrival time 10.00 10.00 clock clk1 (rise edge) 0.00 10.00 clock network delay (ideal) 0.00 10.00 clock reconvergence pessimism -3.00 7.00 output external delay 7.00 data required time --------------------------------------------------------- 7.00 data required time -0.08 data arrival time --------------------------------------------------------- 6.92 slack (MET) Startpoint: reg3 (rising edge-triggered flip-flop clocked by clk2) Endpoint: out2 (output port clocked by clk2) Path Group: clk2 Path Type: max Delay Time Description --------------------------------------------------------- 0.00 0.00 clock clk2 (rise edge) 0.00 0.00 clock network delay (ideal) 0.00 0.00 ^ reg3/CK (DFF_X1) 0.08 0.08 ^ reg3/Q (DFF_X1) 0.00 0.08 ^ out2 (out) 0.08 data arrival time 20.00 20.00 clock clk2 (rise edge) 0.00 20.00 clock network delay (ideal) 0.00 20.00 clock reconvergence pessimism -3.00 17.00 output external delay 17.00 data required time --------------------------------------------------------- 17.00 data required time -0.08 data arrival time --------------------------------------------------------- 16.92 slack (MET) --- multicycle setup --- Startpoint: reg2 (rising edge-triggered flip-flop clocked by clk1) Endpoint: out1 (output port clocked by clk1) Path Group: clk1 Path Type: max Delay Time Description --------------------------------------------------------- 0.00 0.00 clock clk1 (rise edge) 0.00 0.00 clock network delay (ideal) 0.00 0.00 ^ reg2/CK (DFF_X1) 0.08 0.08 ^ reg2/Q (DFF_X1) 0.00 0.08 ^ out1 (out) 0.08 data arrival time 10.00 10.00 clock clk1 (rise edge) 0.00 10.00 clock network delay (ideal) 0.00 10.00 clock reconvergence pessimism -3.00 7.00 output external delay 7.00 data required time --------------------------------------------------------- 7.00 data required time -0.08 data arrival time --------------------------------------------------------- 6.92 slack (MET) Startpoint: reg3 (rising edge-triggered flip-flop clocked by clk2) Endpoint: out2 (output port clocked by clk2) Path Group: clk2 Path Type: max Delay Time Description --------------------------------------------------------- 0.00 0.00 clock clk2 (rise edge) 0.00 0.00 clock network delay (ideal) 0.00 0.00 ^ reg3/CK (DFF_X1) 0.08 0.08 ^ reg3/Q (DFF_X1) 0.00 0.08 ^ out2 (out) 0.08 data arrival time 20.00 20.00 clock clk2 (rise edge) 0.00 20.00 clock network delay (ideal) 0.00 20.00 clock reconvergence pessimism -3.00 17.00 output external delay 17.00 data required time --------------------------------------------------------- 17.00 data required time -0.08 data arrival time --------------------------------------------------------- 16.92 slack (MET) --- multicycle hold --- Startpoint: reg2 (rising edge-triggered flip-flop clocked by clk1) Endpoint: out1 (output port clocked by clk1) Path Group: clk1 Path Type: max Delay Time Description --------------------------------------------------------- 0.00 0.00 clock clk1 (rise edge) 0.00 0.00 clock network delay (ideal) 0.00 0.00 ^ reg2/CK (DFF_X1) 0.08 0.08 ^ reg2/Q (DFF_X1) 0.00 0.08 ^ out1 (out) 0.08 data arrival time 10.00 10.00 clock clk1 (rise edge) 0.00 10.00 clock network delay (ideal) 0.00 10.00 clock reconvergence pessimism -3.00 7.00 output external delay 7.00 data required time --------------------------------------------------------- 7.00 data required time -0.08 data arrival time --------------------------------------------------------- 6.92 slack (MET) Startpoint: reg3 (rising edge-triggered flip-flop clocked by clk2) Endpoint: out2 (output port clocked by clk2) Path Group: clk2 Path Type: max Delay Time Description --------------------------------------------------------- 0.00 0.00 clock clk2 (rise edge) 0.00 0.00 clock network delay (ideal) 0.00 0.00 ^ reg3/CK (DFF_X1) 0.08 0.08 ^ reg3/Q (DFF_X1) 0.00 0.08 ^ out2 (out) 0.08 data arrival time 20.00 20.00 clock clk2 (rise edge) 0.00 20.00 clock network delay (ideal) 0.00 20.00 clock reconvergence pessimism -3.00 17.00 output external delay 17.00 data required time --------------------------------------------------------- 17.00 data required time -0.08 data arrival time --------------------------------------------------------- 16.92 slack (MET) --- multicycle with -start --- Startpoint: reg2 (rising edge-triggered flip-flop clocked by clk1) Endpoint: out1 (output port clocked by clk1) Path Group: clk1 Path Type: max Delay Time Description --------------------------------------------------------- 0.00 0.00 clock clk1 (rise edge) 0.00 0.00 clock network delay (ideal) 0.00 0.00 ^ reg2/CK (DFF_X1) 0.08 0.08 ^ reg2/Q (DFF_X1) 0.00 0.08 ^ out1 (out) 0.08 data arrival time 10.00 10.00 clock clk1 (rise edge) 0.00 10.00 clock network delay (ideal) 0.00 10.00 clock reconvergence pessimism -3.00 7.00 output external delay 7.00 data required time --------------------------------------------------------- 7.00 data required time -0.08 data arrival time --------------------------------------------------------- 6.92 slack (MET) Startpoint: reg3 (rising edge-triggered flip-flop clocked by clk2) Endpoint: out2 (output port clocked by clk2) Path Group: clk2 Path Type: max Delay Time Description --------------------------------------------------------- 0.00 0.00 clock clk2 (rise edge) 0.00 0.00 clock network delay (ideal) 0.00 0.00 ^ reg3/CK (DFF_X1) 0.08 0.08 ^ reg3/Q (DFF_X1) 0.00 0.08 ^ out2 (out) 0.08 data arrival time 20.00 20.00 clock clk2 (rise edge) 0.00 20.00 clock network delay (ideal) 0.00 20.00 clock reconvergence pessimism -3.00 17.00 output external delay 17.00 data required time --------------------------------------------------------- 17.00 data required time -0.08 data arrival time --------------------------------------------------------- 16.92 slack (MET) --- multicycle with -end --- Startpoint: in3 (input port clocked by clk2) Endpoint: reg2 (rising edge-triggered flip-flop clocked by clk1) Path Group: clk1 Path Type: max Delay Time Description --------------------------------------------------------- 0.00 0.00 clock clk2 (rise edge) 0.00 0.00 clock network delay (ideal) 2.00 2.00 v input external delay 0.00 2.00 v in3 (in) 0.05 2.05 v or1/ZN (OR2_X1) 0.03 2.07 ^ nor1/ZN (NOR2_X1) 0.00 2.07 ^ reg2/D (DFF_X1) 2.07 data arrival time 10.00 10.00 clock clk1 (rise edge) 0.00 10.00 clock network delay (ideal) 0.00 10.00 clock reconvergence pessimism 10.00 ^ reg2/CK (DFF_X1) -0.03 9.97 library setup time 9.97 data required time --------------------------------------------------------- 9.97 data required time -2.07 data arrival time --------------------------------------------------------- 7.89 slack (MET) Startpoint: reg3 (rising edge-triggered flip-flop clocked by clk2) Endpoint: out2 (output port clocked by clk2) Path Group: clk2 Path Type: max Delay Time Description --------------------------------------------------------- 0.00 0.00 clock clk2 (rise edge) 0.00 0.00 clock network delay (ideal) 0.00 0.00 ^ reg3/CK (DFF_X1) 0.08 0.08 ^ reg3/Q (DFF_X1) 0.00 0.08 ^ out2 (out) 0.08 data arrival time 20.00 20.00 clock clk2 (rise edge) 0.00 20.00 clock network delay (ideal) 0.00 20.00 clock reconvergence pessimism -3.00 17.00 output external delay 17.00 data required time --------------------------------------------------------- 17.00 data required time -0.08 data arrival time --------------------------------------------------------- 16.92 slack (MET) --- multicycle with rise_from --- Startpoint: in3 (input port clocked by clk2) Endpoint: reg2 (rising edge-triggered flip-flop clocked by clk1) Path Group: clk1 Path Type: max Delay Time Description --------------------------------------------------------- 0.00 0.00 clock clk2 (rise edge) 0.00 0.00 clock network delay (ideal) 2.00 2.00 v input external delay 0.00 2.00 v in3 (in) 0.05 2.05 v or1/ZN (OR2_X1) 0.03 2.07 ^ nor1/ZN (NOR2_X1) 0.00 2.07 ^ reg2/D (DFF_X1) 2.07 data arrival time 10.00 10.00 clock clk1 (rise edge) 0.00 10.00 clock network delay (ideal) 0.00 10.00 clock reconvergence pessimism 10.00 ^ reg2/CK (DFF_X1) -0.03 9.97 library setup time 9.97 data required time --------------------------------------------------------- 9.97 data required time -2.07 data arrival time --------------------------------------------------------- 7.89 slack (MET) Startpoint: reg3 (rising edge-triggered flip-flop clocked by clk2) Endpoint: out2 (output port clocked by clk2) Path Group: clk2 Path Type: max Delay Time Description --------------------------------------------------------- 0.00 0.00 clock clk2 (rise edge) 0.00 0.00 clock network delay (ideal) 0.00 0.00 ^ reg3/CK (DFF_X1) 0.08 0.08 ^ reg3/Q (DFF_X1) 0.00 0.08 ^ out2 (out) 0.08 data arrival time 20.00 20.00 clock clk2 (rise edge) 0.00 20.00 clock network delay (ideal) 0.00 20.00 clock reconvergence pessimism -3.00 17.00 output external delay 17.00 data required time --------------------------------------------------------- 17.00 data required time -0.08 data arrival time --------------------------------------------------------- 16.92 slack (MET) --- multicycle with fall_to --- Startpoint: in3 (input port clocked by clk2) Endpoint: reg2 (rising edge-triggered flip-flop clocked by clk1) Path Group: clk1 Path Type: max Delay Time Description --------------------------------------------------------- 0.00 0.00 clock clk2 (rise edge) 0.00 0.00 clock network delay (ideal) 2.00 2.00 v input external delay 0.00 2.00 v in3 (in) 0.05 2.05 v or1/ZN (OR2_X1) 0.03 2.07 ^ nor1/ZN (NOR2_X1) 0.00 2.07 ^ reg2/D (DFF_X1) 2.07 data arrival time 10.00 10.00 clock clk1 (rise edge) 0.00 10.00 clock network delay (ideal) 0.00 10.00 clock reconvergence pessimism 10.00 ^ reg2/CK (DFF_X1) -0.03 9.97 library setup time 9.97 data required time --------------------------------------------------------- 9.97 data required time -2.07 data arrival time --------------------------------------------------------- 7.89 slack (MET) Startpoint: reg3 (rising edge-triggered flip-flop clocked by clk2) Endpoint: out2 (output port clocked by clk2) Path Group: clk2 Path Type: max Delay Time Description --------------------------------------------------------- 0.00 0.00 clock clk2 (rise edge) 0.00 0.00 clock network delay (ideal) 0.00 0.00 ^ reg3/CK (DFF_X1) 0.08 0.08 ^ reg3/Q (DFF_X1) 0.00 0.08 ^ out2 (out) 0.08 data arrival time 20.00 20.00 clock clk2 (rise edge) 0.00 20.00 clock network delay (ideal) 0.00 20.00 clock reconvergence pessimism -3.00 17.00 output external delay 17.00 data required time --------------------------------------------------------- 17.00 data required time -0.08 data arrival time --------------------------------------------------------- 16.92 slack (MET) --- max_delay --- Startpoint: in3 (input port clocked by clk2) Endpoint: reg2 (rising edge-triggered flip-flop clocked by clk1) Path Group: clk1 Path Type: max Delay Time Description --------------------------------------------------------- 0.00 0.00 clock clk2 (rise edge) 0.00 0.00 clock network delay (ideal) 2.00 2.00 v input external delay 0.00 2.00 v in3 (in) 0.05 2.05 v or1/ZN (OR2_X1) 0.03 2.07 ^ nor1/ZN (NOR2_X1) 0.00 2.07 ^ reg2/D (DFF_X1) 2.07 data arrival time 10.00 10.00 clock clk1 (rise edge) 0.00 10.00 clock network delay (ideal) 0.00 10.00 clock reconvergence pessimism 10.00 ^ reg2/CK (DFF_X1) -0.03 9.97 library setup time 9.97 data required time --------------------------------------------------------- 9.97 data required time -2.07 data arrival time --------------------------------------------------------- 7.89 slack (MET) Startpoint: reg3 (rising edge-triggered flip-flop clocked by clk2) Endpoint: out2 (output port clocked by clk2) Path Group: clk2 Path Type: max Delay Time Description --------------------------------------------------------- 0.00 0.00 clock clk2 (rise edge) 0.00 0.00 clock network delay (ideal) 0.00 0.00 ^ reg3/CK (DFF_X1) 0.08 0.08 ^ reg3/Q (DFF_X1) 0.00 0.08 ^ out2 (out) 0.08 data arrival time 20.00 20.00 clock clk2 (rise edge) 0.00 20.00 clock network delay (ideal) 0.00 20.00 clock reconvergence pessimism -3.00 17.00 output external delay 17.00 data required time --------------------------------------------------------- 17.00 data required time -0.08 data arrival time --------------------------------------------------------- 16.92 slack (MET) --- min_delay --- Startpoint: in1 (input port clocked by clk1) Endpoint: reg2 (rising edge-triggered flip-flop clocked by clk1) Path Group: clk1 Path Type: min Delay Time Description --------------------------------------------------------- 0.00 0.00 clock clk1 (rise edge) 0.00 0.00 clock network delay (ideal) 2.00 2.00 ^ input external delay 0.00 2.00 ^ in1 (in) 0.02 2.02 ^ buf1/Z (BUF_X1) 0.03 2.04 ^ or1/ZN (OR2_X1) 0.01 2.05 v nor1/ZN (NOR2_X1) 0.00 2.05 v reg2/D (DFF_X1) 2.05 data arrival time 30.00 30.00 clock clk1 (rise edge) 0.00 30.00 clock network delay (ideal) 0.00 30.00 clock reconvergence pessimism 30.00 ^ reg2/CK (DFF_X1) 0.00 30.00 library hold time 30.00 data required time --------------------------------------------------------- 30.00 data required time -2.05 data arrival time --------------------------------------------------------- -27.95 slack (VIOLATED) Startpoint: reg3 (rising edge-triggered flip-flop clocked by clk2) Endpoint: out2 (output port clocked by clk2) Path Group: clk2 Path Type: min Delay Time Description --------------------------------------------------------- 0.00 0.00 clock clk2 (rise edge) 0.00 0.00 clock network delay (ideal) 0.00 0.00 ^ reg3/CK (DFF_X1) 0.08 0.08 v reg3/Q (DFF_X1) 0.00 0.08 v out2 (out) 0.08 data arrival time 0.00 0.00 clock clk2 (rise edge) 0.00 0.00 clock network delay (ideal) 0.00 0.00 clock reconvergence pessimism -3.00 -3.00 output external delay -3.00 data required time --------------------------------------------------------- -3.00 data required time -0.08 data arrival time --------------------------------------------------------- 3.08 slack (MET) --- max_delay with through --- Startpoint: in3 (input port clocked by clk2) Endpoint: reg2 (rising edge-triggered flip-flop clocked by clk1) Path Group: clk1 Path Type: max Delay Time Description --------------------------------------------------------- 0.00 0.00 clock clk2 (rise edge) 0.00 0.00 clock network delay (ideal) 2.00 2.00 v input external delay 0.00 2.00 v in3 (in) 0.05 2.05 v or1/ZN (OR2_X1) 0.03 2.07 ^ nor1/ZN (NOR2_X1) 0.00 2.07 ^ reg2/D (DFF_X1) 2.07 data arrival time 10.00 10.00 clock clk1 (rise edge) 0.00 10.00 clock network delay (ideal) 0.00 10.00 clock reconvergence pessimism 10.00 ^ reg2/CK (DFF_X1) -0.03 9.97 library setup time 9.97 data required time --------------------------------------------------------- 9.97 data required time -2.07 data arrival time --------------------------------------------------------- 7.89 slack (MET) Startpoint: reg3 (rising edge-triggered flip-flop clocked by clk2) Endpoint: out2 (output port clocked by clk2) Path Group: clk2 Path Type: max Delay Time Description --------------------------------------------------------- 0.00 0.00 clock clk2 (rise edge) 0.00 0.00 clock network delay (ideal) 0.00 0.00 ^ reg3/CK (DFF_X1) 0.08 0.08 ^ reg3/Q (DFF_X1) 0.00 0.08 ^ out2 (out) 0.08 data arrival time 20.00 20.00 clock clk2 (rise edge) 0.00 20.00 clock network delay (ideal) 0.00 20.00 clock reconvergence pessimism -3.00 17.00 output external delay 17.00 data required time --------------------------------------------------------- 17.00 data required time -0.08 data arrival time --------------------------------------------------------- 16.92 slack (MET) --- min_delay with through --- Startpoint: in1 (input port clocked by clk1) Endpoint: reg2 (rising edge-triggered flip-flop clocked by clk1) Path Group: clk1 Path Type: min Delay Time Description --------------------------------------------------------- 0.00 0.00 clock clk1 (rise edge) 0.00 0.00 clock network delay (ideal) 2.00 2.00 ^ input external delay 0.00 2.00 ^ in1 (in) 0.02 2.02 ^ buf1/Z (BUF_X1) 0.03 2.04 ^ or1/ZN (OR2_X1) 0.01 2.05 v nor1/ZN (NOR2_X1) 0.00 2.05 v reg2/D (DFF_X1) 2.05 data arrival time 30.00 30.00 clock clk1 (rise edge) 0.00 30.00 clock network delay (ideal) 0.00 30.00 clock reconvergence pessimism 30.00 ^ reg2/CK (DFF_X1) 0.00 30.00 library hold time 30.00 data required time --------------------------------------------------------- 30.00 data required time -2.05 data arrival time --------------------------------------------------------- -27.95 slack (VIOLATED) Startpoint: reg3 (rising edge-triggered flip-flop clocked by clk2) Endpoint: out2 (output port clocked by clk2) Path Group: clk2 Path Type: min Delay Time Description --------------------------------------------------------- 0.00 0.00 clock clk2 (rise edge) 0.00 0.00 clock network delay (ideal) 0.00 0.00 ^ reg3/CK (DFF_X1) 0.08 0.08 v reg3/Q (DFF_X1) 0.00 0.08 v out2 (out) 0.08 data arrival time 0.00 0.00 clock clk2 (rise edge) 0.00 0.00 clock network delay (ideal) 0.00 0.00 clock reconvergence pessimism -3.00 -3.00 output external delay -3.00 data required time --------------------------------------------------------- -3.00 data required time -0.08 data arrival time --------------------------------------------------------- 3.08 slack (MET) --- max_delay rise_from --- Startpoint: in3 (input port clocked by clk2) Endpoint: reg2 (rising edge-triggered flip-flop clocked by clk1) Path Group: clk1 Path Type: max Delay Time Description --------------------------------------------------------- 0.00 0.00 clock clk2 (rise edge) 0.00 0.00 clock network delay (ideal) 2.00 2.00 v input external delay 0.00 2.00 v in3 (in) 0.05 2.05 v or1/ZN (OR2_X1) 0.03 2.07 ^ nor1/ZN (NOR2_X1) 0.00 2.07 ^ reg2/D (DFF_X1) 2.07 data arrival time 10.00 10.00 clock clk1 (rise edge) 0.00 10.00 clock network delay (ideal) 0.00 10.00 clock reconvergence pessimism 10.00 ^ reg2/CK (DFF_X1) -0.03 9.97 library setup time 9.97 data required time --------------------------------------------------------- 9.97 data required time -2.07 data arrival time --------------------------------------------------------- 7.89 slack (MET) Startpoint: reg3 (rising edge-triggered flip-flop clocked by clk2) Endpoint: out2 (output port clocked by clk2) Path Group: clk2 Path Type: max Delay Time Description --------------------------------------------------------- 0.00 0.00 clock clk2 (rise edge) 0.00 0.00 clock network delay (ideal) 0.00 0.00 ^ reg3/CK (DFF_X1) 0.08 0.08 ^ reg3/Q (DFF_X1) 0.00 0.08 ^ out2 (out) 0.08 data arrival time 20.00 20.00 clock clk2 (rise edge) 0.00 20.00 clock network delay (ideal) 0.00 20.00 clock reconvergence pessimism -3.00 17.00 output external delay 17.00 data required time --------------------------------------------------------- 17.00 data required time -0.08 data arrival time --------------------------------------------------------- 16.92 slack (MET) --- group_path --- Startpoint: reg2 (rising edge-triggered flip-flop clocked by clk1) Endpoint: out1 (output port clocked by clk1) Path Group: grp1 Path Type: max Delay Time Description --------------------------------------------------------- 0.00 0.00 clock clk1 (rise edge) 0.00 0.00 clock network delay (ideal) 0.00 0.00 ^ reg2/CK (DFF_X1) 0.08 0.08 ^ reg2/Q (DFF_X1) 0.00 0.08 ^ out1 (out) 0.08 data arrival time 20.00 20.00 clock clk1 (rise edge) 0.00 20.00 clock network delay (ideal) 0.00 20.00 clock reconvergence pessimism -3.00 17.00 output external delay 17.00 data required time --------------------------------------------------------- 17.00 data required time -0.08 data arrival time --------------------------------------------------------- 16.92 slack (MET) Startpoint: reg3 (rising edge-triggered flip-flop clocked by clk2) Endpoint: out2 (output port clocked by clk2) Path Group: grp3 Path Type: max Delay Time Description --------------------------------------------------------- 0.00 0.00 clock clk2 (rise edge) 0.00 0.00 clock network delay (ideal) 0.00 0.00 ^ reg3/CK (DFF_X1) 0.08 0.08 ^ reg3/Q (DFF_X1) 0.00 0.08 ^ out2 (out) 0.08 data arrival time 20.00 20.00 clock clk2 (rise edge) 0.00 20.00 clock network delay (ideal) 0.00 20.00 clock reconvergence pessimism -3.00 17.00 output external delay 17.00 data required time --------------------------------------------------------- 17.00 data required time -0.08 data arrival time --------------------------------------------------------- 16.92 slack (MET) Startpoint: in3 (input port clocked by clk2) Endpoint: reg2 (rising edge-triggered flip-flop clocked by clk1) Path Group: clk1 Path Type: max Delay Time Description --------------------------------------------------------- 0.00 0.00 clock clk2 (rise edge) 0.00 0.00 clock network delay (ideal) 2.00 2.00 v input external delay 0.00 2.00 v in3 (in) 0.05 2.05 v or1/ZN (OR2_X1) 0.03 2.07 ^ nor1/ZN (NOR2_X1) 0.00 2.07 ^ reg2/D (DFF_X1) 2.07 data arrival time 10.00 10.00 clock clk1 (rise edge) 0.00 10.00 clock network delay (ideal) 0.00 10.00 clock reconvergence pessimism 10.00 ^ reg2/CK (DFF_X1) -0.03 9.97 library setup time 9.97 data required time --------------------------------------------------------- 9.97 data required time -2.07 data arrival time --------------------------------------------------------- 7.89 slack (MET) --- path group names --- Path group names: clk1 clk2 grp1 grp2 grp3 asynchronous {path delay} {gated clock} unconstrained --- is_path_group_name --- grp1 is group: 1 nonexistent is group: 0 --- exception override: false path then max_delay --- Startpoint: reg2 (rising edge-triggered flip-flop clocked by clk1) Endpoint: out1 (output port clocked by clk1) Path Group: grp1 Path Type: max Delay Time Description --------------------------------------------------------- 0.00 0.00 clock clk1 (rise edge) 0.00 0.00 clock network delay (ideal) 0.00 0.00 ^ reg2/CK (DFF_X1) 0.08 0.08 ^ reg2/Q (DFF_X1) 0.00 0.08 ^ out1 (out) 0.08 data arrival time 20.00 20.00 clock clk1 (rise edge) 0.00 20.00 clock network delay (ideal) 0.00 20.00 clock reconvergence pessimism -3.00 17.00 output external delay 17.00 data required time --------------------------------------------------------- 17.00 data required time -0.08 data arrival time --------------------------------------------------------- 16.92 slack (MET) Startpoint: reg3 (rising edge-triggered flip-flop clocked by clk2) Endpoint: out2 (output port clocked by clk2) Path Group: grp3 Path Type: max Delay Time Description --------------------------------------------------------- 0.00 0.00 clock clk2 (rise edge) 0.00 0.00 clock network delay (ideal) 0.00 0.00 ^ reg3/CK (DFF_X1) 0.08 0.08 ^ reg3/Q (DFF_X1) 0.00 0.08 ^ out2 (out) 0.08 data arrival time 20.00 20.00 clock clk2 (rise edge) 0.00 20.00 clock network delay (ideal) 0.00 20.00 clock reconvergence pessimism -3.00 17.00 output external delay 17.00 data required time --------------------------------------------------------- 17.00 data required time -0.08 data arrival time --------------------------------------------------------- 16.92 slack (MET) Startpoint: in3 (input port clocked by clk2) Endpoint: reg2 (rising edge-triggered flip-flop clocked by clk1) Path Group: clk1 Path Type: max Delay Time Description --------------------------------------------------------- 0.00 0.00 clock clk2 (rise edge) 0.00 0.00 clock network delay (ideal) 2.00 2.00 v input external delay 0.00 2.00 v in3 (in) 0.05 2.05 v or1/ZN (OR2_X1) 0.03 2.07 ^ nor1/ZN (NOR2_X1) 0.00 2.07 ^ reg2/D (DFF_X1) 2.07 data arrival time 10.00 10.00 clock clk1 (rise edge) 0.00 10.00 clock network delay (ideal) 0.00 10.00 clock reconvergence pessimism 10.00 ^ reg2/CK (DFF_X1) -0.03 9.97 library setup time 9.97 data required time --------------------------------------------------------- 9.97 data required time -2.07 data arrival time --------------------------------------------------------- 7.89 slack (MET) --- remove_constraints --- remove_constraints: skipped (API removed) Startpoint: reg2 (rising edge-triggered flip-flop clocked by clk1) Endpoint: out1 (output port clocked by clk1) Path Group: grp1 Path Type: max Delay Time Description --------------------------------------------------------- 0.00 0.00 clock clk1 (rise edge) 0.00 0.00 clock network delay (ideal) 0.00 0.00 ^ reg2/CK (DFF_X1) 0.08 0.08 ^ reg2/Q (DFF_X1) 0.00 0.08 ^ out1 (out) 0.08 data arrival time 20.00 20.00 clock clk1 (rise edge) 0.00 20.00 clock network delay (ideal) 0.00 20.00 clock reconvergence pessimism -3.00 17.00 output external delay 17.00 data required time --------------------------------------------------------- 17.00 data required time -0.08 data arrival time --------------------------------------------------------- 16.92 slack (MET) Startpoint: reg3 (rising edge-triggered flip-flop clocked by clk2) Endpoint: out2 (output port clocked by clk2) Path Group: grp3 Path Type: max Delay Time Description --------------------------------------------------------- 0.00 0.00 clock clk2 (rise edge) 0.00 0.00 clock network delay (ideal) 0.00 0.00 ^ reg3/CK (DFF_X1) 0.08 0.08 ^ reg3/Q (DFF_X1) 0.00 0.08 ^ out2 (out) 0.08 data arrival time 20.00 20.00 clock clk2 (rise edge) 0.00 20.00 clock network delay (ideal) 0.00 20.00 clock reconvergence pessimism -3.00 17.00 output external delay 17.00 data required time --------------------------------------------------------- 17.00 data required time -0.08 data arrival time --------------------------------------------------------- 16.92 slack (MET) Startpoint: in3 (input port clocked by clk2) Endpoint: reg2 (rising edge-triggered flip-flop clocked by clk1) Path Group: clk1 Path Type: max Delay Time Description --------------------------------------------------------- 0.00 0.00 clock clk2 (rise edge) 0.00 0.00 clock network delay (ideal) 2.00 2.00 v input external delay 0.00 2.00 v in3 (in) 0.05 2.05 v or1/ZN (OR2_X1) 0.03 2.07 ^ nor1/ZN (NOR2_X1) 0.00 2.07 ^ reg2/D (DFF_X1) 2.07 data arrival time 10.00 10.00 clock clk1 (rise edge) 0.00 10.00 clock network delay (ideal) 0.00 10.00 clock reconvergence pessimism 10.00 ^ reg2/CK (DFF_X1) -0.03 9.97 library setup time 9.97 data required time --------------------------------------------------------- 9.97 data required time -2.07 data arrival time --------------------------------------------------------- 7.89 slack (MET) --- write_sdc with exceptions --- --- write_sdc compatible with exceptions --- --- read_sdc back --- Startpoint: reg2 (rising edge-triggered flip-flop clocked by clk1) Endpoint: out1 (output port clocked by clk1) Path Group: grp1 Path Type: max Delay Time Description --------------------------------------------------------- 0.00 0.00 clock clk1 (rise edge) 0.00 0.00 clock network delay (ideal) 0.00 0.00 ^ reg2/CK (DFF_X1) 0.08 0.08 ^ reg2/Q (DFF_X1) 0.00 0.08 ^ out1 (out) 0.08 data arrival time 20.00 20.00 clock clk1 (rise edge) 0.00 20.00 clock network delay (ideal) 0.00 20.00 clock reconvergence pessimism -3.00 17.00 output external delay 17.00 data required time --------------------------------------------------------- 17.00 data required time -0.08 data arrival time --------------------------------------------------------- 16.92 slack (MET) Startpoint: reg3 (rising edge-triggered flip-flop clocked by clk2) Endpoint: out2 (output port clocked by clk2) Path Group: grp3 Path Type: max Delay Time Description --------------------------------------------------------- 0.00 0.00 clock clk2 (rise edge) 0.00 0.00 clock network delay (ideal) 0.00 0.00 ^ reg3/CK (DFF_X1) 0.08 0.08 ^ reg3/Q (DFF_X1) 0.00 0.08 ^ out2 (out) 0.08 data arrival time 20.00 20.00 clock clk2 (rise edge) 0.00 20.00 clock network delay (ideal) 0.00 20.00 clock reconvergence pessimism -3.00 17.00 output external delay 17.00 data required time --------------------------------------------------------- 17.00 data required time -0.08 data arrival time --------------------------------------------------------- 16.92 slack (MET) Startpoint: in3 (input port clocked by clk2) Endpoint: reg2 (rising edge-triggered flip-flop clocked by clk1) Path Group: clk1 Path Type: max Delay Time Description --------------------------------------------------------- 0.00 0.00 clock clk2 (rise edge) 0.00 0.00 clock network delay (ideal) 2.00 2.00 v input external delay 0.00 2.00 v in3 (in) 0.05 2.05 v or1/ZN (OR2_X1) 0.03 2.07 ^ nor1/ZN (NOR2_X1) 0.00 2.07 ^ reg2/D (DFF_X1) 2.07 data arrival time 10.00 10.00 clock clk1 (rise edge) 0.00 10.00 clock network delay (ideal) 0.00 10.00 clock reconvergence pessimism 10.00 ^ reg2/CK (DFF_X1) -0.03 9.97 library setup time 9.97 data required time --------------------------------------------------------- 9.97 data required time -2.07 data arrival time --------------------------------------------------------- 7.89 slack (MET)