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# Created by write_sdc
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current_design sdc_test2
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# Timing Constraints
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create_clock -name clk1 -period 10.0000 [get_ports {clk1}]
create_clock -name clk2 -period 20.0000 [get_ports {clk2}]
set_input_delay 2.0000 -clock [get_clocks {clk1}] -add_delay [get_ports {in1}]
set_input_delay 2.0000 -clock [get_clocks {clk1}] -add_delay [get_ports {in2}]
set_input_delay 2.0000 -clock [get_clocks {clk2}] -add_delay [get_ports {in3}]
set_output_delay 3.0000 -clock [get_clocks {clk1}] -add_delay [get_ports {out1}]
set_output_delay 3.0000 -clock [get_clocks {clk2}] -add_delay [get_ports {out2}]
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# Environment
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set_timing_derate -cell_delay -early -clock 0.9600
set_timing_derate -cell_delay -data -rise -early 0.9500
set_timing_derate -cell_delay -data -fall -early 0.9600
set_timing_derate -cell_check -early 0.9800
set_timing_derate -net_delay -early 0.9300
set_timing_derate -cell_delay -late -clock 1.0400
set_timing_derate -cell_delay -data -rise -late 1.0400
set_timing_derate -cell_delay -data -fall -late 1.0500
set_timing_derate -cell_check -late 1.0200
set_timing_derate -net_delay -late 1.0700
set_timing_derate -net_delay -early 0.8600 [get_nets {n3}]
set_timing_derate -net_delay -late 1.1400 [get_nets {n3}]
set_timing_derate -net_delay -early 0.8700 [get_nets {n1}]
set_timing_derate -net_delay -late 1.1300 [get_nets {n1}]
set_timing_derate -cell_check -early 0.8800 [get_cells {reg1}]
set_timing_derate -cell_check -late 1.1200 [get_cells {reg1}]
set_timing_derate -cell_delay -early 0.8900 [get_cells {buf1}]
set_timing_derate -cell_delay -late 1.1100 [get_cells {buf1}]
set_timing_derate -cell_check -early 0.9000 [get_lib_cells {NangateOpenCellLibrary/DFF_X1}]
set_timing_derate -cell_check -late 1.1000 [get_lib_cells {NangateOpenCellLibrary/DFF_X1}]
set_timing_derate -cell_delay -early 0.9100 [get_lib_cells {NangateOpenCellLibrary/INV_X1}]
set_timing_derate -cell_delay -late 1.0900 [get_lib_cells {NangateOpenCellLibrary/INV_X1}]
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# Design Rules
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