############################################################################### # Created by write_sdc ############################################################################### current_design sdc_test2 ############################################################################### # Timing Constraints ############################################################################### create_clock -name clk1 -period 10.0000 [get_ports {clk1}] create_clock -name clk2 -period 20.0000 [get_ports {clk2}] set_propagated_clock [get_clocks {clk2}] create_clock -name vclk1 -period 8.0000 create_clock -name vclk2 -period 12.0000 create_clock -name clk1_2x -add -period 5.0000 [get_ports {clk1}] create_generated_clock -name gclk1 -source [get_ports {clk1}] -divide_by 2 [get_pins {reg1/Q}] create_generated_clock -name gclk2 -source [get_ports {clk2}] -multiply_by 2 [get_pins {reg3/Q}] set_clock_uncertainty -setup 0.2000 [get_pins {reg2/CK}] set_clock_uncertainty -rise_from [get_clocks {clk2}] -rise_to [get_clocks {clk1}] -hold 0.1200 set_clock_uncertainty -rise_from [get_clocks {clk2}] -rise_to [get_clocks {clk1}] -setup 0.2500 set_clock_uncertainty -rise_from [get_clocks {clk2}] -fall_to [get_clocks {clk1}] -hold 0.1200 set_clock_uncertainty -rise_from [get_clocks {clk2}] -fall_to [get_clocks {clk1}] -setup 0.2500 set_clock_uncertainty -fall_from [get_clocks {clk2}] -rise_to [get_clocks {clk1}] -hold 0.1200 set_clock_uncertainty -fall_from [get_clocks {clk2}] -rise_to [get_clocks {clk1}] -setup 0.2500 set_clock_uncertainty -fall_from [get_clocks {clk2}] -fall_to [get_clocks {clk1}] -hold 0.1200 set_clock_uncertainty -fall_from [get_clocks {clk2}] -fall_to [get_clocks {clk1}] -setup 0.2500 set_sense -type clock -stop_propagation -clock [get_clocks {clk1}] [get_pins {and1/ZN}] set_sense -type clock -positive -clock [get_clocks {clk1}] [get_pins {buf1/Z}] set_sense -type clock -negative -clock [get_clocks {clk2}] [get_pins {inv1/ZN}] set_input_delay 2.0000 -clock [get_clocks {clk1}] -add_delay [get_ports {in1}] set_input_delay 2.0000 -clock [get_clocks {clk1}] -add_delay [get_ports {in2}] set_input_delay 2.0000 -clock [get_clocks {clk2}] -add_delay [get_ports {in3}] set_output_delay 3.0000 -clock [get_clocks {clk1}] -add_delay [get_ports {out1}] set_output_delay 3.0000 -clock [get_clocks {clk2}] -add_delay [get_ports {out2}] ############################################################################### # Environment ############################################################################### ############################################################################### # Design Rules ###############################################################################