Startpoint: in1 (input port clocked by clk) Endpoint: reg1 (rising edge-triggered flip-flop clocked by clk) Path Group: clk Path Type: max Delay Time Description --------------------------------------------------------- 0.00 0.00 clock clk (rise edge) 0.00 0.00 clock network delay (ideal) 0.00 0.00 v input external delay 0.00 0.00 v in1 (in) 0.02 0.02 v buf1/Z (BUF_X1) 0.02 0.05 v and1/ZN (AND2_X1) 0.00 0.05 v reg1/D (DFF_X1) 0.05 data arrival time 10.00 10.00 clock clk (rise edge) 0.00 10.00 clock network delay (ideal) 0.00 10.00 clock reconvergence pessimism 10.00 ^ reg1/CK (DFF_X1) -0.04 9.96 library setup time 9.96 data required time --------------------------------------------------------- 9.96 data required time -0.05 data arrival time --------------------------------------------------------- 9.92 slack (MET) --- make_instance using liberty cell --- lib_buf pins: 2 pin: lib_buf/A dir=input pin: lib_buf/Z dir=output --- fanin/fanout on new cells --- fanin to lib_buf/Z: 2 fanout from lib_buf/A: 2 --- disconnect and reconnect --- --- multiple instance creation --- total cells after add: 6 test_* cells: 3 total cells after delete: 3 --- replace_cell tests --- replace_cell buf1 -> BUF_X4: 1 buf1 ref after replace: BUF_X4 Startpoint: reg1 (rising edge-triggered flip-flop clocked by clk) Endpoint: out1 (output port clocked by clk) Path Group: clk Path Type: max Delay Time Description --------------------------------------------------------- 0.00 0.00 clock clk (rise edge) 0.00 0.00 clock network delay (ideal) 0.00 0.00 ^ reg1/CK (DFF_X1) 0.08 0.08 ^ reg1/Q (DFF_X1) 0.00 0.08 ^ out1 (out) 0.08 data arrival time 10.00 10.00 clock clk (rise edge) 0.00 10.00 clock network delay (ideal) 0.00 10.00 clock reconvergence pessimism 0.00 10.00 output external delay 10.00 data required time --------------------------------------------------------- 10.00 data required time -0.08 data arrival time --------------------------------------------------------- 9.92 slack (MET)