--- bus port queries --- total ports: 27 data_a* ports: 8 data_b* ports: 8 result* ports: 8 --- individual bus bit queries --- data_a[0] direction: input data_a[1] direction: input data_a[2] direction: input data_a[3] direction: input data_a[4] direction: input data_a[5] direction: input data_a[6] direction: input data_a[7] direction: input result[0] direction: output result[1] direction: output result[2] direction: output result[3] direction: output result[4] direction: output result[5] direction: output result[6] direction: output result[7] direction: output --- wildcard bus subscript --- data_a[*] ports: 8 data_b[*] ports: 8 result[*] ports: 8 --- bus-style pin queries --- all pins: 98 buf_a* pins: 16 and* pins: 27 reg* pins: 48 --- bus-style net queries --- all nets: 45 stage1* nets: 8 stage2* nets: 8 --- cell pattern queries --- total cells: 28 buf* cells: 10 and* cells: 9 reg* cells: 8 or* cells: 1 --- hierarchical queries --- hierarchical cells: 28 hierarchical nets: 45 hierarchical pins: 98 --- report_net on bus nets --- Net stage1[0] Pin capacitance: 0.87-0.92 Wire capacitance: 0.00 Total capacitance: 0.87-0.92 Number of drivers: 1 Number of loads: 1 Number of pins: 2 Driver pins buf_a0/Z output (BUF_X1) Load pins and0/A1 input (AND2_X1) 0.87-0.92 report_net stage1[0]: done Net stage1[7] Pin capacitance: 0.87-0.92 Wire capacitance: 0.00 Total capacitance: 0.87-0.92 Number of drivers: 1 Number of loads: 1 Number of pins: 2 Driver pins buf_a7/Z output (BUF_X1) Load pins and7/A1 input (AND2_X1) 0.87-0.92 report_net stage1[7]: done Net stage2[0] Pin capacitance: 1.06-1.14 Wire capacitance: 0.00 Total capacitance: 1.06-1.14 Number of drivers: 1 Number of loads: 1 Number of pins: 2 Driver pins and0/ZN output (AND2_X1) Load pins reg0/D input (DFF_X1) 1.06-1.14 report_net stage2[0]: done Net stage2[7] Pin capacitance: 2.73-3.01 Wire capacitance: 0.00 Total capacitance: 2.73-3.01 Number of drivers: 1 Number of loads: 3 Number of pins: 4 Driver pins and7/ZN output (AND2_X1) Load pins and_ovfl/A1 input (AND2_X1) 0.87-0.92 or_carry/A1 input (OR2_X1) 0.79-0.95 reg7/D input (DFF_X1) 1.06-1.14 report_net stage2[7]: done --- report_instance on cells --- Instance buf_a0 Cell: BUF_X1 Library: NangateOpenCellLibrary Path cells: BUF_X1 Input pins: A input data_a[0] Output pins: Z output stage1[0] Other pins: VDD power (unconnected) VSS ground (unconnected) report_instance buf_a0: done Instance and0 Cell: AND2_X1 Library: NangateOpenCellLibrary Path cells: AND2_X1 Input pins: A1 input stage1[0] A2 input data_b[0] Output pins: ZN output stage2[0] Other pins: VDD power (unconnected) VSS ground (unconnected) report_instance and0: done Instance reg0 Cell: DFF_X1 Library: NangateOpenCellLibrary Path cells: DFF_X1 Input pins: D input stage2[0] CK input clk Output pins: Q output result[0] QN output (unconnected) Other pins: IQ internal (unconnected) IQN internal (unconnected) VDD power (unconnected) VSS ground (unconnected) report_instance reg0: done Instance or_carry Cell: OR2_X1 Library: NangateOpenCellLibrary Path cells: OR2_X1 Input pins: A1 input stage2[7] A2 input stage2[6] Output pins: ZN output internal_carry Other pins: VDD power (unconnected) VSS ground (unconnected) report_instance or_carry: done Instance buf_carry Cell: BUF_X1 Library: NangateOpenCellLibrary Path cells: BUF_X1 Input pins: A input internal_carry Output pins: Z output carry Other pins: VDD power (unconnected) VSS ground (unconnected) report_instance buf_carry: done --- lib cell queries --- BUF* lib cells: 6 AND* lib cells: 9 OR* lib cells: 9 INV* lib cells: 6 DFF* lib cells: 8 --- timing analysis --- Startpoint: data_a[6] (input port clocked by clk) Endpoint: carry (output port clocked by clk) Path Group: clk Path Type: max Delay Time Description --------------------------------------------------------- 0.00 0.00 clock clk (rise edge) 0.00 0.00 clock network delay (ideal) 0.00 0.00 v input external delay 0.00 0.00 v data_a[6] (in) 0.02 0.02 v buf_a6/Z (BUF_X1) 0.03 0.05 v and6/ZN (AND2_X1) 0.05 0.10 v or_carry/ZN (OR2_X1) 0.02 0.12 v buf_carry/Z (BUF_X1) 0.00 0.12 v carry (out) 0.12 data arrival time 10.00 10.00 clock clk (rise edge) 0.00 10.00 clock network delay (ideal) 0.00 10.00 clock reconvergence pessimism 0.00 10.00 output external delay 10.00 data required time --------------------------------------------------------- 10.00 data required time -0.12 data arrival time --------------------------------------------------------- 9.88 slack (MET) Startpoint: data_b[0] (input port clocked by clk) Endpoint: reg0 (rising edge-triggered flip-flop clocked by clk) Path Group: clk Path Type: min Delay Time Description --------------------------------------------------------- 0.00 0.00 clock clk (rise edge) 0.00 0.00 clock network delay (ideal) 0.00 0.00 ^ input external delay 0.00 0.00 ^ data_b[0] (in) 0.03 0.03 ^ and0/ZN (AND2_X1) 0.00 0.03 ^ reg0/D (DFF_X1) 0.03 data arrival time 0.00 0.00 clock clk (rise edge) 0.00 0.00 clock network delay (ideal) 0.00 0.00 clock reconvergence pessimism 0.00 ^ reg0/CK (DFF_X1) 0.01 0.01 library hold time 0.01 data required time --------------------------------------------------------- 0.01 data required time -0.03 data arrival time --------------------------------------------------------- 0.02 slack (MET) No paths found. Warning: network_bus_parse.tcl line 1, unknown field nets. Startpoint: data_a[6] (input port clocked by clk) Endpoint: carry (output port clocked by clk) Path Group: clk Path Type: max Fanout Cap Slew Delay Time Description ----------------------------------------------------------------------------- 0.00 0.00 0.00 clock clk (rise edge) 0.00 0.00 clock network delay (ideal) 0.00 0.00 v input external delay 1 0.88 0.00 0.00 0.00 v data_a[6] (in) 0.00 0.00 0.00 v buf_a6/A (BUF_X1) 1 0.87 0.00 0.02 0.02 v buf_a6/Z (BUF_X1) 0.00 0.00 0.02 v and6/A1 (AND2_X1) 3 2.85 0.01 0.03 0.05 v and6/ZN (AND2_X1) 0.01 0.00 0.05 v or_carry/A2 (OR2_X1) 1 0.88 0.01 0.05 0.10 v or_carry/ZN (OR2_X1) 0.01 0.00 0.10 v buf_carry/A (BUF_X1) 1 0.00 0.00 0.02 0.12 v buf_carry/Z (BUF_X1) 0.00 0.00 0.12 v carry (out) 0.12 data arrival time 0.00 10.00 10.00 clock clk (rise edge) 0.00 10.00 clock network delay (ideal) 0.00 10.00 clock reconvergence pessimism 0.00 10.00 output external delay 10.00 data required time ----------------------------------------------------------------------------- 10.00 data required time -0.12 data arrival time ----------------------------------------------------------------------------- 9.88 slack (MET) ALL PASSED