--- get_timing_edges -of_objects instance ---
reg1 timing edges count: 1
--- get_timing_edges -from/-to on instance ---
CK->Q edges count: 1
--- get_timing_edges -from only ---
edges from CK count: 5
--- get_timing_edges -to only ---
edges to Q count: 1
--- report_edges -from/-to ---
CK -> Q Reg Clk to Q
  ^ -> ^ 0.08:0.08
  ^ -> v 0.08:0.08
--- report_edges -from ---
CK -> QN Reg Clk to Q
  ^ -> ^ 0.06:0.06
  ^ -> v 0.06:0.06
CK -> Q Reg Clk to Q
  ^ -> ^ 0.08:0.08
  ^ -> v 0.08:0.08
CK -> CK width
  ^ -> v 0.05:0.05
  v -> ^ 0.05:0.05
CK -> D setup
  ^ -> ^ 0.03:0.03
  ^ -> v 0.04:0.04
CK -> D hold
  ^ -> ^ 0.00:0.00
  ^ -> v 0.00:0.00
--- report_edges -to ---
CK -> D setup
  ^ -> ^ 0.03:0.03
  ^ -> v 0.04:0.04
CK -> D hold
  ^ -> ^ 0.01:0.01
  ^ -> v 0.00:0.00
reg1/Q -> D wire
  ^ -> ^ 0.00:0.00
  v -> v 0.00:0.00
--- report_disabled_edges (baseline) ---
--- set_disable_timing on instance ---
--- report_disabled_edges after disable ---
reg1 CK Q constraint
reg1 CK QN constraint
--- report_checks after disable ---
Startpoint: reg2 (rising edge-triggered flip-flop clocked by clk)
Endpoint: q (output port clocked by clk)
Path Group: clk
Path Type: max

  Delay    Time   Description
---------------------------------------------------------
   0.00    0.00   clock clk (rise edge)
   0.00    0.00   clock network delay (ideal)
   0.00    0.00 ^ reg2/CK (DFF_X1)
   0.08    0.08 ^ reg2/Q (DFF_X1)
   0.00    0.08 ^ q (out)
           0.08   data arrival time

  10.00   10.00   clock clk (rise edge)
   0.00   10.00   clock network delay (ideal)
   0.00   10.00   clock reconvergence pessimism
   0.00   10.00   output external delay
          10.00   data required time
---------------------------------------------------------
          10.00   data required time
          -0.08   data arrival time
---------------------------------------------------------
           9.92   slack (MET)


--- unset_disable_timing on instance ---
--- report_disabled_edges after unset ---
--- set_disable_timing with -from/-to on lib cell ---
--- report_disabled_edges after lib cell disable ---
reg1 CK Q constraint
reg2 CK Q constraint
--- unset_disable_timing lib cell ---
--- report_checks baseline ---
Startpoint: reg1 (rising edge-triggered flip-flop clocked by clk)
Endpoint: reg2 (rising edge-triggered flip-flop clocked by clk)
Path Group: clk
Path Type: max

  Delay    Time   Description
---------------------------------------------------------
   0.00    0.00   clock clk (rise edge)
   0.00    0.00   clock network delay (ideal)
   0.00    0.00 ^ reg1/CK (DFF_X1)
   0.08    0.08 v reg1/Q (DFF_X1)
   0.00    0.08 v reg2/D (DFF_X1)
           0.08   data arrival time

  10.00   10.00   clock clk (rise edge)
   0.00   10.00   clock network delay (ideal)
   0.00   10.00   clock reconvergence pessimism
          10.00 ^ reg2/CK (DFF_X1)
  -0.04    9.96   library setup time
           9.96   data required time
---------------------------------------------------------
           9.96   data required time
          -0.08   data arrival time
---------------------------------------------------------
           9.88   slack (MET)


--- report_checks -path_delay max ---
Startpoint: reg1 (rising edge-triggered flip-flop clocked by clk)
Endpoint: reg2 (rising edge-triggered flip-flop clocked by clk)
Path Group: clk
Path Type: max

  Delay    Time   Description
---------------------------------------------------------
   0.00    0.00   clock clk (rise edge)
   0.00    0.00   clock network delay (ideal)
   0.00    0.00 ^ reg1/CK (DFF_X1)
   0.08    0.08 v reg1/Q (DFF_X1)
   0.00    0.08 v reg2/D (DFF_X1)
           0.08   data arrival time

  10.00   10.00   clock clk (rise edge)
   0.00   10.00   clock network delay (ideal)
   0.00   10.00   clock reconvergence pessimism
          10.00 ^ reg2/CK (DFF_X1)
  -0.04    9.96   library setup time
           9.96   data required time
---------------------------------------------------------
           9.96   data required time
          -0.08   data arrival time
---------------------------------------------------------
           9.88   slack (MET)


--- report_checks -path_delay min ---
Startpoint: d (input port clocked by clk)
Endpoint: reg1 (rising edge-triggered flip-flop clocked by clk)
Path Group: clk
Path Type: min

  Delay    Time   Description
---------------------------------------------------------
   0.00    0.00   clock clk (rise edge)
   0.00    0.00   clock network delay (ideal)
   0.00    0.00 ^ input external delay
   0.00    0.00 ^ d (in)
   0.00    0.00 ^ reg1/D (DFF_X1)
           0.00   data arrival time

   0.00    0.00   clock clk (rise edge)
   0.00    0.00   clock network delay (ideal)
   0.00    0.00   clock reconvergence pessimism
           0.00 ^ reg1/CK (DFF_X1)
   0.00    0.00   library hold time
           0.00   data required time
---------------------------------------------------------
           0.00   data required time
          -0.00   data arrival time
---------------------------------------------------------
           0.00   slack (VIOLATED)


--- report_checks from d to q ---
No paths found.
--- report_edges -from port d ---
d -> reg1/D wire
  ^ -> ^ 0.00:0.00
  v -> v 0.00:0.00
--- report_edges -to port q ---
reg2/Q -> q wire
  ^ -> ^ 0.00:0.00
  v -> v 0.00:0.00
--- get_timing_edges -of_objects reg2 ---
reg2 timing edges count: 1
--- report_slews on d port ---
d ^ 0.00:0.00 v 0.00:0.00
--- report_slews on q port ---
q ^ 0.01:0.01 v 0.00:0.00