time 1ns capacitance 1fF resistance 1kohm voltage 1v current 1mA power 1nW distance 1um Startpoint: data_a[6] (input port clocked by clk) Endpoint: carry (output port clocked by clk) Path Group: clk Path Type: max Delay Time Description --------------------------------------------------------- 0.00 0.00 clock clk (rise edge) 0.00 0.00 clock network delay (ideal) 0.00 0.00 v input external delay 0.00 0.00 v data_a[6] (in) 0.06 0.06 v buf_a6/Z (BUF_X1) 0.03 0.09 v and6/ZN (AND2_X1) 0.05 0.13 v or_carry/ZN (OR2_X1) 0.02 0.16 v buf_carry/Z (BUF_X1) 0.00 0.16 v carry (out) 0.16 data arrival time 10.00 10.00 clock clk (rise edge) 0.00 10.00 clock network delay (ideal) 0.00 10.00 clock reconvergence pessimism 0.00 10.00 output external delay 10.00 data required time --------------------------------------------------------- 10.00 data required time -0.16 data arrival time --------------------------------------------------------- 9.84 slack (MET) Startpoint: data_b[0] (input port clocked by clk) Endpoint: reg0 (rising edge-triggered flip-flop clocked by clk) Path Group: clk Path Type: min Delay Time Description --------------------------------------------------------- 0.00 0.00 clock clk (rise edge) 0.00 0.00 clock network delay (ideal) 0.00 0.00 ^ input external delay 0.00 0.00 ^ data_b[0] (in) 0.04 0.04 ^ and0/ZN (AND2_X1) 0.00 0.04 ^ reg0/D (DFF_X1) 0.04 data arrival time 0.00 0.00 clock clk (rise edge) 0.00 0.00 clock network delay (ideal) 0.00 0.00 clock reconvergence pessimism 0.00 ^ reg0/CK (DFF_X1) 0.01 0.01 library hold time 0.01 data required time --------------------------------------------------------- 0.01 data required time -0.04 data arrival time --------------------------------------------------------- 0.04 slack (MET)