--- read_sdf --- --- report_annotated_delay (all) --- Not Delay type Total Annotated Annotated ---------------------------------------------------------------- cell arcs 3 2 1 internal net arcs 1 0 1 net arcs from primary inputs 2 0 2 net arcs to primary outputs 1 0 1 ---------------------------------------------------------------- 7 2 5 --- report_annotated_delay -cell --- Not Delay type Total Annotated Annotated ---------------------------------------------------------------- cell arcs 3 2 1 ---------------------------------------------------------------- 3 2 1 --- report_annotated_delay -net --- Not Delay type Total Annotated Annotated ---------------------------------------------------------------- internal net arcs 1 0 1 ---------------------------------------------------------------- 1 0 1 --- report_annotated_delay -from_in_ports --- Not Delay type Total Annotated Annotated ---------------------------------------------------------------- net arcs from primary inputs 2 0 2 ---------------------------------------------------------------- 2 0 2 --- report_annotated_delay -to_out_ports --- Not Delay type Total Annotated Annotated ---------------------------------------------------------------- net arcs to primary outputs 1 0 1 ---------------------------------------------------------------- 1 0 1 --- report_annotated_delay -cell -report_annotated --- Not Delay type Total Annotated Annotated ---------------------------------------------------------------- cell arcs 3 2 1 ---------------------------------------------------------------- 3 2 1 Annotated Arcs delay buf1/A -> buf1/Z delay reg1/CK -> reg1/Q --- report_annotated_delay -cell -report_unannotated --- Not Delay type Total Annotated Annotated ---------------------------------------------------------------- cell arcs 3 2 1 ---------------------------------------------------------------- 3 2 1 Unannotated Arcs delay reg1/CK -> reg1/QN --- report_annotated_delay -constant_arcs --- Not Delay type Total Annotated Annotated ---------------------------------------------------------------- cell arcs 3 2 1 constant arcs 0 0 internal net arcs 1 0 1 constant arcs 0 0 net arcs from primary inputs 2 0 2 constant arcs 0 0 net arcs to primary outputs 1 0 1 constant arcs 0 0 ---------------------------------------------------------------- 7 2 5 --- report_annotated_delay -max_lines 5 --- Not Delay type Total Annotated Annotated ---------------------------------------------------------------- cell arcs 3 2 1 internal net arcs 1 0 1 net arcs from primary inputs 2 0 2 net arcs to primary outputs 1 0 1 ---------------------------------------------------------------- 7 2 5 --- report_annotated_check (all) --- Not Check type Total Annotated Annotated ---------------------------------------------------------------- cell setup arcs 1 0 1 cell hold arcs 1 0 1 cell width arcs 1 0 1 ---------------------------------------------------------------- 3 0 3 --- report_annotated_check -setup --- Not Check type Total Annotated Annotated ---------------------------------------------------------------- cell setup arcs 1 0 1 ---------------------------------------------------------------- 1 0 1 --- report_annotated_check -hold --- Not Check type Total Annotated Annotated ---------------------------------------------------------------- cell hold arcs 1 0 1 ---------------------------------------------------------------- 1 0 1 --- report_annotated_check -recovery --- Not Check type Total Annotated Annotated ---------------------------------------------------------------- ---------------------------------------------------------------- 0 0 0 --- report_annotated_check -removal --- Not Check type Total Annotated Annotated ---------------------------------------------------------------- ---------------------------------------------------------------- 0 0 0 --- report_annotated_check -width --- Not Check type Total Annotated Annotated ---------------------------------------------------------------- cell width arcs 1 0 1 ---------------------------------------------------------------- 1 0 1 --- report_annotated_check -period --- Not Check type Total Annotated Annotated ---------------------------------------------------------------- ---------------------------------------------------------------- 0 0 0 --- report_annotated_check -setup -report_annotated --- Not Check type Total Annotated Annotated ---------------------------------------------------------------- cell setup arcs 1 0 1 ---------------------------------------------------------------- 1 0 1 Annotated Arcs --- report_annotated_check -setup -report_unannotated --- Not Check type Total Annotated Annotated ---------------------------------------------------------------- cell setup arcs 1 0 1 ---------------------------------------------------------------- 1 0 1 Unannotated Arcs setup reg1/CK -> reg1/D --- report_annotated_check -constant_arcs --- Not Check type Total Annotated Annotated ---------------------------------------------------------------- cell setup arcs 1 0 1 constant arcs 0 0 cell hold arcs 1 0 1 constant arcs 0 0 cell width arcs 1 0 1 constant arcs 0 0 ---------------------------------------------------------------- 3 0 3 --- report_annotated_check -max_lines 5 --- Not Check type Total Annotated Annotated ---------------------------------------------------------------- cell setup arcs 1 0 1 cell hold arcs 1 0 1 cell width arcs 1 0 1 ---------------------------------------------------------------- 3 0 3 --- report_checks (shows annotated delays) --- Startpoint: reg1 (rising edge-triggered flip-flop clocked by clk) Endpoint: q (output port clocked by clk) Path Group: clk Path Type: max Delay Time Description --------------------------------------------------------- 0.00 0.00 clock clk (rise edge) 0.00 0.00 clock network delay (ideal) 0.00 0.00 ^ reg1/CK (DFF_X1) 0.40 0.40 ^ reg1/Q (DFF_X1) 0.00 0.40 ^ q (out) 0.40 data arrival time 10.00 10.00 clock clk (rise edge) 0.00 10.00 clock network delay (ideal) 0.00 10.00 clock reconvergence pessimism 0.00 10.00 output external delay 10.00 data required time --------------------------------------------------------- 10.00 data required time -0.40 data arrival time --------------------------------------------------------- 9.60 slack (MET) --- report_checks -format full_clock --- Startpoint: reg1 (rising edge-triggered flip-flop clocked by clk) Endpoint: q (output port clocked by clk) Path Group: clk Path Type: max Delay Time Description --------------------------------------------------------- 0.00 0.00 clock clk (rise edge) 0.00 0.00 clock network delay (ideal) 0.00 0.00 ^ reg1/CK (DFF_X1) 0.40 0.40 ^ reg1/Q (DFF_X1) 0.00 0.40 ^ q (out) 0.40 data arrival time 10.00 10.00 clock clk (rise edge) 0.00 10.00 clock network delay (ideal) 0.00 10.00 clock reconvergence pessimism 0.00 10.00 output external delay 10.00 data required time --------------------------------------------------------- 10.00 data required time -0.40 data arrival time --------------------------------------------------------- 9.60 slack (MET) --- report_checks -path_delay min --- Startpoint: d (input port clocked by clk) Endpoint: reg1 (rising edge-triggered flip-flop clocked by clk) Path Group: clk Path Type: min Delay Time Description --------------------------------------------------------- 0.00 0.00 clock clk (rise edge) 0.00 0.00 clock network delay (ideal) 0.00 0.00 ^ input external delay 0.00 0.00 ^ d (in) 0.10 0.10 ^ buf1/Z (BUF_X1) 0.00 0.10 ^ reg1/D (DFF_X1) 0.10 data arrival time 0.00 0.00 clock clk (rise edge) 0.00 0.00 clock network delay (ideal) 0.00 0.00 clock reconvergence pessimism 0.00 ^ reg1/CK (DFF_X1) 0.00 0.00 library hold time 0.00 data required time --------------------------------------------------------- 0.00 data required time -0.10 data arrival time --------------------------------------------------------- 0.10 slack (MET)