--- initial timing --- Startpoint: reg1 (rising edge-triggered flip-flop clocked by clk) Endpoint: out1 (output port clocked by clk) Path Group: clk Path Type: max Delay Time Description --------------------------------------------------------- 0.00 0.00 clock clk (rise edge) 0.00 0.00 clock network delay (ideal) 0.00 0.00 ^ reg1/CK (DFF_X1) 0.09 0.09 ^ reg1/Q (DFF_X1) 0.02 0.10 ^ buf2/Z (BUF_X1) 0.00 0.10 ^ out1 (out) 0.10 data arrival time 10.00 10.00 clock clk (rise edge) 0.00 10.00 clock network delay (ideal) 0.00 10.00 clock reconvergence pessimism -2.00 8.00 output external delay 8.00 data required time --------------------------------------------------------- 8.00 data required time -0.10 data arrival time --------------------------------------------------------- 7.90 slack (MET) Startpoint: reg1 (rising edge-triggered flip-flop clocked by clk) Endpoint: reg2 (rising edge-triggered flip-flop clocked by clk2) Path Group: clk2 Path Type: max Delay Time Description --------------------------------------------------------- 10.00 10.00 clock clk (rise edge) 0.00 10.00 clock network delay (ideal) 0.00 10.00 ^ reg1/CK (DFF_X1) 0.08 10.08 v reg1/Q (DFF_X1) 0.00 10.08 v reg2/D (DFF_X1) 10.08 data arrival time 15.00 15.00 clock clk2 (rise edge) 0.00 15.00 clock network delay (ideal) 0.00 15.00 clock reconvergence pessimism 15.00 ^ reg2/CK (DFF_X1) -0.04 14.96 library setup time 14.96 data required time --------------------------------------------------------- 14.96 data required time -10.08 data arrival time --------------------------------------------------------- 4.88 slack (MET) Startpoint: in_unconst (input port clocked by clk) Endpoint: reg3 (rising edge-triggered flip-flop clocked by clk) Path Group: clk Path Type: min Delay Time Description --------------------------------------------------------- 0.00 0.00 clock clk (rise edge) 0.00 0.00 clock network delay (ideal) 0.50 0.50 ^ input external delay 0.00 0.50 ^ in_unconst (in) 0.02 0.52 ^ buf4/Z (BUF_X1) 0.00 0.52 ^ reg3/D (DFF_X1) 0.52 data arrival time 0.00 0.00 clock clk (rise edge) 0.00 0.00 clock network delay (ideal) 0.00 0.00 clock reconvergence pessimism 0.00 ^ reg3/CK (DFF_X1) 0.00 0.00 library hold time 0.00 data required time --------------------------------------------------------- 0.00 data required time -0.52 data arrival time --------------------------------------------------------- 0.51 slack (MET) Startpoint: reg1 (rising edge-triggered flip-flop clocked by clk) Endpoint: reg2 (rising edge-triggered flip-flop clocked by clk2) Path Group: clk2 Path Type: min Delay Time Description --------------------------------------------------------- 0.00 0.00 clock clk (rise edge) 0.00 0.00 clock network delay (ideal) 0.00 0.00 ^ reg1/CK (DFF_X1) 0.08 0.08 v reg1/Q (DFF_X1) 0.00 0.08 v reg2/D (DFF_X1) 0.08 data arrival time 0.00 0.00 clock clk2 (rise edge) 0.00 0.00 clock network delay (ideal) 0.00 0.00 clock reconvergence pessimism 0.00 ^ reg2/CK (DFF_X1) 0.00 0.00 library hold time 0.00 data required time --------------------------------------------------------- 0.00 data required time -0.08 data arrival time --------------------------------------------------------- 0.08 slack (MET) --- disable_timing --- Startpoint: reg1 (rising edge-triggered flip-flop clocked by clk) Endpoint: out1 (output port clocked by clk) Path Group: clk Path Type: max Delay Time Description --------------------------------------------------------- 0.00 0.00 clock clk (rise edge) 0.00 0.00 clock network delay (ideal) 0.00 0.00 ^ reg1/CK (DFF_X1) 0.09 0.09 ^ reg1/Q (DFF_X1) 0.02 0.10 ^ buf2/Z (BUF_X1) 0.00 0.10 ^ out1 (out) 0.10 data arrival time 10.00 10.00 clock clk (rise edge) 0.00 10.00 clock network delay (ideal) 0.00 10.00 clock reconvergence pessimism -2.00 8.00 output external delay 8.00 data required time --------------------------------------------------------- 8.00 data required time -0.10 data arrival time --------------------------------------------------------- 7.90 slack (MET) Startpoint: reg1 (rising edge-triggered flip-flop clocked by clk) Endpoint: reg2 (rising edge-triggered flip-flop clocked by clk2) Path Group: clk2 Path Type: max Delay Time Description --------------------------------------------------------- 10.00 10.00 clock clk (rise edge) 0.00 10.00 clock network delay (ideal) 0.00 10.00 ^ reg1/CK (DFF_X1) 0.08 10.08 v reg1/Q (DFF_X1) 0.00 10.08 v reg2/D (DFF_X1) 10.08 data arrival time 15.00 15.00 clock clk2 (rise edge) 0.00 15.00 clock network delay (ideal) 0.00 15.00 clock reconvergence pessimism 15.00 ^ reg2/CK (DFF_X1) -0.04 14.96 library setup time 14.96 data required time --------------------------------------------------------- 14.96 data required time -10.08 data arrival time --------------------------------------------------------- 4.88 slack (MET) --- enable_timing --- Startpoint: reg1 (rising edge-triggered flip-flop clocked by clk) Endpoint: out1 (output port clocked by clk) Path Group: clk Path Type: max Delay Time Description --------------------------------------------------------- 0.00 0.00 clock clk (rise edge) 0.00 0.00 clock network delay (ideal) 0.00 0.00 ^ reg1/CK (DFF_X1) 0.09 0.09 ^ reg1/Q (DFF_X1) 0.02 0.10 ^ buf2/Z (BUF_X1) 0.00 0.10 ^ out1 (out) 0.10 data arrival time 10.00 10.00 clock clk (rise edge) 0.00 10.00 clock network delay (ideal) 0.00 10.00 clock reconvergence pessimism -2.00 8.00 output external delay 8.00 data required time --------------------------------------------------------- 8.00 data required time -0.10 data arrival time --------------------------------------------------------- 7.90 slack (MET) Startpoint: reg1 (rising edge-triggered flip-flop clocked by clk) Endpoint: reg2 (rising edge-triggered flip-flop clocked by clk2) Path Group: clk2 Path Type: max Delay Time Description --------------------------------------------------------- 10.00 10.00 clock clk (rise edge) 0.00 10.00 clock network delay (ideal) 0.00 10.00 ^ reg1/CK (DFF_X1) 0.08 10.08 v reg1/Q (DFF_X1) 0.00 10.08 v reg2/D (DFF_X1) 10.08 data arrival time 15.00 15.00 clock clk2 (rise edge) 0.00 15.00 clock network delay (ideal) 0.00 15.00 clock reconvergence pessimism 15.00 ^ reg2/CK (DFF_X1) -0.04 14.96 library setup time 14.96 data required time --------------------------------------------------------- 14.96 data required time -10.08 data arrival time --------------------------------------------------------- 4.88 slack (MET) --- disable lib cell arcs --- Warning: search_levelize_loop_disabled.tcl line 1, library 'Nangate45' not found. Startpoint: reg1 (rising edge-triggered flip-flop clocked by clk) Endpoint: out1 (output port clocked by clk) Path Group: clk Path Type: max Delay Time Description --------------------------------------------------------- 0.00 0.00 clock clk (rise edge) 0.00 0.00 clock network delay (ideal) 0.00 0.00 ^ reg1/CK (DFF_X1) 0.09 0.09 ^ reg1/Q (DFF_X1) 0.02 0.10 ^ buf2/Z (BUF_X1) 0.00 0.10 ^ out1 (out) 0.10 data arrival time 10.00 10.00 clock clk (rise edge) 0.00 10.00 clock network delay (ideal) 0.00 10.00 clock reconvergence pessimism -2.00 8.00 output external delay 8.00 data required time --------------------------------------------------------- 8.00 data required time -0.10 data arrival time --------------------------------------------------------- 7.90 slack (MET) Startpoint: reg1 (rising edge-triggered flip-flop clocked by clk) Endpoint: reg2 (rising edge-triggered flip-flop clocked by clk2) Path Group: clk2 Path Type: max Delay Time Description --------------------------------------------------------- 10.00 10.00 clock clk (rise edge) 0.00 10.00 clock network delay (ideal) 0.00 10.00 ^ reg1/CK (DFF_X1) 0.08 10.08 v reg1/Q (DFF_X1) 0.00 10.08 v reg2/D (DFF_X1) 10.08 data arrival time 15.00 15.00 clock clk2 (rise edge) 0.00 15.00 clock network delay (ideal) 0.00 15.00 clock reconvergence pessimism 15.00 ^ reg2/CK (DFF_X1) -0.04 14.96 library setup time 14.96 data required time --------------------------------------------------------- 14.96 data required time -10.08 data arrival time --------------------------------------------------------- 4.88 slack (MET) --- re-enable lib cell arcs --- Warning: search_levelize_loop_disabled.tcl line 1, library 'Nangate45' not found. Startpoint: reg1 (rising edge-triggered flip-flop clocked by clk) Endpoint: out1 (output port clocked by clk) Path Group: clk Path Type: max Delay Time Description --------------------------------------------------------- 0.00 0.00 clock clk (rise edge) 0.00 0.00 clock network delay (ideal) 0.00 0.00 ^ reg1/CK (DFF_X1) 0.09 0.09 ^ reg1/Q (DFF_X1) 0.02 0.10 ^ buf2/Z (BUF_X1) 0.00 0.10 ^ out1 (out) 0.10 data arrival time 10.00 10.00 clock clk (rise edge) 0.00 10.00 clock network delay (ideal) 0.00 10.00 clock reconvergence pessimism -2.00 8.00 output external delay 8.00 data required time --------------------------------------------------------- 8.00 data required time -0.10 data arrival time --------------------------------------------------------- 7.90 slack (MET) Startpoint: reg1 (rising edge-triggered flip-flop clocked by clk) Endpoint: reg2 (rising edge-triggered flip-flop clocked by clk2) Path Group: clk2 Path Type: max Delay Time Description --------------------------------------------------------- 10.00 10.00 clock clk (rise edge) 0.00 10.00 clock network delay (ideal) 0.00 10.00 ^ reg1/CK (DFF_X1) 0.08 10.08 v reg1/Q (DFF_X1) 0.00 10.08 v reg2/D (DFF_X1) 10.08 data arrival time 15.00 15.00 clock clk2 (rise edge) 0.00 15.00 clock network delay (ideal) 0.00 15.00 clock reconvergence pessimism 15.00 ^ reg2/CK (DFF_X1) -0.04 14.96 library setup time 14.96 data required time --------------------------------------------------------- 14.96 data required time -10.08 data arrival time --------------------------------------------------------- 4.88 slack (MET) --- set_case_analysis --- Startpoint: reg1 (rising edge-triggered flip-flop clocked by clk) Endpoint: out1 (output port clocked by clk) Path Group: clk Path Type: max Delay Time Description --------------------------------------------------------- 0.00 0.00 clock clk (rise edge) 0.00 0.00 clock network delay (ideal) 0.00 0.00 ^ reg1/CK (DFF_X1) 0.09 0.09 ^ reg1/Q (DFF_X1) 0.02 0.10 ^ buf2/Z (BUF_X1) 0.00 0.10 ^ out1 (out) 0.10 data arrival time 10.00 10.00 clock clk (rise edge) 0.00 10.00 clock network delay (ideal) 0.00 10.00 clock reconvergence pessimism -2.00 8.00 output external delay 8.00 data required time --------------------------------------------------------- 8.00 data required time -0.10 data arrival time --------------------------------------------------------- 7.90 slack (MET) Startpoint: reg1 (rising edge-triggered flip-flop clocked by clk) Endpoint: reg2 (rising edge-triggered flip-flop clocked by clk2) Path Group: clk2 Path Type: max Delay Time Description --------------------------------------------------------- 10.00 10.00 clock clk (rise edge) 0.00 10.00 clock network delay (ideal) 0.00 10.00 ^ reg1/CK (DFF_X1) 0.08 10.08 v reg1/Q (DFF_X1) 0.00 10.08 v reg2/D (DFF_X1) 10.08 data arrival time 15.00 15.00 clock clk2 (rise edge) 0.00 15.00 clock network delay (ideal) 0.00 15.00 clock reconvergence pessimism 15.00 ^ reg2/CK (DFF_X1) -0.04 14.96 library setup time 14.96 data required time --------------------------------------------------------- 14.96 data required time -10.08 data arrival time --------------------------------------------------------- 4.88 slack (MET) --- remove case_analysis --- Startpoint: reg1 (rising edge-triggered flip-flop clocked by clk) Endpoint: out1 (output port clocked by clk) Path Group: clk Path Type: max Delay Time Description --------------------------------------------------------- 0.00 0.00 clock clk (rise edge) 0.00 0.00 clock network delay (ideal) 0.00 0.00 ^ reg1/CK (DFF_X1) 0.09 0.09 ^ reg1/Q (DFF_X1) 0.02 0.10 ^ buf2/Z (BUF_X1) 0.00 0.10 ^ out1 (out) 0.10 data arrival time 10.00 10.00 clock clk (rise edge) 0.00 10.00 clock network delay (ideal) 0.00 10.00 clock reconvergence pessimism -2.00 8.00 output external delay 8.00 data required time --------------------------------------------------------- 8.00 data required time -0.10 data arrival time --------------------------------------------------------- 7.90 slack (MET) Startpoint: reg1 (rising edge-triggered flip-flop clocked by clk) Endpoint: reg2 (rising edge-triggered flip-flop clocked by clk2) Path Group: clk2 Path Type: max Delay Time Description --------------------------------------------------------- 10.00 10.00 clock clk (rise edge) 0.00 10.00 clock network delay (ideal) 0.00 10.00 ^ reg1/CK (DFF_X1) 0.08 10.08 v reg1/Q (DFF_X1) 0.00 10.08 v reg2/D (DFF_X1) 10.08 data arrival time 15.00 15.00 clock clk2 (rise edge) 0.00 15.00 clock network delay (ideal) 0.00 15.00 clock reconvergence pessimism 15.00 ^ reg2/CK (DFF_X1) -0.04 14.96 library setup time 14.96 data required time --------------------------------------------------------- 14.96 data required time -10.08 data arrival time --------------------------------------------------------- 4.88 slack (MET) --- check_setup --- Warning: There is 1 output port missing set_output_delay. out_unconst Warning: There is 1 unconstrained endpoint. out_unconst --- report_disabled_edges --- --- inter-clock uncertainty --- Startpoint: reg1 (rising edge-triggered flip-flop clocked by clk) Endpoint: out1 (output port clocked by clk) Path Group: clk Path Type: max Delay Time Description --------------------------------------------------------- 0.00 0.00 clock clk (rise edge) 0.00 0.00 clock network delay (ideal) 0.00 0.00 ^ reg1/CK (DFF_X1) 0.09 0.09 ^ reg1/Q (DFF_X1) 0.02 0.10 ^ buf2/Z (BUF_X1) 0.00 0.10 ^ out1 (out) 0.10 data arrival time 10.00 10.00 clock clk (rise edge) 0.00 10.00 clock network delay (ideal) 0.00 10.00 clock reconvergence pessimism -2.00 8.00 output external delay 8.00 data required time --------------------------------------------------------- 8.00 data required time -0.10 data arrival time --------------------------------------------------------- 7.90 slack (MET) Startpoint: reg1 (rising edge-triggered flip-flop clocked by clk) Endpoint: reg2 (rising edge-triggered flip-flop clocked by clk2) Path Group: clk2 Path Type: max Delay Time Description --------------------------------------------------------- 10.00 10.00 clock clk (rise edge) 0.00 10.00 clock network delay (ideal) 0.00 10.00 ^ reg1/CK (DFF_X1) 0.08 10.08 v reg1/Q (DFF_X1) 0.00 10.08 v reg2/D (DFF_X1) 10.08 data arrival time 15.00 15.00 clock clk2 (rise edge) 0.00 15.00 clock network delay (ideal) -0.50 14.50 inter-clock uncertainty 0.00 14.50 clock reconvergence pessimism 14.50 ^ reg2/CK (DFF_X1) -0.04 14.46 library setup time 14.46 data required time --------------------------------------------------------- 14.46 data required time -10.08 data arrival time --------------------------------------------------------- 4.38 slack (MET) Startpoint: in_unconst (input port clocked by clk) Endpoint: reg3 (rising edge-triggered flip-flop clocked by clk) Path Group: clk Path Type: min Delay Time Description --------------------------------------------------------- 0.00 0.00 clock clk (rise edge) 0.00 0.00 clock network delay (ideal) 0.50 0.50 ^ input external delay 0.00 0.50 ^ in_unconst (in) 0.02 0.52 ^ buf4/Z (BUF_X1) 0.00 0.52 ^ reg3/D (DFF_X1) 0.52 data arrival time 0.00 0.00 clock clk (rise edge) 0.00 0.00 clock network delay (ideal) 0.00 0.00 clock reconvergence pessimism 0.00 ^ reg3/CK (DFF_X1) 0.00 0.00 library hold time 0.00 data required time --------------------------------------------------------- 0.00 data required time -0.52 data arrival time --------------------------------------------------------- 0.51 slack (MET) Startpoint: reg1 (rising edge-triggered flip-flop clocked by clk) Endpoint: reg2 (rising edge-triggered flip-flop clocked by clk2) Path Group: clk2 Path Type: min Delay Time Description --------------------------------------------------------- 0.00 0.00 clock clk (rise edge) 0.00 0.00 clock network delay (ideal) 0.00 0.00 ^ reg1/CK (DFF_X1) 0.08 0.08 v reg1/Q (DFF_X1) 0.00 0.08 v reg2/D (DFF_X1) 0.08 data arrival time 0.00 0.00 clock clk2 (rise edge) 0.00 0.00 clock network delay (ideal) 0.20 0.20 inter-clock uncertainty 0.00 0.20 clock reconvergence pessimism 0.20 ^ reg2/CK (DFF_X1) 0.00 0.20 library hold time 0.20 data required time --------------------------------------------------------- 0.20 data required time -0.08 data arrival time --------------------------------------------------------- -0.12 slack (VIOLATED) --- disable_timing whole instance --- Startpoint: reg1 (rising edge-triggered flip-flop clocked by clk) Endpoint: out1 (output port clocked by clk) Path Group: clk Path Type: max Delay Time Description --------------------------------------------------------- 0.00 0.00 clock clk (rise edge) 0.00 0.00 clock network delay (ideal) 0.00 0.00 ^ reg1/CK (DFF_X1) 0.09 0.09 ^ reg1/Q (DFF_X1) 0.02 0.10 ^ buf2/Z (BUF_X1) 0.00 0.10 ^ out1 (out) 0.10 data arrival time 10.00 10.00 clock clk (rise edge) 0.00 10.00 clock network delay (ideal) 0.00 10.00 clock reconvergence pessimism -2.00 8.00 output external delay 8.00 data required time --------------------------------------------------------- 8.00 data required time -0.10 data arrival time --------------------------------------------------------- 7.90 slack (MET) Startpoint: reg1 (rising edge-triggered flip-flop clocked by clk) Endpoint: reg2 (rising edge-triggered flip-flop clocked by clk2) Path Group: clk2 Path Type: max Delay Time Description --------------------------------------------------------- 10.00 10.00 clock clk (rise edge) 0.00 10.00 clock network delay (ideal) 0.00 10.00 ^ reg1/CK (DFF_X1) 0.08 10.08 v reg1/Q (DFF_X1) 0.00 10.08 v reg2/D (DFF_X1) 10.08 data arrival time 15.00 15.00 clock clk2 (rise edge) 0.00 15.00 clock network delay (ideal) -0.50 14.50 inter-clock uncertainty 0.00 14.50 clock reconvergence pessimism 14.50 ^ reg2/CK (DFF_X1) -0.04 14.46 library setup time 14.46 data required time --------------------------------------------------------- 14.46 data required time -10.08 data arrival time --------------------------------------------------------- 4.38 slack (MET) --- enable_timing whole instance --- Startpoint: reg1 (rising edge-triggered flip-flop clocked by clk) Endpoint: out1 (output port clocked by clk) Path Group: clk Path Type: max Delay Time Description --------------------------------------------------------- 0.00 0.00 clock clk (rise edge) 0.00 0.00 clock network delay (ideal) 0.00 0.00 ^ reg1/CK (DFF_X1) 0.09 0.09 ^ reg1/Q (DFF_X1) 0.02 0.10 ^ buf2/Z (BUF_X1) 0.00 0.10 ^ out1 (out) 0.10 data arrival time 10.00 10.00 clock clk (rise edge) 0.00 10.00 clock network delay (ideal) 0.00 10.00 clock reconvergence pessimism -2.00 8.00 output external delay 8.00 data required time --------------------------------------------------------- 8.00 data required time -0.10 data arrival time --------------------------------------------------------- 7.90 slack (MET) Startpoint: reg1 (rising edge-triggered flip-flop clocked by clk) Endpoint: reg2 (rising edge-triggered flip-flop clocked by clk2) Path Group: clk2 Path Type: max Delay Time Description --------------------------------------------------------- 10.00 10.00 clock clk (rise edge) 0.00 10.00 clock network delay (ideal) 0.00 10.00 ^ reg1/CK (DFF_X1) 0.08 10.08 v reg1/Q (DFF_X1) 0.00 10.08 v reg2/D (DFF_X1) 10.08 data arrival time 15.00 15.00 clock clk2 (rise edge) 0.00 15.00 clock network delay (ideal) -0.50 14.50 inter-clock uncertainty 0.00 14.50 clock reconvergence pessimism 14.50 ^ reg2/CK (DFF_X1) -0.04 14.46 library setup time 14.46 data required time --------------------------------------------------------- 14.46 data required time -10.08 data arrival time --------------------------------------------------------- 4.38 slack (MET) --- check_setup -loops --- --- multiple re-levelize triggers --- Startpoint: reg1 (rising edge-triggered flip-flop clocked by clk) Endpoint: out1 (output port clocked by clk) Path Group: clk Path Type: max Delay Time Description --------------------------------------------------------- 0.00 0.00 clock clk (rise edge) 0.00 0.00 clock network delay (ideal) 0.00 0.00 ^ reg1/CK (DFF_X1) 0.09 0.09 ^ reg1/Q (DFF_X1) 0.02 0.10 ^ buf2/Z (BUF_X1) 0.00 0.10 ^ out1 (out) 0.10 data arrival time 10.00 10.00 clock clk (rise edge) 0.00 10.00 clock network delay (ideal) 0.00 10.00 clock reconvergence pessimism -2.00 8.00 output external delay 8.00 data required time --------------------------------------------------------- 8.00 data required time -0.10 data arrival time --------------------------------------------------------- 7.90 slack (MET) Startpoint: reg1 (rising edge-triggered flip-flop clocked by clk) Endpoint: reg2 (rising edge-triggered flip-flop clocked by clk2) Path Group: clk2 Path Type: max Delay Time Description --------------------------------------------------------- 10.00 10.00 clock clk (rise edge) 0.00 10.00 clock network delay (ideal) 0.00 10.00 ^ reg1/CK (DFF_X1) 0.08 10.08 v reg1/Q (DFF_X1) 0.00 10.08 v reg2/D (DFF_X1) 10.08 data arrival time 15.00 15.00 clock clk2 (rise edge) 0.00 15.00 clock network delay (ideal) -0.50 14.50 inter-clock uncertainty 0.00 14.50 clock reconvergence pessimism 14.50 ^ reg2/CK (DFF_X1) -0.04 14.46 library setup time 14.46 data required time --------------------------------------------------------- 14.46 data required time -10.08 data arrival time --------------------------------------------------------- 4.38 slack (MET) Startpoint: reg1 (rising edge-triggered flip-flop clocked by clk) Endpoint: out1 (output port clocked by clk) Path Group: clk Path Type: max Delay Time Description --------------------------------------------------------- 0.00 0.00 clock clk (rise edge) 0.00 0.00 clock network delay (ideal) 0.00 0.00 ^ reg1/CK (DFF_X1) 0.09 0.09 ^ reg1/Q (DFF_X1) 0.02 0.10 ^ buf2/Z (BUF_X1) 0.00 0.10 ^ out1 (out) 0.10 data arrival time 10.00 10.00 clock clk (rise edge) 0.00 10.00 clock network delay (ideal) 0.00 10.00 clock reconvergence pessimism -2.00 8.00 output external delay 8.00 data required time --------------------------------------------------------- 8.00 data required time -0.10 data arrival time --------------------------------------------------------- 7.90 slack (MET) Startpoint: reg1 (rising edge-triggered flip-flop clocked by clk) Endpoint: reg2 (rising edge-triggered flip-flop clocked by clk2) Path Group: clk2 Path Type: max Delay Time Description --------------------------------------------------------- 10.00 10.00 clock clk (rise edge) 0.00 10.00 clock network delay (ideal) 0.00 10.00 ^ reg1/CK (DFF_X1) 0.08 10.08 v reg1/Q (DFF_X1) 0.00 10.08 v reg2/D (DFF_X1) 10.08 data arrival time 15.00 15.00 clock clk2 (rise edge) 0.00 15.00 clock network delay (ideal) -0.50 14.50 inter-clock uncertainty 0.00 14.50 clock reconvergence pessimism 14.50 ^ reg2/CK (DFF_X1) -0.04 14.46 library setup time 14.46 data required time --------------------------------------------------------- 14.46 data required time -10.08 data arrival time --------------------------------------------------------- 4.38 slack (MET) Startpoint: reg1 (rising edge-triggered flip-flop clocked by clk) Endpoint: out1 (output port clocked by clk) Path Group: clk Path Type: max Delay Time Description --------------------------------------------------------- 0.00 0.00 clock clk (rise edge) 0.00 0.00 clock network delay (ideal) 0.00 0.00 ^ reg1/CK (DFF_X1) 0.09 0.09 ^ reg1/Q (DFF_X1) 0.02 0.10 ^ buf2/Z (BUF_X1) 0.00 0.10 ^ out1 (out) 0.10 data arrival time 10.00 10.00 clock clk (rise edge) 0.00 10.00 clock network delay (ideal) 0.00 10.00 clock reconvergence pessimism -2.00 8.00 output external delay 8.00 data required time --------------------------------------------------------- 8.00 data required time -0.10 data arrival time --------------------------------------------------------- 7.90 slack (MET) Startpoint: reg2 (rising edge-triggered flip-flop clocked by clk2) Endpoint: out2 (output port clocked by clk2) Path Group: clk2 Path Type: max Delay Time Description --------------------------------------------------------- 0.00 0.00 clock clk2 (rise edge) 0.00 0.00 clock network delay (ideal) 0.00 0.00 ^ reg2/CK (DFF_X1) 0.08 0.08 ^ reg2/Q (DFF_X1) 0.02 0.10 ^ buf3/Z (BUF_X1) 0.00 0.10 ^ out2 (out) 0.10 data arrival time 15.00 15.00 clock clk2 (rise edge) 0.00 15.00 clock network delay (ideal) 0.00 15.00 clock reconvergence pessimism -3.00 12.00 output external delay 12.00 data required time --------------------------------------------------------- 12.00 data required time -0.10 data arrival time --------------------------------------------------------- 11.90 slack (MET) --- disable timing on port --- Startpoint: reg1 (rising edge-triggered flip-flop clocked by clk) Endpoint: out1 (output port clocked by clk) Path Group: clk Path Type: max Delay Time Description --------------------------------------------------------- 0.00 0.00 clock clk (rise edge) 0.00 0.00 clock network delay (ideal) 0.00 0.00 ^ reg1/CK (DFF_X1) 0.09 0.09 ^ reg1/Q (DFF_X1) 0.02 0.10 ^ buf2/Z (BUF_X1) 0.00 0.10 ^ out1 (out) 0.10 data arrival time 10.00 10.00 clock clk (rise edge) 0.00 10.00 clock network delay (ideal) 0.00 10.00 clock reconvergence pessimism -2.00 8.00 output external delay 8.00 data required time --------------------------------------------------------- 8.00 data required time -0.10 data arrival time --------------------------------------------------------- 7.90 slack (MET) Startpoint: reg2 (rising edge-triggered flip-flop clocked by clk2) Endpoint: out2 (output port clocked by clk2) Path Group: clk2 Path Type: max Delay Time Description --------------------------------------------------------- 0.00 0.00 clock clk2 (rise edge) 0.00 0.00 clock network delay (ideal) 0.00 0.00 ^ reg2/CK (DFF_X1) 0.08 0.08 ^ reg2/Q (DFF_X1) 0.02 0.10 ^ buf3/Z (BUF_X1) 0.00 0.10 ^ out2 (out) 0.10 data arrival time 15.00 15.00 clock clk2 (rise edge) 0.00 15.00 clock network delay (ideal) 0.00 15.00 clock reconvergence pessimism -3.00 12.00 output external delay 12.00 data required time --------------------------------------------------------- 12.00 data required time -0.10 data arrival time --------------------------------------------------------- 11.90 slack (MET) --- enable timing on port --- Startpoint: reg1 (rising edge-triggered flip-flop clocked by clk) Endpoint: out1 (output port clocked by clk) Path Group: clk Path Type: max Delay Time Description --------------------------------------------------------- 0.00 0.00 clock clk (rise edge) 0.00 0.00 clock network delay (ideal) 0.00 0.00 ^ reg1/CK (DFF_X1) 0.09 0.09 ^ reg1/Q (DFF_X1) 0.02 0.10 ^ buf2/Z (BUF_X1) 0.00 0.10 ^ out1 (out) 0.10 data arrival time 10.00 10.00 clock clk (rise edge) 0.00 10.00 clock network delay (ideal) 0.00 10.00 clock reconvergence pessimism -2.00 8.00 output external delay 8.00 data required time --------------------------------------------------------- 8.00 data required time -0.10 data arrival time --------------------------------------------------------- 7.90 slack (MET) Startpoint: reg2 (rising edge-triggered flip-flop clocked by clk2) Endpoint: out2 (output port clocked by clk2) Path Group: clk2 Path Type: max Delay Time Description --------------------------------------------------------- 0.00 0.00 clock clk2 (rise edge) 0.00 0.00 clock network delay (ideal) 0.00 0.00 ^ reg2/CK (DFF_X1) 0.08 0.08 ^ reg2/Q (DFF_X1) 0.02 0.10 ^ buf3/Z (BUF_X1) 0.00 0.10 ^ out2 (out) 0.10 data arrival time 15.00 15.00 clock clk2 (rise edge) 0.00 15.00 clock network delay (ideal) 0.00 15.00 clock reconvergence pessimism -3.00 12.00 output external delay 12.00 data required time --------------------------------------------------------- 12.00 data required time -0.10 data arrival time --------------------------------------------------------- 11.90 slack (MET) --- set_case_analysis 0 --- Startpoint: reg1 (rising edge-triggered flip-flop clocked by clk) Endpoint: out1 (output port clocked by clk) Path Group: clk Path Type: max Delay Time Description --------------------------------------------------------- 0.00 0.00 clock clk (rise edge) 0.00 0.00 clock network delay (ideal) 0.00 0.00 ^ reg1/CK (DFF_X1) 0.09 0.09 ^ reg1/Q (DFF_X1) 0.02 0.10 ^ buf2/Z (BUF_X1) 0.00 0.10 ^ out1 (out) 0.10 data arrival time 10.00 10.00 clock clk (rise edge) 0.00 10.00 clock network delay (ideal) 0.00 10.00 clock reconvergence pessimism -2.00 8.00 output external delay 8.00 data required time --------------------------------------------------------- 8.00 data required time -0.10 data arrival time --------------------------------------------------------- 7.90 slack (MET) Startpoint: reg2 (rising edge-triggered flip-flop clocked by clk2) Endpoint: out2 (output port clocked by clk2) Path Group: clk2 Path Type: max Delay Time Description --------------------------------------------------------- 0.00 0.00 clock clk2 (rise edge) 0.00 0.00 clock network delay (ideal) 0.00 0.00 ^ reg2/CK (DFF_X1) 0.08 0.08 ^ reg2/Q (DFF_X1) 0.02 0.10 ^ buf3/Z (BUF_X1) 0.00 0.10 ^ out2 (out) 0.10 data arrival time 15.00 15.00 clock clk2 (rise edge) 0.00 15.00 clock network delay (ideal) 0.00 15.00 clock reconvergence pessimism -3.00 12.00 output external delay 12.00 data required time --------------------------------------------------------- 12.00 data required time -0.10 data arrival time --------------------------------------------------------- 11.90 slack (MET) --- remove case_analysis 0 --- Startpoint: reg1 (rising edge-triggered flip-flop clocked by clk) Endpoint: out1 (output port clocked by clk) Path Group: clk Path Type: max Delay Time Description --------------------------------------------------------- 0.00 0.00 clock clk (rise edge) 0.00 0.00 clock network delay (ideal) 0.00 0.00 ^ reg1/CK (DFF_X1) 0.09 0.09 ^ reg1/Q (DFF_X1) 0.02 0.10 ^ buf2/Z (BUF_X1) 0.00 0.10 ^ out1 (out) 0.10 data arrival time 10.00 10.00 clock clk (rise edge) 0.00 10.00 clock network delay (ideal) 0.00 10.00 clock reconvergence pessimism -2.00 8.00 output external delay 8.00 data required time --------------------------------------------------------- 8.00 data required time -0.10 data arrival time --------------------------------------------------------- 7.90 slack (MET) Startpoint: reg2 (rising edge-triggered flip-flop clocked by clk2) Endpoint: out2 (output port clocked by clk2) Path Group: clk2 Path Type: max Delay Time Description --------------------------------------------------------- 0.00 0.00 clock clk2 (rise edge) 0.00 0.00 clock network delay (ideal) 0.00 0.00 ^ reg2/CK (DFF_X1) 0.08 0.08 ^ reg2/Q (DFF_X1) 0.02 0.10 ^ buf3/Z (BUF_X1) 0.00 0.10 ^ out2 (out) 0.10 data arrival time 15.00 15.00 clock clk2 (rise edge) 0.00 15.00 clock network delay (ideal) 0.00 15.00 clock reconvergence pessimism -3.00 12.00 output external delay 12.00 data required time --------------------------------------------------------- 12.00 data required time -0.10 data arrival time --------------------------------------------------------- 11.90 slack (MET) --- add constraints and re-analyze --- Startpoint: reg1 (rising edge-triggered flip-flop clocked by clk) Endpoint: out1 (output port clocked by clk) Path Group: clk Path Type: max Delay Time Description --------------------------------------------------------- 0.00 0.00 clock clk (rise edge) 0.30 0.30 clock network delay (ideal) 0.00 0.30 ^ reg1/CK (DFF_X1) 0.11 0.41 ^ reg1/Q (DFF_X1) 0.02 0.42 ^ buf2/Z (BUF_X1) 0.00 0.42 ^ out1 (out) 0.42 data arrival time 10.00 10.00 clock clk (rise edge) 0.30 10.30 clock network delay (ideal) 0.00 10.30 clock reconvergence pessimism -2.00 8.30 output external delay 8.30 data required time --------------------------------------------------------- 8.30 data required time -0.42 data arrival time --------------------------------------------------------- 7.88 slack (MET) Startpoint: reg2 (rising edge-triggered flip-flop clocked by clk2) Endpoint: out2 (output port clocked by clk2) Path Group: clk2 Path Type: max Delay Time Description --------------------------------------------------------- 0.00 0.00 clock clk2 (rise edge) 0.50 0.50 clock network delay (ideal) 0.00 0.50 ^ reg2/CK (DFF_X1) 0.08 0.58 ^ reg2/Q (DFF_X1) 0.02 0.60 ^ buf3/Z (BUF_X1) 0.00 0.60 ^ out2 (out) 0.60 data arrival time 15.00 15.00 clock clk2 (rise edge) 0.50 15.50 clock network delay (ideal) 0.00 15.50 clock reconvergence pessimism -3.00 12.50 output external delay 12.50 data required time --------------------------------------------------------- 12.50 data required time -0.60 data arrival time --------------------------------------------------------- 11.90 slack (MET) Startpoint: in_unconst (input port clocked by clk) Endpoint: reg3 (rising edge-triggered flip-flop clocked by clk) Path Group: clk Path Type: min Delay Time Description --------------------------------------------------------- 0.00 0.00 clock clk (rise edge) 0.30 0.30 clock network delay (ideal) 0.50 0.80 ^ input external delay 0.00 0.80 ^ in_unconst (in) 0.02 0.82 ^ buf4/Z (BUF_X1) 0.00 0.82 ^ reg3/D (DFF_X1) 0.82 data arrival time 0.00 0.00 clock clk (rise edge) 0.30 0.30 clock network delay (ideal) 0.00 0.30 clock reconvergence pessimism 0.30 ^ reg3/CK (DFF_X1) 0.02 0.32 library hold time 0.32 data required time --------------------------------------------------------- 0.32 data required time -0.82 data arrival time --------------------------------------------------------- 0.50 slack (MET) Startpoint: reg1 (rising edge-triggered flip-flop clocked by clk) Endpoint: reg2 (rising edge-triggered flip-flop clocked by clk2) Path Group: clk2 Path Type: min Delay Time Description --------------------------------------------------------- 0.00 0.00 clock clk (rise edge) 0.30 0.30 clock network delay (ideal) 0.00 0.30 ^ reg1/CK (DFF_X1) 0.10 0.40 v reg1/Q (DFF_X1) 0.00 0.40 v reg2/D (DFF_X1) 0.40 data arrival time 15.00 15.00 clock clk2 (rise edge) 0.50 15.50 clock network delay (ideal) 0.20 15.70 inter-clock uncertainty 0.00 15.70 clock reconvergence pessimism 15.70 ^ reg2/CK (DFF_X1) 0.00 15.70 library hold time 15.70 data required time --------------------------------------------------------- 15.70 data required time -0.40 data arrival time --------------------------------------------------------- -15.30 slack (VIOLATED)