Startpoint: in1 (input port clocked by clk) Endpoint: reg1 (rising edge-triggered flip-flop clocked by clk) Path Group: clk Path Type: max Delay Time Description --------------------------------------------------------- 0.00 0.00 clock clk (rise edge) 0.00 0.00 clock network delay (ideal) 0.00 0.00 v input external delay 0.00 0.00 v in1 (in) 0.06 0.06 v buf1/Z (BUF_X1) 0.03 0.08 v and1/ZN (AND2_X1) 0.00 0.08 v reg1/D (DFF_X1) 0.08 data arrival time 10.00 10.00 clock clk (rise edge) 0.00 10.00 clock network delay (ideal) 0.00 10.00 clock reconvergence pessimism 10.00 ^ reg1/CK (DFF_X1) -0.04 9.96 library setup time 9.96 data required time --------------------------------------------------------- 9.96 data required time -0.08 data arrival time --------------------------------------------------------- 9.88 slack (MET) --- connected pin queries --- Net n1 Pin capacitance: 0.87-0.92 Wire capacitance: 0.00 Total capacitance: 0.87-0.92 Number of drivers: 1 Number of loads: 1 Number of pins: 2 Driver pins buf1/Z output (BUF_X1) Load pins and1/A1 input (AND2_X1) 0.87-0.92 Net n2 Pin capacitance: 1.06-1.14 Wire capacitance: 0.00 Total capacitance: 1.06-1.14 Number of drivers: 1 Number of loads: 1 Number of pins: 2 Driver pins and1/ZN output (AND2_X1) Load pins reg1/D input (DFF_X1) 1.06-1.14 net n1 pins: 2 net n2 pins: 2 --- instance/connection lifecycle --- created 9 instances created 6 nets connect lifecycle_inst_0/A: 1 connect lifecycle_inst_0/Z: 1 connect lifecycle_inst_3/A: 1 connect lifecycle_inst_3/ZN: 1 Net lifecycle_net_1 Pin capacitance: 1.55-1.70 Wire capacitance: 0.00 Total capacitance: 1.55-1.70 Number of drivers: 1 Number of loads: 1 Number of pins: 2 Driver pins lifecycle_inst_0/Z output (BUF_X1) Load pins lifecycle_inst_3/A input (INV_X1) 1.55-1.70 report_net lifecycle_net_1: done replace BUF_X1->BUF_X2: ref=BUF_X2 replace back BUF_X2->BUF_X1: ref=BUF_X1 replace BUF_X1->BUF_X4: ref=BUF_X4 Startpoint: in1 (input port clocked by clk) Endpoint: reg1 (rising edge-triggered flip-flop clocked by clk) Path Group: clk Path Type: max Delay Time Description --------------------------------------------------------- 0.00 0.00 clock clk (rise edge) 0.00 0.00 clock network delay (ideal) 0.00 0.00 v input external delay 0.00 0.00 v in1 (in) 0.06 0.06 v buf1/Z (BUF_X1) 0.03 0.08 v and1/ZN (AND2_X1) 0.00 0.08 v reg1/D (DFF_X1) 0.08 data arrival time 10.00 10.00 clock clk (rise edge) 0.00 10.00 clock network delay (ideal) 0.00 10.00 clock reconvergence pessimism 10.00 ^ reg1/CK (DFF_X1) -0.04 9.96 library setup time 9.96 data required time --------------------------------------------------------- 9.96 data required time -0.08 data arrival time --------------------------------------------------------- 9.88 slack (MET) --- disconnect and delete --- final cells: 3 Startpoint: in1 (input port clocked by clk) Endpoint: reg1 (rising edge-triggered flip-flop clocked by clk) Path Group: clk Path Type: max Delay Time Description --------------------------------------------------------- 0.00 0.00 clock clk (rise edge) 0.00 0.00 clock network delay (ideal) 0.00 0.00 v input external delay 0.00 0.00 v in1 (in) 0.06 0.06 v buf1/Z (BUF_X1) 0.03 0.08 v and1/ZN (AND2_X1) 0.00 0.08 v reg1/D (DFF_X1) 0.08 data arrival time 10.00 10.00 clock clk (rise edge) 0.00 10.00 clock network delay (ideal) 0.00 10.00 clock reconvergence pessimism 10.00 ^ reg1/CK (DFF_X1) -0.04 9.96 library setup time 9.96 data required time --------------------------------------------------------- 9.96 data required time -0.08 data arrival time --------------------------------------------------------- 9.88 slack (MET) --- property queries --- clk: dir=input full_name=clk in1: dir=input full_name=in1 in2: dir=input full_name=in2 out1: dir=output full_name=out1 buf1: ref=BUF_X1 full_name=buf1 and1: ref=AND2_X1 full_name=and1 reg1: ref=DFF_X1 full_name=reg1 buf1/A: dir=input buf1/Z: dir=output and1/A1: dir=input and1/A2: dir=input and1/ZN: dir=output reg1/D: dir=input reg1/CK: dir=input reg1/Q: dir=output --- replace_cell original instances --- and1 -> AND2_X2: AND2_X2 Startpoint: in1 (input port clocked by clk) Endpoint: reg1 (rising edge-triggered flip-flop clocked by clk) Path Group: clk Path Type: max Delay Time Description --------------------------------------------------------- 0.00 0.00 clock clk (rise edge) 0.00 0.00 clock network delay (ideal) 0.00 0.00 v input external delay 0.00 0.00 v in1 (in) 0.06 0.06 v buf1/Z (BUF_X1) 0.02 0.08 v and1/ZN (AND2_X2) 0.00 0.08 v reg1/D (DFF_X1) 0.08 data arrival time 10.00 10.00 clock clk (rise edge) 0.00 10.00 clock network delay (ideal) 0.00 10.00 clock reconvergence pessimism 10.00 ^ reg1/CK (DFF_X1) -0.04 9.96 library setup time 9.96 data required time --------------------------------------------------------- 9.96 data required time -0.08 data arrival time --------------------------------------------------------- 9.88 slack (MET) Startpoint: in1 (input port clocked by clk) Endpoint: reg1 (rising edge-triggered flip-flop clocked by clk) Path Group: clk Path Type: max Delay Time Description --------------------------------------------------------- 0.00 0.00 clock clk (rise edge) 0.00 0.00 clock network delay (ideal) 0.00 0.00 v input external delay 0.00 0.00 v in1 (in) 0.06 0.06 v buf1/Z (BUF_X1) 0.03 0.08 v and1/ZN (AND2_X1) 0.00 0.08 v reg1/D (DFF_X1) 0.08 data arrival time 10.00 10.00 clock clk (rise edge) 0.00 10.00 clock network delay (ideal) 0.00 10.00 clock reconvergence pessimism 10.00 ^ reg1/CK (DFF_X1) -0.04 9.96 library setup time 9.96 data required time --------------------------------------------------------- 9.96 data required time -0.08 data arrival time --------------------------------------------------------- 9.88 slack (MET) buf1 -> BUF_X2: BUF_X2 buf1 -> BUF_X4: BUF_X4 buf1 -> BUF_X8: BUF_X8 buf1 -> BUF_X16: BUF_X16 buf1 -> BUF_X32: BUF_X32 Startpoint: in1 (input port clocked by clk) Endpoint: reg1 (rising edge-triggered flip-flop clocked by clk) Path Group: clk Path Type: max Delay Time Description --------------------------------------------------------- 0.00 0.00 clock clk (rise edge) 0.00 0.00 clock network delay (ideal) 0.00 0.00 v input external delay 0.00 0.00 v in1 (in) 0.06 0.06 v buf1/Z (BUF_X1) 0.03 0.08 v and1/ZN (AND2_X1) 0.00 0.08 v reg1/D (DFF_X1) 0.08 data arrival time 10.00 10.00 clock clk (rise edge) 0.00 10.00 clock network delay (ideal) 0.00 10.00 clock reconvergence pessimism 10.00 ^ reg1/CK (DFF_X1) -0.04 9.96 library setup time 9.96 data required time --------------------------------------------------------- 9.96 data required time -0.08 data arrival time --------------------------------------------------------- 9.88 slack (MET)