Startpoint: reg1 (rising edge-triggered flip-flop clocked by clk)
Endpoint: out1 (output port clocked by clk)
Path Group: clk
Path Type: max

  Delay    Time   Description
---------------------------------------------------------
   0.00    0.00   clock clk (rise edge)
   0.00    0.00   clock network delay (ideal)
   0.00    0.00 ^ reg1/CK (DFF_X1)
   0.08    0.08 ^ reg1/Q (DFF_X1)
   0.02    0.10 ^ buf2/Z (BUF_X1)
   0.00    0.10 ^ out1 (out)
           0.10   data arrival time

  10.00   10.00   clock clk (rise edge)
   0.00   10.00   clock network delay (ideal)
   0.00   10.00   clock reconvergence pessimism
  -2.00    8.00   output external delay
           8.00   data required time
---------------------------------------------------------
           8.00   data required time
          -0.10   data arrival time
---------------------------------------------------------
           7.90   slack (MET)


Startpoint: in1 (input port clocked by clk)
Endpoint: reg1 (rising edge-triggered flip-flop clocked by clk)
Path Group: clk
Path Type: min

  Delay    Time   Description
---------------------------------------------------------
   0.00    0.00   clock clk (rise edge)
   0.00    0.00   clock network delay (ideal)
   1.00    1.00 ^ input external delay
   0.00    1.00 ^ in1 (in)
   0.02    1.02 ^ and1/ZN (AND2_X1)
   0.02    1.04 ^ buf1/Z (BUF_X1)
   0.00    1.04 ^ reg1/D (DFF_X1)
           1.04   data arrival time

   0.00    0.00   clock clk (rise edge)
   0.00    0.00   clock network delay (ideal)
   0.00    0.00   clock reconvergence pessimism
           0.00 ^ reg1/CK (DFF_X1)
   0.00    0.00   library hold time
           0.00   data required time
---------------------------------------------------------
           0.00   data required time
          -1.04   data arrival time
---------------------------------------------------------
           1.04   slack (MET)


Worst slack: 7.899713772019368e-9