--- Test 1: net driver/load queries --- net n1 found n1 driver pins: 1 n1 load pins: 1 net n6 found n6 total pins: 4 Net n1 Pin capacitance: 1.55-1.70 Wire capacitance: 0.00 Total capacitance: 1.55-1.70 Number of drivers: 1 Number of loads: 1 Number of pins: 2 Driver pins buf1/Z output (BUF_X1) Load pins inv1/A input (INV_X1) 1.55-1.70 Net n6 Pin capacitance: 3.82-4.29 Wire capacitance: 0.00 Total capacitance: 3.82-4.29 Number of drivers: 1 Number of loads: 3 Number of pins: 4 Driver pins or1/ZN output (OR2_X1) Load pins buf_out/A input (BUF_X1) 0.88-0.97 nand1/A1 input (NAND2_X1) 1.53-1.60 nor1/A1 input (NOR2_X1) 1.41-1.71 Net n1 Pin capacitance: 1.55-1.70 Wire capacitance: 0.00 Total capacitance: 1.55-1.70 Number of drivers: 1 Number of loads: 1 Number of pins: 2 Driver pins buf1/Z output (BUF_X1) Load pins inv1/A input (INV_X1) 1.55-1.70 report_net n1: done Net n2 Pin capacitance: 1.59-1.78 Wire capacitance: 0.00 Total capacitance: 1.59-1.78 Number of drivers: 1 Number of loads: 1 Number of pins: 2 Driver pins inv1/ZN output (INV_X1) Load pins buf2/A input (BUF_X2) 1.59-1.78 report_net n2: done Net n3 Pin capacitance: 0.79-0.95 Wire capacitance: 0.00 Total capacitance: 0.79-0.95 Number of drivers: 1 Number of loads: 1 Number of pins: 2 Driver pins buf2/Z output (BUF_X2) Load pins or1/A1 input (OR2_X1) 0.79-0.95 report_net n3: done Net n4 Pin capacitance: 0.87-0.92 Wire capacitance: 0.00 Total capacitance: 0.87-0.92 Number of drivers: 1 Number of loads: 1 Number of pins: 2 Driver pins buf3/Z output (BUF_X4) Load pins and1/A1 input (AND2_X1) 0.87-0.92 report_net n4: done Net n5 Pin capacitance: 0.90-0.94 Wire capacitance: 0.00 Total capacitance: 0.90-0.94 Number of drivers: 1 Number of loads: 1 Number of pins: 2 Driver pins and1/ZN output (AND2_X1) Load pins or1/A2 input (OR2_X1) 0.90-0.94 report_net n5: done Net n6 Pin capacitance: 3.82-4.29 Wire capacitance: 0.00 Total capacitance: 3.82-4.29 Number of drivers: 1 Number of loads: 3 Number of pins: 4 Driver pins or1/ZN output (OR2_X1) Load pins buf_out/A input (BUF_X1) 0.88-0.97 nand1/A1 input (NAND2_X1) 1.53-1.60 nor1/A1 input (NOR2_X1) 1.41-1.71 report_net n6: done Net n7 Pin capacitance: 1.06-1.14 Wire capacitance: 0.00 Total capacitance: 1.06-1.14 Number of drivers: 1 Number of loads: 1 Number of pins: 2 Driver pins nand1/ZN output (NAND2_X1) Load pins reg1/D input (DFF_X1) 1.06-1.14 report_net n7: done Net n8 Pin capacitance: 1.06-1.14 Wire capacitance: 0.00 Total capacitance: 1.06-1.14 Number of drivers: 1 Number of loads: 1 Number of pins: 2 Driver pins nor1/ZN output (NOR2_X1) Load pins reg2/D input (DFF_X1) 1.06-1.14 report_net n8: done --- Test 2: net capacitance queries --- n1: total_cap=1.700229965024007e-15 pin_cap=1.700229965024007e-15 wire_cap=0.0 n2: total_cap=1.7792090110918925e-15 pin_cap=1.7792090110918925e-15 wire_cap=0.0 n3: total_cap=9.46813957836449e-16 pin_cap=9.46813957836449e-16 wire_cap=0.0 n4: total_cap=9.181449630663247e-16 pin_cap=9.181449630663247e-16 wire_cap=0.0 n5: total_cap=9.419389655876452e-16 pin_cap=9.419389655876452e-16 wire_cap=0.0 n6: total_cap=4.288162317231782e-15 pin_cap=4.288162317231782e-15 wire_cap=0.0 n7: total_cap=1.140290047274724e-15 pin_cap=1.140290047274724e-15 wire_cap=0.0 n8: total_cap=1.140290047274724e-15 pin_cap=1.140290047274724e-15 wire_cap=0.0 --- Test 3: pin property queries --- in1: driver=1 load=0 leaf=0 top=1 in2: driver=1 load=0 leaf=0 top=1 out1: driver=0 load=1 leaf=0 top=1 out2: driver=0 load=1 leaf=0 top=1 out3: driver=0 load=1 leaf=0 top=1 clk: driver=1 load=0 leaf=0 top=1 buf1/A: driver=0 load=1 leaf=1 top=0 port=A buf1/Z: driver=1 load=0 leaf=1 top=0 port=Z inv1/A: driver=0 load=1 leaf=1 top=0 port=A inv1/ZN: driver=1 load=0 leaf=1 top=0 port=ZN and1/A1: driver=0 load=1 leaf=1 top=0 port=A1 and1/ZN: driver=1 load=0 leaf=1 top=0 port=ZN or1/A1: driver=0 load=1 leaf=1 top=0 port=A1 or1/ZN: driver=1 load=0 leaf=1 top=0 port=ZN reg1/D: driver=0 load=1 leaf=1 top=0 port=D reg1/CK: driver=0 load=1 leaf=1 top=0 port=CK reg1/Q: driver=1 load=0 leaf=1 top=0 port=Q --- Test 4: connected pin queries --- buf1/Z connected pins: 2 inv1/A connected pins: 2 or1/ZN connected pins: 4 --- Test 5: instance iterators --- top child count: 11 reg1 pin count: 8 top net count: 17 --- Test 6: network counts --- instance count: 12 pin count: 65 net count: 17 leaf instance count: 11 leaf pin count: 56 --- Test 7: leaf instance iterator --- leaf instance count via iterator: 11 leaf instances list: 11 --- Test 8: library queries --- library: NangateOpenCellLibrary library: verilog total libraries: 2 BUF* cells in library: 6 all cells in library: 134 --- Test 9: timing reports --- Startpoint: in2 (input port clocked by clk) Endpoint: reg2 (rising edge-triggered flip-flop clocked by clk) Path Group: clk Path Type: max Delay Time Description --------------------------------------------------------- 0.00 0.00 clock clk (rise edge) 0.00 0.00 clock network delay (ideal) 0.00 0.00 v input external delay 0.00 0.00 v in2 (in) 0.05 0.05 v buf3/Z (BUF_X4) 0.03 0.08 v and1/ZN (AND2_X1) 0.05 0.13 v or1/ZN (OR2_X1) 0.02 0.15 ^ nor1/ZN (NOR2_X1) 0.00 0.15 ^ reg2/D (DFF_X1) 0.15 data arrival time 10.00 10.00 clock clk (rise edge) 0.00 10.00 clock network delay (ideal) 0.00 10.00 clock reconvergence pessimism 10.00 ^ reg2/CK (DFF_X1) -0.04 9.96 library setup time 9.96 data required time --------------------------------------------------------- 9.96 data required time -0.15 data arrival time --------------------------------------------------------- 9.81 slack (MET) Startpoint: in4 (input port clocked by clk) Endpoint: reg2 (rising edge-triggered flip-flop clocked by clk) Path Group: clk Path Type: min Delay Time Description --------------------------------------------------------- 0.00 0.00 clock clk (rise edge) 0.00 0.00 clock network delay (ideal) 0.00 0.00 ^ input external delay 0.00 0.00 ^ in4 (in) 0.01 0.01 v nor1/ZN (NOR2_X1) 0.00 0.01 v reg2/D (DFF_X1) 0.01 data arrival time 0.00 0.00 clock clk (rise edge) 0.00 0.00 clock network delay (ideal) 0.00 0.00 clock reconvergence pessimism 0.00 ^ reg2/CK (DFF_X1) 0.00 0.00 library hold time 0.00 data required time --------------------------------------------------------- 0.00 data required time -0.01 data arrival time --------------------------------------------------------- 0.01 slack (MET) Warning: network_net_cap_query.tcl line 1, unknown field nets. Startpoint: in2 (input port clocked by clk) Endpoint: reg2 (rising edge-triggered flip-flop clocked by clk) Path Group: clk Path Type: max Fanout Cap Slew Delay Time Description ----------------------------------------------------------------------------- 0.00 0.00 0.00 clock clk (rise edge) 0.00 0.00 clock network delay (ideal) 0.00 0.00 v input external delay 1 3.00 0.10 0.00 0.00 v in2 (in) 0.10 0.00 0.00 v buf3/A (BUF_X4) 1 0.87 0.01 0.05 0.05 v buf3/Z (BUF_X4) 0.01 0.00 0.05 v and1/A1 (AND2_X1) 1 0.90 0.01 0.03 0.08 v and1/ZN (AND2_X1) 0.01 0.00 0.08 v or1/A2 (OR2_X1) 3 3.82 0.01 0.05 0.13 v or1/ZN (OR2_X1) 0.01 0.00 0.13 v nor1/A1 (NOR2_X1) 1 1.14 0.02 0.02 0.15 ^ nor1/ZN (NOR2_X1) 0.02 0.00 0.15 ^ reg2/D (DFF_X1) 0.15 data arrival time 0.00 10.00 10.00 clock clk (rise edge) 0.00 10.00 clock network delay (ideal) 0.00 10.00 clock reconvergence pessimism 10.00 ^ reg2/CK (DFF_X1) -0.04 9.96 library setup time 9.96 data required time ----------------------------------------------------------------------------- 9.96 data required time -0.15 data arrival time ----------------------------------------------------------------------------- 9.81 slack (MET) Group Slack -------------------------------------------- clk 0.01 clk 9.81 max slew Pin Limit Slew Slack ------------------------------------------------------------ nor1/ZN 0.20 0.02 0.18 (MET) max capacitance Pin Limit Cap Slack ------------------------------------------------------------ nor1/ZN 26.70 1.14 25.56 (MET)