--- baseline report_checks --- Startpoint: d1 (input port clocked by clk) Endpoint: reg2 (rising edge-triggered flip-flop clocked by clk) Path Group: clk Path Type: max Delay Time Description --------------------------------------------------------- 0.00 0.00 clock clk (rise edge) 0.00 0.00 clock network delay (ideal) 1.00 1.00 ^ input external delay 0.00 1.00 ^ d1 (in) 0.03 1.03 ^ buf1/Z (BUF_X1) 0.01 1.04 v inv1/ZN (INV_X1) 0.03 1.07 v and1/ZN (AND2_X1) 0.05 1.11 v or1/ZN (OR2_X1) 0.03 1.14 v buf3/Z (BUF_X1) 0.00 1.14 v reg2/D (DFF_X1) 1.14 data arrival time 10.00 10.00 clock clk (rise edge) 0.00 10.00 clock network delay (ideal) 0.00 10.00 clock reconvergence pessimism 10.00 ^ reg2/CK (DFF_X1) -0.04 9.96 library setup time 9.96 data required time --------------------------------------------------------- 9.96 data required time -1.14 data arrival time --------------------------------------------------------- 8.82 slack (MET) Startpoint: en (input port clocked by clk) Endpoint: reg1 (rising edge-triggered flip-flop clocked by clk) Path Group: clk Path Type: min Delay Time Description --------------------------------------------------------- 0.00 0.00 clock clk (rise edge) 0.00 0.00 clock network delay (ideal) 0.00 0.00 ^ input external delay 0.00 0.00 ^ en (in) 0.05 0.05 ^ and1/ZN (AND2_X1) 0.00 0.05 ^ reg1/D (DFF_X1) 0.05 data arrival time 0.00 0.00 clock clk (rise edge) 0.00 0.00 clock network delay (ideal) 0.00 0.00 clock reconvergence pessimism 0.00 ^ reg1/CK (DFF_X1) 0.01 0.01 library hold time 0.01 data required time --------------------------------------------------------- 0.01 data required time -0.05 data arrival time --------------------------------------------------------- 0.04 slack (MET) Startpoint: d1 (input port clocked by clk) Endpoint: reg2 (rising edge-triggered flip-flop clocked by clk) Path Group: clk Path Type: max Delay Time Description --------------------------------------------------------- 0.00 0.00 clock clk (rise edge) 0.00 0.00 clock network delay (ideal) 1.00 1.00 ^ input external delay 0.00 1.00 ^ d1 (in) 0.03 1.03 ^ buf1/Z (BUF_X1) 0.01 1.04 v inv1/ZN (INV_X1) 0.03 1.07 v and1/ZN (AND2_X1) 0.05 1.11 v or1/ZN (OR2_X1) 0.03 1.14 v buf3/Z (BUF_X1) 0.00 1.14 v reg2/D (DFF_X1) 1.14 data arrival time 10.00 10.00 clock clk (rise edge) 0.00 10.00 clock network delay (ideal) 0.00 10.00 clock reconvergence pessimism 10.00 ^ reg2/CK (DFF_X1) -0.04 9.96 library setup time 9.96 data required time --------------------------------------------------------- 9.96 data required time -1.14 data arrival time --------------------------------------------------------- 8.82 slack (MET) --- multiple paths --- No paths found. No paths found. No paths found. No paths found. No paths found. --- through paths --- Startpoint: d1 (input port clocked by clk) Endpoint: reg2 (rising edge-triggered flip-flop clocked by clk) Path Group: clk Path Type: max Delay Time Description --------------------------------------------------------- 0.00 0.00 clock clk (rise edge) 0.00 0.00 clock network delay (ideal) 1.00 1.00 ^ input external delay 0.00 1.00 ^ d1 (in) 0.03 1.03 ^ buf1/Z (BUF_X1) 0.01 1.04 v inv1/ZN (INV_X1) 0.03 1.07 v and1/ZN (AND2_X1) 0.05 1.11 v or1/ZN (OR2_X1) 0.03 1.14 v buf3/Z (BUF_X1) 0.00 1.14 v reg2/D (DFF_X1) 1.14 data arrival time 10.00 10.00 clock clk (rise edge) 0.00 10.00 clock network delay (ideal) 0.00 10.00 clock reconvergence pessimism 10.00 ^ reg2/CK (DFF_X1) -0.04 9.96 library setup time 9.96 data required time --------------------------------------------------------- 9.96 data required time -1.14 data arrival time --------------------------------------------------------- 8.82 slack (MET) through inv1/ZN: done Startpoint: d1 (input port clocked by clk) Endpoint: reg2 (rising edge-triggered flip-flop clocked by clk) Path Group: clk Path Type: max Delay Time Description --------------------------------------------------------- 0.00 0.00 clock clk (rise edge) 0.00 0.00 clock network delay (ideal) 1.00 1.00 ^ input external delay 0.00 1.00 ^ d1 (in) 0.03 1.03 ^ buf1/Z (BUF_X1) 0.01 1.04 v inv1/ZN (INV_X1) 0.03 1.07 v and1/ZN (AND2_X1) 0.05 1.11 v or1/ZN (OR2_X1) 0.03 1.14 v buf3/Z (BUF_X1) 0.00 1.14 v reg2/D (DFF_X1) 1.14 data arrival time 10.00 10.00 clock clk (rise edge) 0.00 10.00 clock network delay (ideal) 0.00 10.00 clock reconvergence pessimism 10.00 ^ reg2/CK (DFF_X1) -0.04 9.96 library setup time 9.96 data required time --------------------------------------------------------- 9.96 data required time -1.14 data arrival time --------------------------------------------------------- 8.82 slack (MET) through and1/ZN: done Startpoint: d1 (input port clocked by clk) Endpoint: reg2 (rising edge-triggered flip-flop clocked by clk) Path Group: clk Path Type: max Delay Time Description --------------------------------------------------------- 0.00 0.00 clock clk (rise edge) 0.00 0.00 clock network delay (ideal) 1.00 1.00 ^ input external delay 0.00 1.00 ^ d1 (in) 0.03 1.03 ^ buf1/Z (BUF_X1) 0.01 1.04 v inv1/ZN (INV_X1) 0.03 1.07 v and1/ZN (AND2_X1) 0.05 1.11 v or1/ZN (OR2_X1) 0.03 1.14 v buf3/Z (BUF_X1) 0.00 1.14 v reg2/D (DFF_X1) 1.14 data arrival time 10.00 10.00 clock clk (rise edge) 0.00 10.00 clock network delay (ideal) 0.00 10.00 clock reconvergence pessimism 10.00 ^ reg2/CK (DFF_X1) -0.04 9.96 library setup time 9.96 data required time --------------------------------------------------------- 9.96 data required time -1.14 data arrival time --------------------------------------------------------- 8.82 slack (MET) through or1/ZN: done Startpoint: d1 (input port clocked by clk) Endpoint: reg2 (rising edge-triggered flip-flop clocked by clk) Path Group: clk Path Type: max Delay Time Description --------------------------------------------------------- 0.00 0.00 clock clk (rise edge) 0.00 0.00 clock network delay (ideal) 1.00 1.00 ^ input external delay 0.00 1.00 ^ d1 (in) 0.03 1.03 ^ buf1/Z (BUF_X1) 0.01 1.04 v inv1/ZN (INV_X1) 0.03 1.07 v and1/ZN (AND2_X1) 0.05 1.11 v or1/ZN (OR2_X1) 0.03 1.14 v buf3/Z (BUF_X1) 0.00 1.14 v reg2/D (DFF_X1) 1.14 data arrival time 10.00 10.00 clock clk (rise edge) 0.00 10.00 clock network delay (ideal) 0.00 10.00 clock reconvergence pessimism 10.00 ^ reg2/CK (DFF_X1) -0.04 9.96 library setup time 9.96 data required time --------------------------------------------------------- 9.96 data required time -1.14 data arrival time --------------------------------------------------------- 8.82 slack (MET) through buf3/Z: done --- timing edges for multi-input cells --- and1 edges: 1 or1 edges: 1 reg1 edges: 1 reg2 edges: 1 and1 A1->ZN edges: 1 and1 A2->ZN edges: 1 or1 A1->ZN edges: 1 --- report_edges --- A -> Z combinational ^ -> ^ 0.03:0.03 v -> v 0.06:0.06 A -> ZN combinational ^ -> v 0.01:0.01 v -> ^ 0.01:0.01 A1 -> ZN combinational ^ -> ^ 0.03:0.03 v -> v 0.03:0.03 A2 -> ZN combinational ^ -> ^ 0.05:0.05 v -> v 0.07:0.07 A1 -> ZN combinational ^ -> ^ 0.03:0.03 v -> v 0.03:0.03 d1 -> buf1/A wire ^ -> ^ 0.00:0.00 v -> v 0.00:0.00 reg2/Q -> q2 wire ^ -> ^ 0.00:0.00 v -> v 0.00:0.00 --- set_case_analysis --- Startpoint: d1 (input port clocked by clk) Endpoint: reg2 (rising edge-triggered flip-flop clocked by clk) Path Group: clk Path Type: max Delay Time Description --------------------------------------------------------- 0.00 0.00 clock clk (rise edge) 0.00 0.00 clock network delay (ideal) 1.00 1.00 ^ input external delay 0.00 1.00 ^ d1 (in) 0.03 1.03 ^ buf1/Z (BUF_X1) 0.01 1.04 v inv1/ZN (INV_X1) 0.03 1.07 v and1/ZN (AND2_X1) 0.05 1.11 v or1/ZN (OR2_X1) 0.03 1.14 v buf3/Z (BUF_X1) 0.00 1.14 v reg2/D (DFF_X1) 1.14 data arrival time 10.00 10.00 clock clk (rise edge) 0.00 10.00 clock network delay (ideal) 0.00 10.00 clock reconvergence pessimism 10.00 ^ reg2/CK (DFF_X1) -0.04 9.96 library setup time 9.96 data required time --------------------------------------------------------- 9.96 data required time -1.14 data arrival time --------------------------------------------------------- 8.82 slack (MET) No paths found. Startpoint: d2 (input port clocked by clk) Endpoint: reg2 (rising edge-triggered flip-flop clocked by clk) Path Group: clk Path Type: max Delay Time Description --------------------------------------------------------- 0.00 0.00 clock clk (rise edge) 0.00 0.00 clock network delay (ideal) 1.00 1.00 v input external delay 0.00 1.00 v d2 (in) 0.05 1.05 v buf2/Z (BUF_X2) 0.04 1.09 v or1/ZN (OR2_X1) 0.03 1.12 v buf3/Z (BUF_X1) 0.00 1.12 v reg2/D (DFF_X1) 1.12 data arrival time 10.00 10.00 clock clk (rise edge) 0.00 10.00 clock network delay (ideal) 0.00 10.00 clock reconvergence pessimism 10.00 ^ reg2/CK (DFF_X1) -0.04 9.96 library setup time 9.96 data required time --------------------------------------------------------- 9.96 data required time -1.12 data arrival time --------------------------------------------------------- 8.84 slack (MET) Startpoint: d1 (input port clocked by clk) Endpoint: reg2 (rising edge-triggered flip-flop clocked by clk) Path Group: clk Path Type: max Delay Time Description --------------------------------------------------------- 0.00 0.00 clock clk (rise edge) 0.00 0.00 clock network delay (ideal) 1.00 1.00 ^ input external delay 0.00 1.00 ^ d1 (in) 0.03 1.03 ^ buf1/Z (BUF_X1) 0.01 1.04 v inv1/ZN (INV_X1) 0.03 1.07 v and1/ZN (AND2_X1) 0.05 1.11 v or1/ZN (OR2_X1) 0.03 1.14 v buf3/Z (BUF_X1) 0.00 1.14 v reg2/D (DFF_X1) 1.14 data arrival time 10.00 10.00 clock clk (rise edge) 0.00 10.00 clock network delay (ideal) 0.00 10.00 clock reconvergence pessimism 10.00 ^ reg2/CK (DFF_X1) -0.04 9.96 library setup time 9.96 data required time --------------------------------------------------------- 9.96 data required time -1.14 data arrival time --------------------------------------------------------- 8.82 slack (MET) --- disable/enable timing multiple cells --- Startpoint: d2 (input port clocked by clk) Endpoint: reg2 (rising edge-triggered flip-flop clocked by clk) Path Group: clk Path Type: max Delay Time Description --------------------------------------------------------- 0.00 0.00 clock clk (rise edge) 0.00 0.00 clock network delay (ideal) 1.00 1.00 v input external delay 0.00 1.00 v d2 (in) 0.05 1.05 v buf2/Z (BUF_X2) 0.04 1.09 v or1/ZN (OR2_X1) 0.03 1.12 v buf3/Z (BUF_X1) 0.00 1.12 v reg2/D (DFF_X1) 1.12 data arrival time 10.00 10.00 clock clk (rise edge) 0.00 10.00 clock network delay (ideal) 0.00 10.00 clock reconvergence pessimism 10.00 ^ reg2/CK (DFF_X1) -0.04 9.96 library setup time 9.96 data required time --------------------------------------------------------- 9.96 data required time -1.12 data arrival time --------------------------------------------------------- 8.84 slack (MET) Startpoint: d2 (input port clocked by clk) Endpoint: reg2 (rising edge-triggered flip-flop clocked by clk) Path Group: clk Path Type: max Delay Time Description --------------------------------------------------------- 0.00 0.00 clock clk (rise edge) 0.00 0.00 clock network delay (ideal) 1.00 1.00 v input external delay 0.00 1.00 v d2 (in) 0.05 1.05 v buf2/Z (BUF_X2) 0.04 1.09 v or1/ZN (OR2_X1) 0.03 1.12 v buf3/Z (BUF_X1) 0.00 1.12 v reg2/D (DFF_X1) 1.12 data arrival time 10.00 10.00 clock clk (rise edge) 0.00 10.00 clock network delay (ideal) 0.00 10.00 clock reconvergence pessimism 10.00 ^ reg2/CK (DFF_X1) -0.04 9.96 library setup time 9.96 data required time --------------------------------------------------------- 9.96 data required time -1.12 data arrival time --------------------------------------------------------- 8.84 slack (MET) Startpoint: d2 (input port clocked by clk) Endpoint: reg2 (rising edge-triggered flip-flop clocked by clk) Path Group: clk Path Type: max Delay Time Description --------------------------------------------------------- 0.00 0.00 clock clk (rise edge) 0.00 0.00 clock network delay (ideal) 1.00 1.00 v input external delay 0.00 1.00 v d2 (in) 0.05 1.05 v buf2/Z (BUF_X2) 0.04 1.09 v or1/ZN (OR2_X1) 0.03 1.12 v buf3/Z (BUF_X1) 0.00 1.12 v reg2/D (DFF_X1) 1.12 data arrival time 10.00 10.00 clock clk (rise edge) 0.00 10.00 clock network delay (ideal) 0.00 10.00 clock reconvergence pessimism 10.00 ^ reg2/CK (DFF_X1) -0.04 9.96 library setup time 9.96 data required time --------------------------------------------------------- 9.96 data required time -1.12 data arrival time --------------------------------------------------------- 8.84 slack (MET) Startpoint: d1 (input port clocked by clk) Endpoint: reg2 (rising edge-triggered flip-flop clocked by clk) Path Group: clk Path Type: max Delay Time Description --------------------------------------------------------- 0.00 0.00 clock clk (rise edge) 0.00 0.00 clock network delay (ideal) 1.00 1.00 ^ input external delay 0.00 1.00 ^ d1 (in) 0.03 1.03 ^ buf1/Z (BUF_X1) 0.01 1.04 v inv1/ZN (INV_X1) 0.03 1.07 v and1/ZN (AND2_X1) 0.05 1.11 v or1/ZN (OR2_X1) 0.03 1.14 v buf3/Z (BUF_X1) 0.00 1.14 v reg2/D (DFF_X1) 1.14 data arrival time 10.00 10.00 clock clk (rise edge) 0.00 10.00 clock network delay (ideal) 0.00 10.00 clock reconvergence pessimism 10.00 ^ reg2/CK (DFF_X1) -0.04 9.96 library setup time 9.96 data required time --------------------------------------------------------- 9.96 data required time -1.14 data arrival time --------------------------------------------------------- 8.82 slack (MET) buf1 A Z constraint buf3 A Z constraint Startpoint: reg1 (rising edge-triggered flip-flop clocked by clk) Endpoint: q1 (output port clocked by clk) Path Group: clk Path Type: max Delay Time Description --------------------------------------------------------- 0.00 0.00 clock clk (rise edge) 0.00 0.00 clock network delay (ideal) 0.00 0.00 ^ reg1/CK (DFF_X1) 0.08 0.08 ^ reg1/Q (DFF_X1) 0.00 0.08 ^ q1 (out) 0.08 data arrival time 10.00 10.00 clock clk (rise edge) 0.00 10.00 clock network delay (ideal) 0.00 10.00 clock reconvergence pessimism -1.00 9.00 output external delay 9.00 data required time --------------------------------------------------------- 9.00 data required time -0.08 data arrival time --------------------------------------------------------- 8.92 slack (MET) Startpoint: d1 (input port clocked by clk) Endpoint: reg2 (rising edge-triggered flip-flop clocked by clk) Path Group: clk Path Type: max Delay Time Description --------------------------------------------------------- 0.00 0.00 clock clk (rise edge) 0.00 0.00 clock network delay (ideal) 1.00 1.00 ^ input external delay 0.00 1.00 ^ d1 (in) 0.03 1.03 ^ buf1/Z (BUF_X1) 0.01 1.04 v inv1/ZN (INV_X1) 0.03 1.07 v and1/ZN (AND2_X1) 0.05 1.11 v or1/ZN (OR2_X1) 0.03 1.14 v buf3/Z (BUF_X1) 0.00 1.14 v reg2/D (DFF_X1) 1.14 data arrival time 10.00 10.00 clock clk (rise edge) 0.00 10.00 clock network delay (ideal) 0.00 10.00 clock reconvergence pessimism 10.00 ^ reg2/CK (DFF_X1) -0.04 9.96 library setup time 9.96 data required time --------------------------------------------------------- 9.96 data required time -1.14 data arrival time --------------------------------------------------------- 8.82 slack (MET) --- report_check_types --- Startpoint: d1 (input port clocked by clk) Endpoint: reg2 (rising edge-triggered flip-flop clocked by clk) Path Group: clk Path Type: max Delay Time Description --------------------------------------------------------- 0.00 0.00 clock clk (rise edge) 0.00 0.00 clock network delay (ideal) 1.00 1.00 ^ input external delay 0.00 1.00 ^ d1 (in) 0.03 1.03 ^ buf1/Z (BUF_X1) 0.01 1.04 v inv1/ZN (INV_X1) 0.03 1.07 v and1/ZN (AND2_X1) 0.05 1.11 v or1/ZN (OR2_X1) 0.03 1.14 v buf3/Z (BUF_X1) 0.00 1.14 v reg2/D (DFF_X1) 1.14 data arrival time 10.00 10.00 clock clk (rise edge) 0.00 10.00 clock network delay (ideal) 0.00 10.00 clock reconvergence pessimism 10.00 ^ reg2/CK (DFF_X1) -0.04 9.96 library setup time 9.96 data required time --------------------------------------------------------- 9.96 data required time -1.14 data arrival time --------------------------------------------------------- 8.82 slack (MET) Startpoint: en (input port clocked by clk) Endpoint: reg1 (rising edge-triggered flip-flop clocked by clk) Path Group: clk Path Type: min Delay Time Description --------------------------------------------------------- 0.00 0.00 clock clk (rise edge) 0.00 0.00 clock network delay (ideal) 0.00 0.00 ^ input external delay 0.00 0.00 ^ en (in) 0.05 0.05 ^ and1/ZN (AND2_X1) 0.00 0.05 ^ reg1/D (DFF_X1) 0.05 data arrival time 0.00 0.00 clock clk (rise edge) 0.00 0.00 clock network delay (ideal) 0.00 0.00 clock reconvergence pessimism 0.00 ^ reg1/CK (DFF_X1) 0.01 0.01 library hold time 0.01 data required time --------------------------------------------------------- 0.01 data required time -0.05 data arrival time --------------------------------------------------------- 0.04 slack (MET) Startpoint: en (input port clocked by clk) Endpoint: reg1 (rising edge-triggered flip-flop clocked by clk) Path Group: clk Path Type: min Delay Time Description --------------------------------------------------------- 0.00 0.00 clock clk (rise edge) 0.00 0.00 clock network delay (ideal) 0.00 0.00 ^ input external delay 0.00 0.00 ^ en (in) 0.05 0.05 ^ and1/ZN (AND2_X1) 0.00 0.05 ^ reg1/D (DFF_X1) 0.05 data arrival time 0.00 0.00 clock clk (rise edge) 0.00 0.00 clock network delay (ideal) 0.00 0.00 clock reconvergence pessimism 0.00 ^ reg1/CK (DFF_X1) 0.01 0.01 library hold time 0.01 data required time --------------------------------------------------------- 0.01 data required time -0.05 data arrival time --------------------------------------------------------- 0.04 slack (MET) Startpoint: d1 (input port clocked by clk) Endpoint: reg2 (rising edge-triggered flip-flop clocked by clk) Path Group: clk Path Type: max Delay Time Description --------------------------------------------------------- 0.00 0.00 clock clk (rise edge) 0.00 0.00 clock network delay (ideal) 1.00 1.00 ^ input external delay 0.00 1.00 ^ d1 (in) 0.03 1.03 ^ buf1/Z (BUF_X1) 0.01 1.04 v inv1/ZN (INV_X1) 0.03 1.07 v and1/ZN (AND2_X1) 0.05 1.11 v or1/ZN (OR2_X1) 0.03 1.14 v buf3/Z (BUF_X1) 0.00 1.14 v reg2/D (DFF_X1) 1.14 data arrival time 10.00 10.00 clock clk (rise edge) 0.00 10.00 clock network delay (ideal) 0.00 10.00 clock reconvergence pessimism 10.00 ^ reg2/CK (DFF_X1) -0.04 9.96 library setup time 9.96 data required time --------------------------------------------------------- 9.96 data required time -1.14 data arrival time --------------------------------------------------------- 8.82 slack (MET) --- report_slews --- d1 ^ 0.10:0.10 v 0.10:0.10 d2 ^ 0.10:0.10 v 0.10:0.10 en ^ 0.10:0.10 v 0.10:0.10 q1 ^ 0.01:0.01 v 0.00:0.00 q2 ^ 0.01:0.01 v 0.00:0.00 buf1/Z ^ 0.01:0.01 v 0.01:0.01 inv1/ZN ^ 0.01:0.01 v 0.00:0.00 and1/ZN ^ 0.01:0.01 v 0.01:0.01 or1/ZN ^ 0.01:0.01 v 0.01:0.01 reg1/Q ^ 0.01:0.01 v 0.00:0.00 reg2/Q ^ 0.01:0.01 v 0.00:0.00 --- report_checks -unconstrained --- Startpoint: d1 (input port clocked by clk) Endpoint: reg2 (rising edge-triggered flip-flop clocked by clk) Path Group: clk Path Type: max Delay Time Description --------------------------------------------------------- 0.00 0.00 clock clk (rise edge) 0.00 0.00 clock network delay (ideal) 1.00 1.00 ^ input external delay 0.00 1.00 ^ d1 (in) 0.03 1.03 ^ buf1/Z (BUF_X1) 0.01 1.04 v inv1/ZN (INV_X1) 0.03 1.07 v and1/ZN (AND2_X1) 0.05 1.11 v or1/ZN (OR2_X1) 0.03 1.14 v buf3/Z (BUF_X1) 0.00 1.14 v reg2/D (DFF_X1) 1.14 data arrival time 10.00 10.00 clock clk (rise edge) 0.00 10.00 clock network delay (ideal) 0.00 10.00 clock reconvergence pessimism 10.00 ^ reg2/CK (DFF_X1) -0.04 9.96 library setup time 9.96 data required time --------------------------------------------------------- 9.96 data required time -1.14 data arrival time --------------------------------------------------------- 8.82 slack (MET) --- report_checks counts --- Warning: graph_incremental.tcl line 1, report_checks -group_count is deprecated. Use -group_path_count instead. Startpoint: d1 (input port clocked by clk) Endpoint: reg2 (rising edge-triggered flip-flop clocked by clk) Path Group: clk Path Type: max Delay Time Description --------------------------------------------------------- 0.00 0.00 clock clk (rise edge) 0.00 0.00 clock network delay (ideal) 1.00 1.00 ^ input external delay 0.00 1.00 ^ d1 (in) 0.03 1.03 ^ buf1/Z (BUF_X1) 0.01 1.04 v inv1/ZN (INV_X1) 0.03 1.07 v and1/ZN (AND2_X1) 0.05 1.11 v or1/ZN (OR2_X1) 0.03 1.14 v buf3/Z (BUF_X1) 0.00 1.14 v reg2/D (DFF_X1) 1.14 data arrival time 10.00 10.00 clock clk (rise edge) 0.00 10.00 clock network delay (ideal) 0.00 10.00 clock reconvergence pessimism 10.00 ^ reg2/CK (DFF_X1) -0.04 9.96 library setup time 9.96 data required time --------------------------------------------------------- 9.96 data required time -1.14 data arrival time --------------------------------------------------------- 8.82 slack (MET) Startpoint: d1 (input port clocked by clk) Endpoint: reg1 (rising edge-triggered flip-flop clocked by clk) Path Group: clk Path Type: max Delay Time Description --------------------------------------------------------- 0.00 0.00 clock clk (rise edge) 0.00 0.00 clock network delay (ideal) 1.00 1.00 v input external delay 0.00 1.00 v d1 (in) 0.06 1.06 v buf1/Z (BUF_X1) 0.01 1.07 ^ inv1/ZN (INV_X1) 0.03 1.10 ^ and1/ZN (AND2_X1) 0.00 1.10 ^ reg1/D (DFF_X1) 1.10 data arrival time 10.00 10.00 clock clk (rise edge) 0.00 10.00 clock network delay (ideal) 0.00 10.00 clock reconvergence pessimism 10.00 ^ reg1/CK (DFF_X1) -0.03 9.97 library setup time 9.97 data required time --------------------------------------------------------- 9.97 data required time -1.10 data arrival time --------------------------------------------------------- 8.87 slack (MET) Startpoint: reg1 (rising edge-triggered flip-flop clocked by clk) Endpoint: q1 (output port clocked by clk) Path Group: clk Path Type: max Delay Time Description --------------------------------------------------------- 0.00 0.00 clock clk (rise edge) 0.00 0.00 clock network delay (ideal) 0.00 0.00 ^ reg1/CK (DFF_X1) 0.08 0.08 ^ reg1/Q (DFF_X1) 0.00 0.08 ^ q1 (out) 0.08 data arrival time 10.00 10.00 clock clk (rise edge) 0.00 10.00 clock network delay (ideal) 0.00 10.00 clock reconvergence pessimism -1.00 9.00 output external delay 9.00 data required time --------------------------------------------------------- 9.00 data required time -0.08 data arrival time --------------------------------------------------------- 8.92 slack (MET) Warning: graph_incremental.tcl line 1, report_checks -endpoint_count is deprecated. Use -endpoint_path_count instead. Startpoint: d1 (input port clocked by clk) Endpoint: reg2 (rising edge-triggered flip-flop clocked by clk) Path Group: clk Path Type: max Delay Time Description --------------------------------------------------------- 0.00 0.00 clock clk (rise edge) 0.00 0.00 clock network delay (ideal) 1.00 1.00 ^ input external delay 0.00 1.00 ^ d1 (in) 0.03 1.03 ^ buf1/Z (BUF_X1) 0.01 1.04 v inv1/ZN (INV_X1) 0.03 1.07 v and1/ZN (AND2_X1) 0.05 1.11 v or1/ZN (OR2_X1) 0.03 1.14 v buf3/Z (BUF_X1) 0.00 1.14 v reg2/D (DFF_X1) 1.14 data arrival time 10.00 10.00 clock clk (rise edge) 0.00 10.00 clock network delay (ideal) 0.00 10.00 clock reconvergence pessimism 10.00 ^ reg2/CK (DFF_X1) -0.04 9.96 library setup time 9.96 data required time --------------------------------------------------------- 9.96 data required time -1.14 data arrival time --------------------------------------------------------- 8.82 slack (MET) Startpoint: d1 (input port clocked by clk) Endpoint: reg2 (rising edge-triggered flip-flop clocked by clk) Path Group: clk Path Type: max Delay Time Description --------------------------------------------------------- 0.00 0.00 clock clk (rise edge) 0.00 0.00 clock network delay (ideal) 1.00 1.00 v input external delay 0.00 1.00 v d1 (in) 0.06 1.06 v buf1/Z (BUF_X1) 0.01 1.07 ^ inv1/ZN (INV_X1) 0.03 1.10 ^ and1/ZN (AND2_X1) 0.02 1.12 ^ or1/ZN (OR2_X1) 0.02 1.14 ^ buf3/Z (BUF_X1) 0.00 1.14 ^ reg2/D (DFF_X1) 1.14 data arrival time 10.00 10.00 clock clk (rise edge) 0.00 10.00 clock network delay (ideal) 0.00 10.00 clock reconvergence pessimism 10.00 ^ reg2/CK (DFF_X1) -0.03 9.97 library setup time 9.97 data required time --------------------------------------------------------- 9.97 data required time -1.14 data arrival time --------------------------------------------------------- 8.83 slack (MET) Startpoint: d2 (input port clocked by clk) Endpoint: reg2 (rising edge-triggered flip-flop clocked by clk) Path Group: clk Path Type: max Delay Time Description --------------------------------------------------------- 0.00 0.00 clock clk (rise edge) 0.00 0.00 clock network delay (ideal) 1.00 1.00 v input external delay 0.00 1.00 v d2 (in) 0.05 1.05 v buf2/Z (BUF_X2) 0.04 1.09 v or1/ZN (OR2_X1) 0.03 1.12 v buf3/Z (BUF_X1) 0.00 1.12 v reg2/D (DFF_X1) 1.12 data arrival time 10.00 10.00 clock clk (rise edge) 0.00 10.00 clock network delay (ideal) 0.00 10.00 clock reconvergence pessimism 10.00 ^ reg2/CK (DFF_X1) -0.04 9.96 library setup time 9.96 data required time --------------------------------------------------------- 9.96 data required time -1.12 data arrival time --------------------------------------------------------- 8.84 slack (MET) Warning: graph_incremental.tcl line 1, report_checks -endpoint_count is deprecated. Use -endpoint_path_count instead. Startpoint: en (input port clocked by clk) Endpoint: reg1 (rising edge-triggered flip-flop clocked by clk) Path Group: clk Path Type: min Delay Time Description --------------------------------------------------------- 0.00 0.00 clock clk (rise edge) 0.00 0.00 clock network delay (ideal) 0.00 0.00 ^ input external delay 0.00 0.00 ^ en (in) 0.05 0.05 ^ and1/ZN (AND2_X1) 0.00 0.05 ^ reg1/D (DFF_X1) 0.05 data arrival time 0.00 0.00 clock clk (rise edge) 0.00 0.00 clock network delay (ideal) 0.00 0.00 clock reconvergence pessimism 0.00 ^ reg1/CK (DFF_X1) 0.01 0.01 library hold time 0.01 data required time --------------------------------------------------------- 0.01 data required time -0.05 data arrival time --------------------------------------------------------- 0.04 slack (MET) Startpoint: en (input port clocked by clk) Endpoint: reg1 (rising edge-triggered flip-flop clocked by clk) Path Group: clk Path Type: min Delay Time Description --------------------------------------------------------- 0.00 0.00 clock clk (rise edge) 0.00 0.00 clock network delay (ideal) 0.00 0.00 v input external delay 0.00 0.00 v en (in) 0.07 0.07 v and1/ZN (AND2_X1) 0.00 0.07 v reg1/D (DFF_X1) 0.07 data arrival time 0.00 0.00 clock clk (rise edge) 0.00 0.00 clock network delay (ideal) 0.00 0.00 clock reconvergence pessimism 0.00 ^ reg1/CK (DFF_X1) 0.00 0.00 library hold time 0.00 data required time --------------------------------------------------------- 0.00 data required time -0.07 data arrival time --------------------------------------------------------- 0.06 slack (MET) Startpoint: en (input port clocked by clk) Endpoint: reg2 (rising edge-triggered flip-flop clocked by clk) Path Group: clk Path Type: min Delay Time Description --------------------------------------------------------- 0.00 0.00 clock clk (rise edge) 0.00 0.00 clock network delay (ideal) 0.00 0.00 ^ input external delay 0.00 0.00 ^ en (in) 0.05 0.05 ^ and1/ZN (AND2_X1) 0.02 0.07 ^ or1/ZN (OR2_X1) 0.02 0.09 ^ buf3/Z (BUF_X1) 0.00 0.09 ^ reg2/D (DFF_X1) 0.09 data arrival time 0.00 0.00 clock clk (rise edge) 0.00 0.00 clock network delay (ideal) 0.00 0.00 clock reconvergence pessimism 0.00 ^ reg2/CK (DFF_X1) 0.00 0.00 library hold time 0.00 data required time --------------------------------------------------------- 0.00 data required time -0.09 data arrival time --------------------------------------------------------- 0.08 slack (MET) Startpoint: en (input port clocked by clk) Endpoint: reg2 (rising edge-triggered flip-flop clocked by clk) Path Group: clk Path Type: min Delay Time Description --------------------------------------------------------- 0.00 0.00 clock clk (rise edge) 0.00 0.00 clock network delay (ideal) 0.00 0.00 v input external delay 0.00 0.00 v en (in) 0.07 0.07 v and1/ZN (AND2_X1) 0.05 0.11 v or1/ZN (OR2_X1) 0.03 0.14 v buf3/Z (BUF_X1) 0.00 0.14 v reg2/D (DFF_X1) 0.14 data arrival time 0.00 0.00 clock clk (rise edge) 0.00 0.00 clock network delay (ideal) 0.00 0.00 clock reconvergence pessimism 0.00 ^ reg2/CK (DFF_X1) 0.00 0.00 library hold time 0.00 data required time --------------------------------------------------------- 0.00 data required time -0.14 data arrival time --------------------------------------------------------- 0.14 slack (MET) Startpoint: d2 (input port clocked by clk) Endpoint: reg2 (rising edge-triggered flip-flop clocked by clk) Path Group: clk Path Type: min Delay Time Description --------------------------------------------------------- 0.00 0.00 clock clk (rise edge) 0.00 0.00 clock network delay (ideal) 1.00 1.00 ^ input external delay 0.00 1.00 ^ d2 (in) 0.03 1.03 ^ buf2/Z (BUF_X2) 0.02 1.05 ^ or1/ZN (OR2_X1) 0.02 1.07 ^ buf3/Z (BUF_X1) 0.00 1.07 ^ reg2/D (DFF_X1) 1.07 data arrival time 0.00 0.00 clock clk (rise edge) 0.00 0.00 clock network delay (ideal) 0.00 0.00 clock reconvergence pessimism 0.00 ^ reg2/CK (DFF_X1) 0.00 0.00 library hold time 0.00 data required time --------------------------------------------------------- 0.00 data required time -1.07 data arrival time --------------------------------------------------------- 1.06 slack (MET)