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# Created by write_sdc
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current_design sdc_test2
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# Timing Constraints
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create_clock -name clk1 -period 10.0000 [get_ports {clk1}]
set_clock_transition 0.1000 [get_clocks {clk1}]
set_clock_uncertainty -setup 0.2000 clk1
set_clock_uncertainty -hold 0.1000 clk1
set_propagated_clock [get_clocks {clk1}]
create_clock -name clk2 -period 20.0000 [get_ports {clk2}]
create_generated_clock -name gen_div2 -source [get_ports {clk1}] -divide_by 2 [get_pins {reg1/Q}]
set_clock_latency 0.3000 [get_clocks {clk2}]
set_clock_latency -source 0.5000 [get_clocks {clk1}]
set_input_delay 2.0000 -clock [get_clocks {clk1}] -add_delay [get_ports {in1}]
set_input_delay 1.5000 -clock [get_clocks {clk1}] -add_delay [get_ports {in2}]
set_input_delay 1.8000 -clock [get_clocks {clk1}] -add_delay [get_ports {in3}]
set_output_delay 3.0000 -clock [get_clocks {clk1}] -add_delay [get_ports {out1}]
set_output_delay 2.5000 -clock [get_clocks {clk2}] -add_delay [get_ports {out2}]
set_multicycle_path -setup\
    -from [get_ports {in1}]\
    -to [get_ports {out1}] 2
set_max_delay\
    -from [get_ports {in2}]\
    -to [get_ports {out1}] 8.0000
set_false_path\
    -from [get_clocks {clk1}]\
    -to [get_clocks {clk2}]
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# Environment
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set_operating_conditions typical
set_load -pin_load 0.0500 [get_ports {out1}]
set_load -pin_load 0.0400 [get_ports {out2}]
set_driving_cell -lib_cell BUF_X1 -pin {Z} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {in1}]
set_input_transition 0.1500 [get_ports {in1}]
set_case_analysis 0 [get_ports {in3}]
set_timing_derate -early 0.9500
set_timing_derate -late 1.0500
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# Design Rules
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set_max_transition 0.5000 [current_design]
set_max_capacitance 0.2000 [current_design]
set_max_fanout 20.0000 [current_design]