module verilog_supply_tristate (clk,
    in1,
    in2,
    in3,
    en,
    out1,
    out2,
    out3,
    outbus);
 input clk;
 input in1;
 input in2;
 input in3;
 input en;
 output out1;
 tri out1;
 output out2;
 output out3;
 output [3:0] outbus;

 wire gnd_net;
 wire n1;
 wire n2;
 wire n3;
 wire n4;
 wire n5;
 wire n6;
 wire vdd_net;

 AND2_X1 and1 (.A1(n1),
    .A2(n2),
    .ZN(n4));
 BUF_X1 buf1 (.A(in1),
    .Z(n1));
 BUF_X1 buf2 (.A(in2),
    .Z(n2));
 BUF_X1 buf3 (.A(n5),
    .Z(n6));
 OR2_X1 or1 (.A1(n3),
    .A2(n4),
    .ZN(n5));
 DFF_X1 reg1 (.D(n5),
    .CK(clk),
    .Q(out1));
 DFF_X1 reg2 (.D(n6),
    .CK(clk),
    .Q(out2));
 DFF_X1 reg3 (.D(in3),
    .CK(clk),
    .Q(outbus[0]));
 DFF_X1 reg4 (.D(n1),
    .CK(clk),
    .Q(outbus[1]));
 DFF_X1 reg5 (.D(n2),
    .CK(clk),
    .Q(outbus[2]));
 DFF_X1 reg6 (.D(n3),
    .CK(clk),
    .Q(outbus[3]));
 assign out3 = n6;
endmodule