INV_X1 is_leaf = 1
INV_X1 is_buffer = 0
INV_X1 is_inverter = 1
BUF_X1 is_leaf = 1
BUF_X1 is_buffer = 1
BUF_X1 is_inverter = 0
NAND2_X1 is_leaf = 1
NAND2_X1 is_buffer = 0
NAND2_X1 is_inverter = 0
DFF_X1 is_leaf = 1
DFF_X1 is_buffer = 0
DFF_X1 is_inverter = 0
INV_X1 lib name = NangateOpenCellLibrary
SDFF_X1 has test_cell
INV_X1/A function = 
INV_X1/ZN function = !A
TINV_X1/EN function = 
TINV_X1/ZN tristate_enable = !EN
INV_X1/A bus_name = A
INV_X1/A is_bus = 0
INV_X1/A is_bus_bit = 0
INV_X1/A is_bundle = 0
INV_X1/A is_bundle_member = 0
INV_X1/A has_members = 0
INV_X1/A is_pwr_gnd = 0
INV_X1/A scan_signal_type = none
SDFF_X1/SI scan_signal_type = none
SDFF_X1/SI is_bus = 0
INV_X1 all ports = 4
NAND2_X1 A* ports = 2
NAND2_X1 regexp ports = 2
NAND2_X1 nocase zn ports = 0
INV_X1 ports via iterator = 4
AOI21_X1 ports via iterator = 6
Arc: INV_X1 A -> ZN role=combinational is_check=0
  sdf_cond=
DFF Arc: DFF_X1 CK -> D role=hold is_check=1
DFF Arc: DFF_X1 CK -> D role=setup is_check=1
DFF Arc: DFF_X1 CK -> CK role=width is_check=1
DFF Arc: DFF_X1 CK -> Q role=Reg Clk to Q is_check=0
DFF Arc: DFF_X1 CK -> QN role=Reg Clk to Q is_check=0
DFFR Arc: DFFR_X1 CK -> D role=hold is_check=1
DFFR Arc: DFFR_X1 CK -> D role=setup is_check=1
DFFR Arc: DFFR_X1 CK -> RN role=recovery is_check=1
DFFR Arc: DFFR_X1 CK -> RN role=removal is_check=1
DFFR Arc: DFFR_X1 RN -> RN role=width is_check=1
DFFR Arc: DFFR_X1 CK -> CK role=width is_check=1
DFFR Arc: DFFR_X1 CK -> Q role=Reg Clk to Q is_check=0
DFFR Arc: DFFR_X1 RN -> Q role=Reg Set/Clr is_check=0
DFFR Arc: DFFR_X1 RN -> Q role=Reg Set/Clr is_check=0
DFFR Arc: DFFR_X1 RN -> Q role=Reg Set/Clr is_check=0
DFFR Arc: DFFR_X1 RN -> Q role=Reg Set/Clr is_check=0
DFFR Arc: DFFR_X1 CK -> QN role=Reg Clk to Q is_check=0
DFFR Arc: DFFR_X1 RN -> QN role=Reg Set/Clr is_check=0
DFFR Arc: DFFR_X1 RN -> QN role=Reg Set/Clr is_check=0
DFFR Arc: DFFR_X1 RN -> QN role=Reg Set/Clr is_check=0
DFFR Arc: DFFR_X1 RN -> QN role=Reg Set/Clr is_check=0
  Arc detail: A rise -> ZN fall role=combinational
  Arc detail: A fall -> ZN rise role=combinational
  DFF arc: rise -> rise role=hold
  DFF arc: rise -> fall role=hold
  DFF arc: rise -> rise role=setup
  DFF arc: rise -> fall role=setup
  DFF arc: rise -> fall role=width
  DFF arc: fall -> rise role=width
  DFF arc: rise -> rise role=Reg Clk to Q
  DFF arc: rise -> fall role=Reg Clk to Q
  DFF arc: rise -> rise role=Reg Clk to Q
  DFF arc: rise -> fall role=Reg Clk to Q
Default opcond process = 1.0
Default opcond voltage = 1.100000023841858
Default opcond temperature = 25.0
Typical opcond process = 1.0
Typical opcond voltage = 1.100000023841858
Typical opcond temperature = 25.0
Found wireload 5K_hvratio_1_1
Found wireload selection
Library: NangateOpenCellLibrary
INV_X1/A cap max = 1.700229965024007e-15
INV_X1/A cap min = 1.5493600563490969e-15
  PwrGnd port: VDD dir=power
  PwrGnd port: VSS dir=ground
  FA_X1 port: VDD dir=power is_bus=0
  FA_X1 port: VSS dir=ground is_bus=0
  FA_X1 port: A dir=input is_bus=0
  FA_X1 port: B dir=input is_bus=0
  FA_X1 port: CI dir=input is_bus=0
  FA_X1 port: CO dir=output is_bus=0
  FA_X1 port: S dir=output is_bus=0