--- Test 1: read verilog with assign ---
cells: 8
nets: 13
ports: 7
buf1: ref=BUF_X1
buf2: ref=BUF_X1
and1: ref=AND2_X1
inv1: ref=INV_X1
or1: ref=OR2_X1
reg1: ref=DFF_X1
reg2: ref=DFF_X1
reg3: ref=DFF_X1
--- Test 2: timing with assign nets ---
Startpoint: in3 (input port clocked by clk)
Endpoint: reg3 (rising edge-triggered flip-flop clocked by clk)
Path Group: clk
Path Type: max

  Delay    Time   Description
---------------------------------------------------------
   0.00    0.00   clock clk (rise edge)
   0.00    0.00   clock network delay (ideal)
   0.00    0.00 v input external delay
   0.00    0.00 v in3 (in)
   0.00    0.00 v reg3/D (DFF_X1)
           0.00   data arrival time

  10.00   10.00   clock clk (rise edge)
   0.00   10.00   clock network delay (ideal)
   0.00   10.00   clock reconvergence pessimism
          10.00 ^ reg3/CK (DFF_X1)
  -3.03    6.97   library setup time
           6.97   data required time
---------------------------------------------------------
           6.97   data required time
          -0.00   data arrival time
---------------------------------------------------------
           6.97   slack (MET)


Startpoint: in3 (input port clocked by clk)
Endpoint: reg3 (rising edge-triggered flip-flop clocked by clk)
Path Group: clk
Path Type: min

  Delay    Time   Description
---------------------------------------------------------
   0.00    0.00   clock clk (rise edge)
   0.00    0.00   clock network delay (ideal)
   0.00    0.00 v input external delay
   0.00    0.00 v in3 (in)
   0.00    0.00 v reg3/D (DFF_X1)
           0.00   data arrival time

   0.00    0.00   clock clk (rise edge)
   0.00    0.00   clock network delay (ideal)
   0.00    0.00   clock reconvergence pessimism
           0.00 ^ reg3/CK (DFF_X1)
   9.01    9.01   library hold time
           9.01   data required time
---------------------------------------------------------
           9.01   data required time
          -0.00   data arrival time
---------------------------------------------------------
          -9.01   slack (VIOLATED)


No paths found.
No paths found.
No paths found.
Startpoint: in3 (input port clocked by clk)
Endpoint: reg3 (rising edge-triggered flip-flop clocked by clk)
Path Group: clk
Path Type: max

Fanout     Cap    Slew   Delay    Time   Description
-----------------------------------------------------------------------------
                  0.00    0.00    0.00   clock clk (rise edge)
                          0.00    0.00   clock network delay (ideal)
                          0.00    0.00 v input external delay
     2    1.96   10.00    0.00    0.00 v in3 (in)
                 10.00    0.00    0.00 v reg3/D (DFF_X1)
                                  0.00   data arrival time

                  0.00   10.00   10.00   clock clk (rise edge)
                          0.00   10.00   clock network delay (ideal)
                          0.00   10.00   clock reconvergence pessimism
                                 10.00 ^ reg3/CK (DFF_X1)
                         -3.03    6.97   library setup time
                                  6.97   data required time
-----------------------------------------------------------------------------
                                  6.97   data required time
                                 -0.00   data arrival time
-----------------------------------------------------------------------------
                                  6.97   slack (MET)


--- Test 3: assign-related queries ---
assigned_net found: in3
net n1: n1
net n2: n2
net n3: n3
net n4: n4
net n5: n5
Net n1
 Pin capacitance: 0.87-0.92
 Wire capacitance: 0.00
 Total capacitance: 0.87-0.92
 Number of drivers: 1
 Number of loads: 1
 Number of pins: 2

Driver pins
 buf1/Z output (BUF_X1)

Load pins
 and1/A1 input (AND2_X1) 0.87-0.92

report_net n1: done
Net n3
 Pin capacitance: 2.61-2.84
 Wire capacitance: 0.00
 Total capacitance: 2.61-2.84
 Number of drivers: 1
 Number of loads: 2
 Number of pins: 3

Driver pins
 and1/ZN output (AND2_X1)

Load pins
 inv1/A input (INV_X1) 1.55-1.70
 reg1/D input (DFF_X1) 1.06-1.14

report_net n3: done
Net n5
 Pin capacitance: 1.06-1.14
 Wire capacitance: 0.00
 Total capacitance: 1.06-1.14
 Number of drivers: 1
 Number of loads: 1
 Number of pins: 2

Driver pins
 or1/ZN output (OR2_X1)

Load pins
 reg2/D input (DFF_X1) 1.06-1.14

report_net n5: done
Instance buf1
 Cell: BUF_X1
 Library: NangateOpenCellLibrary
 Path cells: BUF_X1
 Input pins:
  A input in1
 Output pins:
  Z output n1
 Other pins:
  VDD power (unconnected)
  VSS ground (unconnected)
report_instance buf1: done
Instance and1
 Cell: AND2_X1
 Library: NangateOpenCellLibrary
 Path cells: AND2_X1
 Input pins:
  A1 input n1
  A2 input n2
 Output pins:
  ZN output n3
 Other pins:
  VDD power (unconnected)
  VSS ground (unconnected)
report_instance and1: done
Instance inv1
 Cell: INV_X1
 Library: NangateOpenCellLibrary
 Path cells: INV_X1
 Input pins:
  A input n3
 Output pins:
  ZN output n4
 Other pins:
  VDD power (unconnected)
  VSS ground (unconnected)
report_instance inv1: done
Instance or1
 Cell: OR2_X1
 Library: NangateOpenCellLibrary
 Path cells: OR2_X1
 Input pins:
  A1 input n4
  A2 input in3
 Output pins:
  ZN output n5
 Other pins:
  VDD power (unconnected)
  VSS ground (unconnected)
report_instance or1: done
Instance reg1
 Cell: DFF_X1
 Library: NangateOpenCellLibrary
 Path cells: DFF_X1
 Input pins:
  D input n3
  CK input clk
 Output pins:
  Q output out1
  QN output (unconnected)
 Other pins:
  VDD power (unconnected)
  VSS ground (unconnected)
  IQ internal (unconnected)
  IQN internal (unconnected)
report_instance reg1: done
Instance reg2
 Cell: DFF_X1
 Library: NangateOpenCellLibrary
 Path cells: DFF_X1
 Input pins:
  D input n5
  CK input clk
 Output pins:
  Q output out2
  QN output (unconnected)
 Other pins:
  VDD power (unconnected)
  VSS ground (unconnected)
  IQ internal (unconnected)
  IQN internal (unconnected)
report_instance reg2: done
--- Test 4: write verilog ---
No differences found.
--- Test 5: fanin/fanout through assign ---
fanin to out2: 3
fanout from in3: 5
fanin cells to out2: 2
fanout cells from in3: 4