module verilog_test1 (clk,
    in1,
    out1);
 input clk;
 input in1;
 output out1;

 wire extra_net;
 wire n1;

 BUF_X1 buf1 (.A(in1),
    .Z(n1));
 BUF_X2 extra_buf (.A(extra_net));
 DFF_X1 reg1 (.D(n1),
    .CK(clk),
    .Q(out1));
endmodule