James Cherry
|
fa849908d7
|
set_cmd_units
|
2019-07-08 11:50:41 -07:00 |
|
James Cherry
|
f34fc4162d
|
base class destructors public virtual or protected non-virtual
|
2019-06-30 22:30:53 -07:00 |
|
James Cherry
|
93f5f9d664
|
no need for virtuals in Concrete network objects
|
2019-06-28 13:38:56 -07:00 |
|
James Cherry
|
12494398e9
|
set_clock_sense -> set_sense, LibertyPort::driveResistance
|
2019-06-23 19:52:29 -07:00 |
|
James Cherry
|
b9a7b349eb
|
template tcl typemap(in) seqs/sets
|
2019-06-22 11:17:13 -07:00 |
|
James Cherry
|
337fab4c44
|
equiv cells dont_use turd
|
2019-06-21 13:21:37 -07:00 |
|
James Cherry
|
5f23536b17
|
support equiv cells across libraries
|
2019-06-20 21:41:49 -07:00 |
|
James Cherry
|
db2a06c430
|
findCmdLineFlag/Key
|
2019-06-17 16:42:26 -07:00 |
|
James Cherry
|
49b2c3cea7
|
rm redundant StaState args
|
2019-06-17 08:32:28 -07:00 |
|
James Cherry
|
d9237aa3e5
|
Liberty cell drive_resistance property
|
2019-06-16 10:20:51 -07:00 |
|
James Cherry
|
96fcf1d8b2
|
ConcreteCell/Port pointers to corresponding liberty
|
2019-06-15 22:20:54 -07:00 |
|
James Cherry
|
61b1ac4d12
|
sync
|
2019-06-04 08:12:22 -07:00 |
|
James Cherry
|
736a977a6d
|
Liberty equiv cells in LibertyCell instead of map
|
2019-05-28 07:45:05 -07:00 |
|
James Cherry
|
53df9472d7
|
resizer support
|
2019-05-27 22:46:24 -07:00 |
|
James Cherry
|
8242035b22
|
LibertyCell::isBuffer()
|
2019-05-25 20:02:33 -07:00 |
|
James Cherry
|
6a194ef6ee
|
LibertyCell::higherDrive(), slowerDrive()
|
2019-05-25 17:08:53 -07:00 |
|
James Cherry
|
a988588dac
|
sync
|
2019-05-19 17:06:06 -06:00 |
|
James Cherry
|
c6db5eb0ae
|
power don't required related_pg_pin in internal_power
|
2019-05-11 07:11:27 -06:00 |
|
James Cherry
|
d1a602cefc
|
2.0.15
|
2019-04-29 08:39:05 -07:00 |
|
James Cherry
|
12ca613886
|
2.0.14
|
2019-04-18 18:01:10 -07:00 |
|
James Cherry
|
4fc8801e76
|
or20190411 write_path_spice with no voltage_map, pg_pins
|
2019-04-13 15:01:14 -07:00 |
|
James Cherry
|
2d519b4740
|
ucsd 20190410 seg fault accessing/setting power_default_signal_toggle_rate
|
2019-04-10 20:36:48 -07:00 |
|
James Cherry
|
fcfec7ae54
|
2.0.13
|
2019-04-01 09:05:07 -07:00 |
|
James Cherry
|
ed3ad4fb30
|
copyright etc
|
2019-03-29 14:18:08 -07:00 |
|
James Cherry
|
75bf56b1f1
|
normalized_voltage template var misspelled
|
2019-03-27 15:01:11 -07:00 |
|
James Cherry
|
28799b9b09
|
sync 03/26/2019
|
2019-03-26 16:07:32 -07:00 |
|
James Cherry
|
e2d02839a3
|
examples
|
2019-03-21 10:48:50 -07:00 |
|
James Cherry
|
5a5164276e
|
read_liberty check timing arcs
|
2019-03-19 21:30:19 -07:00 |
|
James Cherry
|
e5c9bc43fd
|
2.0.10
|
2019-03-12 17:25:53 -07:00 |
|
James Cherry
|
dae85f08e0
|
misspelled "Deescription", gcc warnings
|
2019-03-03 17:50:56 -08:00 |
|
James Cherry
|
0f2dba7eff
|
sync
|
2019-02-26 08:26:12 -08:00 |
|
James Cherry
|
d8146af755
|
remove autotools/configure support
|
2019-02-16 12:07:59 -08:00 |
|
James Cherry
|
3f65204717
|
2.0.6
|
2019-01-26 23:03:01 -08:00 |
|
James Cherry
|
f2a28bdcaf
|
write_path_spice register path support
|
2019-01-22 20:41:32 -08:00 |
|
James Cherry
|
316742202f
|
sync
|
2019-01-16 15:37:31 -08:00 |
|
James Cherry
|
9e5aac37f4
|
cmake, write_path_spice
|
2019-01-03 16:14:15 -08:00 |
|
James Cherry
|
b075ccc783
|
update copyright
|
2019-01-01 12:26:11 -08:00 |
|
James Cherry
|
9435640d5a
|
write_spice alpha
|
2019-01-01 12:25:25 -08:00 |
|
James Cherry
|
a6e21377e6
|
2.0.2
|
2018-12-26 11:03:31 -08:00 |
|
James Cherry
|
4f381f6669
|
2018/12/24 all_fanout from input port
|
2018-12-24 13:07:10 -08:00 |
|
James Cherry
|
e1059eac12
|
find_timing_paths
|
2018-12-20 22:41:54 -08:00 |
|
James Cherry
|
f49dc75d32
|
sync
|
2018-12-05 14:18:41 -08:00 |
|
James Cherry
|
ddf897d4e6
|
report_power, pocv support
|
2018-11-26 09:15:52 -08:00 |
|
James Cherry
|
e9bde796ec
|
2018/11/08 corners > 2 causes internal error, 2018/11/09 Verilog ignore attributes (* blah *)
|
2018-11-09 10:04:16 -08:00 |
|
James Cherry
|
e68203dcf4
|
^/v for arc display
|
2018-10-02 16:20:18 -07:00 |
|
James Cherry
|
1154fb89fd
|
and then there was light...
|
2018-09-28 08:54:21 -07:00 |