James Cherry
|
b36d2753d1
|
graph dcalc use ClkNetwork
|
2020-08-09 22:33:32 -07:00 |
James Cherry
|
0db8d142d8
|
ClkNetwork
|
2020-08-08 18:44:19 -07:00 |
James Cherry
|
ff7557bb1f
|
merge
|
2020-08-05 21:01:53 -07:00 |
James Cherry
|
ae3da179e2
|
set_power_activity -pins
|
2020-08-05 07:23:38 -07:00 |
James Cherry
|
cafb7b9152
|
reorg power headers
|
2020-07-31 09:42:24 -07:00 |
James Cherry
|
a23ba7b88e
|
power activity for internal pins
|
2020-07-30 07:55:48 -07:00 |
James Cherry
|
6cdb9d3cfe
|
power
|
2020-07-29 18:14:56 -07:00 |
James Cherry
|
746ed77193
|
get_property liberty_port drive_resistance
|
2020-07-26 21:41:19 -07:00 |
James Cherry
|
3970a1b314
|
swig cmake
|
2020-07-25 17:02:56 -07:00 |
James Cherry
|
157ef75a10
|
Sta::makeInstanceAfter internal pins may be missing
|
2020-07-25 15:29:46 -07:00 |
James Cherry
|
2ce82bd187
|
include Machine.hh in headers that use __attribute__
|
2020-07-18 19:54:10 -07:00 |
James Cherry
|
305a9bbf70
|
rm deprecated code
|
2020-07-18 09:13:17 -07:00 |
James Cherry
|
1c8f1ec9fc
|
VerilogWriter using instead of include for LibertyCell
|
2020-07-18 09:12:38 -07:00 |
James Cherry
|
9882f9d938
|
swig_link_libraries back in
|
2020-07-15 15:12:14 -07:00 |
James Cherry
|
a5722ae63c
|
write_verilog remove_cells use std::vector
|
2020-07-15 11:56:11 -07:00 |
James Cherry
|
4fa9e46235
|
write_verilog -remove_cells
|
2020-07-15 07:56:34 -07:00 |
James Cherry
|
d296a3405d
|
rm swig_link_libraries
|
2020-07-13 11:30:26 -07:00 |
James Cherry
|
00d0da6d5a
|
Sta::networkChanged() invalidate sdc graph annotations
|
2020-07-13 11:11:39 -07:00 |
James Cherry
|
f3a50663d8
|
set_data_check support mcp, 1/2 cycle path reporting
|
2020-07-13 07:38:39 -07:00 |
James Cherry
|
f60b82fee5
|
hpin clk disables without graph
|
2020-07-12 10:29:06 -07:00 |
James Cherry
|
7e71edecf2
|
separate sdc annotate/remove functions
|
2020-07-12 08:55:44 -07:00 |
James Cherry
|
a49dd870df
|
refactor sdc graph annotation
|
2020-07-11 23:56:39 -07:00 |
James Cherry
|
57a12d9c66
|
merge
|
2020-07-11 17:58:57 -07:00 |
James Cherry
|
7653096fe6
|
Delay compare ops round2
|
2020-07-11 17:43:30 -07:00 |
James Cherry
|
9468da1ae8
|
Delay compare ops
|
2020-07-11 16:24:48 -07:00 |
James Cherry
|
894b4887d8
|
report clk used as data respect -format
|
2020-07-10 17:08:44 -07:00 |
James Cherry
|
b7a572cfe2
|
LibertyPort::capacitance()
|
2020-07-09 16:10:21 -07:00 |
James Cherry
|
b54125a1ae
|
get_property pin is_register_clock
|
2020-07-09 11:26:06 -07:00 |
James Cherry
|
46d2446f88
|
LibertyCell::isInverter
|
2020-07-09 08:42:52 -07:00 |
James Cherry
|
a24048395a
|
merge
|
2020-07-08 08:02:13 -07:00 |
James Cherry
|
b3b4677341
|
worst slack empty check
|
2020-07-08 08:01:43 -07:00 |
James Cherry
|
64a196da75
|
report json syntax
|
2020-07-07 17:08:17 -07:00 |
James Cherry
|
79f3de683c
|
merge
|
2020-07-07 17:08:09 -07:00 |
James Cherry
|
bf161cc759
|
compiler warning
|
2020-07-07 17:07:50 -07:00 |
James Cherry
|
7f037334bf
|
compiler warning
|
2020-07-06 18:35:36 -07:00 |
James Cherry
|
875778b25a
|
json xy digits
|
2020-07-06 16:49:25 -07:00 |
James Cherry
|
6d95ef44e5
|
SdcNetwork::location(pin)
|
2020-07-06 16:28:58 -07:00 |
James Cherry
|
2cab7b18e5
|
Network::location(pin)
|
2020-07-06 15:59:16 -07:00 |
James Cherry
|
ccff78468b
|
pin_location_str
|
2020-07-06 15:42:53 -07:00 |
James Cherry
|
9cb7222f56
|
pin_location
|
2020-07-06 15:35:03 -07:00 |
James Cherry
|
27cc8f1614
|
report_path -format json
|
2020-07-06 15:18:13 -07:00 |
James Cherry
|
17b48a681b
|
get_property pin name
|
2020-07-06 09:45:45 -07:00 |
James Cherry
|
6b448fe2c9
|
write_sdc set_load net
|
2020-07-05 16:37:50 -07:00 |
James Cherry
|
3d4b0cf1a3
|
no crpr for ideal clks
|
2020-07-05 08:08:18 -07:00 |
James Cherry
|
2627ed3812
|
doc
|
2020-07-05 08:08:11 -07:00 |
James Cherry
|
3d492eddee
|
get -filter spaces around op not required
|
2020-07-04 08:26:11 -07:00 |
James Cherry
|
47bb1e124f
|
merge
|
2020-07-03 18:20:20 -07:00 |
James Cherry
|
535a09edcc
|
get_cells -of_objects ports
|
2020-07-03 18:19:39 -07:00 |
James Cherry
|
2b30d90555
|
DelayNormal.cc condition
|
2020-07-03 18:19:26 -07:00 |
James Cherry
|
e7ed3170f3
|
write_verilog power/ground port dcls
|
2020-07-03 16:56:15 -07:00 |