From f72bf5ce019dc4304ccd8c7a96553c547079b39e Mon Sep 17 00:00:00 2001
From: Matt Liberty <mliberty@precisioninno.com>
Date: Tue, 18 Nov 2025 06:36:19 +0000
Subject: [PATCH] Prefetch https://github.com/parallaxsw/OpenSTA/pull/334

Signed-off-by: Matt Liberty <mliberty@precisioninno.com>
---
 verilog/VerilogReader.cc | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/verilog/VerilogReader.cc b/verilog/VerilogReader.cc
index b7e0260f..f9ea77e9 100644
--- a/verilog/VerilogReader.cc
+++ b/verilog/VerilogReader.cc
@@ -534,7 +534,7 @@ VerilogReader::makeModuleInst(const string *module_vname,
   // to reduce the memory footprint of the verilog parser.
   if (liberty_cell
       && hasScalarNamedPortRefs(liberty_cell, pins)) {
-    int port_count = network_->portBitCount(cell);
+    int port_count = liberty_cell->portBitCount();
     StdStringSeq net_names(port_count);
     for (VerilogNet *vnet : *pins) {
       VerilogNetPortRefScalarNet *vpin =