diff --git a/.gitignore b/.gitignore index 3d0ac7c1..01ec0da2 100644 --- a/.gitignore +++ b/.gitignore @@ -32,3 +32,6 @@ test/results test/b3v3_1check.log doc/messages.txt + +# clangd turds +.cache/ diff --git a/CMakeLists.txt b/CMakeLists.txt index 6a06e180..8f28b74e 100644 --- a/CMakeLists.txt +++ b/CMakeLists.txt @@ -155,6 +155,7 @@ set(STA_SOURCE sdc/Sdc.cc sdc/SdcGraph.cc sdc/SdcCmdComment.cc + sdc/Variables.cc sdc/WriteSdc.cc sdf/ReportAnnotation.cc diff --git a/dcalc/ArnoldiDelayCalc.cc b/dcalc/ArnoldiDelayCalc.cc index 4fcf5b4c..efd194a1 100644 --- a/dcalc/ArnoldiDelayCalc.cc +++ b/dcalc/ArnoldiDelayCalc.cc @@ -48,6 +48,7 @@ #include "ArcDelayCalc.hh" #include "LumpedCapDelayCalc.hh" #include "GraphDelayCalc.hh" +#include "Variables.hh" #include "Arnoldi.hh" #include "ArnoldiReduce.hh" @@ -64,6 +65,7 @@ namespace sta { // ra_get_s using std::abs; +using std::vector; struct delay_work; struct delay_c; @@ -234,6 +236,7 @@ private: ArnoldiReduce *reduce_; delay_work *delay_work_; vector unsaved_parasitics_; + bool pocv_enabled_; }; ArcDelayCalc * @@ -391,6 +394,7 @@ ArnoldiDelayCalc::gateDelay(const Pin *drvr_pin, ConcreteParasitic *cparasitic = reinterpret_cast(const_cast(parasitic)); rcmodel_ = dynamic_cast(cparasitic); + pocv_enabled_ = variables_->pocvEnabled(); GateTableModel *table_model = arc->gateTableModel(dcalc_ap); if (table_model && rcmodel_) { const Pvt *pvt = pinPvt(drvr_pin, dcalc_ap); diff --git a/dcalc/ArnoldiReduce.cc b/dcalc/ArnoldiReduce.cc index 5e5ce066..43d57f46 100644 --- a/dcalc/ArnoldiReduce.cc +++ b/dcalc/ArnoldiReduce.cc @@ -38,6 +38,8 @@ namespace sta { +using std::string; + rcmodel::rcmodel() : pinV(nullptr) { diff --git a/dcalc/CcsCeffDelayCalc.hh b/dcalc/CcsCeffDelayCalc.hh index 663b6607..428605ca 100644 --- a/dcalc/CcsCeffDelayCalc.hh +++ b/dcalc/CcsCeffDelayCalc.hh @@ -29,9 +29,7 @@ namespace sta { -using std::vector; - -typedef map WatchPinValuesMap; +typedef std::map WatchPinValuesMap; ArcDelayCalc * makeCcsCeffDelayCalc(StaState *sta); @@ -68,7 +66,7 @@ public: Waveform watchWaveform(const Pin *pin) override; protected: - typedef vector Region; + typedef std::vector Region; void gateDelaySlew(const LibertyLibrary *drvr_library, const RiseFall *rf, diff --git a/dcalc/DelayCalcBase.cc b/dcalc/DelayCalcBase.cc index b4484664..0f4b5c6b 100644 --- a/dcalc/DelayCalcBase.cc +++ b/dcalc/DelayCalcBase.cc @@ -35,6 +35,7 @@ #include "Corner.hh" #include "DcalcAnalysisPt.hh" #include "GraphDelayCalc.hh" +#include "Variables.hh" namespace sta { @@ -167,7 +168,8 @@ DelayCalcBase::checkDelay(const Pin *check_pin, float from_slew1 = delayAsFloat(from_slew); float to_slew1 = delayAsFloat(to_slew); return model->checkDelay(pinPvt(check_pin, dcalc_ap), from_slew1, to_slew1, - related_out_cap, pocv_enabled_); + related_out_cap, + variables_->pocvEnabled()); } else return delay_zero; diff --git a/dcalc/DmpCeff.cc b/dcalc/DmpCeff.cc index a47348d7..d278b7a4 100644 --- a/dcalc/DmpCeff.cc +++ b/dcalc/DmpCeff.cc @@ -47,6 +47,7 @@ #include "DcalcAnalysisPt.hh" #include "ArcDelayCalc.hh" #include "FindRoot.hh" +#include "Variables.hh" namespace sta { @@ -371,7 +372,8 @@ DmpAlg::gateCapDelaySlew(double ceff, { ArcDelay model_delay; Slew model_slew; - gate_model_->gateDelay(pvt_, in_slew_, ceff, pocv_enabled_, + gate_model_->gateDelay(pvt_, in_slew_, ceff, + variables_->pocvEnabled(), model_delay, model_slew); delay = delayAsFloat(model_delay); slew = delayAsFloat(model_slew); @@ -1562,7 +1564,7 @@ DmpCeffDelayCalc::setCeffAlgorithm(const LibertyLibrary *drvr_library, double rd = 0.0; if (gate_model) { rd = gateModelRd(drvr_cell, gate_model, rf, in_slew, c2, c1, - pvt, pocv_enabled_); + pvt, variables_->pocvEnabled()); // Zero Rd means the table is constant and thus independent of load cap. if (rd < 1e-2 // Rpi is small compared to Rd, which makes the load capacitive. @@ -1630,9 +1632,10 @@ DmpCeffDelayCalc::reportGateDelay(const Pin *drvr_pin, const Unit *time_unit = units->timeUnit(); float in_slew1 = delayAsFloat(in_slew); result += model->reportGateDelay(pinPvt(drvr_pin, dcalc_ap), in_slew1, c_eff, - pocv_enabled_, digits); + variables_->pocvEnabled(), digits); result += "Driver waveform slew = "; - result += time_unit->asString(dcalc_result.drvrSlew(), digits); + float drvr_slew = delayAsFloat(dcalc_result.drvrSlew()); + result += time_unit->asString(drvr_slew, digits); result += '\n'; } return result; diff --git a/dcalc/GraphDelayCalc.cc b/dcalc/GraphDelayCalc.cc index da42e090..3047b4b1 100644 --- a/dcalc/GraphDelayCalc.cc +++ b/dcalc/GraphDelayCalc.cc @@ -45,10 +45,12 @@ #include "DcalcAnalysisPt.hh" #include "NetCaps.hh" #include "ClkNetwork.hh" +#include "Variables.hh" namespace sta { using std::abs; +using std::array; static const Slew default_slew = 0.0; @@ -365,7 +367,7 @@ GraphDelayCalc::seedNoDrvrCellSlew(Vertex *drvr_vertex, else { // Top level bidirect driver uses load slew unless // bidirect instance paths are disabled. - if (sdc_->bidirectDrvrSlewFromLoad(drvr_pin)) { + if (bidirectDrvrSlewFromLoad(drvr_pin)) { Vertex *load_vertex = graph_->pinLoadVertex(drvr_pin); slew = graph_->slew(load_vertex, rf, ap_index); } @@ -393,6 +395,17 @@ GraphDelayCalc::seedNoDrvrCellSlew(Vertex *drvr_vertex, arc_delay_calc->finishDrvrPin(); } +// Delay calculation propagates slews from a bidirect driver +// to the bidirect port and back through the bidirect driver when +// sta_bidirect_inst_paths_enabled_ is true. +bool +GraphDelayCalc::bidirectDrvrSlewFromLoad(const Pin *pin) const +{ + return variables_->bidirectInstPathsEnabled() + && network_->direction(pin)->isBidirect() + && network_->isTopLevelPort(pin); +} + void GraphDelayCalc::seedNoDrvrSlew(Vertex *drvr_vertex, const Pin *drvr_pin, @@ -405,7 +418,7 @@ GraphDelayCalc::seedNoDrvrSlew(Vertex *drvr_vertex, Slew slew(default_slew); // Top level bidirect driver uses load slew unless // bidirect instance paths are disabled. - if (sdc_->bidirectDrvrSlewFromLoad(drvr_pin)) { + if (bidirectDrvrSlewFromLoad(drvr_pin)) { Vertex *load_vertex = graph_->pinLoadVertex(drvr_pin); slew = graph_->slew(load_vertex, rf, ap_index); } @@ -1185,7 +1198,7 @@ GraphDelayCalc::annotateLoadDelays(Vertex *drvr_vertex, if (load_changed && observer_) observer_->delayChangedTo(load_vertex); // Enqueue bidirect driver from load vertex. - if (sdc_->bidirectDrvrSlewFromLoad(load_pin)) + if (bidirectDrvrSlewFromLoad(load_pin)) iter_->enqueue(graph_->pinDrvrVertex(load_pin)); changed |= load_changed; } diff --git a/dcalc/LumpedCapDelayCalc.cc b/dcalc/LumpedCapDelayCalc.cc index 66bf9e7f..7bd01419 100644 --- a/dcalc/LumpedCapDelayCalc.cc +++ b/dcalc/LumpedCapDelayCalc.cc @@ -37,6 +37,7 @@ #include "Parasitics.hh" #include "DcalcAnalysisPt.hh" #include "GraphDelayCalc.hh" +#include "Variables.hh" namespace sta { @@ -144,7 +145,8 @@ LumpedCapDelayCalc::gateDelay(const Pin *drvr_pin, // NaNs cause seg faults during table lookup. if (isnan(load_cap) || isnan(delayAsFloat(in_slew))) report_->error(1350, "gate delay input variable is NaN"); - model->gateDelay(pinPvt(drvr_pin, dcalc_ap), in_slew1, load_cap, pocv_enabled_, + model->gateDelay(pinPvt(drvr_pin, dcalc_ap), in_slew1, load_cap, + variables_->pocvEnabled(), gate_delay, drvr_slew); return makeResult(drvr_library, rf, gate_delay, drvr_slew, load_pin_index_map); } diff --git a/dcalc/ParallelDelayCalc.cc b/dcalc/ParallelDelayCalc.cc index 70eb5404..8bb5b18c 100644 --- a/dcalc/ParallelDelayCalc.cc +++ b/dcalc/ParallelDelayCalc.cc @@ -34,6 +34,8 @@ namespace sta { +using std::vector; + ParallelDelayCalc::ParallelDelayCalc(StaState *sta): DelayCalcBase(sta) { diff --git a/dcalc/PrimaDelayCalc.cc b/dcalc/PrimaDelayCalc.cc index 7aeb442f..d72cedff 100644 --- a/dcalc/PrimaDelayCalc.cc +++ b/dcalc/PrimaDelayCalc.cc @@ -285,7 +285,7 @@ PrimaDelayCalc::simulate() simulate1(Gq_, Cq_, Bq_, xq_init_, Vq_, prima_order_); } else { - MatrixXd x_to_v = MatrixXd::Identity(order_, order_); + Eigen::MatrixXd x_to_v = Eigen::MatrixXd::Identity(order_, order_); simulate1(G_, C_, B_, x_init_, x_to_v, order_); } } @@ -293,14 +293,14 @@ PrimaDelayCalc::simulate() void PrimaDelayCalc::simulate1(const MatrixSd &G, const MatrixSd &C, - const MatrixXd &B, - const VectorXd &x_init, - const MatrixXd &x_to_v, + const Eigen::MatrixXd &B, + const Eigen::VectorXd &x_init, + const Eigen::MatrixXd &x_to_v, const size_t order) { - VectorXd x(order); - VectorXd x_prev(order); - VectorXd x_prev2(order); + Eigen::VectorXd x(order); + Eigen::VectorXd x_prev(order); + Eigen::VectorXd x_prev2(order); v_.resize(order); v_prev_.resize(order); @@ -321,7 +321,7 @@ PrimaDelayCalc::simulate1(const MatrixSd &G, // Initial time depends on ceff which impact delay, so use a sim step // to find an initial ceff. setPortCurrents(); - VectorXd rhs(order); + Eigen::VectorXd rhs(order); rhs = B * u_ + (1.0 / time_step_) * C * (3.0 * x_prev - x_prev2); x = A_solver.solve(rhs); v_ = x_to_v * x; @@ -771,12 +771,12 @@ PrimaDelayCalc::primaReduce() SparseLU G_solver(G_); if (G_solver.info() != Eigen::Success) report_->error(1752, "G matrix is singular."); - MatrixXd R(order_, port_count_); + Eigen::MatrixXd R(order_, port_count_); R = G_solver.solve(B_); // Step 4 - HouseholderQR R_solver(R); - MatrixXd Q = R_solver.householderQ(); + Eigen::HouseholderQR R_solver(R); + Eigen::MatrixXd Q = R_solver.householderQ(); // Vq is "X" in the prima paper (too many "x" variables in the paper). Vq_.resize(order_, prima_order_); @@ -785,7 +785,7 @@ PrimaDelayCalc::primaReduce() // Step 6 - Arnolid iteration for (size_t k = 1; k < prima_order_; k++) { - VectorXd V = C_ * Vq_.col(k - 1); + Eigen::VectorXd V = C_ * Vq_.col(k - 1); Vq_.col(k) = G_solver.solve(V); // Modified Gram-Schmidt orthonormalization @@ -793,9 +793,9 @@ PrimaDelayCalc::primaReduce() double H = Vq_.col(j).transpose() * Vq_.col(k); Vq_.col(k) = Vq_.col(k) - H * Vq_.col(j); } - VectorXd Vq_k = Vq_.col(k); - HouseholderQR Vq_k_solver(Vq_k); - MatrixXd VqQ = Vq_k_solver.householderQ(); + Eigen::VectorXd Vq_k = Vq_.col(k); + Eigen::HouseholderQR Vq_k_solver(Vq_k); + Eigen::MatrixXd VqQ = Vq_k_solver.householderQ(); Vq_.col(k) = VqQ.col(0); } @@ -824,36 +824,36 @@ PrimaDelayCalc::primaReduce2() { G_.makeCompressed(); // Step 3: solve G*R = B for R - SparseLU G_solver(G_); - MatrixXd R(order_, port_count_); + Eigen::SparseLU G_solver(G_); + Eigen::MatrixXd R(order_, port_count_); R = G_solver.solve(B_); // Step 4 - HouseholderQR R_solver(R); - MatrixXd Q = R_solver.householderQ(); + Eigen::HouseholderQR R_solver(R); + Eigen::MatrixXd Q = R_solver.householderQ(); // Vq is "X" in the prima paper (too many "x" variables in the paper). size_t n = ceil(prima_order_ / static_cast(port_count_)); - MatrixXd Vq(order_, n * port_count_); + Eigen::MatrixXd Vq(order_, n * port_count_); // // Vq = first port_count columns of Q. Vq.block(0, 0, order_, port_count_) = Q.block(0, 0, order_, port_count_); // Step 6 - Arnolid iteration for (size_t k = 1; k < n; k++) { - MatrixXd V = C_ * Vq.block(0, (k - 1) * port_count_, order_, port_count_); - MatrixXd GV = G_solver.solve(V); + Eigen::MatrixXd V = C_ * Vq.block(0, (k - 1) * port_count_, order_, port_count_); + Eigen::MatrixXd GV = G_solver.solve(V); Vq.block(0, k * port_count_, order_, port_count_) = GV; // Modified Gram-Schmidt orthonormalization for (size_t j = 0; j < k; j++) { - MatrixXd H = Vq.block(0, j * port_count_, order_, port_count_).transpose() + Eigen::MatrixXd H = Vq.block(0, j * port_count_, order_, port_count_).transpose() * Vq.block(0, k * port_count_, order_, port_count_); Vq.block(0, k * port_count_, order_, port_count_) = Vq.block(0, k * port_count_, order_, port_count_) - Vq.block(0, j * port_count_, order_, port_count_) * H; } - MatrixXd Vq_k = Vq.block(0, k * port_count_, order_, port_count_); - HouseholderQR Vq_k_solver(Vq_k); - MatrixXd VqQ = Vq_k_solver.householderQ(); + Eigen::MatrixXd Vq_k = Vq.block(0, k * port_count_, order_, port_count_); + Eigen::HouseholderQR Vq_k_solver(Vq_k); + Eigen::MatrixXd VqQ = Vq_k_solver.householderQ(); Vq.block(0, k * port_count_, order_, port_count_) = VqQ.block(0, 0, order_, port_count_); } @@ -970,7 +970,7 @@ PrimaDelayCalc::reportMatrix(const char *name, void PrimaDelayCalc::reportMatrix(const char *name, - MatrixXd &matrix) + Eigen::MatrixXd &matrix) { report_->reportLine("%s", name); reportMatrix(matrix); @@ -978,7 +978,7 @@ PrimaDelayCalc::reportMatrix(const char *name, void PrimaDelayCalc::reportMatrix(const char *name, - VectorXd &matrix) + Eigen::VectorXd &matrix) { report_->reportLine("%s", name); reportMatrix(matrix); @@ -986,7 +986,7 @@ PrimaDelayCalc::reportMatrix(const char *name, void PrimaDelayCalc::reportVector(const char *name, - vector &matrix) + std::vector &matrix) { report_->reportLine("%s", name); reportVector(matrix); @@ -995,10 +995,10 @@ PrimaDelayCalc::reportVector(const char *name, void PrimaDelayCalc::reportMatrix(MatrixSd &matrix) { - for (Index i = 0; i < matrix.rows(); i++) { + for (Eigen::Index i = 0; i < matrix.rows(); i++) { string line = "| "; - for (Index j = 0; j < matrix.cols(); j++) { - string entry = stdstrPrint("%10.3e", matrix.coeff(i, j)); + for (Eigen::Index j = 0; j < matrix.cols(); j++) { + std::string entry = stdstrPrint("%10.3e", matrix.coeff(i, j)); line += entry; line += " "; } @@ -1008,12 +1008,12 @@ PrimaDelayCalc::reportMatrix(MatrixSd &matrix) } void -PrimaDelayCalc::reportMatrix(MatrixXd &matrix) +PrimaDelayCalc::reportMatrix(Eigen::MatrixXd &matrix) { - for (Index i = 0; i < matrix.rows(); i++) { - string line = "| "; - for (Index j = 0; j < matrix.cols(); j++) { - string entry = stdstrPrint("%10.3e", matrix.coeff(i, j)); + for (Eigen::Index i = 0; i < matrix.rows(); i++) { + std::string line = "| "; + for (Eigen::Index j = 0; j < matrix.cols(); j++) { + std::string entry = stdstrPrint("%10.3e", matrix.coeff(i, j)); line += entry; line += " "; } @@ -1023,11 +1023,11 @@ PrimaDelayCalc::reportMatrix(MatrixXd &matrix) } void -PrimaDelayCalc::reportMatrix(VectorXd &matrix) +PrimaDelayCalc::reportMatrix(Eigen::VectorXd &matrix) { - string line = "| "; - for (Index i = 0; i < matrix.rows(); i++) { - string entry = stdstrPrint("%10.3e", matrix.coeff(i)); + std::string line = "| "; + for (Eigen::Index i = 0; i < matrix.rows(); i++) { + std::string entry = stdstrPrint("%10.3e", matrix.coeff(i)); line += entry; line += " "; } @@ -1036,11 +1036,11 @@ PrimaDelayCalc::reportMatrix(VectorXd &matrix) } void -PrimaDelayCalc::reportVector(vector &matrix) +PrimaDelayCalc::reportVector(std::vector &matrix) { - string line = "| "; + std::string line = "| "; for (size_t i = 0; i < matrix.size(); i++) { - string entry = stdstrPrint("%10.3e", matrix[i]); + std::string entry = stdstrPrint("%10.3e", matrix[i]); line += entry; line += " "; } diff --git a/dcalc/PrimaDelayCalc.hh b/dcalc/PrimaDelayCalc.hh index 530d9813..454fdc98 100644 --- a/dcalc/PrimaDelayCalc.hh +++ b/dcalc/PrimaDelayCalc.hh @@ -40,21 +40,12 @@ class ArcDelayCalc; class StaState; class Corner; -using std::vector; -using std::array; -using Eigen::MatrixXd; -using Eigen::MatrixXcd; -using Eigen::VectorXd; -using Eigen::SparseMatrix; -using Eigen::Index; -using std::map; - typedef Map PinNodeMap; -typedef map NodeIndexMap; +typedef std::map NodeIndexMap; typedef Map PortIndexMap; -typedef SparseMatrix MatrixSd; -typedef Map PinLMap; -typedef map WatchPinValuesMap; +typedef Eigen::SparseMatrix MatrixSd; +typedef Map PinLMap; +typedef std::map WatchPinValuesMap; typedef Table1 Waveform; @@ -96,14 +87,14 @@ public: ArcDcalcResultSeq gateDelays(ArcDcalcArgSeq &dcalc_args, const LoadPinIndexMap &load_pin_index_map, const DcalcAnalysisPt *dcalc_ap) override; - string reportGateDelay(const Pin *drvr_pin, - const TimingArc *arc, - const Slew &in_slew, - float load_cap, - const Parasitic *parasitic, - const LoadPinIndexMap &load_pin_index_map, - const DcalcAnalysisPt *dcalc_ap, - int digits) override; + std::string reportGateDelay(const Pin *drvr_pin, + const TimingArc *arc, + const Slew &in_slew, + float load_cap, + const Parasitic *parasitic, + const LoadPinIndexMap &load_pin_index_map, + const DcalcAnalysisPt *dcalc_ap, + int digits) override; // Record waveform for drvr/load pin. void watchPin(const Pin *pin) override; @@ -116,9 +107,9 @@ protected: void simulate(); void simulate1(const MatrixSd &G, const MatrixSd &C, - const MatrixXd &B, - const VectorXd &x_init, - const MatrixXd &x_to_v, + const Eigen::MatrixXd &B, + const Eigen::VectorXd &x_init, + const Eigen::MatrixXd &x_to_v, const size_t order); double maxTime(); double timeStep(); @@ -164,15 +155,15 @@ protected: void reportMatrix(const char *name, MatrixSd &matrix); void reportMatrix(const char *name, - MatrixXd &matrix); + Eigen::MatrixXd &matrix); void reportMatrix(const char *name, - VectorXd &matrix); + Eigen::VectorXd &matrix); void reportVector(const char *name, - vector &matrix); + std::vector &matrix); void reportMatrix(MatrixSd &matrix); - void reportMatrix(MatrixXd &matrix); - void reportMatrix(VectorXd &matrix); - void reportVector(vector &matrix); + void reportMatrix(Eigen::MatrixXd &matrix); + void reportMatrix(Eigen::VectorXd &matrix); + void reportVector(std::vector &matrix); ArcDcalcArgSeq *dcalc_args_; size_t drvr_count_; @@ -184,10 +175,10 @@ protected: PinNodeMap pin_node_map_; // Parasitic pin -> array index NodeIndexMap node_index_map_; // Parasitic node -> array index - vector output_waveforms_; + std::vector output_waveforms_; double resistance_sum_; - vector node_capacitances_; + std::vector node_capacitances_; bool includes_pin_caps_; float coupling_cap_multiplier_; @@ -199,25 +190,25 @@ protected: // G*x(t) + C*x'(t) = B*u(t) MatrixSd G_; MatrixSd C_; - MatrixXd B_; - VectorXd x_init_; - VectorXd u_; + Eigen::MatrixXd B_; + Eigen::VectorXd x_init_; + Eigen::VectorXd u_; // Prima reduced MNA eqns size_t prima_order_; - MatrixXd Vq_; + Eigen::MatrixXd Vq_; MatrixSd Gq_; MatrixSd Cq_; - MatrixXd Bq_; - VectorXd xq_init_; + Eigen::MatrixXd Bq_; + Eigen::VectorXd xq_init_; // Node voltages. - VectorXd v_; // voltage[node_idx] - VectorXd v_prev_; + Eigen::VectorXd v_; // voltage[node_idx] + Eigen::VectorXd v_prev_; // Indexed by driver index. - vector ceff_; - vector drvr_current_; + std::vector ceff_; + std::vector drvr_current_; double time_step_; double time_step_prev_; @@ -240,11 +231,11 @@ protected: static constexpr size_t threshold_vth = 1; static constexpr size_t threshold_vh = 2; static constexpr size_t measure_threshold_count_ = 3; - typedef array ThresholdTimes; + typedef std::array ThresholdTimes; // Vl Vth Vh ThresholdTimes measure_thresholds_; // Indexed by node number. - vector threshold_times_; + std::vector threshold_times_; // Delay calculator to use when ccs waveforms are missing from liberty. ArcDelayCalc *table_dcalc_; diff --git a/examples/gcd_sky130hd.saif.gz b/examples/gcd_sky130hd.saif.gz index 82ef6e7d..b2d65eed 100644 Binary files a/examples/gcd_sky130hd.saif.gz and b/examples/gcd_sky130hd.saif.gz differ diff --git a/graph/DelayNormal1.cc b/graph/DelayNormal1.cc index 37aa3d13..d50db11f 100644 --- a/graph/DelayNormal1.cc +++ b/graph/DelayNormal1.cc @@ -32,6 +32,7 @@ #include "Fuzzy.hh" #include "Units.hh" #include "StaState.hh" +#include "Variables.hh" // SSTA compilation. #if (SSTA == 1) @@ -237,7 +238,7 @@ delayAsFloat(const Delay &delay, const EarlyLate *early_late, const StaState *sta) { - if (sta->pocvEnabled()) { + if (sta->variables()->pocvEnabled()) { if (early_late == EarlyLate::early()) return delay.mean() - delay.sigma() * sta->sigmaFactor(); else if (early_late == EarlyLate::late()) @@ -268,7 +269,7 @@ delayAsString(const Delay &delay, int digits) { const Unit *unit = sta->units()->timeUnit(); - if (sta->pocvEnabled()) { + if (sta->variables()->pocvEnabled()) { float sigma = delay.sigma(); return stringPrintTmp("%s[%s]", unit->asString(delay.mean(), digits), diff --git a/graph/Graph.cc b/graph/Graph.cc index b0f45b22..aa78eedf 100644 --- a/graph/Graph.cc +++ b/graph/Graph.cc @@ -38,6 +38,8 @@ namespace sta { +using std::string; + //////////////////////////////////////////////////////////////// // // Graph @@ -1298,7 +1300,8 @@ Edge::setArcDelayAnnotated(const TimingArc *arc, if (index > sizeof(intptr_t) * 8 && arc_delay_annotated_is_bits_) { arc_delay_annotated_is_bits_ = false; - arc_delay_annotated_.seq_ = new vector(ap_count * RiseFall::index_count * 2); + size_t bit_count = ap_count * RiseFall::index_count * 2; + arc_delay_annotated_.seq_ = new std::vector(bit_count); } if (arc_delay_annotated_is_bits_) { if (annotated) diff --git a/include/sta/ArcDelayCalc.hh b/include/sta/ArcDelayCalc.hh index 5f670189..3d9ef21c 100644 --- a/include/sta/ArcDelayCalc.hh +++ b/include/sta/ArcDelayCalc.hh @@ -40,10 +40,6 @@ namespace sta { -using std::string; -using std::vector; -using std::map; - class Corner; class Parasitic; class DcalcAnalysisPt; @@ -54,7 +50,7 @@ typedef std::vector ArcDcalcArgPtrSeq; typedef std::vector ArcDcalcArgSeq; // Driver load pin -> index in driver loads. -typedef map LoadPinIndexMap; +typedef std::map LoadPinIndexMap; // Arguments for gate delay calculation delay/slew at one driver pin // through one timing arc at one delay calc analysis point. @@ -138,12 +134,12 @@ protected: ArcDelay gate_delay_; Slew drvr_slew_; // Load wire delay and slews indexed by load pin index. - vector wire_delays_; - vector load_slews_; + std::vector wire_delays_; + std::vector load_slews_; }; -typedef vector ArcDcalcArgSeq; -typedef vector ArcDcalcResultSeq; +typedef std::vector ArcDcalcArgSeq; +typedef std::vector ArcDcalcResultSeq; // Delay calculator class hierarchy. // ArcDelayCalc diff --git a/include/sta/ConcreteLibrary.hh b/include/sta/ConcreteLibrary.hh index 26128899..4dda2647 100644 --- a/include/sta/ConcreteLibrary.hh +++ b/include/sta/ConcreteLibrary.hh @@ -45,10 +45,10 @@ class PatternMatch; class LibertyCell; class LibertyPort; -typedef Map ConcreteCellMap; -typedef std::map AttributeMap; +typedef Map ConcreteCellMap; +typedef std::map AttributeMap; typedef Vector ConcretePortSeq; -typedef Map ConcretePortMap; +typedef Map ConcretePortMap; typedef ConcreteCellMap::ConstIterator ConcreteLibraryCellIterator; typedef ConcretePortSeq::ConstIterator ConcreteCellPortIterator; typedef ConcretePortSeq::ConstIterator ConcretePortMemberIterator; @@ -82,9 +82,9 @@ protected: void renameCell(ConcreteCell *cell, const char *cell_name); - string name_; + std::string name_; ObjectId id_; - string filename_; + std::string filename_; bool is_liberty_; char bus_brkt_left_; char bus_brkt_right_; @@ -114,9 +114,9 @@ public: ConcreteCellPortBitIterator *portBitIterator() const; bool isLeaf() const { return is_leaf_; } void setIsLeaf(bool is_leaf); - void setAttribute(const string &key, - const string &value); - string getAttribute(const string &key) const; + void setAttribute(const std::string &key, + const std::string &value); + std::string getAttribute(const std::string &key) const; // Cell acts as port factory. ConcretePort *makePort(const char *name); @@ -156,10 +156,10 @@ protected: const char *name, int index); - string name_; + std::string name_; ObjectId id_; // Filename is optional. - string filename_; + std::string filename_; ConcreteLibrary *library_; LibertyCell *liberty_cell_; // External application cell. @@ -236,7 +236,7 @@ protected: ConcretePortSeq *member_ports, ConcreteCell *cell); - string name_; + std::string name_; ObjectId id_; ConcreteCell *cell_; PortDirection *direction_; diff --git a/include/sta/ConcreteNetwork.hh b/include/sta/ConcreteNetwork.hh index 1ca87061..ad182ada 100644 --- a/include/sta/ConcreteNetwork.hh +++ b/include/sta/ConcreteNetwork.hh @@ -46,7 +46,7 @@ class ConcreteBindingTbl; class ConcreteLibertyLibraryIterator; typedef Vector ConcreteLibrarySeq; -typedef std::map AttributeMap; +typedef std::map AttributeMap; typedef Map ConcreteLibraryMap; typedef ConcreteLibrarySeq::ConstIterator ConcreteLibraryIterator; typedef Map class EnumNameMap { public: - EnumNameMap(initializer_list> enum_names); + EnumNameMap(std::initializer_list> enum_names); const char *find(ENUM key) const; - ENUM find(string name, + ENUM find(std::string name, ENUM unknown_key) const; - void find(string name, + void find(std::string name, // Return values. ENUM &key, bool &exists) const; private: - map enum_map_; - map name_map_; + std::map enum_map_; + std::map name_map_; }; template -EnumNameMap::EnumNameMap(initializer_list> enum_names) : +EnumNameMap::EnumNameMap(std::initializer_list> enum_names) : enum_map_(enum_names) { for (const auto& [key, name] : enum_map_) @@ -74,7 +69,7 @@ EnumNameMap::find(ENUM key) const template void -EnumNameMap::find(string name, +EnumNameMap::find(std::string name, // Return values. ENUM &key, bool &exists) const @@ -90,7 +85,7 @@ EnumNameMap::find(string name, template ENUM -EnumNameMap::find(string name, +EnumNameMap::find(std::string name, ENUM unknown_key) const { auto find_iter = name_map_.find(name); diff --git a/include/sta/Error.hh b/include/sta/Error.hh index e700a58e..e5dc3b8f 100644 --- a/include/sta/Error.hh +++ b/include/sta/Error.hh @@ -48,7 +48,7 @@ public: virtual bool suppressed() const { return suppressed_; } private: - string msg_; + std::string msg_; bool suppressed_; }; diff --git a/include/sta/FuncExpr.hh b/include/sta/FuncExpr.hh index 5ccf2be1..ae7a0bc1 100644 --- a/include/sta/FuncExpr.hh +++ b/include/sta/FuncExpr.hh @@ -32,8 +32,6 @@ namespace sta { -using std::string; - class FuncExpr { public: @@ -79,7 +77,7 @@ public: TimingSense portTimingSense(const LibertyPort *port) const; // Return true if expression has port as an input. bool hasPort(const LibertyPort *port) const; - string to_string() const; + std::string to_string() const; // Sub expression for a bus function (bit_offset is 0 to bus->size()-1). FuncExpr *bitSubExpr(int bit_offset); // Check to make sure the function and port size are compatible. @@ -88,9 +86,9 @@ public: bool checkSize(LibertyPort *port); private: - string to_string(bool with_parens) const; - string to_string(bool with_parens, - char op) const; + std::string to_string(bool with_parens) const; + std::string to_string(bool with_parens, + char op) const; Operator op_; FuncExpr *left_; diff --git a/include/sta/Graph.hh b/include/sta/Graph.hh index daff9bb6..365d979c 100644 --- a/include/sta/Graph.hh +++ b/include/sta/Graph.hh @@ -247,7 +247,7 @@ public: ~Vertex(); Pin *pin() const { return pin_; } // Pin path with load/driver suffix for bidirects. - string to_string(const StaState *sta) const; + std::string to_string(const StaState *sta) const; // compatibility const char *name(const Network *network) const; bool isBidirectDriver() const { return is_bidirect_drvr_; } @@ -366,7 +366,7 @@ class Edge public: Edge(); ~Edge(); - string to_string(const StaState *sta) const; + std::string to_string(const StaState *sta) const; Vertex *to(const Graph *graph) const { return graph->vertex(to_); } VertexId to() const { return to_; } Vertex *from(const Graph *graph) const { return graph->vertex(from_); } @@ -426,7 +426,7 @@ protected: ArcDelay *arc_delays_; union { uintptr_t bits_; - vector *seq_; + std::vector *seq_; } arc_delay_annotated_; bool arc_delay_annotated_is_bits_:1; bool delay_annotation_is_incremental_:1; diff --git a/include/sta/GraphClass.hh b/include/sta/GraphClass.hh index 1f381f37..381a9b8b 100644 --- a/include/sta/GraphClass.hh +++ b/include/sta/GraphClass.hh @@ -35,8 +35,6 @@ namespace sta { -using std::vector; - // Class declarations for pointer references. class Graph; class Vertex; @@ -56,7 +54,7 @@ typedef int Level; typedef int DcalcAPIndex; typedef int TagGroupIndex; typedef Vector GraphLoopSeq; -typedef vector SlewSeq; +typedef std::vector SlewSeq; static constexpr int level_max = std::numeric_limits::max(); diff --git a/include/sta/GraphDelayCalc.hh b/include/sta/GraphDelayCalc.hh index 96857d6c..959c6d50 100644 --- a/include/sta/GraphDelayCalc.hh +++ b/include/sta/GraphDelayCalc.hh @@ -38,17 +38,13 @@ namespace sta { -using std::vector; -using std::map; -using std::array; - class DelayCalcObserver; class MultiDrvrNet; class FindVertexDelays; class NetCaps; typedef Map MultiDrvrNetMap; -typedef vector DrvrLoadSlews; +typedef std::vector DrvrLoadSlews; // This class traverses the graph calling the arc delay calculator and // annotating delays on graph edges. @@ -132,6 +128,7 @@ public: const RiseFall *from_rf, const TimingRole *role, const DcalcAnalysisPt *dcalc_ap); + bool bidirectDrvrSlewFromLoad(const Pin *pin) const; protected: void seedInvalidDelays(); @@ -190,7 +187,7 @@ protected: ArcDelayCalc *arc_delay_calc, LoadPinIndexMap &load_pin_index_map, // Return value. - array &delay_exists); + std::array &delay_exists); bool findDriverArcDelays(Vertex *drvr_vertex, const MultiDrvrNet *multi_drvr, Edge *edge, @@ -246,7 +243,6 @@ protected: Slew checkEdgeClkSlew(const Vertex *from_vertex, const RiseFall *from_rf, const DcalcAnalysisPt *dcalc_ap); - bool bidirectDrvrSlewFromLoad(const Vertex *vertex) const; float loadCap(const Pin *drvr_pin, const RiseFall *rf, const DcalcAnalysisPt *dcalc_ap, @@ -333,7 +329,7 @@ private: Vertex *dcalc_drvr_; VertexSeq drvrs_; // [drvr_rf->index][dcalc_ap->index] - vector net_caps_; + std::vector net_caps_; }; } // namespace diff --git a/include/sta/Hash.hh b/include/sta/Hash.hh index de5fde5d..4389d7ce 100644 --- a/include/sta/Hash.hh +++ b/include/sta/Hash.hh @@ -29,8 +29,6 @@ namespace sta { -using std::size_t; - const size_t hash_init_value = 5381; // Dan Bernstein, comp.lang.c. diff --git a/include/sta/InternalPower.hh b/include/sta/InternalPower.hh index 6c9e8756..1ca4bf2e 100644 --- a/include/sta/InternalPower.hh +++ b/include/sta/InternalPower.hh @@ -87,11 +87,11 @@ public: const Pvt *pvt, float in_slew, float load_cap) const; - string reportPower(const LibertyCell *cell, - const Pvt *pvt, - float in_slew, - float load_cap, - int digits) const; + std::string reportPower(const LibertyCell *cell, + const Pvt *pvt, + float in_slew, + float load_cap, + int digits) const; protected: void findAxisValues(float in_slew, diff --git a/include/sta/Liberty.hh b/include/sta/Liberty.hh index 23e881d9..fec901fa 100644 --- a/include/sta/Liberty.hh +++ b/include/sta/Liberty.hh @@ -88,9 +88,9 @@ typedef Map LatchEnableMap; typedef Vector LatchEnableSeq; typedef Map OcvDerateMap; typedef Vector InternalPowerAttrsSeq; -typedef Map SupplyVoltageMap; -typedef Map LibertyPgPortMap; -typedef Map DriverWaveformMap; +typedef Map SupplyVoltageMap; +typedef Map LibertyPgPortMap; +typedef Map DriverWaveformMap; typedef Vector DcalcAnalysisPtSeq; enum class ClockGateType { none, latch_posedge, latch_negedge, other }; @@ -647,8 +647,8 @@ protected: bool has_internal_ports_; std::atomic have_voltage_waveforms_; std::mutex waveform_lock_; - string footprint_; - string user_function_class_; + std::string footprint_; + std::string user_function_class_; private: friend class LibertyLibrary; @@ -888,8 +888,8 @@ protected: float min_pulse_width_[RiseFall::index_count]; const RiseFall *pulse_clk_trigger_; const RiseFall *pulse_clk_sense_; - string related_ground_pin_; - string related_power_pin_; + std::string related_ground_pin_; + std::string related_power_pin_; Vector corner_ports_; ReceiverModelPtr receiver_model_; DriverWaveform *driver_waveform_[RiseFall::index_count]; @@ -969,7 +969,7 @@ public: void setWireloadTree(WireloadTree tree); protected: - string name_; + std::string name_; WireloadTree wire_load_tree_; }; @@ -996,7 +996,7 @@ public: void print(); protected: - string name_; + std::string name_; float scales_[scale_factor_type_count][scale_factor_pvt_count][RiseFall::index_count]; }; @@ -1011,7 +1011,7 @@ public: int to() const { return to_; } protected: - string name_; + std::string name_; int from_; int to_; }; @@ -1032,7 +1032,7 @@ protected: // Private to LibertyCell::makeModeDef. ModeDef(const char *name); - string name_; + std::string name_; ModeValueMap values_; private: @@ -1056,9 +1056,9 @@ protected: FuncExpr *cond, const char *sdf_cond); - string value_; + std::string value_; FuncExpr *cond_; - string sdf_cond_; + std::string sdf_cond_; private: friend class ModeDef; @@ -1085,7 +1085,7 @@ public: void setAxis3(TableAxisPtr axis); protected: - string name_; + std::string name_; TableAxisPtr axis1_; TableAxisPtr axis2_; TableAxisPtr axis3_; @@ -1143,13 +1143,13 @@ public: const LibertyPgPort *port2); private: - string name_; + std::string name_; PgType pg_type_; - string voltage_name_; + std::string voltage_name_; LibertyCell *cell_; }; -string +std::string portLibertyToSta(const char *port_name); const char * scanSignalTypeName(ScanSignalType scan_type); diff --git a/include/sta/LibertyClass.hh b/include/sta/LibertyClass.hh index 51ecf4a9..b28d0765 100644 --- a/include/sta/LibertyClass.hh +++ b/include/sta/LibertyClass.hh @@ -32,8 +32,6 @@ namespace sta { -using std::vector; - class Units; class Unit; class LibertyLibrary; @@ -81,7 +79,7 @@ typedef std::shared_ptr TablePtr; typedef std::shared_ptr TimingArcAttrsPtr; typedef std::shared_ptr TableAxisPtr; typedef std::shared_ptr ReceiverModelPtr; -typedef vector StatetableRows; +typedef std::vector StatetableRows; enum class ScaleFactorType : unsigned { pin_cap, diff --git a/include/sta/MinMax.hh b/include/sta/MinMax.hh index 6555852b..15de0e72 100644 --- a/include/sta/MinMax.hh +++ b/include/sta/MinMax.hh @@ -32,8 +32,6 @@ namespace sta { -using std::string; - class MinMax; class MinMaxAll; @@ -58,7 +56,7 @@ public: static int earlyIndex() { return min_.index_; } static int maxIndex() { return max_.index_; } static int lateIndex() { return max_.index_; } - const string &to_string() const { return name_; } + const std::string &to_string() const { return name_; } int index() const { return index_; } float initValue() const { return init_value_; } int initValueInt() const { return init_value_int_; } @@ -91,7 +89,7 @@ private: bool (*compare)(float value1, float value2)); - const string name_; + const std::string name_; int index_; float init_value_; int init_value_int_; @@ -114,7 +112,7 @@ public: static const MinMaxAll *max() { return &max_; } static const MinMaxAll *late() { return &max_; } static const MinMaxAll *all() { return &all_; } - const string &to_string() const { return name_; } + const std::string &to_string() const { return name_; } int index() const { return index_; } const MinMax *asMinMax() const; bool matches(const MinMax *min_max) const; @@ -131,7 +129,7 @@ private: std::vector range, std::vector range_index); - const string name_; + const std::string name_; int index_; const std::vector range_; const std::vector range_index_; diff --git a/include/sta/Network.hh b/include/sta/Network.hh index b7c4ae93..113ffe20 100644 --- a/include/sta/Network.hh +++ b/include/sta/Network.hh @@ -35,8 +35,6 @@ namespace sta { -using std::function; - class Report; class PatternMatch; class PinVisitor; @@ -44,8 +42,8 @@ class PinVisitor; typedef Map LibertyLibraryMap; // Link network function returns top level instance. // Return nullptr if link fails. -typedef function LinkNetworkFunc; +typedef std::function LinkNetworkFunc; typedef Map NetDrvrPinsMap; // The Network class defines the network API used by sta. @@ -153,8 +151,8 @@ public: // Filename may return null. virtual const char *filename(const Cell *cell) = 0; // Attributes can be null - virtual string getAttribute(const Cell *cell, - const string &key) const = 0; + virtual std::string getAttribute(const Cell *cell, + const std::string &key) const = 0; // Name can be a simple, bundle, bus, or bus bit name. virtual Port *findPort(const Cell *cell, const char *name) const = 0; @@ -217,8 +215,8 @@ public: const PatternMatch *pattern) const; virtual InstanceSeq findInstancesHierMatching(const Instance *instance, const PatternMatch *pattern) const; - virtual string getAttribute(const Instance *inst, - const string &key) const = 0; + virtual std::string getAttribute(const Instance *inst, + const std::string &key) const = 0; // Hierarchical path name. virtual const char *pathName(const Instance *instance) const; bool pathNameLess(const Instance *inst1, @@ -559,11 +557,11 @@ public: virtual void setIsLeaf(Cell *cell, bool is_leaf) = 0; virtual void setAttribute(Cell *cell, - const string &key, - const string &value) = 0; + const std::string &key, + const std::string &value) = 0; virtual void setAttribute(Instance *instance, - const string &key, - const string &value) = 0; + const std::string &key, + const std::string &value) = 0; virtual Port *makePort(Cell *cell, const char *name) = 0; virtual Port *makeBusPort(Cell *cell, diff --git a/include/sta/Parasitics.hh b/include/sta/Parasitics.hh index d3b46241..18a64da6 100644 --- a/include/sta/Parasitics.hh +++ b/include/sta/Parasitics.hh @@ -314,7 +314,7 @@ public: void setCouplingCapFactor(float factor); private: - string name_; + std::string name_; int index_; int index_max_; float coupling_cap_factor_; diff --git a/include/sta/ParseBus.hh b/include/sta/ParseBus.hh index 64e75304..a7058efd 100644 --- a/include/sta/ParseBus.hh +++ b/include/sta/ParseBus.hh @@ -28,8 +28,6 @@ namespace sta { -using std::string; - // Return true if name is a bus. bool isBusName(const char *name, @@ -51,7 +49,7 @@ parseBusName(const char *name, char escape, // Return values. bool &is_bus, - string &bus_name, + std::string &bus_name, int &index); // Allow multiple different left/right bus brackets. void @@ -61,7 +59,7 @@ parseBusName(const char *name, char escape, // Return values. bool &is_bus, - string &bus_name, + std::string &bus_name, int &index); // Parse a bus range, such as BUS[4:0]. @@ -75,7 +73,7 @@ parseBusName(const char *name, // Return values. bool &is_bus, bool &is_range, - string &bus_name, + std::string &bus_name, int &from, int &to, bool &subscript_wild); @@ -90,13 +88,13 @@ parseBusName(const char *name, // Return values. bool &is_bus, bool &is_range, - string &bus_name, + std::string &bus_name, int &from, int &to, bool &subscript_wild); // Insert escapes before ch1 and ch2 in token. -string +std::string escapeChars(const char *token, const char ch1, const char ch2, diff --git a/include/sta/Path.hh b/include/sta/Path.hh index 762ea987..27444e7a 100644 --- a/include/sta/Path.hh +++ b/include/sta/Path.hh @@ -61,7 +61,7 @@ public: bool is_enum, const StaState *sta); ~Path(); - string to_string(const StaState *sta) const; + std::string to_string(const StaState *sta) const; bool isNull() const; // prev_path null void init(Vertex *vertex, @@ -122,6 +122,8 @@ public: void checkPrevPath(const StaState *sta) const; void checkPrevPaths(const StaState *sta) const; + static Path *vertexPath(const Path *path, + const StaState *sta); static Path *vertexPath(const Path &path, const StaState *sta); static Path *vertexPath(const Vertex *vertex, diff --git a/include/sta/PathAnalysisPt.hh b/include/sta/PathAnalysisPt.hh index 49fd4490..6d6a7e94 100644 --- a/include/sta/PathAnalysisPt.hh +++ b/include/sta/PathAnalysisPt.hh @@ -37,8 +37,6 @@ class MinMax; class DcalcAnalysisPt; class Corner; -using std::string; - class PathAnalysisPt { public: @@ -46,7 +44,7 @@ public: PathAPIndex index, const MinMax *path_min_max, DcalcAnalysisPt *dcalc_ap); - string to_string() const; + std::string to_string() const; Corner *corner() const { return corner_; } PathAPIndex index() const { return index_; } const MinMax *pathMinMax() const { return path_min_max_; } diff --git a/include/sta/PathEnd.hh b/include/sta/PathEnd.hh index 46351593..c41cda50 100644 --- a/include/sta/PathEnd.hh +++ b/include/sta/PathEnd.hh @@ -40,8 +40,6 @@ class RiseFall; class MinMax; class ReportPath; -using std::string; - // PathEnds represent search endpoints that are either unconstrained // or constrained by a timing check, output delay, data check, // or path delay. diff --git a/include/sta/PatternMatch.hh b/include/sta/PatternMatch.hh index fd3aaba0..3531b8a4 100644 --- a/include/sta/PatternMatch.hh +++ b/include/sta/PatternMatch.hh @@ -53,10 +53,10 @@ public: PatternMatch(const char *pattern); PatternMatch(const char *pattern, const PatternMatch *inherit_from); - PatternMatch(const string &pattern, + PatternMatch(const std::string &pattern, const PatternMatch *inherit_from); bool match(const char *str) const; - bool match(const string &str) const; + bool match(const std::string &str) const; bool matchNoCase(const char *str) const; const char *pattern() const { return pattern_; } bool isRegexp() const { return is_regexp_; } diff --git a/include/sta/Property.hh b/include/sta/Property.hh index 3b175c72..cd8eb1e5 100644 --- a/include/sta/Property.hh +++ b/include/sta/Property.hh @@ -34,8 +34,6 @@ namespace sta { -using std::string; - class Sta; // Adding a new property type @@ -58,7 +56,7 @@ public: type_clk, type_clks, type_paths, type_pwr_activity }; PropertyValue(); PropertyValue(const char *value); - PropertyValue(string &value); + PropertyValue(std::string &value); PropertyValue(float value, const Unit *unit); explicit PropertyValue(bool value); diff --git a/include/sta/Report.hh b/include/sta/Report.hh index eb71e39b..7d2aebe9 100644 --- a/include/sta/Report.hh +++ b/include/sta/Report.hh @@ -36,8 +36,6 @@ struct Tcl_Interp; namespace sta { -using std::string; - // Output streams used for printing. // This is a wrapper for all printing. It supports logging output to // a file and redirection of command output to a file. @@ -51,7 +49,7 @@ public: virtual void reportLine(const char *fmt, ...) __attribute__((format (printf, 2, 3))); virtual void reportLineString(const char *line); - virtual void reportLineString(const string &line); + virtual void reportLineString(const std::string &line); virtual void reportBlankLine(); //////////////////////////////////////////////////////////////// @@ -158,7 +156,7 @@ protected: FILE *log_stream_; FILE *redirect_stream_; bool redirect_to_string_; - string redirect_string_; + std::string redirect_string_; // Buffer to support printf style arguments. size_t buffer_size_; char *buffer_; diff --git a/include/sta/Sdc.hh b/include/sta/Sdc.hh index 80c4e823..b402e43a 100644 --- a/include/sta/Sdc.hh +++ b/include/sta/Sdc.hh @@ -62,8 +62,6 @@ class Corner; class ClockPinIterator; class ClockIterator; -using std::vector; - typedef std::pair PinClockPair; class ClockInsertionkLess @@ -733,6 +731,7 @@ public: // combinational loops when dynamic loop breaking is enabled. void makeLoopExceptions(); void makeLoopExceptions(GraphLoop *loop); + void deleteLoopExceptions(); void makeMulticyclePath(ExceptionFrom *from, ExceptionThruSeq *thrus, ExceptionTo *to, @@ -793,54 +792,6 @@ public: const WireloadSelection *wireloadSelection(const MinMax *min_max); void setWireloadSelection(WireloadSelection *selection, const MinMaxAll *min_max); - // Common reconvergent clock pessimism. - // TCL variable sta_crpr_enabled. - bool crprEnabled() const; - void setCrprEnabled(bool enabled); - // TCL variable sta_crpr_mode. - CrprMode crprMode() const; - void setCrprMode(CrprMode mode); - // True when analysis type is on chip variation and crpr is enabled. - bool crprActive() const; - // TCL variable sta_propagate_gated_clock_enable. - // Propagate gated clock enable arrivals. - bool propagateGatedClockEnable() const; - void setPropagateGatedClockEnable(bool enable); - // TCL variable sta_preset_clear_arcs_enabled. - // Enable search through preset/clear arcs. - bool presetClrArcsEnabled() const; - void setPresetClrArcsEnabled(bool enable); - // TCL variable sta_cond_default_arcs_enabled. - // Enable/disable default arcs when conditional arcs exist. - bool condDefaultArcsEnabled() const; - void setCondDefaultArcsEnabled(bool enabled); - bool isDisabledCondDefault(Edge *edge) const; - // TCL variable sta_internal_bidirect_instance_paths_enabled. - // Enable/disable timing from bidirect pins back into the instance. - bool bidirectInstPathsEnabled() const; - void setBidirectInstPathsEnabled(bool enabled); - // TCL variable sta_bidirect_net_paths_enabled. - // Enable/disable timing from bidirect driver pins to their own loads. - bool bidirectNetPathsEnabled() const; - void setBidirectNetPathsEnabled(bool enabled); - // TCL variable sta_recovery_removal_checks_enabled. - bool recoveryRemovalChecksEnabled() const; - void setRecoveryRemovalChecksEnabled(bool enabled); - // TCL variable sta_gated_clock_checks_enabled. - bool gatedClkChecksEnabled() const; - void setGatedClkChecksEnabled(bool enabled); - // TCL variable sta_dynamic_loop_breaking. - bool dynamicLoopBreaking() const; - void setDynamicLoopBreaking(bool enable); - // TCL variable sta_propagate_all_clocks. - bool propagateAllClocks() const; - void setPropagateAllClocks(bool prop); - // TCL var sta_clock_through_tristate_enabled. - bool clkThruTristateEnabled() const; - void setClkThruTristateEnabled(bool enable); - // TCL variable sta_input_port_default_clock. - bool useDefaultArrivalClock(); - void setUseDefaultArrivalClock(bool enable); // STA interface. InputDelaySet *refPinInputDelays(const Pin *ref_pin) const; @@ -1071,7 +1022,6 @@ public: const Pin *drvr, const Pin *load); void ensureClkHpinDisables(); - bool bidirectDrvrSlewFromLoad(const Pin *pin) const; protected: void portMembers(const Port *port, @@ -1214,7 +1164,6 @@ protected: const Pin *loop_prev_pin); void makeLoopExceptionThru(const Pin *pin, ExceptionThruSeq *thrus); - void deleteLoopExceptions(); void deleteConstraints(); InputDelay *findInputDelay(const Pin *pin, const ClockEdge *clk_edge); @@ -1317,7 +1266,6 @@ protected: int clk_index_; // Default clock used for unclocked input arrivals. Clock *default_arrival_clk_; - bool use_default_arrival_clock_; ClockNameMap clock_name_map_; ClockPinMap clock_pin_map_; // Clocks on hierarchical pins are indexed by the load pins. @@ -1371,12 +1319,12 @@ protected: // set_load port // set_fanout_load port // Indexed by corner_index. - vector port_ext_cap_maps_; + std::vector port_ext_cap_maps_; // set_load net // Indexed by corner_index. - vector net_wire_cap_maps_; + std::vector net_wire_cap_maps_; // Indexed by corner_index. - vector drvr_pin_wire_cap_maps_; + std::vector drvr_pin_wire_cap_maps_; NetResistanceMap net_res_map_; PinSet disabled_pins_; PortSet disabled_ports_; @@ -1430,19 +1378,6 @@ protected: Wireload *wireload_[MinMax::index_count]; WireloadMode wireload_mode_; WireloadSelection *wireload_selection_[MinMax::index_count]; - bool crpr_enabled_; - CrprMode crpr_mode_; - bool pocv_enabled_; - bool propagate_gated_clock_enable_; - bool preset_clr_arcs_enabled_; - bool cond_default_arcs_enabled_; - bool bidirect_net_paths_enabled_; - bool bidirect_inst_paths_enabled_; - bool recovery_removal_checks_enabled_; - bool gated_clk_checks_enabled_; - bool clk_thru_tristate_enabled_; - bool dynamic_loop_breaking_; - bool propagate_all_clks_; // Annotations on graph objects that are stored in constraints // rather on the graph itself. diff --git a/include/sta/SdcClass.hh b/include/sta/SdcClass.hh index f6d7c3f7..a6a5a49a 100644 --- a/include/sta/SdcClass.hh +++ b/include/sta/SdcClass.hh @@ -122,8 +122,6 @@ public: class ExceptionPath; typedef Set ExceptionStateSet; -enum class CrprMode { same_pin, same_transition }; - // Constraint applies to clock or data paths. enum class PathClkOrData { clk, data }; diff --git a/include/sta/SdcNetwork.hh b/include/sta/SdcNetwork.hh index 49c58137..fd75063c 100644 --- a/include/sta/SdcNetwork.hh +++ b/include/sta/SdcNetwork.hh @@ -54,8 +54,8 @@ public: const PatternMatch *pattern) const override; const char *name(const Cell *cell) const override; - string getAttribute(const Cell *cell, - const string &key) const override; + std::string getAttribute(const Cell *cell, + const std::string &key) const override; ObjectId id(const Cell *cell) const override; Library *library(const Cell *cell) const override; LibertyCell *libertyCell(Cell *cell) const override; @@ -91,8 +91,8 @@ public: bool hasMembers(const Port *port) const override; ObjectId id(const Instance *instance) const override; - string getAttribute(const Instance *inst, - const string &key) const override; + std::string getAttribute(const Instance *inst, + const std::string &key) const override; Instance *topInstance() const override; Cell *cell(const Instance *instance) const override; Instance *parent(const Instance *instance) const override; diff --git a/include/sta/Search.hh b/include/sta/Search.hh index 8129ae4f..cd2dd9e7 100644 --- a/include/sta/Search.hh +++ b/include/sta/Search.hh @@ -70,7 +70,7 @@ typedef UnorderedSet TagGroupSet; typedef Map VertexSlackMap; typedef Vector VertexSlackMapSeq; typedef Vector WorstSlacksSeq; -typedef vector DelayDblSeq; +typedef std::vector DelayDblSeq; class Search : public StaState { @@ -629,14 +629,14 @@ protected: // Entries in tags_ may be missing where previous filter tags were deleted. TagIndex tag_capacity_; std::atomic tags_; - vector tags_prev_; + std::vector tags_prev_; TagIndex tag_next_; // Holes in tags_ left by deleting filter tags. std::vector tag_free_indices_; std::mutex tag_lock_; TagGroupSet *tag_group_set_; std::atomic tag_groups_; - vector tag_groups_prev_; + std::vector tag_groups_prev_; TagGroupIndex tag_group_next_; // Holes in tag_groups_ left by deleting filter tag groups. std::vector tag_group_free_indices_; @@ -861,11 +861,11 @@ protected: class DynLoopSrchPred { public: - explicit DynLoopSrchPred(TagGroupBldr *tag_bldr); + DynLoopSrchPred(TagGroupBldr *tag_bldr); protected: bool loopEnabled(Edge *edge, - const Sdc *sdc, + bool dynamic_loop_breaking_enabled, const Graph *graph, Search *search); bool hasPendingLoopPaths(Edge *edge, diff --git a/include/sta/SearchClass.hh b/include/sta/SearchClass.hh index 39c516f3..2e304781 100644 --- a/include/sta/SearchClass.hh +++ b/include/sta/SearchClass.hh @@ -119,7 +119,7 @@ typedef UnorderedMap PathIndexMap; typedef Vector SlackSeq; typedef Delay Crpr; typedef Vector PathSeq; -typedef vector ConstPathSeq; +typedef std::vector ConstPathSeq; enum class ReportPathFormat { full, full_clock, diff --git a/include/sta/Sequential.hh b/include/sta/Sequential.hh index 69a89af0..cba09523 100644 --- a/include/sta/Sequential.hh +++ b/include/sta/Sequential.hh @@ -55,10 +55,8 @@ enum class StateInternalValue { class StatetableRow; -using std::vector; - -typedef vector StateInputValues; -typedef vector StateInternalValues; +typedef std::vector StateInputValues; +typedef std::vector StateInternalValues; // Register/Latch class Sequential diff --git a/include/sta/Sta.hh b/include/sta/Sta.hh index 61b0b66e..a346ddd7 100644 --- a/include/sta/Sta.hh +++ b/include/sta/Sta.hh @@ -38,14 +38,12 @@ #include "PowerClass.hh" #include "ArcDelayCalc.hh" #include "CircuitSim.hh" +#include "Variables.hh" struct Tcl_Interp; namespace sta { -using std::string; -using ::Tcl_Interp; - // Don't include headers to minimize dependencies. class MinMax; class MinMaxAll; @@ -436,8 +434,6 @@ public: void removeDisable(TimingArcSet *arc_set); // Edge is disabled by constant. bool isDisabledConstant(Edge *edge); - // Edge is default cond disabled by timing_disable_cond_default_arcs var. - bool isDisabledCondDefault(Edge *edge); // Return a set of constant pins that disabled edge. // Caller owns the returned set. PinSet disabledConstantPins(Edge *edge); @@ -793,61 +789,7 @@ public: bool no_version); // Remove all delay and slew annotations. void removeDelaySlewAnnotations(); - // TCL variable sta_crpr_enabled. - // Common Reconvergent Clock Removal (CRPR). - // Timing check source/target common clock path overlap for search - // with analysis mode on_chip_variation. - bool crprEnabled() const; - void setCrprEnabled(bool enabled); - // TCL variable sta_crpr_mode. - CrprMode crprMode() const; - void setCrprMode(CrprMode mode); - // TCL variable sta_pocv_enabled. - // Parametric on chip variation (statisical sta). - bool pocvEnabled() const; - void setPocvEnabled(bool enabled); - // Number of std deviations from mean to use for normal distributions. - void setSigmaFactor(float factor); - // TCL variable sta_propagate_gated_clock_enable. - // Propagate gated clock enable arrivals. - bool propagateGatedClockEnable() const; - void setPropagateGatedClockEnable(bool enable); - // TCL variable sta_preset_clear_arcs_enabled. - // Enable search through preset/clear arcs. - bool presetClrArcsEnabled() const; - void setPresetClrArcsEnabled(bool enable); - // TCL variable sta_cond_default_arcs_enabled. - // Enable/disable default arcs when conditional arcs exist. - bool condDefaultArcsEnabled() const; - void setCondDefaultArcsEnabled(bool enabled); - // TCL variable sta_internal_bidirect_instance_paths_enabled. - // Enable/disable timing from bidirect pins back into the instance. - bool bidirectInstPathsEnabled() const; - void setBidirectInstPathsEnabled(bool enabled); - // TCL variable sta_bidirect_net_paths_enabled. - // Enable/disable timing from bidirect driver pins to their own loads. - bool bidirectNetPathsEnabled() const; - void setBidirectNetPathsEnabled(bool enabled); - // TCL variable sta_recovery_removal_checks_enabled. - bool recoveryRemovalChecksEnabled() const; - void setRecoveryRemovalChecksEnabled(bool enabled); - // TCL variable sta_gated_clock_checks_enabled. - bool gatedClkChecksEnabled() const; - void setGatedClkChecksEnabled(bool enabled); - // TCL variable sta_dynamic_loop_breaking. - bool dynamicLoopBreaking() const; - void setDynamicLoopBreaking(bool enable); - // TCL variable sta_propagate_all_clocks. - // Clocks defined after sta_propagate_all_clocks is true - // are propagated (existing clocks are not effected). - bool propagateAllClocks() const; - void setPropagateAllClocks(bool prop); - // TCL var sta_clock_through_tristate_enabled. - bool clkThruTristateEnabled() const; - void setClkThruTristateEnabled(bool enable); - // TCL variable sta_input_port_default_clock. - bool useDefaultArrivalClock() const; - void setUseDefaultArrivalClock(bool enable); + virtual CheckErrorSeq &checkTiming(bool no_input_delay, bool no_output_delay, bool reg_multiple_clks, @@ -1178,7 +1120,9 @@ public: bool includes_pin_caps, const ParasiticAnalysisPt *ap); + //////////////////////////////////////////////////////////////// // TCL network edit function support. + virtual Instance *makeInstance(const char *name, LibertyCell *cell, Instance *parent); @@ -1322,10 +1266,71 @@ public: const char *gnd_name, CircuitSim ckt_sim); + //////////////////////////////////////////////////////////////// + // TCL Variables + + // TCL variable sta_crpr_enabled. + // Common Reconvergent Clock Removal (CRPR). + // Timing check source/target common clock path overlap for search + // with analysis mode on_chip_variation. + bool crprEnabled() const; + void setCrprEnabled(bool enabled); + // TCL variable sta_crpr_mode. + CrprMode crprMode() const; + void setCrprMode(CrprMode mode); + // TCL variable sta_pocv_enabled. + // Parametric on chip variation (statisical sta). + bool pocvEnabled() const; + void setPocvEnabled(bool enabled); + // Number of std deviations from mean to use for normal distributions. + void setSigmaFactor(float factor); + // TCL variable sta_propagate_gated_clock_enable. + // Propagate gated clock enable arrivals. + bool propagateGatedClockEnable() const; + void setPropagateGatedClockEnable(bool enable); + // TCL variable sta_preset_clear_arcs_enabled. + // Enable search through preset/clear arcs. + bool presetClrArcsEnabled() const; + void setPresetClrArcsEnabled(bool enable); + // TCL variable sta_cond_default_arcs_enabled. + // Enable/disable default arcs when conditional arcs exist. + bool condDefaultArcsEnabled() const; + void setCondDefaultArcsEnabled(bool enabled); + // TCL variable sta_internal_bidirect_instance_paths_enabled. + // Enable/disable timing from bidirect pins back into the instance. + bool bidirectInstPathsEnabled() const; + void setBidirectInstPathsEnabled(bool enabled); + // TCL variable sta_bidirect_net_paths_enabled. + // Enable/disable timing from bidirect driver pins to their own loads. + bool bidirectNetPathsEnabled() const; + void setBidirectNetPathsEnabled(bool enabled); + // TCL variable sta_recovery_removal_checks_enabled. + bool recoveryRemovalChecksEnabled() const; + void setRecoveryRemovalChecksEnabled(bool enabled); + // TCL variable sta_gated_clock_checks_enabled. + bool gatedClkChecksEnabled() const; + void setGatedClkChecksEnabled(bool enabled); + // TCL variable sta_dynamic_loop_breaking. + bool dynamicLoopBreaking() const; + void setDynamicLoopBreaking(bool enable); + // TCL variable sta_propagate_all_clocks. + // Clocks defined after sta_propagate_all_clocks is true + // are propagated (existing clocks are not effected). + bool propagateAllClocks() const; + void setPropagateAllClocks(bool prop); + // TCL var sta_clock_through_tristate_enabled. + bool clkThruTristateEnabled() const; + void setClkThruTristateEnabled(bool enable); + // TCL variable sta_input_port_default_clock. + bool useDefaultArrivalClock() const; + void setUseDefaultArrivalClock(bool enable); + //////////////////////////////////////////////////////////////// + protected: // Default constructors that are called by makeComponents in the Sta // constructor. These can be redefined by a derived class to // specialize the sta components. + virtual void makeVariables(); virtual void makeReport(); virtual void makeDebug(); virtual void makeUnits(); diff --git a/include/sta/StaState.hh b/include/sta/StaState.hh index 111bced3..cce271be 100644 --- a/include/sta/StaState.hh +++ b/include/sta/StaState.hh @@ -35,6 +35,7 @@ class NetworkReader; class Sdc; class Corners; class Graph; +class Edge; class Levelize; class Sim; class Search; @@ -44,6 +45,7 @@ class GraphDelayCalc; class Latches; class ClkNetwork; class DispatchQueue; +class Variables; // Most STA components use functionality in other components. // This class simplifies the process of copying pointers to the @@ -54,7 +56,7 @@ class StaState public: // Make an empty state. StaState(); - explicit StaState(const StaState *sta); + StaState(const StaState *sta); // Copy the state from sta. This is virtual so that a component // can notify sub-components. virtual void copyState(const StaState *sta); @@ -102,8 +104,12 @@ public: ClkNetwork *clkNetwork() { return clk_network_; } ClkNetwork *clkNetwork() const { return clk_network_; } unsigned threadCount() const { return thread_count_; } - bool pocvEnabled() const { return pocv_enabled_; } float sigmaFactor() const { return sigma_factor_; } + bool crprActive() const; + Variables *variables() { return variables_; } + const Variables *variables() const { return variables_; } + // Edge is default cond disabled by timing_disable_cond_default_arcs var. + bool isDisabledCondDefault(Edge *edge) const; protected: Report *report_; @@ -124,9 +130,9 @@ protected: Search *search_; Latches *latches_; ClkNetwork *clk_network_; + Variables *variables_; int thread_count_; DispatchQueue *dispatch_queue_; - bool pocv_enabled_; float sigma_factor_; }; diff --git a/include/sta/StringSet.hh b/include/sta/StringSet.hh index 7dc66736..ae643e35 100644 --- a/include/sta/StringSet.hh +++ b/include/sta/StringSet.hh @@ -31,7 +31,7 @@ namespace sta { typedef Set StringSet; -typedef std::set StdStringSet; +typedef std::set StdStringSet; void deleteContents(StringSet *strings); diff --git a/include/sta/StringUtil.hh b/include/sta/StringUtil.hh index ddcdb606..c858df5f 100644 --- a/include/sta/StringUtil.hh +++ b/include/sta/StringUtil.hh @@ -33,8 +33,6 @@ namespace sta { -using std::string; - inline bool stringEq(const char *str1, const char *str2) @@ -167,19 +165,19 @@ isDigits(const char *str); char * stringPrint(const char *fmt, ...) __attribute__((format (printf, 1, 2))); -string +std::string stdstrPrint(const char *fmt, ...) __attribute__((format (printf, 1, 2))); char * stringPrintArgs(const char *fmt, va_list args); void -stringPrint(string &str, +stringPrint(std::string &str, const char *fmt, ...) __attribute__((format (printf, 2, 3))); // Formated append to std::string. void -stringAppend(string &str, +stringAppend(std::string &str, const char *fmt, ...) __attribute__((format (printf, 2, 3))); @@ -191,7 +189,7 @@ stringPrintTmp(const char *fmt, char * makeTmpString(size_t length); char * -makeTmpString(string &str); +makeTmpString(std::string &str); bool isTmpString(const char *str); @@ -199,13 +197,13 @@ isTmpString(const char *str); // Trim right spaces. void -trimRight(string &str); +trimRight(std::string &str); -typedef Vector StringVector; +typedef Vector StringVector; void -split(const string &text, - const string &delims, +split(const std::string &text, + const std::string &delims, // Return values. StringVector &tokens); diff --git a/include/sta/TableModel.hh b/include/sta/TableModel.hh index 5834b44a..afcebcea 100644 --- a/include/sta/TableModel.hh +++ b/include/sta/TableModel.hh @@ -35,8 +35,6 @@ namespace sta { -using std::string; - class Unit; class Units; class Report; diff --git a/include/sta/TimingRole.hh b/include/sta/TimingRole.hh index bc6cf44b..b9456cc1 100644 --- a/include/sta/TimingRole.hh +++ b/include/sta/TimingRole.hh @@ -33,7 +33,7 @@ namespace sta { class TimingRole; -typedef std::map TimingRoleMap; +typedef std::map TimingRoleMap; class TimingRole { @@ -68,7 +68,7 @@ public: static const TimingRole *nonSeqHold() { return &non_seq_hold_; } static const TimingRole *clockTreePathMin() { return &clock_tree_path_min_; } static const TimingRole *clockTreePathMax() { return &clock_tree_path_max_; } - const string &to_string() const { return name_; } + const std::string &to_string() const { return name_; } int index() const { return index_; } bool isWire() const; bool isTimingCheck() const { return is_timing_check_; } @@ -101,7 +101,7 @@ private: const TimingRole *generic_role, int index); - const string name_; + const std::string name_; bool is_timing_check_; bool is_sdf_iopath_; bool is_non_seq_check_; diff --git a/include/sta/Transition.hh b/include/sta/Transition.hh index 87220d3d..c7a490a8 100644 --- a/include/sta/Transition.hh +++ b/include/sta/Transition.hh @@ -37,7 +37,7 @@ class Transition; class RiseFall; class RiseFallBoth; -typedef Map TransitionMap; +typedef Map TransitionMap; // Rise/fall transition. class RiseFall @@ -48,7 +48,7 @@ public: static const RiseFall *fall() { return &fall_; } static int riseIndex() { return rise_.sdf_triple_index_; } static int fallIndex() { return fall_.sdf_triple_index_; } - const string &to_string() const { return short_name_; } + const std::string &to_string() const { return short_name_; } const char *name() const { return name_.c_str(); } const char *shortName() const { return short_name_.c_str(); } int index() const { return sdf_triple_index_; } @@ -75,8 +75,8 @@ protected: const char *short_name, int sdf_triple_index); - const string name_; - const string short_name_; + const std::string name_; + const std::string short_name_; const int sdf_triple_index_; static const RiseFall rise_; @@ -93,7 +93,7 @@ public: static const RiseFallBoth *rise() { return &rise_; } static const RiseFallBoth *fall() { return &fall_; } static const RiseFallBoth *riseFall() { return &rise_fall_; } - const string &to_string() const { return short_name_; } + const std::string &to_string() const { return short_name_; } const char *name() const { return name_.c_str(); } const char *shortName() const { return short_name_.c_str(); } int index() const { return sdf_triple_index_; } @@ -119,8 +119,8 @@ protected: std::vector range, std::vector range_index); - const string name_; - const string short_name_; + const std::string name_; + const std::string short_name_; const int sdf_triple_index_; const RiseFall *as_rise_fall_; const std::vector range_; @@ -150,7 +150,7 @@ public: static const Transition *trZX() { return &tr_ZX_; } // Matches rise and fall. static const Transition *riseFall() { return &rise_fall_; } - const string &to_string() const { return name_; } + const std::string &to_string() const { return name_; } // As initial/final value pair. const char *asInitFinalString() const { return init_final_.c_str(); } int sdfTripleIndex() const { return sdf_triple_index_; } @@ -168,8 +168,8 @@ private: const RiseFall *as_rise_fall, int sdf_triple_index); - const string name_; - const string init_final_; + const std::string name_; + const std::string init_final_; const RiseFall *as_rise_fall_; const int sdf_triple_index_; diff --git a/include/sta/Units.hh b/include/sta/Units.hh index 675d7e65..ffee1840 100644 --- a/include/sta/Units.hh +++ b/include/sta/Units.hh @@ -28,8 +28,6 @@ namespace sta { -using std::string; - class Unit { public: @@ -62,8 +60,8 @@ private: void setScaledSuffix(); float scale_; // multiplier from user units to internal units - string suffix_; // print suffix - string scaled_suffix_; + std::string suffix_; // print suffix + std::string scaled_suffix_; int digits_; // print digits (after decimal pt) }; diff --git a/include/sta/Variables.hh b/include/sta/Variables.hh new file mode 100644 index 00000000..696347a1 --- /dev/null +++ b/include/sta/Variables.hh @@ -0,0 +1,98 @@ +// OpenSTA, Static Timing Analyzer +// Copyright (c) 2025, Parallax Software, Inc. +// +// This program is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see . +// +// The origin of this software must not be misrepresented; you must not +// claim that you wrote the original software. +// +// Altered source versions must be plainly marked as such, and must not be +// misrepresented as being the original software. +// +// This notice may not be removed or altered from any source distribution. + +#pragma once + +namespace sta { + +enum class CrprMode { same_pin, same_transition }; + +// TCL Variables +class Variables +{ +public: + Variables(); + // TCL variable sta_propagate_gated_clock_enable. + bool crprEnabled() const { return crpr_enabled_; } + void setCrprEnabled(bool enabled); + CrprMode crprMode() const { return crpr_mode_; } + void setCrprMode(CrprMode mode); + // Propagate gated clock enable arrivals. + bool propagateGatedClockEnable() const { return propagate_gated_clock_enable_; } + void setPropagateGatedClockEnable(bool enable); + // TCL variable sta_preset_clear_arcs_enabled. + // Enable search through preset/clear arcs. + bool presetClrArcsEnabled() const { return preset_clr_arcs_enabled_; } + void setPresetClrArcsEnabled(bool enable); + // TCL variable sta_cond_default_arcs_enabled. + // Enable/disable default arcs when conditional arcs exist. + bool condDefaultArcsEnabled() const { return cond_default_arcs_enabled_; } + void setCondDefaultArcsEnabled(bool enabled); + // TCL variable sta_internal_bidirect_instance_paths_enabled. + // Enable/disable timing from bidirect pins back into the instance. + bool bidirectInstPathsEnabled() const { return bidirect_inst_paths_enabled_; } + void setBidirectInstPathsEnabled(bool enabled); + // TCL variable sta_bidirect_net_paths_enabled. + // Enable/disable timing from bidirect driver pins to their own loads. + bool bidirectNetPathsEnabled() const { return bidirect_net_paths_enabled_; } + void setBidirectNetPathsEnabled(bool enabled); + // TCL variable sta_recovery_removal_checks_enabled. + bool recoveryRemovalChecksEnabled() const { return recovery_removal_checks_enabled_; } + void setRecoveryRemovalChecksEnabled(bool enabled); + // TCL variable sta_gated_clock_checks_enabled. + bool gatedClkChecksEnabled() const { return gated_clk_checks_enabled_; } + void setGatedClkChecksEnabled(bool enabled); + // TCL variable sta_dynamic_loop_breaking. + bool dynamicLoopBreaking() const { return dynamic_loop_breaking_; } + void setDynamicLoopBreaking(bool enable); + // TCL variable sta_propagate_all_clocks. + bool propagateAllClocks() const { return propagate_all_clks_; } + void setPropagateAllClocks(bool prop); + // TCL var sta_clock_through_tristate_enabled. + bool clkThruTristateEnabled() const { return clk_thru_tristate_enabled_; } + void setClkThruTristateEnabled(bool enable); + // TCL variable sta_input_port_default_clock. + bool useDefaultArrivalClock() { return use_default_arrival_clock_; } + void setUseDefaultArrivalClock(bool enable); + bool pocvEnabled() const { return pocv_enabled_; } + void setPocvEnabled(bool enabled); + +private: + bool crpr_enabled_; + CrprMode crpr_mode_; + bool propagate_gated_clock_enable_; + bool preset_clr_arcs_enabled_; + bool cond_default_arcs_enabled_; + bool bidirect_net_paths_enabled_; + bool bidirect_inst_paths_enabled_; + bool recovery_removal_checks_enabled_; + bool gated_clk_checks_enabled_; + bool clk_thru_tristate_enabled_; + bool dynamic_loop_breaking_; + bool propagate_all_clks_; + bool use_default_arrival_clock_; + bool pocv_enabled_; +}; + +} // namespace diff --git a/include/sta/VerilogNamespace.hh b/include/sta/VerilogNamespace.hh index d793ef6a..835bd45e 100644 --- a/include/sta/VerilogNamespace.hh +++ b/include/sta/VerilogNamespace.hh @@ -28,24 +28,22 @@ namespace sta { -using std::string; - -string +std::string cellVerilogName(const char *sta_name); -string +std::string instanceVerilogName(const char *sta_name); -string +std::string netVerilogName(const char *sta_name); -string +std::string portVerilogName(const char *sta_name); -string -moduleVerilogToSta(const string *sta_name); -string -instanceVerilogToSta(const string *sta_name); -string -netVerilogToSta(const string *sta_name); -string -portVerilogToSta(const string *sta_name); +std::string +moduleVerilogToSta(const std::string *sta_name); +std::string +instanceVerilogToSta(const std::string *sta_name); +std::string +netVerilogToSta(const std::string *sta_name); +std::string +portVerilogToSta(const std::string *sta_name); } // namespace diff --git a/include/sta/VerilogReader.hh b/include/sta/VerilogReader.hh index 2482dbe0..dc76ccc6 100644 --- a/include/sta/VerilogReader.hh +++ b/include/sta/VerilogReader.hh @@ -70,10 +70,6 @@ typedef Vector VerilogAttrStmtSeq; typedef Vector VerilogAttrEntrySeq; typedef Vector VerilogErrorSeq; -using std::string; -using std::vector; -using std::set; - class VerilogReader { public: @@ -81,12 +77,12 @@ public: ~VerilogReader(); bool read(const char *filename); - void makeModule(const string *module_name, + void makeModule(const std::string *module_name, VerilogNetSeq *ports, VerilogStmtSeq *stmts, VerilogAttrStmtSeq *attr_stmts, int line); - void makeModule(const string *module_name, + void makeModule(const std::string *module_name, VerilogStmtSeq *port_dcls, VerilogStmtSeq *stmts, VerilogAttrStmtSeq *attr_stmts, @@ -99,7 +95,7 @@ public: VerilogDclArg *arg, VerilogAttrStmtSeq *attr_stmts, int line); - VerilogDclArg *makeDclArg(const string *net_name); + VerilogDclArg *makeDclArg(const std::string *net_name); VerilogDclArg*makeDclArg(VerilogAssign *assign); VerilogDclBus *makeDclBus(PortDirection *dir, int from_index, @@ -113,36 +109,36 @@ public: VerilogDclArgSeq *args, VerilogAttrStmtSeq *attr_stmts, int line); - VerilogInst *makeModuleInst(const string *module_name, - const string *inst_name, + VerilogInst *makeModuleInst(const std::string *module_name, + const std::string *inst_name, VerilogNetSeq *pins, VerilogAttrStmtSeq *attr_stmts, const int line); VerilogAssign *makeAssign(VerilogNet *lhs, VerilogNet *rhs, int line); - VerilogNetScalar *makeNetScalar(const string *name); - VerilogNetPortRef *makeNetNamedPortRefScalarNet(const string *port_vname); - VerilogNetPortRef *makeNetNamedPortRefScalarNet(const string *port_name, - const string *net_name); - VerilogNetPortRef *makeNetNamedPortRefBitSelect(const string *port_name, - const string *bus_name, + VerilogNetScalar *makeNetScalar(const std::string *name); + VerilogNetPortRef *makeNetNamedPortRefScalarNet(const std::string *port_vname); + VerilogNetPortRef *makeNetNamedPortRefScalarNet(const std::string *port_name, + const std::string *net_name); + VerilogNetPortRef *makeNetNamedPortRefBitSelect(const std::string *port_name, + const std::string *bus_name, int index); - VerilogNetPortRef *makeNetNamedPortRefScalar(const string *port_name, + VerilogNetPortRef *makeNetNamedPortRefScalar(const std::string *port_name, VerilogNet *net); - VerilogNetPortRef *makeNetNamedPortRefBit(const string *port_name, + VerilogNetPortRef *makeNetNamedPortRefBit(const std::string *port_name, int index, VerilogNet *net); - VerilogNetPortRef *makeNetNamedPortRefPart(const string *port_name, + VerilogNetPortRef *makeNetNamedPortRefPart(const std::string *port_name, int from_index, int to_index, VerilogNet *net); VerilogNetConcat *makeNetConcat(VerilogNetSeq *nets); - VerilogNetConstant *makeNetConstant(const string *constant, + VerilogNetConstant *makeNetConstant(const std::string *constant, int line); - VerilogNetBitSelect *makeNetBitSelect(const string *name, + VerilogNetBitSelect *makeNetBitSelect(const std::string *name, int index); - VerilogNetPartSelect *makeNetPartSelect(const string *name, + VerilogNetPartSelect *makeNetPartSelect(const std::string *name, int from_index, int to_index); VerilogModule *module(Cell *cell); @@ -160,11 +156,11 @@ public: const char *filename, int line, const char *fmt, ...); - const string &zeroNetName() const { return zero_net_name_; } - const string &oneNetName() const { return one_net_name_; } + const std::string &zeroNetName() const { return zero_net_name_; } + const std::string &oneNetName() const { return one_net_name_; } void deleteModules(); void reportStmtCounts(); - const string &constant10Max() const { return constant10_max_; } + const std::string &constant10Max() const { return constant10_max_; } protected: void init(const char *filename); @@ -173,13 +169,13 @@ protected: VerilogNetSeq *ports); Port *makeCellPort(Cell *cell, VerilogModule *module, - const string &port_name); + const std::string &port_name); void makeNamedPortRefCellPorts(Cell *cell, VerilogModule *module, VerilogNet *mod_port, StdStringSet &port_names); void checkModuleDcls(VerilogModule *module, - set &port_names); + std::set &port_names); void makeModuleInstBody(VerilogModule *module, Instance *inst, VerilogBindingTbl *bindings, @@ -230,7 +226,7 @@ protected: bool is_leaf); void makeInstPin(Instance *inst, Port *port, - const string &net_name, + const std::string &net_name, VerilogBindingTbl *bindings, Instance *parent, VerilogBindingTbl *parent_bindings, @@ -259,7 +255,7 @@ protected: bool hasScalarNamedPortRefs(LibertyCell *liberty_cell, VerilogNetSeq *pins); - string filename_; + std::string filename_; Report *report_; Debug *debug_; NetworkReader *network_; @@ -268,9 +264,9 @@ protected: int black_box_index_; VerilogModuleMap module_map_; VerilogErrorSeq link_errors_; - const string zero_net_name_; - const string one_net_name_; - string constant10_max_; + const std::string zero_net_name_; + const std::string one_net_name_; + std::string constant10_max_; ViewType *view_type_; bool report_stmt_stats_; int module_count_; diff --git a/liberty/FuncExpr.cc b/liberty/FuncExpr.cc index be095ac7..91139a44 100644 --- a/liberty/FuncExpr.cc +++ b/liberty/FuncExpr.cc @@ -30,6 +30,8 @@ namespace sta { +using std::string; + FuncExpr * FuncExpr::makePort(LibertyPort *port) { diff --git a/liberty/LibExprParse.yy b/liberty/LibExprParse.yy index 336e0811..fe8f7e76 100644 --- a/liberty/LibExprParse.yy +++ b/liberty/LibExprParse.yy @@ -37,7 +37,7 @@ #pragma GCC diagnostic ignored "-Wunused-but-set-variable" void -sta::LibExprParse::error(const string &msg) +sta::LibExprParse::error(const std::string &msg) { reader->parseError(msg.c_str()); } diff --git a/liberty/LibExprReader.cc b/liberty/LibExprReader.cc index 232202a8..f4b873c2 100644 --- a/liberty/LibExprReader.cc +++ b/liberty/LibExprReader.cc @@ -42,7 +42,7 @@ parseFuncExpr(const char *func, Report *report) { if (func != nullptr && func[0] != '\0') { - string func1(func); + std::string func1(func); std::istringstream stream(func); LibExprReader reader(func, cell, error_msg, report); LibExprScanner scanner(stream); diff --git a/liberty/LibExprScanner.hh b/liberty/LibExprScanner.hh index 735abfe2..f3ec9cf1 100644 --- a/liberty/LibExprScanner.hh +++ b/liberty/LibExprScanner.hh @@ -36,8 +36,6 @@ namespace sta { -using std::string; - class Report; class LibExprParse; @@ -56,7 +54,7 @@ public: private: Report *report_; - string token_; + std::string token_; }; } // namespace diff --git a/liberty/LibertyParse.yy b/liberty/LibertyParse.yy index 64aeb95f..7cc067e3 100644 --- a/liberty/LibertyParse.yy +++ b/liberty/LibertyParse.yy @@ -39,7 +39,7 @@ void sta::LibertyParse::error(const location_type &loc, - const string &msg) + const std::string &msg) { reader->report()->fileError(164, reader->filename().c_str(), loc.begin.line, "%s", msg.c_str()); diff --git a/liberty/LibertyParser.cc b/liberty/LibertyParser.cc index 9bd82954..f1eddb1b 100644 --- a/liberty/LibertyParser.cc +++ b/liberty/LibertyParser.cc @@ -36,6 +36,8 @@ namespace sta { +using std::string; + void parseLibertyFile(const char *filename, LibertyGroupVisitor *library_visitor, diff --git a/liberty/LibertyParser.hh b/liberty/LibertyParser.hh index 17d31700..c1a9ec46 100644 --- a/liberty/LibertyParser.hh +++ b/liberty/LibertyParser.hh @@ -48,11 +48,11 @@ class LibertyScanner; typedef Vector LibertyStmtSeq; typedef Vector LibertyGroupSeq; typedef Vector LibertyAttrSeq; -typedef Map LibertyAttrMap; -typedef Map LibertyDefineMap; +typedef Map LibertyAttrMap; +typedef Map LibertyDefineMap; typedef Vector LibertyAttrValueSeq; -typedef Map LibertyVariableMap; -typedef MapLibertyGroupVisitorMap; +typedef Map LibertyVariableMap; +typedef MapLibertyGroupVisitorMap; typedef LibertyAttrValueSeq::Iterator LibertyAttrValueIterator; typedef Vector LibertyGroupSeq; @@ -67,8 +67,8 @@ public: LibertyParser(const char *filename, LibertyGroupVisitor *library_visitor, Report *report); - const string &filename() const { return filename_; } - void setFilename(const string &filename); + const std::string &filename() const { return filename_; } + void setFilename(const std::string &filename); Report *report() const { return report_; } LibertyStmt *makeDefine(LibertyAttrValueSeq *values, int line); @@ -93,7 +93,7 @@ public: int line); private: - string filename_; + std::string filename_; LibertyGroupVisitor *group_visitor_; Report *report_; LibertyGroupSeq group_stack_; @@ -143,7 +143,7 @@ public: protected: void parseNames(LibertyAttrValueSeq *values); - string type_; + std::string type_; LibertyAttrValueSeq *params_; LibertyAttrSeq *attrs_; LibertyAttrMap *attr_map_; @@ -177,7 +177,7 @@ public: virtual LibertyAttrValue *firstValue() = 0; protected: - string name_; + std::string name_; }; // Abstract base class for simple attributes. @@ -239,7 +239,7 @@ public: virtual const char *stringValue(); private: - string value_; + std::string value_; }; class LibertyFloatAttrValue : public LibertyAttrValue @@ -272,7 +272,7 @@ public: LibertyAttrType valueType() const { return value_type_; } private: - string name_; + std::string name_; LibertyGroupType group_type_; LibertyAttrType value_type_; }; @@ -292,7 +292,7 @@ public: float value() const { return value_; } private: - string var_; + std::string var_; float value_; }; diff --git a/liberty/LibertyReader.cc b/liberty/LibertyReader.cc index 0ff9257d..e41b1d7d 100644 --- a/liberty/LibertyReader.cc +++ b/liberty/LibertyReader.cc @@ -2775,6 +2775,7 @@ LibertyReader::endVector(LibertyGroup *group) if (!reference_time_exists_) libWarn(1224, group->line(), "vector reference_time not found."); reference_time_exists_ = false; + tbl_template_ = nullptr; } } diff --git a/liberty/LibertyReaderPvt.hh b/liberty/LibertyReaderPvt.hh index b546758f..8fbce9dc 100644 --- a/liberty/LibertyReaderPvt.hh +++ b/liberty/LibertyReaderPvt.hh @@ -60,8 +60,6 @@ class TimingArcBuilder; class LibertyAttr; class OutputWaveform; -using std::vector; - typedef void (LibertyReader::*LibraryAttrVisitor)(LibertyAttr *attr); typedef void (LibertyReader::*LibraryGroupVisitor)(LibertyGroup *group); typedef Map LibraryAttrMap; @@ -74,7 +72,7 @@ typedef Vector InternalPowerGroupSeq; typedef Vector LeakagePowerGroupSeq; typedef void (LibertyPort::*LibertyPortBoolSetter)(bool value); typedef Vector OutputWaveformSeq; -typedef vector StdStringSeq; +typedef std::vector StdStringSeq; class LibertyReader : public LibertyGroupVisitor { diff --git a/liberty/LibertyScanner.hh b/liberty/LibertyScanner.hh index 93131d1e..c53d3f88 100644 --- a/liberty/LibertyScanner.hh +++ b/liberty/LibertyScanner.hh @@ -61,13 +61,13 @@ private: void error(const char *msg); std::istream *stream_; - string filename_; + std::string filename_; LibertyParser *reader_; Report *report_; - string token_; + std::string token_; // Previous lex state for include files. - string filename_prev_; + std::string filename_prev_; std::istream *stream_prev_; }; diff --git a/network/ConcreteLibrary.cc b/network/ConcreteLibrary.cc index fb52df22..ec897b1e 100644 --- a/network/ConcreteLibrary.cc +++ b/network/ConcreteLibrary.cc @@ -34,6 +34,7 @@ namespace sta { +using std::string; using std::map; using std::min; using std::max; diff --git a/network/ConcreteNetwork.cc b/network/ConcreteNetwork.cc index 8123f88e..ed9c5d6c 100644 --- a/network/ConcreteNetwork.cc +++ b/network/ConcreteNetwork.cc @@ -33,6 +33,8 @@ namespace sta { +using std::string; + static void makeChildNetwork(Instance *proto, Instance *parent, diff --git a/network/Network.cc b/network/Network.cc index 40d70be6..d80b21ef 100644 --- a/network/Network.cc +++ b/network/Network.cc @@ -34,6 +34,8 @@ namespace sta { +using std::string; + Network::Network() : default_liberty_(nullptr), divider_('/'), diff --git a/network/SdcNetwork.cc b/network/SdcNetwork.cc index 6e9275c0..c21cab50 100644 --- a/network/SdcNetwork.cc +++ b/network/SdcNetwork.cc @@ -30,6 +30,7 @@ namespace sta { +using std::string; using std::to_string; static string diff --git a/network/VerilogNamespace.cc b/network/VerilogNamespace.cc index a20cdd23..94cc2f3f 100644 --- a/network/VerilogNamespace.cc +++ b/network/VerilogNamespace.cc @@ -31,6 +31,8 @@ namespace sta { +using std::string; + constexpr char verilog_escape = '\\'; static string diff --git a/parasitics/SpefParse.yy b/parasitics/SpefParse.yy index aca13ade..b8fbb0c2 100755 --- a/parasitics/SpefParse.yy +++ b/parasitics/SpefParse.yy @@ -39,7 +39,7 @@ void sta::SpefParse::error(const location_type &loc, - const string &msg) + const std::string &msg) { reader->report()->fileError(164,reader->filename(), loc.begin.line,"%s",msg.c_str()); diff --git a/parasitics/SpefReaderPvt.hh b/parasitics/SpefReaderPvt.hh index 2337a76c..033a3431 100644 --- a/parasitics/SpefReaderPvt.hh +++ b/parasitics/SpefReaderPvt.hh @@ -41,9 +41,7 @@ class SpefTriple; class Corner; class SpefScanner; -using std::string; - -typedef std::map SpefNameMap; +typedef std::map SpefNameMap; class SpefReader : public StaState { diff --git a/parasitics/SpefScanner.hh b/parasitics/SpefScanner.hh index 5c607749..eb59d16f 100644 --- a/parasitics/SpefScanner.hh +++ b/parasitics/SpefScanner.hh @@ -41,7 +41,7 @@ class SpefScanner : public SpefFlexLexer { public: SpefScanner(std::istream *stream, - const string &filename, + const std::string &filename, SpefReader *reader, Report *report); virtual ~SpefScanner() {} @@ -58,10 +58,10 @@ public: using FlexLexer::yylex; private: - string filename_; + std::string filename_; SpefReader *reader_; Report *report_; - string token_; + std::string token_; }; } // namespace diff --git a/power/Power.cc b/power/Power.cc index a0981adb..b66681e1 100644 --- a/power/Power.cc +++ b/power/Power.cc @@ -74,6 +74,8 @@ using std::abs; using std::max; using std::min; using std::isnormal; +using std::vector; +using std::map; static bool isPositiveUnate(const LibertyCell *cell, @@ -942,7 +944,7 @@ Power::getMinRfSlew(const Pin *pin) if (delayGreater(slew, mm_slew, min_max, this)) mm_slew = slew; } - return mm_slew; + return delayAsFloat(mm_slew); } return 0.0; } diff --git a/power/SaifParse.yy b/power/SaifParse.yy index 03076627..0cae9d63 100644 --- a/power/SaifParse.yy +++ b/power/SaifParse.yy @@ -40,7 +40,7 @@ void sta::SaifParse::error(const location_type &loc, - const string &msg) + const std::string &msg) { reader->report()->fileError(169,reader->filename(),loc.begin.line,"%s",msg.c_str()); } diff --git a/power/SaifReader.cc b/power/SaifReader.cc index 2e717799..54ea69fc 100644 --- a/power/SaifReader.cc +++ b/power/SaifReader.cc @@ -131,7 +131,7 @@ SaifReader::instancePush(const char *instance_name) bool first = true; for (string &inst : saif_scope_) { if (!first) - saif_scope += network_->pathDivider(); + saif_scope += sdc_network_->pathDivider(); saif_scope += inst; first = false; } @@ -140,8 +140,8 @@ SaifReader::instancePush(const char *instance_name) } else { // Inside annotation scope. - Instance *parent = path_.empty() ? network_->topInstance() : path_.back(); - Instance *child = network_->findChild(parent, instance_name); + Instance *parent = path_.empty() ? sdc_network_->topInstance() : path_.back(); + Instance *child = sdc_network_->findChild(parent, instance_name); path_.push_back(child); } stringDelete(instance_name); @@ -163,7 +163,7 @@ SaifReader::setNetDurations(const char *net_name, SaifStateDurations &durations) { if (in_scope_level_ > 0) { - Instance *parent = path_.empty() ? network_->topInstance() : path_.back(); + Instance *parent = path_.empty() ? sdc_network_->topInstance() : path_.back(); if (parent) { string unescaped_name = unescaped(net_name); const Pin *pin = sdc_network_->findPin(parent, unescaped_name.c_str()); @@ -196,9 +196,7 @@ SaifReader::unescaped(const char *token) string unescaped; for (const char *t = token; *t; t++) { char ch = *t; - if (ch == escape_) - unescaped += *(t+1); - else + if (ch != escape_) // Just the normal noises. unescaped += ch; } diff --git a/power/SaifReaderPvt.hh b/power/SaifReaderPvt.hh index c640dfcb..bcc183a9 100644 --- a/power/SaifReaderPvt.hh +++ b/power/SaifReaderPvt.hh @@ -45,9 +45,6 @@ class Sta; class Power; class SaifScanner; -using std::vector; -using std::string; - enum class SaifState { T0, T1, TX, TZ, TB, TC, IG }; typedef std::array(SaifState::IG)+1> SaifStateDurations; @@ -71,7 +68,7 @@ public: const char *filename() { return filename_; } private: - string unescaped(const char *token); + std::string unescaped(const char *token); const char *filename_; const char *scope_; // Divider delimited scope to begin annotation. @@ -81,9 +78,9 @@ private: double timescale_; int64_t duration_; - vector saif_scope_; // Scope during parsing. + std::vector saif_scope_; // Scope during parsing. size_t in_scope_level_; - vector path_; // Path within scope. + std::vector path_; // Path within scope. std::set annotated_pins_; Power *power_; }; diff --git a/power/SaifScanner.hh b/power/SaifScanner.hh index f4d4f486..2e7e6dcb 100644 --- a/power/SaifScanner.hh +++ b/power/SaifScanner.hh @@ -41,7 +41,7 @@ class SaifScanner : public SaifFlexLexer { public: SaifScanner(std::istream *stream, - const string &filename, + const std::string &filename, SaifReader *reader, Report *report); virtual ~SaifScanner() {} @@ -57,10 +57,10 @@ public: using FlexLexer::yylex; private: - string filename_; + std::string filename_; SaifReader *reader_; Report *report_; - string token_; + std::string token_; }; } // namespace diff --git a/power/VcdParse.cc b/power/VcdParse.cc index 7857eff5..04861237 100644 --- a/power/VcdParse.cc +++ b/power/VcdParse.cc @@ -34,6 +34,8 @@ namespace sta { +using std::vector; +using std::string; using std::isspace; // Very imprecise syntax definition @@ -52,7 +54,7 @@ VcdParse::read(const char *filename, reader_ = reader; file_line_ = 1; stmt_line_ = 1; - string token = getToken(); + std::string token = getToken(); while (!token.empty()) { if (token == "$date") reader_->setDate(readStmtString()); diff --git a/power/VcdParse.hh b/power/VcdParse.hh index bd42be60..6fb371c9 100644 --- a/power/VcdParse.hh +++ b/power/VcdParse.hh @@ -33,11 +33,8 @@ namespace sta { -using std::string; -using std::vector; - typedef int64_t VcdTime; -typedef vector VcdScope; +typedef std::vector VcdScope; enum class VcdVarType { wire, @@ -71,19 +68,19 @@ public: private: void parseTimescale(); - void setTimeUnit(const string &time_unit, + void setTimeUnit(const std::string &time_unit, double time_scale); void parseVar(); void parseScope(); void parseUpscope(); void parseVarValues(); - string getToken(); - string readStmtString(); - vector readStmtTokens(); + std::string getToken(); + std::string readStmtString(); + std::vector readStmtTokens(); VcdReader *reader_; gzFile stream_; - string token_; + std::string token_; const char *filename_; int file_line_; int stmt_line_; @@ -101,24 +98,24 @@ class VcdReader { public: virtual ~VcdReader() {} - virtual void setDate(const string &date) = 0; - virtual void setComment(const string &comment) = 0; - virtual void setVersion(const string &version) = 0; - virtual void setTimeUnit(const string &time_unit, + virtual void setDate(const std::string &date) = 0; + virtual void setComment(const std::string &comment) = 0; + virtual void setVersion(const std::string &version) = 0; + virtual void setTimeUnit(const std::string &time_unit, double time_unit_scale, double time_scale) = 0; virtual void setTimeMax(VcdTime time_max) = 0; virtual void varMinDeltaTime(VcdTime min_delta_time) = 0; - virtual bool varIdValid(const string &id) = 0; + virtual bool varIdValid(const std::string &id) = 0; virtual void makeVar(const VcdScope &scope, - const string &name, + const std::string &name, VcdVarType type, size_t width, - const string &id) = 0; - virtual void varAppendValue(const string &id, + const std::string &id) = 0; + virtual void varAppendValue(const std::string &id, VcdTime time, char value) = 0; - virtual void varAppendBusValue(const string &id, + virtual void varAppendBusValue(const std::string &id, VcdTime time, int64_t bus_value) = 0; }; diff --git a/sdc/ExceptionPath.cc b/sdc/ExceptionPath.cc index 3f265c65..046a6bdc 100644 --- a/sdc/ExceptionPath.cc +++ b/sdc/ExceptionPath.cc @@ -37,6 +37,8 @@ namespace sta { +using std::string; + static bool thrusIntersectPts(ExceptionThruSeq *thrus1, ExceptionThruSeq *thrus2, diff --git a/sdc/Sdc.cc b/sdc/Sdc.cc index 2e46416f..aa02e319 100644 --- a/sdc/Sdc.cc +++ b/sdc/Sdc.cc @@ -30,6 +30,7 @@ #include "Debug.hh" #include "Mutex.hh" #include "Report.hh" +#include "Variables.hh" #include "PatternMatch.hh" #include "MinMax.hh" #include "TimingRole.hh" @@ -233,19 +234,6 @@ void Sdc::initVariables() { analysis_type_ = AnalysisType::ocv; - use_default_arrival_clock_ = false; - crpr_enabled_ = true; - crpr_mode_ = CrprMode::same_pin; - propagate_gated_clock_enable_ = true; - preset_clr_arcs_enabled_ = false; - cond_default_arcs_enabled_ = true; - bidirect_net_paths_enabled_ = false; - bidirect_inst_paths_enabled_ = false; - recovery_removal_checks_enabled_ = true; - gated_clk_checks_enabled_ = true; - clk_thru_tristate_enabled_ = false; - dynamic_loop_breaking_ = false; - propagate_all_clks_ = false; wireload_mode_ = WireloadMode::unknown; max_area_ = 0.0; path_delays_without_to_ = false; @@ -1000,7 +988,7 @@ Sdc::makeClock(const char *name, else { // Fresh clock definition. clk = new Clock(name, clk_index_++, network_); - clk->setIsPropagated(propagate_all_clks_); + clk->setIsPropagated(variables_->propagateAllClocks()); clocks_.push_back(clk); // Use the copied name in the map. clock_name_map_[clk->name()] = clk; @@ -1041,7 +1029,8 @@ Sdc::makeGeneratedClock(const char *name, clk->initGeneratedClk(pins, add_to_pins, src_pin, master_clk, divide_by, multiply_by, duty_cycle, invert, combinational, - edges, edge_shifts, propagate_all_clks_, + edges, edge_shifts, + variables_->propagateAllClocks(), comment, network_); makeClkPinMappings(clk); clearCycleAcctings(); @@ -1249,6 +1238,12 @@ Sdc::sortedClocks(ClockSeq &clks) sort(clks, ClkNameLess()); } +ClockEdge * +Sdc::defaultArrivalClockEdge() const +{ + return default_arrival_clk_->edge(RiseFall::rise()); +} + //////////////////////////////////////////////////////////////// class ClkHpinDisable @@ -5481,203 +5476,6 @@ Sdc::setWireloadSelection(WireloadSelection *selection, //////////////////////////////////////////////////////////////// -bool -Sdc::crprEnabled() const -{ - return crpr_enabled_; -} - -void -Sdc::setCrprEnabled(bool enabled) -{ - crpr_enabled_ = enabled; -} - -CrprMode -Sdc::crprMode() const -{ - return crpr_mode_; -} - -void -Sdc::setCrprMode(CrprMode mode) -{ - crpr_mode_ = mode; -} - -bool -Sdc::crprActive() const -{ - return analysis_type_ == AnalysisType::ocv - && crpr_enabled_; -} - -bool -Sdc::propagateGatedClockEnable() const -{ - return propagate_gated_clock_enable_; -} - -void -Sdc::setPropagateGatedClockEnable(bool enable) -{ - propagate_gated_clock_enable_ = enable; -} - -bool -Sdc::presetClrArcsEnabled() const -{ - return preset_clr_arcs_enabled_; -} - -void -Sdc::setPresetClrArcsEnabled(bool enable) -{ - preset_clr_arcs_enabled_ = enable; -} - -bool -Sdc::condDefaultArcsEnabled() const -{ - return cond_default_arcs_enabled_; -} - -void -Sdc::setCondDefaultArcsEnabled(bool enabled) -{ - cond_default_arcs_enabled_ = enabled; -} - -bool -Sdc::isDisabledCondDefault(Edge *edge) const -{ - return !cond_default_arcs_enabled_ - && edge->timingArcSet()->isCondDefault(); -} - -bool -Sdc::bidirectInstPathsEnabled() const -{ - return bidirect_inst_paths_enabled_; -} - -void -Sdc::setBidirectInstPathsEnabled(bool enabled) -{ - bidirect_inst_paths_enabled_ = enabled; -} - -// Delay calculation propagates slews from a bidirect driver -// to the bidirect port and back through the bidirect driver when -// sta_bidirect_inst_paths_enabled_ is true. -bool -Sdc::bidirectDrvrSlewFromLoad(const Pin *pin) const -{ - return bidirect_inst_paths_enabled_ - && network_->direction(pin)->isBidirect() - && network_->isTopLevelPort(pin); -} - -bool -Sdc::bidirectNetPathsEnabled() const -{ - return bidirect_inst_paths_enabled_; -} - -void -Sdc::setBidirectNetPathsEnabled(bool enabled) -{ - bidirect_inst_paths_enabled_ = enabled; -} - -bool -Sdc::recoveryRemovalChecksEnabled() const -{ - return recovery_removal_checks_enabled_; -} - -void -Sdc::setRecoveryRemovalChecksEnabled(bool enabled) -{ - recovery_removal_checks_enabled_ = enabled; -} - -bool -Sdc::gatedClkChecksEnabled() const -{ - return gated_clk_checks_enabled_; -} - -void -Sdc::setGatedClkChecksEnabled(bool enabled) -{ - gated_clk_checks_enabled_ = enabled; -} - -bool -Sdc::dynamicLoopBreaking() const -{ - return dynamic_loop_breaking_; -} - -void -Sdc::setDynamicLoopBreaking(bool enable) -{ - if (dynamic_loop_breaking_ != enable) { - if (levelize_->levelized()) { - if (enable) - makeLoopExceptions(); - else - deleteLoopExceptions(); - } - dynamic_loop_breaking_ = enable; - } -} - -bool -Sdc::propagateAllClocks() const -{ - return propagate_all_clks_; -} - -void -Sdc::setPropagateAllClocks(bool prop) -{ - propagate_all_clks_ = prop; -} - -bool -Sdc::clkThruTristateEnabled() const -{ - return clk_thru_tristate_enabled_; -} - -void -Sdc::setClkThruTristateEnabled(bool enable) -{ - clk_thru_tristate_enabled_ = enable; -} - -ClockEdge * -Sdc::defaultArrivalClockEdge() const -{ - return default_arrival_clk_->edge(RiseFall::rise()); -} - -bool -Sdc::useDefaultArrivalClock() -{ - return use_default_arrival_clock_; -} - -void -Sdc::setUseDefaultArrivalClock(bool enable) -{ - use_default_arrival_clock_ = enable; -} - -//////////////////////////////////////////////////////////////// - void Sdc::connectPinAfter(const Pin *pin) { diff --git a/sdc/Variables.cc b/sdc/Variables.cc new file mode 100644 index 00000000..1cb10bd0 --- /dev/null +++ b/sdc/Variables.cc @@ -0,0 +1,131 @@ +// OpenSTA, Static Timing Analyzer +// Copyright (c) 2025, Parallax Software, Inc. +// +// This program is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see . +// +// The origin of this software must not be misrepresented; you must not +// claim that you wrote the original software. +// +// Altered source versions must be plainly marked as such, and must not be +// misrepresented as being the original software. +// +// This notice may not be removed or altered from any source distribution. + +#include "Variables.hh" + +namespace sta { + +Variables::Variables() : + crpr_enabled_(true), + crpr_mode_(CrprMode::same_pin), + propagate_gated_clock_enable_(true), + preset_clr_arcs_enabled_(false), + cond_default_arcs_enabled_(true), + bidirect_net_paths_enabled_(false), + bidirect_inst_paths_enabled_(false), + recovery_removal_checks_enabled_(true), + gated_clk_checks_enabled_(true), + clk_thru_tristate_enabled_(false), + dynamic_loop_breaking_(false), + propagate_all_clks_(false), + use_default_arrival_clock_(false), + pocv_enabled_(false) +{ +} + +void +Variables::setCrprEnabled(bool enabled) +{ + crpr_enabled_ = enabled; +} + +void +Variables::setCrprMode(CrprMode mode) +{ + crpr_mode_ = mode; +} + +void +Variables::setPropagateGatedClockEnable(bool enable) +{ + propagate_gated_clock_enable_ = enable; +} + +void +Variables::setPresetClrArcsEnabled(bool enable) +{ + preset_clr_arcs_enabled_ = enable; +} + +void +Variables::setCondDefaultArcsEnabled(bool enabled) +{ + cond_default_arcs_enabled_ = enabled; +} + +void +Variables::setBidirectInstPathsEnabled(bool enabled) +{ + bidirect_inst_paths_enabled_ = enabled; +} + +void +Variables::setBidirectNetPathsEnabled(bool enabled) +{ + bidirect_net_paths_enabled_ = enabled; +} + +void +Variables::setRecoveryRemovalChecksEnabled(bool enabled) +{ + recovery_removal_checks_enabled_ = enabled; +} + +void +Variables::setGatedClkChecksEnabled(bool enabled) +{ + gated_clk_checks_enabled_ = enabled; +} + +void +Variables::setDynamicLoopBreaking(bool enable) +{ + dynamic_loop_breaking_ = enable; +} + +void +Variables::setPropagateAllClocks(bool prop) +{ + propagate_all_clks_ = prop; +} + +void +Variables::setClkThruTristateEnabled(bool enable) +{ + clk_thru_tristate_enabled_ = enable; +} + +void +Variables::setUseDefaultArrivalClock(bool enable) +{ + use_default_arrival_clock_ = enable; +} + +void +Variables::setPocvEnabled(bool enabled) +{ + pocv_enabled_ = enabled; +} + +} // namespace diff --git a/sdc/WriteSdc.cc b/sdc/WriteSdc.cc index 93f55ba9..5c448a8c 100644 --- a/sdc/WriteSdc.cc +++ b/sdc/WriteSdc.cc @@ -55,10 +55,13 @@ #include "Fuzzy.hh" #include "StaState.hh" #include "Corner.hh" +#include "Variables.hh" #include "WriteSdcPvt.hh" namespace sta { +using std::string; + typedef Set ClockSenseSet; typedef Vector ClockSenseSeq; @@ -2324,13 +2327,13 @@ WriteSdc::writeFanoutLimits(const MinMax *min_max, void WriteSdc::writeVariables() const { - if (sdc_->propagateAllClocks()) { + if (variables_->propagateAllClocks()) { if (native_) gzprintf(stream_, "set sta_propagate_all_clocks 1\n"); else gzprintf(stream_, "set timing_all_clocks_propagated true\n"); } - if (sdc_->presetClrArcsEnabled()) { + if (variables_->presetClrArcsEnabled()) { if (native_) gzprintf(stream_, "set sta_preset_clear_arcs_enabled 1\n"); else diff --git a/sdf/ReportAnnotation.cc b/sdf/ReportAnnotation.cc index 76ce7a4c..649853e9 100644 --- a/sdf/ReportAnnotation.cc +++ b/sdf/ReportAnnotation.cc @@ -290,7 +290,7 @@ ReportAnnotated::reportCheckCount(const TimingRole *role, { int index = role->index(); if (edge_count_[index] > 0) { - string title; + std::string title; stringPrint(title, "cell %s arcs", role->to_string().c_str()); reportCount(title.c_str(), index, total, annotated_total); } diff --git a/sdf/SdfLex.ll b/sdf/SdfLex.ll index 33d0a349..19849ff3 100644 --- a/sdf/SdfLex.ll +++ b/sdf/SdfLex.ll @@ -82,7 +82,7 @@ EOL \r?\n "\"" { BEGIN INITIAL; - yylval->string = new string(token_); + yylval->string = new std::string(token_); return token::QSTRING; } @@ -157,7 +157,7 @@ COND { "("{BLANK}*IOPATH { BEGIN INITIAL; - yylval->string = new string(token_); + yylval->string = new std::string(token_); return token::EXPR_OPEN_IOPATH; } @@ -167,7 +167,7 @@ COND { */ if (reader_->inTimingCheck()) { BEGIN INITIAL; - yylval->string = new string(token_); + yylval->string = new std::string(token_); return token::EXPR_OPEN; } else @@ -179,9 +179,9 @@ COND { if (reader_->inTimingCheck()) { BEGIN INITIAL; /* remove trailing ")" */ - string cond_id(token_); + std::string cond_id(token_); cond_id += yytext; - yylval->string = new string(cond_id.substr(0, cond_id.size() - 1)); + yylval->string = new std::string(cond_id.substr(0, cond_id.size() - 1)); /* No way to pass expr and id separately, so pass them together. */ return token::EXPR_ID_CLOSE; } @@ -194,7 +194,7 @@ COND { . { token_ += yytext[0]; } {ID} { - yylval->string = new string(yytext); + yylval->string = new std::string(yytext); return token::ID; } diff --git a/sdf/SdfParse.yy b/sdf/SdfParse.yy index 04ebad21..8475dafe 100644 --- a/sdf/SdfParse.yy +++ b/sdf/SdfParse.yy @@ -36,7 +36,7 @@ void sta::SdfParse::error(const location_type &loc, - const string &msg) + const std::string &msg) { reader->report()->fileError(164,reader->filename().c_str(), loc.begin.line,"%s",msg.c_str()); diff --git a/sdf/SdfReader.cc b/sdf/SdfReader.cc index 10eaac7d..00279e49 100644 --- a/sdf/SdfReader.cc +++ b/sdf/SdfReader.cc @@ -45,6 +45,7 @@ namespace sta { +using std::string; using std::to_string; class SdfTriple @@ -65,8 +66,8 @@ class SdfPortSpec { public: SdfPortSpec(const Transition *tr, - const string *port, - const string *cond); + const std::string *port, + const std::string *cond); ~SdfPortSpec(); const string *port() const { return port_; } const Transition *transition() const { return tr_; } diff --git a/sdf/SdfReaderPvt.hh b/sdf/SdfReaderPvt.hh index c85c8fdd..06749391 100644 --- a/sdf/SdfReaderPvt.hh +++ b/sdf/SdfReaderPvt.hh @@ -59,7 +59,7 @@ public: void setDivider(char divider); void setTimescale(float multiplier, - const string *units); + const std::string *units); void setPortDeviceDelay(Edge *edge, SdfTripleSeq *triples, bool from_trans); @@ -80,17 +80,17 @@ public: int triple_index, int arc_delay_index, const MinMax *min_max); - void setInstance(const string *instance_name); + void setInstance(const std::string *instance_name); void setInstanceWildcard(); void cellFinish(); - void setCell(const string *cell_name); - void interconnect(const string *from_pin_name, - const string *to_pin_name, + void setCell(const std::string *cell_name); + void interconnect(const std::string *from_pin_name, + const std::string *to_pin_name, SdfTripleSeq *triples); void iopath(SdfPortSpec *from_edge, - const string *to_port_name, + const std::string *to_port_name, SdfTripleSeq *triples, - const string *cond, + const std::string *cond, bool condelse); void timingCheck(const TimingRole *role, SdfPortSpec *data_edge, @@ -118,10 +118,10 @@ public: SdfPortSpec *clk_edge, SdfTriple *before_triple, SdfTriple *after_triple); - void port(const string *to_pin_name, + void port(const std::string *to_pin_name, SdfTripleSeq *triples); void device(SdfTripleSeq *triples); - void device(const string *to_pin_name, + void device(const std::string *to_pin_name, SdfTripleSeq *triples); SdfTriple *makeTriple(); @@ -133,20 +133,20 @@ public: SdfTripleSeq *makeTripleSeq(); void deleteTripleSeq(SdfTripleSeq *triples); SdfPortSpec *makePortSpec(const Transition *tr, - const string *port, - const string *cond); - SdfPortSpec *makeCondPortSpec(const string *cond_port); - string *unescaped(const string *token); - string *makePath(const string *head, - const string *tail); + const std::string *port, + const std::string *cond); + SdfPortSpec *makeCondPortSpec(const std::string *cond_port); + std::string *unescaped(const std::string *token); + std::string *makePath(const std::string *head, + const std::string *tail); // Parser state used to control lexer for COND handling. bool inTimingCheck() { return in_timing_check_; } void setInTimingCheck(bool in); bool inIncremental() const { return in_incremental_; } void setInIncremental(bool incr); - string *makeBusName(string *bus_name, - int index); - const string &filename() const { return filename_; } + std::string *makeBusName(std::string *bus_name, + int index); + const std::string &filename() const { return filename_; } void sdfWarn(int id, const char *fmt, ...); void sdfError(int id, @@ -161,11 +161,11 @@ private: Edge *findCheckEdge(Pin *from_pin, Pin *to_pin, const TimingRole *sdf_role, - const string *cond_start, - const string *cond_end); + const std::string *cond_start, + const std::string *cond_end); Edge *findWireEdge(Pin *from_pin, Pin *to_pin); - bool condMatch(const string *sdf_cond, + bool condMatch(const std::string *sdf_cond, const char *lib_cond); void timingCheck1(const TimingRole *role, Port *data_port, @@ -180,17 +180,17 @@ private: const TimingRole *sdf_role, SdfTriple *triple, bool match_generic); - Pin *findPin(const string *name); - Instance *findInstance(const string *name); + Pin *findPin(const std::string *name); + Instance *findInstance(const std::string *name); void setEdgeDelays(Edge *edge, SdfTripleSeq *triples, const char *sdf_cmd); void setDevicePinDelays(Pin *to_pin, SdfTripleSeq *triples); Port *findPort(const Cell *cell, - const string *port_name); + const std::string *port_name); - string filename_; + std::string filename_; SdfScanner *scanner_; const char *path_; // Which values to pull out of the sdf triples. @@ -207,7 +207,7 @@ private: char divider_; char escape_; Instance *instance_; - const string *cell_name_; + const std::string *cell_name_; bool in_timing_check_; bool in_incremental_; float timescale_; diff --git a/sdf/SdfScanner.hh b/sdf/SdfScanner.hh index 9b1b92f1..e66e8593 100644 --- a/sdf/SdfScanner.hh +++ b/sdf/SdfScanner.hh @@ -41,7 +41,7 @@ class SdfScanner : public SdfFlexLexer { public: SdfScanner(std::istream *stream, - const string &filename, + const std::string &filename, SdfReader *reader, Report *report); virtual ~SdfScanner() {} @@ -57,10 +57,10 @@ public: using FlexLexer::yylex; private: - string filename_; + std::string filename_; SdfReader *reader_; Report *report_; - string token_; + std::string token_; }; } // namespace diff --git a/search/CheckTiming.hh b/search/CheckTiming.hh index 150ad322..205ad2da 100644 --- a/search/CheckTiming.hh +++ b/search/CheckTiming.hh @@ -72,7 +72,7 @@ protected: ClockSet &clks); void errorMsgSubst(const char *msg, int count, - string &error_msg); + std::string &error_msg); CheckErrorSeq errors_; }; diff --git a/search/ClkInfo.cc b/search/ClkInfo.cc index e7112255..409f50b8 100644 --- a/search/ClkInfo.cc +++ b/search/ClkInfo.cc @@ -133,7 +133,7 @@ ClkInfo::asString(const StaState *sta) const { Network *network = sta->network(); Corners *corners = sta->corners(); - string result; + std::string result; PathAnalysisPt *path_ap = corners->findPathAnalysisPt(path_ap_index_); result += path_ap->pathMinMax()->to_string(); @@ -217,7 +217,7 @@ clkInfoEqual(const ClkInfo *clk_info1, const ClkInfo *clk_info2, const StaState *sta) { - bool crpr_on = sta->sdc()->crprActive(); + bool crpr_on = sta->crprActive(); ClockUncertainties *uncertainties1 = clk_info1->uncertainties(); ClockUncertainties *uncertainties2 = clk_info2->uncertainties(); return clk_info1->clkEdge() == clk_info2->clkEdge() @@ -290,7 +290,7 @@ clkInfoCmp(const ClkInfo *clk_info1, if (gen_clk_src1 > gen_clk_src2) return 1; - bool crpr_on = sta->sdc()->crprActive(); + bool crpr_on = sta->crprActive(); if (crpr_on) { const Path *crpr_path1 = clk_info1->crprClkPath(sta); const Path *crpr_path2 = clk_info2->crprClkPath(sta); diff --git a/search/Corner.cc b/search/Corner.cc index 0ed7834c..193e173b 100644 --- a/search/Corner.cc +++ b/search/Corner.cc @@ -149,7 +149,7 @@ Corners::makeParasiticAnalysisPts(bool per_corner) int ap_index = corner->index() * MinMax::index_count + mm_index; int ap_index_max = corner->index() * MinMax::index_count + MinMax::max()->index(); - string ap_name = corner->name(); + std::string ap_name = corner->name(); ap_name += "_"; ap_name += min_max->to_string(); ParasiticAnalysisPt *ap = new ParasiticAnalysisPt(ap_name.c_str(), diff --git a/search/Crpr.cc b/search/Crpr.cc index ea819248..894a1e9b 100644 --- a/search/Crpr.cc +++ b/search/Crpr.cc @@ -41,6 +41,7 @@ #include "PathEnd.hh" #include "Search.hh" #include "Genclks.hh" +#include "Variables.hh" namespace sta { @@ -107,9 +108,9 @@ CheckCrpr::checkCrpr(const Path *src_path, { crpr = 0.0; crpr_pin = nullptr; - if (sdc_->crprActive() + if (crprActive() && src_path && tgt_clk_path) { - bool same_pin = (sdc_->crprMode() == CrprMode::same_pin); + bool same_pin = (variables_->crprMode() == CrprMode::same_pin); checkCrpr1(src_path, tgt_clk_path, same_pin, crpr, crpr_pin); } } @@ -267,7 +268,7 @@ Crpr CheckCrpr::findCrpr1(const Path *src_clk_path, const Path *tgt_clk_path) { - if (pocv_enabled_) { + if (variables_->pocvEnabled()) { // Remove variation on the common path. // Note that the crpr sigma is negative to offset the // sigma of the common clock path. @@ -329,10 +330,10 @@ CheckCrpr::outputDelayCrpr(const Path *src_path, { crpr = 0.0; crpr_pin = nullptr; - if (sdc_->crprActive()) { + if (crprActive()) { const PathAnalysisPt *path_ap = src_path->pathAnalysisPt(this); const PathAnalysisPt *tgt_path_ap = path_ap->tgtClkAnalysisPt(); - bool same_pin = (sdc_->crprMode() == CrprMode::same_pin); + bool same_pin = (variables_->crprMode() == CrprMode::same_pin); outputDelayCrpr1(src_path,tgt_clk_edge,tgt_path_ap, same_pin, crpr, crpr_pin); } diff --git a/search/Genclks.cc b/search/Genclks.cc index f36a150c..10f67951 100644 --- a/search/Genclks.cc +++ b/search/Genclks.cc @@ -42,6 +42,7 @@ #include "Levelize.hh" #include "Path.hh" #include "Search.hh" +#include "Variables.hh" namespace sta { @@ -249,7 +250,7 @@ GenClkMasterSearchPred::searchFrom(const Vertex *from_vertex) bool GenClkMasterSearchPred::searchThru(Edge *edge) { - const Sdc *sdc = sta_->sdc(); + const Variables *variables = sta_->variables(); const TimingRole *role = edge->role(); // Propagate clocks through constants. return !(edge->role()->isTimingCheck() @@ -257,14 +258,14 @@ GenClkMasterSearchPred::searchThru(Edge *edge) || edge->isDisabledConstraint() // Constants disable edge cond expression. || edge->isDisabledCond() - || sdc->isDisabledCondDefault(edge) + || sta_->isDisabledCondDefault(edge) // Register/latch preset/clr edges are disabled by default. - || (!sdc->presetClrArcsEnabled() + || (!variables->presetClrArcsEnabled() && role == TimingRole::regSetClr()) || (edge->isBidirectInstPath() - && !sdc->bidirectInstPathsEnabled()) + && !variables->bidirectInstPathsEnabled()) || (edge->isBidirectNetPath() - && !sdc->bidirectNetPathsEnabled())); + && !variables->bidirectNetPathsEnabled())); } bool @@ -481,7 +482,7 @@ GenClkInsertionSearchPred::searchThru(Edge *edge) EdgeSet *fdbk_edges = genclk_info_->fdbkEdges(); return SearchPred0::searchThru(edge) && !role->isTimingCheck() - && (sdc->clkThruTristateEnabled() + && (sta_->variables()->clkThruTristateEnabled() || !(role == TimingRole::tristateEnable() || role == TimingRole::tristateDisable())) && !(fdbk_edges && fdbk_edges->hasKey(edge)) @@ -740,13 +741,12 @@ GenClkArrivalSearchPred::GenClkArrivalSearchPred(Clock *gclk, bool GenClkArrivalSearchPred::searchThru(Edge *edge) { - const Sdc *sdc = sta_->sdc(); const TimingRole *role = edge->role(); return EvalPred::searchThru(edge) && (role == TimingRole::combinational() || role->isWire() || !combinational_) - && (sdc->clkThruTristateEnabled() + && (sta_->variables()->clkThruTristateEnabled() || !(role == TimingRole::tristateEnable() || role == TimingRole::tristateDisable())); } @@ -895,7 +895,7 @@ Genclks::recordSrcPaths(Clock *gclk) bool has_edges = gclk->edges() != nullptr; for (const Pin *gclk_pin : gclk->leafPins()) { - vector &src_paths = genclk_src_paths_[ClockPinPair(gclk, gclk_pin)]; + std::vector &src_paths = genclk_src_paths_[ClockPinPair(gclk, gclk_pin)]; src_paths.resize(path_count); Vertex *gclk_vertex = srcPath(gclk_pin); bool found_src_paths = false; @@ -1002,7 +1002,7 @@ Genclks::srcPath(const Clock *gclk, { auto itr = genclk_src_paths_.find(ClockPinPair(gclk, src_pin)); if (itr != genclk_src_paths_.end()) { - vector src_paths = itr->second; + std::vector src_paths = itr->second; if (!src_paths.empty()) { size_t path_index = srcPathIndex(rf, path_ap); Path &src_path = src_paths[path_index]; @@ -1023,12 +1023,10 @@ Genclks::updateSrcPathPrevs() if (!src_path.isNull()) { const Path *p = &src_path; while (p) { - Path *src_vpath = Path::vertexPath(p->vertex(this), - p->tag(this), this); + Path *src_vpath = Path::vertexPath(p, this); Path *prev_path = p->prevPath(); if (prev_path) { - Path *prev_vpath = Path::vertexPath(prev_path->vertex(this), - prev_path->tag(this), this); + Path *prev_vpath = Path::vertexPath(prev_path, this); src_vpath->setPrevPath(prev_vpath); src_vpath->setPrevEdgeArc(p->prevEdge(this), p->prevArc(this), this); diff --git a/search/Genclks.hh b/search/Genclks.hh index c063d31b..12e2626a 100644 --- a/search/Genclks.hh +++ b/search/Genclks.hh @@ -50,7 +50,7 @@ public: }; typedef Map GenclkInfoMap; -typedef Map, ClockPinPairLess> GenclkSrcPathMap; +typedef Map, ClockPinPairLess> GenclkSrcPathMap; class Genclks : public StaState { diff --git a/search/Latches.cc b/search/Latches.cc index 171df269..15469083 100644 --- a/search/Latches.cc +++ b/search/Latches.cc @@ -352,8 +352,7 @@ Latches::latchOutArrival(const Path *data_path, q_arrival = adjusted_data_arrival + arc_delay; // Tag switcheroo - data passing thru gets latch enable tag. // States and path ap come from Q, everything else from enable. - Path *crpr_clk_path = - sdc_->crprActive() ? enable_path : nullptr; + Path *crpr_clk_path = crprActive() ? enable_path : nullptr; ClkInfo *q_clk_info = search_->findClkInfo(en_clk_edge, en_clk_info->clkSrc(), diff --git a/search/Levelize.cc b/search/Levelize.cc index 0cc5ac52..b2f03e78 100644 --- a/search/Levelize.cc +++ b/search/Levelize.cc @@ -36,6 +36,8 @@ #include "Graph.hh" #include "GraphCmp.hh" #include "SearchPred.hh" +#include "Variables.hh" +#include "GraphDelayCalc.hh" namespace sta { @@ -185,7 +187,7 @@ Levelize::isRoot(Vertex *vertex) return false; } // Bidirect pins are not treated as roots in this case. - return !sdc_->bidirectDrvrSlewFromLoad(vertex->pin()); + return !graph_delay_calc_->bidirectDrvrSlewFromLoad(vertex->pin()); } else return false; @@ -250,7 +252,7 @@ Levelize::visit(Vertex *vertex, latch_d_to_q_edges_.insert(edge); } // Levelize bidirect driver as if it was a fanout of the bidirect load. - if (sdc_->bidirectDrvrSlewFromLoad(from_pin) + if (graph_delay_calc_->bidirectDrvrSlewFromLoad(from_pin) && !vertex->isBidirectDriver()) { Vertex *to_vertex = graph_->pinDrvrVertex(from_pin); if (search_pred_->searchTo(to_vertex) @@ -288,7 +290,7 @@ Levelize::recordLoop(Edge *edge, EdgeSeq *loop_edges = loopEdges(path, edge); GraphLoop *loop = new GraphLoop(loop_edges); loops_->push_back(loop); - if (sdc_->dynamicLoopBreaking()) + if (variables_->dynamicLoopBreaking()) sdc_->makeLoopExceptions(loop); } // Record disabled loop edges so they can be cleared without diff --git a/search/MakeTimingModel.cc b/search/MakeTimingModel.cc index 88e6accb..aa4083e2 100644 --- a/search/MakeTimingModel.cc +++ b/search/MakeTimingModel.cc @@ -209,6 +209,7 @@ MakeTimingModel::makePorts() float load_cap = graph_delay_calc_->loadCap(pin, dcalc_ap); lib_bit_port->setCapacitance(load_cap); } + delete member_iter; } else { LibertyPort *lib_port = lib_builder_->makePort(cell_, port_name); diff --git a/search/Path.cc b/search/Path.cc index b2b76f37..670be92f 100644 --- a/search/Path.cc +++ b/search/Path.cc @@ -200,7 +200,7 @@ Path::init(Vertex *vertex, is_enum_ = false; } -string +std::string Path::to_string(const StaState *sta) const { const PathAnalysisPt *path_ap = pathAnalysisPt(sta); @@ -473,6 +473,13 @@ Path::setIsEnum(bool is_enum) //////////////////////////////////////////////////////////////// +Path * +Path::vertexPath(const Path *path, + const StaState *sta) +{ + return vertexPath(path->vertex(sta), path->tag(sta), sta); +} + Path * Path::vertexPath(const Path &path, const StaState *sta) diff --git a/search/PathAnalysisPt.cc b/search/PathAnalysisPt.cc index e137ff76..476a8649 100644 --- a/search/PathAnalysisPt.cc +++ b/search/PathAnalysisPt.cc @@ -42,10 +42,10 @@ PathAnalysisPt::PathAnalysisPt(Corner *corner, { } -string +std::string PathAnalysisPt::to_string() const { - string name = corner_->name(); + std::string name = corner_->name(); name += '/'; name += path_min_max_->to_string(); return name; diff --git a/search/PathEnum.cc b/search/PathEnum.cc index 48601683..dcf970e9 100644 --- a/search/PathEnum.cc +++ b/search/PathEnum.cc @@ -295,7 +295,7 @@ PathEnumFaninVisitor::PathEnumFaninVisitor(PathEnd *path_end, before_div_ap_index_(before_div_->pathAnalysisPtIndex(this)), before_div_arrival_(before_div_->arrival()), path_enum_(path_enum), - crpr_active_(sdc_->crprActive()) + crpr_active_(crprActive()) { } @@ -506,16 +506,16 @@ PathEnum::makeDiversions(PathEnd *path_end, Path *prev_path = path->prevPath(); TimingArc *prev_arc = path->prevArc(this); PathEnumFaninVisitor fanin_visitor(path_end, path, unique_pins_, this); - while (prev_path - // Do not enumerate paths in the clk network. - && !path->isClock(this)) { + while (prev_path) { // Fanin visitor does all the work. // While visiting the fanins the fanin_visitor finds the // previous path and arc as well as diversions. fanin_visitor.visitFaninPathsThru(path, prev_path->vertex(this), prev_arc); // Do not enumerate beyond latch D to Q edges. // This breaks latch loop paths. - if (prev_arc->role() == TimingRole::latchDtoQ()) + const TimingRole *prev_role = prev_arc->role(); + if (prev_role == TimingRole::latchDtoQ() + || prev_role == TimingRole::regClkToQ()) break; path = prev_path; prev_path = path->prevPath(); @@ -555,13 +555,13 @@ PathEnum::makeDivertedPath(Path *path, prev_copy->setPrevPath(copy); copies.push_back(copy); - if (Path::equal(p, after_div, this)) + if (p == after_div) after_div_copy = copy; if (first) div_path = copy; else if (network_->isLatchData(p->pin(this))) break; - if (Path::equal(p, before_div, this)) { + if (p == before_div) { // Replaced on next pass. copy->setPrevPath(after_div); copy->setPrevEdgeArc(div_edge, div_arc, this); @@ -603,12 +603,14 @@ PathEnum::updatePathHeadDelays(PathSeq &paths, delayAsString(arrival, this)); path->setArrival(arrival); prev_arrival = arrival; - if (sdc_->crprActive() + const Tag *tag = path->tag(this); + const ClkInfo *clk_info = tag->clkInfo(); + if (crprActive() + && clk_info != prev_clk_info // D->Q paths use the EN->Q clk info so no need to update. && arc->role() != TimingRole::latchDtoQ()) { // When crpr is enabled the diverion may be from another crpr clk pin, // so update the tags to use the corresponding ClkInfo. - Tag *tag = path->tag(this); Tag *updated_tag = search_->findTag(path->transition(this), path_ap, prev_clk_info, diff --git a/search/PathGroup.cc b/search/PathGroup.cc index 857eac11..b2661fa7 100644 --- a/search/PathGroup.cc +++ b/search/PathGroup.cc @@ -152,7 +152,8 @@ PathGroup::enumMinSlackUnderMin(PathEnd *path_end) if (tagMatchCrpr(other->tag(sta_), tag)) { PathEnd *end_min = path_end->copy(); end_min->setPath(other); - bool slack_under = fuzzyGreater(end_min->slackNoCrpr(sta_), slack_min_); + float slack = delayAsFloat(end_min->slackNoCrpr(sta_)); + bool slack_under = fuzzyGreater(slack, slack_min_); delete end_min; if (slack_under) return true; diff --git a/search/ReportPath.cc b/search/ReportPath.cc index 5a895a3e..9cea1857 100644 --- a/search/ReportPath.cc +++ b/search/ReportPath.cc @@ -59,6 +59,7 @@ #include "Latches.hh" #include "Corner.hh" #include "Genclks.hh" +#include "Variables.hh" namespace sta { @@ -1397,7 +1398,7 @@ ReportPath::reportVerbose(const MinPulseWidthCheck *check) const reportLine(clk_ideal_prop, check->closeDelay(this), close_arrival, close_el); reportLine(pin_name, delay_zero, close_arrival, close_el); - if (sdc_->crprEnabled()) { + if (variables_->crprEnabled()) { Crpr pessimism = check->checkCrpr(this); close_arrival += pessimism; reportLine("clock reconvergence pessimism", pessimism, close_arrival, close_el); @@ -2530,7 +2531,7 @@ void ReportPath::reportCommonClkPessimism(const PathEnd *end, Arrival &clk_arrival) const { - if (sdc_->crprEnabled()) { + if (variables_->crprEnabled()) { Crpr pessimism = end->checkCrpr(this); clk_arrival += pessimism; reportLine("clock reconvergence pessimism", pessimism, clk_arrival, diff --git a/search/ReportPath.hh b/search/ReportPath.hh index 4f3a6812..be229016 100644 --- a/search/ReportPath.hh +++ b/search/ReportPath.hh @@ -37,8 +37,6 @@ class DcalcAnalysisPt; class PathExpanded; class ReportField; -using std::string; - typedef Vector ReportFieldSeq; class ReportPath : public StaState @@ -102,12 +100,12 @@ public: const char *path_name, int indent, bool trailing_comma, - string &result) const; + std::string &result) const; void reportJson(const PathExpanded &expanded, const char *path_name, int indent, bool trailing_comma, - string &result) const; + std::string &result) const; void reportEndHeader() const; void reportEndLine(const PathEnd *end) const; @@ -189,17 +187,17 @@ protected: void reportEndpointOutputDelay(const PathEndClkConstrained *end) const; void reportEndpoint(const PathEndPathDelay *end) const; void reportEndpoint(const PathEndGatedClock *end) const; - string pathEndpoint(const PathEnd *end) const; - string pathStartpoint(const PathEnd *end, - const PathExpanded &expanded) const; + std::string pathEndpoint(const PathEnd *end) const; + std::string pathStartpoint(const PathEnd *end, + const PathExpanded &expanded) const; void reportBorrowing(const PathEndLatchCheck *end, Arrival &borrow, Arrival &time_given_to_startpoint) const; void reportEndpoint(const PathEndDataCheck *end) const; const char *clkNetworkDelayIdealProp(bool is_ideal) const; - string checkRoleReason(const PathEnd *end) const; - string checkRoleString(const PathEnd *end) const; + std::string checkRoleReason(const PathEnd *end) const; + std::string checkRoleString(const PathEnd *end) const; virtual void reportGroup(const PathEnd *end) const; void reportStartpoint(const PathEnd *end, const PathExpanded &expanded) const; @@ -209,13 +207,13 @@ protected: void reportEndpoint(const PathEndLatchCheck *end) const; const char *latchDesc(const PathEndLatchCheck *end) const; void reportStartpoint(const char *start, - const string reason) const; + const std::string reason) const; void reportEndpoint(const char *end, - const string reason) const; + const std::string reason) const; void reportStartEndPoint(const char *pt, - const string reason, + const std::string reason, const char *key) const; - string tgtClkName(const PathEnd *end) const; + std::string tgtClkName(const PathEnd *end) const; const char *clkRegLatchDesc(const PathEnd *end) const; void reportSrcPath(const PathEnd *end, const PathExpanded &expanded) const; @@ -285,13 +283,13 @@ protected: Arrival clk_time, const MinMax *min_max) const ; void reportRequired(const PathEnd *end, - string margin_msg) const ; + std::string margin_msg) const ; void reportSlack(const PathEnd *end) const ; void reportSlack(Slack slack) const ; void reportSpaceSlack(const PathEnd *end, - string &line) const ; + std::string &line) const ; void reportSpaceSlack(Slack slack, - string &line) const ; + std::string &line) const ; void reportSrcPathArrival(const PathEnd *end, const PathExpanded &expanded) const ; void reportPath(const PathEnd *end, @@ -362,7 +360,7 @@ protected: bool total_with_minus, const EarlyLate *early_late, const RiseFall *rf, - string src_attr, + std::string src_attr, const char *line_case) const; void reportLineTotal(const char *what, Delay incr, @@ -376,47 +374,47 @@ protected: const EarlyLate *early_late) const; void reportDashLineTotal() const; void reportDescription(const char *what, - string &result) const; + std::string &result) const; void reportDescription(const char *what, bool first_field, bool last_field, - string &result) const; + std::string &result) const; void reportFieldTime(float value, ReportField *field, - string &result) const; + std::string &result) const; void reportSpaceFieldTime(float value, - string &result) const; + std::string &result) const; void reportSpaceFieldDelay(Delay value, const EarlyLate *early_late, - string &result) const; + std::string &result) const; void reportFieldDelayMinus(Delay value, const EarlyLate *early_late, const ReportField *field, - string &result) const; + std::string &result) const; void reportTotalDelay(Delay value, const EarlyLate *early_late, - string &result) const; + std::string &result) const; void reportFieldDelay(Delay value, const EarlyLate *early_late, const ReportField *field, - string &result) const; + std::string &result) const; void reportField(float value, const ReportField *field, - string &result) const; + std::string &result) const; void reportField(const char *value, const ReportField *field, - string &result) const; + std::string &result) const; void reportFieldBlank(const ReportField *field, - string &result) const; + std::string &result) const; void reportDashLine() const; void reportDashLine(int line_width) const; void reportBlankLine() const; - string descriptionField(const Vertex *vertex) const; - string descriptionField(const Pin *pin) const; - string descriptionNet(const Pin *pin) const; + std::string descriptionField(const Vertex *vertex) const; + std::string descriptionField(const Pin *pin) const; + std::string descriptionNet(const Pin *pin) const; bool reportClkPath() const; - string clkName(const Clock *clk, - bool inverted) const; + std::string clkName(const Clock *clk, + bool inverted) const; bool hasExtInputDriver(const Pin *pin, const RiseFall *rf, const MinMax *min_max) const; diff --git a/search/Search.cc b/search/Search.cc index a8b14824..33239653 100644 --- a/search/Search.cc +++ b/search/Search.cc @@ -67,6 +67,7 @@ #include "Latches.hh" #include "Crpr.hh" #include "Genclks.hh" +#include "Variables.hh" namespace sta { @@ -91,10 +92,9 @@ EvalPred::setSearchThruLatches(bool thru_latches) bool EvalPred::searchThru(Edge *edge) { - const Sdc *sdc = sta_->sdc(); const TimingRole *role = edge->role(); return SearchPred0::searchThru(edge) - && (sdc->dynamicLoopBreaking() + && (sta_->variables()->dynamicLoopBreaking() || !edge->isDisabledLoop()) && !role->isTimingCheck() && (search_thru_latches_ @@ -121,12 +121,12 @@ DynLoopSrchPred::DynLoopSrchPred(TagGroupBldr *tag_bldr) : bool DynLoopSrchPred::loopEnabled(Edge *edge, - const Sdc *sdc, + bool dynamic_loop_breaking_enabled, const Graph *graph, Search *search) { return !edge->isDisabledLoop() - || (sdc->dynamicLoopBreaking() + || (dynamic_loop_breaking_enabled && hasPendingLoopPaths(edge, graph, search)); } @@ -179,14 +179,14 @@ bool SearchThru::searchThru(Edge *edge) { const Graph *graph = sta_->graph(); - const Sdc *sdc = sta_->sdc(); Search *search = sta_->search(); return EvalPred::searchThru(edge) // Only search thru latch D->Q if it is always open. // Enqueue thru latches is handled explicitly by search. && (edge->role() != TimingRole::latchDtoQ() || sta_->latches()->latchDtoQState(edge) == LatchEnableState::open) - && loopEnabled(edge, sdc, graph, search); + && loopEnabled(edge, sta_->variables()->dynamicLoopBreaking(), + graph, search); } ClkArrivalSearchPred::ClkArrivalSearchPred(const StaState *sta) : @@ -460,9 +460,9 @@ Search::findPathEnds(ExceptionFrom *from, bool clk_gating_hold) { findFilteredArrivals(from, thrus, to, unconstrained, true); - if (!sdc_->recoveryRemovalChecksEnabled()) + if (!variables_->recoveryRemovalChecksEnabled()) recovery = removal = false; - if (!sdc_->gatedClkChecksEnabled()) + if (!variables_->gatedClkChecksEnabled()) clk_gating_setup = clk_gating_hold = false; makePathGroups(group_path_count, endpoint_path_count, unique_pins, slack_min, slack_max, @@ -1112,7 +1112,7 @@ ArrivalVisitor::init(bool always_to_endpoints, { always_to_endpoints_ = always_to_endpoints; pred_ = pred; - crpr_active_ = sdc_->crprActive(); + crpr_active_ = crprActive(); } @@ -1231,7 +1231,7 @@ ArrivalVisitor::constrainedRequiredsInvalid(Vertex *vertex, } } // Gated clocks. - if (is_clk && sdc_->gatedClkChecksEnabled()) { + if (is_clk && variables_->gatedClkChecksEnabled()) { PinSet enable_pins(network_); search_->gatedClk()->gatedClkEnables(vertex, enable_pins); for (const Pin *enable : enable_pins) @@ -1798,11 +1798,11 @@ Search::seedInputDelayArrival(const Pin *pin, if (input_delay) { clk_edge = input_delay->clkEdge(); if (clk_edge == nullptr - && sdc_->useDefaultArrivalClock()) + && variables_->useDefaultArrivalClock()) clk_edge = sdc_->defaultArrivalClockEdge(); ref_pin = input_delay->refPin(); } - else if (sdc_->useDefaultArrivalClock()) + else if (variables_->useDefaultArrivalClock()) clk_edge = sdc_->defaultArrivalClockEdge(); if (ref_pin) { Vertex *ref_vertex = graph_->pinLoadVertex(ref_pin); @@ -2124,7 +2124,7 @@ PathVisitor::visitFromPath(const Pin *from_pin, Arrival to_arrival; if (from_clk_info->isGenClkSrcPath()) { if (!sdc_->clkStopPropagation(clk,from_pin,from_rf,to_pin,to_rf) - && (sdc_->clkThruTristateEnabled() + && (variables_->clkThruTristateEnabled() || !(role == TimingRole::tristateEnable() || role == TimingRole::tristateDisable()))) { const Clock *gclk = from_tag->genClkSrcPathClk(this); @@ -2148,7 +2148,8 @@ PathVisitor::visitFromPath(const Pin *from_pin, path_ap->corner()->findPathAnalysisPt(min_max->opposite()); Delay arc_delay_opp = search_->deratedDelay(from_vertex, arc, edge, true, path_ap_opp); - bool arc_delay_min_max_eq = fuzzyEqual(arc_delay, arc_delay_opp); + bool arc_delay_min_max_eq = + fuzzyEqual(delayAsFloat(arc_delay), delayAsFloat(arc_delay_opp)); to_tag = search_->thruClkTag(from_path, from_vertex, from_tag, true, edge, to_rf, arc_delay_min_max_eq, min_max, path_ap); @@ -2227,7 +2228,7 @@ PathVisitor::visitFromPath(const Pin *from_pin, // Propagate arrival as non-clock at the end of the clock tree. bool to_propagates_clk = !sdc_->clkStopPropagation(clk,from_pin,from_rf,to_pin,to_rf) - && (sdc_->clkThruTristateEnabled() + && (variables_->clkThruTristateEnabled() || !(role == TimingRole::tristateEnable() || role == TimingRole::tristateDisable())); arc_delay = search_->deratedDelay(from_vertex, arc, edge, @@ -2236,7 +2237,8 @@ PathVisitor::visitFromPath(const Pin *from_pin, path_ap->corner()->findPathAnalysisPt(min_max->opposite()); Delay arc_delay_opp = search_->deratedDelay(from_vertex, arc, edge, to_propagates_clk, path_ap_opp); - bool arc_delay_min_max_eq = fuzzyEqual(arc_delay, arc_delay_opp); + bool arc_delay_min_max_eq = + fuzzyEqual(delayAsFloat(arc_delay), delayAsFloat(arc_delay_opp)); to_tag = search_->thruClkTag(from_path, from_vertex, from_tag, to_propagates_clk, edge, to_rf, arc_delay_min_max_eq, @@ -2388,7 +2390,7 @@ Search::clkInfoWithCrprClkPath(ClkInfo *from_clk_info, Path *from_path, const PathAnalysisPt *path_ap) { - if (sdc_->crprActive()) + if (crprActive()) return findClkInfo(from_clk_info->clkEdge(), from_clk_info->clkSrc(), from_clk_info->isPropagated(), @@ -2489,7 +2491,7 @@ Search::thruClkInfo(Path *from_path, // the clkinfo. const Pin *gen_clk_src = nullptr; if (from_clk_info->isGenClkSrcPath() - && sdc_->crprActive() + && crprActive() && sdc_->isClock(to_pin)) { // Don't care that it could be a regular clock root. gen_clk_src = to_pin; @@ -2497,7 +2499,7 @@ Search::thruClkInfo(Path *from_path, } Path *to_crpr_clk_path = nullptr; - if (sdc_->crprActive() + if (crprActive() // Update crpr clk path for combinational paths leaving the clock // network (ie, tristate en->out) and buffer driving reg clk. && ((from_is_clk @@ -2772,7 +2774,7 @@ Search::reportArrivals(Vertex *vertex) const const PathAnalysisPt *path_ap = tag->pathAnalysisPt(this); const RiseFall *rf = tag->transition(); const char *req = delayAsString(path->required(), this); - string prev_str; + std::string prev_str; Path *prev_path = path->prevPath(); if (prev_path) { prev_str += prev_path->to_string(this); @@ -3244,7 +3246,7 @@ Search::isEndpoint(Vertex *vertex, return hasFanin(vertex, pred, graph_) && ((vertex->hasChecks() && hasEnabledChecks(vertex)) - || (sdc_->gatedClkChecksEnabled() + || (variables_->gatedClkChecksEnabled() && gated_clk_->isGatedClkEnable(vertex)) || vertex->isConstrained() || sdc_->isPathDelayInternalEndpoint(pin) diff --git a/search/SearchPred.cc b/search/SearchPred.cc index 04bb6025..9cb0401e 100644 --- a/search/SearchPred.cc +++ b/search/SearchPred.cc @@ -33,6 +33,7 @@ #include "Levelize.hh" #include "Search.hh" #include "Latches.hh" +#include "Variables.hh" namespace sta { @@ -59,19 +60,20 @@ SearchPred0::searchThru(Edge *edge) { const TimingRole *role = edge->role(); const Sdc *sdc = sta_->sdc(); + const Variables *variables = sta_->variables(); return !(edge->isDisabledConstraint() // Constants disable edge cond expression. || edge->isDisabledCond() || sdc->isDisabledCondDefault(edge) // Register/latch preset/clr edges are disabled by default. || (role == TimingRole::regSetClr() - && !sdc->presetClrArcsEnabled()) + && !variables->presetClrArcsEnabled()) // Constants on other pins disable this edge (ie, a mux select). || edge->simTimingSense() == TimingSense::none || (edge->isBidirectInstPath() - && !sdc->bidirectInstPathsEnabled()) + && !variables->bidirectInstPathsEnabled()) || (edge->isBidirectNetPath() - && !sdc->bidirectNetPathsEnabled()) + && !variables->bidirectNetPathsEnabled()) || (role == TimingRole::latchDtoQ() && sta_->latches()->latchDtoQState(edge) == LatchEnableState::closed)); @@ -152,12 +154,11 @@ ClkTreeSearchPred::ClkTreeSearchPred(const StaState *sta) : bool ClkTreeSearchPred::searchThru(Edge *edge) { - const Sdc *sdc = sta_->sdc(); // Propagate clocks through constants. const TimingRole *role = edge->role(); return (role->isWire() || role == TimingRole::combinational()) - && (sdc->clkThruTristateEnabled() + && (sta_->variables()->clkThruTristateEnabled() || !(role == TimingRole::tristateEnable() || role == TimingRole::tristateDisable())) && SearchPred1::searchThru(edge); diff --git a/search/Sta.cc b/search/Sta.cc index 75b1baf2..14ddc15e 100644 --- a/search/Sta.cc +++ b/search/Sta.cc @@ -44,6 +44,7 @@ #include "Graph.hh" #include "GraphCmp.hh" #include "Sdc.hh" +#include "Variables.hh" #include "WriteSdc.hh" #include "ExceptionPath.hh" #include "MakeConcreteParasitics.hh" @@ -283,6 +284,7 @@ Sta::Sta() : void Sta::makeComponents() { + makeVariables(); makeReport(); makeDebug(); makeUnits(); @@ -505,6 +507,12 @@ Sta::makePower() power_ = new Power(this); } +void +Sta::makeVariables() +{ + variables_ = new Variables(); +} + void Sta::setSta(Sta *sta) { @@ -519,6 +527,7 @@ Sta::sta() Sta::~Sta() { + delete variables_; // Verilog modules refer to the network in the sta so it has // to deleted before the network. delete verilog_reader_; @@ -1693,12 +1702,6 @@ Sta::isDisabledLoop(Edge *edge) const return levelize_->isDisabledLoop(edge); } -bool -Sta::isDisabledCondDefault(Edge *edge) -{ - return sdc_->isDisabledCondDefault(edge); -} - PinSet Sta::disabledConstantPins(Edge *edge) { @@ -1768,21 +1771,21 @@ Sta::exprConstantPins(FuncExpr *expr, bool Sta::isDisabledBidirectInstPath(Edge *edge) const { - return !sdc_->bidirectInstPathsEnabled() + return !variables_->bidirectInstPathsEnabled() && edge->isBidirectInstPath(); } bool Sta::isDisabledBidirectNetPath(Edge *edge) const { - return !sdc_->bidirectNetPathsEnabled() + return !variables_->bidirectNetPathsEnabled() && edge->isBidirectNetPath(); } bool Sta::isDisabledPresetClr(Edge *edge) const { - return !sdc_->presetClrArcsEnabled() + return !variables_->presetClrArcsEnabled() && edge->role() == TimingRole::regSetClr(); } @@ -2161,10 +2164,12 @@ Sta::checkTiming(bool no_input_delay, loops, generated_clks); } +//////////////////////////////////////////////////////////////// + bool Sta::crprEnabled() const { - return sdc_->crprEnabled(); + return variables_->crprEnabled(); } void @@ -2172,15 +2177,15 @@ Sta::setCrprEnabled(bool enabled) { // Pessimism is only relevant for on_chip_variation analysis. if (sdc_->analysisType() == AnalysisType::ocv - && enabled != sdc_->crprEnabled()) + && enabled != variables_->crprEnabled()) search_->arrivalsInvalid(); - sdc_->setCrprEnabled(enabled); + variables_->setCrprEnabled(enabled); } CrprMode Sta::crprMode() const { - return sdc_->crprMode(); + return variables_->crprMode(); } void @@ -2188,25 +2193,24 @@ Sta::setCrprMode(CrprMode mode) { // Pessimism is only relevant for on_chip_variation analysis. if (sdc_->analysisType() == AnalysisType::ocv - && sdc_->crprEnabled() - && sdc_->crprMode() != mode) + && variables_->crprEnabled() + && variables_->crprMode() != mode) search_->arrivalsInvalid(); - sdc_->setCrprMode(mode); + variables_->setCrprMode(mode); } bool Sta::pocvEnabled() const { - return pocv_enabled_; + return variables_->pocvEnabled(); } void Sta::setPocvEnabled(bool enabled) { - if (enabled != pocv_enabled_) + if (enabled != variables_->pocvEnabled()) delaysInvalid(); - pocv_enabled_ = enabled; - updateComponentsState(); + variables_->setPocvEnabled(enabled); } void @@ -2222,135 +2226,141 @@ Sta::setSigmaFactor(float factor) bool Sta::propagateGatedClockEnable() const { - return sdc_->propagateGatedClockEnable(); + return variables_->propagateGatedClockEnable(); } void Sta::setPropagateGatedClockEnable(bool enable) { - if (sdc_->propagateGatedClockEnable() != enable) + if (variables_->propagateGatedClockEnable() != enable) search_->arrivalsInvalid(); - sdc_->setPropagateGatedClockEnable(enable); + variables_->setPropagateGatedClockEnable(enable); } bool Sta::presetClrArcsEnabled() const { - return sdc_->presetClrArcsEnabled(); + return variables_->presetClrArcsEnabled(); } void Sta::setPresetClrArcsEnabled(bool enable) { - if (sdc_->presetClrArcsEnabled() != enable) { + if (variables_->presetClrArcsEnabled() != enable) { levelize_->invalid(); delaysInvalid(); } - sdc_->setPresetClrArcsEnabled(enable); + variables_->setPresetClrArcsEnabled(enable); } bool Sta::condDefaultArcsEnabled() const { - return sdc_->condDefaultArcsEnabled(); + return variables_->condDefaultArcsEnabled(); } void Sta::setCondDefaultArcsEnabled(bool enabled) { - if (sdc_->condDefaultArcsEnabled() != enabled) { + if (variables_->condDefaultArcsEnabled() != enabled) { delaysInvalid(); - sdc_->setCondDefaultArcsEnabled(enabled); + variables_->setCondDefaultArcsEnabled(enabled); } } bool Sta::bidirectInstPathsEnabled() const { - return sdc_->bidirectInstPathsEnabled(); + return variables_->bidirectInstPathsEnabled(); } void Sta::setBidirectInstPathsEnabled(bool enabled) { - if (sdc_->bidirectInstPathsEnabled() != enabled) { + if (variables_->bidirectInstPathsEnabled() != enabled) { levelize_->invalid(); delaysInvalid(); - sdc_->setBidirectInstPathsEnabled(enabled); + variables_->setBidirectInstPathsEnabled(enabled); } } bool Sta::bidirectNetPathsEnabled() const { - return sdc_->bidirectNetPathsEnabled(); + return variables_->bidirectNetPathsEnabled(); } void Sta::setBidirectNetPathsEnabled(bool enabled) { - if (sdc_->bidirectNetPathsEnabled() != enabled) { + if (variables_->bidirectNetPathsEnabled() != enabled) { delaysInvalid(); - sdc_->setBidirectNetPathsEnabled(enabled); + variables_->setBidirectNetPathsEnabled(enabled); } } bool Sta::recoveryRemovalChecksEnabled() const { - return sdc_->recoveryRemovalChecksEnabled(); + return variables_->recoveryRemovalChecksEnabled(); } void Sta::setRecoveryRemovalChecksEnabled(bool enabled) { - if (sdc_->recoveryRemovalChecksEnabled() != enabled) { + if (variables_->recoveryRemovalChecksEnabled() != enabled) { search_->arrivalsInvalid(); - sdc_->setRecoveryRemovalChecksEnabled(enabled); + variables_->setRecoveryRemovalChecksEnabled(enabled); } } bool Sta::gatedClkChecksEnabled() const { - return sdc_->gatedClkChecksEnabled(); + return variables_->gatedClkChecksEnabled(); } void Sta::setGatedClkChecksEnabled(bool enabled) { - if (sdc_->gatedClkChecksEnabled() != enabled) { + if (variables_->gatedClkChecksEnabled() != enabled) { search_->arrivalsInvalid(); - sdc_->setGatedClkChecksEnabled(enabled); + variables_->setGatedClkChecksEnabled(enabled); } } bool Sta::dynamicLoopBreaking() const { - return sdc_->dynamicLoopBreaking(); + return variables_->dynamicLoopBreaking(); } void Sta::setDynamicLoopBreaking(bool enable) { - if (sdc_->dynamicLoopBreaking() != enable) { - sdc_->setDynamicLoopBreaking(enable); + if (variables_->dynamicLoopBreaking() != enable) { + if (levelize_->levelized()) { + if (enable) + sdc_->makeLoopExceptions(); + else + sdc_->deleteLoopExceptions(); + } search_->arrivalsInvalid(); + variables_->setDynamicLoopBreaking(enable); } } bool Sta::useDefaultArrivalClock() const { - return sdc_->useDefaultArrivalClock(); + return variables_->useDefaultArrivalClock(); } void Sta::setUseDefaultArrivalClock(bool enable) { - if (sdc_->useDefaultArrivalClock() != enable) { - sdc_->setUseDefaultArrivalClock(enable); + if (variables_->useDefaultArrivalClock() != enable) { + variables_->setUseDefaultArrivalClock(enable); search_->arrivalsInvalid(); } } @@ -2358,27 +2368,27 @@ Sta::setUseDefaultArrivalClock(bool enable) bool Sta::propagateAllClocks() const { - return sdc_->propagateAllClocks(); + return variables_->propagateAllClocks(); } void Sta::setPropagateAllClocks(bool prop) { - sdc_->setPropagateAllClocks(prop); + variables_->setPropagateAllClocks(prop); } bool Sta::clkThruTristateEnabled() const { - return sdc_->clkThruTristateEnabled(); + return variables_->clkThruTristateEnabled(); } void Sta::setClkThruTristateEnabled(bool enable) { - if (enable != sdc_->clkThruTristateEnabled()) { + if (enable != variables_->clkThruTristateEnabled()) { search_->arrivalsInvalid(); - sdc_->setClkThruTristateEnabled(enable); + variables_->setClkThruTristateEnabled(enable); } } @@ -3207,7 +3217,7 @@ Sta::findRequired(Vertex *vertex) searchPreamble(); search_->findAllArrivals(); search_->findRequireds(vertex->level()); - if (sdc_->crprEnabled() + if (variables_->crprEnabled() && search_->crprPathPruningEnabled() && !search_->crprApproxMissingRequireds() // Clocks invariably have requireds that are pruned but it isn't @@ -4856,12 +4866,11 @@ FanInOutSrchPred::searchFrom(const Vertex *from_vertex) bool FanInOutSrchPred::searchThru(Edge *edge) { - const Sdc *sdc = sta_->sdc(); return searchThruRole(edge) && (thru_disabled_ || !(edge->isDisabledConstraint() || edge->isDisabledCond() - || sdc->isDisabledCondDefault(edge))) + || sta_->isDisabledCondDefault(edge))) && (thru_constants_ || edge->simTimingSense() != TimingSense::none); } diff --git a/search/StaState.cc b/search/StaState.cc index bf457a2f..c9eb7438 100644 --- a/search/StaState.cc +++ b/search/StaState.cc @@ -29,6 +29,10 @@ #include "DispatchQueue.hh" #include "Units.hh" #include "Network.hh" +#include "Variables.hh" +#include "Sdc.hh" +#include "Graph.hh" +#include "TimingArc.hh" namespace sta { @@ -48,9 +52,9 @@ StaState::StaState() : search_(nullptr), latches_(nullptr), clk_network_(nullptr), + variables_(nullptr), thread_count_(1), dispatch_queue_(nullptr), - pocv_enabled_(false), sigma_factor_(1.0) { } @@ -108,4 +112,18 @@ StaState::setDebug(Debug *debug) debug_ = debug; } +bool +StaState::crprActive() const +{ + return sdc_->analysisType() == AnalysisType::ocv + && variables_->crprEnabled(); +} + +bool +StaState::isDisabledCondDefault(Edge *edge) const +{ + return !variables_->condDefaultArcsEnabled() + && edge->timingArcSet()->isCondDefault(); +} + } // namespace diff --git a/search/Tag.cc b/search/Tag.cc index 96ea0eda..69269cf8 100644 --- a/search/Tag.cc +++ b/search/Tag.cc @@ -89,20 +89,20 @@ Tag::~Tag() delete states_; } -string +std::string Tag::to_string(const StaState *sta) const { return to_string(true, true, sta); } -string +std::string Tag::to_string(bool report_index, bool report_rf_min_max, const StaState *sta) const { const Network *network = sta->network(); const Corners *corners = sta->corners(); - string result; + std::string result; if (report_index) result += std::to_string(index_); @@ -418,7 +418,7 @@ tagMatch(const Tag *tag1, && tag1->isSegmentStart() == tag2->isSegmentStart() && clk_info1->isGenClkSrcPath() == clk_info2->isGenClkSrcPath() && (!match_crpr_clk_pin - || !sta->sdc()->crprActive() + || !sta->crprActive() || clk_info1->crprClkVertexId(sta) == clk_info2->crprClkVertexId(sta)) && tagStateEqual(tag1, tag2)); } @@ -479,7 +479,7 @@ tagMatchCmp(const Tag *tag1, return 1; if (match_crpr_clk_pin - && sta->sdc()->crprActive()) { + && sta->crprActive()) { VertexId crpr_vertex1 = clk_info1->crprClkVertexId(sta); VertexId crpr_vertex2 = clk_info2->crprClkVertexId(sta); if (crpr_vertex1 < crpr_vertex2) diff --git a/search/Tag.hh b/search/Tag.hh index 00a1bf1b..4317cd4b 100644 --- a/search/Tag.hh +++ b/search/Tag.hh @@ -62,10 +62,10 @@ public: bool own_states, const StaState *sta); ~Tag(); - string to_string(const StaState *sta) const; - string to_string(bool report_index, - bool report_rf_min_max, - const StaState *sta) const; + std::string to_string(const StaState *sta) const; + std::string to_string(bool report_index, + bool report_rf_min_max, + const StaState *sta) const; ClkInfo *clkInfo() const { return clk_info_; } bool isClock() const { return is_clk_; } const ClockEdge *clkEdge() const; diff --git a/search/TagGroup.hh b/search/TagGroup.hh index 2d36aedf..a54f9045 100644 --- a/search/TagGroup.hh +++ b/search/TagGroup.hh @@ -144,7 +144,7 @@ protected: Vertex *vertex_; int default_path_count_; PathIndexMap path_index_map_; - vector paths_; + std::vector paths_; bool has_clk_tag_; bool has_genclk_src_tag_; bool has_filter_tag_; diff --git a/search/VisitPathEnds.cc b/search/VisitPathEnds.cc index 561b5fb2..5345627f 100644 --- a/search/VisitPathEnds.cc +++ b/search/VisitPathEnds.cc @@ -39,6 +39,7 @@ #include "PathEnd.hh" #include "Search.hh" #include "GatedClk.hh" +#include "Variables.hh" namespace sta { @@ -122,7 +123,7 @@ VisitPathEnds::visitClkedPathEnds(const Pin *pin, is_constrained = true; } } - if (sdc_->gatedClkChecksEnabled()) + if (variables_->gatedClkChecksEnabled()) visitGatedClkEnd(pin, vertex, path, end_rf, path_ap, filtered, visitor, is_constrained); visitDataCheckEnd(pin, path, end_rf, path_ap, filtered, visitor, @@ -288,7 +289,7 @@ VisitPathEnds::checkEdgeEnabled(Edge *edge) const && !sdc_->isDisabledCondDefault(edge) && !((check_role == TimingRole::recovery() || check_role == TimingRole::removal()) - && !sdc_->recoveryRemovalChecksEnabled()); + && !variables_->recoveryRemovalChecksEnabled()); } void diff --git a/spice/WriteSpice.cc b/spice/WriteSpice.cc index 1be4e187..64a4f635 100644 --- a/spice/WriteSpice.cc +++ b/spice/WriteSpice.cc @@ -46,6 +46,7 @@ namespace sta { using std::ifstream; +using std::ofstream; using std::swap; using std::set; @@ -183,8 +184,8 @@ WriteSpice::replaceFileExt(string filename, void WriteSpice::writeGnuplotFile(StdStringSeq &node_nanes) { - string gnuplot_filename = replaceFileExt(spice_filename_, "gnuplot"); - string csv_filename = replaceFileExt(spice_filename_, "csv"); + std::string gnuplot_filename = replaceFileExt(spice_filename_, "gnuplot"); + std::string csv_filename = replaceFileExt(spice_filename_, "csv"); ofstream gnuplot_stream; gnuplot_stream.open(gnuplot_filename); if (gnuplot_stream.is_open()) { diff --git a/spice/WriteSpice.hh b/spice/WriteSpice.hh index 0396764c..05be3912 100644 --- a/spice/WriteSpice.hh +++ b/spice/WriteSpice.hh @@ -39,13 +39,10 @@ namespace sta { -using std::string; -using std::ofstream; - typedef std::map ParasiticNodeMap; -typedef Map CellSpicePortNames; +typedef Map CellSpicePortNames; typedef Map LibertyPortLogicValues; -typedef std::vector StdStringSeq; +typedef std::vector StdStringSeq; // Utilities for writing a spice deck. class WriteSpice : public StaState @@ -63,7 +60,7 @@ public: protected: void initPowerGnd(); - void writeHeader(string &title, + void writeHeader(std::string &title, float max_time, float time_step); void writePrintStmt(StdStringSeq &node_names); @@ -128,10 +125,10 @@ protected: const RiseFall *from_rf, const Pin *to_pin, const RiseFall *to_rf, - string prefix); + std::string prefix); void writeMeasureSlewStmt(const Pin *pin, const RiseFall *rf, - string prefix); + std::string prefix); const char *spiceTrans(const RiseFall *rf); float findSlew(Vertex *vertex, const RiseFall *rf, @@ -164,8 +161,8 @@ protected: InstanceSet &written_insts); PinSeq drvrLoads(const Pin *drvr_pin); void writeSubcktInstVoltSrcs(); - string replaceFileExt(string filename, - const char *ext); + std::string replaceFileExt(std::string filename, + const char *ext); const char *spice_filename_; const char *subckt_filename_; @@ -176,7 +173,7 @@ protected: CircuitSim ckt_sim_; const DcalcAnalysisPt *dcalc_ap_; - ofstream spice_stream_; + std::ofstream spice_stream_; LibertyLibrary *default_library_; float power_voltage_; float gnd_voltage_; @@ -193,7 +190,7 @@ protected: }; void -streamPrint(ofstream &stream, +streamPrint(std::ofstream &stream, const char *fmt, ...) __attribute__((format (printf, 2, 3))); diff --git a/test/prima3.ok b/test/prima3.ok index cb6d66b9..98c9c3cd 100644 --- a/test/prima3.ok +++ b/test/prima3.ok @@ -1,9 +1,3 @@ -Warning: asap7_simple.lib.gz line 71510, when attribute inside table model. -Warning: asap7_simple.lib.gz line 71986, when attribute inside table model. -Warning: asap7_simple.lib.gz line 72462, when attribute inside table model. -Warning: asap7_simple.lib.gz line 72938, when attribute inside table model. -Warning: asap7_simple.lib.gz line 73414, when attribute inside table model. -Warning: asap7_simple.lib.gz line 74830, when attribute inside table model. Warning: asap7_simple.lib.gz line 71029, timing group from output port. Warning: asap7_simple.lib.gz line 71505, timing group from output port. Warning: asap7_simple.lib.gz line 71981, timing group from output port. @@ -11,8 +5,6 @@ Warning: asap7_simple.lib.gz line 72457, timing group from output port. Warning: asap7_simple.lib.gz line 72933, timing group from output port. Warning: asap7_simple.lib.gz line 73409, timing group from output port. Warning: asap7_simple.lib.gz line 73885, timing group from output port. -Warning: asap7_simple.lib.gz line 82276, when attribute inside table model. -Warning: asap7_simple.lib.gz line 83692, when attribute inside table model. Warning: asap7_simple.lib.gz line 81795, timing group from output port. Warning: asap7_simple.lib.gz line 82271, timing group from output port. Warning: asap7_simple.lib.gz line 82747, timing group from output port. diff --git a/util/MachineLinux.cc b/util/MachineLinux.cc index 104b8717..231634d6 100644 --- a/util/MachineLinux.cc +++ b/util/MachineLinux.cc @@ -81,7 +81,7 @@ systemRunTime() size_t memoryUsage() { - string proc_filename; + std::string proc_filename; stringPrint(proc_filename, "/proc/%d/status", getpid()); size_t memory = 0; FILE *status = fopen(proc_filename.c_str(), "r"); diff --git a/util/Report.cc b/util/Report.cc index d3fdda65..e541606c 100644 --- a/util/Report.cc +++ b/util/Report.cc @@ -111,7 +111,7 @@ Report::reportLineString(const char *line) } void -Report::reportLineString(const string &line) +Report::reportLineString(const std::string &line) { printLine(line.c_str(), line.length()); } diff --git a/util/StringUtil.cc b/util/StringUtil.cc index b2d604f3..e9b0d74a 100644 --- a/util/StringUtil.cc +++ b/util/StringUtil.cc @@ -37,6 +37,7 @@ namespace sta { using std::max; +using std::string; static void stringPrintTmp(const char *fmt, diff --git a/verilog/VerilogLex.ll b/verilog/VerilogLex.ll index 01c9e06b..af6a01be 100644 --- a/verilog/VerilogLex.ll +++ b/verilog/VerilogLex.ll @@ -93,22 +93,22 @@ ID_TOKEN {ID_ESCAPED_TOKEN}|{ID_ALPHA_TOKEN} } {SIGN}?{UNSIGNED_NUMBER}?"'"[sS]?[bB][01_xz]+ { - yylval->constant = new string(yytext); + yylval->constant = new std::string(yytext); return token::CONSTANT; } {SIGN}?{UNSIGNED_NUMBER}?"'"[sS]?[oO][0-7_xz]+ { - yylval->constant = new string(yytext); + yylval->constant = new std::string(yytext); return token::CONSTANT; } {SIGN}?{UNSIGNED_NUMBER}?"'"[sS]?[dD][0-9_]+ { - yylval->constant = new string(yytext); + yylval->constant = new std::string(yytext); return token::CONSTANT; } {SIGN}?{UNSIGNED_NUMBER}?"'"[sS]?[hH][0-9a-fA-F_xz]+ { - yylval->constant = new string(yytext); + yylval->constant = new std::string(yytext); return token::CONSTANT; } @@ -140,7 +140,7 @@ wire { return token::WIRE; } wor { return token::WOR; } {ID_TOKEN}("."{ID_TOKEN})* { - yylval->string = new string(yytext, yyleng); + yylval->string = new std::string(yytext, yyleng); return token::ID; } @@ -152,7 +152,7 @@ wor { return token::WOR; } {BLANK} { /* ignore blanks */ } \" { - yylval->string = new string; + yylval->string = new std::string; BEGIN(QSTRING); } diff --git a/verilog/VerilogParse.yy b/verilog/VerilogParse.yy index acaf3ae0..c25de12a 100644 --- a/verilog/VerilogParse.yy +++ b/verilog/VerilogParse.yy @@ -42,7 +42,7 @@ void sta::VerilogParse::error(const location_type &loc, - const string &msg) + const std::string &msg) { reader->report()->fileError(164,reader->filename(),loc.begin.line, "%s",msg.c_str()); @@ -521,7 +521,7 @@ attr_spec_value: | STRING { $$ = $1; } | INT - { $$ = new string(std::to_string($1)); } + { $$ = new std::string(std::to_string($1)); } ; %% diff --git a/verilog/VerilogReader.cc b/verilog/VerilogReader.cc index 3baea0e5..96fe9ca6 100644 --- a/verilog/VerilogReader.cc +++ b/verilog/VerilogReader.cc @@ -41,6 +41,8 @@ namespace sta { +using std::string; + typedef unsigned long long VerilogConstant10; static string @@ -351,7 +353,7 @@ VerilogReader::makeNamedPortRefCellPorts(Cell *cell, // Make sure each declaration appears in the module port list. void VerilogReader::checkModuleDcls(VerilogModule *module, - set &port_names) + std::set &port_names) { for (auto const & [port_name, dcl] : *module->declarationMap()) { PortDirection *dir = dcl->direction(); @@ -1641,13 +1643,13 @@ VerilogAttrEntry::VerilogAttrEntry(const string &key, { } -std::string +string VerilogAttrEntry::key() { return key_; } -std::string +string VerilogAttrEntry::value() { return value_; diff --git a/verilog/VerilogReader.hh b/verilog/VerilogReader.hh index 223b98b6..aca56682 100644 --- a/verilog/VerilogReader.hh +++ b/verilog/VerilogReader.hh @@ -70,10 +70,6 @@ typedef Vector VerilogAttrStmtSeq; typedef Vector VerilogAttrEntrySeq; typedef Vector VerilogErrorSeq; -using std::string; -using std::vector; -using std::set; - class VerilogReader { public: @@ -81,12 +77,12 @@ public: ~VerilogReader(); bool read(const char *filename); - void makeModule(const string *module_name, + void makeModule(const std::string *module_name, VerilogNetSeq *ports, VerilogStmtSeq *stmts, VerilogAttrStmtSeq *attr_stmts, int line); - void makeModule(const string *module_name, + void makeModule(const std::string *module_name, VerilogStmtSeq *port_dcls, VerilogStmtSeq *stmts, VerilogAttrStmtSeq *attr_stmts, @@ -99,7 +95,7 @@ public: VerilogDclArg *arg, VerilogAttrStmtSeq *attr_stmts, int line); - VerilogDclArg *makeDclArg(const string *net_name); + VerilogDclArg *makeDclArg(const std::string *net_name); VerilogDclArg*makeDclArg(VerilogAssign *assign); VerilogDclBus *makeDclBus(PortDirection *dir, int from_index, @@ -113,36 +109,36 @@ public: VerilogDclArgSeq *args, VerilogAttrStmtSeq *attr_stmts, int line); - VerilogInst *makeModuleInst(const string *module_name, - const string *inst_name, + VerilogInst *makeModuleInst(const std::string *module_name, + const std::string *inst_name, VerilogNetSeq *pins, VerilogAttrStmtSeq *attr_stmts, const int line); VerilogAssign *makeAssign(VerilogNet *lhs, VerilogNet *rhs, int line); - VerilogNetScalar *makeNetScalar(const string *name); - VerilogNetPortRef *makeNetNamedPortRefScalarNet(const string *port_vname); - VerilogNetPortRef *makeNetNamedPortRefScalarNet(const string *port_name, - const string *net_name); - VerilogNetPortRef *makeNetNamedPortRefBitSelect(const string *port_name, - const string *bus_name, + VerilogNetScalar *makeNetScalar(const std::string *name); + VerilogNetPortRef *makeNetNamedPortRefScalarNet(const std::string *port_vname); + VerilogNetPortRef *makeNetNamedPortRefScalarNet(const std::string *port_name, + const std::string *net_name); + VerilogNetPortRef *makeNetNamedPortRefBitSelect(const std::string *port_name, + const std::string *bus_name, int index); - VerilogNetPortRef *makeNetNamedPortRefScalar(const string *port_name, + VerilogNetPortRef *makeNetNamedPortRefScalar(const std::string *port_name, VerilogNet *net); - VerilogNetPortRef *makeNetNamedPortRefBit(const string *port_name, + VerilogNetPortRef *makeNetNamedPortRefBit(const std::string *port_name, int index, VerilogNet *net); - VerilogNetPortRef *makeNetNamedPortRefPart(const string *port_name, + VerilogNetPortRef *makeNetNamedPortRefPart(const std::string *port_name, int from_index, int to_index, VerilogNet *net); VerilogNetConcat *makeNetConcat(VerilogNetSeq *nets); - VerilogNetConstant *makeNetConstant(const string *constant, + VerilogNetConstant *makeNetConstant(const std::string *constant, int line); - VerilogNetBitSelect *makeNetBitSelect(const string *name, + VerilogNetBitSelect *makeNetBitSelect(const std::string *name, int index); - VerilogNetPartSelect *makeNetPartSelect(const string *name, + VerilogNetPartSelect *makeNetPartSelect(const std::string *name, int from_index, int to_index); VerilogModule *module(Cell *cell); @@ -160,11 +156,11 @@ public: const char *filename, int line, const char *fmt, ...); - const string &zeroNetName() const { return zero_net_name_; } - const string &oneNetName() const { return one_net_name_; } + const std::string &zeroNetName() const { return zero_net_name_; } + const std::string &oneNetName() const { return one_net_name_; } void deleteModules(); void reportStmtCounts(); - const string &constant10Max() const { return constant10_max_; } + const std::string &constant10Max() const { return constant10_max_; } protected: void init(const char *filename); @@ -173,13 +169,13 @@ protected: VerilogNetSeq *ports); Port *makeCellPort(Cell *cell, VerilogModule *module, - const string &port_name); + const std::string &port_name); void makeNamedPortRefCellPorts(Cell *cell, VerilogModule *module, VerilogNet *mod_port, StdStringSet &port_names); void checkModuleDcls(VerilogModule *module, - set &port_names); + std::set &port_names); void makeModuleInstBody(VerilogModule *module, Instance *inst, VerilogBindingTbl *bindings, @@ -230,7 +226,7 @@ protected: bool is_leaf); void makeInstPin(Instance *inst, Port *port, - const string &net_name, + const std::string &net_name, VerilogBindingTbl *bindings, Instance *parent, VerilogBindingTbl *parent_bindings, @@ -259,7 +255,7 @@ protected: bool hasScalarNamedPortRefs(LibertyCell *liberty_cell, VerilogNetSeq *pins); - string filename_; + std::string filename_; Report *report_; Debug *debug_; NetworkReader *network_; @@ -268,9 +264,9 @@ protected: int black_box_index_; VerilogModuleMap module_map_; VerilogErrorSeq link_errors_; - const string zero_net_name_; - const string one_net_name_; - string constant10_max_; + const std::string zero_net_name_; + const std::string one_net_name_; + std::string constant10_max_; ViewType *view_type_; bool report_stmt_stats_; int module_count_; diff --git a/verilog/VerilogReaderPvt.hh b/verilog/VerilogReaderPvt.hh index 35be91f1..aa1dc207 100644 --- a/verilog/VerilogReaderPvt.hh +++ b/verilog/VerilogReaderPvt.hh @@ -32,9 +32,9 @@ namespace sta { -typedef Map VerilogDclMap; +typedef Map VerilogDclMap; typedef Vector VerilogConstantValue; -typedef vector StdStringSeq; +typedef std::vector StdStringSeq; class VerilogStmt { @@ -55,19 +55,19 @@ private: class VerilogModule : public VerilogStmt { public: - VerilogModule(const string &name, + VerilogModule(const std::string &name, VerilogNetSeq *ports, VerilogStmtSeq *stmts, VerilogAttrStmtSeq *attr_stmts, - const string &filename, + const std::string &filename, int line, VerilogReader *reader); virtual ~VerilogModule(); - const string &name() { return name_; } + const std::string &name() { return name_; } const char *filename() { return filename_.c_str(); } VerilogAttrStmtSeq *attrStmts() { return attr_stmts_; } VerilogNetSeq *ports() { return ports_; } - VerilogDcl *declaration(const string &net_name); + VerilogDcl *declaration(const std::string &net_name); VerilogStmtSeq *stmts() { return stmts_; } VerilogDclMap *declarationMap() { return &dcl_map_; } void parseDcl(VerilogDcl *dcl, @@ -79,8 +79,8 @@ private: StdStringSet &inst_names, VerilogReader *reader); - string name_; - string filename_; + std::string name_; + std::string filename_; VerilogNetSeq *ports_; VerilogStmtSeq *stmts_; VerilogDclMap dcl_map_; @@ -99,7 +99,7 @@ public: VerilogAttrStmtSeq *attr_stmts, int line); virtual ~VerilogDcl(); - const string &portName(); + const std::string &portName(); virtual bool isBus() const { return false; } virtual bool isDeclaration() const { return true; } VerilogDclArgSeq *args() const { return args_; } @@ -143,15 +143,15 @@ private: class VerilogDclArg { public: - VerilogDclArg(const string &net_name); + VerilogDclArg(const std::string &net_name); VerilogDclArg(VerilogAssign *assign); ~VerilogDclArg(); - const string &netName(); + const std::string &netName(); bool isNamed() const { return assign_ == nullptr; } VerilogAssign *assign() { return assign_; } private: - string net_name_; + std::string net_name_; VerilogAssign *assign_; }; @@ -175,37 +175,37 @@ private: class VerilogInst : public VerilogStmt { public: - VerilogInst(const string &inst_name, + VerilogInst(const std::string &inst_name, VerilogAttrStmtSeq *attr_stmts, const int line); virtual ~VerilogInst(); virtual bool isInstance() const { return true; } - const string &instanceName() const { return inst_name_; } + const std::string &instanceName() const { return inst_name_; } VerilogAttrStmtSeq *attrStmts() const { return attr_stmts_; } - void setInstanceName(const string &inst_name); + void setInstanceName(const std::string &inst_name); private: - string inst_name_; + std::string inst_name_; VerilogAttrStmtSeq *attr_stmts_; }; class VerilogModuleInst : public VerilogInst { public: - VerilogModuleInst(const string &module_name, - const string &inst_name, + VerilogModuleInst(const std::string &module_name, + const std::string &inst_name, VerilogNetSeq *pins, VerilogAttrStmtSeq *attr_stmts, const int line); virtual ~VerilogModuleInst(); virtual bool isModuleInst() const { return true; } - const string &moduleName() const { return module_name_; } + const std::string &moduleName() const { return module_name_; } VerilogNetSeq *pins() const { return pins_; } bool namedPins(); bool hasPins(); private: - string module_name_; + std::string module_name_; VerilogNetSeq *pins_; }; @@ -216,7 +216,7 @@ class VerilogLibertyInst : public VerilogInst { public: VerilogLibertyInst(LibertyCell *cell, - const string &inst_name, + const std::string &inst_name, const StdStringSeq &net_names, VerilogAttrStmtSeq *attr_stmts, const int line); @@ -236,7 +236,7 @@ public: VerilogNet() {} virtual ~VerilogNet() {} virtual bool isNamed() const = 0; - virtual const string &name() const = 0; + virtual const std::string &name() const = 0; virtual bool isNamedPortRef() { return false; } virtual bool isNamedPortRefScalarNet() const { return false; } virtual int size(VerilogModule *module) = 0; @@ -249,30 +249,30 @@ class VerilogNetUnnamed : public VerilogNet public: VerilogNetUnnamed() {} bool isNamed() const override { return false; } - const string &name() const override { return null_; } + const std::string &name() const override { return null_; } private: - static const string null_; + static const std::string null_; }; class VerilogNetNamed : public VerilogNet { public: - VerilogNetNamed(const string &name); + VerilogNetNamed(const std::string &name); virtual ~VerilogNetNamed(); bool isNamed() const override { return true; } virtual bool isScalar() const = 0; - const string &name() const override { return name_; } + const std::string &name() const override { return name_; } protected: - string name_; + std::string name_; }; // Named net reference, which could be the name of a scalar or bus signal. class VerilogNetScalar : public VerilogNetNamed { public: - VerilogNetScalar(const string &name); + VerilogNetScalar(const std::string &name); virtual bool isScalar() const { return true; } virtual int size(VerilogModule *module); virtual VerilogNetNameIterator *nameIterator(VerilogModule *module, @@ -282,7 +282,7 @@ public: class VerilogNetBitSelect : public VerilogNetNamed { public: - VerilogNetBitSelect(const string &name, + VerilogNetBitSelect(const std::string &name, int index); int index() { return index_; } virtual bool isScalar() const { return false; } @@ -296,7 +296,7 @@ private: class VerilogNetPartSelect : public VerilogNetNamed { public: - VerilogNetPartSelect(const string &name, + VerilogNetPartSelect(const std::string &name, int from_index, int to_index); virtual bool isScalar() const { return false; } @@ -314,7 +314,7 @@ private: class VerilogNetConstant : public VerilogNetUnnamed { public: - VerilogNetConstant(const string *constant, + VerilogNetConstant(const std::string *constant, VerilogReader *reader, int line); virtual ~VerilogNetConstant(); @@ -323,14 +323,14 @@ public: VerilogReader *reader); private: - void parseConstant(const string *constant, + void parseConstant(const std::string *constant, VerilogReader *reader, int line); - void parseConstant(const string *constant, + void parseConstant(const std::string *constant, size_t base_idx, int base, int digit_bit_count); - void parseConstant10(const string *constant, + void parseConstant10(const std::string *constant, size_t base_idx, VerilogReader *reader, int line); @@ -355,7 +355,7 @@ private: class VerilogNetPortRef : public VerilogNetScalar { public: - VerilogNetPortRef(const string &name); + VerilogNetPortRef(const std::string &name); virtual bool isNamedPortRef() { return true; } virtual bool hasNet() = 0; }; @@ -367,26 +367,26 @@ public: class VerilogNetPortRefScalarNet : public VerilogNetPortRef { public: - VerilogNetPortRefScalarNet(const string &name); - VerilogNetPortRefScalarNet(const string &name, - const string &net_name); + VerilogNetPortRefScalarNet(const std::string &name); + VerilogNetPortRefScalarNet(const std::string &name, + const std::string &net_name); virtual bool isScalar() const { return true; } virtual bool isNamedPortRefScalarNet() const { return true; } virtual int size(VerilogModule *module); virtual VerilogNetNameIterator *nameIterator(VerilogModule *module, VerilogReader *reader); virtual bool hasNet() { return !net_name_.empty(); } - const string &netName() const { return net_name_; } - void setNetName(const string &net_name) { net_name_ = net_name; } + const std::string &netName() const { return net_name_; } + void setNetName(const std::string &net_name) { net_name_ = net_name; } private: - string net_name_; + std::string net_name_; }; class VerilogNetPortRefScalar : public VerilogNetPortRef { public: - VerilogNetPortRefScalar(const string &name, + VerilogNetPortRefScalar(const std::string &name, VerilogNet *net); virtual ~VerilogNetPortRefScalar(); virtual bool isScalar() const { return true; } @@ -402,23 +402,23 @@ private: class VerilogNetPortRefBit : public VerilogNetPortRefScalar { public: - VerilogNetPortRefBit(const string &name, + VerilogNetPortRefBit(const std::string &name, int index, VerilogNet *net); - const string &name() const override { return bit_name_; } + const std::string &name() const override { return bit_name_; } private: - string bit_name_; + std::string bit_name_; }; class VerilogNetPortRefPart : public VerilogNetPortRefBit { public: - VerilogNetPortRefPart(const string &name, + VerilogNetPortRefPart(const std::string &name, int from_index, int to_index, VerilogNet *net); - const string &name() const override; + const std::string &name() const override; int toIndex() const { return to_index_; } private: @@ -426,7 +426,7 @@ private: }; // Abstract class for iterating over the component nets of a net. -class VerilogNetNameIterator : public Iterator +class VerilogNetNameIterator : public Iterator { }; @@ -444,15 +444,15 @@ private: class VerilogAttrEntry { public: - VerilogAttrEntry(const string &key, - const string &value); - virtual string key(); - virtual string value(); + VerilogAttrEntry(const std::string &key, + const std::string &value); + virtual std::string key(); + virtual std::string value(); virtual ~VerilogAttrEntry() = default; private: - string key_; - string value_; + std::string key_; + std::string value_; }; } // namespace diff --git a/verilog/VerilogWriter.cc b/verilog/VerilogWriter.cc index 6fe3485a..52c9d548 100644 --- a/verilog/VerilogWriter.cc +++ b/verilog/VerilogWriter.cc @@ -39,6 +39,7 @@ namespace sta { using std::min; using std::max; +using std::string; class VerilogWriter { @@ -179,7 +180,7 @@ void VerilogWriter::writeModule(const Instance *inst) { Cell *cell = network_->cell(inst); - string cell_vname = cellVerilogName(network_->name(cell)); + std::string cell_vname = cellVerilogName(network_->name(cell)); fprintf(stream_, "module %s (", cell_vname.c_str()); writePorts(cell); writePortDcls(cell); @@ -202,7 +203,7 @@ VerilogWriter::writePorts(const Cell *cell) || !network_->direction(port)->isPowerGround()) { if (!first) fprintf(stream_, ",\n "); - string verilog_name = portVerilogName(network_->name(port)); + std::string verilog_name = portVerilogName(network_->name(port)); fprintf(stream_, "%s", verilog_name.c_str()); first = false; } @@ -220,7 +221,7 @@ VerilogWriter::writePortDcls(const Cell *cell) PortDirection *dir = network_->direction(port); if (include_pwr_gnd_ || !network_->direction(port)->isPowerGround()) { - string port_vname = portVerilogName(network_->name(port)); + std::string port_vname = portVerilogName(network_->name(port)); const char *vtype = verilogPortDir(dir); if (vtype) { fprintf(stream_, " %s", vtype); @@ -274,7 +275,7 @@ VerilogWriter::writeWireDcls(const Instance *inst) { Cell *cell = network_->cell(inst); char escape = network_->pathEscape(); - Map> bus_ranges; + Map> bus_ranges; NetIterator *net_iter = network_->netIterator(inst); while (net_iter->hasNext()) { Net *net = net_iter->next(); @@ -284,7 +285,7 @@ VerilogWriter::writeWireDcls(const Instance *inst) if (network_->findPort(cell, net_name) == nullptr) { if (isBusName(net_name, '[', ']', escape)) { bool is_bus; - string bus_name; + std::string bus_name; int index; parseBusName(net_name, '[', ']', escape, is_bus, bus_name, index); BusIndexRange &range = bus_ranges[bus_name]; @@ -292,7 +293,7 @@ VerilogWriter::writeWireDcls(const Instance *inst) range.second = min(range.second, index); } else { - string net_vname = netVerilogName(net_name); + std::string net_vname = netVerilogName(net_name); fprintf(stream_, " wire %s;\n", net_vname.c_str());; } } @@ -302,7 +303,7 @@ VerilogWriter::writeWireDcls(const Instance *inst) for (const auto& [bus_name1, range] : bus_ranges) { const char *bus_name = bus_name1.c_str(); - string net_vname = netVerilogName(bus_name); + std::string net_vname = netVerilogName(bus_name); fprintf(stream_, " wire [%d:%d] %s;\n", range.first, range.second,