From eb0446d4e20679fcacd85d941069fbe83b4d7d87 Mon Sep 17 00:00:00 2001 From: Deepashree Sengupta Date: Tue, 3 Mar 2026 00:48:15 +0000 Subject: [PATCH] Write verilog escape (#394) * Fir for write_verilog issue 3826 Signed-off-by: dsengupta0628 * staToVerilog2 remove escaped_name+=ch Signed-off-by: dsengupta0628 * updated regression to remove \ from module name Signed-off-by: dsengupta0628 * Using helpers.tcl function to redirect results Signed-off-by: dsengupta0628 * add std::string and remove trailing space, update regression name Signed-off-by: dsengupta0628 * update regression to reflect correct output verilog name Signed-off-by: dsengupta0628 --------- Signed-off-by: dsengupta0628 --- network/VerilogNamespace.cc | 10 ++-------- test/regression_vars.tcl | 1 + test/verilog_write_escape.ok | 18 ++++++++++++++++++ test/verilog_write_escape.tcl | 10 ++++++++++ test/verilog_write_escape.v | 13 +++++++++++++ verilog/VerilogWriter.cc | 3 ++- 6 files changed, 46 insertions(+), 9 deletions(-) create mode 100644 test/verilog_write_escape.ok create mode 100644 test/verilog_write_escape.tcl create mode 100644 test/verilog_write_escape.v diff --git a/network/VerilogNamespace.cc b/network/VerilogNamespace.cc index 5362d115..1d0231d9 100644 --- a/network/VerilogNamespace.cc +++ b/network/VerilogNamespace.cc @@ -86,15 +86,12 @@ staToVerilog(const char *sta_name) for (const char *s = sta_name; *s ; s++) { char ch = s[0]; if (ch == verilog_escape) { + escaped = true; char next_ch = s[1]; if (next_ch == verilog_escape) { - escaped_name += ch; escaped_name += next_ch; s++; } - else - // Skip escape. - escaped = true; } else { if ((!(isalnum(ch) || ch == '_'))) @@ -124,15 +121,12 @@ staToVerilog2(const char *sta_name) for (const char *s = sta_name; *s ; s++) { char ch = s[0]; if (ch == verilog_escape) { + escaped = true; char next_ch = s[1]; if (next_ch == verilog_escape) { - escaped_name += ch; escaped_name += next_ch; s++; } - else - // Skip escape. - escaped = true; } else { bool is_brkt = (ch == bus_brkt_left || ch == bus_brkt_right); diff --git a/test/regression_vars.tcl b/test/regression_vars.tcl index c1ed29ea..ab1f6c62 100644 --- a/test/regression_vars.tcl +++ b/test/regression_vars.tcl @@ -165,6 +165,7 @@ record_public_tests { suppress_msg verilog_attribute verilog_specify + verilog_write_escape } define_test_group fast [group_tests all] diff --git a/test/verilog_write_escape.ok b/test/verilog_write_escape.ok new file mode 100644 index 00000000..4906a851 --- /dev/null +++ b/test/verilog_write_escape.ok @@ -0,0 +1,18 @@ +module multi_sink (clk); + input clk; + + wire \alu_adder_result_ex[0] ; + + hier_block \h1\x (.childclk(clk), + .\Y[2:1] ({\alu_adder_result_ex[0] , + \alu_adder_result_ex[0] })); +endmodule +module hier_block (childclk, + \Y[2:1] ); + input childclk; + output [1:0] \Y[2:1] ; + + + BUFx2_ASAP7_75t_R \abuf_$100 (.A(childclk)); + BUFx2_ASAP7_75t_R \ff0/name (.A(childclk)); +endmodule diff --git a/test/verilog_write_escape.tcl b/test/verilog_write_escape.tcl new file mode 100644 index 00000000..29e78590 --- /dev/null +++ b/test/verilog_write_escape.tcl @@ -0,0 +1,10 @@ +# Check if "h1\x" and \Y[2:1] are correctly processed from input to output of Verilog +source helpers.tcl +read_liberty gf180mcu_sram.lib.gz +read_liberty asap7_small.lib.gz +read_verilog verilog_write_escape.v +link_design multi_sink +set verilog_file [make_result_file "verilog_write_escape.v"] +write_verilog $verilog_file +report_file $verilog_file +read_verilog $verilog_file diff --git a/test/verilog_write_escape.v b/test/verilog_write_escape.v new file mode 100644 index 00000000..e0c43c3e --- /dev/null +++ b/test/verilog_write_escape.v @@ -0,0 +1,13 @@ +module multi_sink (clk); + input clk; + wire \alu_adder_result_ex[0] ; + \hier_block \h1\x (.childclk(clk), .\Y[2:1] ({ \alu_adder_result_ex[0] , \alu_adder_result_ex[0] }) ); +endmodule // multi_sink + +module hier_block (childclk, \Y[2:1] ); + input childclk; + output [1:0] \Y[2:1] ; + wire [1:0] \Y[2:1] ; + BUFx2_ASAP7_75t_R \abuf_$100 (.A(childclk)); + BUFx2_ASAP7_75t_R \ff0/name (.A(childclk)); +endmodule // hier_block1 diff --git a/verilog/VerilogWriter.cc b/verilog/VerilogWriter.cc index a38e44b9..3d6e274c 100644 --- a/verilog/VerilogWriter.cc +++ b/verilog/VerilogWriter.cc @@ -386,7 +386,8 @@ VerilogWriter::writeInstBusPin(const Instance *inst, if (!first_port) fprintf(stream_, ",\n "); - fprintf(stream_, ".%s({", network_->name(port)); + std::string port_vname = portVerilogName(network_->name(port)); + fprintf(stream_, ".%s({", port_vname.c_str()); first_port = false; bool first_member = true;