From 12f03395ec80d3593f4796b2a3cf5480e75735bd Mon Sep 17 00:00:00 2001 From: James Cherry Date: Mon, 4 Aug 2025 08:21:37 -0700 Subject: [PATCH 01/13] rm bfs printf Signed-off-by: James Cherry --- search/Bfs.cc | 7 ++++--- 1 file changed, 4 insertions(+), 3 deletions(-) diff --git a/search/Bfs.cc b/search/Bfs.cc index 42cb4885..d6987508 100644 --- a/search/Bfs.cc +++ b/search/Bfs.cc @@ -303,12 +303,14 @@ BfsIterator::checkInQueue(Vertex *vertex) if (vertex->bfsInQueue(bfs_index_)) return; else - printf("extra %s\n", vertex->to_string(this).c_str()); + debugPrint(debug_, "bfs", 1, "extra %s", + vertex->to_string(this).c_str()); } } } if (vertex->bfsInQueue(bfs_index_)) - printf("missing %s\n", vertex->to_string(this).c_str()); + debugPrint(debug_, "brs", 1, "missing %s", + vertex->to_string(this).c_str()); } void @@ -327,7 +329,6 @@ BfsIterator::remove(Vertex *vertex) && static_cast(queue_.size()) > level) { debugPrint(debug_, "bfs", 2, "remove %s", vertex->to_string(this).c_str()); - printf("bfs remove %s\n", vertex->to_string(this).c_str()); for (Vertex *&v : queue_[level]) { if (v == vertex) { v = nullptr; From 82fd625199d25dbe6ca25db9b62417caad358bb9 Mon Sep 17 00:00:00 2001 From: James Cherry Date: Wed, 6 Aug 2025 10:10:11 -0700 Subject: [PATCH 02/13] Levelize rm relevelized limit Signed-off-by: James Cherry --- search/Levelize.cc | 4 +--- search/Levelize.hh | 1 - 2 files changed, 1 insertion(+), 4 deletions(-) diff --git a/search/Levelize.cc b/search/Levelize.cc index 9effdad0..69273479 100644 --- a/search/Levelize.cc +++ b/search/Levelize.cc @@ -51,7 +51,6 @@ Levelize::Levelize(StaState *sta) : levels_valid_(false), max_level_(0), level_space_(10), - max_incremental_level_(100), roots_(graph_), relevelize_from_(graph_), observer_(nullptr) @@ -105,8 +104,7 @@ void Levelize::ensureLevelized() { if (!levels_valid_) { - if (levelized_ - && relevelize_from_.size() < max_incremental_level_) + if (levelized_) relevelize(); else levelize(); diff --git a/search/Levelize.hh b/search/Levelize.hh index f0e5667b..fb9c1af9 100644 --- a/search/Levelize.hh +++ b/search/Levelize.hh @@ -108,7 +108,6 @@ protected: bool levels_valid_; Level max_level_; Level level_space_; - size_t max_incremental_level_; VertexSet roots_; VertexSet relevelize_from_; GraphLoopSeq loops_; From 6d18003c048ed7ed98a026f1128f03fec4f9e60d Mon Sep 17 00:00:00 2001 From: Ethan Mahintorabi Date: Mon, 11 Aug 2025 16:25:47 -0700 Subject: [PATCH 03/13] util: Fix memory leak in PatternMatch (#282) When allocating a new string object in tcl you need increment and then decremenet the ref counter in order for objects to be correctly collected. Signed-off-by: Ethan Mahintorabi --- util/PatternMatch.cc | 2 ++ 1 file changed, 2 insertions(+) diff --git a/util/PatternMatch.cc b/util/PatternMatch.cc index 94b32641..2dd32df9 100644 --- a/util/PatternMatch.cc +++ b/util/PatternMatch.cc @@ -89,7 +89,9 @@ PatternMatch::compileRegexp() anchored_pattern += '$'; Tcl_Obj *pattern_obj = Tcl_NewStringObj(anchored_pattern.c_str(), anchored_pattern.size()); + Tcl_IncrRefCount(pattern_obj); regexp_ = Tcl_GetRegExpFromObj(interp_, pattern_obj, flags); + Tcl_DecrRefCount(pattern_obj); if (regexp_ == nullptr && interp_) throw RegexpCompileError(pattern_); } From d31e3b06e266016131dac0326b87de1ea24b9a1c Mon Sep 17 00:00:00 2001 From: James Cherry Date: Tue, 12 Aug 2025 12:32:36 -0700 Subject: [PATCH 04/13] doc spell check Signed-off-by: James Cherry --- doc/OpenSTA.fodt | 1428 +++++++++++++++++++++++----------------------- doc/OpenSTA.pdf | Bin 1426899 -> 1427456 bytes 2 files changed, 721 insertions(+), 707 deletions(-) diff --git a/doc/OpenSTA.fodt b/doc/OpenSTA.fodt index b3f99eef..b62d4b94 100644 --- a/doc/OpenSTA.fodt +++ b/doc/OpenSTA.fodt @@ -1,24 +1,24 @@ - Parallax STA documentationJames Cherry4802025-03-17T12:59:52.4638705382010-07-31T21:07:002025-06-25T12:59:54.918116000P117DT14H32M14SLibreOffice/25.2.2.2$MacOSX_AARCH64 LibreOffice_project/7370d4be9e3cf6031a51beef54ff3bda878e3facPDF files: James CherryJames Cherry12.00000falsefalsefalsefalse + Parallax STA documentationJames Cherry4812025-03-17T12:59:52.4638705382010-07-31T21:07:002025-08-12T12:31:42.963746000P117DT14H34M45SLibreOffice/25.2.2.2$MacOSX_AARCH64 LibreOffice_project/7370d4be9e3cf6031a51beef54ff3bda878e3facPDF files: James CherryJames Cherry12.00000falsefalsefalsefalse - 2140611 + 999943 0 30224 - 18512 + 17736 true false view2 - 22729 - 2151184 + 12256 + 1005261 0 - 2140611 + 999943 30222 - 2159122 + 1017677 0 1 false @@ -87,7 +87,7 @@ false true false - 25552607 + 25694037 0 false @@ -130,6 +130,15 @@ true true high-resolution + + + en + US + + + + + false true @@ -152,7 +161,9 @@ - + + + @@ -183,7 +194,7 @@ - + @@ -5517,651 +5528,654 @@ - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + + + + @@ -6296,24 +6310,24 @@ Variables80 - Command Line Arguments + Command Line Arguments The command line arguments for sta are shown below. sta -help show help and exit -version show version and exit -no_init do not read ~/.sta -no_splash do not print the splash message -threads count|max use count threads -exit exit after reading cmd_file cmd_file source cmd_file When OpenSTA starts up, commands are first read from the user initialization file ~/.sta if it exists. If a TCL command file cmd_file is specified on the command line, commands are read from the file and executed before entering an interactive TCL command interpreter. If -exit is specified the application exits after reading cmd_file. Use the TCL exit command to exit the application. The –threads option specifies how many parallel threads to use. Use –threads max to use one thread per processor. - Example Command Scripts + Example Command Scripts To read a design into OpenSTA use the read_liberty command to read Liberty library files. Next, read hierarchical structural Verilog files with the read_verilog command. The link_design command links the Verilog to the Liberty timing cells. Any number of Liberty and Verilog files can be read before linking the design. Delays used for timing analysis are calculated using the Liberty timing models. If no parasitics are read only the pin capacitances of the timing models are used in delay calculation. Use the read_spef command to read parasitics from an extractor, or read_sdf to use delays calculated by an external delay calculator. Timing constraints can be entered as TCL commands or read using the read_sdc command. The units used by OpenSTA for all command arguments and reports are taken from the first Liberty file that is read. Use the set_cmd_units command to override the default units. - Timing Analysis using SDF + Timing Analysis using SDF A sample command file that reads a library and a Verilog netlist and reports timing checks is shown below. read_liberty example1_slow.libread_verilog example1.vlink_design topread_sdf example1.sdfcreate_clock -name clk -period 10 {clk1 clk2 clk3}set_input_delay -clock clk 0 {in1 in2}report_checks This example can be found in examples/sdf_delays.tcl. - Timing Analysis with Multiple Process Corners + Timing Analysis with Multiple Process Corners An example command script using three process corners and +/-10% min/max derating is shown below. define_corners wc typ bcread_liberty -corner wc example1_slow.libread_liberty -corner typ example1_typ.libread_liberty -corner bc example1_fast.libread_verilog example1.vlink_design topset_timing_derate -early 0.9set_timing_derate -late 1.1create_clock -name clk -period 10 {clk1 clk2 clk3}set_input_delay -clock clk 0 {in1 in2}report_checks -path_delay min_maxreport_checks -corner typ This example can be found in examples/spef_parasitics.tcl. Other examples can be found in the examples directory. - Power Analysis + Power Analysis OpenSTA also supports static power analysis with the report_power command. Probabalistic switching activities are propagated from the input ports to determine switching activities for internal pins. read_liberty sky130hd_tt.libread_verilog gcd_sky130hd.vlink_design gcdread_sdc gcd_sky130hd.sdcread_spef gcd_sky130hd.spefset_power_activity -input -activity 0.1set_power_activity -input_port reset -activity 0report_power In this example the activity for all inputs is set to 0.1, and then the activity for the reset signal is set to zero because it does not switch during steady state operation. @@ -6325,14 +6339,14 @@ read_liberty sky130hd_tt.libread_verilog gcd_sky130hd.vlink_design gcdread_sdc gcd_sky130hd.sdcread_spef gcd_sky130hd.spefread_vcd -scope gcd_tb/gcd1 gcd_sky130hd.vcd.gzreport_power This example can be found in examples/power_vcd.tcl. Note that in this simple example design simulation based activities does not significantly change the results. - TCL Interpreter + TCL Interpreter Keyword arguments to commands may be abbreviated. For example, report_checks -unique is equivalent to the following command. report_checks -unique_paths_to_endpoint The help command lists matching commands and their arguments. > help report*report_annotated_check [-setup] [-hold] [-recovery] [-removal] [-nochange] [-width] [-period] [-max_skew] [-max_lines liness] [-list_annotated]group_path_count [-list_not_annotated] [-constant_arcs]report_annotated_delay [-cell] [-net] [-from_in_ports] [-to_out_ports] [-max_lines liness] [-list_annotated] [-list_not_annotated] [-constant_arcs]report_arrival pinreport_check_types [-violators] [-verbose] [-corner corner] [-format slack_only|end] [-max_delay] [-min_delay] [-recovery] [-removal] [-clock_gating_setup] [-clock_gating_hold] [-max_slew] [-min_slew] [-max_fanout] [-min_fanout] [-max_capacitance] [-min_capacitance [-min_pulse_width] [-min_period] [-max_skew] [-net net] [-digits digits [-no_line_splits] [> filename] [>> filename]report_checks [-from from_list|-rise_from from_list|-fall_from from_list] [-through through_list|-rise_through through_list|-fall_through through_list] [-to to_list|-rise_to to_list|-fall_to to_list] [-unconstrained] [-path_delay min|min_rise|min_fall|max|max_rise|max_fall|min_max] [-corner corner] [-group_path_count path_count] [-endpoint_path_count path_count] [-unique_paths_to_endpoint] [-slack_max slack_max] [-slack_min slack_min] [-sort_by_slack] [-path_group group_name] [-format full|full_clock|full_clock_expanded|short|end|summary]... - Many reporting commands support redirection of the output to a file much like a Unix shell. + Many reporting commands support redirection of the output to a file much like a Unix shell. report_checks -to out1 > path.logreport_checks -to out2 >> path.log Debugging Timing Here are some guidelines for debugging your design if static timing does not report any paths, or does not report the expected paths. @@ -6358,13 +6372,13 @@ Next, check the arrival times at the D and CP pins of the register with report_arrivals. % report_arrivals r1/D (clk1 ^) r 1.00:1.00 f 1.00:1.00% report_arrivals r1/CP (clk1 ^) r 0.00:0.00 f INF:-INF (clk1 v) r INF:-INF f 5.00:5.00 If there are no arrivals on an input port of the design, use the set_input_delay command to specify the arrival times on the port. - Commands + Commands - all_clocks + all_clocks @@ -6377,7 +6391,7 @@ - all_inputs + all_inputs [-no_clocks] @@ -6398,7 +6412,7 @@ - all_outputs + all_outputs @@ -6411,7 +6425,7 @@ - all_registers + all_registers [-clock clock_names][-cells | -data_pins | -clock_pins | -async_pins | ‑output_pins][-level_sensitive][-edge_triggered] @@ -6488,7 +6502,7 @@ - check_setup + check_setup [-verbose][-unconstrained_endpoints][-multiple_clock][-no_clock][-no_input_delay][-loops][-generated_clocks][> filename][>> filename] @@ -6557,7 +6571,7 @@ - connect_pin + connect_pin netport|pin @@ -6657,7 +6671,7 @@ - create_generated_clock + create_generated_clock [-name clock_name]-source master_pin[-master_clock master_clock][-divide_by divisor][-multiply_by multiplier][-duty_cycle duty_cycle][-invert][-edges edge_list][-edge_shift shift_list][-add]pin_list @@ -6773,7 +6787,7 @@ - create_voltage_area + create_voltage_area [-name name][-coordinate coordinates][-guard_band_x guard_x][-guard_band_y guard_y]cells @@ -6786,7 +6800,7 @@ - current_design + current_design [design] @@ -6799,7 +6813,7 @@ - current_instance + current_instance [instance] @@ -6821,7 +6835,7 @@ - define_corners + define_corners corner1 [corner2]... @@ -6843,7 +6857,7 @@ - delete_clock + delete_clock [-all] clocks @@ -6864,7 +6878,7 @@ - delete_from_list + delete_from_list list objects @@ -6893,7 +6907,7 @@ - delete_generated_clock + delete_generated_clock [-all] clocks @@ -6914,7 +6928,7 @@ - delete_instance + delete_instance instance @@ -6936,7 +6950,7 @@ - delete_net + delete_net net @@ -6957,7 +6971,7 @@ - disconnect_pin + disconnect_pin netport | pin | -all @@ -7002,7 +7016,7 @@ - elapsed_run_time + elapsed_run_time @@ -7016,7 +7030,7 @@ - find_timing_paths + find_timing_paths [-from from_list |-rise_from from_list |-fall_from from_list][-through through_list |-rise_through through_list |-fall_through through_list][-to to_list |-rise_to to_list |-fall_to to_list][-unconstrained][-path_delay min|min_rise|min_fall |max|max_rise|max_fall |min_max][-group_path_count path_count][-endpoint_path_count endpoint_path_count][-unique_paths_to_endpoint][-corner corner][-slack_max max_slack][-slack_min min_slack][-sort_by_slack][-path_group groups] @@ -7230,7 +7244,7 @@ - get_cells + get_cells [-hierarchical][-hsc separator][-filter expr][-regexp][-nocase][-quiet][-of_objects objects][patterns] @@ -7308,7 +7322,7 @@ - get_clocks + get_clocks [-regexp][-nocase][-filter expr][-quiet]patterns @@ -7362,7 +7376,7 @@ - get_fanin + get_fanin -to sink_list[-flat][-only_cells][-startpoints_only][-levels level_count][-pin_levels pin_count][-trace_arcs timing|enabled|all] @@ -7447,7 +7461,7 @@ - get_fanout + get_fanout -from source_list[-flat][-only_cells][-endpoints_only][-levels level_count][-pin_levels pin_count][-trace_arcs timing|enabled|all] @@ -7533,7 +7547,7 @@ - get_full_name + get_full_name object @@ -7624,7 +7638,7 @@ - get_lib_pins + get_lib_pins [-of_objects objects][-hsc separator][-filter expr][-regexp][-nocase][-quiet]patterns @@ -7693,7 +7707,7 @@ - get_libs + get_libs [-filter expr][-regexp][-nocase][-quiet]patterns @@ -7747,7 +7761,7 @@ - get_nets + get_nets [-hierarchical][-hsc separator][-filter expr][-regexp][-nocase][-quiet][-of_objects objects][patterns] @@ -7824,7 +7838,7 @@ - get_name + get_name object @@ -7845,7 +7859,7 @@ - get_pins + get_pins [-hierarchical][-hsc separator][-filter expr][-regexp][-nocase][-quiet][-of_objects objects][patterns] @@ -7917,7 +7931,7 @@ - get_ports + get_ports [-filter expr][-regexp][-nocase][-quiet][-of_objects objects][patterns] @@ -7978,7 +7992,7 @@ - get_property + get_property [-object_type object_type]objectproperty @@ -8039,7 +8053,7 @@ - get_timing_edges + get_timing_edges [-from from_pins][-to to_pins][-of_objects objects][-filter expr][patterns] @@ -8084,7 +8098,7 @@ - group_path + group_path -name group_name[-weight weight][-critical_range range][-from from_list |-rise_from from_list |-fall_from from_list][-through through_list][-rise_through through_list][-fall_through through_list][-to to_list |-rise_to to_list |-fall_to to_list] @@ -8194,7 +8208,7 @@ - include + include [-echo|-e][-verbose|-v]filename[> log_filename][>> log_filename] @@ -8248,7 +8262,7 @@ - link_design + link_design [-no_black_boxes][cell_name] @@ -8279,7 +8293,7 @@ - make_instance + make_instance inst_pathlib_cell @@ -8308,7 +8322,7 @@ - make_net + make_net net_name_list @@ -8329,7 +8343,7 @@ - read_liberty + read_liberty [-corner corner][-min][-max][-infer_latches]filename @@ -8378,7 +8392,7 @@ - read_saif + read_saif [-scope scope]filename @@ -8407,7 +8421,7 @@ - read_sdc + read_sdc [-echo]filename @@ -8438,7 +8452,7 @@ - read_sdf + read_sdf [-corner corner][-unescaped_dividers]filename @@ -8480,7 +8494,7 @@ - read_spef + read_spef [-min][-max][-path path][-corner corner][-keep_capacitive_coupling][-coupling_reduction_factor factor][-reduce]filename @@ -8552,7 +8566,7 @@ - The read_spef command reads a file of net parasitics in SPEF format. Use the ‑report_parasitic_annotation command to check for nets that are not annotated. + The read_spef command reads a file of net parasitics in SPEF format. Use the ‑report_parasitic_annotation command to check for nets that are not annotated. Files compressed with gzip are automatically uncompressed. Separate parasitics can be annotated for corners and min and max paths using the -corner, –min and -max arguments. To use the same parastiics for every corner and for min/max delay calculation read the SPEF without -corner, -min, and -max options. read_spef spef1 @@ -8567,14 +8581,14 @@ The following SPEF constructs are ignored. *DESIGN_FLOW (all values are ignored)*S slews*D driving cell*I pin capacitances (library cell capacitances are used instead)*Q r_net load poles*K r_net load residues If the SPEF file contains triplet values the first value is used. - Parasitic networks (DSPEF) can be annotated on hierarchical blocks using the -path argument to specify the instance path to the block. Parasitic networks in the higher level netlist are stitched together at the hierarchcal pins of the blocks. + Parasitic networks (DSPEF) can be annotated on hierarchical blocks using the -path argument to specify the instance path to the block. Parasitic networks in the higher level netlist are stitched together at the hierarchical pins of the blocks. - read_vcd + read_vcd [-scope scope]filename @@ -8597,13 +8611,13 @@ - The read_vcd command reads a VCD (Value Change Dump) file from a Verilog simulation and extracts pin activities and duty cycles for use in power estimation. Files compressed with gzip are supported. Annotated activities are propagated to the fanout of the annotated pins. + The read_vcd command reads a VCD (Value Change Dump) file from a Verilog simulation and extracts pin activities and duty cycles for use in power estimation. Files compressed with gzip are supported. Annotated activities are propagated to the fanout of the annotated pins. - read_verilog + read_verilog filename @@ -8618,7 +8632,7 @@ - The read_verilog command reads a gate level verilog netlist. After all verilog netlist and Liberty libraries are read the design must be linked with the link_design command. + The read_verilog command reads a gate level verilog netlist. After all verilog netlist and Liberty libraries are read the design must be linked with the link_design command. Verilog 2001 module port declaratations are supported. An example is shown below. module top (input in1, in2, clk1, clk2, clk3, output out); Files compressed with gzip are automatically uncompressed. @@ -8627,7 +8641,7 @@ - replace_cell + replace_cell instance_listreplacement_cell @@ -8650,13 +8664,13 @@ - The replace_cell command changes the cell of an instance. The replacement cell must have the same port list (number, name, and order) as the instance's existing cell for the replacement to be successful. + The replace_cell command changes the cell of an instance. The replacement cell must have the same port list (number, name, and order) as the instance's existing cell for the replacement to be successful. - replace_activity_annotation + replace_activity_annotation [-report_unannotated][-report_annotated] @@ -8667,7 +8681,7 @@ -report_unannotated - Report unannotated pins. + Report unannotated pins. @@ -8675,17 +8689,17 @@ -report_unannotated - Report annotated pins. + Report annotated pins. - Report a summary of pins that are annotated by read_vcd, read_saif or set_power_activity. Sequential internal pins and hierarchical pins are ignored. + Report a summary of pins that are annotated by read_vcd, read_saif or set_power_activity. Sequential internal pins and hierarchical pins are ignored. - report_annotated_check + report_annotated_check [-setup][-hold][-recovery][-removal][-nochange][-width][-period][-max_skew][-max_line lines][-report_annotated][-report_unannotated][-constant_arcs] @@ -8757,7 +8771,7 @@ - -max_line lines + -max_line lines Maximum number of lines listed by the –report_annotated and ‑report_unannotated options. @@ -8788,17 +8802,17 @@ - The report_annotated_check command reports a summary of SDF timing check annotation. The -report_annotated and –report_annotated options can be used to list arcs that are annotated or not annotated. + The report_annotated_check command reports a summary of SDF timing check annotation. The -report_annotated and –report_annotated options can be used to list arcs that are annotated or not annotated. - report_annotated_delay + report_annotated_delay - [-cell][-net][-from_in_ports][-to_out_ports][-max_lines lines][-report_annotated][-report_unannotated][-constant_arcs] + [-cell][-net][-from_in_ports][-to_out_ports][-max_lines lines][-report_annotated][-report_unannotated][-constant_arcs] @@ -8819,7 +8833,7 @@ - -from_in_ports + -from_in_ports Report annotated delays from input ports. @@ -8827,7 +8841,7 @@ - -to_out_ports + -to_out_ports Report annotated delays to output ports. @@ -8835,7 +8849,7 @@ - -max_lines lines + -max_lines lines Maximum number of lines listed by the –report_annotated and ‑report_unannotated options. @@ -8866,17 +8880,17 @@ - The report_annotated_delay command reports a summary of SDF delay annotation. Without the ‑from_in_ports and –to_out_ports options arcs to and from top level ports are not reported. The ‑report_annotated and –report_unannotated options can be used to list arcs that are annotated or not annotated. + The report_annotated_delay command reports a summary of SDF delay annotation. Without the ‑from_in_ports and –to_out_ports options arcs to and from top level ports are not reported. The ‑report_annotated and –report_unannotated options can be used to list arcs that are annotated or not annotated. - report_checks + report_checks - [-from from_list |-rise_from from_list |-fall_from from_list][-through through_list |-rise_through through_list |-fall_through through_list][-to to_list |-rise_to to_list |-fall_to to_list][-unconstrained][-path_delay min|min_rise|min_fall |max|max_rise|max_fall |min_max][-group_path_count path_count][-endpoint_path_count endpoint_path_count][-unique_paths_to_endpoint][-corner corner][-slack_max max_slack][-slack_min min_slack][-sort_by_slack][-path_group groups][-format end|full|short|summary |full_clock|full_clock_expanded |json][-fields fields][-digits digits][-no_line_split][> filename][>> filename] + [-from from_list |-rise_from from_list |-fall_from from_list][-through through_list |-rise_through through_list |-fall_through through_list][-to to_list |-rise_to to_list |-fall_to to_list][-unconstrained][-path_delay min|min_rise|min_fall |max|max_rise|max_fall |min_max][-group_path_count path_count][-endpoint_path_count endpoint_path_count][-unique_paths_to_endpoint][-corner corner][-slack_max max_slack][-slack_min min_slack][-sort_by_slack][-path_group groups][-format end|full|short|summary |full_clock|full_clock_expanded |json][-fields fields][-digits digits][-no_line_split][> filename][>> filename] @@ -9042,10 +9056,10 @@ - -corner corner + -corner corner - Report paths for one process corner. The default is to report paths for all process corners. + Report paths for one process corner. The default is to report paths for all process corners. @@ -9074,10 +9088,10 @@ - -path_group groups + -path_group groups - List of path groups to report. The default is to report all path groups. + List of path groups to report. The default is to report all path groups. @@ -9131,23 +9145,23 @@ - -format json + -format json - Report in json format. -fields is ignored. + Report in json format. -fields is ignored. - -fields fields + -fields fields - List of capacitance|slew|input_pins|hierarcial_pins|nets|fanout|src_attr + List of capacitance|slew|input_pins|hierarchical_pins|nets|fanout|src_attr - -digits digits + -digits digits The number of digits after the decimal point to report. The default value is the variable sta_report_default_digits. @@ -9162,14 +9176,14 @@ - The report_checks command reports paths in the design. Paths are reported in groups by capture clock, unclocked path delays, gated clocks and unconstrained. + The report_checks command reports paths in the design. Paths are reported in groups by capture clock, unclocked path delays, gated clocks and unconstrained. See set_false_path for a description of allowed from_list, through_list and to_list objects. - report_check_types + report_check_types [-violators][-verbose][-format slack_only|end][-max_delay][-min_delay][-recovery][-removal][-clock_gating_setup][-clock_gating_hold][-max_slew][-min_slew][-min_pulse_width][-min_period][-digits digits][-no_split_lines][> filename][>> filename] @@ -9178,7 +9192,7 @@ - -violators + -violators Report all violated timing and design rule constraints. @@ -9194,18 +9208,18 @@ - -format slack_only + -format slack_only - Report the minumum slack for each timing check. + Report the minimum slack for each timing check. - -format end + -format end - Report the endpoint for each check. + Report the endpoint for each check. @@ -9298,7 +9312,7 @@ - -digits digits + -digits digits The number of digits after the decimal point to report. The default value is the variable sta_report_default_digits. @@ -9319,10 +9333,10 @@ - report_clock_latency + report_clock_latency - [-clock clocks][-include_internal_latency][-digits digits] + [-clock clocks][-include_internal_latency][-digits digits] @@ -9357,7 +9371,7 @@ - report_clock_min_period + report_clock_min_period [-clocks clocks][-include_port_paths] @@ -9380,13 +9394,13 @@ - Report the minimum period and maximum frequency for clocks. If the -clocks argument is not specified all clocks are reported. The minimum period is determined by examining the smallest slack paths between registers the rising edges of the clock or between falling edges of the clock. Paths between different clocks, different clock edges of the same clock, level sensitive latches, or paths constrained by set_multicycle_path, set_max_path are not considered. + Report the minimum period and maximum frequency for clocks. If the -clocks argument is not specified all clocks are reported. The minimum period is determined by examining the smallest slack paths between registers the rising edges of the clock or between falling edges of the clock. Paths between different clocks, different clock edges of the same clock, level sensitive latches, or paths constrained by set_multicycle_path, set_max_path are not considered. - report_clock_properties + report_clock_properties [clock_names] @@ -9407,10 +9421,10 @@ - report_clock_skew + report_clock_skew - [-setup|-hold][-clock clocks][-include_internal_latency][-digits digits] + [-setup|-hold][-clock clocks][-include_internal_latency][-digits digits] @@ -9454,14 +9468,14 @@ - Report the maximum difference in clock arrival between every source and target register that has a path between the source and target registers. + Report the maximum difference in clock arrival between every source and target register that has a path between the source and target registers. - report_dcalc + report_dcalc [-from from_pin][-to to_pin][-corner corner][-min][-max][-digits digits][> filename][>> filename] @@ -9472,44 +9486,44 @@ -from from_pin - Report delay calculations for timing arcs from instance input pin from_pin. + Report delay calculations for timing arcs from instance input pin from_pin. - -to to_pin + -to to_pin - Report delay calculations for timing arcs to instance output pin to_pin. + Report delay calculations for timing arcs to instance output pin to_pin. - -corner corner + -corner corner - Report paths for process corner. The -corner keyword is required if more than one process corner is defined. + Report paths for process corner. The -corner keyword is required if more than one process corner is defined. - -min + -min - Report delay calculation for min delays. + Report delay calculation for min delays. - -max + -max - Report delay calculation for max delays. + Report delay calculation for max delays. - -digits digits + -digits digits The number of digits after the decimal point to report. The default is sta_report_default_digits. @@ -9522,7 +9536,7 @@ - report_disabled_edges + report_disabled_edges @@ -9530,13 +9544,13 @@ The report_disabled_edges command reports disabled timing arcs along with the reason they are disabled. Each disabled timing arc is reported as the instance name along with the from and to ports of the arc. The disable reason is shown next. Arcs that are disabled with set_disable_timing are reported with constraint as the reason. Arcs that are disabled by constants are reported with constant as the reason along with the constant instance pin and value. Arcs that are disabled to break combinational feedback loops are reported with loop as the reason. - > report_disabled_edgesu1 A B constant B=0 + > report_disabled_edgesu1 A B constant B=0 - report_edges + report_edges [-from from_pin][-to to_pin] @@ -9547,25 +9561,25 @@ -from from_pin - Report edges/timing arcs from pin from_pin. + Report edges/timing arcs from pin from_pin. - -to to_pin + -to to_pin - Report edges/timing arcs to pin to_pin. + Report edges/timing arcs to pin to_pin. - Report the edges/timing arcs and their delays in the timing graph from/to/between pins. + Report the edges/timing arcs and their delays in the timing graph from/to/between pins. - report_instance + report_instance instance_path[> filename][>> filename] @@ -9576,7 +9590,7 @@ instance_path - Hierarchical path to a instance. + Hierarchical path to an instance. @@ -9586,7 +9600,7 @@ - report_lib_cell + report_lib_cell cell_name[> filename][>> filename] @@ -9607,7 +9621,7 @@ - report_net + report_net [-digits digits]net_path[> filename][>> filename] @@ -9636,10 +9650,10 @@ - report_parasitic_annotation + report_parasitic_annotation - [-report_unannotated][> filename][>> filename] + [-report_unannotated][> filename][>> filename] @@ -9658,10 +9672,10 @@ - report_power + report_power - [-instances instances][-highest_power_instances count][-digits digits][> filename][>> filename] + [-instances instances][-highest_power_instances count][-digits digits][> filename][>> filename] @@ -9669,35 +9683,35 @@ -instances instances - Report the power for each instance of instances. If the instance is hierarchical the total power for the instances inside the hierarchical instance is reported. + Report the power for each instance of instances. If the instance is hierarchical the total power for the instances inside the hierarchical instance is reported. - -highest_power_instances count + -highest_power_instances count - Report the power for the count highest power instances. + Report the power for the count highest power instances. - -digits digits + -digits digits The number of digits after the decimal point to report. The default value is the variable sta_report_default_digits. - The report_power command uses static power analysis based on propagated or annotated pin activities in the circuit using Liberty power models. The internal, switching, leakage and total power are reported. Design power is reported separately for combinational, sequential, macro and pad groups. Power values are reported in watts. - The read_vcd or read_saif commands can be used to read activities from a file based on simulation. If no simulation activities are available, the set_power_activity command should be used to set the activity of input ports or pins in the design. The default input activity and duty for inputs are 0.1 and 0.5 respectively. The activities are propagated from annotated input ports or pins through gates and used in the power calculations. + The report_power command uses static power analysis based on propagated or annotated pin activities in the circuit using Liberty power models. The internal, switching, leakage and total power are reported. Design power is reported separately for combinational, sequential, macro and pad groups. Power values are reported in watts. + The read_vcd or read_saif commands can be used to read activities from a file based on simulation. If no simulation activities are available, the set_power_activity command should be used to set the activity of input ports or pins in the design. The default input activity and duty for inputs are 0.1 and 0.5 respectively. The activities are propagated from annotated input ports or pins through gates and used in the power calculations. Group Internal Switching Leakage Total Power Power Power Power----------------------------------------------------------------Sequential 3.29e-06 3.41e-08 2.37e-07 3.56e-06 92.4%Combinational 1.86e-07 3.31e-08 7.51e-08 2.94e-07 7.6%Macro 0.00e+00 0.00e+00 0.00e+00 0.00e+00 0.0%Pad 0.00e+00 0.00e+00 0.00e+00 0.00e+00 0.0%---------------------------------------------------------------Total 3.48e-06 6.72e-08 3.12e-07 3.86e-06 100.0% 90.2% 1.7% 8.1% - report_pulse_width_checks + report_pulse_width_checks [-verbose][-digits digits][-no_line_splits][pins][> filename][>> filename] @@ -9713,7 +9727,7 @@ - -digits digits + -digits digits The number of digits after the decimal point to report. The default value is the variable sta_report_default_digits. @@ -9737,13 +9751,13 @@ - The report_pulse_width_checks command reports min pulse width checks for pins in the clock network. If pins is not specified all clock network pins are reported. + The report_pulse_width_checks command reports min pulse width checks for pins in the clock network. If pins is not specified all clock network pins are reported. - report_slews + report_slews [-corner corner]pin @@ -9751,10 +9765,10 @@ - -corner corner + -corner corner - Report paths for process corner. The -corner keyword is required if more than one process corner is defined. + Report paths for process corner. The -corner keyword is required if more than one process corner is defined. @@ -9772,7 +9786,7 @@ - report_tns + report_tns [-min][-max][-digits digits] @@ -9783,7 +9797,7 @@ -max - Report the total max/setup slack. + Report the total max/setup slack. @@ -9791,12 +9805,12 @@ -min - Report the total min/hold slack. + Report the total min/hold slack. - -digits digits + -digits digits The number of digits after the decimal point to report. The default value is the variable sta_report_default_digits. @@ -9809,14 +9823,14 @@ - report_units + report_units - Report the units used for command arguments and reporting. + Report the units used for command arguments and reporting. report_units time 1ns capacitance 1pF resistance 1kohm voltage 1v current 1A power 1pW distance 1um @@ -9824,7 +9838,7 @@ - report_wns + report_wns [-min][-max][-digits digits] @@ -9848,20 +9862,20 @@ - -digits digits + -digits digits The number of digits after the decimal point to report. The default value is the variable sta_report_default_digits. - Report the worst negative slack. If the worst slack is posiive, zero is reported. + Report the worst negative slack. If the worst slack is positive, zero is reported. - report_worst_slack + report_worst_slack [-min][-max][-digits digits] @@ -9885,7 +9899,7 @@ - -digits digits + -digits digits The number of digits after the decimal point to report. The default value is the variable sta_report_default_digits. @@ -9898,7 +9912,7 @@ - set_assigned_check + set_assigned_check -setup|-hold|-recovery|-removal[-rise][-fall][-corner corner][-min][-max][-from from_pins][-to to_pins][-clock rise|fall][-cond sdf_cond][-worst]margin @@ -9909,7 +9923,7 @@ -setup - Annotate setup timing checks. + Annotate setup timing checks. @@ -9917,7 +9931,7 @@ -hold - Annotate hold timing checks. + Annotate hold timing checks. @@ -9926,7 +9940,7 @@ -recovery - Annotate recovery timing checks. + Annotate recovery timing checks. @@ -9934,7 +9948,7 @@ -removal - Annotate removal timing checks. + Annotate removal timing checks. @@ -9955,7 +9969,7 @@ - -corner corner + -corner corner The name of a process corner. The -corner keyword is required if more than one process corner is defined. @@ -9979,7 +9993,7 @@ - -from from_pins + -from from_pins A list of pins for the clock. @@ -9987,7 +10001,7 @@ - -to to_pins + -to to_pins A list of pins for the data. @@ -9998,7 +10012,7 @@ -clock rise|fall - The timing check clock pin transition. + The timing check clock pin transition. @@ -10006,17 +10020,17 @@ margin - The timing check margin. + The timing check margin. - The set_assigned_check command is used to annotate the timing checks between two pins on an instance. The annotated delay overrides the calculated delay. This command is a interactive way to back-annotate delays like an SDF file. + The set_assigned_check command is used to annotate the timing checks between two pins on an instance. The annotated delay overrides the calculated delay. This command is an interactive way to back-annotate delays like an SDF file. - set_assigned_delay + set_assigned_delay -cell|-net[-rise][-fall][-corner corner][-min][-max][-from from_pins][-to to_pins]delay @@ -10057,7 +10071,7 @@ - -corner corner + -corner corner The name of a process corner. The -corner keyword is required if more than one process corner is defined. @@ -10081,7 +10095,7 @@ - -from from_pins + -from from_pins A list of pins. @@ -10089,7 +10103,7 @@ - -to to_pins + -to to_pins A list of pins. @@ -10104,14 +10118,14 @@ - The set_assigned_delay command is used to annotate the delays between two pins on an instance or net. The annotated delay overrides the calculated delay. This command is a interactive way to back-annotate delays like an SDF file. + The set_assigned_delay command is used to annotate the delays between two pins on an instance or net. The annotated delay overrides the calculated delay. This command is an interactive way to back-annotate delays like an SDF file. Use the -corner keyword to specify a process corner. The -corner keyword is required if more than one process corner is defined. - set_assigned_transition + set_assigned_transition [-rise][-fall][-corner corner][-min][-max]slewpin_list @@ -10135,10 +10149,10 @@ - -corner corner + -corner corner - Annotate delays for process corner. + Annotate delays for process corner. @@ -10181,7 +10195,7 @@ - set_case_analysis + set_case_analysis 0|1|zero|one|rise|rising|fall|fallingport_or_pin_list @@ -10203,7 +10217,7 @@ - set_clock_gating_check + set_clock_gating_check [-setup setup_time][-hold hold_time][-rise][-fall][-high][-low][objects] @@ -10211,7 +10225,7 @@ - -setup setup_time + -setup setup_time Clock enable setup margin. @@ -10219,7 +10233,7 @@ - -hold hold_time + -hold hold_time Clock enable hold margin. @@ -10276,7 +10290,7 @@ - set_clock_groups + set_clock_groups [-name name][-logically_exclusive][-physically_exclusive][-asynchronous][-allow_paths]-group clocks @@ -10284,7 +10298,7 @@ - -name name + -name name The clock group name. @@ -10331,13 +10345,13 @@ - The set_clock_groups command is used to deifine groups of clocks that interact with each other. Clocks in different groups do not interact and paths between them are not reported. Use a –group argument for each clock group. + The set_clock_groups command is used to define groups of clocks that interact with each other. Clocks in different groups do not interact and paths between them are not reported. Use a –group argument for each clock group. - set_clock_latency + set_clock_latency [-source][-clock clock][-rise][-fall][-min][-max]delayobjects @@ -10345,7 +10359,7 @@ - -source + -source The latency is at the clock source. @@ -10353,7 +10367,7 @@ - -clock clock + -clock clock If multiple clocks are defined at a pin this use this option to specify the latency for a specific clock. @@ -10415,7 +10429,7 @@ - set_clock_transition + set_clock_transition [-rise][-fall][-min][-max]transitionclocks @@ -10426,7 +10440,7 @@ -rise - Set the transition time for the rising edge of the clock. + Set the transition time for the rising edge of the clock. @@ -10434,7 +10448,7 @@ -fall - Set the transition time for the falling edge of the clock. + Set the transition time for the falling edge of the clock. @@ -10442,7 +10456,7 @@ -min - Set the min transition time. + Set the min transition time. @@ -10450,7 +10464,7 @@ -max - Set the min transition time. + Set the min transition time. @@ -10470,14 +10484,14 @@ - The set_clock_transition command describes expected transition times of the clock tree when analzying a design using ideal clocks. + The set_clock_transition command describes expected transition times of the clock tree when analyzing a design using ideal clocks. - set_clock_uncertainty + set_clock_uncertainty [-from|-rise_from|-fall_from from_clock][-to|-rise_to|-fall_to to_clock][-rise][-fall][-setup][-hold]uncertainty[objects] @@ -10485,7 +10499,7 @@ - -from from_clock + -from from_clock Inter-clock uncertainty source clock. @@ -10493,7 +10507,7 @@ - -to to_clock + -to to_clock Inter-clock uncertainty target clock. @@ -10504,7 +10518,7 @@ -rise - Inter-clock target clock rise edge, alternative to ‑rise_to.Inter-clock target clock rise edge, alternative to ‑rise_to. + Inter-clock target clock rise edge, alternative to ‑rise_to.Inter-clock target clock rise edge, alternative to ‑rise_to. @@ -10512,7 +10526,7 @@ -fall - Inter-clock target clock rise edge, alternative to ‑fall_to. + Inter-clock target clock rise edge, alternative to ‑fall_to. @@ -10520,7 +10534,7 @@ -setup - uncertainty is for setup checks. + uncertainty is for setup checks. @@ -10528,7 +10542,7 @@ -hold - uncertainty is for hold checks. + uncertainty is for hold checks. @@ -10548,22 +10562,22 @@ - The set_clock_uncertainty command specifies the uncertainty or jitter in a clock. The uncertainty for a clock can be specified on its source pin or port, or the clock itself. - set_clock_uncertainty .1 [get_clock clk1] - Inter-clock uncertainty between the source and target clocks of timing checks is specified with the ‑from|‑rise_from|-fall_from and ‑to|‑rise_to|-fall_to arguments . - set_clock_uncertainty -from [get_clock clk1] -to [get_clocks clk2] .1 - The following commands are equivalent. - set_clock_uncertainty -from [get_clock clk1] -rise_to [get_clocks clk2] .1set_clock_uncertainty -from [get_clock clk1] -to [get_clocks clk2] -rise .1 + The set_clock_uncertainty command specifies the uncertainty or jitter in a clock. The uncertainty for a clock can be specified on its source pin or port, or the clock itself. + set_clock_uncertainty .1 [get_clock clk1] + Inter-clock uncertainty between the source and target clocks of timing checks is specified with the ‑from|‑rise_from|-fall_from and ‑to|‑rise_to|-fall_to arguments . + set_clock_uncertainty -from [get_clock clk1] -to [get_clocks clk2] .1 + The following commands are equivalent. + set_clock_uncertainty -from [get_clock clk1] -rise_to [get_clocks clk2] .1set_clock_uncertainty -from [get_clock clk1] -to [get_clocks clk2] -rise .1 - set_cmd_units + set_cmd_units - [-capacitance cap_unit][-resistance res_unit][-time time_unit][-voltage voltage_unit][-current current_unit][-power power_unit][-distance distance_unit] + [-capacitance cap_unit][-resistance res_unit][-time time_unit][-voltage voltage_unit][-current current_unit][-power power_unit][-distance distance_unit] @@ -10595,7 +10609,7 @@ -voltage voltage_unit - The voltage scale factor followed by 'v'. + The voltage scale factor followed by 'v'. @@ -10623,7 +10637,7 @@ - The set_cmd_units command is used to change the units used by the STA command interpreter when parsing commands and reporting results. The default units are the units specified in the first Liberty library file that is read. + The set_cmd_units command is used to change the units used by the STA command interpreter when parsing commands and reporting results. The default units are the units specified in the first Liberty library file that is read. Units are specified as a scale factor followed by a unit name. The scale factors are as follows. M 1E+6k 1E+3m 1E-3u 1E-6n 1E-9p 1E-12f 1E-15 An example of the set_units command is shown below. @@ -10634,15 +10648,15 @@ - set_data_check + set_data_check - [-from|-rise_from|-fall_from from_pin][-to|-rise_to|-fall_to to_pin][-setup][-hold][-clock clock]margin + [-from|-rise_from|-fall_from from_pin][-to|-rise_to|-fall_to to_pin][-setup][-hold][-clock clock]margin - -from from_pin + -from from_pin A pin used as the timing check reference. @@ -10650,7 +10664,7 @@ - -to to_pin + -to to_pin A pin that the setup/hold check is applied to. @@ -10695,7 +10709,7 @@ - set_disable_inferred_clock_gating + set_disable_inferred_clock_gating objects @@ -10710,13 +10724,13 @@ - The set_disable_inferred_clock_gating command disables clock gating checks on a clock gating instance, clock gating pin, or clock gating enable pin. + The set_disable_inferred_clock_gating command disables clock gating checks on a clock gating instance, clock gating pin, or clock gating enable pin. - set_disable_timing + set_disable_timing [-from from_port][-to to_port]objects @@ -10743,7 +10757,7 @@ objects - A list of instances, ports, pins, cells, cell/port, or library/cell/port. + A list of instances, ports, pins, cells, cell/port, or library/cell/port. @@ -10761,10 +10775,10 @@ - set_drive + set_drive - [-rise][-fall][-max][-min]resistanceports + [-rise][-fall][-max][-min]resistanceports @@ -10788,7 +10802,7 @@ -max - Set the maximum resistance. + Set the maximum resistance. @@ -10796,7 +10810,7 @@ -min - Set the minimum resistance. + Set the minimum resistance. @@ -10809,7 +10823,7 @@ - ports + ports A list of ports. @@ -10823,10 +10837,10 @@ - set_driving_cell + set_driving_cell - [-lib_cell cell_name][-library library][-rise][-fall][-min][-max][-pin pin][-from_pin from_pin][-input_transition_rise trans_rise][-input_transition_fall trans_fall]ports + [-lib_cell cell_name][-library library][-rise][-fall][-min][-max][-pin pin][-from_pin from_pin][-input_transition_rise trans_rise][-input_transition_fall trans_fall]ports @@ -10842,7 +10856,7 @@ -library library - The driving cell library. + The driving cell library. @@ -10850,7 +10864,7 @@ -rise - Set the driving cell for a risingn edge. + Set the driving cell for a rising edge. @@ -10858,7 +10872,7 @@ -fall - Set the driving cell for a falling edge. + Set the driving cell for a falling edge. @@ -10866,7 +10880,7 @@ -max - Set the driving cell for max delays. + Set the driving cell for max delays. @@ -10874,12 +10888,12 @@ -min - Set the driving cell for min delays. + Set the driving cell for min delays. - -pin pin + -pin pin The output port of the driving cell. @@ -10887,10 +10901,10 @@ - -from_pin from_pin + -from_pin from_pin - Use timng arcs from from_pin to the output pin. + Use timing arcs from from_pin to the output pin. @@ -10903,7 +10917,7 @@ - -input_transition_fall trans_fall + -input_transition_fall trans_fall The transition time for a falling input at from_pin. @@ -10911,7 +10925,7 @@ - ports + ports A list of ports. @@ -10925,7 +10939,7 @@ - set_false_path + set_false_path [-setup][-hold][-rise][-fall][-from from_list][-rise_from from_list][-fall_from from_list][-through through_list][-rise_through through_list][-fall_through through_list][-to to_list][-rise_to to_list][-fall_to to_list][-reset_path] @@ -10936,7 +10950,7 @@ -setup - Apply to setup checks. + Apply to setup checks. @@ -10944,7 +10958,7 @@ -hold - Apply to hold checks. + Apply to hold checks. @@ -10952,7 +10966,7 @@ -rise - Apply to rising path edges. + Apply to rising path edges. @@ -10960,7 +10974,7 @@ -fall - Apply to falling path edges. + Apply to falling path edges. @@ -11006,7 +11020,7 @@ - set_fanout_load + set_fanout_load fanoutport_list @@ -11019,7 +11033,7 @@ - set_hierarchy_separator + set_hierarchy_separator separator @@ -11040,7 +11054,7 @@ - set_ideal_latency + set_ideal_latency [-rise] [-fall] [-min] [-max] delay objects @@ -11053,7 +11067,7 @@ - set_ideal_network + set_ideal_network [-no_propagation] objects @@ -11066,7 +11080,7 @@ - set_ideal_transition + set_ideal_transition [-rise] [-fall] [-min] [-max] transition_time objects @@ -11079,7 +11093,7 @@ - set_input_delay + set_input_delay [-rise][-fall][-max][-min][-clock clock][-clock_fall][-reference_pin ref_pin][-source_latency_included][-network_latency_included][-add_delay]delayport_pin_list @@ -11090,7 +11104,7 @@ -rise - Set the arrival time for the rising edge of the input. + Set the arrival time for the rising edge of the input. @@ -11098,7 +11112,7 @@ -fall - Set the arrival time for the falling edge of the input. + Set the arrival time for the falling edge of the input. @@ -11107,7 +11121,7 @@ -max - Set the maximum arrival time. + Set the maximum arrival time. @@ -11115,7 +11129,7 @@ -min - Set the minimum arrival time. + Set the minimum arrival time. @@ -11147,7 +11161,7 @@ -source_latency_included - D no add the clock source latency (insertion delay) to the delay value. + D no add the clock source latency (insertion delay) to the delay value. @@ -11155,7 +11169,7 @@ -network_latency_included - Do not add the clock latency to the delay value when the clock is ideal. + Do not add the clock latency to the delay value when the clock is ideal. @@ -11184,19 +11198,19 @@ The set_input_delay command is used to specify the arrival time of an input signal. - The following command sets the min, max, rise and fall times on the in1 input port 1.0 time units after the rising edge of clk1. + The following command sets the min, max, rise and fall times on the in1 input port 1.0 time units after the rising edge of clk1. set_input_delay -clock clk1 1.0 [get_ports in1] - Use multiple commands with the -add_delay option to specifiy separate arrival times for min, max, rise and fall times or multiple clocks. For example, the following specifies separate arrival times with respect to clocks clk1 and clk2. - set_input_delay -clock clk1 1.0 [get_ports in1]set_input_delay -add_delay -clock clk2 2.0 [get_ports in1] + Use multiple commands with the -add_delay option to specify separate arrival times for min, max, rise and fall times or multiple clocks. For example, the following specifies separate arrival times with respect to clocks clk1 and clk2. + set_input_delay -clock clk1 1.0 [get_ports in1]set_input_delay -add_delay -clock clk2 2.0 [get_ports in1] The –reference_pin option is used to specify an arrival time with respect to the arrival on a pin in the clock network. For propagated clocks, the input arrival time is relative to the clock arrival time at the reference pin (the clock source latency and network latency from the clock source to the reference pin). For ideal clocks, input arrival time is relative to the reference pin clock source latency. With the -clock_fall flag the arrival time is relative to the falling transition at the reference pin. If no clocks arrive at the reference pin the set_input_delay command is ignored. If no -clock is specified the arrival time is with respect to all clocks that arrive at the reference pin. The -source_latency_included and -network_latency_included options cannot be used with -reference_pin. - Paths from inputs that do not have an arrival time defined by set_input_delay are not reported. Set the sta_input_port_default_clock variable to 1 to report paths from inputs without a set_input_delay. + Paths from inputs that do not have an arrival time defined by set_input_delay are not reported. Set the sta_input_port_default_clock variable to 1 to report paths from inputs without a set_input_delay. - set_input_transition + set_input_transition [-rise][-fall][-max][-min]transitionport_list @@ -11207,7 +11221,7 @@ -rise - Set the rising edge transition. + Set the rising edge transition. @@ -11215,7 +11229,7 @@ -fall - Set the falling edge transition. + Set the falling edge transition. @@ -11223,7 +11237,7 @@ -max - Set the minimum transition time. + Set the minimum transition time. @@ -11231,7 +11245,7 @@ -min - Set the maximum transition time. + Set the maximum transition time. @@ -11257,7 +11271,7 @@ - set_level_shifter_strategy + set_level_shifter_strategy [-rule rule_type] @@ -11270,7 +11284,7 @@ - set_level_shifter_threshold + set_level_shifter_threshold [-voltage voltage] @@ -11283,7 +11297,7 @@ - set_load + set_load [-rise][-fall][-max][-min][-subtract_pin_load][-pin_load][-wire_load]capacitanceobjects @@ -11294,7 +11308,7 @@ -rise - Set the external port rising capacitance (ports only). + Set the external port rising capacitance (ports only). @@ -11302,7 +11316,7 @@ -fall - Set the external port falling capacitance (ports only). + Set the external port falling capacitance (ports only). @@ -11311,7 +11325,7 @@ -max - Set the max capacitance. + Set the max capacitance. @@ -11319,7 +11333,7 @@ -min - Set the min capacitance. + Set the min capacitance. @@ -11327,7 +11341,7 @@ -subtract_pin_load - Subtract the capacitance of all instance pins connected to the net from capacitance (nets only). If the resulting capacitance is negative, zero is used. Pin capacitances are ignored by delay calculatioin when this option is used. + Subtract the capacitance of all instance pins connected to the net from capacitance (nets only). If the resulting capacitance is negative, zero is used. Pin capacitances are ignored by delay calculation when this option is used. @@ -11335,7 +11349,7 @@ -pin_load - capcitance is external instance pin capacitance (ports only). + capacitance is external instance pin capacitance (ports only). @@ -11343,7 +11357,7 @@ -wire_load - capcitance is external wire capacitance (ports only). + capacitance is external wire capacitance (ports only). @@ -11363,16 +11377,16 @@ - The set_load command annotates wire capacitance on a net or external capacitance on a port. There are four different uses for the set_load commanc: - set_load -wire_load port external port wire capacitanceset_load -pin_load port external port pin capacitanceset_load port same as -pin_loadset_load net net wire capacitance - External port capacitance can be annotated separately with the -pin_load and ‑wire_load options. Without the -pin_load and -wire_load options pin capacitance is annotated. - When annnotating net wire capacitance with the -subtract_pin_load option the capacitance of all instance pins connected to the net is subtracted from capacitance. Setting the capacitance on a net overrides SPEF parasitics for delay calculation. + The set_load command annotates wire capacitance on a net or external capacitance on a port. There are four different uses for the set_load commanc: + set_load -wire_load port external port wire capacitanceset_load -pin_load port external port pin capacitanceset_load port same as -pin_loadset_load net net wire capacitance + External port capacitance can be annotated separately with the -pin_load and ‑wire_load options. Without the -pin_load and -wire_load options pin capacitance is annotated. + When annotating net wire capacitance with the -subtract_pin_load option the capacitance of all instance pins connected to the net is subtracted from capacitance. Setting the capacitance on a net overrides SPEF parasitics for delay calculation. - set_logic_dc + set_logic_dc port_list @@ -11393,7 +11407,7 @@ - set_logic_one + set_logic_one port_list @@ -11408,14 +11422,14 @@ - Set a port or pin to a constant logic one value. No paths are propagated from constant pins. Constant values set with the set_logic_one command are not propagated through downstream gates. + Set a port or pin to a constant logic one value. No paths are propagated from constant pins. Constant values set with the set_logic_one command are not propagated through downstream gates. - set_logic_zero + set_logic_zero port_list @@ -11430,13 +11444,13 @@ - Set a port or pin to a constant logic zero value. No paths are propagated from constant pins. Constant values set with the set_logic_zero command are not propagated through downstream gates. + Set a port or pin to a constant logic zero value. No paths are propagated from constant pins. Constant values set with the set_logic_zero command are not propagated through downstream gates. - set_max_area + set_max_area area @@ -11457,7 +11471,7 @@ - set_max_capacitance + set_max_capacitance capacitanceobjects @@ -11486,10 +11500,10 @@ - set_max_delay + set_max_delay - [-rise][-fall][-from from_list][-rise_from from_list][-fall_from from_list][-through through_list][-rise_through through_list][-fall_through through_list][-to to_list][-rise_to to_list][-fall_to to_list][-ignore_clock_latency][-probe][-reset_path]delay + [-rise][-fall][-from from_list][-rise_from from_list][-fall_from from_list][-through through_list][-rise_through through_list][-fall_through through_list][-to to_list][-rise_to to_list][-fall_to to_list][-ignore_clock_latency][-probe][-reset_path]delay @@ -11497,7 +11511,7 @@ -rise - Set max delay for rising paths. + Set max delay for rising paths. @@ -11505,13 +11519,13 @@ -fall - Set max delay for falling paths. + Set max delay for falling paths. - -from from_list + -from from_list A list of clocks, instances, ports or pins. @@ -11519,7 +11533,7 @@ - -through through_list + -through through_list A list of instances, pins or nets. @@ -11527,7 +11541,7 @@ - -to to_list + -to to_list A list of clocks, instances, ports or pins. @@ -11573,7 +11587,7 @@ - set_max_dynamic_power + set_max_dynamic_power power [unit] @@ -11586,7 +11600,7 @@ - set_max_fanout + set_max_fanout fanoutobjects @@ -11615,7 +11629,7 @@ - set_max_leakage_power + set_max_leakage_power power [unit] @@ -11628,7 +11642,7 @@ - set_max_time_borrow + set_max_time_borrow delayobjects @@ -11652,13 +11666,13 @@ - The set_max_time_borrow command specifies the maximum amount of time that latches can borrow. Time borrowing is the time that a data input to a transparent latch arrives after the latch opens. + The set_max_time_borrow command specifies the maximum amount of time that latches can borrow. Time borrowing is the time that a data input to a transparent latch arrives after the latch opens. - set_max_transition + set_max_transition [-data_path][-clock_path][-rise][-fall]transitionobjects @@ -11701,7 +11715,7 @@ transition - The maximum slew/transition time. + The maximum slew/transition time. @@ -11713,7 +11727,7 @@ - The set_max_transition command is specifies the maximum transition time (slew) design rule checked by the report_check_types –max_transition command. + The set_max_transition command is specifies the maximum transition time (slew) design rule checked by the report_check_types –max_transition command. If specified for a design, the default maximum transition is set for the design. If specified for a clock, the maximum transition is applied to all pins in the clock domain. The –clock_path option restricts the maximum transition to clocks in clock paths. The -data_path option restricts the maximum transition to clocks data paths. The –clock_path, -data_path, -rise and –fall options only apply to clock objects. @@ -11721,7 +11735,7 @@ - set_min_capacitance + set_min_capacitance capacitanceobjects @@ -11751,10 +11765,10 @@ - set_min_delay + set_min_delay - [-rise][-fall][-from from_list][-rise_from from_list][-fall_from from_list][-through through_list][-rise_through through_list][-fall_through through_list][-to to_list][-rise_to to_list][-fall_to to_list][-ignore_clock_latency][-probe][-reset_path]delay + [-rise][-fall][-from from_list][-rise_from from_list][-fall_from from_list][-through through_list][-rise_through through_list][-fall_through through_list][-to to_list][-rise_to to_list][-fall_to to_list][-ignore_clock_latency][-probe][-reset_path]delay @@ -11762,7 +11776,7 @@ -rise - Set min delay for rising paths. + Set min delay for rising paths. @@ -11770,12 +11784,12 @@ -fall - Set min delay for falling paths. + Set min delay for falling paths. - -from from_list + -from from_list A list of clocks, instances, ports or pins. @@ -11783,7 +11797,7 @@ - -through through_list + -through through_list A list of instances, pins or nets. @@ -11791,7 +11805,7 @@ - -to to_list + -to to_list A list of clocks, instances, ports or pins. @@ -11826,7 +11840,7 @@ delay - The minimum delay. + The minimum delay. @@ -11838,7 +11852,7 @@ - set_min_pulse_width + set_min_pulse_width [-high][-low]min_widthobjects @@ -11883,7 +11897,7 @@ - set_multicycle_path + set_multicycle_path [-setup][-hold][-rise][-fall][-start][-end][-from from_list][-rise_from from_list][-fall_from from_list][-through through_list][-rise_through through_list][-fall_through through_list][-to to_list][-rise_to to_list][-fall_to to_list][-reset_path]path_multiplier @@ -11894,7 +11908,7 @@ -setup - Set cycle count for setup checks. + Set cycle count for setup checks. @@ -11902,7 +11916,7 @@ -hold - Set cycle count for hold checks. + Set cycle count for hold checks. @@ -11910,7 +11924,7 @@ -rise - Set cycle count for rising path edges. + Set cycle count for rising path edges. @@ -11918,7 +11932,7 @@ -fall - Set cycle count for falling path edges. + Set cycle count for falling path edges. @@ -11940,7 +11954,7 @@ - -from from_list + -from from_list A list of clocks, instances, ports or pins. @@ -11948,7 +11962,7 @@ - -through through_list + -through through_list A list of instances, pins or nets. @@ -11956,7 +11970,7 @@ - -to to_list + -to to_list A list of clocks, instances, ports or pins. @@ -11985,7 +11999,7 @@ - set_operating_conditions + set_operating_conditions [-analysis_type single|bc_wc|on_chip_variation][-library lib][condition][-min min_condition][-max max_condition][-min_library min_lib][-max_library max_lib] @@ -12012,12 +12026,12 @@ ‑analysis_type on_chip_variation - The min and max operating conditions represent variations on the chip that can occur simultaineously. Setup checks use max_condition for data paths and min_condition for clock paths. Hold checks use min_condition for data paths and max_condition for clock paths. This is the default analysis type. + The min and max operating conditions represent variations on the chip that can occur simultaneously. Setup checks use max_condition for data paths and min_condition for clock paths. Hold checks use min_condition for data paths and max_condition for clock paths. This is the default analysis type. - -library lib + -library lib The name of the library that contains condition. @@ -12033,7 +12047,7 @@ - -min min_condition + -min min_condition The operating condition to use for min paths and hold checks. @@ -12041,7 +12055,7 @@ - -max max_condition + -max max_condition The operating condition to use for max paths and setup checks. @@ -12057,7 +12071,7 @@ - -max_library max_lib + -max_library max_lib The name of the library that contains max_condition. @@ -12070,7 +12084,7 @@ - set_output_delay + set_output_delay [-rise][-fall][-max][-min][-clock clock][-clock_fall][-reference_pin ref_pin][-source_latency_included][-network_latency_included][-add_delay]delayport_pin_list @@ -12081,7 +12095,7 @@ -rise - Set the output delay for the rising edge of the input. + Set the output delay for the rising edge of the input. @@ -12089,7 +12103,7 @@ -fall - Set the output delay for the falling edge of the input. + Set the output delay for the falling edge of the input. @@ -12097,7 +12111,7 @@ -max - Set the maximum output delay. + Set the maximum output delay. @@ -12105,7 +12119,7 @@ -min - Set the minimum output delay. + Set the minimum output delay. @@ -12113,7 +12127,7 @@ -clock clock - The external check is to clock. The default clock edge is rising. + The external check is to clock. The default clock edge is rising. @@ -12121,7 +12135,7 @@ -clock_fall - The external check is to the falling edge of clock. + The external check is to the falling edge of clock. @@ -12129,7 +12143,7 @@ -reference_pin ref_pin - The external check is clocked by the clock that arrives at ref_pin. + The external check is clocked by the clock that arrives at ref_pin. @@ -12137,7 +12151,7 @@ -add_delay - Add this output delay to any existing output delays. + Add this output delay to any existing output delays. @@ -12145,7 +12159,7 @@ delay - The external delay to the check clocked by clock. + The external delay to the check clocked by clock. @@ -12157,17 +12171,17 @@ - The set_output_delay command is used to specify the external delay to a setup/hold check on an output port or internal pin that is clocked by clock. Unless the -add_delay option is specified any existing output delays are replaced. - The –reference_pin option is used to specify a timing check with respect to the arrival on a pin in the clock network. For propagated clocks, the timing check is relative to the clock arrival time at the reference pin (the clock source latency and network latency from the clock source to the reference pin). For ideal clocks, the timing check is relative to the reference pin clock source latency. With the -clock_fall flag the timing check is relative to the falling edge of the reference pin. If no clocks arrive at the reference pin the set_output_delay command is ignored. If no -clock is specified the timing check is with respect to all clocks that arrive at the reference pin. The -source_latency_included and -network_latency_included options cannot be used with -reference_pin. + The set_output_delay command is used to specify the external delay to a setup/hold check on an output port or internal pin that is clocked by clock. Unless the -add_delay option is specified any existing output delays are replaced. + The –reference_pin option is used to specify a timing check with respect to the arrival on a pin in the clock network. For propagated clocks, the timing check is relative to the clock arrival time at the reference pin (the clock source latency and network latency from the clock source to the reference pin). For ideal clocks, the timing check is relative to the reference pin clock source latency. With the -clock_fall flag the timing check is relative to the falling edge of the reference pin. If no clocks arrive at the reference pin the set_output_delay command is ignored. If no -clock is specified the timing check is with respect to all clocks that arrive at the reference pin. The -source_latency_included and -network_latency_included options cannot be used with -reference_pin. - set_port_fanout_number + set_port_fanout_number - [-min][-max]fanoutports + [-min][-max]fanoutports @@ -12175,7 +12189,7 @@ -min - Set the min fanout. + Set the min fanout. @@ -12183,7 +12197,7 @@ -max - Set the max fanout. + Set the max fanout. @@ -12209,15 +12223,15 @@ - set_power_activity + set_power_activity - [-global][-input][-input_ports ports][-pins pins][-activity activity | -density density][-duty duty][-clock clock] + [-global][-input][-input_ports ports][-pins pins][-activity activity | -density density][-duty duty][-clock clock] - -global + -global Set the activity/duty for all non-clock pins. @@ -12233,7 +12247,7 @@ - -input_ports input_ports + -input_ports input_ports Set the input port activity/duty. @@ -12241,7 +12255,7 @@ - -pins pins + -pins pins Set the pin activity/duty. @@ -12249,46 +12263,46 @@ - -activity activity + -activity activity - The activity, or number of transitions per clock cycle. If clock is not specified the clock with the minimum period is used. If no clocks are defined an error is reported. + The activity, or number of transitions per clock cycle. If clock is not specified the clock with the minimum period is used. If no clocks are defined an error is reported. - -density density + -density density - Transitioins per library time unit. + Transitions per library time unit. - -duty duty + -duty duty - The duty, or probability the signal is high (0 <= duty <= 1.0). Defaults to 0.5. + The duty, or probability the signal is high (0 <= duty <= 1.0). Defaults to 0.5. - -clock clock + -clock clock The clock to use for the period with -activity. This option is ignored if -density is used. - The set_power_activity command is used to set the activity and duty used for power analysis globally or for input ports or pins in the design. - The default input activity for inputs is 0.1 transitions per minimum clock period if a clock is defined or 0.0 if there are no clocks defined. The default input duty is 0.5. This is equivalent to the following command: - set_power_activity -input -activity 0.1 -duty 0.5 + The set_power_activity command is used to set the activity and duty used for power analysis globally or for input ports or pins in the design. + The default input activity for inputs is 0.1 transitions per minimum clock period if a clock is defined or 0.0 if there are no clocks defined. The default input duty is 0.5. This is equivalent to the following command: + set_power_activity -input -activity 0.1 -duty 0.5 - set_propagated_clock + set_propagated_clock objects @@ -12309,7 +12323,7 @@ - set_pvt + set_pvt [-min][-max][-process process][-voltage voltage] @@ -12321,7 +12335,7 @@ -min - Set the PVT values for max delays. + Set the PVT values for max delays. @@ -12329,12 +12343,12 @@ -max - Set the PVT values for min delays. + Set the PVT values for min delays. - -process process + -process process A process value (float). @@ -12342,7 +12356,7 @@ - -voltage voltage + -voltage voltage A voltage value (float). @@ -12350,7 +12364,7 @@ - -temperature temperature + -temperature temperature A temperature value (float). @@ -12372,7 +12386,7 @@ - set_sense + set_sense [-type clock|data][-positive][-negative][-pulse pulse_type][-stop_propagation][-clock clocks]pins @@ -12399,7 +12413,7 @@ -positive - The clock sense is positive unate. + The clock sense is positive unate. @@ -12407,7 +12421,7 @@ -negative - The clock sense is negative unate. + The clock sense is negative unate. @@ -12415,7 +12429,7 @@ -pulse pulse_type - rise_triggered_high_pulserise_triggered_low_pulsefall_triggered_high_pulsefall_triggered_low_pulseNot supported. + rise_triggered_high_pulserise_triggered_low_pulsefall_triggered_high_pulsefall_triggered_low_pulseNot supported. @@ -12450,7 +12464,7 @@ - set_timing_derate + set_timing_derate [-rise][-fall][-early][-late][-clock][-data][-net_delay][-cell_delay][-cell_check]derate[objects] @@ -12458,7 +12472,7 @@ - -rise + -rise Set the derating for rising delays. @@ -12466,7 +12480,7 @@ - -fall + -fall Set the derating for falling delays. @@ -12533,7 +12547,7 @@ derate - The derating factor to apply to delays. + The derating factor to apply to delays. @@ -12552,10 +12566,10 @@ - set_resistance + set_resistance - [-max][-min]resistancenets + [-max][-min]resistancenets @@ -12585,7 +12599,7 @@ - nets + nets A list of nets. @@ -12598,10 +12612,10 @@ - set_units + set_units - [-capacitance cap_unit][-resistance res_unit][-time time_unit][-voltage voltage_unit][-current current_unit][-power power_unit][-distance distance_unit] + [-capacitance cap_unit][-resistance res_unit][-time time_unit][-voltage voltage_unit][-current current_unit][-power power_unit][-distance distance_unit] @@ -12653,7 +12667,7 @@ - The set_units command is used to check the units used by the STA command interpreter when parsing commands and reporting results. If the current units differ from the set_unit value a warning is printed. Use the set_cmd_units command to change the command units. + The set_units command is used to check the units used by the STA command interpreter when parsing commands and reporting results. If the current units differ from the set_unit value a warning is printed. Use the set_cmd_units command to change the command units. Units are specified as a scale factor followed by a unit name. The scale factors are as follows. M 1E+6k 1E+3m 1E-3u 1E-6n 1E-9p 1E-12f 1E-15 An example of the set_units command is shown below. @@ -12663,7 +12677,7 @@ - set_wire_load_min_block_size + set_wire_load_min_block_size size @@ -12676,7 +12690,7 @@ - set_wire_load_mode + set_wire_load_mode top|enclosed|segmented @@ -12713,7 +12727,7 @@ - set_wire_load_model + set_wire_load_model -name model_name[-library library][-max][-min][objects] @@ -12766,7 +12780,7 @@ - set_wire_load_selection_group + set_wire_load_selection_group [-library library][-max][-min]group_name[objects] @@ -12820,28 +12834,28 @@ - suppress_msg + suppress_msg - msg_ids + msg_ids - msg_ids + msg_ids - A list of error/warning message IDs to suppress. + A list of error/warning message IDs to suppress. - The suppress_msg command suppresses specified error/warning messages by ID. The list of message IDs can be found in doc/messages.txt. + The suppress_msg command suppresses specified error/warning messages by ID. The list of message IDs can be found in doc/messages.txt. - unset_case_analysis + unset_case_analysis port_or_pin_list @@ -12862,7 +12876,7 @@ - unset_clock_latency + unset_clock_latency [-source]objects @@ -12891,7 +12905,7 @@ - unset_clock_transition + unset_clock_transition clocks @@ -12913,7 +12927,7 @@ - unset_clock_uncertainty + unset_clock_uncertainty [-from|-rise_from|-fall_from from_clock][-to|-rise_to|-fall_to to_clock][-rise][-fall][-setup][-hold][objects] @@ -12990,10 +13004,10 @@ - unset_data_check + unset_data_check - [-from|-rise_from|-fall_from from_object][-to|-rise_to|-fall_to to_object][-setup][-hold][-clock clock] + [-from|-rise_from|-fall_from from_object][-to|-rise_to|-fall_to to_object][-setup][-hold][-clock clock] @@ -13043,7 +13057,7 @@ - unset_disable_inferred_clock_gating + unset_disable_inferred_clock_gating objects @@ -13058,13 +13072,13 @@ - The unset_disable_inferred_clock_gating command removes a previous set_disable_inferred_clock_gating command. + The unset_disable_inferred_clock_gating command removes a previous set_disable_inferred_clock_gating command. - unset_disable_timing + unset_disable_timing [-from from_port][-to to_port]objects @@ -13101,7 +13115,7 @@ - unset_input_delay + unset_input_delay [-rise][-fall][-max][-min][-clock clock][-clock_fall]port_pin_list @@ -13112,7 +13126,7 @@ -rise - Unset the arrival time for the rising edge of the input. + Unset the arrival time for the rising edge of the input. @@ -13120,7 +13134,7 @@ -fall - Unset the arrival time for the falling edge of the input. + Unset the arrival time for the falling edge of the input. @@ -13128,7 +13142,7 @@ -max - Unset the minimum arrival time. + Unset the minimum arrival time. @@ -13136,7 +13150,7 @@ -min - Unset the maximum arrival time. + Unset the maximum arrival time. @@ -13144,7 +13158,7 @@ clock - Unset the arrival time from clock. + Unset the arrival time from clock. @@ -13152,7 +13166,7 @@ -clock_fall - Unset the arrival time from the falling edge of clock + Unset the arrival time from the falling edge of clock @@ -13171,7 +13185,7 @@ - unset_output_delay + unset_output_delay [-rise][-fall][-max][-min][-clock clock][-clock_fall]port_pin_list @@ -13240,10 +13254,10 @@ - unset_path_exceptions + unset_path_exceptions - [-setup][-hold][-rise][-fall][-from|-rise_from|-fall_from from][-through|-rise_through|-fall_through through][-to|-rise_to|-fall_to to] + [-setup][-hold][-rise][-fall][-from|-rise_from|-fall_from from][-through|-rise_through|-fall_through through][-to|-rise_to|-fall_to to] @@ -13251,7 +13265,7 @@ -setup - Unset path exceptions for setup checks. + Unset path exceptions for setup checks. @@ -13259,7 +13273,7 @@ -hold - Unset path exceptions for hold checks. + Unset path exceptions for hold checks. @@ -13267,7 +13281,7 @@ -rise - Unset path exceptions for rising path edges. + Unset path exceptions for rising path edges. @@ -13276,12 +13290,12 @@ -fall - Unset path exceptions for falling path edges. + Unset path exceptions for falling path edges. - -from from + -from from A list of clocks, instances, ports or pins. @@ -13289,7 +13303,7 @@ - -through through + -through through A list of instances, pins or nets. @@ -13297,7 +13311,7 @@ - -to to + -to to A list of clocks, instances, ports or pins. @@ -13311,15 +13325,15 @@ - unset_power_activity + unset_power_activity - [-global][-input][-input_ports ports][-pins pins] + [-global][-input][-input_ports ports][-pins pins] - -global + -global Set the activity/duty for all non-clock pins. @@ -13335,7 +13349,7 @@ - -input_ports input_ports + -input_ports input_ports Set the input port activity/duty. @@ -13343,7 +13357,7 @@ - -pins pins + -pins pins Set the pin activity/duty. @@ -13351,20 +13365,20 @@ - -activity activity + -activity activity - The activity, or number of transitions per clock cycle. If clock is not specified the clock with the minimum period is used. If no clocks are defined an error is reported. + The activity, or number of transitions per clock cycle. If clock is not specified the clock with the minimum period is used. If no clocks are defined an error is reported. - The unset_power_activity_command is used to undo the efffects of the set_power_activity command. + The unset_power_activity_command is used to undo the effects of the set_power_activity command. - unset_propagated_clock + unset_propagated_clock objects @@ -13385,7 +13399,7 @@ - unset_timing_derate + unset_timing_derate @@ -13399,28 +13413,28 @@ - unsuppress_msg + unsuppress_msg - msg_ids + msg_ids - msg_ids + msg_ids - A list of error/warning message IDs to unsuppress. + A list of error/warning message IDs to unsuppress. - The unsuppress_msg command removes suppressions for the specified error/warning messages by ID. The list of message IDs can be found in doc/messages.txt. + The unsuppress_msg command removes suppressions for the specified error/warning messages by ID. The list of message IDs can be found in doc/messages.txt. - user_run_time + user_run_time @@ -13433,7 +13447,7 @@ - with_output_to_variable + with_output_to_variable var { commands } @@ -13456,16 +13470,16 @@ - The with_output_to_variable command redirects the output of TCL commands to a variable. + The with_output_to_variable command redirects the output of TCL commands to a variable. - write_path_spice + write_path_spice - -path_args path_args-spice_directory spice_directory-lib_subckt_file lib_subckts_file-model_file model_file-power power-ground ground[-simulator hspice|ngspice|xyce] + -path_args path_args-spice_directory spice_directory-lib_subckt_file lib_subckts_file-model_file model_file-power power-ground ground[-simulator hspice|ngspice|xyce] @@ -13481,7 +13495,7 @@ spice_directory - Directory for spice to write output files. + Directory for spice to write output files. @@ -13518,7 +13532,7 @@ - -simulator + -simulator Simulator that will read the spice netlist. @@ -13536,7 +13550,7 @@ - write_sdc + write_sdc [-digits digits][-gzip][-no_timestamp]filename @@ -13555,7 +13569,7 @@ -gzip - Compress the SDC with gzip. + Compress the SDC with gzip. @@ -13581,7 +13595,7 @@ - write_sdf + write_sdf [-corner corner][-divider /|.][-include_typ][-digits digits][-gzip][-no_timestamp][-no_version]filename @@ -13592,7 +13606,7 @@ corner - Write delays for corner. + Write delays for corner. @@ -13614,7 +13628,7 @@ - -digits digits + -digits digits The number of digits after the decimal point to report. The default is 4. @@ -13625,7 +13639,7 @@ -gzip - Compress the SDF using gzip. + Compress the SDF using gzip. @@ -13649,42 +13663,42 @@ filename - The SDF filename to write. + The SDF filename to write. - Write the delay calculation delays for the design in SDF format to filename. If -corner is not specified the min/max delays are across all corners. With -corner the min/max delays for corner are written. The SDF TIMESCALE is same as the time_unit in the first liberty file read. + Write the delay calculation delays for the design in SDF format to filename. If -corner is not specified the min/max delays are across all corners. With -corner the min/max delays for corner are written. The SDF TIMESCALE is same as the time_unit in the first liberty file read. - write_timing_model + write_timing_model - [-library_name lib_name][-cell_name cell_name] - [-corner corner]filename + [-library_name lib_name][-cell_name cell_name] + [-corner corner]filename - -library_name lib_name + -library_name lib_name - The name to use for the liberty library. Defaults to cell_name. + The name to use for the liberty library. Defaults to cell_name. - -cell_name cell_name + -cell_name cell_name - The name to use for the liberty cell. Defaults to the top level module name. + The name to use for the liberty cell. Defaults to the top level module name. - -corner corner + -corner corner The process corner to use for extracting the model. @@ -13695,16 +13709,16 @@ filename - Filename for the liberty timing model. + Filename for the liberty timing model. - The write_timing_model command constructs a liberty timing model for the current design and writes it to filename. cell_name defaults to the cell name of the top level block in the design. - The SDC used to extract the block should include the clock definitions. If the block contains a clock network set_propagated_clock should be used so the clock delays are included in the timing model. The following SDC commands are ignored when bulding the timing model. - set_input_delayset_output_delayset_loadset_timing_derate - Using set_input_transition with the slew from the block context will be used will improve the match between the timing model and the block netlist. Paths defined on clocks that are defined on internal pins are ignored because the model has no way to include the clock definition. + The write_timing_model command constructs a liberty timing model for the current design and writes it to filename. cell_name defaults to the cell name of the top level block in the design. + The SDC used to extract the block should include the clock definitions. If the block contains a clock network set_propagated_clock should be used so the clock delays are included in the timing model. The following SDC commands are ignored when building the timing model. + set_input_delayset_output_delayset_loadset_timing_derate + Using set_input_transition with the slew from the block context will be used will improve the match between the timing model and the block netlist. Paths defined on clocks that are defined on internal pins are ignored because the model has no way to include the clock definition. The resulting timing model can be used in a hierarchical timing flow as a replacement for the block to speed up timing analysis. This hierarchical timing methodology does not handle timing exceptions that originate or terminate inside the block. The timing model includes: - combinational paths between inputs and outputssetup and hold timing constraints on inputsclock to output timing paths + combinational paths between inputs and outputssetup and hold timing constraints on inputsclock to output timing paths Resistance of long wires on inputs and outputs of the block cannot be modeled in Liberty. To reduce inaccuracies from wire resistance in technologies with resistive wires place buffers on inputs and ouputs. The extracted timing model setup/hold checks are scalar (no input slew dependence). Delay timing arcs are load dependent but do not include input slew dependency. @@ -13712,7 +13726,7 @@ - write_verilog + write_verilog [-sort] @@ -13721,7 +13735,7 @@ - -sort + -sort Sort the instances in the netlist. @@ -13732,7 +13746,7 @@ -include_pwr_gnd - Incluce power and ground pins on instances. + Include power and ground pins on instances. @@ -13740,7 +13754,7 @@ -remove_cells lib_cells - Liberty cells to remove from the verilog netlist. Use get_lib_cells, a list of cells names, or a cell name with wildcards. + Liberty cells to remove from the Verilog netlist. Use get_lib_cells, a list of cells names, or a cell name with wildcards. @@ -13748,12 +13762,12 @@ filename - Filename for the liberty library. + Filename for the liberty library. - The write_verilog command writes a verilog netlist to filename. Use -sort to sort the instances so the results are reproducible across operating systems. Use -remove_cells to remove instances of lib_cells from the netlist. - Filter Expressions + The write_verilog command writes a Verilog netlist to filename. Use -sort to sort the instances so the results are reproducible across operating systems. Use -remove_cells to remove instances of lib_cells from the netlist. + Filter Expressions The get_cells, get_pins, get_ports and get_timing_edges functions support filtering the returned objects by property values. Supported filter expressions are shown below. @@ -13763,7 +13777,7 @@ property - Return objects with property value equal to 1. + Return objects with property value equal to 1. @@ -13776,7 +13790,7 @@ - property=~pattern + property=~pattern Return objects with property value that matches pattern. @@ -13784,7 +13798,7 @@ - property!=value + property!=value Return objects with property value not equal to value. @@ -13792,15 +13806,15 @@ - property!~value + property!~value - Return objects with property value that does not match pattern. + Return objects with property value that does not match pattern. - expr1&&expr2 + expr1&&expr2 Return objects with expr1 and expr2. expr1 and expr2 are one of the first three property value forms shown above. @@ -13809,24 +13823,24 @@ - expr1||expr2 + expr1||expr2 Return objects with expr1 or expr2. expr1 and expr2 are one of the first three property value forms shown above. - where property is an property supported by the get_property command. Note that if there are spaces in the expression it must be enclosed in quotes so that it is a single argument. - Variables + Where property is a property supported by the get_property command. Note that if there are spaces in the expression it must be enclosed in quotes so that it is a single argument. + Variables - hierarchy_separator + hierarchy_separator - Any character. + Any character. @@ -13836,7 +13850,7 @@ - sta_bidirect_net_paths_enabled + sta_bidirect_net_paths_enabled 0|1 @@ -13849,20 +13863,20 @@ - sta_continue_on_error + sta_continue_on_error 0|1 - The include and read_sdc commands stop and report any errors encountered while reading a file unless sta_continue_on_error is 1. The default value is 0. + The include and read_sdc commands stop and report any errors encountered while reading a file unless sta_continue_on_error is 1. The default value is 0. - sta_crpr_mode + sta_crpr_mode same_pin|same_transition @@ -13875,7 +13889,7 @@ - sta_cond_default_arcs_enabled + sta_cond_default_arcs_enabled 0|1 @@ -13888,20 +13902,20 @@ - sta_crpr_enabled + sta_crpr_enabled 0|1 - During min/max timing analysis for on_chip_variation the data and clock paths may overlap. For a setup check the maximum path delays are used for the data and the minimum path delays are used for the clock. Because the gates cannot simultaneously have minimum and maximum delays the timing check slack is pessimistic. This pessimism is known as Common Reconvergent Pesssimism Removal, or “CRPR”. Enabling CRPR slows down the analysis. The default value is 1. + During min/max timing analysis for on_chip_variation the data and clock paths may overlap. For a setup check the maximum path delays are used for the data and the minimum path delays are used for the clock. Because the gates cannot simultaneously have minimum and maximum delays the timing check slack is pessimistic. This pessimism is known as Common Reconvergent Pessimism Removal, or “CRPR”. Enabling CRPR slows down the analysis. The default value is 1. - sta_dynamic_loop_breaking + sta_dynamic_loop_breaking 0|1 @@ -13914,20 +13928,20 @@ - sta_gated_clock_checks_enabled + sta_gated_clock_checks_enabled 0|1 - When sta_gated_clock_checks_enabled is 1, clock gating setup and hold timing checks are checked. The default value is 1. + When sta_gated_clock_checks_enabled is 1, clock gating setup and hold timing checks are checked. The default value is 1. - sta_input_port_default_clock + sta_input_port_default_clock 0|1 @@ -13940,7 +13954,7 @@ - sta_internal_bidirect_instance_paths_enabled + sta_internal_bidirect_instance_paths_enabled 0|1 @@ -13953,7 +13967,7 @@ - sta_pocv_enabled + sta_pocv_enabled 0|1 @@ -13966,49 +13980,49 @@ - sta_propagate_all_clocks + sta_propagate_all_clocks 0|1 - All clocks defined after sta_propagate_all_clocks is set to 1 are propagated. If it is set before any clocks are defined it has the same effect as + All clocks defined after sta_propagate_all_clocks is set to 1 are propagated. If it is set before any clocks are defined it has the same effect as set_propagated_clock [all_clocks] - after all clocks have been defined. The default value is 0. + After all clocks have been defined. The default value is 0. - sta_propagate_gated_clock_enable + sta_propagate_gated_clock_enable 0|1 - When set to 1, paths of gated clock enables are propagated through the clock gating instances. If the gated clock controls sequential elements setting sta_propagate_gated_clock_enable to 0 prevents spurious paths from the clock enable. The default value is 1. + When set to 1, paths of gated clock enables are propagated through the clock gating instances. If the gated clock controls sequential elements setting sta_propagate_gated_clock_enable to 0 prevents spurious paths from the clock enable. The default value is 1. - sta_recovery_removal_checks_enabled + sta_recovery_removal_checks_enabled 0|1 - When sta_recovery_removal_checks_enabled is 0, recovery and removal timing checks are disabled. The default value is 1. + When sta_recovery_removal_checks_enabled is 0, recovery and removal timing checks are disabled. The default value is 1. - sta_report_default_digits + sta_report_default_digits integer @@ -14021,7 +14035,7 @@ - sta_preset_clear_arcs_enabled + sta_preset_clear_arcs_enabled 0|1 @@ -14231,7 +14245,7 @@ - Version 2.6.0, Sep 23, 2024Copyright (c) 2024, Parallax Software, Inc. + Version 2.6.0, Sep 23, 2024Copyright (c) 2024, Parallax Software, Inc. This program is free software: you can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free Software Foundation, either version 3 of the License, or (at your option) any later version. This program is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details. You should have received a copy of the GNU General Public License along with this program. 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virtual Required requiredTime(const StaState *sta) const; virtual Arrival borrow(const StaState *sta) const; + virtual float targetClkTime(const StaState *sta) const; + virtual float targetClkOffset(const StaState *sta) const; Arrival targetClkWidth(const StaState *sta) const; virtual int exceptPathCmp(const PathEnd *path_end, const StaState *sta) const; diff --git a/search/Latches.cc b/search/Latches.cc index 15469083..c75028b1 100644 --- a/search/Latches.cc +++ b/search/Latches.cc @@ -93,7 +93,7 @@ Latches::latchRequired(const Path *data_path, CycleAccting *acct = sdc_->cycleAccting(data_clk_edge, enable_clk_edge); // checkTgtClkTime - float tgt_clk_time = acct->requiredTime(check_role); + float tgt_clk_time = path_delay ? 0.0 : acct->requiredTime(check_role); // checkTgtClkArrival broken down into components. Arrival enable_arrival = max_delay + tgt_clk_time diff --git a/search/PathEnd.cc b/search/PathEnd.cc index 203b3d52..aa3e7ac9 100644 --- a/search/PathEnd.cc +++ b/search/PathEnd.cc @@ -1193,6 +1193,24 @@ PathEndLatchCheck::checkRole(const StaState *sta) const return TimingRole::latchSetup(); } +float +PathEndLatchCheck::targetClkTime(const StaState *sta) const +{ + if (path_delay_) + return 0.0; + else + return PathEndClkConstrained::targetClkTime(sta); +} + +float +PathEndLatchCheck::targetClkOffset(const StaState *sta) const +{ + if (path_delay_) + return -targetClkEdge(sta)->time(); + else + return PathEndClkConstrained::targetClkOffset(sta); +} + Required PathEndLatchCheck::requiredTime(const StaState *sta) const { From 4920f673a87b3712b2f9c0f80e9f4c8bef8e6149 Mon Sep 17 00:00:00 2001 From: Akash Levy Date: Wed, 13 Aug 2025 09:53:44 -0700 Subject: [PATCH 06/13] JSON reporting: split out source clock path (#285) --- search/ReportPath.cc | 5 ++++- test/report_json1.ok | 6 ++++-- 2 files changed, 8 insertions(+), 3 deletions(-) diff --git a/search/ReportPath.cc b/search/ReportPath.cc index 5f8d5fe0..01e7cac6 100644 --- a/search/ReportPath.cc +++ b/search/ReportPath.cc @@ -1103,6 +1103,7 @@ ReportPath::reportJson(const PathEnd *end, sdc_network_->pathName(endpoint)); const ClockEdge *src_clk_edge = end->sourceClkEdge(this); + const Path *src_clk_path = expanded.clkPath(); const Path *tgt_clk_path = end->targetClkPath(); if (src_clk_edge) { stringAppend(result, " \"source_clock\": \"%s\",\n", @@ -1110,6 +1111,8 @@ ReportPath::reportJson(const PathEnd *end, stringAppend(result, " \"source_clock_edge\": \"%s\",\n", src_clk_edge->transition()->name()); } + if (src_clk_path) + reportJson(src_clk_path, "source_clock_path", 2, true, result); reportJson(expanded, "source_path", 2, !end->isUnconstrained(), result); const ClockEdge *tgt_clk_edge = end->targetClkEdge(this); @@ -1180,7 +1183,7 @@ ReportPath::reportJson(const PathExpanded &expanded, string &result) const { stringAppend(result, "%*s\"%s\": [\n", indent, "", path_name); - for (size_t i = 0; i < expanded.size(); i++) { + for (size_t i = expanded.startIndex(); i < expanded.size(); i++) { const Path *path = expanded.path(i); const Pin *pin = path->vertex(this)->pin(); const Net *net = network_->net(pin); diff --git a/test/report_json1.ok b/test/report_json1.ok index f5a1e56e..51e8ae79 100644 --- a/test/report_json1.ok +++ b/test/report_json1.ok @@ -7,7 +7,7 @@ "endpoint": "_1416_[0]/D", "source_clock": "clk", "source_clock_edge": "rise", - "source_path": [ + "source_clock_path": [ { "instance": "", "cell": "counter", @@ -25,7 +25,9 @@ "net": "clk", "arrival": 0.000e+00, "slew": 0.000e+00 - }, + } + ], + "source_path": [ { "instance": "_1415_", "cell": "sky130_fd_sc_hd__dfrtp_1", From 5b56558e7a314a57ef0b55f0074705b027db9e65 Mon Sep 17 00:00:00 2001 From: James Cherry Date: Wed, 13 Aug 2025 11:43:40 -0700 Subject: [PATCH 07/13] GraphDelayCalc::findDelays no need to visit if iter empty Signed-off-by: James Cherry --- dcalc/GraphDelayCalc.cc | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/dcalc/GraphDelayCalc.cc b/dcalc/GraphDelayCalc.cc index 531e1eeb..9106ca9d 100644 --- a/dcalc/GraphDelayCalc.cc +++ b/dcalc/GraphDelayCalc.cc @@ -260,8 +260,10 @@ GraphDelayCalc::findDelays(Level level) if (incremental_) seedInvalidDelays(); - FindVertexDelays visitor(this); - dcalc_count += iter_->visitParallel(level, &visitor); + if (!iter_->empty()) { + FindVertexDelays visitor(this); + dcalc_count += iter_->visitParallel(level, &visitor); + } // Timing checks require slews at both ends of the arc, // so find their delays after all slews are known. From 872f611fea7d7c30d8a27a76708916bf080dfbbc Mon Sep 17 00:00:00 2001 From: Matt Liberty Date: Fri, 15 Aug 2025 18:28:05 +0000 Subject: [PATCH 08/13] Support redirection for report_clock_min_period (#286) Signed-off-by: Matt Liberty --- search/Search.tcl | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/search/Search.tcl b/search/Search.tcl index 6e6aa78c..41f53a70 100644 --- a/search/Search.tcl +++ b/search/Search.tcl @@ -1111,7 +1111,7 @@ proc parse_path_group_arg { group_names } { define_cmd_args "report_clock_min_period" \ { [-clocks clocks] [-include_port_paths] } -proc report_clock_min_period { args } { +proc_redirect report_clock_min_period { parse_key_args "report_min_clock_period" args \ keys {-clocks} flags {-include_port_paths} 0 @@ -1131,7 +1131,7 @@ proc report_clock_min_period { args } { # max frequency in MHz set fmax [expr 1.0e-6 / $min_period] } - puts "[get_name $clk] period_min = [sta::format_time $min_period 2] fmax = [format %.2f $fmax]" + report_line "[get_name $clk] period_min = [sta::format_time $min_period 2] fmax = [format %.2f $fmax]" } } From 70f4bc0459a876c36b0ae9f95f7aad50ffc612db Mon Sep 17 00:00:00 2001 From: James Cherry Date: Mon, 18 Aug 2025 13:27:30 -0700 Subject: [PATCH 09/13] latch nworst thru D->Q (eagle 20250815) Signed-off-by: James Cherry --- search/PathEnum.cc | 97 +++++++++++++++++--------- search/ReportPath.cc | 162 +++++++++++++++++++++---------------------- search/ReportPath.hh | 14 ++-- 3 files changed, 150 insertions(+), 123 deletions(-) diff --git a/search/PathEnum.cc b/search/PathEnum.cc index 1f39e029..a63f76e9 100644 --- a/search/PathEnum.cc +++ b/search/PathEnum.cc @@ -35,6 +35,7 @@ #include "PathAnalysisPt.hh" #include "Tag.hh" #include "Search.hh" +#include "Latches.hh" #include "PathEnd.hh" #include "Path.hh" @@ -219,7 +220,8 @@ PathEnum::reportDiversionPath(Diversion *div) p->to_string(this).c_str(), delayAsString(p->arrival(), this), Path::equal(p, after_div, this) ? " <-after diversion" : ""); - if (p != path && network_->isLatchData(p->pin(this))) + if (p != path + && network_->isLatchData(p->pin(this))) break; p = p->prevPath(); } @@ -529,13 +531,23 @@ PathEnum::divSlack(Path *before_div, const TimingArc *div_arc, const PathAnalysisPt *path_ap) { - Arrival arc_arrival = before_div->arrival(); + Arrival before_div_arrival = before_div->arrival(); if (div_edge) { - ArcDelay div_delay = search_->deratedDelay(div_edge->from(graph_), - div_arc, div_edge, - false, path_ap); - Arrival div_arrival = search_->clkPathArrival(after_div) + div_delay; - return div_arrival - arc_arrival; + if (div_edge->role()->isLatchDtoQ()) { + Arrival div_arrival; + ArcDelay div_delay; + Tag *q_tag; + latches_->latchOutArrival(after_div, div_arc, div_edge, path_ap, + q_tag, div_delay, div_arrival); + return div_arrival - before_div_arrival; + } + else { + ArcDelay div_delay = search_->deratedDelay(div_edge->from(graph_), + div_arc, div_edge, + false, path_ap); + Arrival div_arrival = search_->clkPathArrival(after_div) + div_delay; + return div_arrival - before_div_arrival; + } } else { report()->error(1370, "path diversion missing edge."); @@ -634,39 +646,56 @@ PathEnum::updatePathHeadDelays(PathSeq &paths, Tag *prev_tag = after_div->tag(this); ClkInfo *prev_clk_info = prev_tag->clkInfo(); Arrival prev_arrival = search_->clkPathArrival(after_div); - for (int i = paths.size() - 1; i >= 0; i--) { + int path_idx_max = paths.size() - 1; + // paths[0] is the path endpoint + for (int i = path_idx_max; i >= 0; i--) { Path *path = paths[i]; TimingArc *arc = path->prevArc(this); Edge *edge = path->prevEdge(this); if (edge) { + Arrival arrival; PathAnalysisPt *path_ap = path->pathAnalysisPt(this); - ArcDelay arc_delay = search_->deratedDelay(edge->from(graph_), - arc, edge, false, path_ap); - Arrival arrival = prev_arrival + arc_delay; - debugPrint(debug_, "path_enum", 5, "update arrival %s %s %s -> %s", - path->vertex(this)->to_string(this).c_str(), - path->tag(this)->to_string(this).c_str(), - delayAsString(path->arrival(), this), - delayAsString(arrival, this)); - path->setArrival(arrival); - prev_arrival = arrival; - const Tag *tag = path->tag(this); - const ClkInfo *clk_info = tag->clkInfo(); - if (crprActive() - && clk_info != prev_clk_info - // D->Q paths use the EN->Q clk info so no need to update. - && arc->role() != TimingRole::latchDtoQ()) { - // When crpr is enabled the diverion may be from another crpr clk pin, - // so update the tags to use the corresponding ClkInfo. - Tag *updated_tag = search_->findTag(path->transition(this), - path_ap, - prev_clk_info, - tag->isClock(), - tag->inputDelay(), - tag->isSegmentStart(), - tag->states(), false); - path->setTag(updated_tag); + const MinMax *min_max = path->minMax(this); + if (i == path_idx_max + && edge->role()->isLatchDtoQ() + && min_max == MinMax::max()) { + ArcDelay arc_delay; + Tag *q_tag; + latches_->latchOutArrival(after_div, arc, edge, path_ap, + q_tag, arc_delay, arrival); + path->setArrival(arrival); + path->setTag(q_tag); + prev_clk_info = q_tag->clkInfo(); } + else { + ArcDelay arc_delay = search_->deratedDelay(edge->from(graph_), + arc, edge, false, path_ap); + arrival = prev_arrival + arc_delay; + path->setArrival(arrival); + const Tag *tag = path->tag(this); + const ClkInfo *clk_info = tag->clkInfo(); + if (crprActive() + && clk_info != prev_clk_info + // D->Q paths use the EN->Q clk info so no need to update. + && arc->role() != TimingRole::latchDtoQ()) { + // When crpr is enabled the diverion may be from another crpr clk pin, + // so update the tags to use the corresponding ClkInfo. + Tag *updated_tag = search_->findTag(path->transition(this), + path_ap, + prev_clk_info, + tag->isClock(), + tag->inputDelay(), + tag->isSegmentStart(), + tag->states(), false); + path->setTag(updated_tag); + } + debugPrint(debug_, "path_enum", 5, "update arrival %s %s %s -> %s", + path->vertex(this)->to_string(this).c_str(), + path->tag(this)->to_string(this).c_str(), + delayAsString(path->arrival(), this), + delayAsString(arrival, this)); + } + prev_arrival = arrival; } } } diff --git a/search/ReportPath.cc b/search/ReportPath.cc index 01e7cac6..889f5d53 100644 --- a/search/ReportPath.cc +++ b/search/ReportPath.cc @@ -549,8 +549,7 @@ ReportPath::reportFull(const PathEndLatchCheck *end) const if (ignore_clk_latency) { // Based on reportSrcPath. reportPathHeader(); - reportPath3(end->path(), expanded, false, false, 0.0, - end->sourceClkOffset(this)); + reportPath3(end->path(), expanded, false, end->sourceClkOffset(this)); } else reportSrcPath(end, expanded); @@ -716,8 +715,7 @@ ReportPath::reportFull(const PathEndPathDelay *end) const if (end->ignoreClkLatency(this)) { // Based on reportSrcPath. reportPathHeader(); - reportPath3(end->path(), expanded, false, false, 0.0, - end->sourceClkOffset(this)); + reportPath3(end->path(), expanded, false, end->sourceClkOffset(this)); } else reportSrcPath(end, expanded); @@ -935,11 +933,9 @@ ReportPath::reportFull(const PathEndDataCheck *end) const const ClockEdge *tgt_clk_edge = end->targetClkEdge(this); float prev = delayAsFloat(clk_arrival) + src_offset; float offset = prev - delayAsFloat(clk_delay) - tgt_clk_edge->time(); - reportPath5(data_clk_path, clk_expanded, clk_expanded.startIndex(), - clk_expanded.size() - 1, - data_clk_path->clkInfo(search_)->isPropagated(), false, - // Delay to startpoint is already included. - prev, offset); + // Delay to startpoint is already included. + reportPath6(data_clk_path, clk_expanded, clk_expanded.startIndex(), + true, false, prev, offset); } reportRequired(end, checkRoleReason(end)); reportSlack(end); @@ -1660,7 +1656,7 @@ ReportPath::reportSkewClkPath(const char *arrival_msg, insertion, latency); reportClkSrcLatency(insertion, clk_time, early_late); PathExpanded clk_expanded(clk_path, this); - reportPath2(clk_path, clk_expanded, false, 0.0); + reportPath1(clk_path, clk_expanded, false, 0.0); } } else { @@ -2229,8 +2225,8 @@ ReportPath::reportTgtClk(const PathEnd *end, PathExpanded clk_expanded(clk_path, this); float insertion_offset = tgtClkInsertionOffet(clk_path, early_late, path_ap); - reportPath5(clk_path, clk_expanded, 0, clk_expanded.size() - 1, is_prop, - reportClkPath(), delay_zero, time_offset + insertion_offset); + reportPath6(clk_path, clk_expanded, 0, is_prop, reportClkPath(), + delay_zero, time_offset + insertion_offset); } else { // Output departure. @@ -2377,7 +2373,7 @@ ReportPath::reportGenClkSrcAndPath(const Path *path, time_offset, clk_used_as_data); if (path) { PathExpanded expanded(path, this); - reportPath4(path, expanded, skip_first_path, false, clk_used_as_data, + reportPath2(path, expanded, skip_first_path, clk_used_as_data, path_time_offset); } } @@ -2419,7 +2415,7 @@ ReportPath::reportGenClkSrcPath1(const Clock *clk, reportClkSrcLatency(insertion, gclk_time, early_late); } PathExpanded src_expanded(src_path, this); - reportPath4(src_path, src_expanded, skip_first_path, false, + reportPath2(src_path, src_expanded, skip_first_path, clk_used_as_data, gclk_time); if (!clk->isPropagated()) reportLine("clock network delay (ideal)", 0.0, @@ -2603,11 +2599,51 @@ ReportPath::reportPathFull(const Path *path) const //////////////////////////////////////////////////////////////// +// Main entry point for reporting a path. void ReportPath::reportPath1(const Path *path, const PathExpanded &expanded, bool clk_used_as_data, float time_offset) const +{ + reportPath2(path, expanded, false, clk_used_as_data, time_offset); +} + +// Alternate entry point with skip_first_path arg. +void +ReportPath::reportPath2(const Path *path, + const PathExpanded &expanded, + bool skip_first_path, + bool clk_used_as_data, + float time_offset) const +{ + bool clk_is_propagated = path->clkInfo(search_)->isPropagated(); + bool report_clk_path = (reportClkPath() && clk_is_propagated) + || clk_used_as_data; + bool propagated_clk = clk_is_propagated || clk_used_as_data; + reportPath4(path, expanded, skip_first_path, propagated_clk, + report_clk_path, time_offset); +} + +// Alternate entry point with report_clk_path arg. +void +ReportPath::reportPath3(const Path *path, + const PathExpanded &expanded, + bool report_clk_path, + float time_offset) const +{ + bool propagated_clk = path->clkInfo(search_)->isPropagated(); + reportPath4(path, expanded, false, propagated_clk, + report_clk_path, time_offset); +} + +void +ReportPath::reportPath4(const Path *path, + const PathExpanded &expanded, + bool skip_first_path, + bool propagated_clk, + bool report_clk_path, + float time_offset) const { const Path *d_path, *q_path; Edge *d_q_edge; @@ -2620,11 +2656,11 @@ ReportPath::reportPath1(const Path *path, if (latch_enable_path) { const EarlyLate *early_late = latch_enable_path->minMax(this); latch_enable_time = search_->clkPathArrival(latch_enable_path); - if (reportClkPath()) { + if (report_clk_path) { PathExpanded enable_expanded(latch_enable_path, this); // Report the path to the latch enable. - reportPath2(latch_enable_path, enable_expanded, false, - time_offset); + reportPath5(latch_enable_path, enable_expanded, skip_first_path, + propagated_clk, report_clk_path, time_offset); } Arrival time = latch_enable_time + latch_time_given; Arrival incr = latch_time_given; @@ -2634,86 +2670,45 @@ ReportPath::reportPath1(const Path *path, reportLine("time borrowed from startpoint", incr, time, early_late); // Override latch D arrival with enable + given. reportPathLine(expanded.path(0), delay_zero, time, "latch_D"); - bool propagated_clk = path->clkInfo(search_)->isPropagated(); - bool report_clk_path = path->isClock(search_) || reportClkPath(); - reportPath5(path, expanded, 1, expanded.size() - 1, - propagated_clk, report_clk_path, + reportPath6(path, expanded, 1, propagated_clk, report_clk_path, latch_enable_time + latch_time_given, time_offset); } } else - reportPath2(path, expanded, clk_used_as_data, time_offset); -} - -void -ReportPath::reportPath2(const Path *path, - const PathExpanded &expanded, - bool clk_used_as_data, - float time_offset) const -{ - // Report the clock path if the end is a clock or we wouldn't have - // anything to report. - bool report_clk_path = clk_used_as_data - || (reportClkPath() - && path->clkInfo(search_)->isPropagated()); - reportPath3(path, expanded, clk_used_as_data, report_clk_path, - delay_zero, time_offset); -} - -void -ReportPath::reportPath3(const Path *path, - const PathExpanded &expanded, - bool clk_used_as_data, - bool report_clk_path, - Arrival prev_time, - float time_offset) const -{ - bool propagated_clk = clk_used_as_data - || path->clkInfo(search_)->isPropagated(); - size_t path_last_index = expanded.size() - 1; - reportPath5(path, expanded, 0, path_last_index, propagated_clk, - report_clk_path, prev_time, time_offset); -} - -void -ReportPath::reportPath4(const Path *path, - const PathExpanded &expanded, - bool skip_first_path, - bool skip_last_path, - bool clk_used_as_data, - float time_offset) const -{ - size_t path_first_index = 0; - Arrival prev_time(0.0); - if (skip_first_path) { - path_first_index = 1; - const Path *start = expanded.path(0); - prev_time = start->arrival() + time_offset; - } - size_t path_last_index = expanded.size() - 1; - if (skip_last_path - && path_last_index > 1) - path_last_index--; - bool propagated_clk = clk_used_as_data - || path->clkInfo(search_)->isPropagated(); - // Report the clock path if the end is a clock or we wouldn't have - // anything to report. - bool report_clk_path = path->isClock(search_) - || (reportClkPath() && propagated_clk); - reportPath5(path, expanded, path_first_index, path_last_index, - propagated_clk, report_clk_path, prev_time, time_offset); + reportPath5(path, expanded, skip_first_path, propagated_clk, + report_clk_path, time_offset); } void ReportPath::reportPath5(const Path *path, + const PathExpanded &expanded, + bool skip_first_path, + bool propagated_clk, + bool report_clk_path, + float time_offset) const +{ + size_t path_first_index = 0; + Arrival prev_time = 0.0; + if (skip_first_path) { + path_first_index = 1; + const Path *start = expanded.path(0); + prev_time = start->arrival() + time_offset; + } + reportPath6(path, expanded, path_first_index, propagated_clk, + report_clk_path, prev_time, time_offset); +} + +// This does the real workk of reporting an expanded path. +void +ReportPath::reportPath6(const Path *path, const PathExpanded &expanded, size_t path_first_index, - size_t path_last_index, bool propagated_clk, bool report_clk_path, Arrival prev_time, float time_offset) const { + size_t path_last_index = expanded.size() - 1; const MinMax *min_max = path->minMax(this); DcalcAnalysisPt *dcalc_ap = path->pathAnalysisPt(this)->dcalcAnalysisPt(); DcalcAPIndex ap_index = dcalc_ap->index(); @@ -2989,8 +2984,7 @@ ReportPath::reportInputExternalDelay(const Path *first_path, pathInputDelayRefPath(first_path, input_delay, ref_path); if (!ref_path.isNull() && reportClkPath()) { PathExpanded ref_expanded(&ref_path, this); - reportPath3(&ref_path, ref_expanded, false, true, - delay_zero, 0.0); + reportPath3(&ref_path, ref_expanded, true, 0.0); } } float input_arrival = diff --git a/search/ReportPath.hh b/search/ReportPath.hh index be229016..b9f4364b 100644 --- a/search/ReportPath.hh +++ b/search/ReportPath.hh @@ -302,24 +302,28 @@ protected: float time_offset) const; void reportPath2(const Path *path, const PathExpanded &expanded, + bool skip_first_path, bool clk_used_as_data, float time_offset) const; void reportPath3(const Path *path, const PathExpanded &expanded, - bool clk_used_as_data, bool report_clk_path, - Arrival prev_time, float time_offset) const; void reportPath4(const Path *path, const PathExpanded &expanded, - bool clk_used_as_data, bool skip_first_path, - bool skip_last_path, + bool propagated_clk, + bool report_clk_path, float time_offset) const; void reportPath5(const Path *path, + const PathExpanded &expanded, + bool skip_first_path, + bool propagated_clk, + bool report_clk_path, + float time_offset) const; + void reportPath6(const Path *path, const PathExpanded &expanded, size_t path_first_index, - size_t path_last_index, bool propagated_clk, bool report_clk_path, Arrival prev_time, From b654fd48a867bed27835e153fd8d3640f62a6666 Mon Sep 17 00:00:00 2001 From: James Cherry Date: Wed, 20 Aug 2025 16:00:33 -0700 Subject: [PATCH 10/13] read_liberty leak resolves ORFS#1184 Signed-off-by: James Cherry --- liberty/LibertyReader.cc | 2 ++ 1 file changed, 2 insertions(+) diff --git a/liberty/LibertyReader.cc b/liberty/LibertyReader.cc index 4cdbd280..df789154 100644 --- a/liberty/LibertyReader.cc +++ b/liberty/LibertyReader.cc @@ -557,6 +557,8 @@ LibertyReader::defineVisitors() defineGroupVisitor("ecsm_waveform", &LibertyReader::beginEcsmWaveform, &LibertyReader::endEcsmWaveform); + defineGroupVisitor("ecsm_waveform_set", &LibertyReader::beginEcsmWaveform, + &LibertyReader::endEcsmWaveform); } void From 255988633fe90820536b6542a6b608db4d9648bc Mon Sep 17 00:00:00 2001 From: Drew Lewis Date: Sat, 23 Aug 2025 14:34:32 -0400 Subject: [PATCH 11/13] Change DmpAlg to use preallocated arrays (#283) * Change DmpAlg to use preallocated arrays DmpAlg isn't called with nr_order_ > 3 so this change saves 9 news and 9 frees for each construction and destruction of the class. * Remove nr_order size check in DmpAlg constructor Signed-off-by: Drew Lewis --------- Signed-off-by: Drew Lewis --- dcalc/DmpCeff.cc | 37 +++++++++++++------------------------ 1 file changed, 13 insertions(+), 24 deletions(-) diff --git a/dcalc/DmpCeff.cc b/dcalc/DmpCeff.cc index abdcaa92..e5b8f85e 100644 --- a/dcalc/DmpCeff.cc +++ b/dcalc/DmpCeff.cc @@ -263,12 +263,16 @@ protected: // Driver parameter Newton-Raphson state. int nr_order_; - double *x_; - double *fvec_; - double **fjac_; - double *scale_; - double *p_; - int *index_; + + static constexpr int max_nr_order_ = 3; + + double x_[max_nr_order_]; + double fvec_[max_nr_order_]; + double fjac_storage_[max_nr_order_ * max_nr_order_]; + double *fjac_[max_nr_order_]; + double scale_[max_nr_order_]; + double p_[max_nr_order_ ]; + int index_[max_nr_order_]; // Driver slew used to check load delay. double drvr_slew_; @@ -288,27 +292,12 @@ DmpAlg::DmpAlg(int nr_order, c1_(0.0), nr_order_(nr_order) { - x_ = new double[nr_order_]; - fvec_ = new double[nr_order_]; - scale_ = new double[nr_order_]; - p_ = new double[nr_order_]; - fjac_ = new double*[nr_order_]; for (int i = 0; i < nr_order_; i++) - fjac_[i] = new double[nr_order_]; - index_ = new int[nr_order_]; + // Only use the upper left block of the matrix + fjac_[i] = fjac_storage_ + i * max_nr_order_; } -DmpAlg::~DmpAlg() -{ - delete [] x_; - delete [] fvec_; - delete [] scale_; - delete [] p_; - for (int i = 0; i < nr_order_; i++) - delete [] fjac_[i]; - delete [] fjac_; - delete [] index_; -} +DmpAlg::~DmpAlg() = default; void DmpAlg::init(const LibertyLibrary *drvr_library, From e4a1ebf00eaff4988b650bbd3682ff46530ba92a Mon Sep 17 00:00:00 2001 From: James Cherry Date: Wed, 3 Sep 2025 15:05:14 -0700 Subject: [PATCH 12/13] TaGGroup refcount to reclaim memory commit cd7169f99ab8b67323c444d4c22d065487e439c1 Author: James Cherry Date: Sun Aug 31 16:02:03 2025 -0700 reportArrivals report_tag_index Signed-off-by: James Cherry commit 658f842a776bb43eef7dbfd9a08e191c31fb9f11 Author: James Cherry Date: Mon Aug 25 16:20:50 2025 -0700 tag group ref count Signed-off-by: James Cherry Signed-off-by: James Cherry --- include/sta/Search.hh | 5 ++++- search/Search.cc | 34 +++++++++++++++++++++++++--------- search/Search.i | 5 +++-- search/Tag.cc | 2 +- search/Tag.hh | 3 +++ search/TagGroup.cc | 14 ++++++++++++++ search/TagGroup.hh | 4 ++++ 7 files changed, 54 insertions(+), 13 deletions(-) diff --git a/include/sta/Search.hh b/include/sta/Search.hh index d54a8a5b..40ddc542 100644 --- a/include/sta/Search.hh +++ b/include/sta/Search.hh @@ -356,7 +356,8 @@ public: TagGroup *tagGroup(const Vertex *vertex) const; TagGroup *tagGroup(TagGroupIndex index) const; - void reportArrivals(Vertex *vertex) const; + void reportArrivals(Vertex *vertex, + bool report_tag_index) const; Slack wnsSlack(Vertex *vertex, PathAPIndex path_ap_index); void levelsChangedBefore(); @@ -410,6 +411,7 @@ public: TagGroupIndex tag_index); void checkPrevPaths() const; void deletePaths(Vertex *vertex); + void deleteTagGroup(TagGroup *group); protected: void init(StaState *sta); @@ -645,6 +647,7 @@ protected: // Capacity of tag_groups_. TagGroupIndex tag_group_capacity_; std::mutex tag_group_lock_; + std::mutex tag_group_ref_count_lock_; // Latches data outputs to queue on the next search pass. VertexSet *pending_latch_outputs_; std::mutex pending_latch_outputs_lock_; diff --git a/search/Search.cc b/search/Search.cc index 8677dab6..2023daca 100644 --- a/search/Search.cc +++ b/search/Search.cc @@ -554,15 +554,20 @@ Search::deleteFilterTagGroups() for (TagGroupIndex i = 0; i < tag_group_next_; i++) { TagGroup *group = tag_groups_[i]; if (group - && group->hasFilterTag()) { - tag_group_set_->erase(group); - tag_groups_[group->index()] = nullptr; - tag_group_free_indices_.push_back(i); - delete group; - } + && group->hasFilterTag()) + deleteTagGroup(group); } } +void +Search::deleteTagGroup(TagGroup *group) +{ + tag_group_set_->erase(group); + tag_groups_[group->index()] = nullptr; + tag_group_free_indices_.push_back(group->index()); + delete group; +} + void Search::deleteFilterTags() { @@ -2777,6 +2782,15 @@ Search::setVertexArrivals(Vertex *vertex, filtered_arrivals_->insert(vertex); } } + if (tag_group != prev_tag_group) { + LockGuard lock(tag_group_ref_count_lock_); + tag_group->incrRefCount(); + if (prev_tag_group) { + prev_tag_group->decrRefCount(); + if (prev_tag_group->refCount() == 0) + deleteTagGroup(prev_tag_group); + } + } } } @@ -2819,12 +2833,14 @@ ReportPathLess::operator()(const Path *path1, } void -Search::reportArrivals(Vertex *vertex) const +Search::reportArrivals(Vertex *vertex, + bool report_tag_index) const { report_->reportLine("Vertex %s", vertex->to_string(this).c_str()); TagGroup *tag_group = tagGroup(vertex); if (tag_group) { - report_->reportLine("Group %u", tag_group->index()); + if (report_tag_index) + report_->reportLine("Group %u", tag_group->index()); std::vector paths; VertexPathIterator path_iter(vertex, this); while (path_iter.hasNext()) { @@ -2859,7 +2875,7 @@ Search::reportArrivals(Vertex *vertex) const path_ap->pathMinMax()->to_string().c_str(), delayAsString(path->arrival(), this), req, - tag->to_string(true, false, this).c_str(), + tag->to_string(report_tag_index, false, this).c_str(), prev_str.c_str()); } } diff --git a/search/Search.i b/search/Search.i index 73f4761a..76338830 100644 --- a/search/Search.i +++ b/search/Search.i @@ -264,9 +264,10 @@ report_tag_groups() } void -report_tag_arrivals_cmd(Vertex *vertex) +report_tag_arrivals_cmd(Vertex *vertex, + bool report_tag_index) { - Sta::sta()->search()->reportArrivals(vertex); + Sta::sta()->search()->reportArrivals(vertex, report_tag_index); } void diff --git a/search/Tag.cc b/search/Tag.cc index d4e36bae..80578548 100644 --- a/search/Tag.cc +++ b/search/Tag.cc @@ -355,7 +355,7 @@ tagCmp(const Tag *tag1, return tagStateCmp(tag1, tag2); } -int +bool tagEqual(const Tag *tag1, const Tag *tag2) { diff --git a/search/Tag.hh b/search/Tag.hh index 3fa91de2..d0e44506 100644 --- a/search/Tag.hh +++ b/search/Tag.hh @@ -140,6 +140,9 @@ public: const Tag *tag2) const; }; +bool +tagEqual(const Tag *tag1, + const Tag *tag2); int tagCmp(const Tag *tag1, const Tag *tag2, diff --git a/search/TagGroup.cc b/search/TagGroup.cc index f060463b..5a79f7de 100644 --- a/search/TagGroup.cc +++ b/search/TagGroup.cc @@ -44,6 +44,7 @@ TagGroup::TagGroup(TagGroupIndex index, bool has_loop_tag) : path_index_map_(path_index_map), hash_(pathIndexMapHash(path_index_map)), + ref_count_(0), index_(index), has_clk_tag_(has_clk_tag), has_genclk_src_tag_(has_genclk_src_tag), @@ -56,6 +57,7 @@ TagGroup::TagGroup(TagGroupIndex index, TagGroup::TagGroup(TagGroupBldr *tag_bldr) : path_index_map_(&tag_bldr->pathIndexMap()), hash_(pathIndexMapHash(path_index_map_)), + ref_count_(0), own_path_map_(false) { } @@ -66,6 +68,18 @@ TagGroup::~TagGroup() delete path_index_map_; } +void +TagGroup::incrRefCount() +{ + ref_count_++; +} + +void +TagGroup::decrRefCount() +{ + ref_count_--; +} + size_t TagGroup::pathIndexMapHash(PathIndexMap *path_index_map) { diff --git a/search/TagGroup.hh b/search/TagGroup.hh index a54f9045..74b073ab 100644 --- a/search/TagGroup.hh +++ b/search/TagGroup.hh @@ -65,6 +65,9 @@ public: size_t pathIndex(Tag *tag) const; PathIndexMap *pathIndexMap() const { return path_index_map_; } bool hasTag(Tag *tag) const; + void incrRefCount(); + void decrRefCount(); + int refCount() const { return ref_count_; } protected: static size_t pathIndexMapHash(PathIndexMap *path_index_map); @@ -72,6 +75,7 @@ protected: // tag -> path index PathIndexMap *path_index_map_; size_t hash_; + int ref_count_; unsigned int index_:tag_group_index_bits; bool has_clk_tag_:1; bool has_genclk_src_tag_:1; From 849832a951d6c93e9c7c2fede2466c14d8c2e136 Mon Sep 17 00:00:00 2001 From: Waylander <62927863+Faholan@users.noreply.github.com> Date: Thu, 4 Sep 2025 00:12:26 +0200 Subject: [PATCH 13/13] Fix an undefined behaviour and a memory leak (#289) * Use a unique_ptr to avoid leaks * Use memmove instead of memcopy As both arguments can overlap, use memmove instead of memcopy * Fix code style issues --- search/Sta.cc | 1 + util/gzstream.hh | 2 +- 2 files changed, 2 insertions(+), 1 deletion(-) diff --git a/search/Sta.cc b/search/Sta.cc index a766d927..f384a820 100644 --- a/search/Sta.cc +++ b/search/Sta.cc @@ -2963,6 +2963,7 @@ Sta::netSlack(const Net *net, slack = pin_slack; } } + delete pin_iter; return slack; } diff --git a/util/gzstream.hh b/util/gzstream.hh index ec2ded6c..26e85352 100644 --- a/util/gzstream.hh +++ b/util/gzstream.hh @@ -117,7 +117,7 @@ public: int n_putback = gptr() - eback(); if ( n_putback > 4) n_putback = 4; - memcpy( buffer + (4 - n_putback), gptr() - n_putback, n_putback); + memmove( buffer + (4 - n_putback), gptr() - n_putback, n_putback); int num = gzread( file, buffer+4, bufferSize-4); if (num <= 0) // ERROR or EOF