diff --git a/include/sta/Liberty.hh b/include/sta/Liberty.hh index cc242634..9e829504 100644 --- a/include/sta/Liberty.hh +++ b/include/sta/Liberty.hh @@ -51,6 +51,7 @@ typedef Set LibrarySet; typedef Map TableTemplateMap; typedef Vector TableTemplateSeq; typedef Map BusDclMap; +typedef Vector BusDclSeq; typedef Map ScaleFactorsMap; typedef Map WireloadMap; typedef Map WireloadSelectionMap; @@ -131,6 +132,7 @@ public: void setDelayModelType(DelayModelType type); void addBusDcl(BusDcl *bus_dcl); BusDcl *findBusDcl(const char *name) const; + BusDclSeq busDcls() const; void addTableTemplate(TableTemplate *tbl_template, TableTemplateType type); TableTemplate *findTableTemplate(const char *name, @@ -645,6 +647,7 @@ public: LibertyLibrary *libertyLibrary() const { return liberty_cell_->libertyLibrary(); } LibertyPort *findLibertyMember(int index) const; LibertyPort *findLibertyBusBit(int index) const; + BusDcl *busDcl() const { return bus_dcl_; } void setDirection(PortDirection *dir); void fanoutLoad(// Return values. float &fanout_load, @@ -766,7 +769,8 @@ protected: LibertyPort(LibertyCell *cell, const char *name, bool is_bus, - int from_index, + BusDcl *bus_dcl, + int from_index, int to_index, bool is_bundle, ConcretePortSeq *members); @@ -776,13 +780,14 @@ protected: LibertyPort *scaled_port); LibertyCell *liberty_cell_; + BusDcl *bus_dcl_; FuncExpr *function_; FuncExpr *tristate_enable_; ScaledPortMap *scaled_ports_; RiseFallMinMax capacitance_; - MinMaxFloatValues slew_limit_; // inputs and outputs + MinMaxFloatValues slew_limit_; // inputs and outputs MinMaxFloatValues cap_limit_; // outputs - float fanout_load_; // inputs + float fanout_load_; // inputs bool fanout_load_exists_; MinMaxFloatValues fanout_limit_; // outputs float min_period_; diff --git a/include/sta/Network.hh b/include/sta/Network.hh index 3631fcf9..e209f898 100644 --- a/include/sta/Network.hh +++ b/include/sta/Network.hh @@ -172,9 +172,9 @@ public: int index) const = 0; virtual int fromIndex(const Port *port) const = 0; virtual int toIndex(const Port *port) const = 0; - // Predicate to determine if subscript is within bus range. - // (toIndex > fromIndex) && fromIndex <= subscript <= toIndex - // || (fromIndex > toIndex) && fromIndex >= subscript >= toIndex + // Predicate to determine if index is within bus range. + // (toIndex > fromIndex) && fromIndex <= index <= toIndex + // || (fromIndex > toIndex) && fromIndex >= index >= toIndex bool busIndexInRange(const Port *port, int index); // Find Bundle/bus member by index. diff --git a/liberty/Liberty.cc b/liberty/Liberty.cc index 76041d99..d05a7647 100644 --- a/liberty/Liberty.cc +++ b/liberty/Liberty.cc @@ -178,6 +178,15 @@ LibertyLibrary::findBusDcl(const char *name) const return bus_dcls_.findKey(name); } +BusDclSeq +LibertyLibrary::busDcls() const +{ + BusDclSeq dcls; + for (auto name_dcl : bus_dcls_) + dcls.push_back(name_dcl.second); + return dcls; +} + void LibertyLibrary::addTableTemplate(TableTemplate *tbl_template, TableTemplateType type) @@ -1857,12 +1866,14 @@ LibertyCellPortBitIterator::next() LibertyPort::LibertyPort(LibertyCell *cell, const char *name, bool is_bus, - int from_index, + BusDcl *bus_dcl, + int from_index, int to_index, bool is_bundle, ConcretePortSeq *members) : ConcretePort(cell, name, is_bus, from_index, to_index, is_bundle, members), liberty_cell_(cell), + bus_dcl_(bus_dcl), function_(nullptr), tristate_enable_(nullptr), scaled_ports_(nullptr), diff --git a/liberty/LibertyBuilder.cc b/liberty/LibertyBuilder.cc index 44605274..b0c88ea8 100644 --- a/liberty/LibertyBuilder.cc +++ b/liberty/LibertyBuilder.cc @@ -41,7 +41,7 @@ LibertyPort * LibertyBuilder::makePort(LibertyCell *cell, const char *name) { - LibertyPort *port = new LibertyPort(cell, name, false, -1, -1, false, nullptr); + LibertyPort *port = new LibertyPort(cell, name, false, nullptr, -1, -1, false, nullptr); cell->addPort(port); return port; } @@ -49,10 +49,12 @@ LibertyBuilder::makePort(LibertyCell *cell, LibertyPort * LibertyBuilder::makeBusPort(LibertyCell *cell, const char *name, - int from_index, - int to_index) + int from_index, + int to_index, + BusDcl *bus_dcl) { - LibertyPort *port = new LibertyPort(cell, name, true, from_index, to_index, + LibertyPort *port = new LibertyPort(cell, name, true, bus_dcl, + from_index, to_index, false, new ConcretePortSeq); cell->addPort(port); makeBusPortBits(cell->library(), cell, port, name, from_index, to_index); @@ -99,7 +101,7 @@ LibertyBuilder::makePort(LibertyCell *cell, const char *bit_name, int bit_index) { - LibertyPort *port = new LibertyPort(cell, bit_name, false, + LibertyPort *port = new LibertyPort(cell, bit_name, false, nullptr, bit_index, bit_index, false, nullptr); return port; } @@ -109,7 +111,7 @@ LibertyBuilder::makeBundlePort(LibertyCell *cell, const char *name, ConcretePortSeq *members) { - LibertyPort *port = new LibertyPort(cell, name, false, -1, -1, true, members); + LibertyPort *port = new LibertyPort(cell, name, false, nullptr, -1, -1, true, members); cell->addPort(port); return port; } diff --git a/liberty/LibertyBuilder.hh b/liberty/LibertyBuilder.hh index 477f4be4..f11a4de0 100644 --- a/liberty/LibertyBuilder.hh +++ b/liberty/LibertyBuilder.hh @@ -40,7 +40,8 @@ public: virtual LibertyPort *makeBusPort(LibertyCell *cell, const char *name, int from_index, - int to_index); + int to_index, + BusDcl *bus_dcl); virtual LibertyPort *makeBundlePort(LibertyCell *cell, const char *name, ConcretePortSeq *members); diff --git a/liberty/LibertyReader.cc b/liberty/LibertyReader.cc index 5eb249b5..93354a9f 100644 --- a/liberty/LibertyReader.cc +++ b/liberty/LibertyReader.cc @@ -2726,9 +2726,8 @@ LibertyReader::visitBusType(LibertyAttr *attr) while (name_iter.hasNext()) { const char *name = name_iter.next(); debugPrint(debug_, "liberty", 1, " bus %s", name); - LibertyPort *port = builder_->makeBusPort(cell_, name, - bus_dcl->from(), - bus_dcl->to()); + LibertyPort *port = builder_->makeBusPort(cell_, name, bus_dcl->from(), + bus_dcl->to(), bus_dcl); ports_->push_back(port); } } @@ -3360,14 +3359,14 @@ LibertyReader::beginSequential(LibertyGroup *group, LibertyPort *out_port_inv = nullptr; if (out_name) { if (has_size) - out_port = builder_->makeBusPort(cell_, out_name, size - 1, 0); + out_port = builder_->makeBusPort(cell_, out_name, size - 1, 0, nullptr); else out_port = builder_->makePort(cell_,out_name); out_port->setDirection(PortDirection::internal()); } if (out_inv_name) { if (has_size) - out_port_inv = builder_->makeBusPort(cell_, out_inv_name, size - 1, 0); + out_port_inv = builder_->makeBusPort(cell_, out_inv_name, size - 1, 0, nullptr); else out_port_inv = builder_->makePort(cell_, out_inv_name); out_port_inv->setDirection(PortDirection::internal()); diff --git a/verilog/Verilog.tcl b/verilog/Verilog.tcl index 1bb2b9d4..68438af8 100644 --- a/verilog/Verilog.tcl +++ b/verilog/Verilog.tcl @@ -20,7 +20,7 @@ namespace eval sta { define_cmd_args "read_verilog" {filename} proc_redirect read_verilog { - read_verilog_cmd $args + read_verilog_cmd [file nativename [lindex $args 0]] } define_cmd_args "write_verilog" {[-sort] [-include_pwr_gnd]\