From d42b821c0067a0065e49a68cce406fa1f866281c Mon Sep 17 00:00:00 2001 From: James Cherry Date: Sat, 3 Jan 2026 16:59:35 -0800 Subject: [PATCH] rel 3.0 Signed-off-by: James Cherry --- CMakeLists.txt | 20 +- app/Main.cc | 43 +- app/StaMain.cc | 37 +- dcalc/ArcDcalcWaveforms.cc | 10 +- dcalc/ArcDcalcWaveforms.hh | 6 +- dcalc/ArcDelayCalc.cc | 5 +- dcalc/Arnoldi.hh | 2 +- dcalc/ArnoldiDelayCalc.cc | 287 +- dcalc/ArnoldiReduce.cc | 43 +- dcalc/ArnoldiReduce.hh | 16 +- dcalc/CcsCeffDelayCalc.cc | 40 +- dcalc/CcsCeffDelayCalc.hh | 13 +- dcalc/DcalcAnalysisPt.cc | 68 - dcalc/DelayCalc.cc | 14 +- dcalc/DelayCalc.i | 14 +- dcalc/DelayCalc.tcl | 166 +- dcalc/DelayCalcBase.cc | 63 +- dcalc/DelayCalcBase.hh | 29 +- dcalc/DmpCeff.cc | 429 +- dcalc/DmpCeff.hh | 25 +- dcalc/DmpDelayCalc.cc | 139 +- dcalc/FindRoot.cc | 20 +- dcalc/FindRoot.hh | 26 +- dcalc/GraphDelayCalc.cc | 577 +- dcalc/LumpedCapDelayCalc.cc | 71 +- dcalc/LumpedCapDelayCalc.hh | 15 +- dcalc/NetCaps.cc | 12 +- dcalc/NetCaps.hh | 12 +- dcalc/ParallelDelayCalc.cc | 19 +- dcalc/ParallelDelayCalc.hh | 6 +- dcalc/PrimaDelayCalc.cc | 95 +- dcalc/PrimaDelayCalc.hh | 41 +- dcalc/UnitDelayCalc.cc | 70 +- dcalc/UnitDelayCalc.hh | 32 +- doc/ApiChanges.txt | 39 + doc/ChangeLog.txt | 179 + doc/OpenSTA.fodt | 6688 +++++++++-------- doc/OpenSTA.pdf | Bin 1424501 -> 1424807 bytes examples/asap7_small_ff.lib.gz | Bin 0 -> 72203 bytes examples/asap7_small_ss.lib.gz | Bin 0 -> 72452 bytes examples/mcmm2_mode1.sdc | 2 + examples/mcmm2_mode2.sdc | 2 + examples/mcmm3.tcl | 18 + examples/multi_corner.tcl | 21 +- examples/reg1_asap7.spef | 135 + examples/reg1_asap7.v | 11 + examples/reg1_asap7_ss.spef | 135 + graph/Delay.cc | 2 +- graph/DelayFloat.cc | 60 +- graph/DelayNormal1.cc | 130 +- graph/DelayNormal2.cc | 146 +- graph/Graph.cc | 448 +- graph/Graph.i | 249 +- graph/Graph.tcl | 58 +- graph/GraphCmp.cc | 13 +- include/sta/ArcDelayCalc.hh | 73 +- include/sta/Bdd.hh | 4 +- include/sta/Bfs.hh | 26 +- include/sta/BoundedHeap.hh | 256 + include/sta/ClkNetwork.hh | 25 +- include/sta/Clock.hh | 126 +- include/sta/ClockGroups.hh | 10 +- include/sta/ClockInsertion.hh | 12 +- include/sta/ClockLatency.hh | 20 +- include/sta/ConcreteLibrary.hh | 71 +- include/sta/ConcreteNetwork.hh | 45 +- include/sta/ContainerHelpers.hh | 381 + include/sta/Corner.hh | 139 - include/sta/CycleAccting.hh | 47 +- include/sta/DataCheck.hh | 34 +- include/sta/DcalcAnalysisPt.hh | 81 - include/sta/Debug.hh | 19 +- include/sta/Delay.hh | 10 +- include/sta/DelayCalc.hh | 6 +- include/sta/DelayFloat.hh | 78 +- include/sta/DelayNormal1.hh | 84 +- include/sta/DelayNormal2.hh | 86 +- include/sta/DeratingFactors.hh | 74 +- include/sta/DisabledPorts.hh | 24 +- include/sta/EnumNameMap.hh | 16 +- include/sta/EquivCells.hh | 24 +- include/sta/Error.hh | 6 +- include/sta/ExceptionPath.hh | 277 +- include/sta/FuncExpr.hh | 59 +- include/sta/Fuzzy.hh | 10 +- include/sta/Graph.hh | 226 +- include/sta/GraphClass.hh | 38 +- include/sta/GraphCmp.hh | 12 +- include/sta/GraphDelayCalc.hh | 88 +- include/sta/Hash.hh | 4 +- include/sta/HpinDrvrLoad.hh | 15 +- include/sta/InputDrive.hh | 58 +- include/sta/InternalPower.hh | 36 +- include/sta/Iterator.hh | 76 + include/sta/LeakagePower.hh | 2 +- include/sta/Liberty.hh | 468 +- include/sta/LibertyClass.hh | 39 +- include/sta/LinearModel.hh | 4 +- include/sta/Machine.hh | 2 +- include/sta/Map.hh | 191 - include/sta/MinMax.hh | 25 +- include/sta/MinMaxValues.hh | 50 +- include/sta/Mode.hh | 95 + include/sta/Mutex.hh | 2 +- include/sta/Network.hh | 226 +- include/sta/NetworkClass.hh | 80 +- include/sta/NetworkCmp.hh | 19 +- include/sta/ObjectId.hh | 6 +- include/sta/ObjectTable.hh | 18 +- include/sta/Parasitics.hh | 210 +- include/sta/ParasiticsClass.hh | 1 - include/sta/ParseBus.hh | 38 +- include/sta/Path.hh | 69 +- include/sta/PathAnalysisPt.hh | 69 - include/sta/PathEnd.hh | 358 +- include/sta/PathExpanded.hh | 16 +- include/sta/PathGroup.hh | 181 +- include/sta/PatternMatch.hh | 22 +- include/sta/PinPair.hh | 11 +- include/sta/PortDelay.hh | 20 +- include/sta/PortDirection.hh | 2 +- include/sta/PortExtCap.hh | 51 +- include/sta/PowerClass.hh | 14 +- include/sta/Property.hh | 83 +- include/sta/Report.hh | 2 +- include/sta/ReportTcl.hh | 4 +- include/sta/RiseFallMinMax.hh | 44 +- ...teParasitics.hh => RiseFallMinMaxDelay.hh} | 24 +- include/sta/RiseFallValues.hh | 4 +- include/sta/Scene.hh | 99 + include/sta/Sdc.hh | 1288 ++-- include/sta/SdcClass.hh | 53 +- include/sta/SdcNetwork.hh | 36 +- include/sta/Search.hh | 795 +- include/sta/SearchClass.hh | 67 +- include/sta/SearchPred.hh | 114 +- include/sta/Sequential.hh | 20 +- include/sta/Set.hh | 220 - include/sta/Sta.hh | 1704 +++-- include/sta/StaMain.hh | 30 +- include/sta/StaState.hh | 44 +- include/sta/Stats.hh | 4 +- include/sta/StringSeq.hh | 6 +- include/sta/StringSet.hh | 6 +- include/sta/StringUtil.hh | 44 +- include/sta/TableModel.hh | 132 +- include/sta/TclTypeHelpers.hh | 20 +- include/sta/TimingArc.hh | 66 +- include/sta/TimingModel.hh | 12 +- include/sta/TimingRole.hh | 26 +- include/sta/TokenParser.hh | 2 +- include/sta/Transition.hh | 10 +- include/sta/Units.hh | 2 +- include/sta/UnorderedMap.hh | 203 - include/sta/UnorderedSet.hh | 139 - include/sta/Variables.hh | 5 - include/sta/Vector.hh | 146 - include/sta/VectorMap.hh | 494 ++ include/sta/VerilogReader.hh | 183 +- include/sta/VerilogWriter.hh | 6 +- include/sta/VertexId.hh | 2 +- include/sta/VisitPathEnds.hh | 167 +- include/sta/Wireload.hh | 36 +- include/sta/WriteSdc.hh | 20 +- include/sta/Zlib.hh | 2 +- liberty/EquivCells.cc | 105 +- liberty/FuncExpr.cc | 201 +- liberty/InternalPower.cc | 46 +- liberty/LeakagePower.cc | 2 +- liberty/LibExprReader.cc | 18 +- liberty/LibExprReader.hh | 6 +- liberty/LibExprReaderPvt.hh | 14 +- liberty/Liberty.cc | 833 +- liberty/Liberty.i | 45 +- liberty/Liberty.tcl | 18 +- liberty/LibertyBuilder.cc | 297 +- liberty/LibertyBuilder.hh | 151 +- liberty/LibertyExt.cc | 40 +- liberty/LibertyParser.cc | 77 +- liberty/LibertyParser.hh | 108 +- liberty/LibertyReader.cc | 1471 ++-- liberty/LibertyReader.hh | 4 +- liberty/LibertyReaderPvt.hh | 275 +- liberty/LibertyWriter.cc | 19 +- liberty/LinearModel.cc | 42 +- liberty/Sequential.cc | 16 +- liberty/TableModel.cc | 379 +- liberty/TimingArc.cc | 194 +- liberty/TimingRole.cc | 14 +- liberty/Units.cc | 6 +- liberty/Wireload.cc | 54 +- network/ConcreteLibrary.cc | 119 +- network/ConcreteNetwork.cc | 384 +- network/HpinDrvrLoad.cc | 232 +- network/Network.cc | 634 +- network/Network.i | 154 +- network/Network.tcl | 85 +- network/NetworkCmp.cc | 19 +- network/NetworkEdit.i | 12 +- network/NetworkEdit.tcl | 18 +- network/ParseBus.cc | 68 +- network/PortDirection.cc | 2 +- network/SdcNetwork.cc | 283 +- network/VerilogNamespace.cc | 28 +- parasitics/ConcreteParasitics.cc | 520 +- parasitics/ConcreteParasitics.hh | 65 +- parasitics/ConcreteParasiticsPvt.hh | 84 +- parasitics/EstimateParasitics.cc | 133 +- parasitics/EstimateParasitics.hh | 96 +- parasitics/Parasitics.cc | 107 +- parasitics/Parasitics.i | 54 +- parasitics/Parasitics.tcl | 32 +- parasitics/ReduceParasitics.cc | 269 +- parasitics/ReduceParasitics.hh | 24 +- parasitics/ReportParasiticAnnotation.cc | 40 +- parasitics/ReportParasiticAnnotation.hh | 8 +- parasitics/SpefNamespace.cc | 46 +- parasitics/SpefNamespace.hh | 4 +- parasitics/SpefParse.yy | 2 +- parasitics/SpefReader.cc | 138 +- parasitics/SpefReader.hh | 27 +- parasitics/SpefReaderPvt.hh | 71 +- power/Power.cc | 550 +- power/Power.hh | 91 +- power/Power.i | 93 +- power/Power.tcl | 264 +- power/ReportPower.cc | 247 + power/ReportPower.hh | 91 + power/SaifReader.cc | 4 +- power/SaifReaderPvt.hh | 2 +- power/VcdParse.hh | 4 +- power/VcdReader.cc | 63 +- power/VcdReader.hh | 7 +- sdc/Clock.cc | 170 +- sdc/ClockGroups.cc | 13 +- sdc/ClockInsertion.cc | 28 +- sdc/ClockLatency.cc | 20 +- sdc/CycleAccting.cc | 215 +- sdc/DataCheck.cc | 40 +- sdc/DeratingFactors.cc | 74 +- sdc/DisabledPorts.cc | 28 +- sdc/ExceptionPath.cc | 803 +- sdc/InputDrive.cc | 70 +- sdc/PinPair.cc | 6 +- sdc/PortDelay.cc | 12 +- sdc/PortExtCap.cc | 48 +- sdc/Sdc.cc | 2761 +++---- sdc/Sdc.i | 1219 +-- sdc/Sdc.tcl | 478 +- sdc/SdcGraph.cc | 396 - sdc/Variables.cc | 7 - sdc/WriteSdc.cc | 940 ++- sdc/WriteSdcPvt.hh | 163 +- sdf/ReportAnnotation.cc | 362 +- sdf/ReportAnnotation.hh | 47 +- sdf/Sdf.i | 86 +- sdf/Sdf.tcl | 50 +- sdf/SdfReader.cc | 288 +- sdf/SdfReader.hh | 4 +- sdf/SdfReaderPvt.hh | 135 +- sdf/SdfWriter.cc | 313 +- sdf/SdfWriter.hh | 16 +- search/Bdd.cc | 14 +- search/Bfs.cc | 59 +- search/CheckCapacitanceLimits.cc | 356 - search/CheckCapacitanceLimits.hh | 105 - search/CheckCapacitances.cc | 369 + search/CheckCapacitances.hh | 128 + search/CheckFanoutLimits.cc | 332 - search/CheckFanoutLimits.hh | 82 - search/CheckFanouts.cc | 334 + search/CheckFanouts.hh | 126 + search/CheckMaxSkews.cc | 237 +- search/CheckMaxSkews.hh | 63 +- search/CheckMinPeriods.cc | 234 +- search/CheckMinPeriods.hh | 64 +- search/CheckMinPulseWidths.cc | 364 +- search/CheckMinPulseWidths.hh | 73 +- search/CheckSlewLimits.cc | 422 -- search/CheckSlewLimits.hh | 129 - search/CheckSlews.cc | 420 ++ search/CheckSlews.hh | 168 + search/CheckTiming.cc | 178 +- search/CheckTiming.hh | 40 +- search/ClkInfo.cc | 85 +- search/ClkInfo.hh | 50 +- search/ClkLatency.cc | 36 +- search/ClkLatency.hh | 8 +- search/ClkNetwork.cc | 111 +- search/ClkSkew.cc | 640 +- search/ClkSkew.hh | 40 +- search/Corner.cc | 461 -- search/Crpr.cc | 133 +- search/Crpr.hh | 62 +- search/FindRegister.cc | 458 +- search/FindRegister.hh | 40 +- search/GatedClk.cc | 211 +- search/GatedClk.hh | 32 +- search/Genclks.cc | 661 +- search/Genclks.hh | 87 +- search/Latches.cc | 420 +- search/Latches.hh | 113 +- search/Levelize.cc | 332 +- search/Levelize.hh | 13 +- search/MakeTimingModel.cc | 52 +- search/MakeTimingModel.hh | 4 +- search/MakeTimingModelPvt.hh | 12 +- search/Mode.cc | 146 + search/Path.cc | 203 +- search/PathAnalysisPt.cc | 73 - search/PathEnd.cc | 586 +- search/PathEnum.cc | 294 +- search/PathEnum.hh | 42 +- search/PathExpanded.cc | 93 +- search/PathGroup.cc | 622 +- search/Property.cc | 505 +- search/Property.i | 24 +- search/ReportPath.cc | 1285 ++-- search/ReportPath.hh | 443 +- search/Scene.cc | 187 + search/Search.cc | 2825 ++++--- search/Search.i | 650 +- search/Search.tcl | 493 +- search/SearchPred.cc | 270 +- search/Sim.cc | 694 +- search/Sim.hh | 171 +- search/Sta.cc | 2974 ++++---- search/StaState.cc | 57 +- search/Tag.cc | 323 +- search/Tag.hh | 68 +- search/TagGroup.cc | 69 +- search/TagGroup.hh | 27 +- search/VisitPathEnds.cc | 641 +- search/WorstSlack.cc | 93 +- search/WorstSlack.hh | 38 +- spice/WritePathSpice.cc | 117 +- spice/WritePathSpice.hh | 20 +- spice/WriteSpice.cc | 63 +- spice/WriteSpice.hh | 82 +- spice/WriteSpice.i | 12 +- spice/WriteSpice.tcl | 30 +- spice/Xyce.hh | 4 +- tcl/CmdArgs.tcl | 313 +- tcl/CmdUtil.tcl | 34 +- tcl/Sta.tcl | 150 +- tcl/StaTclTypes.i | 240 +- tcl/TclTypeHelpers.cc | 71 +- tcl/Util.tcl | 84 +- tcl/Variables.tcl | 10 +- test/disconnect_mcp_pin.ok | 8 +- test/liberty_arcs_one2one_1.ok | 2 +- test/liberty_arcs_one2one_2.ok | 2 +- test/mcmm3.ok | 208 + test/power.ok | 12 +- test/power_json.tcl | 2 +- test/power_vcd.ok | 2 +- test/prima3.ok | 10 - test/regression.tcl | 105 +- test/regression_vars.tcl | 5 +- test/report_json1.ok | 10 +- test/suppress_msg.ok | 12 +- util/Debug.cc | 50 +- util/Error.cc | 4 +- util/Fuzzy.cc | 10 +- util/MachineLinux.cc | 14 +- util/MinMax.cc | 30 +- util/PatternMatch.cc | 26 +- util/Report.cc | 28 +- util/RiseFallMinMax.cc | 76 +- util/RiseFallMinMaxDelay.cc | 77 + util/RiseFallValues.cc | 6 +- util/StringSeq.cc | 5 +- util/StringSet.cc | 5 +- util/StringUtil.cc | 38 +- util/TokenParser.cc | 18 +- util/Transition.cc | 14 +- util/Util.i | 28 +- verilog/Verilog.i | 4 +- verilog/Verilog.tcl | 2 +- verilog/VerilogParse.yy | 5 +- verilog/VerilogReader.cc | 719 +- verilog/VerilogReader.hh | 296 - verilog/VerilogReaderPvt.hh | 68 +- verilog/VerilogWriter.cc | 81 +- 384 files changed, 33435 insertions(+), 32562 deletions(-) create mode 100644 examples/asap7_small_ff.lib.gz create mode 100644 examples/asap7_small_ss.lib.gz create mode 100644 examples/mcmm2_mode1.sdc create mode 100644 examples/mcmm2_mode2.sdc create mode 100644 examples/mcmm3.tcl create mode 100644 examples/reg1_asap7.spef create mode 100644 examples/reg1_asap7.v create mode 100644 examples/reg1_asap7_ss.spef create mode 100644 include/sta/BoundedHeap.hh create mode 100644 include/sta/ContainerHelpers.hh delete mode 100644 include/sta/Corner.hh delete mode 100644 include/sta/DcalcAnalysisPt.hh delete mode 100644 include/sta/Map.hh create mode 100644 include/sta/Mode.hh delete mode 100644 include/sta/PathAnalysisPt.hh rename include/sta/{MakeConcreteParasitics.hh => RiseFallMinMaxDelay.hh} (65%) create mode 100644 include/sta/Scene.hh delete mode 100644 include/sta/Set.hh delete mode 100644 include/sta/UnorderedMap.hh delete mode 100644 include/sta/UnorderedSet.hh delete mode 100644 include/sta/Vector.hh create mode 100644 include/sta/VectorMap.hh create mode 100644 power/ReportPower.cc create mode 100644 power/ReportPower.hh delete mode 100644 sdc/SdcGraph.cc delete mode 100644 search/CheckCapacitanceLimits.cc delete mode 100644 search/CheckCapacitanceLimits.hh create mode 100644 search/CheckCapacitances.cc create mode 100644 search/CheckCapacitances.hh delete mode 100644 search/CheckFanoutLimits.cc delete mode 100644 search/CheckFanoutLimits.hh create mode 100644 search/CheckFanouts.cc create mode 100644 search/CheckFanouts.hh delete mode 100644 search/CheckSlewLimits.cc delete mode 100644 search/CheckSlewLimits.hh create mode 100644 search/CheckSlews.cc create mode 100644 search/CheckSlews.hh create mode 100644 search/Mode.cc create mode 100644 search/Scene.cc create mode 100644 test/mcmm3.ok create mode 100644 util/RiseFallMinMaxDelay.cc delete mode 100644 verilog/VerilogReader.hh diff --git a/CMakeLists.txt b/CMakeLists.txt index f41fcac0..dda0ca9d 100644 --- a/CMakeLists.txt +++ b/CMakeLists.txt @@ -32,7 +32,7 @@ if(CMAKE_VERSION VERSION_GREATER_EQUAL 3.14) cmake_policy(SET CMP0086 NEW) endif() -project(STA VERSION 2.7.0 +project(STA VERSION 3.0.0 LANGUAGES CXX ) @@ -77,7 +77,6 @@ set(STA_SOURCE dcalc/ArnoldiDelayCalc.cc dcalc/ArnoldiReduce.cc dcalc/CcsCeffDelayCalc.cc - dcalc/DcalcAnalysisPt.cc dcalc/DelayCalc.cc dcalc/DelayCalcBase.cc dcalc/DmpCeff.cc @@ -135,6 +134,7 @@ set(STA_SOURCE parasitics/SpefReaderPvt.hh power/Power.cc + power/ReportPower.cc power/VcdReader.cc power/SaifReader.cc power/VcdParse.cc @@ -154,7 +154,6 @@ set(STA_SOURCE sdc/PortDelay.cc sdc/PortExtCap.cc sdc/Sdc.cc - sdc/SdcGraph.cc sdc/SdcCmdComment.cc sdc/Variables.cc sdc/WriteSdc.cc @@ -168,15 +167,14 @@ set(STA_SOURCE search/CheckMaxSkews.cc search/CheckMinPeriods.cc search/CheckMinPulseWidths.cc - search/CheckCapacitanceLimits.cc - search/CheckFanoutLimits.cc - search/CheckSlewLimits.cc + search/CheckCapacitances.cc + search/CheckFanouts.cc + search/CheckSlews.cc search/CheckTiming.cc search/ClkInfo.cc search/ClkLatency.cc search/ClkNetwork.cc search/ClkSkew.cc - search/Corner.cc search/Crpr.cc search/FindRegister.cc search/GatedClk.cc @@ -184,8 +182,8 @@ set(STA_SOURCE search/Latches.cc search/Levelize.cc search/MakeTimingModel.cc + search/Mode.cc search/Path.cc - search/PathAnalysisPt.cc search/Path.cc search/PathEnd.cc search/PathEnum.cc @@ -195,6 +193,7 @@ set(STA_SOURCE search/ReportPath.cc search/Search.cc search/SearchPred.cc + search/Scene.cc search/Sim.cc search/Sta.cc search/StaState.cc @@ -222,6 +221,7 @@ set(STA_SOURCE util/ReportStd.cc util/ReportTcl.cc util/RiseFallMinMax.cc + util/RiseFallMinMaxDelay.cc util/RiseFallValues.cc util/Stats.cc util/StringSeq.cc @@ -549,14 +549,14 @@ endif() target_compile_options(OpenSTA PRIVATE - $<$:${CXX_FLAGS}> + $<$:${CXX_FLAGS} -Wno-format-zero-length> $<$:${CXX_FLAGS} -Wno-gnu-zero-variadic-macro-arguments> $<$:${CXX_FLAGS} -Wno-gnu-zero-variadic-macro-arguments> ) # Disable compiler specific extensions like gnu++11. set_target_properties(OpenSTA PROPERTIES CXX_EXTENSIONS OFF) -target_compile_features(OpenSTA PUBLIC cxx_std_17) +target_compile_features(OpenSTA PUBLIC cxx_std_20) message(STATUS "STA library: ${CMAKE_BINARY_DIR}/libOpenSTA.a") diff --git a/app/Main.cc b/app/Main.cc index 4c7e56e9..baa1c0ea 100644 --- a/app/Main.cc +++ b/app/Main.cc @@ -27,6 +27,7 @@ #include #include // exit +#include #include #if TCL_READLINE #include @@ -47,7 +48,6 @@ using sta::evalTclInit; using sta::sourceTclFile; using sta::parseThreadsArg; using sta::tcl_inits; -using sta::is_regular_file; // Swig uses C linkage for init functions. extern "C" { @@ -60,18 +60,18 @@ static const char *init_filename = ".sta"; static void showUsage(const char *prog, - const char *init_filename); + const char *init_filename); static int tclAppInit(Tcl_Interp *interp); static int staTclAppInit(int argc, - char *argv[], - const char *init_filename, - Tcl_Interp *interp); + char *argv[], + const char *init_filename, + Tcl_Interp *interp); static void initStaApp(int &argc, - char *argv[], - Tcl_Interp *interp); + char *argv[], + Tcl_Interp *interp); int main(int argc, @@ -87,20 +87,11 @@ main(int argc, } else { // Set argc to 1 so Tcl_Main doesn't source any files. - // Tcl_Main never returns. -#if 0 - // It should be possible to pass argc/argv to staTclAppInit with - // a closure but I couldn't get the signature to match Tcl_AppInitProc. - Tcl_Main(1, argv, [=](Tcl_Interp *interp) - { sta::staTclAppInit(argc, argv, interp); - return 1; - }); -#else - // Workaround. + // Store argc and argv in static variables for tclAppInit. cmd_argc = argc; cmd_argv = argv; + // Tcl_Main never returns. Tcl_Main(1, argv, tclAppInit); -#endif return 0; } } @@ -114,9 +105,9 @@ tclAppInit(Tcl_Interp *interp) // Tcl init executed inside Tcl_Main. static int staTclAppInit(int argc, - char *argv[], - const char *init_filename, - Tcl_Interp *interp) + char *argv[], + const char *init_filename, + Tcl_Interp *interp) { // source init.tcl if (Tcl_Init(interp) == TCL_ERROR) @@ -141,7 +132,7 @@ staTclAppInit(int argc, string init_path = home; init_path += "/"; init_path += init_filename; - if (is_regular_file(init_path.c_str())) + if (std::filesystem::is_regular_file(init_path.c_str())) sourceTclFile(init_path.c_str(), true, true, interp); } } @@ -157,7 +148,7 @@ staTclAppInit(int argc, if (argc == 2) { char *cmd_file = argv[1]; if (cmd_file) { - int result = sourceTclFile(cmd_file, false, false, interp); + int result = sourceTclFile(cmd_file, false, false, interp); if (exit_after_cmd_file) { int exit_code = (result == TCL_OK) ? EXIT_SUCCESS : EXIT_FAILURE; exit(exit_code); @@ -174,8 +165,8 @@ staTclAppInit(int argc, static void initStaApp(int &argc, - char *argv[], - Tcl_Interp *interp) + char *argv[], + Tcl_Interp *interp) { initSta(); Sta *sta = new Sta; @@ -194,7 +185,7 @@ initStaApp(int &argc, static void showUsage(const char *prog, - const char *init_filename) + const char *init_filename) { printf("Usage: %s [-help] [-version] [-no_init] [-exit] cmd_file\n", prog); printf(" -help show help and exit\n"); diff --git a/app/StaMain.cc b/app/StaMain.cc index 97040fd7..5be334ea 100644 --- a/app/StaMain.cc +++ b/app/StaMain.cc @@ -30,14 +30,13 @@ #include "Machine.hh" #include "StringUtil.hh" -#include "Vector.hh" #include "Sta.hh" namespace sta { int parseThreadsArg(int &argc, - char *argv[]) + char *argv[]) { char *thread_arg = findCmdLineKey(argc, argv, "-threads"); if (thread_arg) { @@ -53,15 +52,15 @@ parseThreadsArg(int &argc, bool findCmdLineFlag(int &argc, - char *argv[], - const char *flag) + char *argv[], + const char *flag) { for (int i = 1; i < argc; i++) { char *arg = argv[i]; if (stringEq(arg, flag)) { // Remove flag from argv. for (int j = i + 1; j < argc; j++, i++) - argv[i] = argv[j]; + argv[i] = argv[j]; argc--; argv[argc] = nullptr; return true; @@ -72,8 +71,8 @@ findCmdLineFlag(int &argc, char * findCmdLineKey(int &argc, - char *argv[], - const char *key) + char *argv[], + const char *key) { for (int i = 1; i < argc; i++) { char *arg = argv[i]; @@ -81,7 +80,7 @@ findCmdLineKey(int &argc, char *value = argv[i + 1]; // Remove key and value from argv. for (int j = i + 2; j < argc; j++, i++) - argv[i] = argv[j]; + argv[i] = argv[j]; argc -= 2; argv[argc] = nullptr; return value; @@ -93,15 +92,15 @@ findCmdLineKey(int &argc, // Use overridden version of source to echo cmds and results. int sourceTclFile(const char *filename, - bool echo, - bool verbose, - Tcl_Interp *interp) + bool echo, + bool verbose, + Tcl_Interp *interp) { std::string cmd; stringPrint(cmd, "sta::include_file %s %s %s", - filename, - echo ? "1" : "0", - verbose ? "1" : "0"); + filename, + echo ? "1" : "0", + verbose ? "1" : "0"); int code = Tcl_Eval(interp, cmd.c_str()); const char *result = Tcl_GetStringResult(interp); if (result[0] != '\0') @@ -111,7 +110,7 @@ sourceTclFile(const char *filename, void evalTclInit(Tcl_Interp *interp, - const char *inits[]) + const char *inits[]) { char *unencoded = unencode(inits); if (Tcl_Eval(interp, unencoded) != TCL_OK) { @@ -148,12 +147,4 @@ unencode(const char *inits[]) return unencoded; } -// Hack until c++17 filesystem is better supported. -bool -is_regular_file(const char *filename) -{ - struct stat sb; - return stat(filename, &sb) == 0 && S_ISREG(sb.st_mode); -} - } // namespace diff --git a/dcalc/ArcDcalcWaveforms.cc b/dcalc/ArcDcalcWaveforms.cc index 4b8d340d..16595a28 100644 --- a/dcalc/ArcDcalcWaveforms.cc +++ b/dcalc/ArcDcalcWaveforms.cc @@ -31,7 +31,6 @@ #include "Network.hh" #include "Graph.hh" #include "ArcDelayCalc.hh" -#include "DcalcAnalysisPt.hh" #include "GraphDelayCalc.hh" namespace sta { @@ -40,7 +39,8 @@ using std::make_shared; Waveform ArcDcalcWaveforms::inputWaveform(ArcDcalcArg &dcalc_arg, - const DcalcAnalysisPt *dcalc_ap, + const Scene *scene, + const MinMax *min_max, const StaState *sta) { const Network *network = sta->network(); @@ -55,7 +55,8 @@ ArcDcalcWaveforms::inputWaveform(ArcDcalcArg &dcalc_arg, const Vertex *in_vertex = graph->pinLoadVertex(in_pin); GraphDelayCalc *graph_dcalc = sta->graphDelayCalc(); Slew in_slew = graph_dcalc->edgeFromSlew(in_vertex, in_rf, - dcalc_arg.arc()->role(), dcalc_ap); + dcalc_arg.arc()->role(), + scene, min_max); LibertyLibrary *library = port->libertyLibrary(); float vdd; bool vdd_exists; @@ -67,7 +68,8 @@ ArcDcalcWaveforms::inputWaveform(ArcDcalcArg &dcalc_arg, FloatSeq *time_values = new FloatSeq; for (float time : *in_waveform.axis1()->values()) time_values->push_back(time + dcalc_arg.inputDelay()); - TableAxisPtr time_axis = make_shared(TableAxisVariable::time, time_values); + TableAxisPtr time_axis = make_shared(TableAxisVariable::time, + time_values); // Scale the waveform from 0:vdd. FloatSeq *scaled_values = new FloatSeq; for (float value : *in_waveform.values()) { diff --git a/dcalc/ArcDcalcWaveforms.hh b/dcalc/ArcDcalcWaveforms.hh index 2cbcf3b5..6babfce6 100644 --- a/dcalc/ArcDcalcWaveforms.hh +++ b/dcalc/ArcDcalcWaveforms.hh @@ -31,8 +31,7 @@ namespace sta { class StaState; -class Corner; -class DcalcAnalysisPt; +class Scene; class ArcDcalcArg; // Abstract class for delay calculation waveforms for ploting. @@ -47,7 +46,8 @@ public: protected: Waveform inputWaveform(ArcDcalcArg &dcalc_arg, - const DcalcAnalysisPt *dcalc_ap, + const Scene *scene, + const MinMax *min_max, const StaState *sta); }; diff --git a/dcalc/ArcDelayCalc.cc b/dcalc/ArcDelayCalc.cc index d20ca928..2f6fcbfd 100644 --- a/dcalc/ArcDelayCalc.cc +++ b/dcalc/ArcDelayCalc.cc @@ -46,14 +46,15 @@ ArcDelayCalc::gateDelay(const TimingArc *arc, const Parasitic *parasitic, float, const Pvt *, - const DcalcAnalysisPt *dcalc_ap, + const Scene *scene, + const MinMax *min_max, // Return values. ArcDelay &gate_delay, Slew &drvr_slew) { LoadPinIndexMap load_pin_index_map(network_); ArcDcalcResult dcalc_result = gateDelay(nullptr, arc, in_slew, load_cap, parasitic, - load_pin_index_map, dcalc_ap); + load_pin_index_map, scene, min_max); gate_delay = dcalc_result.gateDelay(); drvr_slew = dcalc_result.drvrSlew(); } diff --git a/dcalc/Arnoldi.hh b/dcalc/Arnoldi.hh index 05a11b71..77512413 100644 --- a/dcalc/Arnoldi.hh +++ b/dcalc/Arnoldi.hh @@ -66,7 +66,7 @@ public: // n is the number of terms // The vectors U[j] are of size n class rcmodel : public ConcreteParasitic, - public arnoldi1 + public arnoldi1 { public: rcmodel(); diff --git a/dcalc/ArnoldiDelayCalc.cc b/dcalc/ArnoldiDelayCalc.cc index 62f973c9..ac6705d8 100644 --- a/dcalc/ArnoldiDelayCalc.cc +++ b/dcalc/ArnoldiDelayCalc.cc @@ -43,7 +43,6 @@ #include "Graph.hh" #include "Parasitics.hh" #include "Sdc.hh" -#include "DcalcAnalysisPt.hh" #include "DelayCalc.hh" #include "ArcDelayCalc.hh" #include "LumpedCapDelayCalc.hh" @@ -78,7 +77,7 @@ static void delay_work_destroy(delay_work *D); static double * delay_work_get_residues(delay_work *D, - int term_index); + int term_index); static bool tridiagEV(int n,double *d,double *e,double *p,double **v); @@ -129,17 +128,20 @@ public: const char *name() const override { return "arnoldi"; } Parasitic *findParasitic(const Pin *drvr_pin, const RiseFall *rf, - const DcalcAnalysisPt *dcalc_ap) override; + const Scene *scene, + const MinMax *min_max) override; Parasitic *reduceParasitic(const Parasitic *parasitic_network, const Pin *drvr_pin, const RiseFall *rf, - const DcalcAnalysisPt *dcalc_ap) override; + const Scene *scene, + const MinMax *min_max) override; ArcDcalcResult inputPortDelay(const Pin *port_pin, float in_slew, const RiseFall *rf, const Parasitic *parasitic, const LoadPinIndexMap &load_pin_index_map, - const DcalcAnalysisPt *dcalc_ap) override; + const Scene *scene, + const MinMax *min_max) override; ArcDcalcResult gateDelay(const Pin *drvr_pin, const TimingArc *arc, const Slew &in_slew, @@ -147,21 +149,23 @@ public: float load_cap, const Parasitic *parasitic, const LoadPinIndexMap &load_pin_index_map, - const DcalcAnalysisPt *dcalc_ap) override; + const Scene *scene, + const MinMax *min_max) override; string reportGateDelay(const Pin *drvr_pin, const TimingArc *arc, const Slew &in_slew, float load_cap, const Parasitic *parasitic, const LoadPinIndexMap &load_pin_index_map, - const DcalcAnalysisPt *dcalc_ap, + const Scene *scene, + const MinMax *min_max, int digits) override; void finishDrvrPin() override; void delay_work_set_thresholds(delay_work *D, - double lo, - double hi, - bool rising, - double derate); + double lo, + double hi, + bool rising, + double derate); private: ArcDcalcResult gateDelaySlew(const LibertyCell *drvr_cell, @@ -173,61 +177,61 @@ private: void ar1_ceff_delay(delay_work *D, timing_table *tab, arnoldi1 *mod, - double *delays, + double *delays, double *slews); double ra_rdelay_1(timing_table *tab, - double ctot); + double ctot); double ra_get_r(delay_work *D, - timing_table *tab, - double rdelay, - double ctot); + timing_table *tab, + double rdelay, + double ctot); double ra_get_s(delay_work *D, - timing_table *tab, - double r, - double c); + timing_table *tab, + double r, + double c); void ra_solve_for_s(delay_work *D, - double p, - double tlohi, - double &s); + double p, + double tlohi, + double &s); // from poles and residues, solve for t20,t50,t80 void pr_solve1(double s, - int order, - double *p, - double *rr, - double v1, - double *t1); + int order, + double *p, + double *rr, + double v1, + double *t1); void pr_solve3(double s, - int order, - double *p, - double *rr, - double vhi, - double *thi, - double vmid, - double *tmid, - double vlo, - double *tlo); + int order, + double *p, + double *rr, + double vhi, + double *thi, + double vmid, + double *tmid, + double vlo, + double *tlo); // // routines for linear drive model and ceff // double pr_ceff(double s, - double rdrive, - int order, - double *p, - double *rr, - double ceff_time); + double rdrive, + int order, + double *p, + double *rr, + double ceff_time); double ra_solve_for_t(double p, - double s, - double v); + double s, + double v); void ra_solve_for_pt(double ps, - double v, - double *pt, - double *d); + double v, + double *pt, + double *d); void ra_calc_c(double lo, - double hi, - double *c_smin, - double *c_x1, - double *c_y1); + double hi, + double *c_smin, + double *c_x1, + double *c_y1); rcmodel *rcmodel_; int _pinNmax; @@ -272,36 +276,35 @@ ArnoldiDelayCalc::~ArnoldiDelayCalc() Parasitic * ArnoldiDelayCalc::findParasitic(const Pin *drvr_pin, - const RiseFall *drvr_rf, - const DcalcAnalysisPt *dcalc_ap) + const RiseFall *drvr_rf, + const Scene *scene, + const MinMax *min_max) { Parasitic *parasitic = nullptr; - const Corner *corner = dcalc_ap->corner(); - // set_load net has precedence over parasitics. - if (sdc_->drvrPinHasWireCap(drvr_pin, corner) + const Sdc *sdc = scene->sdc(); + Parasitics *parasitics = scene->parasitics(min_max); + if (parasitics == nullptr + // set_load net has precedence over parasitics. || network_->direction(drvr_pin)->isInternal()) return nullptr; - const ParasiticAnalysisPt *parasitic_ap = dcalc_ap->parasiticAnalysisPt(); Parasitic *parasitic_network = - parasitics_->findParasiticNetwork(drvr_pin, parasitic_ap); - const MinMax *min_max = dcalc_ap->constraintMinMax(); + parasitics->findParasiticNetwork(drvr_pin); if (parasitic_network == nullptr) { - Wireload *wireload = sdc_->wireload(min_max); + Wireload *wireload = sdc->wireload(min_max); if (wireload) { float pin_cap, wire_cap, fanout; bool has_wire_cap; - graph_delay_calc_->netCaps(drvr_pin, drvr_rf, dcalc_ap, + graph_delay_calc_->netCaps(drvr_pin, drvr_rf, scene, min_max, pin_cap, wire_cap, fanout, has_wire_cap); - parasitic_network = parasitics_->makeWireloadNetwork(drvr_pin, wireload, - fanout, min_max, - parasitic_ap); + parasitic_network = parasitics->makeWireloadNetwork(drvr_pin, wireload, + fanout, scene, min_max); } } if (parasitic_network) { rcmodel *rcmodel = reduce_->reduceToArnoldi(parasitic_network, drvr_pin, - parasitic_ap->couplingCapFactor(), - drvr_rf, corner, min_max, parasitic_ap); + parasitics->couplingCapFactor(), + drvr_rf, scene, min_max); // Arnoldi parasitics are their own class that are not saved in the parasitic db. unsaved_parasitics_.push_back(rcmodel); parasitic = rcmodel; @@ -313,7 +316,8 @@ Parasitic * ArnoldiDelayCalc::reduceParasitic(const Parasitic *, const Pin *, const RiseFall *, - const DcalcAnalysisPt *) + const Scene *, + const MinMax *) { // Decline because reduced arnoldi parasitics are not stored in the parasitics db. return nullptr; @@ -333,7 +337,8 @@ ArnoldiDelayCalc::inputPortDelay(const Pin *, const RiseFall *rf, const Parasitic *parasitic, const LoadPinIndexMap &load_pin_index_map, - const DcalcAnalysisPt *) + const Scene *, + const MinMax *) { rcmodel_ = nullptr; _delayV[0] = 0.0; @@ -389,28 +394,29 @@ ArnoldiDelayCalc::gateDelay(const Pin *drvr_pin, float load_cap, const Parasitic *parasitic, const LoadPinIndexMap &load_pin_index_map, - const DcalcAnalysisPt *dcalc_ap) + const Scene *scene, + const MinMax *min_max) { const LibertyCell *drvr_cell = arc->from()->libertyCell(); ConcreteParasitic *cparasitic = reinterpret_cast(const_cast(parasitic)); rcmodel_ = dynamic_cast(cparasitic); pocv_enabled_ = variables_->pocvEnabled(); - GateTableModel *table_model = arc->gateTableModel(dcalc_ap); + GateTableModel *table_model = arc->gateTableModel(scene, min_max); if (table_model && rcmodel_) { - const Pvt *pvt = pinPvt(drvr_pin, dcalc_ap); + const Pvt *pvt = pinPvt(drvr_pin, scene, min_max); return gateDelaySlew(drvr_cell, arc, table_model, in_slew, load_pin_index_map, pvt); } else return LumpedCapDelayCalc::gateDelay(drvr_pin, arc, in_slew, load_cap, - parasitic, load_pin_index_map, dcalc_ap); + parasitic, load_pin_index_map, scene, min_max); } ArcDcalcResult ArnoldiDelayCalc::gateDelaySlew(const LibertyCell *drvr_cell, const TimingArc *arc, - const GateTableModel *table_model, - const Slew &in_slew, + const GateTableModel *table_model, + const Slew &in_slew, const LoadPinIndexMap &load_pin_index_map, const Pvt *pvt) { @@ -432,7 +438,7 @@ ArnoldiDelayCalc::gateDelaySlew(const LibertyCell *drvr_cell, double hi_thresh = drvr_library->slewUpperThreshold(rf); bool rising = (rf == RiseFall::rise()); delay_work_set_thresholds(delay_work_, lo_thresh, hi_thresh, rising, - slew_derate); + slew_derate); if (rcmodel_->order > 0) { timing_table tab; tab.table = table_model; @@ -440,7 +446,7 @@ ArnoldiDelayCalc::gateDelaySlew(const LibertyCell *drvr_cell, tab.pvt = pvt; tab.in_slew = delayAsFloat(in_slew); ar1_ceff_delay(delay_work_, &tab, rcmodel_, - _delayV, _slewV); + _delayV, _slewV); } dcalc_result.setGateDelay(_delayV[0]); dcalc_result.setDrvrSlew(_slewV[0]); @@ -470,12 +476,13 @@ ArnoldiDelayCalc::reportGateDelay(const Pin *drvr_pin, float load_cap, const Parasitic *parasitic, const LoadPinIndexMap &load_pin_index_map, - const DcalcAnalysisPt *dcalc_ap, + const Scene *scene, + const MinMax *min_max, int digits) { return LumpedCapDelayCalc::reportGateDelay(drvr_pin, arc, in_slew, load_cap, parasitic, load_pin_index_map, - dcalc_ap, digits); + scene, min_max, digits); } //////////////////////////////////////////////////////////////// @@ -560,10 +567,10 @@ delay_work_alloc(delay_work *D,int n) void ArnoldiDelayCalc::delay_work_set_thresholds(delay_work *D, - double lo, - double hi, - bool rising, - double derate) + double lo, + double hi, + bool rising, + double derate) { double mid = 0.5; // 0.0:1.0 int i = rising?1:0; @@ -582,7 +589,7 @@ ArnoldiDelayCalc::delay_work_set_thresholds(delay_work *D, D->c->vmid = mid; D->c->vlg = log(hi/lo); ra_calc_c(lo,hi, - &(D->c->smin), &(D->c->x1),&(D->c->y1)); + &(D->c->smin), &(D->c->x1),&(D->c->y1)); } D->lo_thresh = D->c->vlo; D->hi_thresh = D->c->vhi; @@ -790,7 +797,7 @@ get_dv(double t, double s, int order, double *p, double *rr, static double solve_t_bracketed(double s,int order,double *p,double *rr, - double val,double x1,double x2,double v1,double v2) + double val,double x1,double x2,double v1,double v2) { int j; double df,dx,dxold,f,f2,f1; @@ -859,17 +866,17 @@ solve_t_bracketed(double s,int order,double *p,double *rr, void ArnoldiDelayCalc::pr_solve1(double s, - int order, - double *p, - double *rr, - double v1, - double *t1) + int order, + double *p, + double *rr, + double v1, + double *t1) { double tmin = 0.0,tmax = 0.0,vmin = 0.0,vmax = 0.0; int h, h0 = 0; while (order>1 - && rr[order-1]<1e-8 // 1e-8V - && rr[order-1]>-1e-8) + && rr[order-1]<1e-8 // 1e-8V + && rr[order-1]>-1e-8) order--; if (rr[0]<0.5) { for (h=1;h0.3 && rr[h]>rr[0]) { h0 = h; break; } @@ -893,7 +900,7 @@ ArnoldiDelayCalc::pr_solve1(double s, // ignoring a typical error at drive node, that comes // from slight inaccuracies in rr if (!(rr[order-1]>1.0 && p[order-1]>500.0 && va>v1-0.002)) - debugPrint(debug_, "arnoldi", 1, "err, pr_solve1, vav1) - debugPrint(debug_, "arnoldi", 1, "err, pr_solve1, va>v1"); + debugPrint(debug_, "arnoldi", 1, "err, pr_solve1, va>v1"); tmax = ta; vmax = va; } } else { @@ -925,15 +932,15 @@ ArnoldiDelayCalc::pr_solve1(double s, void ArnoldiDelayCalc::pr_solve3(double s, - int order, - double *p, - double *rr, - double vhi, - double *thi, - double vmid, - double *tmid, - double vlo, - double *tlo) + int order, + double *p, + double *rr, + double vhi, + double *thi, + double vmid, + double *tmid, + double vlo, + double *tlo) { // falling, thi1 - && rr[order-1]<1e-8 // 1e-8V - && rr[order-1]>-1e-8) + && rr[order-1]<1e-8 // 1e-8V + && rr[order-1]>-1e-8) order--; if (rr[0]<0.5) { for (h=1;h0.3 && rr[h]>rr[0]) { h0 = h; break; } @@ -1111,11 +1118,11 @@ calc_integ(double p,double s,double t) double ArnoldiDelayCalc::pr_ceff(double s, - double rdrive, - int order, - double *p, - double *rr, - double ceff_time) + double rdrive, + int order, + double *p, + double *rr, + double ceff_time) { double integi = 0.0; double ceff, v0; @@ -1133,7 +1140,7 @@ ArnoldiDelayCalc::pr_ceff(double s, static double ra_hinv(double y, - Debug *debug) + Debug *debug) { double x; if (y<1.0) { @@ -1160,8 +1167,8 @@ ra_hinv(double y, double ArnoldiDelayCalc::ra_solve_for_t(double p, - double s, - double v) + double s, + double v) { double t; double ps = p*s; @@ -1180,9 +1187,9 @@ ArnoldiDelayCalc::ra_solve_for_t(double p, void ArnoldiDelayCalc::ra_solve_for_pt(double ps, - double v, - double *pt, - double *d) + double v, + double *pt, + double *d) { if (ps>30.0) { *pt = 1.0+ps*(1.0-v); @@ -1201,10 +1208,10 @@ ArnoldiDelayCalc::ra_solve_for_pt(double ps, void ArnoldiDelayCalc::ra_calc_c(double vlo, - double vhi, - double *c_smin, - double *c_x1, - double *c_y1) + double vhi, + double *c_smin, + double *c_x1, + double *c_y1) { double a = log(1.0/vhi); *c_smin = a + ra_hinv((1.0-vhi)/vhi - a, debug_); @@ -1224,9 +1231,9 @@ ArnoldiDelayCalc::ra_calc_c(double vlo, void ArnoldiDelayCalc::ra_solve_for_s(delay_work *D, - double p, - double tlohi, - double &s) + double p, + double tlohi, + double &s) { delay_c *c = D->c; double vhi = c->vhi; @@ -1258,28 +1265,28 @@ ArnoldiDelayCalc::ra_solve_for_s(delay_work *D, f = (ptlo-pthi)/p - tlohi; df = dlo-dhi; s = s - f/df; - if (abs(f)<.001e-12) return; // .001ps + if (abs(f)<.001e-12) return; // .001ps ra_solve_for_pt(p*s,vlo,&ptlo,&dlo); ra_solve_for_pt(p*s,vhi,&pthi,&dhi); f = (ptlo-pthi)/p - tlohi; df = dlo-dhi; s = s - f/df; - if (abs(f)<.001e-12) return; // .001ps + if (abs(f)<.001e-12) return; // .001ps ra_solve_for_pt(p*s,vlo,&ptlo,&dlo); ra_solve_for_pt(p*s,vhi,&pthi,&dhi); f = (ptlo-pthi)/p - tlohi; df = dlo-dhi; s = s - f/df; - if (abs(f)<.001e-12) return; // .001ps + if (abs(f)<.001e-12) return; // .001ps ra_solve_for_pt(p*s,vlo,&ptlo,&dlo); ra_solve_for_pt(p*s,vhi,&pthi,&dhi); f = (ptlo-pthi)/p - tlohi; df = dlo-dhi; s = s - f/df; - if (abs(f)<.001e-12) return; // .001ps + if (abs(f)<.001e-12) return; // .001ps ra_solve_for_pt(p*s,vlo,&ptlo,&dlo); ra_solve_for_pt(p*s,vhi,&pthi,&dhi); @@ -1308,9 +1315,9 @@ ArnoldiDelayCalc::ra_solve_for_s(delay_work *D, // Rough translation of ra_get_r(sy_table) used by ar1_ceff_delay. double ArnoldiDelayCalc::ra_get_r(delay_work *D, - timing_table *tab, - double rdelay, - double ctot) + timing_table *tab, + double rdelay, + double ctot) { // find the maximum r that allows a solution for s of // (s,r,ctot)-> output_slew @@ -1333,9 +1340,9 @@ ArnoldiDelayCalc::ra_get_r(delay_work *D, double ArnoldiDelayCalc::ra_get_s(delay_work *D, - timing_table *tab, - double r, - double c) + timing_table *tab, + double r, + double c) { delay_c *con = D->c; double slew_derate = con->slew_derate; @@ -1367,7 +1374,7 @@ ArnoldiDelayCalc::ra_get_s(delay_work *D, double ArnoldiDelayCalc::ra_rdelay_1(timing_table *tab, - double ctot) + double ctot) { // determine the drive resistance from change in delay versus ctot float c1 = ctot; @@ -1387,10 +1394,10 @@ ArnoldiDelayCalc::ra_rdelay_1(timing_table *tab, void ArnoldiDelayCalc::ar1_ceff_delay(delay_work *D, - timing_table *tab, - arnoldi1 *mod, - double *delays, - double *slews) + timing_table *tab, + arnoldi1 *mod, + double *delays, + double *slews) { delay_c *con = D->c; double slew_derate = con->slew_derate; @@ -1411,13 +1418,13 @@ ArnoldiDelayCalc::ar1_ceff_delay(delay_work *D, r = rdelay; r = ra_get_r(D,tab,rdelay,ctot); if (! (r>0.0 - && r<100e+3)) // 100khom + && r<100e+3)) // 100khom rdelay = 1e+3; // 1kohm bool bad = (r0.0 - && s<100e-9)) // 100ns + && s<100e-9)) // 100ns s = 0.5e-9; // .5ns if (debug_->check("arnoldi", 1)) { @@ -1464,9 +1471,9 @@ ArnoldiDelayCalc::ar1_ceff_delay(delay_work *D, ceff = pr_ceff(s,r,mod->order,p,rr,ceff_time); if ((ceff-1e-20) < 0.0) { // 1e-8pf - debugPrint(debug_, "arnoldi", 1, + debugPrint(debug_, "arnoldi", 1, "Invalid effective capacitance, using total capacitance"); - ceff = ctot; + ceff = ctot; } // new mvs at ceff diff --git a/dcalc/ArnoldiReduce.cc b/dcalc/ArnoldiReduce.cc index 43d57f46..f05f8abc 100644 --- a/dcalc/ArnoldiReduce.cc +++ b/dcalc/ArnoldiReduce.cc @@ -151,20 +151,20 @@ ArnoldiReduce::~ArnoldiReduce() rcmodel * ArnoldiReduce::reduceToArnoldi(Parasitic *parasitic, - const Pin *drvr_pin, - float coupling_cap_factor, - const RiseFall *rf, - const Corner *corner, - const MinMax *min_max, - const ParasiticAnalysisPt *ap) + const Pin *drvr_pin, + float coupling_cap_factor, + const RiseFall *rf, + const Scene *scene, + const MinMax *min_max) { - parasitic_network_ = reinterpret_cast(parasitic); drvr_pin_ = drvr_pin; coupling_cap_factor_ = coupling_cap_factor; rf_ = rf; - corner_ = corner; + scene_ = scene; min_max_ = min_max; - ap_ = ap; + parasitics_ = scene->parasitics(min_max); + parasitic_network_ = reinterpret_cast(parasitic); + loadWork(); return makeRcmodelDrv(); } @@ -426,17 +426,17 @@ ArnoldiReduce::getRC() if (p->node_) { ParasiticNode *node = p->node_; double cap = parasitics_->nodeGndCap(node) - + pinCapacitance(node); + + pinCapacitance(node); if (cap > 0.0) { - p->c = cap; - ctot_ += cap; + p->c = cap; + ctot_ += cap; } else - p->c = 0.0; + p->c = 0.0; if (p->in_edge && p->in_edge->resistor_) p->r = parasitics_->value(p->in_edge->resistor_); if (!(p->r>=0.0 && p->r<100e+3)) { // 0 < r < 100kohm - debugPrint(debug_, "arnoldi", 1, + debugPrint(debug_, "arnoldi", 1, "R value %g out of range, drvr pin %s", p->r, network_->pathName(drvr_pin_)); @@ -444,7 +444,7 @@ ArnoldiReduce::getRC() } } for (ParasiticCapacitor *capacitor : parasitics_->capacitors(parasitic_network_)) { - float cap = parasitics_->value(capacitor) * ap_->couplingCapFactor(); + float cap = parasitics_->value(capacitor) * parasitics_->couplingCapFactor(); ParasiticNode *node1 = parasitics_->node1(capacitor); if (!parasitics_->isExternal(node1)) { ts_point *pt = findPt(node1); @@ -466,10 +466,11 @@ ArnoldiReduce::pinCapacitance(ParasiticNode *node) if (pin) { Port *port = network_->port(pin); LibertyPort *lib_port = network_->libertyPort(port); + const Sdc *sdc = scene_->sdc(); if (lib_port) - pin_cap = sdc_->pinCapacitance(pin,rf_, corner_, min_max_); + pin_cap = sdc->pinCapacitance(pin,rf_, scene_, min_max_); else if (network_->isTopLevelPort(pin)) - pin_cap = sdc_->portExtCap(port, rf_, corner_, min_max_); + pin_cap = sdc->portExtCap(port, rf_, min_max_); } return pin_cap; } @@ -510,7 +511,7 @@ ArnoldiReduce::makeRcmodelFromTs() if (p->is_term) debugPrint(debug_, "arnoldi", 1, " term %d", p->tindex); if (p->in_edge) - debugPrint(debug_, "arnoldi", 1, " from T%d,P%ld r=%s", + debugPrint(debug_, "arnoldi", 1, " from T%d,P%ld r=%s", p->in_edge->from->ts, p->in_edge->from-p0, units_->resistanceUnit()->asString(p->r)); @@ -610,19 +611,19 @@ ArnoldiReduce::makeRcmodelFromTs() report_->reportLine("order %d n %d",order,n); for (h=0;hreportLine(" d[%d] %s e[%d] %s", + report_->reportLine(" d[%d] %s e[%d] %s", h, units_->timeUnit()->asString(d[h]), h, units_->timeUnit()->asString(e[h])); else - report_->reportLine(" d[%d] %s", + report_->reportLine(" d[%d] %s", h, units_->timeUnit()->asString(d[h])); string line = stdstrPrint("U[%d]",h); for (i=0;ireportLineString(line); } } diff --git a/dcalc/ArnoldiReduce.hh b/dcalc/ArnoldiReduce.hh index 14e5d68a..96297bb7 100644 --- a/dcalc/ArnoldiReduce.hh +++ b/dcalc/ArnoldiReduce.hh @@ -28,7 +28,8 @@ #pragma once -#include "Map.hh" +#include + #include "Transition.hh" #include "NetworkClass.hh" #include "ParasiticsClass.hh" @@ -39,13 +40,13 @@ namespace sta { class ConcreteParasiticNetwork; class ConcreteParasiticNode; -class Corner; +class Scene; class rcmodel; struct ts_edge; struct ts_point; -typedef Map ArnolidPtMap; +using ArnolidPtMap = std::map; class ArnoldiReduce : public StaState { @@ -56,9 +57,8 @@ public: const Pin *drvr_pin, float coupling_cap_factor, const RiseFall *rf, - const Corner *corner, - const MinMax *cnst_min_max, - const ParasiticAnalysisPt *ap); + const Scene *scene, + const MinMax *min_max); protected: void loadWork(); @@ -73,13 +73,13 @@ protected: void makeRcmodelFromTs(); rcmodel *makeRcmodelFromW(); + Parasitics *parasitics_; ConcreteParasiticNetwork *parasitic_network_; const Pin *drvr_pin_; float coupling_cap_factor_; const RiseFall *rf_; - const Corner *corner_; + const Scene *scene_; const MinMax *min_max_; - const ParasiticAnalysisPt *ap_; // ParasiticNode -> ts_point index. ArnolidPtMap pt_map_; diff --git a/dcalc/CcsCeffDelayCalc.cc b/dcalc/CcsCeffDelayCalc.cc index f5462661..e068a73d 100644 --- a/dcalc/CcsCeffDelayCalc.cc +++ b/dcalc/CcsCeffDelayCalc.cc @@ -30,8 +30,7 @@ #include "TimingArc.hh" #include "Network.hh" #include "Graph.hh" -#include "Corner.hh" -#include "DcalcAnalysisPt.hh" +#include "Scene.hh" #include "Parasitics.hh" #include "GraphDelayCalc.hh" #include "DmpDelayCalc.hh" @@ -86,17 +85,20 @@ CcsCeffDelayCalc::gateDelay(const Pin *drvr_pin, float load_cap, const Parasitic *parasitic, const LoadPinIndexMap &load_pin_index_map, - const DcalcAnalysisPt *dcalc_ap) + const Scene *scene, + const MinMax *min_max) { in_slew_ = delayAsFloat(in_slew); load_cap_ = load_cap; + parasitics_ = scene->parasitics(min_max); parasitic_ = parasitic; output_waveforms_ = nullptr; - GateTableModel *table_model = arc->gateTableModel(dcalc_ap); + GateTableModel *table_model = arc->gateTableModel(scene, min_max); if (table_model && parasitic) { OutputWaveforms *output_waveforms = table_model->outputWaveforms(); - parasitics_->piModel(parasitic, c2_, rpi_, c1_); + Parasitics *parasitics = scene->parasitics(min_max); + parasitics->piModel(parasitic, c2_, rpi_, c1_); if (output_waveforms && rpi_ > 0.0 && c1_ > 0.0 // Bounds check because extrapolating waveforms does not work for shit. @@ -114,8 +116,7 @@ CcsCeffDelayCalc::gateDelay(const Pin *drvr_pin, vl_ = drvr_library->slewLowerThreshold(drvr_rf_) * vdd_; vh_ = drvr_library->slewUpperThreshold(drvr_rf_) * vdd_; - const DcalcAnalysisPtSeq &dcalc_aps = corners_->dcalcAnalysisPts(); - drvr_cell->ensureVoltageWaveforms(dcalc_aps); + drvr_cell->ensureVoltageWaveforms(scenes_); in_slew_ = delayAsFloat(in_slew); output_waveforms_ = output_waveforms; ref_time_ = output_waveforms_->referenceTime(in_slew_); @@ -129,7 +130,7 @@ CcsCeffDelayCalc::gateDelay(const Pin *drvr_pin, } } return table_dcalc_->gateDelay(drvr_pin, arc, in_slew, load_cap, parasitic, - load_pin_index_map, dcalc_ap); + load_pin_index_map, scene, min_max); } void @@ -574,7 +575,7 @@ CcsCeffDelayCalc::drvrRampWaveform(const Pin *in_pin, const Pin *drvr_pin, const RiseFall *drvr_rf, const Pin *load_pin, - const Corner *corner, + const Scene *scene, const MinMax *min_max) { bool elmore_exists = false; @@ -582,7 +583,7 @@ CcsCeffDelayCalc::drvrRampWaveform(const Pin *in_pin, if (parasitic_) { parasitics_->findElmore(parasitic_, load_pin, elmore, elmore_exists); bool dcalc_success = makeWaveformPreamble(in_pin, in_rf, drvr_pin, - drvr_rf, corner, min_max); + drvr_rf, scene, min_max); if (dcalc_success && elmore_exists) { FloatSeq *load_times = new FloatSeq; @@ -617,7 +618,7 @@ CcsCeffDelayCalc::makeWaveformPreamble(const Pin *in_pin, const RiseFall *in_rf, const Pin *drvr_pin, const RiseFall *drvr_rf, - const Corner *corner, + const Scene *scene, const MinMax *min_max) { Vertex *in_vertex = graph_->pinLoadVertex(in_pin); @@ -641,15 +642,15 @@ CcsCeffDelayCalc::makeWaveformPreamble(const Pin *in_pin, } } if (arc) { - DcalcAnalysisPt *dcalc_ap = corner->findDcalcAnalysisPt(min_max); - const Slew &in_slew = graph_->slew(in_vertex, in_rf, dcalc_ap->index()); - parasitic_ = arc_delay_calc_->findParasitic(drvr_pin, drvr_rf, dcalc_ap); + DcalcAPIndex slew_index = scene->dcalcAnalysisPtIndex(min_max); + const Slew &in_slew = graph_->slew(in_vertex, in_rf, slew_index); + parasitic_ = arc_delay_calc_->findParasitic(drvr_pin, drvr_rf, scene, min_max); if (parasitic_) { parasitics_->piModel(parasitic_, c2_, rpi_, c1_); LoadPinIndexMap load_pin_index_map = graph_delay_calc_->makeLoadPinIndexMap(drvr_vertex); gateDelay(drvr_pin, arc, in_slew, load_cap_, parasitic_, - load_pin_index_map, dcalc_ap); + load_pin_index_map, scene, min_max); return true; } } @@ -666,20 +667,19 @@ CcsCeffDelayCalc::reportGateDelay(const Pin *drvr_pin, float load_cap, const Parasitic *parasitic, const LoadPinIndexMap &load_pin_index_map, - const DcalcAnalysisPt *dcalc_ap, + const Scene *scene, + const MinMax *min_max, int digits) { Parasitic *pi_elmore = nullptr; const RiseFall *rf = arc->toEdge()->asRiseFall(); if (parasitic && !parasitics_->isPiElmore(parasitic)) { - const ParasiticAnalysisPt *ap = dcalc_ap->parasiticAnalysisPt(); pi_elmore = parasitics_->reduceToPiElmore(parasitic, drvr_pin_, rf, - dcalc_ap->corner(), - dcalc_ap->constraintMinMax(), ap); + scene, min_max); } string report = table_dcalc_->reportGateDelay(drvr_pin, arc, in_slew, load_cap, pi_elmore, load_pin_index_map, - dcalc_ap, digits); + scene, min_max, digits); parasitics_->deleteDrvrReducedParasitics(drvr_pin); return report; } diff --git a/dcalc/CcsCeffDelayCalc.hh b/dcalc/CcsCeffDelayCalc.hh index 389a7776..27c5159a 100644 --- a/dcalc/CcsCeffDelayCalc.hh +++ b/dcalc/CcsCeffDelayCalc.hh @@ -29,7 +29,7 @@ namespace sta { -typedef std::map WatchPinValuesMap; +using WatchPinValuesMap = std::map; ArcDelayCalc * makeCcsCeffDelayCalc(StaState *sta); @@ -49,14 +49,16 @@ public: float load_cap, const Parasitic *parasitic, const LoadPinIndexMap &load_pin_index_map, - const DcalcAnalysisPt *dcalc_ap) override; + const Scene *scene, + const MinMax *min_max) override; std::string reportGateDelay(const Pin *drvr_pin, const TimingArc *arc, const Slew &in_slew, float load_cap, const Parasitic *parasitic, const LoadPinIndexMap &load_pin_index_map, - const DcalcAnalysisPt *dcalc_ap, + const Scene *scene, + const MinMax *min_max, int digits) override; // Record waveform for drvr/load pin. @@ -100,7 +102,7 @@ protected: const RiseFall *in_rf, const Pin *drvr_pin, const RiseFall *drvr_rf, - const Corner *corner, + const Scene *scene, const MinMax *min_max); Waveform drvrWaveform(); Waveform loadWaveform(const Pin *load_pin); @@ -109,7 +111,7 @@ protected: const Pin *drvr_pin, const RiseFall *drvr_rf, const Pin *load_pin, - const Corner *corner, + const Scene *scene, const MinMax *min_max); void vl(double t, double elmore, @@ -124,6 +126,7 @@ protected: const RiseFall *drvr_rf_; double in_slew_; double load_cap_; + Parasitics *parasitics_; const Parasitic *parasitic_; OutputWaveforms *output_waveforms_; diff --git a/dcalc/DcalcAnalysisPt.cc b/dcalc/DcalcAnalysisPt.cc index 1c5b89ed..e69de29b 100644 --- a/dcalc/DcalcAnalysisPt.cc +++ b/dcalc/DcalcAnalysisPt.cc @@ -1,68 +0,0 @@ -// OpenSTA, Static Timing Analyzer -// Copyright (c) 2025, Parallax Software, Inc. -// -// This program is free software: you can redistribute it and/or modify -// it under the terms of the GNU General Public License as published by -// the Free Software Foundation, either version 3 of the License, or -// (at your option) any later version. -// -// This program is distributed in the hope that it will be useful, -// but WITHOUT ANY WARRANTY; without even the implied warranty of -// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -// GNU General Public License for more details. -// -// You should have received a copy of the GNU General Public License -// along with this program. If not, see . -// -// The origin of this software must not be misrepresented; you must not -// claim that you wrote the original software. -// -// Altered source versions must be plainly marked as such, and must not be -// misrepresented as being the original software. -// -// This notice may not be removed or altered from any source distribution. - -#include "StringUtil.hh" -#include "DcalcAnalysisPt.hh" -#include "Corner.hh" - -namespace sta { - -DcalcAnalysisPt::DcalcAnalysisPt(Corner *corner, - DcalcAPIndex index, - const OperatingConditions *op_cond, - const MinMax *min_max, - const MinMax *check_clk_slew_min_max) : - corner_(corner), - index_(index), - op_cond_(op_cond), - min_max_(min_max), - check_clk_slew_min_max_(check_clk_slew_min_max) -{ -} - -void -DcalcAnalysisPt::setOperatingConditions(const OperatingConditions *op_cond) -{ - op_cond_ = op_cond; -} - -ParasiticAnalysisPt * -DcalcAnalysisPt::parasiticAnalysisPt() const -{ - return corner_->findParasiticAnalysisPt(min_max_); -} - -void -DcalcAnalysisPt::setCheckClkSlewIndex(DcalcAPIndex index) -{ - check_clk_slew_index_ = index; -} - -int -DcalcAnalysisPt::libertyIndex() const -{ - return corner_->libertyIndex(min_max_); -} - -} // namespace diff --git a/dcalc/DelayCalc.cc b/dcalc/DelayCalc.cc index 77fc7ed1..bde9248c 100644 --- a/dcalc/DelayCalc.cc +++ b/dcalc/DelayCalc.cc @@ -24,7 +24,9 @@ #include "DelayCalc.hh" -#include "Map.hh" +#include + +#include "ContainerHelpers.hh" #include "StringUtil.hh" #include "UnitDelayCalc.hh" #include "LumpedCapDelayCalc.hh" @@ -35,7 +37,7 @@ namespace sta { -typedef Map DelayCalcMap; +typedef std::map DelayCalcMap; static DelayCalcMap *delay_calcs = nullptr; @@ -53,7 +55,7 @@ registerDelayCalcs() void registerDelayCalc(const char *name, - MakeArcDelayCalc maker) + MakeArcDelayCalc maker) { if (delay_calcs == nullptr) delay_calcs = new DelayCalcMap; @@ -69,9 +71,9 @@ deleteDelayCalcs() ArcDelayCalc * makeDelayCalc(const char *name, - StaState *sta) + StaState *sta) { - MakeArcDelayCalc maker = delay_calcs->findKey(name); + MakeArcDelayCalc maker = findKey(delay_calcs, name); if (maker) return maker(sta); else @@ -81,7 +83,7 @@ makeDelayCalc(const char *name, bool isDelayCalcName(const char *name) { - return delay_calcs->hasKey(name); + return delay_calcs->contains(name); } StringSeq diff --git a/dcalc/DelayCalc.i b/dcalc/DelayCalc.i index e3494286..a0bbaea6 100644 --- a/dcalc/DelayCalc.i +++ b/dcalc/DelayCalc.i @@ -32,8 +32,6 @@ #include "dcalc/PrimaDelayCalc.hh" #include "Sta.hh" -using std::string; - %} %inline %{ @@ -62,15 +60,15 @@ set_delay_calc_incremental_tolerance(float tol) Sta::sta()->setIncrementalDelayTolerance(tol); } -string +std::string report_delay_calc_cmd(Edge *edge, - TimingArc *arc, - const Corner *corner, - const MinMax *min_max, - int digits) + TimingArc *arc, + const Scene *scene, + const MinMax *min_max, + int digits) { Sta *sta = Sta::sta(); - return sta->reportDelayCalc(edge, arc, corner, min_max, digits); + return sta->reportDelayCalc(edge, arc, scene, min_max, digits); } void diff --git a/dcalc/DelayCalc.tcl b/dcalc/DelayCalc.tcl index b920e4b0..e195fa23 100644 --- a/dcalc/DelayCalc.tcl +++ b/dcalc/DelayCalc.tcl @@ -25,7 +25,7 @@ namespace eval sta { define_cmd_args "report_dcalc" \ - {[-from from_pin] [-to to_pin] [-corner corner] [-min] [-max] [-digits digits]} + {[-from from_pin] [-to to_pin] [-scene scene] [-min] [-max] [-digits digits]} proc_redirect report_dcalc { report_dcalc_cmd "report_dcalc" $args "-digits" @@ -36,9 +36,9 @@ proc report_dcalc_cmd { cmd cmd_args digits_key } { global sta_report_default_digits parse_key_args $cmd cmd_args \ - keys "$digits_key -from -to -corner" \ + keys "$digits_key -from -to -scene -corner" \ flags {-min -max} - set corner [parse_corner keys] + set scene [parse_scene keys] set min_max [parse_min_max_flags flags] check_argc_eq0 $cmd $cmd_args @@ -52,14 +52,14 @@ proc report_dcalc_cmd { cmd cmd_args digits_key } { set to_pin [get_port_pin_error "to_pin" $keys(-to)] foreach from_vertex [$from_pin vertices] { foreach to_vertex [$to_pin vertices] { - set iter [$from_vertex out_edge_iterator] - while {[$iter has_next]} { - set edge [$iter next] - if { [$edge to] == $to_vertex } { - report_edge_dcalc $edge $corner $min_max $digits - } - } - $iter finish + set iter [$from_vertex out_edge_iterator] + while {[$iter has_next]} { + set edge [$iter next] + if { [$edge to] == $to_vertex } { + report_edge_dcalc $edge $scene $min_max $digits + } + } + $iter finish } } } elseif [info exists keys(-from)] { @@ -67,8 +67,8 @@ proc report_dcalc_cmd { cmd cmd_args digits_key } { foreach from_vertex [$from_pin vertices] { set iter [$from_vertex out_edge_iterator] while {[$iter has_next]} { - set edge [$iter next] - report_edge_dcalc $edge $corner $min_max $digits + set edge [$iter next] + report_edge_dcalc $edge $scene $min_max $digits } $iter finish } @@ -77,15 +77,15 @@ proc report_dcalc_cmd { cmd cmd_args digits_key } { foreach to_vertex [$to_pin vertices] { set iter [$to_vertex in_edge_iterator] while {[$iter has_next]} { - set edge [$iter next] - report_edge_dcalc $edge $corner $min_max $digits + set edge [$iter next] + report_edge_dcalc $edge $scene $min_max $digits } $iter finish } } } -proc report_edge_dcalc { edge corner min_max digits } { +proc report_edge_dcalc { edge scene min_max digits } { set role [$edge role] if { $role != "wire" } { set from_vertex [$edge from] @@ -96,7 +96,7 @@ proc report_edge_dcalc { edge corner min_max digits } { set library [$cell library] # Filter timing checks based on min_max. if {!(($min_max == "max" && $role == "hold") \ - || ($min_max=="min" && $role=="setup"))} { + || ($min_max=="min" && $role=="setup"))} { report_line "Library: [get_name $library]" report_line "Cell: [get_name $cell]" set sense [$edge sense] @@ -106,18 +106,18 @@ proc report_edge_dcalc { edge corner min_max digits } { report_line "Arc type: $role" foreach arc [$edge timing_arcs] { - set from [get_name [$from_pin port]] - set from_rf [$arc from_edge] - set to [get_name [$to_pin port]] - set to_rf [$arc to_edge] - report_line "$from $from_rf -> $to $to_rf" - report_line [report_delay_calc_cmd $edge $arc $corner $min_max $digits] - if { [$edge delay_annotated $arc $corner $min_max] } { - set delay [$edge arc_delay $arc $corner $min_max] - report_line "Annotated value = [format_time $delay $digits]" - } - report_line "............................................." - report_line "" + set from [get_name [$from_pin port]] + set from_rf [$arc from_edge] + set to [get_name [$to_pin port]] + set to_rf [$arc to_edge] + report_line "$from $from_rf -> $to $to_rf" + report_line [report_delay_calc_cmd $edge $arc $scene $min_max $digits] + if { [$edge delay_annotated $arc $scene $min_max] } { + set delay [$edge arc_delay $arc $scene $min_max] + report_line "Annotated value = [format_time $delay $digits]" + } + report_line "............................................." + report_line "" } } } @@ -140,16 +140,16 @@ define_cmd_args "set_pocv_sigma_factor" { factor } ################################################################ define_cmd_args "set_assigned_delay" \ - {-cell|-net [-rise] [-fall] [-corner corner] [-min] [-max]\ + {-cell|-net [-rise] [-fall] [-scene scene] [-min] [-max]\ [-from from_pins] [-to to_pins] delay} # Change the delay for timing arcs between from_pins and to_pins matching # on cell (instance) or net. proc set_assigned_delay { args } { - parse_key_args "set_assigned_delay" args keys {-corner -from -to} \ + parse_key_args "set_assigned_delay" args keys {-scene -corner -from -to} \ flags {-cell -net -rise -fall -max -min} check_argc_eq1 "set_assigned_delay" $args - set corner [parse_corner keys] + set scene [parse_scene keys] set min_max [parse_min_max_all_check_flags flags] set to_rf [parse_rise_fall_flags flags] @@ -176,14 +176,14 @@ proc set_assigned_delay { args } { if { $from_pins != {} } { set inst [[lindex $from_pins 0] instance] foreach pin $from_pins { - if {[$pin instance] != $inst} { - sta_error 185 "set_assigned_delay pin [get_full_name $pin] is not attached to instance [get_full_name $inst]." - } + if {[$pin instance] != $inst} { + sta_error 185 "set_assigned_delay pin [get_full_name $pin] is not attached to instance [get_full_name $inst]." + } } foreach pin $to_pins { - if {[$pin instance] != $inst} { - sta_error 186 "set_assigned_delay pin [get_full_name $pin] is not attached to instance [get_full_name $inst]" - } + if {[$pin instance] != $inst} { + sta_error 186 "set_assigned_delay pin [get_full_name $pin] is not attached to instance [get_full_name $inst]" + } } } } elseif {![info exists flags(-net)]} { @@ -192,40 +192,40 @@ proc set_assigned_delay { args } { foreach from_pin $from_pins { set from_vertices [$from_pin vertices] set_assigned_delay1 [lindex $from_vertices 0] \ - $to_pins $to_rf $corner $min_max $delay + $to_pins $to_rf $scene $min_max $delay if { [llength $from_vertices] == 2 } { set_assigned_delay1 [lindex $from_vertices 1] \ - $to_pins $to_rf $corner $min_max $delay + $to_pins $to_rf $scene $min_max $delay } } } -proc set_assigned_delay1 { from_vertex to_pins to_rf corner min_max delay } { +proc set_assigned_delay1 { from_vertex to_pins to_rf scene min_max delay } { foreach to_pin $to_pins { set to_vertices [$to_pin vertices] set_assigned_delay2 $from_vertex [lindex $to_vertices 0] \ - $to_rf $corner $min_max $delay + $to_rf $scene $min_max $delay if { [llength $to_vertices] == 2 } { # Bidirect driver. set_assigned_delay2 $from_vertex [lindex $to_vertices 1] \ - $to_rf $corner $min_max $delay + $to_rf $scene $min_max $delay } } } -proc set_assigned_delay2 {from_vertex to_vertex to_rf corner min_max delay} { +proc set_assigned_delay2 {from_vertex to_vertex to_rf scene min_max delay} { set matched 0 set edge_iter [$from_vertex out_edge_iterator] while {[$edge_iter has_next]} { set edge [$edge_iter next] if { [$edge to] == $to_vertex \ - && ![timing_role_is_check [$edge role]] } { + && ![timing_role_is_check [$edge role]] } { foreach arc [$edge timing_arcs] { - if { $to_rf == "rise_fall" \ - || $to_rf eq [$arc to_edge_name] } { - set_arc_delay $edge $arc $corner $min_max $delay + if { $to_rf == "rise_fall" \ + || $to_rf eq [$arc to_edge_name] } { + set_arc_delay $edge $arc $scene $min_max $delay set matched 1 - } + } } } } @@ -239,13 +239,13 @@ proc set_assigned_delay2 {from_vertex to_vertex to_rf corner min_max delay} { define_cmd_args "set_assigned_check" \ {-setup|-hold|-recovery|-removal [-rise] [-fall]\ - [-corner corner] [-min] [-max]\ + [-scene scene] [-min] [-max]\ [-from from_pins] [-to to_pins] [-clock rise|fall]\ [-cond sdf_cond] check_value} proc set_assigned_check { args } { parse_key_args "set_assigned_check" args \ - keys {-from -to -corner -clock -cond} \ + keys {-from -to -scene -corner -clock -cond} \ flags {-setup -hold -recovery -removal -rise -fall -max -min} check_argc_eq1 "set_assigned_check" $args @@ -258,7 +258,7 @@ proc set_assigned_check { args } { if { [info exists keys(-clock)] } { set clk_arg $keys(-clock) if { $clk_arg eq "rise" \ - || $clk_arg eq "fall" } { + || $clk_arg eq "fall" } { set from_rf $clk_arg } else { sta_error 189 "set_assigned_check -clock must be rise or fall." @@ -271,7 +271,7 @@ proc set_assigned_check { args } { sta_error 190 "set_assigned_check missing -to argument." } set to_rf [parse_rise_fall_flags flags] - set corner [parse_corner keys] + set scene [parse_scene keys] set min_max [parse_min_max_all_check_flags flags] if { [info exists flags(-setup)] } { @@ -298,46 +298,46 @@ proc set_assigned_check { args } { foreach from_pin $from_pins { set from_vertices [$from_pin vertices] set_assigned_check1 [lindex $from_vertices 0] $from_rf \ - $to_pins $to_rf $role $corner $min_max $cond $check_value + $to_pins $to_rf $role $scene $min_max $cond $check_value if { [llength $from_vertices] == 2 } { set_assigned_check1 [lindex $from_vertices 1] $from_rf \ - $to_pins $to_rf $role $corner $min_max $cond $check_value + $to_pins $to_rf $role $scene $min_max $cond $check_value } } } proc set_assigned_check1 { from_vertex from_rf to_pins to_rf \ - role corner min_max cond check_value } { + role scene min_max cond check_value } { foreach to_pin $to_pins { set to_vertices [$to_pin vertices] set_assigned_check2 $from_vertex $from_rf [lindex $to_vertices 0] \ - $to_rf $role $corner $min_max $cond $check_value + $to_rf $role $scene $min_max $cond $check_value if { [llength $to_vertices] == 2 } { # Bidirect driver. set_assigned_check2 $from_vertex $from_rf \ - [lindex $to_vertices 1] $to_rf $role $corner $min_max \ - $cond $check_value + [lindex $to_vertices 1] $to_rf $role $scene $min_max \ + $cond $check_value } } } proc set_assigned_check2 { from_vertex from_rf to_vertex to_rf \ - role corner min_max cond check_value } { + role scene min_max cond check_value } { set edge_iter [$from_vertex out_edge_iterator] set matched 0 while {[$edge_iter has_next]} { set edge [$edge_iter next] if { [$edge to] == $to_vertex } { foreach arc [$edge timing_arcs] { - if { ($from_rf eq "rise_fall" \ - || $from_rf eq [$arc from_edge_name]) \ - && ($to_rf eq "rise_fall" \ - || $to_rf eq [$arc to_edge_name]) \ - && [$arc role] eq $role \ - && ($cond eq "" || [$arc sdf_cond] eq $cond) } { - set_arc_delay $edge $arc $corner $min_max $check_value + if { ($from_rf eq "rise_fall" \ + || $from_rf eq [$arc from_edge_name]) \ + && ($to_rf eq "rise_fall" \ + || $to_rf eq [$arc to_edge_name]) \ + && [$arc role] eq $role \ + && ($cond eq "" || [$arc sdf_cond] eq $cond) } { + set_arc_delay $edge $arc $scene $min_max $check_value set matched 1 - } + } } } } @@ -350,14 +350,14 @@ proc set_assigned_check2 { from_vertex from_rf to_vertex to_rf \ ################################################################a define_cmd_args "set_assigned_transition" \ - {[-rise] [-fall] [-corner corner] [-min] [-max] slew pins} + {[-rise] [-fall] [-scene scene] [-min] [-max] slew pins} # Change the slew on a list of ports. proc set_assigned_transition { args } { - parse_key_args "set_assigned_transition" args keys {-corner} \ + parse_key_args "set_assigned_transition" args keys {-scene -corner} \ flags {-rise -fall -max -min} - set corner [parse_corner keys] + set scene [parse_scene keys] set min_max [parse_min_max_all_check_flags flags] set tr [parse_rise_fall_flags flags] check_argc_eq2 "set_assigned_transition" $args @@ -371,7 +371,7 @@ proc set_assigned_transition { args } { foreach pin $pins { set vertices [$pin vertices] set vertex [lindex $vertices 0] - set_annotated_slew $vertex $corner $min_max $tr $slew + set_annotated_slew $vertex $scene $min_max $tr $slew if { [llength $vertices] == 2 } { # Bidirect driver. set vertex [lindex $vertices 1] @@ -380,5 +380,27 @@ proc set_assigned_transition { args } { } } +################################################################ + +define_cmd_args "report_slews" {[-scenes scenes] pin} + +proc report_slews { args } { + global sta_report_default_digits + + parse_key_args "report_slews" args keys {-corner -scenes} flags {} + check_argc_eq1 "report_slews" $args + + set scenes [parse_scenes_or_all keys] + set pin [get_port_pin_error "pin" [lindex $args 0]] + set digits $sta_report_default_digits + foreach vertex [$pin vertices] { + set rise_min [format_time [$vertex slew_scenes rise $scenes min] $digits] + set rise_max [format_time [$vertex slew_scenes rise $scenes max] $digits] + set fall_min [format_time [$vertex slew_scenes fall $scenes min] $digits] + set fall_max [format_time [$vertex slew_scenes fall $scenes max] $digits] + report_line "[vertex_path_name $vertex] [rise_short_name] $rise_min:$rise_max [fall_short_name] $fall_min:$fall_max" + } +} + # sta namespace end } diff --git a/dcalc/DelayCalcBase.cc b/dcalc/DelayCalcBase.cc index 8c15bfdb..ecaa16d4 100644 --- a/dcalc/DelayCalcBase.cc +++ b/dcalc/DelayCalcBase.cc @@ -32,8 +32,7 @@ #include "Parasitics.hh" #include "Graph.hh" #include "Sdc.hh" -#include "Corner.hh" -#include "DcalcAnalysisPt.hh" +#include "Scene.hh" #include "GraphDelayCalc.hh" #include "Variables.hh" @@ -50,7 +49,7 @@ DelayCalcBase::DelayCalcBase(StaState *sta) : void DelayCalcBase::reduceParasitic(const Parasitic *parasitic_network, const Net *net, - const Corner *corner, + const Scene *scene, const MinMaxAll *min_max) { NetConnectedPinIterator *pin_iter = network_->connectedPinIterator(net); @@ -59,16 +58,12 @@ DelayCalcBase::reduceParasitic(const Parasitic *parasitic_network, if (network_->isDriver(pin)) { for (const RiseFall *rf : RiseFall::range()) { for (const MinMax *min_max : min_max->range()) { - if (corner == nullptr) { - for (const Corner *corner1 : *corners_) { - DcalcAnalysisPt *dcalc_ap = corner1->findDcalcAnalysisPt(min_max); - reduceParasitic(parasitic_network, pin, rf, dcalc_ap); - } - } - else { - DcalcAnalysisPt *dcalc_ap = corner->findDcalcAnalysisPt(min_max); - reduceParasitic(parasitic_network, pin, rf, dcalc_ap); + if (scene == nullptr) { + for (const Scene *scene1 : scenes_) + reduceParasitic(parasitic_network, pin, rf, scene1, min_max); } + else + reduceParasitic(parasitic_network, pin, rf, scene, min_max); } } } @@ -136,7 +131,7 @@ DelayCalcBase::thresholdAdjust(const Pin *load_pin, float drvr_slew_derate = drvr_library->slewDerateFromLibrary(); float load_slew_derate = load_library->slewDerateFromLibrary(); load_slew = load_slew * ((load_slew_delta / load_slew_derate) - / (drvr_slew_delta / drvr_slew_derate)); + / (drvr_slew_delta / drvr_slew_derate)); } } @@ -162,13 +157,15 @@ DelayCalcBase::checkDelay(const Pin *check_pin, const Slew &from_slew, const Slew &to_slew, float related_out_cap, - const DcalcAnalysisPt *dcalc_ap) + const Scene *scene, + const MinMax *min_max) { - CheckTimingModel *model = arc->checkModel(dcalc_ap); + CheckTimingModel *model = arc->checkModel(scene, min_max); if (model) { float from_slew1 = delayAsFloat(from_slew); float to_slew1 = delayAsFloat(to_slew); - return model->checkDelay(pinPvt(check_pin, dcalc_ap), from_slew1, to_slew1, + return model->checkDelay(pinPvt(check_pin, scene, min_max), + from_slew1, to_slew1, related_out_cap, variables_->pocvEnabled()); } @@ -183,40 +180,46 @@ DelayCalcBase::reportCheckDelay(const Pin *check_pin, const char *from_slew_annotation, const Slew &to_slew, float related_out_cap, - const DcalcAnalysisPt *dcalc_ap, + const Scene *scene, + const MinMax *min_max, int digits) { - CheckTimingModel *model = arc->checkModel(dcalc_ap); + CheckTimingModel *model = arc->checkModel(scene, min_max); if (model) { float from_slew1 = delayAsFloat(from_slew); float to_slew1 = delayAsFloat(to_slew); - return model->reportCheckDelay(pinPvt(check_pin, dcalc_ap), from_slew1, - from_slew_annotation, to_slew1, - related_out_cap, false, digits); + return model->reportCheckDelay(pinPvt(check_pin, scene, min_max), + from_slew1, from_slew_annotation, + to_slew1, related_out_cap, false, + digits); } return ""; } const Pvt * DelayCalcBase::pinPvt(const Pin *pin, - const DcalcAnalysisPt *dcalc_ap) + const Scene *scene, + const MinMax *min_max) { const Instance *drvr_inst = network_->instance(pin); - const Pvt *pvt = sdc_->pvt(drvr_inst, dcalc_ap->constraintMinMax()); + const Sdc *sdc = scene->sdc(); + const Pvt *pvt = sdc->pvt(drvr_inst, min_max); if (pvt == nullptr) - pvt = dcalc_ap->operatingConditions(); + pvt = sdc->operatingConditions(min_max); return pvt; } void DelayCalcBase::setDcalcArgParasiticSlew(ArcDcalcArg &gate, - const DcalcAnalysisPt *dcalc_ap) + const Scene *scene, + const MinMax *min_max) { const Pin *drvr_pin = gate.drvrPin(); if (drvr_pin) { const Parasitic *parasitic; float load_cap; - graph_delay_calc_->parasiticLoad(drvr_pin, gate.drvrEdge(), dcalc_ap, + graph_delay_calc_->parasiticLoad(drvr_pin, gate.drvrEdge(), + scene, min_max, nullptr, this, load_cap, parasitic); gate.setLoadCap(load_cap); @@ -224,17 +227,19 @@ DelayCalcBase::setDcalcArgParasiticSlew(ArcDcalcArg &gate, const Pin *in_pin = gate.inPin(); const Vertex *in_vertex = graph_->pinLoadVertex(in_pin); const Slew &in_slew = graph_delay_calc_->edgeFromSlew(in_vertex, gate.inEdge(), - gate.edge(), dcalc_ap); + gate.edge(), + scene, min_max); gate.setInSlew(in_slew); } } void DelayCalcBase::setDcalcArgParasiticSlew(ArcDcalcArgSeq &gates, - const DcalcAnalysisPt *dcalc_ap) + const Scene *scene, + const MinMax *min_max) { for (ArcDcalcArg &gate : gates) - setDcalcArgParasiticSlew(gate, dcalc_ap); + setDcalcArgParasiticSlew(gate, scene, min_max); } } // namespace diff --git a/dcalc/DelayCalcBase.hh b/dcalc/DelayCalcBase.hh index 82597f7e..6caa4f6c 100644 --- a/dcalc/DelayCalcBase.hh +++ b/dcalc/DelayCalcBase.hh @@ -34,23 +34,26 @@ class GateTableModel; class DelayCalcBase : public ArcDelayCalc { public: - explicit DelayCalcBase(StaState *sta); + DelayCalcBase(StaState *sta); void finishDrvrPin() override; void reduceParasitic(const Parasitic *parasitic_network, const Net *net, - const Corner *corner, + const Scene *scene, const MinMaxAll *min_max) override; void setDcalcArgParasiticSlew(ArcDcalcArg &gate, - const DcalcAnalysisPt *dcalc_ap) override; + const Scene *scene, + const MinMax *min_max) override; void setDcalcArgParasiticSlew(ArcDcalcArgSeq &gates, - const DcalcAnalysisPt *dcalc_ap) override; + const Scene *scene, + const MinMax *min_max) override; ArcDelay checkDelay(const Pin *check_pin, const TimingArc *arc, const Slew &from_slew, const Slew &to_slew, float related_out_cap, - const DcalcAnalysisPt *dcalc_ap) override; + const Scene *scene, + const MinMax *min_max) override; std::string reportCheckDelay(const Pin *check_pin, const TimingArc *arc, @@ -58,7 +61,8 @@ public: const char *from_slew_annotation, const Slew &to_slew, float related_out_cap, - const DcalcAnalysisPt *dcalc_ap, + const Scene *scene, + const MinMax *min_max, int digits) override; protected: @@ -68,18 +72,19 @@ protected: void thresholdAdjust(const Pin *load_pin, const LibertyLibrary *drvr_library, const RiseFall *rf, - ArcDelay &load_delay, - Slew &load_slew); + ArcDelay &load_delay, + Slew &load_slew); // Helper function for input ports driving dspf parasitic. void dspfWireDelaySlew(const Pin *load_pin, - const RiseFall *rf, + const RiseFall *rf, Slew drvr_slew, float elmore, // Return values. - ArcDelay &wire_delay, - Slew &load_slew); + ArcDelay &wire_delay, + Slew &load_slew); const Pvt *pinPvt(const Pin *pin, - const DcalcAnalysisPt *dcalc_ap); + const Scene *scene, + const MinMax *min_max); using ArcDelayCalc::reduceParasitic; }; diff --git a/dcalc/DmpCeff.cc b/dcalc/DmpCeff.cc index e5b8f85e..d759fc40 100644 --- a/dcalc/DmpCeff.cc +++ b/dcalc/DmpCeff.cc @@ -44,7 +44,6 @@ #include "Network.hh" #include "Sdc.hh" #include "Parasitics.hh" -#include "DcalcAnalysisPt.hh" #include "ArcDelayCalc.hh" #include "FindRoot.hh" #include "Variables.hh" @@ -95,36 +94,36 @@ private: static double gateModelRd(const LibertyCell *cell, - const GateTableModel *gate_model, - const RiseFall *rf, - double in_slew, - double c2, - double c1, - const Pvt *pvt, - bool pocv_enabled); + const GateTableModel *gate_model, + const RiseFall *rf, + double in_slew, + double c2, + double c1, + const Pvt *pvt, + bool pocv_enabled); static void newtonRaphson(const int max_iter, - double x[], - const int n, - const double x_tol, - // eval(state) is called to fill fvec and fjac. - function eval, - // Temporaries supplied by caller. - double *fvec, - double **fjac, - int *index, - double *p, - double *scale); + double x[], + const int n, + const double x_tol, + // eval(state) is called to fill fvec and fjac. + function eval, + // Temporaries supplied by caller. + double *fvec, + double **fjac, + int *index, + double *p, + double *scale); static void luSolve(double **a, - const int size, - const int *index, - double b[]); + const int size, + const int *index, + double b[]); static void luDecomp(double **a, - const int size, - int *index, - double *scale); + const int size, + int *index, + double *scale); //////////////////////////////////////////////////////////////// @@ -138,23 +137,23 @@ public: virtual const char *name() = 0; // Set driver model and pi model parameters for delay calculation. virtual void init(const LibertyLibrary *library, - const LibertyCell *drvr_cell, - const Pvt *pvt, - const GateTableModel *gate_model, - const RiseFall *rf, - double rd, - double in_slew, - double c2, - double rpi, - double c1); + const LibertyCell *drvr_cell, + const Pvt *pvt, + const GateTableModel *gate_model, + const RiseFall *rf, + double rd, + double in_slew, + double c2, + double rpi, + double c1); virtual void gateDelaySlew(// Return values. double &delay, - double &slew) = 0; + double &slew) = 0; virtual void loadDelaySlew(const Pin *load_pin, - double elmore, + double elmore, // Return values. - ArcDelay &delay, - Slew &slew); + ArcDelay &delay, + Slew &slew); double ceff() { return ceff_; } // Given x_ as a vector of input parameters, fill fvec_ with the @@ -176,32 +175,32 @@ protected: void findDriverParams(double ceff); void gateCapDelaySlew(double cl, // Return values. - double &delay, - double &slew); + double &delay, + double &slew); void gateDelays(double ceff, // Return values. - double &t_vth, - double &t_vl, - double &slew); + double &t_vth, + double &t_vl, + double &slew); // Partial derivatives of y(t) (jacobian). void dy(double t, - double t0, - double dt, - double cl, + double t0, + double dt, + double cl, // Return values. - double &dydt0, - double &dyddt, - double &dydcl); + double &dydt0, + double &dyddt, + double &dydcl); double y0dt(double t, - double cl); + double cl); double y0dcl(double t, - double cl); + double cl); void showX(); void showFvec(); void showJacobian(); void findDriverDelaySlew(// Return values. double &delay, - double &slew); + double &slew); double findVoCrossing(double vth, double lower_bound, double upper_bound); @@ -214,12 +213,12 @@ protected: // Output response to vs(t) ramp driving capacitive load. double y(double t, - double t0, - double dt, - double cl); + double t0, + double dt, + double cl); // Output response to unit ramp driving capacitive load. double y0(double t, - double cl); + double cl); // Output response to unit ramp driving pi model load. virtual void V0(double t, // Return values. @@ -285,7 +284,7 @@ protected: }; DmpAlg::DmpAlg(int nr_order, - StaState *sta): + StaState *sta): StaState(sta), c2_(0.0), rpi_(0.0), @@ -301,16 +300,16 @@ DmpAlg::~DmpAlg() = default; void DmpAlg::init(const LibertyLibrary *drvr_library, - const LibertyCell *drvr_cell, - const Pvt *pvt, - const GateTableModel *gate_model, - const RiseFall *rf, - double rd, - double in_slew, - // Pi model. - double c2, - double rpi, - double c1) + const LibertyCell *drvr_cell, + const Pvt *pvt, + const GateTableModel *gate_model, + const RiseFall *rf, + double rd, + double in_slew, + // Pi model. + double c2, + double rpi, + double c1) { drvr_library_ = drvr_library; drvr_cell_ = drvr_cell; @@ -343,7 +342,7 @@ DmpAlg::findDriverParams(double ceff) x_[DmpParam::t0] = t0; newtonRaphson(100, x_, nr_order_, driver_param_tol, [this] () { evalDmpEqns(); }, - fvec_, fjac_, index_, p_, scale_); + fvec_, fjac_, index_, p_, scale_); t0_ = x_[DmpParam::t0]; dt_ = x_[DmpParam::dt]; debugPrint(debug_, "dmp_ceff", 3, " t0 = %s dt = %s ceff = %s", @@ -356,9 +355,9 @@ DmpAlg::findDriverParams(double ceff) void DmpAlg::gateCapDelaySlew(double ceff, - // Return values. + // Return values. double &delay, - double &slew) + double &slew) { ArcDelay model_delay; Slew model_slew; @@ -371,10 +370,10 @@ DmpAlg::gateCapDelaySlew(double ceff, void DmpAlg::gateDelays(double ceff, - // Return values. + // Return values. double &t_vth, - double &t_vl, - double &slew) + double &t_vl, + double &slew) { double table_slew; gateCapDelaySlew(ceff, t_vth, table_slew); @@ -385,9 +384,9 @@ DmpAlg::gateDelays(double ceff, double DmpAlg::y(double t, - double t0, - double dt, - double cl) + double t0, + double dt, + double cl) { double t1 = t - t0; if (t1 <= 0.0) @@ -400,20 +399,20 @@ DmpAlg::y(double t, double DmpAlg::y0(double t, - double cl) + double cl) { return t - rd_ * cl * (1.0 - exp2(-t / (rd_ * cl))); } void DmpAlg::dy(double t, - double t0, - double dt, - double cl, - // Return values. - double &dydt0, - double &dyddt, - double &dydcl) + double t0, + double dt, + double cl, + // Return values. + double &dydt0, + double &dyddt, + double &dydcl) { double t1 = t - t0; if (t1 <= 0.0) @@ -433,14 +432,14 @@ DmpAlg::dy(double t, double DmpAlg::y0dt(double t, - double cl) + double cl) { return 1.0 - exp2(-t / (rd_ * cl)); } double DmpAlg::y0dcl(double t, - double cl) + double cl) { return rd_ * ((1.0 + t / (rd_ * cl)) * exp2(-t / (rd_ * cl)) - 1); } @@ -478,7 +477,7 @@ DmpAlg::showJacobian() void DmpAlg::findDriverDelaySlew(// Return values. double &delay, - double &slew) + double &slew) { double t_upper = voCrossingUpperBound(); delay = findVoCrossing(vth_, t0_, t_upper); @@ -554,9 +553,9 @@ DmpAlg::showVo() void DmpAlg::loadDelaySlew(const Pin *, - double elmore, - ArcDelay &delay, - Slew &slew) + double elmore, + ArcDelay &delay, + Slew &slew) { if (!driver_valid_ || elmore == 0.0 @@ -570,7 +569,7 @@ DmpAlg::loadDelaySlew(const Pin *, // convert the delay and slew to the load's thresholds. try { if (debug_->check("dmp_ceff", 4)) - showVl(); + showVl(); elmore_ = elmore; p3_ = 1.0 / elmore; double t_lower = t0_; @@ -583,17 +582,17 @@ DmpAlg::loadDelaySlew(const Pin *, // Convert measured slew to reported/table slew. double slew1 = (th - tl) / slew_derate_; if (delay1 < 0.0) { - // Only report a problem if the difference is significant. - if (-delay1 > vth_time_tol * vo_delay_) - fail("load delay less than zero"); - // Use elmore delay. - delay1 = elmore; + // Only report a problem if the difference is significant. + if (-delay1 > vth_time_tol * vo_delay_) + fail("load delay less than zero"); + // Use elmore delay. + delay1 = elmore; } if (slew1 < drvr_slew_) { - // Only report a problem if the difference is significant. - if ((drvr_slew_ - slew1) > vth_time_tol * drvr_slew_) - fail("load slew less than driver slew"); - slew1 = drvr_slew_; + // Only report a problem if the difference is significant. + if ((drvr_slew_ - slew1) > vth_time_tol * drvr_slew_) + fail("load slew less than driver slew"); + slew1 = drvr_slew_; } delay = delay1; slew = slew1; @@ -735,26 +734,26 @@ DmpCap::DmpCap(StaState *sta): void DmpCap::init(const LibertyLibrary *drvr_library, - const LibertyCell *drvr_cell, - const Pvt *pvt, - const GateTableModel *gate_model, - const RiseFall *rf, - double rd, - double in_slew, - double c2, - double rpi, - double c1) + const LibertyCell *drvr_cell, + const Pvt *pvt, + const GateTableModel *gate_model, + const RiseFall *rf, + double rd, + double in_slew, + double c2, + double rpi, + double c1) { debugPrint(debug_, "dmp_ceff", 3, "Using DMP cap"); DmpAlg::init(drvr_library, drvr_cell, pvt, gate_model, rf, - rd, in_slew, c2, rpi, c1); + rd, in_slew, c2, rpi, c1); ceff_ = c1 + c2; } void DmpCap::gateDelaySlew(// Return values. double &delay, - double &slew) + double &slew) { debugPrint(debug_, "dmp_ceff", 3, " ceff = %s", units_->capacitanceUnit()->asString(ceff_)); @@ -764,9 +763,9 @@ DmpCap::gateDelaySlew(// Return values. void DmpCap::loadDelaySlew(const Pin *, - double elmore, - ArcDelay &delay, - Slew &slew) + double elmore, + ArcDelay &delay, + Slew &slew) { delay = elmore; slew = drvr_slew_; @@ -830,9 +829,9 @@ public: private: void findDriverParamsPi(); double ipiIceff(double t0, - double dt, - double ceff_time, - double ceff); + double dt, + double ceff_time, + double ceff); void V0(double t, // Return values. double &vo, @@ -876,19 +875,19 @@ DmpPi::DmpPi(StaState *sta) : void DmpPi::init(const LibertyLibrary *drvr_library, - const LibertyCell *drvr_cell, - const Pvt *pvt, - const GateTableModel *gate_model, - const RiseFall *rf, - double rd, - double in_slew, - double c2, - double rpi, - double c1) + const LibertyCell *drvr_cell, + const Pvt *pvt, + const GateTableModel *gate_model, + const RiseFall *rf, + double rd, + double in_slew, + double c2, + double rpi, + double c1) { debugPrint(debug_, "dmp_ceff", 3, "Using DMP Pi"); DmpAlg::init(drvr_library, drvr_cell, pvt, gate_model, rf, rd, - in_slew, c2, rpi, c1); + in_slew, c2, rpi, c1); // Find poles/zeros. z1_ = 1.0 / (rpi_ * c1_); @@ -914,7 +913,7 @@ DmpPi::init(const LibertyLibrary *drvr_library, void DmpPi::gateDelaySlew(// Return values. double &delay, - double &slew) + double &slew) { driver_valid_ = false; try { @@ -1000,7 +999,7 @@ DmpPi::evalDmpEqns() (-A_ * dt + B_ * dt * exp_p1_dt - (2 * B_ / p1_) * (1.0 - exp_p1_dt) + D_ * dt * exp_p2_dt - (2 * D_ / p2_) * (1.0 - exp_p2_dt) + rd_ * ceff * (dt + dt * exp_dt_rd_ceff - - 2 * rd_ * ceff * (1.0 - exp_dt_rd_ceff))) + - 2 * rd_ * ceff * (1.0 - exp_dt_rd_ceff))) / (rd_ * dt * dt * dt); fjac_[DmpFunc::ipi][DmpParam::ceff] = (2 * rd_ * ceff - dt - (2 * rd_ * ceff + dt) * exp2(-dt / (rd_ * ceff))) @@ -1027,17 +1026,17 @@ DmpPi::evalDmpEqns() // Eqn 13, Eqn 14. double DmpPi::ipiIceff(double, double dt, - double ceff_time, - double ceff) + double ceff_time, + double ceff) { double exp_p1_dt = exp2(-p1_ * ceff_time); double exp_p2_dt = exp2(-p2_ * ceff_time); double exp_dt_rd_ceff = exp2(-ceff_time / (rd_ * ceff)); double ipi = (A_ * ceff_time + (B_ / p1_) * (1.0 - exp_p1_dt) - + (D_ / p2_) * (1.0 - exp_p2_dt)) + + (D_ / p2_) * (1.0 - exp_p2_dt)) / (rd_ * ceff_time * dt); double iceff = (rd_ * ceff * ceff_time - (rd_ * ceff) * (rd_ * ceff) - * (1.0 - exp_dt_rd_ceff)) + * (1.0 - exp_dt_rd_ceff)) / (rd_ * ceff_time * dt); return ipi - iceff; } @@ -1064,7 +1063,7 @@ DmpPi::Vl0(double t, double D3 = -p3_ * k0_ * k3_ / (p1_ - p3_); double D4 = -p3_ * k0_ * k4_ / (p2_ - p3_); double D5 = k0_ * (k2_ / p3_ - k1_ + p3_ * k3_ / (p1_ - p3_) - + p3_ * k4_ / (p2_ - p3_)); + + p3_ * k4_ / (p2_ - p3_)); double exp_p1 = exp2(-p1_ * t); double exp_p2 = exp2(-p2_ * t); double exp_p3 = exp2(-p3_ * t); @@ -1194,19 +1193,19 @@ DmpZeroC2::DmpZeroC2(StaState *sta) : void DmpZeroC2::init(const LibertyLibrary *drvr_library, - const LibertyCell *drvr_cell, - const Pvt *pvt, - const GateTableModel *gate_model, - const RiseFall *rf, - double rd, - double in_slew, - double c2, - double rpi, - double c1) + const LibertyCell *drvr_cell, + const Pvt *pvt, + const GateTableModel *gate_model, + const RiseFall *rf, + double rd, + double in_slew, + double c2, + double rpi, + double c1) { debugPrint(debug_, "dmp_ceff", 3, "Using DMP C2=0"); DmpAlg::init(drvr_library, drvr_cell, pvt, gate_model, rf, rd, - in_slew, c2, rpi, c1); + in_slew, c2, rpi, c1); ceff_ = c1; z1_ = 1.0 / (rpi_ * c1_); @@ -1221,7 +1220,7 @@ DmpZeroC2::init(const LibertyLibrary *drvr_library, void DmpZeroC2::gateDelaySlew(// Return values. double &delay, - double &slew) + double &slew) { try { findDriverParams(c1_); @@ -1280,16 +1279,16 @@ DmpZeroC2::voCrossingUpperBound() // Return error msg on failure. static void newtonRaphson(const int max_iter, - double x[], - const int size, - const double x_tol, - function eval, - // Temporaries supplied by caller. - double *fvec, - double **fjac, - int *index, - double *p, - double *scale) + double x[], + const int size, + const double x_tol, + function eval, + // Temporaries supplied by caller. + double *fvec, + double **fjac, + int *index, + double *p, + double *scale) { for (int k = 0; k < max_iter; k++) { eval(); @@ -1302,7 +1301,7 @@ newtonRaphson(const int max_iter, bool all_under_x_tol = true; for (int i = 0; i < size; i++) { if (abs(p[i]) > abs(x[i]) * x_tol) - all_under_x_tol = false; + all_under_x_tol = false; x[i] += p[i]; } if (all_under_x_tol) @@ -1325,11 +1324,11 @@ newtonRaphson(const int max_iter, // Return error msg on failure. void luDecomp(double **a, - const int size, - int *index, - // Temporary supplied by caller. - // scale stores the implicit scaling of each row. - double *scale) + const int size, + int *index, + // Temporary supplied by caller. + // scale stores the implicit scaling of each row. + double *scale) { // Find implicit scaling factors. for (int i = 0; i < size; i++) { @@ -1337,7 +1336,7 @@ luDecomp(double **a, for (int j = 0; j < size; j++) { double temp = abs(a[i][j]); if (temp > big) - big = temp; + big = temp; } if (big == 0.0) throw DmpError("LU decomposition: no non-zero row element"); @@ -1349,7 +1348,7 @@ luDecomp(double **a, for (int i = 0; i < j; i++) { double sum = a[i][j]; for (int k = 0; k < i; k++) - sum -= a[i][k] * a[k][j]; + sum -= a[i][k] * a[k][j]; a[i][j] = sum; } // Run down jth subdiag to form the residuals after the elimination @@ -1362,21 +1361,21 @@ luDecomp(double **a, for (int i = j; i < size; i++) { double sum = a[i][j]; for (int k = 0; k < j; k++) - sum -= a[i][k] * a[k][j]; + sum -= a[i][k] * a[k][j]; a[i][j] = sum; double dum = scale[i] * abs(sum); if (dum >= big) { - big = dum; - imax = i; + big = dum; + imax = i; } } // Permute current row with imax. if (j != imax) { // Yes, do so... for (int k = 0; k < size; k++) { - double dum = a[imax][k]; - a[imax][k] = a[j][k]; - a[j][k] = dum; + double dum = a[imax][k]; + a[imax][k] = a[j][k]; + a[j][k] = dum; } scale[imax] = scale[j]; } @@ -1387,7 +1386,7 @@ luDecomp(double **a, if (j != size_1) { double pivot = 1.0 / a[j][j]; for (int i = j + 1; i < size; i++) - a[i][j] *= pivot; + a[i][j] *= pivot; } } } @@ -1399,9 +1398,9 @@ luDecomp(double **a, // a and index are not modified. void luSolve(double **a, - const int size, - const int *index, - double b[]) + const int size, + const int *index, + double b[]) { // Transform b allowing for leading zeros. int non_zero = -1; @@ -1411,11 +1410,11 @@ luSolve(double **a, b[iperm] = b[i]; if (non_zero != -1) { for (int j = non_zero; j <= i - 1; j++) - sum -= a[i][j] * b[j]; + sum -= a[i][j] * b[j]; } else { if (sum != 0.0) - non_zero = i; + non_zero = i; } b[i] = sum; } @@ -1495,20 +1494,22 @@ DmpCeffDelayCalc::gateDelay(const Pin *drvr_pin, float load_cap, const Parasitic *parasitic, const LoadPinIndexMap &load_pin_index_map, - const DcalcAnalysisPt *dcalc_ap) + const Scene *scene, + const MinMax *min_max) { + parasitics_ = scene->parasitics(min_max); const RiseFall *rf = arc->toEdge()->asRiseFall(); const LibertyCell *drvr_cell = arc->from()->libertyCell(); const LibertyLibrary *drvr_library = drvr_cell->libertyLibrary(); - GateTableModel *table_model = arc->gateTableModel(dcalc_ap); + GateTableModel *table_model = arc->gateTableModel(scene, min_max); if (table_model && parasitic) { float in_slew1 = delayAsFloat(in_slew); float c2, rpi, c1; parasitics_->piModel(parasitic, c2, rpi, c1); if (isnan(c2) || isnan(c1) || isnan(rpi)) report_->error(1040, "parasitic Pi model has NaNs."); - setCeffAlgorithm(drvr_library, drvr_cell, pinPvt(drvr_pin, dcalc_ap), + setCeffAlgorithm(drvr_library, drvr_cell, pinPvt(drvr_pin, scene, min_max), table_model, rf, in_slew1, c2, rpi, c1); double gate_delay, drvr_slew; gateDelaySlew(gate_delay, drvr_slew); @@ -1529,12 +1530,12 @@ DmpCeffDelayCalc::gateDelay(const Pin *drvr_pin, else { ArcDcalcResult dcalc_result = LumpedCapDelayCalc::gateDelay(drvr_pin, arc, in_slew, load_cap, parasitic, - load_pin_index_map, dcalc_ap); + load_pin_index_map, scene, min_max); if (parasitic - && !unsuppored_model_warned_) { + && !unsuppored_model_warned_) { unsuppored_model_warned_ = true; report_->warn(1041, "cell %s delay model not supported on SPF parasitics by DMP delay calculator", - drvr_cell->name()); + drvr_cell->name()); } return dcalc_result; } @@ -1542,25 +1543,25 @@ DmpCeffDelayCalc::gateDelay(const Pin *drvr_pin, void DmpCeffDelayCalc::setCeffAlgorithm(const LibertyLibrary *drvr_library, - const LibertyCell *drvr_cell, - const Pvt *pvt, - const GateTableModel *gate_model, - const RiseFall *rf, - double in_slew, - double c2, - double rpi, - double c1) + const LibertyCell *drvr_cell, + const Pvt *pvt, + const GateTableModel *gate_model, + const RiseFall *rf, + double in_slew, + double c2, + double rpi, + double c1) { double rd = 0.0; if (gate_model) { rd = gateModelRd(drvr_cell, gate_model, rf, in_slew, c2, c1, - pvt, variables_->pocvEnabled()); + pvt, variables_->pocvEnabled()); // Zero Rd means the table is constant and thus independent of load cap. if (rd < 1e-2 - // Rpi is small compared to Rd, which makes the load capacitive. - || rpi < rd * 1e-3 - // c1/Rpi can be ignored. - || (c1 == 0.0 || c1 < c2 * 1e-3 || rpi == 0.0)) + // Rpi is small compared to Rd, which makes the load capacitive. + || rpi < rd * 1e-3 + // c1/Rpi can be ignored. + || (c1 == 0.0 || c1 < c2 * 1e-3 || rpi == 0.0)) dmp_alg_ = dmp_cap_; else if (c2 < c1 * 1e-3) dmp_alg_ = dmp_zero_c2_; @@ -1571,7 +1572,7 @@ DmpCeffDelayCalc::setCeffAlgorithm(const LibertyLibrary *drvr_library, else dmp_alg_ = dmp_cap_; dmp_alg_->init(drvr_library, drvr_cell, pvt, gate_model, - rf, rd, in_slew, c2, rpi, c1); + rf, rd, in_slew, c2, rpi, c1); debugPrint(debug_, "dmp_ceff", 3, " DMP in_slew = %s c2 = %s rpi = %s c1 = %s Rd = %s (%s alg)", units_->timeUnit()->asString(in_slew), @@ -1585,16 +1586,17 @@ DmpCeffDelayCalc::setCeffAlgorithm(const LibertyLibrary *drvr_library, string DmpCeffDelayCalc::reportGateDelay(const Pin *drvr_pin, const TimingArc *arc, - const Slew &in_slew, - float load_cap, - const Parasitic *parasitic, + const Slew &in_slew, + float load_cap, + const Parasitic *parasitic, const LoadPinIndexMap &load_pin_index_map, - const DcalcAnalysisPt *dcalc_ap, - int digits) + const Scene *scene, + const MinMax *min_max, + int digits) { ArcDcalcResult dcalc_result = gateDelay(drvr_pin, arc, in_slew, load_cap, - parasitic, load_pin_index_map, dcalc_ap); - GateTableModel *model = arc->gateTableModel(dcalc_ap); + parasitic, load_pin_index_map, scene, min_max); + GateTableModel *model = arc->gateTableModel(scene, min_max); float c_eff = 0.0; string result; const LibertyCell *drvr_cell = arc->to()->libertyCell(); @@ -1603,9 +1605,11 @@ DmpCeffDelayCalc::reportGateDelay(const Pin *drvr_pin, const Unit *cap_unit = units->capacitanceUnit(); const Unit *res_unit = units->resistanceUnit(); if (parasitic && dmp_alg_) { + Parasitics *parasitics = scene->parasitics(min_max); + c_eff = dmp_alg_->ceff(); float c2, rpi, c1; - parasitics_->piModel(parasitic, c2, rpi, c1); + parasitics->piModel(parasitic, c2, rpi, c1); result += "Pi model C2="; result += cap_unit->asString(c2, digits); result += " Rpi="; @@ -1621,7 +1625,8 @@ DmpCeffDelayCalc::reportGateDelay(const Pin *drvr_pin, if (model) { const Unit *time_unit = units->timeUnit(); float in_slew1 = delayAsFloat(in_slew); - result += model->reportGateDelay(pinPvt(drvr_pin, dcalc_ap), in_slew1, c_eff, + result += model->reportGateDelay(pinPvt(drvr_pin, scene, min_max), + in_slew1, c_eff, variables_->pocvEnabled(), digits); result += "Driver waveform slew = "; float drvr_slew = delayAsFloat(dcalc_result.drvrSlew()); @@ -1633,13 +1638,13 @@ DmpCeffDelayCalc::reportGateDelay(const Pin *drvr_pin, static double gateModelRd(const LibertyCell *cell, - const GateTableModel *gate_model, - const RiseFall *rf, - double in_slew, - double c2, - double c1, - const Pvt *pvt, - bool pocv_enabled) + const GateTableModel *gate_model, + const RiseFall *rf, + double in_slew, + double c2, + double c1, + const Pvt *pvt, + bool pocv_enabled) { float cap1 = c1 + c2; float cap2 = cap1 + 1e-15; @@ -1655,7 +1660,7 @@ gateModelRd(const LibertyCell *cell, void DmpCeffDelayCalc::gateDelaySlew(// Return values. double &delay, - double &slew) + double &slew) { dmp_alg_->gateDelaySlew(delay, slew); } diff --git a/dcalc/DmpCeff.hh b/dcalc/DmpCeff.hh index e8515151..fc3fbb2b 100644 --- a/dcalc/DmpCeff.hh +++ b/dcalc/DmpCeff.hh @@ -49,14 +49,16 @@ public: float load_cap, const Parasitic *parasitic, const LoadPinIndexMap &load_pin_index_map, - const DcalcAnalysisPt *dcalc_ap) override; + const Scene *scene, + const MinMax *min_max) override; std::string reportGateDelay(const Pin *drvr_pin, const TimingArc *arc, const Slew &in_slew, float load_cap, const Parasitic *parasitic, const LoadPinIndexMap &load_pin_index_map, - const DcalcAnalysisPt *dcalc_ap, + const Scene *scene, + const MinMax *min_max, int digits) override; void copyState(const StaState *sta) override; @@ -71,22 +73,23 @@ protected: Slew &load_slew) = 0; void gateDelaySlew(// Return values. double &delay, - double &slew); + double &slew); void loadDelaySlewElmore(const Pin *load_pin, double elmore, ArcDelay &delay, Slew &slew); // Select the appropriate special case Dartu/Menezes/Pileggi algorithm. void setCeffAlgorithm(const LibertyLibrary *library, - const LibertyCell *cell, - const Pvt *pvt, - const GateTableModel *gate_model, - const RiseFall *rf, - double in_slew, - double c2, - double rpi, - double c1); + const LibertyCell *cell, + const Pvt *pvt, + const GateTableModel *gate_model, + const RiseFall *rf, + double in_slew, + double c2, + double rpi, + double c1); + const Parasitics *parasitics_; static bool unsuppored_model_warned_; private: diff --git a/dcalc/DmpDelayCalc.cc b/dcalc/DmpDelayCalc.cc index 9081a65d..5e8b37b0 100644 --- a/dcalc/DmpDelayCalc.cc +++ b/dcalc/DmpDelayCalc.cc @@ -31,7 +31,6 @@ #include "Network.hh" #include "Sdc.hh" #include "Parasitics.hh" -#include "DcalcAnalysisPt.hh" #include "GraphDelayCalc.hh" #include "DmpCeff.hh" @@ -50,7 +49,8 @@ public: const RiseFall *rf, const Parasitic *parasitic, const LoadPinIndexMap &load_pin_index_map, - const DcalcAnalysisPt *dcalc_ap) override; + const Scene *scene, + const MinMax *min_max) override; protected: void loadDelaySlew(const Pin *load_pin, @@ -86,8 +86,10 @@ DmpCeffElmoreDelayCalc::inputPortDelay(const Pin *, const RiseFall *rf, const Parasitic *parasitic, const LoadPinIndexMap &load_pin_index_map, - const DcalcAnalysisPt *) + const Scene *scene, + const MinMax *min_max) { + Parasitics *parasitics = scene->parasitics(min_max); ArcDcalcResult dcalc_result(load_pin_index_map.size()); LibertyLibrary *drvr_library = network_->defaultLibertyLibrary(); for (auto [load_pin, load_idx] : load_pin_index_map) { @@ -96,7 +98,7 @@ DmpCeffElmoreDelayCalc::inputPortDelay(const Pin *, bool elmore_exists = false; float elmore = 0.0; if (parasitic) - parasitics_->findElmore(parasitic, load_pin, elmore, elmore_exists); + parasitics->findElmore(parasitic, load_pin, elmore, elmore_exists); if (elmore_exists) // Input port with no external driver. dspfWireDelaySlew(load_pin, rf, in_slew, elmore, wire_delay, load_slew); @@ -140,20 +142,23 @@ public: const char *name() const override { return "dmp_ceff_two_pole"; } Parasitic *findParasitic(const Pin *drvr_pin, const RiseFall *rf, - const DcalcAnalysisPt *dcalc_ap) override; + const Scene *scene, + const MinMax *min_max) override; ArcDcalcResult inputPortDelay(const Pin *port_pin, float in_slew, const RiseFall *rf, const Parasitic *parasitic, const LoadPinIndexMap &load_pin_index_map, - const DcalcAnalysisPt *dcalc_ap) override; + const Scene *scene, + const MinMax *min_max) override; ArcDcalcResult gateDelay(const Pin *drvr_pin, const TimingArc *arc, const Slew &in_slew, float load_cap, const Parasitic *parasitic, const LoadPinIndexMap &load_pin_index_map, - const DcalcAnalysisPt *dcalc_ap) override; + const Scene *scene, + const MinMax *min_max) override; private: void loadDelaySlew(const Pin *load_pin, @@ -166,20 +171,20 @@ private: Slew &load_slew) override; void loadDelay(double drvr_slew, Parasitic *pole_residue, - double p1, - double k1, - ArcDelay &wire_delay, - Slew &load_slew); + double p1, + double k1, + ArcDelay &wire_delay, + Slew &load_slew); float loadDelay(double vth, - double p1, - double p2, - double k1, - double k2, - double B, - double k1_p1_2, - double k2_p2_2, - double tt, - double y_tt); + double p1, + double p2, + double k1, + double k2, + double B, + double k1_p1_2, + double k2_p2_2, + double tt, + double y_tt); bool parasitic_is_pole_residue_; float vth_; @@ -212,43 +217,41 @@ DmpCeffTwoPoleDelayCalc::copy() Parasitic * DmpCeffTwoPoleDelayCalc::findParasitic(const Pin *drvr_pin, - const RiseFall *rf, - const DcalcAnalysisPt *dcalc_ap) + const RiseFall *rf, + const Scene *scene, + const MinMax *min_max) { Parasitic *parasitic = nullptr; - const Corner *corner = dcalc_ap->corner(); - // set_load net has precedence over parasitics. - if (sdc_->drvrPinHasWireCap(drvr_pin, corner) + const Sdc *sdc = scene->sdc(); + Parasitics *parasitics = scene->parasitics(min_max); + if (parasitics == nullptr + // set_load net has precedence over parasitics. || network_->direction(drvr_pin)->isInternal()) return nullptr; - const ParasiticAnalysisPt *parasitic_ap = dcalc_ap->parasiticAnalysisPt(); // Prefer PiPoleResidue. - parasitic = parasitics_->findPiPoleResidue(drvr_pin, rf, parasitic_ap); + parasitic = parasitics->findPiPoleResidue(drvr_pin, rf, min_max); if (parasitic) return parasitic; - parasitic = parasitics_->findPiElmore(drvr_pin, rf, parasitic_ap); + parasitic = parasitics->findPiElmore(drvr_pin, rf, min_max); if (parasitic) return parasitic; Parasitic *parasitic_network = - parasitics_->findParasiticNetwork(drvr_pin, parasitic_ap); + parasitics->findParasiticNetwork(drvr_pin); if (parasitic_network) { - parasitic = parasitics_->reduceToPiPoleResidue2(parasitic_network, drvr_pin, rf, - corner, - dcalc_ap->constraintMinMax(), - parasitic_ap); + parasitic = parasitics->reduceToPiPoleResidue2(parasitic_network, drvr_pin, rf, + scene, min_max); if (parasitic) return parasitic; } - const MinMax *cnst_min_max = dcalc_ap->constraintMinMax(); - Wireload *wireload = sdc_->wireload(cnst_min_max); + Wireload *wireload = sdc->wireload(min_max); if (wireload) { float pin_cap, wire_cap, fanout; bool has_wire_cap; - graph_delay_calc_->netCaps(drvr_pin, rf, dcalc_ap, pin_cap, wire_cap, + graph_delay_calc_->netCaps(drvr_pin, rf, scene, min_max, pin_cap, wire_cap, fanout, has_wire_cap); - parasitic = parasitics_->estimatePiElmore(drvr_pin, rf, wireload, - fanout, pin_cap, corner, - cnst_min_max); + parasitic = parasitics->estimatePiElmore(drvr_pin, rf, wireload, + fanout, pin_cap, + scene, min_max); } return parasitic; } @@ -259,21 +262,23 @@ DmpCeffTwoPoleDelayCalc::inputPortDelay(const Pin *, const RiseFall *rf, const Parasitic *parasitic, const LoadPinIndexMap &load_pin_index_map, - const DcalcAnalysisPt *) + const Scene *scene, + const MinMax *min_max) { + const Parasitics *parasitics = scene->parasitics(min_max); ArcDcalcResult dcalc_result(load_pin_index_map.size()); ArcDelay wire_delay = 0.0; Slew load_slew = in_slew; LibertyLibrary *drvr_library = network_->defaultLibertyLibrary(); for (const auto [load_pin, load_idx] : load_pin_index_map) { - if (parasitics_->isPiPoleResidue(parasitic)) { - const Parasitic *pole_residue = parasitics_->findPoleResidue(parasitic, load_pin); + if (parasitics->isPiPoleResidue(parasitic)) { + const Parasitic *pole_residue = parasitics->findPoleResidue(parasitic, load_pin); if (pole_residue) { - size_t pole_count = parasitics_->poleResidueCount(pole_residue); + size_t pole_count = parasitics->poleResidueCount(pole_residue); if (pole_count >= 1) { ComplexFloat pole1, residue1; // Find the 1st (elmore) pole. - parasitics_->poleResidue(pole_residue, 0, pole1, residue1); + parasitics->poleResidue(pole_residue, 0, pole1, residue1); if (pole1.imag() == 0.0 && residue1.imag() == 0.0) { float p1 = pole1.real(); @@ -297,8 +302,10 @@ DmpCeffTwoPoleDelayCalc::gateDelay(const Pin *drvr_pin, float load_cap, const Parasitic *parasitic, const LoadPinIndexMap &load_pin_index_map, - const DcalcAnalysisPt *dcalc_ap) + const Scene *scene, + const MinMax *min_max) { + parasitics_ = scene->parasitics(min_max); const LibertyLibrary *drvr_library = arc->to()->libertyLibrary(); const RiseFall *rf = arc->toEdge()->asRiseFall(); vth_ = drvr_library->outputThreshold(rf); @@ -306,7 +313,7 @@ DmpCeffTwoPoleDelayCalc::gateDelay(const Pin *drvr_pin, vh_ = drvr_library->slewUpperThreshold(rf); slew_derate_ = drvr_library->slewDerateFromLibrary(); return DmpCeffDelayCalc::gateDelay(drvr_pin, arc, in_slew, load_cap, parasitic, - load_pin_index_map, dcalc_ap) ; + load_pin_index_map, scene, min_max) ; } void @@ -333,9 +340,9 @@ DmpCeffTwoPoleDelayCalc::loadDelaySlew(const Pin *load_pin, // Find the 1st (elmore) pole. parasitics_->poleResidue(pole_residue, 0, pole1, residue1); if (pole1.imag() == 0.0 - && residue1.imag() == 0.0) { - float p1 = pole1.real(); - float k1 = residue1.real(); + && residue1.imag() == 0.0) { + float p1 = pole1.real(); + float k1 = residue1.real(); if (pole_count >= 2) loadDelay(drvr_slew, pole_residue, p1, k1, wire_delay, load_slew); else { @@ -352,11 +359,11 @@ DmpCeffTwoPoleDelayCalc::loadDelaySlew(const Pin *load_pin, void DmpCeffTwoPoleDelayCalc::loadDelay(double drvr_slew, Parasitic *pole_residue, - double p1, + double p1, double k1, - // Return values. + // Return values. ArcDelay &wire_delay, - Slew &load_slew) + Slew &load_slew) { ComplexFloat pole2, residue2; parasitics_->poleResidue(pole_residue, 1, pole2, residue2); @@ -371,7 +378,7 @@ DmpCeffTwoPoleDelayCalc::loadDelay(double drvr_slew, // Convert tt to 0:1 range. float tt = delayAsFloat(drvr_slew) * slew_derate_ / (vh_ - vl_); double y_tt = (tt - B + k1_p1_2 * exp(-p1 * tt) - + k2_p2_2 * exp(-p2 * tt)) / tt; + + k2_p2_2 * exp(-p2 * tt)) / tt; wire_delay = loadDelay(vth_, p1, p2, k1, k2, B, k1_p1_2, k2_p2_2, tt, y_tt) - tt * vth_; @@ -383,15 +390,15 @@ DmpCeffTwoPoleDelayCalc::loadDelay(double drvr_slew, float DmpCeffTwoPoleDelayCalc::loadDelay(double vth, - double p1, - double p2, - double k1, - double k2, - double B, - double k1_p1_2, - double k2_p2_2, - double tt, - double y_tt) + double p1, + double p2, + double k1, + double k2, + double B, + double k1_p1_2, + double k2_p2_2, + double tt, + double y_tt) { if (y_tt < vth) { // t1 > tt @@ -403,9 +410,9 @@ DmpCeffTwoPoleDelayCalc::loadDelay(double vth, double exp_p1_t1_tt = exp(-p1 * (t1 - tt)); double exp_p2_t1_tt = exp(-p2 * (t1 - tt)); double y_t1 = (tt - k1_p1_2 * (exp_p1_t1_tt - exp_p1_t1) - - k2_p2_2 * (exp_p2_t1_tt - exp_p2_t1)) / tt; + - k2_p2_2 * (exp_p2_t1_tt - exp_p2_t1)) / tt; double yp_t1 = (k1 / p1 * (exp_p1_t1_tt - exp_p1_t1) - - k2 / p2 * (exp_p2_t1_tt - exp_p2_t1)) / tt; + - k2 / p2 * (exp_p2_t1_tt - exp_p2_t1)) / tt; double delay = t1 - (y_t1 - vth) / yp_t1; return static_cast(delay); } @@ -417,9 +424,9 @@ DmpCeffTwoPoleDelayCalc::loadDelay(double vth, double exp_p1_t1 = exp(-p1 * t1); double exp_p2_t1 = exp(-p2 * t1); double y_t1 = (t1 - B + k1_p1_2 * exp_p1_t1 - + k2_p2_2 * exp_p1_t1) / tt; + + k2_p2_2 * exp_p1_t1) / tt; double yp_t1 = (1 - k1 / p1 * exp_p1_t1 - - k2 / p2 * exp_p2_t1) / tt; + - k2 / p2 * exp_p2_t1) / tt; double delay = t1 - (y_t1 - vth) / yp_t1; return static_cast(delay); } diff --git a/dcalc/FindRoot.cc b/dcalc/FindRoot.cc index ded4bec0..b74d7d16 100644 --- a/dcalc/FindRoot.cc +++ b/dcalc/FindRoot.cc @@ -32,10 +32,10 @@ using std::abs; double findRoot(FindRootFunc func, - double x1, - double x2, - double x_tol, - int max_iter, + double x1, + double x2, + double x_tol, + int max_iter, // Return value. bool &fail) { @@ -47,12 +47,12 @@ findRoot(FindRootFunc func, double findRoot(FindRootFunc func, - double x1, - double y1, + double x1, + double y1, double x2, - double y2, + double y2, double x_tol, - int max_iter, + int max_iter, // Return value. bool &fail) { @@ -83,8 +83,8 @@ findRoot(FindRootFunc func, for (int iter = 0; iter < max_iter; iter++) { // Newton/raphson out of range. if ((((root - x2) * dy - y) * ((root - x1) * dy - y) > 0.0) - // Not decreasing fast enough. - || (abs(2.0 * y) > abs(dx_prev * dy))) { + // Not decreasing fast enough. + || (abs(2.0 * y) > abs(dx_prev * dy))) { // Bisect x1/x2 interval. dx_prev = dx; dx = (x2 - x1) * 0.5; diff --git a/dcalc/FindRoot.hh b/dcalc/FindRoot.hh index e4d4d854..7224671d 100644 --- a/dcalc/FindRoot.hh +++ b/dcalc/FindRoot.hh @@ -28,28 +28,28 @@ namespace sta { -typedef const std::function FindRootFunc; +using FindRootFunc = const std::function; double findRoot(FindRootFunc func, - double x1, - double x2, - double x_tol, - int max_iter, + double x1, + double x2, + double x_tol, + int max_iter, // Return value. bool &fail); double findRoot(FindRootFunc func, - double x1, - double y1, + double x1, + double y1, double x2, - double y2, - double x_tol, - int max_iter, + double y2, + double x_tol, + int max_iter, // Return value. bool &fail); diff --git a/dcalc/GraphDelayCalc.cc b/dcalc/GraphDelayCalc.cc index 6fcaa870..f75883c9 100644 --- a/dcalc/GraphDelayCalc.cc +++ b/dcalc/GraphDelayCalc.cc @@ -24,6 +24,9 @@ #include "GraphDelayCalc.hh" +#include + +#include "ContainerHelpers.hh" #include "Debug.hh" #include "Stats.hh" #include "MinMax.hh" @@ -35,17 +38,18 @@ #include "Network.hh" #include "InputDrive.hh" #include "Sdc.hh" +#include "Mode.hh" #include "Graph.hh" #include "Parasitics.hh" #include "search/Levelize.hh" -#include "Corner.hh" +#include "Scene.hh" #include "SearchPred.hh" #include "Bfs.hh" #include "ArcDelayCalc.hh" -#include "DcalcAnalysisPt.hh" #include "NetCaps.hh" #include "ClkNetwork.hh" #include "Variables.hh" +#include "search/Latches.hh" namespace sta { @@ -59,16 +63,94 @@ static bool isLeafDriver(const Pin *pin, const Network *network); +//////////////////////////////////////////////////////////////// + +class DcalcPred : public SearchPred +{ +public: + DcalcPred(const StaState *sta); + bool searchFrom(const Vertex *from_vertex, + const Mode *mode) const override; + bool searchThru(Edge *edge, + const Mode *mode) const override; + bool searchTo(const Vertex *to_vertex, + const Mode *mode) const override; +}; + +DcalcPred::DcalcPred(const StaState *sta) : + SearchPred(sta) +{ +} + +bool +DcalcPred::searchFrom(const Vertex *from_vertex, + const Mode *mode) const +{ + const Pin *from_pin = from_vertex->pin(); + const Sdc *sdc = mode->sdc(); + const Network *network = sta_->network(); + Net *net = network->net(from_pin); + return !(sdc->isDisabledConstraint(from_pin) + || (net && (network->isPower(net) + || network->isGround(net)))); +} + +bool +DcalcPred::searchThru(Edge *edge, + const Mode *mode) const +{ + const Sdc *sdc = mode->sdc(); + const Variables *variables = sta_->variables(); + const TimingRole *role = edge->role(); + return !(role->isTimingCheck() + || (role == TimingRole::regSetClr() + && !variables->presetClrArcsEnabled()) + || edge->isDisabledLoop() + || sdc->isDisabledConstraint(edge) + || sdc->isDisabledCondDefault(edge) + || (edge->isBidirectInstPath() + && !variables->bidirectInstPathsEnabled())); +} + +bool +DcalcPred::searchTo(const Vertex *, + const Mode *) const +{ + return true; +} + +class DcalcNonLatchPred : public DcalcPred +{ +public: + DcalcNonLatchPred(const StaState *sta); + bool searchThru(Edge *edge, + const Mode *mode) const override; +}; + +DcalcNonLatchPred::DcalcNonLatchPred(const StaState *sta) : + DcalcPred(sta) +{ +} + +bool +DcalcNonLatchPred::searchThru(Edge *edge, + const Mode *mode) const +{ + return DcalcPred::searchThru(edge, mode) + && !edge->role()->isLatchDtoQ(); +} + +//////////////////////////////////////////////////////////////// + GraphDelayCalc::GraphDelayCalc(StaState *sta) : StaState(sta), observer_(nullptr), delays_seeded_(false), incremental_(false), delays_exist_(false), - invalid_delays_(new VertexSet(graph_)), - search_pred_(new SearchPred1(sta)), - search_non_latch_pred_(new SearchPredNonLatch2(sta)), - clk_pred_(new ClkTreeSearchPred(sta)), + invalid_delays_(makeVertexSet(this)), + search_pred_(new DcalcPred(sta)), + search_non_latch_pred_(new DcalcNonLatchPred(sta)), iter_(new BfsFwdIterator(BfsIndex::dcalc, search_non_latch_pred_, sta)), incremental_delay_tolerance_(0.0) { @@ -77,9 +159,7 @@ GraphDelayCalc::GraphDelayCalc(StaState *sta) : GraphDelayCalc::~GraphDelayCalc() { delete search_pred_; - delete invalid_delays_; delete search_non_latch_pred_; - delete clk_pred_; delete iter_; deleteMultiDrvrNets(); delete observer_; @@ -88,16 +168,14 @@ GraphDelayCalc::~GraphDelayCalc() void GraphDelayCalc::deleteMultiDrvrNets() { - Set drvr_nets; - MultiDrvrNetMap::Iterator multi_iter(multi_drvr_net_map_); - while (multi_iter.hasNext()) { - MultiDrvrNet *multi_drvr = multi_iter.next(); + std::set drvr_nets; + for (auto [vertex, multi_drvr] : multi_drvr_net_map_) { // Multiple drvr pins point to the same drvr PinSet, // so collect them into a set. drvr_nets.insert(multi_drvr); } multi_drvr_net_map_.clear(); - drvr_nets.deleteContents(); + deleteContents(drvr_nets); } void @@ -106,6 +184,8 @@ GraphDelayCalc::copyState(const StaState *sta) StaState::copyState(sta); // Notify sub-components. iter_->copyState(sta); + search_pred_->copyState(sta); + search_non_latch_pred_->copyState(sta); } void @@ -143,7 +223,7 @@ GraphDelayCalc::delaysInvalid() incremental_ = false; iter_->clear(); // No need to keep track of incremental updates any more. - invalid_delays_->clear(); + invalid_delays_.clear(); invalid_check_edges_.clear(); invalid_latch_edges_.clear(); } @@ -176,11 +256,11 @@ GraphDelayCalc::delayInvalid(Vertex *vertex) debugPrint(debug_, "delay_calc", 2, "delay invalid %s", vertex->to_string(this).c_str()); if (graph_ && incremental_) { - invalid_delays_->insert(vertex); + invalid_delays_.insert(vertex); // Invalidate driver that triggers dcalc for multi-driver nets. MultiDrvrNet *multi_drvr = multiDrvrNet(vertex); if (multi_drvr) - invalid_delays_->insert(multi_drvr->dcalcDrvr()); + invalid_delays_.insert(multi_drvr->dcalcDrvr()); } } @@ -202,7 +282,7 @@ GraphDelayCalc::deleteVertexBefore(Vertex *vertex) { iter_->deleteVertexBefore(vertex); if (incremental_) - invalid_delays_->erase(vertex); + invalid_delays_.erase(vertex); MultiDrvrNet *multi_drvr = multiDrvrNet(vertex); if (multi_drvr) { // Don't bother incrementally updating MultiDrvrNet. @@ -298,15 +378,9 @@ GraphDelayCalc::findDelays(Level level) void GraphDelayCalc::seedInvalidDelays() { - for (Vertex *vertex : *invalid_delays_) { - if (vertex->isRoot()) - seedRootSlew(vertex, arc_delay_calc_); - else { - if (search_non_latch_pred_->searchFrom(vertex)) + for (Vertex *vertex : invalid_delays_) iter_->enqueue(vertex); - } - } - invalid_delays_->clear(); + invalid_delays_.clear(); } void @@ -334,32 +408,34 @@ GraphDelayCalc::seedDrvrSlew(Vertex *drvr_vertex, const Pin *drvr_pin = drvr_vertex->pin(); debugPrint(debug_, "delay_calc", 2, "seed driver slew %s", drvr_vertex->to_string(this).c_str()); - InputDrive *drive = 0; + for (const Scene *scene : scenes_) { + const Sdc *sdc = scene->sdc(); + for (const MinMax *min_max : MinMax::range()) { + for (const RiseFall *rf : RiseFall::range()) { + InputDrive *drive = nullptr; if (network_->isTopLevelPort(drvr_pin)) { Port *port = network_->port(drvr_pin); - drive = sdc_->findInputDrive(port); + drive = sdc->findInputDrive(port); } - for (const RiseFall *rf : RiseFall::range()) { - for (const DcalcAnalysisPt *dcalc_ap : corners_->dcalcAnalysisPts()) { if (drive) { - const MinMax *cnst_min_max = dcalc_ap->constraintMinMax(); const LibertyCell *drvr_cell; const LibertyPort *from_port, *to_port; float *from_slews; - drive->driveCell(rf, cnst_min_max, drvr_cell, from_port, + drive->driveCell(rf, min_max, drvr_cell, from_port, from_slews, to_port); if (drvr_cell) { if (from_port == nullptr) from_port = driveCellDefaultFromPort(drvr_cell, to_port); findInputDriverDelay(drvr_cell, drvr_pin, drvr_vertex, rf, - from_port, from_slews, to_port, dcalc_ap); + from_port, from_slews, to_port, scene, min_max); } else - seedNoDrvrCellSlew(drvr_vertex, drvr_pin, rf, drive, dcalc_ap, + seedNoDrvrCellSlew(drvr_vertex, drvr_pin, rf, drive, scene, min_max, arc_delay_calc); } else - seedNoDrvrSlew(drvr_vertex, drvr_pin, rf, dcalc_ap, arc_delay_calc); + seedNoDrvrSlew(drvr_vertex, drvr_pin, rf, scene, min_max, arc_delay_calc); + } } } } @@ -369,15 +445,15 @@ GraphDelayCalc::seedNoDrvrCellSlew(Vertex *drvr_vertex, const Pin *drvr_pin, const RiseFall *rf, const InputDrive *drive, - const DcalcAnalysisPt *dcalc_ap, + const Scene *scene, + const MinMax *min_max, ArcDelayCalc *arc_delay_calc) { - DcalcAPIndex ap_index = dcalc_ap->index(); - const MinMax *cnst_min_max = dcalc_ap->constraintMinMax(); + DcalcAPIndex ap_index = scene->dcalcAnalysisPtIndex(min_max); Slew slew = default_slew; float drive_slew; bool exists; - drive->slew(rf, cnst_min_max, drive_slew, exists); + drive->slew(rf, min_max, drive_slew, exists); if (exists) slew = drive_slew; else { @@ -390,24 +466,23 @@ GraphDelayCalc::seedNoDrvrCellSlew(Vertex *drvr_vertex, } Delay drive_delay = delay_zero; float drive_res; - drive->driveResistance(rf, cnst_min_max, drive_res, exists); + drive->driveResistance(rf, min_max, drive_res, exists); const Parasitic *parasitic; float load_cap; - parasiticLoad(drvr_pin, rf, dcalc_ap, nullptr, arc_delay_calc, + parasiticLoad(drvr_pin, rf, scene, min_max, nullptr, arc_delay_calc, load_cap, parasitic); if (exists) { drive_delay = load_cap * drive_res; slew = load_cap * drive_res; } - const MinMax *slew_min_max = dcalc_ap->slewMinMax(); - if (!drvr_vertex->slewAnnotated(rf, slew_min_max)) + if (!drvr_vertex->slewAnnotated(rf, min_max)) graph_->setSlew(drvr_vertex, rf, ap_index, slew); LoadPinIndexMap load_pin_index_map = makeLoadPinIndexMap(drvr_vertex); ArcDcalcResult dcalc_result = arc_delay_calc->inputPortDelay(drvr_pin, delayAsFloat(slew), rf, parasitic, - load_pin_index_map, dcalc_ap); + load_pin_index_map, scene, min_max); annotateLoadDelays(drvr_vertex, rf, dcalc_result, load_pin_index_map, - drive_delay, false, dcalc_ap); + drive_delay, false, scene, min_max); arc_delay_calc->finishDrvrPin(); } @@ -426,11 +501,11 @@ void GraphDelayCalc::seedNoDrvrSlew(Vertex *drvr_vertex, const Pin *drvr_pin, const RiseFall *rf, - const DcalcAnalysisPt *dcalc_ap, + const Scene *scene, + const MinMax *min_max, ArcDelayCalc *arc_delay_calc) { - const MinMax *slew_min_max = dcalc_ap->slewMinMax(); - DcalcAPIndex ap_index = dcalc_ap->index(); + DcalcAPIndex ap_index = scene->dcalcAnalysisPtIndex(min_max); Slew slew(default_slew); // Top level bidirect driver uses load slew unless // bidirect instance paths are disabled. @@ -438,15 +513,15 @@ GraphDelayCalc::seedNoDrvrSlew(Vertex *drvr_vertex, Vertex *load_vertex = graph_->pinLoadVertex(drvr_pin); slew = graph_->slew(load_vertex, rf, ap_index); } - if (!drvr_vertex->slewAnnotated(rf, slew_min_max)) + if (!drvr_vertex->slewAnnotated(rf, min_max)) graph_->setSlew(drvr_vertex, rf, ap_index, slew); - Parasitic *parasitic = arc_delay_calc->findParasitic(drvr_pin, rf, dcalc_ap); + Parasitic *parasitic = arc_delay_calc->findParasitic(drvr_pin, rf, scene, min_max); LoadPinIndexMap load_pin_index_map = makeLoadPinIndexMap(drvr_vertex); ArcDcalcResult dcalc_result = arc_delay_calc->inputPortDelay(drvr_pin, delayAsFloat(slew), rf, parasitic, - load_pin_index_map, dcalc_ap); + load_pin_index_map, scene, min_max); annotateLoadDelays(drvr_vertex, rf, dcalc_result, load_pin_index_map, delay_zero, - false, dcalc_ap); + false, scene, min_max); arc_delay_calc->finishDrvrPin(); } @@ -456,28 +531,28 @@ GraphDelayCalc::seedLoadSlew(Vertex *vertex) const Pin *pin = vertex->pin(); debugPrint(debug_, "delay_calc", 2, "seed load slew %s", vertex->to_string(this).c_str()); - ClockSet *clks = sdc_->findLeafPinClocks(pin); initSlew(vertex); + for (const Scene *scene : scenes_) { + const Sdc *sdc = scene->sdc(); + for (const MinMax *min_max : MinMax::range()) { + DcalcAPIndex ap_index = scene->dcalcAnalysisPtIndex(min_max); for (const RiseFall *rf : RiseFall::range()) { - for (const DcalcAnalysisPt *dcalc_ap : corners_->dcalcAnalysisPts()) { - const MinMax *slew_min_max = dcalc_ap->slewMinMax(); - if (!vertex->slewAnnotated(rf, slew_min_max)) { + ClockSet *clks = sdc->findLeafPinClocks(pin); + if (!vertex->slewAnnotated(rf, min_max)) { float slew = 0.0; if (clks) { - slew = slew_min_max->initValue(); - ClockSet::Iterator clk_iter(clks); - while (clk_iter.hasNext()) { - Clock *clk = clk_iter.next(); - float clk_slew = clk->slew(rf, slew_min_max); - if (slew_min_max->compare(clk_slew, slew)) + slew = min_max->initValue(); + for (Clock *clk : *clks) { + float clk_slew = clk->slew(rf, min_max); + if (min_max->compare(clk_slew, slew)) slew = clk_slew; } } - DcalcAPIndex ap_index = dcalc_ap->index(); graph_->setSlew(vertex, rf, ap_index, slew); } } } + } } // If a driving cell does not specify a -from_pin, the first port @@ -526,7 +601,8 @@ GraphDelayCalc::findInputDriverDelay(const LibertyCell *drvr_cell, const LibertyPort *from_port, float *from_slews, const LibertyPort *to_port, - const DcalcAnalysisPt *dcalc_ap) + const Scene *scene, + const MinMax *min_max) { debugPrint(debug_, "delay_calc", 2, " driver cell %s %s", drvr_cell->name(), @@ -535,7 +611,7 @@ GraphDelayCalc::findInputDriverDelay(const LibertyCell *drvr_cell, for (TimingArc *arc : arc_set->arcs()) { if (arc->toEdge()->asRiseFall() == rf) { float from_slew = from_slews[arc->fromEdge()->index()]; - findInputArcDelay(drvr_pin, drvr_vertex, arc, from_slew, dcalc_ap); + findInputArcDelay(drvr_pin, drvr_vertex, arc, from_slew, scene, min_max); } } } @@ -550,7 +626,8 @@ GraphDelayCalc::findInputArcDelay(const Pin *drvr_pin, Vertex *drvr_vertex, const TimingArc *arc, float from_slew, - const DcalcAnalysisPt *dcalc_ap) + const Scene *scene, + const MinMax *min_max) { debugPrint(debug_, "delay_calc", 3, " %s %s -> %s %s (%s)", arc->from()->name(), @@ -560,23 +637,24 @@ GraphDelayCalc::findInputArcDelay(const Pin *drvr_pin, arc->role()->to_string().c_str()); const RiseFall *drvr_rf = arc->toEdge()->asRiseFall(); if (drvr_rf) { - DcalcAPIndex ap_index = dcalc_ap->index(); + DcalcAPIndex ap_index = scene->dcalcAnalysisPtIndex(min_max); + const Parasitic *parasitic; float load_cap; - parasiticLoad(drvr_pin, drvr_rf, dcalc_ap, nullptr, arc_delay_calc_, + parasiticLoad(drvr_pin, drvr_rf, scene, min_max, nullptr, arc_delay_calc_, load_cap, parasitic); LoadPinIndexMap load_pin_index_map = makeLoadPinIndexMap(drvr_vertex); ArcDcalcResult intrinsic_result = arc_delay_calc_->gateDelay(drvr_pin, arc, Slew(from_slew), 0.0, nullptr, - load_pin_index_map, dcalc_ap); + load_pin_index_map, scene, min_max); ArcDelay intrinsic_delay = intrinsic_result.gateDelay(); ArcDcalcResult gate_result = arc_delay_calc_->gateDelay(drvr_pin, arc, Slew(from_slew), load_cap, parasitic, load_pin_index_map, - dcalc_ap); + scene, min_max); ArcDelay gate_delay = gate_result.gateDelay(); Slew gate_slew = gate_result.drvrSlew(); @@ -588,7 +666,7 @@ GraphDelayCalc::findInputArcDelay(const Pin *drvr_pin, delayAsString(gate_slew, this)); graph_->setSlew(drvr_vertex, drvr_rf, ap_index, gate_slew); annotateLoadDelays(drvr_vertex, drvr_rf, gate_result, load_pin_index_map, - load_delay, false, dcalc_ap); + load_delay, false, scene, min_max); arc_delay_calc_->finishDrvrPin(); } } @@ -608,11 +686,8 @@ GraphDelayCalc::findVertexDelay(Vertex *vertex, debugPrint(debug_, "delay_calc", 2, "find delays %s (%s)", vertex->to_string(this).c_str(), network_->cellName(network_->instance(pin))); - if (vertex->isRoot()) { + if (vertex->isRoot()) seedRootSlew(vertex, arc_delay_calc); - if (propagate) - iter_->enqueueAdjacentVertices(vertex); - } else { if (network_->isLeaf(pin)) { if (vertex->isDriver(network_)) { @@ -793,7 +868,7 @@ isLeafDriver(const Pin *pin, MultiDrvrNet * GraphDelayCalc::multiDrvrNet(const Vertex *drvr_vertex) const { - return multi_drvr_net_map_.findKey(drvr_vertex); + return findKey(multi_drvr_net_map_, drvr_vertex); } MultiDrvrNet * @@ -827,7 +902,7 @@ GraphDelayCalc::makeMultiDrvrNet(Vertex *drvr_vertex) } } multi_drvr->setDcalcDrvr(max_drvr); - multi_drvr->findCaps(sdc_); + multi_drvr->findCaps(this); return multi_drvr; } report_->critical(1101, "mult_drvr missing load."); @@ -842,17 +917,19 @@ GraphDelayCalc::initLoadSlews(Vertex *drvr_vertex) Edge *wire_edge = edge_iter.next(); if (wire_edge->isWire()) { Vertex *load_vertex = wire_edge->to(graph_); - for (const DcalcAnalysisPt *dcalc_ap : corners_->dcalcAnalysisPts()) { - const MinMax *slew_min_max = dcalc_ap->slewMinMax(); - Slew slew_init_value(slew_min_max->initValue()); - DcalcAPIndex ap_index = dcalc_ap->index(); + + for (Scene *scene : scenes_) { + for (const MinMax *min_max : MinMax::range()) { + DcalcAPIndex ap_index = scene->dcalcAnalysisPtIndex(min_max); + Slew slew_init_value(min_max->initValue()); for (const RiseFall *rf : RiseFall::range()) { - if (!load_vertex->slewAnnotated(rf, slew_min_max)) + if (!load_vertex->slewAnnotated(rf, min_max)) graph_->setSlew(load_vertex, rf, ap_index, slew_init_value); } } } } + } } bool @@ -868,11 +945,7 @@ GraphDelayCalc::findDriverDelays1(Vertex *drvr_vertex, VertexInEdgeIterator edge_iter(drvr_vertex, graph_); while (edge_iter.hasNext()) { Edge *edge = edge_iter.next(); - Vertex *from_vertex = edge->from(graph_); - // Don't let disabled edges set slews that influence downstream delays. - if (search_pred_->searchFrom(from_vertex) - && search_pred_->searchThru(edge) - && !edge->role()->isLatchDtoQ()) + if (!edge->role()->isLatchDtoQ()) delay_changed |= findDriverEdgeDelays(drvr_vertex, multi_drvr, edge, arc_delay_calc, load_pin_index_map, delay_exists); @@ -891,14 +964,15 @@ GraphDelayCalc::findDriverDelays1(Vertex *drvr_vertex, void GraphDelayCalc::initRootSlews(Vertex *vertex) { - for (const DcalcAnalysisPt *dcalc_ap : corners_->dcalcAnalysisPts()) { - const MinMax *slew_min_max = dcalc_ap->slewMinMax(); - DcalcAPIndex ap_index = dcalc_ap->index(); + for (Scene *scene : scenes_) { + for (const MinMax *min_max : MinMax::range()) { + DcalcAPIndex ap_index = scene->dcalcAnalysisPtIndex(min_max); for (const RiseFall *rf : RiseFall::range()) { - if (!vertex->slewAnnotated(rf, slew_min_max)) + if (!vertex->slewAnnotated(rf, min_max)) graph_->setSlew(vertex, rf, ap_index, default_slew); } } + } } void @@ -930,13 +1004,20 @@ GraphDelayCalc::findDriverEdgeDelays(Vertex *drvr_vertex, Vertex *from_vertex = edge->from(graph_); const TimingArcSet *arc_set = edge->timingArcSet(); bool delay_changed = false; - for (const DcalcAnalysisPt *dcalc_ap : corners_->dcalcAnalysisPts()) { + + for (Scene *scene : scenes_) { + const Mode *mode = scene->mode(); + if (search_pred_->searchFrom(from_vertex, mode) + && search_pred_->searchThru(edge, mode)) { + for (const MinMax *min_max : MinMax::range()) { for (const TimingArc *arc : arc_set->arcs()) { delay_changed |= findDriverArcDelays(drvr_vertex, multi_drvr, edge, arc, - dcalc_ap, arc_delay_calc, + scene, min_max, arc_delay_calc, load_pin_index_map); delay_exists[arc->toEdge()->asRiseFall()->index()] = true; } + } + } } if (delay_changed && observer_) { observer_->delayChangedFrom(from_vertex); @@ -950,12 +1031,13 @@ void GraphDelayCalc::findDriverArcDelays(Vertex *drvr_vertex, Edge *edge, const TimingArc *arc, - const DcalcAnalysisPt *dcalc_ap, + const Scene *scene, + const MinMax *min_max, ArcDelayCalc *arc_delay_calc) { MultiDrvrNet *multi_drvr = multiDrvrNet(drvr_vertex); LoadPinIndexMap load_pin_index_map = makeLoadPinIndexMap(drvr_vertex); - findDriverArcDelays(drvr_vertex, multi_drvr, edge, arc, dcalc_ap, + findDriverArcDelays(drvr_vertex, multi_drvr, edge, arc, scene, min_max, arc_delay_calc, load_pin_index_map); } @@ -964,7 +1046,8 @@ GraphDelayCalc::findDriverArcDelays(Vertex *drvr_vertex, const MultiDrvrNet *multi_drvr, Edge *edge, const TimingArc *arc, - const DcalcAnalysisPt *dcalc_ap, + const Scene *scene, + const MinMax *min_max, ArcDelayCalc *arc_delay_calc, LoadPinIndexMap &load_pin_index_map) { @@ -975,33 +1058,33 @@ GraphDelayCalc::findDriverArcDelays(Vertex *drvr_vertex, const Pin *drvr_pin = drvr_vertex->pin(); const Parasitic *parasitic; float load_cap; - parasiticLoad(drvr_pin, drvr_rf, dcalc_ap, multi_drvr, arc_delay_calc, + parasiticLoad(drvr_pin, drvr_rf, scene, min_max, multi_drvr, arc_delay_calc, load_cap, parasitic); if (multi_drvr && multi_drvr->parallelGates(network_)) { ArcDcalcArgSeq dcalc_args = makeArcDcalcArgs(drvr_vertex, multi_drvr, - edge, arc, dcalc_ap, + edge, arc, scene, min_max, arc_delay_calc); ArcDcalcResultSeq dcalc_results = - arc_delay_calc->gateDelays(dcalc_args, load_pin_index_map, dcalc_ap); + arc_delay_calc->gateDelays(dcalc_args, load_pin_index_map, scene, min_max); for (size_t drvr_idx = 0; drvr_idx < dcalc_args.size(); drvr_idx++) { ArcDcalcArg &dcalc_arg = dcalc_args[drvr_idx]; ArcDcalcResult &dcalc_result = dcalc_results[drvr_idx]; delay_changed |= annotateDelaysSlews(dcalc_arg.edge(), dcalc_arg.arc(), dcalc_result, load_pin_index_map, - dcalc_ap); + scene, min_max); } } else { Vertex *from_vertex = edge->from(graph_); - const Slew in_slew = edgeFromSlew(from_vertex, from_rf, edge, dcalc_ap); + const Slew in_slew = edgeFromSlew(from_vertex, from_rf, edge, scene, min_max); ArcDcalcResult dcalc_result = arc_delay_calc->gateDelay(drvr_pin, arc, in_slew, load_cap, parasitic, load_pin_index_map, - dcalc_ap); + scene, min_max); delay_changed |= annotateDelaysSlews(edge, arc, dcalc_result, - load_pin_index_map, dcalc_ap); + load_pin_index_map, scene, min_max); } arc_delay_calc->finishDrvrPin(); } @@ -1013,7 +1096,8 @@ GraphDelayCalc::makeArcDcalcArgs(Vertex *drvr_vertex, const MultiDrvrNet *multi_drvr, Edge *edge, const TimingArc *arc, - const DcalcAnalysisPt *dcalc_ap, + const Scene *scene, + const MinMax *min_max, ArcDelayCalc *arc_delay_calc) { ArcDcalcArgSeq dcalc_args; @@ -1032,11 +1116,13 @@ GraphDelayCalc::makeArcDcalcArgs(Vertex *drvr_vertex, const Pin *from_pin = from_vertex->pin(); const RiseFall *from_rf = arc1->fromEdge()->asRiseFall(); const RiseFall *drvr_rf = arc1->toEdge()->asRiseFall(); - const Slew in_slew = edgeFromSlew(from_vertex, from_rf, edge1, dcalc_ap); + Slew in_slew = edgeFromSlew(from_vertex, from_rf, edge1, scene, min_max); + in_slew = edgeFromSlew(from_vertex, from_rf, edge1, scene, min_max); + const Pin *drvr_pin1 = drvr_vertex1->pin(); float load_cap; const Parasitic *parasitic; - parasiticLoad(drvr_pin1, drvr_rf, dcalc_ap, multi_drvr, arc_delay_calc, + parasiticLoad(drvr_pin1, drvr_rf, scene, min_max, multi_drvr, arc_delay_calc, load_cap, parasitic); dcalc_args.emplace_back(from_pin, drvr_pin1, edge1, arc1, in_slew, load_cap, parasitic); @@ -1062,7 +1148,8 @@ GraphDelayCalc::findParallelEdge(Vertex *vertex, VertexInEdgeIterator edge_iter(vertex, graph_); while (edge_iter.hasNext()) { edge = edge_iter.next(); - if (edge->timingArcSet() == arc->set()) + if (edge->timingArcSet() == arc->set() + && !edge->isBidirectInstPath()) return; } } @@ -1072,7 +1159,8 @@ GraphDelayCalc::findParallelEdge(Vertex *vertex, edge = edge_iter.next(); for (TimingArc *arc1 : edge->timingArcSet()->arcs()) { if (arc1->fromEdge() == drvr_arc->fromEdge() - && arc1->toEdge() == drvr_arc->toEdge()) { + && arc1->toEdge() == drvr_arc->toEdge() + && !edge->isBidirectInstPath()) { arc = arc1; return; } @@ -1088,17 +1176,18 @@ GraphDelayCalc::annotateDelaysSlews(Edge *edge, const TimingArc *arc, ArcDcalcResult &dcalc_result, LoadPinIndexMap &load_pin_index_map, - const DcalcAnalysisPt *dcalc_ap) + const Scene *scene, + const MinMax *min_max) { bool delay_changed = annotateDelaySlew(edge, arc, dcalc_result.gateDelay(), - dcalc_result.drvrSlew(), dcalc_ap); + dcalc_result.drvrSlew(), scene, min_max); if (!edge->role()->isLatchDtoQ()) { Vertex *drvr_vertex = edge->to(graph_); delay_changed |= annotateLoadDelays(drvr_vertex, arc->toEdge()->asRiseFall(), dcalc_result, load_pin_index_map, delay_zero, true, - dcalc_ap); + scene, min_max); } return delay_changed; } @@ -1111,30 +1200,30 @@ GraphDelayCalc::annotateDelaySlew(Edge *edge, const TimingArc *arc, ArcDelay &gate_delay, Slew &gate_slew, - const DcalcAnalysisPt *dcalc_ap) + const Scene *scene, + const MinMax *min_max) { - bool delay_changed = false; - DcalcAPIndex ap_index = dcalc_ap->index(); + DcalcAPIndex ap_index = scene->dcalcAnalysisPtIndex(min_max); debugPrint(debug_, "delay_calc", 3, - " %s %s -> %s %s (%s) corner:%s/%s", + " %s %s -> %s %s (%s) scene:%s/%s", arc->from()->name(), arc->fromEdge()->to_string().c_str(), arc->to()->name(), arc->toEdge()->to_string().c_str(), arc->role()->to_string().c_str(), - dcalc_ap->corner()->name(), - dcalc_ap->delayMinMax()->to_string().c_str()); + scene->name().c_str(), + min_max->to_string().c_str()); debugPrint(debug_, "delay_calc", 3, " gate delay = %s slew = %s", delayAsString(gate_delay, this), delayAsString(gate_slew, this)); + bool delay_changed = false; Vertex *drvr_vertex = edge->to(graph_); const RiseFall *drvr_rf = arc->toEdge()->asRiseFall(); // Merge slews. const Slew &drvr_slew = graph_->slew(drvr_vertex, drvr_rf, ap_index); - const MinMax *slew_min_max = dcalc_ap->slewMinMax(); - if (delayGreater(gate_slew, drvr_slew, slew_min_max, this) - && !drvr_vertex->slewAnnotated(drvr_rf, slew_min_max) + if (delayGreater(gate_slew, drvr_slew, min_max, this) + && !drvr_vertex->slewAnnotated(drvr_rf, min_max) && !edge->role()->isLatchDtoQ()) graph_->setSlew(drvr_vertex, drvr_rf, ap_index, gate_slew); if (!graph_->arcDelayAnnotated(edge, arc, ap_index)) { @@ -1160,11 +1249,11 @@ GraphDelayCalc::annotateLoadDelays(Vertex *drvr_vertex, LoadPinIndexMap &load_pin_index_map, const ArcDelay &extra_delay, bool merge, - const DcalcAnalysisPt *dcalc_ap) + const Scene *scene, + const MinMax *min_max) { + DcalcAPIndex ap_index = scene->dcalcAnalysisPtIndex(min_max); bool changed = false; - DcalcAPIndex ap_index = dcalc_ap->index(); - const MinMax *slew_min_max = dcalc_ap->slewMinMax(); VertexOutEdgeIterator edge_iter(drvr_vertex, graph_); while (edge_iter.hasNext()) { Edge *wire_edge = edge_iter.next(); @@ -1180,8 +1269,8 @@ GraphDelayCalc::annotateLoadDelays(Vertex *drvr_vertex, delayAsString(wire_delay, this), delayAsString(load_slew, this)); bool load_changed = false; - if (!load_vertex->slewAnnotated(drvr_rf, slew_min_max)) { - if (drvr_vertex->slewAnnotated(drvr_rf, slew_min_max)) { + if (!load_vertex->slewAnnotated(drvr_rf, min_max)) { + if (drvr_vertex->slewAnnotated(drvr_rf, min_max)) { // Copy the driver slew to the load if it is annotated. const Slew &drvr_slew = graph_->slew(drvr_vertex,drvr_rf,ap_index); graph_->setSlew(load_vertex, drvr_rf, ap_index, drvr_slew); @@ -1190,7 +1279,7 @@ GraphDelayCalc::annotateLoadDelays(Vertex *drvr_vertex, else { const Slew &slew = graph_->slew(load_vertex, drvr_rf, ap_index); if (!merge - || delayGreater(load_slew, slew, slew_min_max, this)) { + || delayGreater(load_slew, slew, min_max, this)) { graph_->setSlew(load_vertex, drvr_rf, ap_index, load_slew); load_changed = true; } @@ -1202,9 +1291,8 @@ GraphDelayCalc::annotateLoadDelays(Vertex *drvr_vertex, // rather than set. const ArcDelay &delay = graph_->wireArcDelay(wire_edge, drvr_rf, ap_index); Delay wire_delay_extra = extra_delay + wire_delay; - const MinMax *delay_min_max = dcalc_ap->delayMinMax(); if (!merge - || delayGreater(wire_delay_extra, delay, delay_min_max, this)) { + || delayGreater(wire_delay_extra, delay, min_max, this)) { graph_->setWireArcDelay(wire_edge, drvr_rf, ap_index, wire_delay_extra); load_changed = true; } @@ -1241,12 +1329,12 @@ GraphDelayCalc::makeLoadPinIndexMap(Vertex *drvr_vertex) // External float GraphDelayCalc::loadCap(const Pin *drvr_pin, - const DcalcAnalysisPt *dcalc_ap) const + const Scene *scene, + const MinMax *min_max) const { - const MinMax *min_max = dcalc_ap->constraintMinMax(); float load_cap = min_max->initValue(); for (const RiseFall *drvr_rf : RiseFall::range()) { - float cap = loadCap(drvr_pin, drvr_rf, dcalc_ap); + float cap = loadCap(drvr_pin, drvr_rf, scene, min_max); load_cap = min_max->minMax(cap, load_cap); } arc_delay_calc_->finishDrvrPin(); @@ -1257,10 +1345,11 @@ GraphDelayCalc::loadCap(const Pin *drvr_pin, float GraphDelayCalc::loadCap(const Pin *drvr_pin, const RiseFall *rf, - const DcalcAnalysisPt *dcalc_ap) const + const Scene *scene, + const MinMax *min_max) const { float pin_cap, wire_cap; - loadCap(drvr_pin, rf, dcalc_ap, pin_cap, wire_cap); + loadCap(drvr_pin, rf, scene, min_max, pin_cap, wire_cap); return pin_cap + wire_cap; } @@ -1268,7 +1357,8 @@ GraphDelayCalc::loadCap(const Pin *drvr_pin, void GraphDelayCalc::loadCap(const Pin *drvr_pin, const RiseFall *rf, - const DcalcAnalysisPt *dcalc_ap, + const Scene *scene, + const MinMax *min_max, float &pin_cap, float &wire_cap) const { @@ -1278,7 +1368,7 @@ GraphDelayCalc::loadCap(const Pin *drvr_pin, multi_drvr = multiDrvrNet(drvr_vertex); } const Parasitic *parasitic; - parasiticLoad(drvr_pin, rf, dcalc_ap, multi_drvr, arc_delay_calc_, + parasiticLoad(drvr_pin, rf, scene, min_max, multi_drvr, arc_delay_calc_, pin_cap, wire_cap, parasitic); arc_delay_calc_->finishDrvrPin(); } @@ -1286,12 +1376,13 @@ GraphDelayCalc::loadCap(const Pin *drvr_pin, float GraphDelayCalc::loadCap(const Pin *drvr_pin, const RiseFall *rf, - const DcalcAnalysisPt *dcalc_ap, + const Scene *scene, + const MinMax *min_max, ArcDelayCalc *arc_delay_calc) const { const Parasitic *parasitic; float pin_cap, wire_cap; - parasiticLoad(drvr_pin, rf, dcalc_ap, nullptr, arc_delay_calc, + parasiticLoad(drvr_pin, rf, scene, min_max, nullptr, arc_delay_calc, pin_cap, wire_cap, parasitic); return pin_cap + wire_cap; } @@ -1299,7 +1390,8 @@ GraphDelayCalc::loadCap(const Pin *drvr_pin, void GraphDelayCalc::parasiticLoad(const Pin *drvr_pin, const RiseFall *rf, - const DcalcAnalysisPt *dcalc_ap, + const Scene *scene, + const MinMax *min_max, const MultiDrvrNet *multi_drvr, ArcDelayCalc *arc_delay_calc, // Return values. @@ -1307,7 +1399,7 @@ GraphDelayCalc::parasiticLoad(const Pin *drvr_pin, const Parasitic *¶sitic) const { float pin_cap, wire_cap; - parasiticLoad(drvr_pin, rf, dcalc_ap, multi_drvr, arc_delay_calc, + parasiticLoad(drvr_pin, rf, scene, min_max, multi_drvr, arc_delay_calc, pin_cap, wire_cap, parasitic); load_cap = pin_cap + wire_cap; } @@ -1315,7 +1407,8 @@ GraphDelayCalc::parasiticLoad(const Pin *drvr_pin, void GraphDelayCalc::parasiticLoad(const Pin *drvr_pin, const RiseFall *rf, - const DcalcAnalysisPt *dcalc_ap, + const Scene *scene, + const MinMax *min_max, const MultiDrvrNet *multi_drvr, ArcDelayCalc *arc_delay_calc, // Return values. @@ -1323,19 +1416,20 @@ GraphDelayCalc::parasiticLoad(const Pin *drvr_pin, float &wire_cap, const Parasitic *¶sitic) const { + Parasitics *parasitics = scene->parasitics(min_max); bool has_net_load; float fanout; - netCaps(drvr_pin, rf, dcalc_ap, multi_drvr, + netCaps(drvr_pin, rf, scene, min_max, multi_drvr, pin_cap, wire_cap, fanout, has_net_load); - parasitic = arc_delay_calc->findParasitic(drvr_pin, rf, dcalc_ap); + parasitic = arc_delay_calc->findParasitic(drvr_pin, rf, scene, min_max); // set_load net has precedence over parasitics. if (!has_net_load && parasitic) { - if (parasitics_->isParasiticNetwork(parasitic)) - wire_cap += parasitics_->capacitance(parasitic); + if (parasitics->isParasiticNetwork(parasitic)) + wire_cap += parasitics->capacitance(parasitic); else { // PiModel includes both pin and external caps. - float parasitic_cap = parasitics_->capacitance(parasitic); + float parasitic_cap = parasitics->capacitance(parasitic); if (parasitic_cap >= pin_cap) wire_cap = parasitic_cap - pin_cap; else { @@ -1350,7 +1444,8 @@ GraphDelayCalc::parasiticLoad(const Pin *drvr_pin, void GraphDelayCalc::netCaps(const Pin *drvr_pin, const RiseFall *rf, - const DcalcAnalysisPt *dcalc_ap, + const Scene *scene, + const MinMax *min_max, // Return values. float &pin_cap, float &wire_cap, @@ -1362,14 +1457,15 @@ GraphDelayCalc::netCaps(const Pin *drvr_pin, Vertex *drvr_vertex = graph_->pinDrvrVertex(drvr_pin); multi_drvr = multiDrvrNet(drvr_vertex); } - netCaps(drvr_pin, rf, dcalc_ap, multi_drvr, + netCaps(drvr_pin, rf, scene, min_max, multi_drvr, pin_cap, wire_cap, fanout, has_net_load); } void GraphDelayCalc::netCaps(const Pin *drvr_pin, const RiseFall *rf, - const DcalcAnalysisPt *dcalc_ap, + const Scene *scene, + const MinMax *min_max, const MultiDrvrNet *multi_drvr, // Return values. float &pin_cap, @@ -1378,13 +1474,12 @@ GraphDelayCalc::netCaps(const Pin *drvr_pin, bool &has_net_load) const { if (multi_drvr) - multi_drvr->netCaps(rf, dcalc_ap, + multi_drvr->netCaps(rf, scene, min_max, pin_cap, wire_cap, fanout, has_net_load); else { - const Corner *corner = dcalc_ap->corner(); - const MinMax *min_max = dcalc_ap->constraintMinMax(); + const Sdc *sdc = scene->sdc(); // Find pin and external pin/wire capacitance. - sdc_->connectedCap(drvr_pin, rf, corner, min_max, + sdc->connectedCap(drvr_pin, rf, scene, min_max, pin_cap, wire_cap, fanout, has_net_load); } } @@ -1392,12 +1487,12 @@ GraphDelayCalc::netCaps(const Pin *drvr_pin, void GraphDelayCalc::initSlew(Vertex *vertex) { + for (Scene *scene : scenes_) { + for (const MinMax *min_max : MinMax::range()) { + DcalcAPIndex ap_index = scene->dcalcAnalysisPtIndex(min_max); for (const RiseFall *rf : RiseFall::range()) { - for (const DcalcAnalysisPt *dcalc_ap : corners_->dcalcAnalysisPts()) { - const MinMax *slew_min_max = dcalc_ap->slewMinMax(); - if (!vertex->slewAnnotated(rf, slew_min_max)) { - DcalcAPIndex ap_index = dcalc_ap->index(); - graph_->setSlew(vertex, rf, ap_index, slew_min_max->initValue()); + if (!vertex->slewAnnotated(rf, min_max)) + graph_->setSlew(vertex, rf, ap_index, min_max->initValue()); } } } @@ -1407,26 +1502,25 @@ void GraphDelayCalc::zeroSlewAndWireDelays(Vertex *drvr_vertex, const RiseFall *rf) { - for (const DcalcAnalysisPt *dcalc_ap : corners_->dcalcAnalysisPts()) { - DcalcAPIndex ap_index = dcalc_ap->index(); - const MinMax *slew_min_max = dcalc_ap->slewMinMax(); - // Init drvr slew. - if (!drvr_vertex->slewAnnotated(rf, slew_min_max)) { - DcalcAPIndex ap_index = dcalc_ap->index(); - graph_->setSlew(drvr_vertex, rf, ap_index, slew_min_max->initValue()); - } + for (Scene *scene : scenes_) { + for (const MinMax *min_max : MinMax::range()) { + DcalcAPIndex ap_index = scene->dcalcAnalysisPtIndex(min_max); + // Init drvr slew. + if (!drvr_vertex->slewAnnotated(rf, min_max)) + graph_->setSlew(drvr_vertex, rf, ap_index, min_max->initValue()); - // Init wire delays and slews. - VertexOutEdgeIterator edge_iter(drvr_vertex, graph_); - while (edge_iter.hasNext()) { - Edge *wire_edge = edge_iter.next(); - if (wire_edge->isWire()) { - Vertex *load_vertex = wire_edge->to(graph_); - if (!graph_->wireDelayAnnotated(wire_edge, rf, ap_index)) - graph_->setWireArcDelay(wire_edge, rf, ap_index, 0.0); - // Init load vertex slew. - if (!load_vertex->slewAnnotated(rf, slew_min_max)) - graph_->setSlew(load_vertex, rf, ap_index, 0.0); + // Init wire delays and slews. + VertexOutEdgeIterator edge_iter(drvr_vertex, graph_); + while (edge_iter.hasNext()) { + Edge *wire_edge = edge_iter.next(); + if (wire_edge->isWire()) { + Vertex *load_vertex = wire_edge->to(graph_); + if (!graph_->wireDelayAnnotated(wire_edge, rf, ap_index)) + graph_->setWireArcDelay(wire_edge, rf, ap_index, 0.0); + // Init load vertex slew. + if (!load_vertex->slewAnnotated(rf, min_max)) + graph_->setSlew(load_vertex, rf, ap_index, 0.0); + } } } } @@ -1439,10 +1533,11 @@ GraphDelayCalc::initWireDelays(Vertex *drvr_vertex) while (edge_iter.hasNext()) { Edge *wire_edge = edge_iter.next(); if (wire_edge->isWire()) { - for (const DcalcAnalysisPt * dcalc_ap : corners_->dcalcAnalysisPts()) { - const MinMax *delay_min_max = dcalc_ap->delayMinMax(); - Delay delay_init_value(delay_min_max->initValue()); - DcalcAPIndex ap_index = dcalc_ap->index(); + for (Scene *scene : scenes_) { + for (const MinMax *min_max : MinMax::range()) { + DcalcAPIndex ap_index = scene->dcalcAnalysisPtIndex(min_max); + + Delay delay_init_value(min_max->initValue()); for (const RiseFall *rf : RiseFall::range()) { if (!graph_->wireDelayAnnotated(wire_edge, rf, ap_index)) graph_->setWireArcDelay(wire_edge, rf, ap_index, delay_init_value); @@ -1450,15 +1545,17 @@ GraphDelayCalc::initWireDelays(Vertex *drvr_vertex) } } } + } } Slew GraphDelayCalc::edgeFromSlew(const Vertex *from_vertex, const RiseFall *from_rf, const Edge *edge, - const DcalcAnalysisPt *dcalc_ap) + const Scene *scene, + const MinMax *min_max) { - return edgeFromSlew(from_vertex, from_rf, edge->role(), dcalc_ap); + return edgeFromSlew(from_vertex, from_rf, edge->role(), scene, min_max); } // Use clock slew for register/latch clk->q edges. @@ -1466,15 +1563,17 @@ Slew GraphDelayCalc::edgeFromSlew(const Vertex *from_vertex, const RiseFall *from_rf, const TimingRole *role, - const DcalcAnalysisPt *dcalc_ap) + const Scene *scene, + const MinMax *min_max) { - + const ClkNetwork *clk_network = scene->mode()->clkNetwork(); if (role->genericRole() == TimingRole::regClkToQ() - && clk_network_->isIdealClock(from_vertex->pin())) - return clk_network_->idealClkSlew(from_vertex->pin(), from_rf, - dcalc_ap->slewMinMax()); - else - return graph_->slew(from_vertex, from_rf, dcalc_ap->index()); + && clk_network->isIdealClock(from_vertex)) + return clk_network->idealClkSlew(from_vertex->pin(), from_rf, min_max); + else { + DcalcAPIndex ap_index = scene->dcalcAnalysisPtIndex(min_max); + return graph_->slew(from_vertex, from_rf, ap_index); + } } void @@ -1499,32 +1598,34 @@ GraphDelayCalc::findCheckEdgeDelays(Edge *edge, const Pin *related_out_pin = 0; if (related_out_port) related_out_pin = network_->findPin(inst, related_out_port); - for (const DcalcAnalysisPt *dcalc_ap : corners_->dcalcAnalysisPts()) { - DcalcAPIndex ap_index = dcalc_ap->index(); + + for (Scene *scene : scenes_) { + for (const MinMax *min_max : MinMax::range()) { + DcalcAPIndex ap_index = scene->dcalcAnalysisPtIndex(min_max); if (!graph_->arcDelayAnnotated(edge, arc, ap_index)) { const Slew &from_slew = checkEdgeClkSlew(from_vertex, from_rf, - dcalc_ap); - int slew_index = dcalc_ap->checkDataSlewIndex(); - const Slew &to_slew = graph_->slew(to_vertex, to_rf, slew_index); + scene, min_max); + const Slew &to_slew = graph_->slew(to_vertex, to_rf, ap_index); debugPrint(debug_, "delay_calc", 3, - " %s %s -> %s %s (%s) corner:%s/%s", + " %s %s -> %s %s (%s) scene:%s/%s", arc_set->from()->name(), arc->fromEdge()->to_string().c_str(), arc_set->to()->name(), arc->toEdge()->to_string().c_str(), arc_set->role()->to_string().c_str(), - dcalc_ap->corner()->name(), - dcalc_ap->delayMinMax()->to_string().c_str()); + scene->name().c_str(), + min_max->to_string().c_str()); debugPrint(debug_, "delay_calc", 3, " from_slew = %s to_slew = %s", delayAsString(from_slew, this), delayAsString(to_slew, this)); float related_out_cap = 0.0; if (related_out_pin) - related_out_cap = loadCap(related_out_pin, to_rf,dcalc_ap,arc_delay_calc); + related_out_cap = loadCap(related_out_pin, to_rf,scene,min_max, + arc_delay_calc); ArcDelay check_delay = arc_delay_calc->checkDelay(to_pin, arc, from_slew, to_slew, related_out_cap, - dcalc_ap); + scene, min_max); debugPrint(debug_, "delay_calc", 3, " check_delay = %s", delayAsString(check_delay, this)); @@ -1535,6 +1636,7 @@ GraphDelayCalc::findCheckEdgeDelays(Edge *edge, } } } + } if (delay_changed && observer_) observer_->checkDelayChangedTo(to_vertex); @@ -1544,13 +1646,16 @@ GraphDelayCalc::findCheckEdgeDelays(Edge *edge, Slew GraphDelayCalc::checkEdgeClkSlew(const Vertex *from_vertex, const RiseFall *from_rf, - const DcalcAnalysisPt *dcalc_ap) + const Scene *scene, + const MinMax *min_max) { - if (clk_network_->isIdealClock(from_vertex->pin())) - return clk_network_->idealClkSlew(from_vertex->pin(), from_rf, - dcalc_ap->checkClkSlewMinMax()); + const ClkNetwork *clk_network = scene->mode()->clkNetwork(); + if (clk_network->isIdealClock(from_vertex)) + return clk_network->idealClkSlew(from_vertex->pin(), from_rf, + scene->checkClkSlewMinMax(min_max)); else - return graph_->slew(from_vertex, from_rf, dcalc_ap->checkClkSlewIndex()); + return graph_->slew(from_vertex, from_rf, + scene->checkClkSlewIndex(min_max)); } //////////////////////////////////////////////////////////////// @@ -1558,7 +1663,7 @@ GraphDelayCalc::checkEdgeClkSlew(const Vertex *from_vertex, string GraphDelayCalc::reportDelayCalc(const Edge *edge, const TimingArc *arc, - const Corner *corner, + const Scene *scene, const MinMax *min_max, int digits) { @@ -1569,7 +1674,6 @@ GraphDelayCalc::reportDelayCalc(const Edge *edge, const Instance *inst = network_->instance(to_pin); const TimingArcSet *arc_set = edge->timingArcSet(); string result; - DcalcAnalysisPt *dcalc_ap = corner->findDcalcAnalysisPt(min_max); const RiseFall *from_rf = arc->fromEdge()->asRiseFall(); const RiseFall *to_rf = arc->toEdge()->asRiseFall(); if (from_rf && to_rf) { @@ -1579,27 +1683,28 @@ GraphDelayCalc::reportDelayCalc(const Edge *edge, related_out_pin = network_->findPin(inst, related_out_port); float related_out_cap = 0.0; if (related_out_pin) - related_out_cap = loadCap(related_out_pin, to_rf, dcalc_ap, arc_delay_calc_); + related_out_cap = loadCap(related_out_pin, to_rf, scene, min_max, arc_delay_calc_); if (role->isTimingCheck()) { - const Slew &from_slew = checkEdgeClkSlew(from_vertex, from_rf, dcalc_ap); - int slew_index = dcalc_ap->checkDataSlewIndex(); + const Slew &from_slew = checkEdgeClkSlew(from_vertex, from_rf, scene, min_max); + DcalcAPIndex slew_index = scene->dcalcAnalysisPtIndex(min_max); const Slew &to_slew = graph_->slew(to_vertex, to_rf, slew_index); - bool from_ideal_clk = clk_network_->isIdealClock(from_vertex->pin()); + const ClkNetwork *clk_network = scene->mode()->clkNetwork(); + bool from_ideal_clk = clk_network->isIdealClock(from_vertex); const char *from_slew_annotation = from_ideal_clk ? " (ideal clock)" : nullptr; result = arc_delay_calc_->reportCheckDelay(to_pin, arc, from_slew, from_slew_annotation, to_slew, - related_out_cap, dcalc_ap, digits); + related_out_cap, scene, min_max, digits); } else { - const Slew &from_slew = edgeFromSlew(from_vertex, from_rf, edge, dcalc_ap); + const Slew &from_slew = edgeFromSlew(from_vertex, from_rf, edge, scene, min_max); const Parasitic *to_parasitic; float load_cap; - parasiticLoad(to_pin, to_rf, dcalc_ap, nullptr, arc_delay_calc_, + parasiticLoad(to_pin, to_rf, scene, min_max, nullptr, arc_delay_calc_, load_cap, to_parasitic); LoadPinIndexMap load_pin_index_map = makeLoadPinIndexMap(to_vertex); result = arc_delay_calc_->reportGateDelay(to_pin, arc, from_slew, load_cap, to_parasitic, load_pin_index_map, - dcalc_ap, digits); + scene, min_max, digits); } arc_delay_calc_->finishDrvrPin(); } @@ -1610,19 +1715,18 @@ GraphDelayCalc::reportDelayCalc(const Edge *edge, void GraphDelayCalc::minPeriod(const Pin *pin, - const Corner *corner, + const Scene *scene, // Return values. float &min_period, bool &exists) { exists = false; const MinMax *min_max = MinMax::max(); - const DcalcAnalysisPt *dcalc_ap = corner->findDcalcAnalysisPt(min_max); + const DcalcAPIndex dcalc_ap_index = scene->dcalcAnalysisPtIndex(min_max); // Sdf annotation. float min_period1 = 0.0; bool exists1 = false; - graph_->periodCheckAnnotation(pin, dcalc_ap->index(), - min_period, exists); + graph_->periodCheckAnnotation(pin, dcalc_ap_index, min_period, exists); if (exists1 && (!exists || min_period1 < min_period)) { min_period = min_period1; @@ -1636,7 +1740,7 @@ GraphDelayCalc::minPeriod(const Pin *pin, graph_->minPeriodArc(vertex, RiseFall::rise(), edge, arc); if (edge) { exists = true; - min_period = delayAsFloat(graph_->arcDelay(edge, arc, dcalc_ap->index())); + min_period = delayAsFloat(graph_->arcDelay(edge, arc, dcalc_ap_index)); } } if (!exists) { @@ -1644,9 +1748,19 @@ GraphDelayCalc::minPeriod(const Pin *pin, LibertyPort *port = network_->libertyPort(pin); if (port) { Instance *inst = network_->instance(pin); - OperatingConditions *op_cond = sdc_->operatingConditions(min_max); - const Pvt *pvt = inst ? sdc_->pvt(inst, min_max) : nullptr; - port->minPeriod(op_cond, pvt, min_period, exists); + for (const Mode *mode : modes_) { + const Sdc *sdc = mode->sdc(); + OperatingConditions *op_cond = sdc->operatingConditions(min_max); + const Pvt *pvt = inst ? sdc->pvt(inst, min_max) : nullptr; + float min_period1 = 0.0; + bool exists1 = false; + port->minPeriod(op_cond, pvt, min_period1, exists1); + if (exists1 + && (!exists || min_period1 < min_period)) { + min_period = min_period1; + exists = true; + } + } } } } @@ -1660,14 +1774,15 @@ MultiDrvrNet::MultiDrvrNet() : void MultiDrvrNet::netCaps(const RiseFall *drvr_rf, - const DcalcAnalysisPt *dcalc_ap, + const Scene *scene, + const MinMax *min_max, // Return values. float &pin_cap, float &wire_cap, float &fanout, bool &has_net_load) const { - int index = dcalc_ap->index() * RiseFall::index_count + int index = scene->dcalcAnalysisPtIndex(min_max) * RiseFall::index_count + drvr_rf->index(); const NetCaps &net_caps = net_caps_[index]; pin_cap = net_caps.pinCap(); @@ -1677,16 +1792,15 @@ MultiDrvrNet::netCaps(const RiseFall *drvr_rf, } void -MultiDrvrNet::findCaps(const Sdc *sdc) +MultiDrvrNet::findCaps(const StaState *sta) { - Corners *corners = sdc->corners(); - int count = RiseFall::index_count * corners->dcalcAnalysisPtCount(); + int count = RiseFall::index_count * sta->dcalcAnalysisPtCount(); net_caps_.resize(count); const Pin *drvr_pin = dcalc_drvr_->pin(); - for (const DcalcAnalysisPt *dcalc_ap : corners->dcalcAnalysisPts()) { - DcalcAPIndex ap_index = dcalc_ap->index(); - const Corner *corner = dcalc_ap->corner(); - const MinMax *min_max = dcalc_ap->constraintMinMax(); + for (Scene *scene : sta->scenes()) { + const Sdc *sdc = scene->sdc(); + for (const MinMax *min_max : MinMax::range()) { + DcalcAPIndex ap_index = scene->dcalcAnalysisPtIndex(min_max); for (const RiseFall *drvr_rf : RiseFall::range()) { int drvr_rf_index = drvr_rf->index(); int index = ap_index * RiseFall::index_count + drvr_rf_index; @@ -1694,11 +1808,12 @@ MultiDrvrNet::findCaps(const Sdc *sdc) float pin_cap, wire_cap, fanout; bool has_net_load; // Find pin and external pin/wire capacitance. - sdc->connectedCap(drvr_pin, drvr_rf, corner, min_max, + sdc->connectedCap(drvr_pin, drvr_rf, scene, min_max, pin_cap, wire_cap, fanout, has_net_load); net_caps.init(pin_cap, wire_cap, fanout, has_net_load); } } + } } void diff --git a/dcalc/LumpedCapDelayCalc.cc b/dcalc/LumpedCapDelayCalc.cc index 33436662..948e277f 100644 --- a/dcalc/LumpedCapDelayCalc.cc +++ b/dcalc/LumpedCapDelayCalc.cc @@ -35,7 +35,6 @@ #include "Network.hh" #include "Sdc.hh" #include "Parasitics.hh" -#include "DcalcAnalysisPt.hh" #include "GraphDelayCalc.hh" #include "Variables.hh" @@ -63,36 +62,38 @@ LumpedCapDelayCalc::copy() Parasitic * LumpedCapDelayCalc::findParasitic(const Pin *drvr_pin, - const RiseFall *rf, - const DcalcAnalysisPt *dcalc_ap) + const RiseFall *rf, + const Scene *scene, + const MinMax *min_max) { Parasitic *parasitic = nullptr; - const Corner *corner = dcalc_ap->corner(); - // set_load net has precedence over parasitics. - if (sdc_->drvrPinHasWireCap(drvr_pin, corner) + Parasitics *parasitics = scene->parasitics(min_max); + const Sdc *sdc = scene->sdc(); + if (parasitics == nullptr + // set_load net has precedence over parasitics. + || sdc->drvrPinHasWireCap(drvr_pin) || network_->direction(drvr_pin)->isInternal()) - return nullptr; - const ParasiticAnalysisPt *parasitic_ap = dcalc_ap->parasiticAnalysisPt(); + return nullptr; + // Prefer PiElmore. - parasitic = parasitics_->findPiElmore(drvr_pin, rf, parasitic_ap); + parasitic = parasitics->findPiElmore(drvr_pin, rf, min_max); if (parasitic) return parasitic; - Parasitic *parasitic_network = parasitics_->findParasiticNetwork(drvr_pin, - parasitic_ap); + Parasitic *parasitic_network = parasitics->findParasiticNetwork(drvr_pin); if (parasitic_network) { - parasitic = reduceParasitic(parasitic_network, drvr_pin, rf, dcalc_ap); + parasitic = reduceParasitic(parasitic_network, drvr_pin, rf, scene, min_max); if (parasitic) return parasitic; } - const MinMax *min_max = dcalc_ap->constraintMinMax(); - Wireload *wireload = sdc_->wireload(min_max); + + Wireload *wireload = sdc->wireload(min_max); if (wireload) { float pin_cap, wire_cap, fanout; bool has_net_load; - graph_delay_calc_->netCaps(drvr_pin, rf, dcalc_ap, + graph_delay_calc_->netCaps(drvr_pin, rf, scene, min_max, pin_cap, wire_cap, fanout, has_net_load); - parasitic = parasitics_->estimatePiElmore(drvr_pin, rf, wireload, fanout, - pin_cap, corner, min_max); + parasitic = parasitics->estimatePiElmore(drvr_pin, rf, wireload, fanout, + pin_cap, scene, min_max); } return parasitic; } @@ -101,14 +102,13 @@ Parasitic * LumpedCapDelayCalc::reduceParasitic(const Parasitic *parasitic_network, const Pin *drvr_pin, const RiseFall *rf, - const DcalcAnalysisPt *dcalc_ap) + const Scene *scene, + const MinMax *min_max) { - const Corner *corner = dcalc_ap->corner(); - const ParasiticAnalysisPt *parasitic_ap = dcalc_ap->parasiticAnalysisPt(); - return parasitics_->reduceToPiElmore(parasitic_network, drvr_pin, rf, - corner, dcalc_ap->constraintMinMax(), - parasitic_ap); + Parasitics *parasitics = scene->parasitics(min_max); + return parasitics->reduceToPiElmore(parasitic_network, drvr_pin, rf, + scene, min_max); } ArcDcalcResult @@ -117,7 +117,8 @@ LumpedCapDelayCalc::inputPortDelay(const Pin *, const RiseFall *rf, const Parasitic *, const LoadPinIndexMap &load_pin_index_map, - const DcalcAnalysisPt *) + const Scene *, + const MinMax *) { const LibertyLibrary *drvr_library = network_->defaultLibertyLibrary(); return makeResult(drvr_library,rf, 0.0, in_slew, load_pin_index_map); @@ -126,13 +127,14 @@ LumpedCapDelayCalc::inputPortDelay(const Pin *, ArcDcalcResult LumpedCapDelayCalc::gateDelay(const Pin *drvr_pin, const TimingArc *arc, - const Slew &in_slew, - float load_cap, - const Parasitic *, + const Slew &in_slew, + float load_cap, + const Parasitic *, const LoadPinIndexMap &load_pin_index_map, - const DcalcAnalysisPt *dcalc_ap) + const Scene *scene, + const MinMax *min_max) { - GateTimingModel *model = arc->gateModel(dcalc_ap); + GateTimingModel *model = arc->gateModel(scene, min_max); debugPrint(debug_, "delay_calc", 3, " in_slew = %s load_cap = %s lumped", delayAsString(in_slew, this), @@ -146,7 +148,7 @@ LumpedCapDelayCalc::gateDelay(const Pin *drvr_pin, // NaNs cause seg faults during table lookup. if (isnan(load_cap) || isnan(delayAsFloat(in_slew))) report_->error(1350, "gate delay input variable is NaN"); - model->gateDelay(pinPvt(drvr_pin, dcalc_ap), in_slew1, load_cap, + model->gateDelay(pinPvt(drvr_pin, scene, min_max), in_slew1, load_cap, variables_->pocvEnabled(), gate_delay, drvr_slew); return makeResult(drvr_library, rf, gate_delay, drvr_slew, load_pin_index_map); @@ -182,14 +184,15 @@ LumpedCapDelayCalc::reportGateDelay(const Pin *check_pin, float load_cap, const Parasitic *, const LoadPinIndexMap &, - const DcalcAnalysisPt *dcalc_ap, + const Scene *scene, + const MinMax *min_max, int digits) { - GateTimingModel *model = arc->gateModel(dcalc_ap); + GateTimingModel *model = arc->gateModel(scene, min_max); if (model) { float in_slew1 = delayAsFloat(in_slew); - return model->reportGateDelay(pinPvt(check_pin, dcalc_ap), in_slew1, load_cap, - false, digits); + return model->reportGateDelay(pinPvt(check_pin, scene, min_max), + in_slew1, load_cap, false, digits); } return ""; } diff --git a/dcalc/LumpedCapDelayCalc.hh b/dcalc/LumpedCapDelayCalc.hh index 5170d7a5..5cf829bd 100644 --- a/dcalc/LumpedCapDelayCalc.hh +++ b/dcalc/LumpedCapDelayCalc.hh @@ -38,32 +38,37 @@ public: const char *name() const override { return "lumped_cap"; } Parasitic *findParasitic(const Pin *drvr_pin, const RiseFall *rf, - const DcalcAnalysisPt *dcalc_ap) override; + const Scene *scene, + const MinMax *min_max) override; bool reduceSupported() const override { return true; } Parasitic *reduceParasitic(const Parasitic *parasitic_network, const Pin *drvr_pin, const RiseFall *rf, - const DcalcAnalysisPt *dcalc_ap) override; + const Scene *scene, + const MinMax *min_max) override; ArcDcalcResult inputPortDelay(const Pin *port_pin, float in_slew, const RiseFall *rf, const Parasitic *parasitic, const LoadPinIndexMap &load_pin_index_map, - const DcalcAnalysisPt *dcalc_ap) override; + const Scene *scene, + const MinMax *min_max) override; ArcDcalcResult gateDelay(const Pin *drvr_pin, const TimingArc *arc, const Slew &in_slew, float load_cap, const Parasitic *parasitic, const LoadPinIndexMap &load_pin_index_map, - const DcalcAnalysisPt *dcalc_ap) override; + const Scene *scene, + const MinMax *min_max) override; std::string reportGateDelay(const Pin *drvr_pin, const TimingArc *arc, const Slew &in_slew, float load_cap, const Parasitic *parasitic, const LoadPinIndexMap &load_pin_index_map, - const DcalcAnalysisPt *dcalc_ap, + const Scene *scene, + const MinMax *min_max, int digits) override; protected: diff --git a/dcalc/NetCaps.cc b/dcalc/NetCaps.cc index 5aa200ed..0500b57d 100644 --- a/dcalc/NetCaps.cc +++ b/dcalc/NetCaps.cc @@ -31,9 +31,9 @@ NetCaps::NetCaps() } NetCaps::NetCaps(float pin_cap, - float wire_cap, - float fanout, - bool has_net_load) : + float wire_cap, + float fanout, + bool has_net_load) : pin_cap_(pin_cap), wire_cap_(wire_cap), fanout_(fanout), @@ -43,9 +43,9 @@ NetCaps::NetCaps(float pin_cap, void NetCaps::init(float pin_cap, - float wire_cap, - float fanout, - bool has_net_load) + float wire_cap, + float fanout, + bool has_net_load) { pin_cap_ = pin_cap; wire_cap_ = wire_cap; diff --git a/dcalc/NetCaps.hh b/dcalc/NetCaps.hh index 5679d7ae..aeb1d9ff 100644 --- a/dcalc/NetCaps.hh +++ b/dcalc/NetCaps.hh @@ -32,13 +32,13 @@ class NetCaps public: NetCaps(); NetCaps(float pin_cap, - float wire_cap, - float fanout, - bool has_net_load); + float wire_cap, + float fanout, + bool has_net_load); void init(float pin_cap, - float wire_cap, - float fanout, - bool has_net_load); + float wire_cap, + float fanout, + bool has_net_load); float pinCap() const { return pin_cap_; } float wireCap() const{ return wire_cap_; } float fanout() const{ return fanout_; } diff --git a/dcalc/ParallelDelayCalc.cc b/dcalc/ParallelDelayCalc.cc index 8bb5b18c..f18c785d 100644 --- a/dcalc/ParallelDelayCalc.cc +++ b/dcalc/ParallelDelayCalc.cc @@ -25,7 +25,7 @@ #include "ParallelDelayCalc.hh" #include "TimingArc.hh" -#include "Corner.hh" +#include "Scene.hh" #include "Network.hh" #include "Graph.hh" #include "Sdc.hh" @@ -44,25 +44,28 @@ ParallelDelayCalc::ParallelDelayCalc(StaState *sta): ArcDcalcResultSeq ParallelDelayCalc::gateDelays(ArcDcalcArgSeq &dcalc_args, const LoadPinIndexMap &load_pin_index_map, - const DcalcAnalysisPt *dcalc_ap) + const Scene *scene, + const MinMax *min_max) { if (dcalc_args.size() == 1) { ArcDcalcArg &dcalc_arg = dcalc_args[0]; ArcDcalcResult dcalc_result = gateDelay(dcalc_arg.drvrPin(), dcalc_arg.arc(), dcalc_arg.inSlew(), dcalc_arg.loadCap(), dcalc_arg.parasitic(), - load_pin_index_map, dcalc_ap); + load_pin_index_map, + scene, min_max); ArcDcalcResultSeq dcalc_results; dcalc_results.push_back(dcalc_result); return dcalc_results; } - return gateDelaysParallel(dcalc_args, load_pin_index_map, dcalc_ap); + return gateDelaysParallel(dcalc_args, load_pin_index_map, scene, min_max); } ArcDcalcResultSeq ParallelDelayCalc::gateDelaysParallel(ArcDcalcArgSeq &dcalc_args, const LoadPinIndexMap &load_pin_index_map, - const DcalcAnalysisPt *dcalc_ap) + const Scene *scene, + const MinMax *min_max) { size_t drvr_count = dcalc_args.size(); ArcDcalcResultSeq dcalc_results(drvr_count); @@ -75,16 +78,16 @@ ParallelDelayCalc::gateDelaysParallel(ArcDcalcArgSeq &dcalc_args, ArcDcalcResult &dcalc_result = dcalc_results[drvr_idx]; const Pin *drvr_pin = dcalc_arg.drvrPin(); const TimingArc *arc = dcalc_arg.arc(); - Slew in_slew = dcalc_arg.inSlew(); + const Slew &in_slew = dcalc_arg.inSlew(); ArcDcalcResult intrinsic_result = gateDelay(drvr_pin, arc, in_slew, 0.0, nullptr, - load_pin_index_map, dcalc_ap); + load_pin_index_map, scene, min_max); ArcDelay intrinsic_delay = intrinsic_result.gateDelay(); intrinsic_delays[drvr_idx] = intrinsic_result.gateDelay(); ArcDcalcResult gate_result = gateDelay(drvr_pin, arc, in_slew, dcalc_arg.loadCap(), dcalc_arg.parasitic(), - load_pin_index_map, dcalc_ap); + load_pin_index_map, scene, min_max); ArcDelay gate_delay = gate_result.gateDelay(); Slew drvr_slew = gate_result.drvrSlew(); ArcDelay load_delay = gate_delay - intrinsic_delay; diff --git a/dcalc/ParallelDelayCalc.hh b/dcalc/ParallelDelayCalc.hh index 40c8bc14..45f86814 100644 --- a/dcalc/ParallelDelayCalc.hh +++ b/dcalc/ParallelDelayCalc.hh @@ -38,11 +38,13 @@ public: ParallelDelayCalc(StaState *sta); ArcDcalcResultSeq gateDelays(ArcDcalcArgSeq &dcalc_args, const LoadPinIndexMap &load_pin_index_map, - const DcalcAnalysisPt *dcalc_ap) override; + const Scene *scene, + const MinMax *min_max) override; protected: ArcDcalcResultSeq gateDelaysParallel(ArcDcalcArgSeq &dcalc_args, const LoadPinIndexMap &load_pin_index_map, - const DcalcAnalysisPt *dcalc_ap); + const Scene *scene, + const MinMax *min_max); }; } // namespace diff --git a/dcalc/PrimaDelayCalc.cc b/dcalc/PrimaDelayCalc.cc index bce55d36..6379b85e 100644 --- a/dcalc/PrimaDelayCalc.cc +++ b/dcalc/PrimaDelayCalc.cc @@ -33,8 +33,7 @@ #include "PortDirection.hh" #include "Network.hh" #include "Sdc.hh" -#include "DcalcAnalysisPt.hh" -#include "Corner.hh" +#include "Scene.hh" #include "Graph.hh" #include "Parasitics.hh" #include "GraphDelayCalc.hh" @@ -64,9 +63,12 @@ makePrimaDelayCalc(StaState *sta) PrimaDelayCalc::PrimaDelayCalc(StaState *sta) : DelayCalcBase(sta), dcalc_args_(nullptr), + scene_(nullptr), + min_max_(nullptr), + parasitics_(nullptr), + parasitic_network_(nullptr), load_pin_index_map_(nullptr), pin_node_map_(network_), - node_index_map_(ParasiticNodeLess(parasitics_, network_)), prima_order_(3), make_waveforms_(false), waveform_drvr_pin_(nullptr), @@ -81,7 +83,7 @@ PrimaDelayCalc::PrimaDelayCalc(const PrimaDelayCalc &dcalc) : dcalc_args_(nullptr), load_pin_index_map_(nullptr), pin_node_map_(network_), - node_index_map_(ParasiticNodeLess(parasitics_, network_)), + node_index_map_(dcalc.node_index_map_), prima_order_(dcalc.prima_order_), make_waveforms_(false), waveform_drvr_pin_(nullptr), @@ -113,27 +115,26 @@ PrimaDelayCalc::copyState(const StaState *sta) Parasitic * PrimaDelayCalc::findParasitic(const Pin *drvr_pin, const RiseFall *rf, - const DcalcAnalysisPt *dcalc_ap) + const Scene *scene, + const MinMax *min_max) { - const Corner *corner = dcalc_ap->corner(); - const ParasiticAnalysisPt *parasitic_ap = dcalc_ap->parasiticAnalysisPt(); - // set_load net has precidence over parasitics. - if (sdc_->drvrPinHasWireCap(drvr_pin, corner) + const Sdc *sdc = scene->sdc(); + Parasitics *parasitics = scene->parasitics(min_max); + if (parasitics == nullptr + // set_load net has precedence over parasitics. || network_->direction(drvr_pin)->isInternal()) return nullptr; - Parasitic *parasitic = parasitics_->findParasiticNetwork(drvr_pin, parasitic_ap); + Parasitic *parasitic = parasitics->findParasiticNetwork(drvr_pin); if (parasitic) return parasitic; - const MinMax *cnst_min_max = dcalc_ap->constraintMinMax(); - Wireload *wireload = sdc_->wireload(cnst_min_max); + Wireload *wireload = sdc->wireload(min_max); if (wireload) { float pin_cap, wire_cap, fanout; bool has_wire_cap; - graph_delay_calc_->netCaps(drvr_pin, rf, dcalc_ap, pin_cap, wire_cap, + graph_delay_calc_->netCaps(drvr_pin, rf, scene, min_max, pin_cap, wire_cap, fanout, has_wire_cap); - parasitic = parasitics_->makeWireloadNetwork(drvr_pin, wireload, - fanout, cnst_min_max, - parasitic_ap); + parasitic = parasitics->makeWireloadNetwork(drvr_pin, wireload, + fanout, scene, min_max); } return parasitic; } @@ -142,7 +143,8 @@ Parasitic * PrimaDelayCalc::reduceParasitic(const Parasitic *, const Pin *, const RiseFall *, - const DcalcAnalysisPt *) + const Scene *, + const MinMax *) { return nullptr; } @@ -153,18 +155,16 @@ PrimaDelayCalc::inputPortDelay(const Pin *drvr_pin, const RiseFall *rf, const Parasitic *parasitic, const LoadPinIndexMap &load_pin_index_map, - const DcalcAnalysisPt *dcalc_ap) + const Scene *scene, + const MinMax *min_max) { + Parasitics *parasitics = scene->parasitics(min_max); ArcDcalcResult dcalc_result(load_pin_index_map.size()); LibertyLibrary *drvr_library = network_->defaultLibertyLibrary(); - const Parasitic *pi_elmore = nullptr; - if (parasitic && parasitics_->isParasiticNetwork(parasitic)) { - const ParasiticAnalysisPt *ap = dcalc_ap->parasiticAnalysisPt(); - pi_elmore = parasitics_->reduceToPiElmore(parasitic, drvr_pin, rf, - dcalc_ap->corner(), - dcalc_ap->constraintMinMax(), ap); - } + if (parasitic && parasitics->isParasiticNetwork(parasitic)) + pi_elmore = parasitics->reduceToPiElmore(parasitic, drvr_pin, rf, + scene, min_max); for (auto load_pin_index : load_pin_index_map) { const Pin *load_pin = load_pin_index.first; @@ -174,7 +174,7 @@ PrimaDelayCalc::inputPortDelay(const Pin *drvr_pin, bool elmore_exists = false; float elmore = 0.0; if (pi_elmore) - parasitics_->findElmore(pi_elmore, load_pin, elmore, elmore_exists); + parasitics->findElmore(pi_elmore, load_pin, elmore, elmore_exists); if (elmore_exists) // Input port with no external driver. dspfWireDelaySlew(load_pin, rf, in_slew, elmore, wire_delay, load_slew); @@ -192,33 +192,37 @@ PrimaDelayCalc::gateDelay(const Pin *drvr_pin, float load_cap, const Parasitic *parasitic, const LoadPinIndexMap &load_pin_index_map, - const DcalcAnalysisPt *dcalc_ap) + const Scene *scene, + const MinMax *min_max) { ArcDcalcArgSeq dcalc_args; dcalc_args.emplace_back(nullptr, drvr_pin, nullptr, arc, in_slew, load_cap, parasitic); - ArcDcalcResultSeq dcalc_results = gateDelays(dcalc_args, load_pin_index_map, dcalc_ap); + ArcDcalcResultSeq dcalc_results = gateDelays(dcalc_args, load_pin_index_map, scene, min_max); return dcalc_results[0]; } ArcDcalcResultSeq PrimaDelayCalc::gateDelays(ArcDcalcArgSeq &dcalc_args, const LoadPinIndexMap &load_pin_index_map, - const DcalcAnalysisPt *dcalc_ap) + const Scene *scene, + const MinMax *min_max) { dcalc_args_ = &dcalc_args; load_pin_index_map_ = &load_pin_index_map; drvr_count_ = dcalc_args.size(); - dcalc_ap_ = dcalc_ap; + scene_ = scene; + min_max_ = min_max; drvr_rf_ = dcalc_args[0].arc()->toEdge()->asRiseFall(); parasitic_network_ = dcalc_args[0].parasitic(); load_cap_ = dcalc_args[0].loadCap(); + parasitics_ = scene->parasitics(min_max); + node_index_map_ = NodeIndexMap(ParasiticNodeLess(parasitics_, network_)); bool failed = false; output_waveforms_.resize(drvr_count_); - const DcalcAnalysisPtSeq &dcalc_aps = corners_->dcalcAnalysisPts(); for (size_t drvr_idx = 0; drvr_idx < drvr_count_; drvr_idx++) { ArcDcalcArg &dcalc_arg = dcalc_args[drvr_idx]; - GateTableModel *table_model = dcalc_arg.arc()->gateTableModel(dcalc_ap); + GateTableModel *table_model = dcalc_arg.arc()->gateTableModel(scene, min_max); if (table_model && dcalc_arg.parasitic()) { OutputWaveforms *output_waveforms = table_model->outputWaveforms(); float in_slew = dcalc_arg.inSlewFlt(); @@ -236,7 +240,7 @@ PrimaDelayCalc::gateDelays(ArcDcalcArgSeq &dcalc_args, drvr_library->supplyVoltage("VDD", vdd_, vdd_exists); if (!vdd_exists) report_->error(1720, "VDD not defined in library %s", drvr_library->name()); - drvr_cell->ensureVoltageWaveforms(dcalc_aps); + drvr_cell->ensureVoltageWaveforms(scenes_); if (drvr_idx == 0) { vth_ = drvr_library->outputThreshold(drvr_rf_) * vdd_; vl_ = drvr_library->slewLowerThreshold(drvr_rf_) * vdd_; @@ -266,11 +270,13 @@ PrimaDelayCalc::tableDcalcResults() const Pin *drvr_pin = dcalc_arg.drvrPin(); if (drvr_pin) { const RiseFall *rf = dcalc_arg.drvrEdge(); - const Parasitic *parasitic = table_dcalc_->findParasitic(drvr_pin, rf, dcalc_ap_); + const Parasitic *parasitic = table_dcalc_->findParasitic(drvr_pin, rf, + scene_, min_max_); dcalc_arg.setParasitic(parasitic); } } - return table_dcalc_->gateDelays(*dcalc_args_, *load_pin_index_map_, dcalc_ap_); + return table_dcalc_->gateDelays(*dcalc_args_, *load_pin_index_map_, + scene_, min_max_); } void @@ -388,8 +394,7 @@ PrimaDelayCalc::driverResistance() { const Pin *drvr_pin = (*dcalc_args_)[0].drvrPin(); LibertyPort *drvr_port = network_->libertyPort(drvr_pin); - const MinMax *min_max = dcalc_ap_->delayMinMax(); - return drvr_port->driveResistance(drvr_rf_, min_max); + return drvr_port->driveResistance(drvr_rf_, min_max_); } void @@ -458,17 +463,16 @@ PrimaDelayCalc::pinCapacitance(ParasiticNode *node) { const Pin *pin = parasitics_->pin(node); float pin_cap = 0.0; + const Sdc *sdc = scene_->sdc(); if (pin) { Port *port = network_->port(pin); LibertyPort *lib_port = network_->libertyPort(port); - const Corner *corner = dcalc_ap_->corner(); - const MinMax *cnst_min_max = dcalc_ap_->constraintMinMax(); if (lib_port) { if (!includes_pin_caps_) - pin_cap = sdc_->pinCapacitance(pin, drvr_rf_, corner, cnst_min_max); + pin_cap = sdc->pinCapacitance(pin, drvr_rf_, scene_, min_max_); } else if (network_->isTopLevelPort(pin)) - pin_cap = sdc_->portExtCap(port, drvr_rf_, corner, cnst_min_max); + pin_cap = sdc->portExtCap(port, drvr_rf_, min_max_); } return pin_cap; } @@ -910,14 +914,15 @@ PrimaDelayCalc::reportGateDelay(const Pin *drvr_pin, float load_cap, const Parasitic *, const LoadPinIndexMap &, - const DcalcAnalysisPt *dcalc_ap, + const Scene *scene, + const MinMax *min_max, int digits) { - GateTimingModel *model = arc->gateModel(dcalc_ap); + GateTimingModel *model = arc->gateModel(scene, min_max); if (model) { float in_slew1 = delayAsFloat(in_slew); - return model->reportGateDelay(pinPvt(drvr_pin, dcalc_ap), in_slew1, load_cap, - false, digits); + return model->reportGateDelay(pinPvt(drvr_pin, scene, min_max), + in_slew1, load_cap, false, digits); } return ""; } diff --git a/dcalc/PrimaDelayCalc.hh b/dcalc/PrimaDelayCalc.hh index 454fdc98..20e84c24 100644 --- a/dcalc/PrimaDelayCalc.hh +++ b/dcalc/PrimaDelayCalc.hh @@ -29,7 +29,6 @@ #include #include -#include "Map.hh" #include "LumpedCapDelayCalc.hh" #include "ArcDcalcWaveforms.hh" #include "Parasitics.hh" @@ -38,16 +37,16 @@ namespace sta { class ArcDelayCalc; class StaState; -class Corner; +class Scene; -typedef Map PinNodeMap; -typedef std::map NodeIndexMap; -typedef Map PortIndexMap; -typedef Eigen::SparseMatrix MatrixSd; -typedef Map PinLMap; -typedef std::map WatchPinValuesMap; +using PinNodeMap = std::map; +using NodeIndexMap = std::map; +using PortIndexMap = std::map; +using MatrixSd = Eigen::SparseMatrix; +using PinLMap = std::map; +using WatchPinValuesMap = std::map; -typedef Table1 Waveform; +using Waveform = Table1; ArcDelayCalc * makePrimaDelayCalc(StaState *sta); @@ -65,35 +64,41 @@ public: void setPrimaReduceOrder(size_t order); Parasitic *findParasitic(const Pin *drvr_pin, const RiseFall *rf, - const DcalcAnalysisPt *dcalc_ap) override; + const Scene *scene, + const MinMax *min_max) override; bool reduceSupported() const override { return false; } Parasitic *reduceParasitic(const Parasitic *parasitic_network, const Pin *drvr_pin, const RiseFall *rf, - const DcalcAnalysisPt *dcalc_ap) override; + const Scene *scene, + const MinMax *min_max) override; ArcDcalcResult inputPortDelay(const Pin *drvr_pin, float in_slew, const RiseFall *rf, const Parasitic *parasitic, const LoadPinIndexMap &load_pin_index_map, - const DcalcAnalysisPt *dcalc_ap) override; + const Scene *scene, + const MinMax *min_max) override; ArcDcalcResult gateDelay(const Pin *drvr_pin, const TimingArc *arc, const Slew &in_slew, float load_cap, const Parasitic *parasitic, const LoadPinIndexMap &load_pin_index_map, - const DcalcAnalysisPt *dcalc_ap) override; + const Scene *scene, + const MinMax *min_max) override; ArcDcalcResultSeq gateDelays(ArcDcalcArgSeq &dcalc_args, const LoadPinIndexMap &load_pin_index_map, - const DcalcAnalysisPt *dcalc_ap) override; + const Scene *scene, + const MinMax *min_max) override; std::string reportGateDelay(const Pin *drvr_pin, const TimingArc *arc, const Slew &in_slew, float load_cap, const Parasitic *parasitic, const LoadPinIndexMap &load_pin_index_map, - const DcalcAnalysisPt *dcalc_ap, + const Scene *scene, + const MinMax *min_max, int digits) override; // Record waveform for drvr/load pin. @@ -147,7 +152,7 @@ protected: const Pin *drvr_pin, const RiseFall *drvr_rf, const Pin *load_pin, - const Corner *corner, + const Scene *scene, const MinMax *min_max); void primaReduce(); void primaReduce2(); @@ -168,7 +173,9 @@ protected: ArcDcalcArgSeq *dcalc_args_; size_t drvr_count_; float load_cap_; - const DcalcAnalysisPt *dcalc_ap_; + const Scene *scene_; + const MinMax *min_max_; + Parasitics *parasitics_; const Parasitic *parasitic_network_; const RiseFall *drvr_rf_; const LoadPinIndexMap *load_pin_index_map_; diff --git a/dcalc/UnitDelayCalc.cc b/dcalc/UnitDelayCalc.cc index 63f88a4b..c32197fb 100644 --- a/dcalc/UnitDelayCalc.cc +++ b/dcalc/UnitDelayCalc.cc @@ -49,8 +49,9 @@ UnitDelayCalc::copy() Parasitic * UnitDelayCalc::findParasitic(const Pin *, - const RiseFall *, - const DcalcAnalysisPt *) + const RiseFall *, + const Scene *, + const MinMax *) { return nullptr; } @@ -59,7 +60,8 @@ Parasitic * UnitDelayCalc::reduceParasitic(const Parasitic *, const Pin *, const RiseFall *, - const DcalcAnalysisPt *) + const Scene *, + const MinMax *) { return nullptr; } @@ -67,30 +69,33 @@ UnitDelayCalc::reduceParasitic(const Parasitic *, void UnitDelayCalc::reduceParasitic(const Parasitic *, const Net *, - const Corner *, + const Scene *, const MinMaxAll *) { } void UnitDelayCalc::setDcalcArgParasiticSlew(ArcDcalcArg &, - const DcalcAnalysisPt *) + const Scene *, + const MinMax *) { } void UnitDelayCalc::setDcalcArgParasiticSlew(ArcDcalcArgSeq &, - const DcalcAnalysisPt *) + const Scene *, + const MinMax *) { } ArcDcalcResult UnitDelayCalc::inputPortDelay(const Pin *, - float, - const RiseFall *, - const Parasitic *, + float, + const RiseFall *, + const Parasitic *, const LoadPinIndexMap &load_pin_index_map, - const DcalcAnalysisPt *) + const Scene *, + const MinMax *) { return unitDelayResult(load_pin_index_map); } @@ -98,11 +103,12 @@ UnitDelayCalc::inputPortDelay(const Pin *, ArcDcalcResult UnitDelayCalc::gateDelay(const Pin *, const TimingArc *, - const Slew &, - float, - const Parasitic *, + const Slew &, + float, + const Parasitic *, const LoadPinIndexMap &load_pin_index_map, - const DcalcAnalysisPt *) + const Scene *, + const MinMax *) { return unitDelayResult(load_pin_index_map); } @@ -110,7 +116,8 @@ UnitDelayCalc::gateDelay(const Pin *, ArcDcalcResultSeq UnitDelayCalc::gateDelays(ArcDcalcArgSeq &dcalc_args, const LoadPinIndexMap &load_pin_index_map, - const DcalcAnalysisPt *) + const Scene *, + const MinMax *) { size_t drvr_count = dcalc_args.size(); ArcDcalcResultSeq dcalc_results(drvr_count); @@ -138,12 +145,13 @@ UnitDelayCalc::unitDelayResult(const LoadPinIndexMap &load_pin_index_map) string UnitDelayCalc::reportGateDelay(const Pin *, const TimingArc *, - const Slew &, - float, - const Parasitic *, + const Slew &, + float, + const Parasitic *, const LoadPinIndexMap &, - const DcalcAnalysisPt *, - int) + const Scene *, + const MinMax *, + int) { string result("Delay = 1.0\n"); result += "Slew = 0.0\n"; @@ -153,10 +161,11 @@ UnitDelayCalc::reportGateDelay(const Pin *, ArcDelay UnitDelayCalc::checkDelay(const Pin *, const TimingArc *, - const Slew &, - const Slew &, - float, - const DcalcAnalysisPt *) + const Slew &, + const Slew &, + float, + const Scene *, + const MinMax *) { return units_->timeUnit()->scale(); } @@ -164,12 +173,13 @@ UnitDelayCalc::checkDelay(const Pin *, string UnitDelayCalc::reportCheckDelay(const Pin *, const TimingArc *, - const Slew &, - const char *, - const Slew &, - float, - const DcalcAnalysisPt *, - int) + const Slew &, + const char *, + const Slew &, + float, + const Scene *, + const MinMax *, + int) { return "Check = 1.0\n"; } diff --git a/dcalc/UnitDelayCalc.hh b/dcalc/UnitDelayCalc.hh index b0491c0b..094626cd 100644 --- a/dcalc/UnitDelayCalc.hh +++ b/dcalc/UnitDelayCalc.hh @@ -37,26 +37,31 @@ public: const char *name() const override { return "unit"; } Parasitic *findParasitic(const Pin *drvr_pin, const RiseFall *rf, - const DcalcAnalysisPt *dcalc_ap) override; + const Scene *scene, + const MinMax *min_max) override; bool reduceSupported() const override { return false; } Parasitic *reduceParasitic(const Parasitic *parasitic_network, const Pin *drvr_pin, const RiseFall *rf, - const DcalcAnalysisPt *dcalc_ap) override; + const Scene *scene, + const MinMax *min_max) override; void reduceParasitic(const Parasitic *parasitic_network, const Net *net, - const Corner *corner, + const Scene *scene, const MinMaxAll *min_max) override; void setDcalcArgParasiticSlew(ArcDcalcArg &gate, - const DcalcAnalysisPt *dcalc_ap) override; + const Scene *scene, + const MinMax *min_max) override; void setDcalcArgParasiticSlew(ArcDcalcArgSeq &gates, - const DcalcAnalysisPt *dcalc_ap) override; + const Scene *scene, + const MinMax *min_max) override; ArcDcalcResult inputPortDelay(const Pin *port_pin, float in_slew, const RiseFall *rf, const Parasitic *parasitic, const LoadPinIndexMap &load_pin_index_map, - const DcalcAnalysisPt *dcalc_ap) override; + const Scene *scene, + const MinMax *min_max) override; ArcDcalcResult gateDelay(const Pin *drvr_pin, const TimingArc *arc, const Slew &in_slew, @@ -64,23 +69,27 @@ public: float load_cap, const Parasitic *parasitic, const LoadPinIndexMap &load_pin_index_map, - const DcalcAnalysisPt *dcalc_ap) override; + const Scene *scene, + const MinMax *min_max) override; ArcDcalcResultSeq gateDelays(ArcDcalcArgSeq &args, const LoadPinIndexMap &load_pin_index_map, - const DcalcAnalysisPt *dcalc_ap) override; + const Scene *scene, + const MinMax *min_max) override; ArcDelay checkDelay(const Pin *check_pin, const TimingArc *arc, const Slew &from_slew, const Slew &to_slew, float related_out_cap, - const DcalcAnalysisPt *dcalc_ap) override; + const Scene *scene, + const MinMax *min_max) override; std::string reportGateDelay(const Pin *drvr_pin, const TimingArc *arc, const Slew &in_slew, float load_cap, const Parasitic *parasitic, const LoadPinIndexMap &load_pin_index_map, - const DcalcAnalysisPt *dcalc_ap, + const Scene *scene, + const MinMax *min_max, int digits) override; std::string reportCheckDelay(const Pin *check_pin, const TimingArc *arc, @@ -88,7 +97,8 @@ public: const char *from_slew_annotation, const Slew &to_slew, float related_out_cap, - const DcalcAnalysisPt *dcalc_ap, + const Scene *scene, + const MinMax *min_max, int digits) override; void finishDrvrPin() override; diff --git a/doc/ApiChanges.txt b/doc/ApiChanges.txt index d2ad43f8..553db6b3 100644 --- a/doc/ApiChanges.txt +++ b/doc/ApiChanges.txt @@ -24,6 +24,45 @@ This file summarizes STA API changes for each release. +Release 3.0.0 2025/11/26 +------------------------ + +OpenSTA now requires c++ 20. + +Corner replaced by Scene + mode() + parasitics(min_max) +DcalcAnalysisPt replaced by scene/min_min +DcalcAnalysisPt replaced by scene/min_min +PathAnalysisPt replaced by scene/min_min +StaState::sdc_ moved to Mode +StaState::sim_ moved to Mode +StaState::clk_network__ moved to Mode +StaState::parasitics_ moved to Scene + +Sta::findPathEnds group_paths arg has been changed from PathGroupNameSet* +to StdStringSeq&. + +Sta::isClock has been removed. Use mode->clkNetwork()->isClock instead. + +Sta::vertexSlew renamed to slew +Sta::vertexSlack renamed to slack +Sta::vertexSlacks renamed to slacks +Sta::vertexArrival renamed to arrival +Sta::vertexRequired renamed to required +Sta::pinSlack renamed to slack +Sta::pinArrival renamed to arrival + +FuncExpr::Operator::op_* renamed to FuncExpr::Op::* +FuncExprPortIterator has been removed. Use FuncExpr::ports(). + +Sdc::clocks() now returns ClockSeq&. +Sdc::clks() has been removed. + +The Vector/Map/Set/UnorderedSet classes have been removed and replaced by +the std containers. The member functions are now templated functions found +in ContainerHelpers.hh. + Release 2.6.2 2025/03/30 ------------------------ diff --git a/doc/ChangeLog.txt b/doc/ChangeLog.txt index 932339f8..9c8c8220 100644 --- a/doc/ChangeLog.txt +++ b/doc/ChangeLog.txt @@ -3,6 +3,180 @@ OpenSTA Timing Analyzer Release Notes This file summarizes user visible changes for each release. +Release 3.0.0 2025/11/26 +------------------------ + +This release adds multi-corner multi-mode (mcmm) support. The SDC +constraints in each mode describe a different operating mode, such as +mission mode or scan mode. + +A "scene" is the combination of a mode and corner. Each scene can have +separate min/max liberty and spef files. + +THe basic structure of a multi-corner/multi-mode command file is + read_liberty + read_verilog + link_design + read_sdc -mode... or set_mode followed by sdc commands + read_spef -name... + define_scene... + report_checks [-scenes] + +This is an example script with 2 corners, 2 modes and 3 scenes. + +read_liberty bc.lib +read_liberty wc.lib + +read_verilog design.v +link_design top + +read_sdc -mode run design.sdc +read_sdc -mode scan design_scan.sdc + +read_spef -name bc bc.spef +read_spef -name wc wc.spef + +define_scene bc \ + -mode run \ + -liberty bc \ + -spef bc +define_scene wc \ + -mode run \ + -liberty wc \ + -spef wc +define_scene scan \ + -mode scan \ + -liberty wc \ + -spef wc + +report_checks +report_checks -scenes bc +report_checks -scenes wc +report_checks -scenes scan + +................ + +Alternatively, the set_mode command can be used to define commands +for each mode at the command level instead of using SDC files. + +set_mode run +create_clock -period 10 clock +set_input_delay 0 -clock clock [all_inputs -no_clocks] +set_output_delay 0 -clock clock [all_outputs] + +set_mode scan +create_clock -period 100 scan_clock +set_input_delay 0 -clock scan_clock scan_in +set_output_delay 0 -clock scan_clock scan_out + +................ + +The define_corners command is supported for compatiblity but should +not be used with mcmm flows. Similarly, the -min/-max arguemnts to +read_liberty and read_spaf are supported for compabibility but should +not be used with mcmm flows. + +................ + +An initial mode and scene named "default" are defined for single mode, +single corner analysis. SDC commands defined interactively and read +with read_sdc without a -mode argument are defined in the "default" +mode. + +Use the set_mode command to define a mode or set the command +interpreter to add following commands to mode mode_name. + + set_mode mode_name + +If mode_name does not exist it is created. When modes are created the +default mode is deleted. + +The read_sdc command has a -mode argument to assign the commands in the file +to a mode. + + read_sdc [-mode mode_name] + +If the mode does not exist it is created. Multiple SDC files can +append commands to a mode by using the -mode_name argument for each +one. If no -mode arguement is is used the commands are added to the +current mode. + +................ + +The define_scene command defines a scene for a mode (SDC), liberty files +and spef parasitics. + + define_scene -mode mode_name + -liberty liberty_files | -liberty_min liberty_min_files -liberty_max liberty_max_files + [-spef spef_file | -spef_min spef_min_file -spef_max spef_max_file] + +Use get_scenes to find defined scenes. + + get_scenes [-modes mode_names] scene_name + +................ + +Use the read_spef -name argument to append multiple parasitics files +to annotate hierarchical blocks. Scene definitions use the spef_name +to specify which parasitices to use for each scene. + + read_spef -name spef_name + report_parasitic_annotation [-name spef_name] + +If -name is omitted the base name of the file name is used. + +The read_spef -corner/-min/-max arguments are supported for comppatibility +but will be removed in a future release. + +The read_spef -reduce options don't work because sdc, liberty ap isn't known + +................ + +The report_checks and report_check_typescommands support a -scenes +argument to report timing checks/paths from multiple scenes. + + report_checks -scenes + report_check_types -scenes + report_slews -scenes + report_clock_latency -scenes + +................ + +To annotate delays with SDF when there are multiple scenes, use +the -scene argument. + + read_sdf -scene + report_annotated_delay -scene + report_annotated_check -scene + +SDF annotation for mcmm analysis must follow the scene definitions. + +................ + +VCD annotation with read_vcd now supports a -mode arguement. + + read_vcd [-mode mode_name] + +................ + +The -corner args has been removed from the following commands because they are no +longer necessary. + set_load -corner + set_port_fanout_number -corner + +................ + +The report_pulse_width_checks command is no longer supported. Use +report_check_types -min_pulse_width. + +................ + +Delay calculation slew values now propagate through set_case_analysis +and set_logic_zero, set_logic_one, set_logic_dc constraints. + +Power analysis now ignores set_case_analysis and set_logic_zero, +set_logic_one, set_logic_dc. + Release 2.7.0 2025/05/19 ------------------------- @@ -19,6 +193,9 @@ to remove paths through identical pins and rise/fall edges. Instances now have pins for verilog netlist power/ground connections, +Sta::findPathEnds group_paths arg has been changed from PathGroupNameSet* +to StdStringSeq&. + Release 2.6.1 2025/03/30 ------------------------- @@ -93,6 +270,8 @@ timing groups. report_clock_skew -include_internal_latency report_clock_latency -include_internal_latency +The report_clock_skew requires a -scene argument if multiple scenes are defined. + The all_inputs command now supports the -no_clocks argument to exclude clocks from the list. diff --git a/doc/OpenSTA.fodt b/doc/OpenSTA.fodt index f7a17c62..39de2a67 100644 --- a/doc/OpenSTA.fodt +++ b/doc/OpenSTA.fodt @@ -1,24 +1,24 @@ - Parallax STA documentationJames Cherry4832025-03-17T12:59:52.4638705382010-07-31T21:07:002025-11-04T12:25:14.489956000P117DT14H41M24SLibreOffice/25.8.1.1$MacOSX_AARCH64 LibreOffice_project/54047653041915e595ad4e45cccea684809c77b5PDF files: James CherryJames Cherry12.00000falsefalsefalsefalse + Parallax STA documentationJames Cherry5112025-03-17T12:59:52.4638705382010-07-31T21:07:002025-12-25T18:12:25.212818000P122DT13H54M10SLibreOffice/25.8.1.1$MacOSX_AARCH64 LibreOffice_project/54047653041915e595ad4e45cccea684809c77b5PDF files: James CherryJames Cherry12.00000falsefalsefalsefalse - 981699 + 2475563 0 - 30224 + 19290 17736 true false view2 - 16529 - 988826 + 3041 + 2477826 0 - 981699 - 30222 - 999434 + 2475563 + 19288 + 2493298 0 1 false @@ -89,7 +89,7 @@ false true false - 25757696 + 26291860 0 false @@ -198,7 +198,7 @@ - + @@ -364,7 +364,7 @@ - + @@ -452,6 +452,7 @@ + @@ -534,6 +535,12 @@ + + + + + + @@ -1373,22 +1380,22 @@ - + - + - + - + - + - + @@ -1790,6 +1797,24 @@ + + + + + + + + + + + + + + + + + + @@ -1980,14 +2005,29 @@ - + + + + + + + + + + + + + + + + @@ -2348,24 +2388,6 @@ - - - - - - - - - - - - - - - - - - @@ -3149,6 +3171,21 @@ + + + + + + + + + + + + + + + @@ -3857,21 +3894,6 @@ - - - - - - - - - - - - - - - @@ -4116,1053 +4138,1149 @@ + + + + - + - - - - - + - + + + + + + + + + + + + + + + + + + + + + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - - - - - - - - - - - - - - - - - - - - - - - - - + + - + - + + - - - - - - - - + + + + + + + + + + - - + - + - - + - - + + - - - + + - + - + + - - + + - - + + - + - - - + + - - + - - + + - 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+ - + - + - + - + - + - + - + - + @@ -5181,1029 +5299,1056 @@ - + - + - + - + - + - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + + + + + + + + + + + + + + + + + + + + + + + + + + + + @@ -6324,92 +6469,100 @@ Table of Contents - Command Line Arguments1 - Example Command Scripts1 - Timing Analysis using SDF2 - Timing Analysis with Multiple Process Corners2 - Power Analysis2 - TCL Interpreter3 - Debugging Timing4 - No paths found4 - No path reported an endpoint5 - Commands6 - Filter Expressions80 - Variables80 + Command Line Arguments1 + Example Command Scripts1 + Timing Analysis using SDF2 + Timing Analysis with Multiple Process Corners2 + Timing Analysis with Multiple Modes3 + Power Analysis3 + TCL Interpreter5 + Debugging Timing6 + No paths found6 + No path reported an endpoint7 + Commands7 + Filter Expressions84 + Variables85 - Command Line Arguments + Command Line Arguments The command line arguments for sta are shown below. sta -help show help and exit -version show version and exit -no_init do not read ~/.sta -no_splash do not print the splash message -threads count|max use count threads -exit exit after reading cmd_file cmd_file source cmd_file When OpenSTA starts up, commands are first read from the user initialization file ~/.sta if it exists. If a TCL command file cmd_file is specified on the command line, commands are read from the file and executed before entering an interactive TCL command interpreter. If -exit is specified the application exits after reading cmd_file. Use the TCL exit command to exit the application. The –threads option specifies how many parallel threads to use. Use –threads max to use one thread per processor. - Example Command Scripts + Example Command Scripts To read a design into OpenSTA use the read_liberty command to read Liberty library files. Next, read hierarchical structural Verilog files with the read_verilog command. The link_design command links the Verilog to the Liberty timing cells. Any number of Liberty and Verilog files can be read before linking the design. Delays used for timing analysis are calculated using the Liberty timing models. If no parasitics are read only the pin capacitances of the timing models are used in delay calculation. Use the read_spef command to read parasitics from an extractor, or read_sdf to use delays calculated by an external delay calculator. Timing constraints can be entered as TCL commands or read using the read_sdc command. - The units used by OpenSTA for all command arguments and reports are taken from the first Liberty file that is read. Use the set_cmd_units command to override the default units. - Timing Analysis using SDF - A sample command file that reads a library and a Verilog netlist and reports timing checks is shown below. - read_liberty example1_slow.libread_verilog example1.vlink_design topread_sdf example1.sdfcreate_clock -name clk -period 10 {clk1 clk2 clk3}set_input_delay -clock clk 0 {in1 in2}report_checks - This example can be found in examples/sdf_delays.tcl. - Timing Analysis with Multiple Process Corners - An example command script using three process corners and +/-10% min/max derating is shown below. - define_corners wc typ bcread_liberty -corner wc example1_slow.libread_liberty -corner typ example1_typ.libread_liberty -corner bc example1_fast.libread_verilog example1.vlink_design topset_timing_derate -early 0.9set_timing_derate -late 1.1create_clock -name clk -period 10 {clk1 clk2 clk3}set_input_delay -clock clk 0 {in1 in2}report_checks -path_delay min_maxreport_checks -corner typ - This example can be found in examples/spef_parasitics.tcl. Other examples can be found in the examples directory. - Power Analysis - OpenSTA also supports static power analysis with the report_power command. Probabalistic switching activities are propagated from the input ports to determine switching activities for internal pins. - read_liberty sky130hd_tt.libread_verilog gcd_sky130hd.vlink_design gcdread_sdc gcd_sky130hd.sdcread_spef gcd_sky130hd.spefset_power_activity -input -activity 0.1set_power_activity -input_port reset -activity 0report_power - In this example the activity for all inputs is set to 0.1, and then the activity for the reset signal is set to zero because it does not switch during steady state operation. - Group Internal Switching Leakage Total Power Power Power Power (Watts)----------------------------------------------------------------Sequential 3.27e-04 7.87e-05 2.96e-10 4.06e-04 36.4%Combinational 2.34e-04 3.10e-04 6.95e-10 5.43e-04 48.7%Clock 4.68e-05 1.20e-04 2.30e-11 1.67e-04 15.0%Macro 0.00e+00 0.00e+00 0.00e+00 0.00e+00 0.0%Pad 0.00e+00 0.00e+00 0.00e+00 0.00e+00 0.0%----------------------------------------------------------------Total 6.07e-04 5.09e-04 1.01e-09 1.12e-03 100.0% 54.4% 45.6% 0.0% - This example can be found in examples/power.tcl. - Gate level simulation results can be used to get a more accurate power estimate. For example, the Icarus verilog simulator can be used to run the the test bench examples/gcd_tb.v for the gcd design in the previous example. + The units used by OpenSTA for all command arguments and reports are taken from the first Liberty file that is read. Use the set_cmd_units command to override the default units. Use the report_units command to see the ccmmand units. + Timing Analysis using SDF + A sample command file that reads a library and a Verilog netlist and reports timing checks is shown below. + read_liberty example1_slow.libread_verilog example1.vlink_design topread_sdf example1.sdfcreate_clock -name clk -period 10 {clk1 clk2 clk3}set_input_delay -clock clk 0 {in1 in2}report_checks + This example can be found in examples/sdf_delays.tcl. + Timing Analysis with Multiple Process Corners + An example command script using three process corners and +/-10% min/max derating is shown below. + read_liberty nangate45_slow.lib.gzread_liberty nangate45_typ.lib.gzread_liberty nangate45_fast.lib.gzread_verilog example1.link_design topset_timing_derate -early 0.9set_timing_derate -late 1.1create_clock -name clk -period 10 {clk1 clk2 clk3}set_input_delay -clock clk 0 {in1 in2}define_scene ss -liberty nangate45_slowdefine_scene tt -liberty nangate45_typdefine_scene ff -liberty nangate45_fast# report all scenesreport_checks -path_delay min_max# report typical scenereport_checks -scene tt + This example can be found in examples/multi_corner.tcl. Other examples can be found in the examples directory. + Timing Analysis with Multiple Modes + OpenSTA supports multi-corner, multi-mode analysis. Each corner/mode combination is called a “scene”. The SDC constraints in each mode describe a different operating mode, such as mission mode or scan mode. Each corner has min/max Liberty libraries and SPEF parasitics. + A mode named “default” is initially created for SDC commands. It is deleted when a mode is defined with set_mode or read_sdc -mode. Similartly, a named “default” is initially created that is deleted when define_scene is used to define a scene. + An example command script using two process corners two modes is shown below. + read_liberty asap7_small_ff.lib.gzread_liberty asap7_small_ss.lib.gzread_verilog reg1_asap7.vlink_design topread_sdc -mode mode1 mcmm2_mode1.sdcread_sdc -mode mode2 mcmm2_mode2.sdcread_spef -name reg1_ff reg1_asap7.spefread_spef -name reg1_ss reg1_asap7_ss.spefdefine_scene scene1 -mode mode1 -liberty asap7_small_ff -spef reg1_ffdefine_scene scene2 -mode mode2 -liberty asap7_small_ss -spef reg1_ssreport_checks -scenes scene1report_checks -scenes scene2report_checks -group_path_count 4 + This example can be found in examples/mcmm3.tcl.In the example show above the SDC for the modes is in separate files. Alternatively, the SDC can be defined in the command file using the set_mode command between SDC command groups. + set_mode mode1create_clock -name m1_clk -period 1000 {clk1 clk2 clk3}set_input_delay -clock m1_clk 100 {in1 in2}set_mode mode2create_clock -name m2_clk -period 500 {clk1 clk3}set_output_delay -clock m2_clk 100 out + Power Analysis + OpenSTA also supports static power analysis with the report_power command. Probabalistic switching activities are propagated from the input ports to determine switching activities for internal pins. + read_liberty sky130hd_tt.libread_verilog gcd_sky130hd.vlink_design gcdread_sdc gcd_sky130hd.sdcread_spef gcd_sky130hd.spefset_power_activity -input -activity 0.1set_power_activity -input_port reset -activity 0report_power + In this example the activity for all inputs is set to 0.1, and then the activity for the reset signal is set to zero because it does not switch during steady state operation. + Group Internal Switching Leakage Total Power Power Power Power (Watts)----------------------------------------------------------------Sequential 3.27e-04 7.87e-05 2.96e-10 4.06e-04 36.4%Combinational 2.34e-04 3.10e-04 6.95e-10 5.43e-04 48.7%Clock 4.68e-05 1.20e-04 2.30e-11 1.67e-04 15.0%Macro 0.00e+00 0.00e+00 0.00e+00 0.00e+00 0.0%Pad 0.00e+00 0.00e+00 0.00e+00 0.00e+00 0.0%----------------------------------------------------------------Total 6.07e-04 5.09e-04 1.01e-09 1.12e-03 100.0% 54.4% 45.6% 0.0% + This example can be found in examples/power.tcl. + Gate level simulation results can be used to get a more accurate power estimate. For example, the Icarus verilog simulator can be used to run the the test bench examples/gcd_tb.v for the gcd design in the previous example. iverilog -o gcd_tb gcd_tb.vvvp gcd_tb - The test bench writes the VCD (Value Change Data) file gcd_sky130hd.vcd which can then be read with the read_vcd command. - read_liberty sky130hd_tt.libread_verilog gcd_sky130hd.vlink_design gcdread_sdc gcd_sky130hd.sdcread_spef gcd_sky130hd.spefread_vcd -scope gcd_tb/gcd1 gcd_sky130hd.vcd.gzreport_power - This example can be found in examples/power_vcd.tcl. - Note that in this simple example design simulation based activities does not significantly change the results. - TCL Interpreter + The test bench writes the VCD (Value Change Data) file gcd_sky130hd.vcd which can then be read with the read_vcd command. + read_liberty sky130hd_tt.libread_verilog gcd_sky130hd.vlink_design gcdread_sdc gcd_sky130hd.sdcread_spef gcd_sky130hd.spefread_vcd -scope gcd_tb/gcd1 gcd_sky130hd.vcd.gzreport_power + This example can be found in examples/power_vcd.tcl. + Note that in this simple example design simulation based activities does not significantly change the results. + TCL Interpreter Keyword arguments to commands may be abbreviated. For example, report_checks -unique is equivalent to the following command. report_checks -unique_paths_to_endpoint - The help command lists matching commands and their arguments. - > help report*report_annotated_check [-setup] [-hold] [-recovery] [-removal] [-nochange] [-width] [-period] [-max_skew] [-max_lines liness] [-list_annotated]group_path_count [-list_not_annotated] [-constant_arcs]report_annotated_delay [-cell] [-net] [-from_in_ports] [-to_out_ports] [-max_lines liness] [-list_annotated] [-list_not_annotated] [-constant_arcs]report_arrival pinreport_check_types [-violators] [-verbose] [-corner corner] [-format slack_only|end] [-max_delay] [-min_delay] [-recovery] [-removal] [-clock_gating_setup] [-clock_gating_hold] [-max_slew] [-min_slew] [-max_fanout] [-min_fanout] [-max_capacitance] [-min_capacitance [-min_pulse_width] [-min_period] [-max_skew] [-net net] [-digits digits [-no_line_splits] [> filename] [>> filename]report_checks [-from from_list|-rise_from from_list|-fall_from from_list] [-through through_list|-rise_through through_list|-fall_through through_list] [-to to_list|-rise_to to_list|-fall_to to_list] [-unconstrained] [-path_delay min|min_rise|min_fall|max|max_rise|max_fall|min_max] [-corner corner] [-group_path_count path_count] [-endpoint_path_count path_count] [-unique_paths_to_endpoint] [-slack_max slack_max] [-slack_min slack_min] [-sort_by_slack] [-path_group group_name] [-format full|full_clock|full_clock_expanded|short|end|summary]... - Many reporting commands support redirection of the output to a file much like a Unix shell. - report_checks -to out1 > path.logreport_checks -to out2 >> path.log - Debugging Timing - Here are some guidelines for debugging your design if static timing does not report any paths, or does not report the expected paths. - Debugging timing problems generally involves using the following commands to follow the propagation of arrival times from a known arrival downstream to understand why the arrival times are not propagating: + The help command lists matching commands and their arguments. + > help report*report_annotated_check [-setup] [-hold] [-recovery] [-removal] [-nochange] [-width] [-period] [-max_skew] [-max_lines liness] [-list_annotated]group_path_count [-list_not_annotated] [-constant_arcs]report_annotated_delay [-cell] [-net] [-from_in_ports] [-to_out_ports] [-max_lines liness] [-list_annotated] [-list_not_annotated] [-constant_arcs]report_arrival pinreport_check_types [-violators] [-verbose] [-scene scene] [-format slack_only|end] [-max_delay] [-min_delay] [-recovery] [-removal] [-clock_gating_setup] [-clock_gating_hold] [-max_slew] [-min_slew] [-max_fanout] [-min_fanout] [-max_capacitance] [-min_capacitance [-min_pulse_width] [-min_period] [-max_skew] [-net net] [-digits digits [-no_line_splits] [> filename] [>> filename]report_checks [-from from_list|-rise_from from_list|-fall_from from_list] [-through through_list|-rise_through through_list|-fall_through through_list] [-to to_list|-rise_to to_list|-fall_to to_list] [-unconstrained] [-path_delay min|min_rise|min_fall|max|max_rise|max_fall|min_max] [-scene scene] [-group_path_count path_count] [-endpoint_path_count path_count] [-unique_paths_to_endpoint] [-slack_max slack_max] [-slack_min slack_min] [-sort_by_slack] [-path_group group_name] [-format full|full_clock|full_clock_expanded|short|end|summary]... + Many reporting commands support redirection of the output to a file much like a Unix shell. + report_checks -to out1 > path.logreport_checks -to out2 >> path.log + Debugging Timing + Here are some guidelines for debugging your design if static timing does not report any paths, or does not report the expected paths. + Debugging timing problems generally involves using the following commands to follow the propagation of arrival times from a known arrival downstream to understand why the arrival times are not propagating: report_edgesreport_arrivalsreport_net - report_edges -from can be used to walk forward and report_edges -to to walk backward in the netlist/timing graph. report_arrivals shows the min/max rise/fall arrival times with respect to each clock that has a path to the pin. report_net shows connections to a net across hierarchy levels. + report_edges -from can be used to walk forward and report_edges -to to walk backward in the netlist/timing graph. report_arrivals shows the min/max rise/fall arrival times with respect to each clock that has a path to the pin. report_net shows connections to a net across hierarchy levels. No paths found - The report_checks command only reports paths that are constrained by timing checks or SDC commands such as set_output_delay. If the design has only combinational logic (no registers or latches), there are no timing checks, so no paths are reported. Use the -unconstrained option to report_checks to see unconstrained paths. + The report_checks command only reports paths that are constrained by timing checks or SDC commands such as set_output_delay. If the design has only combinational logic (no registers or latches), there are no timing checks, so no paths are reported. Use the -unconstrained option to report_checks to see unconstrained paths. % report_checks -unconstrained - If the design is sequential (has registers or latches) and no paths are reported, it is likely that there is a problem with the clock propagation. Check the timing at an register in the design with the report_arrivals command. - % report_arrivals r1/CP (clk ^) r 0.00:0.00 f INF:-INF (clk v) r INF:-INF f 5.00:5.00 - In this example the rising edge of the clock "clk" causes the rising arrival min:max time at 0.00, and the falling edge arrives at 5.00. Since the rising edge of the clock causes the rising edge of the register clock pin, the clock path is positive unate. - The clock path should be positive or negative unate. Something is probably wrong with the clock network if it is non-unate. A non-unate clock path will report arrivals similar to the foillowing: + If the design is sequential (has registers or latches) and no paths are reported, it is likely that there is a problem with the clock propagation. Check the timing at an register in the design with the report_arrivals command. + % report_arrivals r1/CP (clk ^) r 0.00:0.00 f INF:-INF (clk v) r INF:-INF f 5.00:5.00 + In this example the rising edge of the clock "clk" causes the rising arrival min:max time at 0.00, and the falling edge arrives at 5.00. Since the rising edge of the clock causes the rising edge of the register clock pin, the clock path is positive unate. + The clock path should be positive or negative unate. Something is probably wrong with the clock network if it is non-unate. A non-unate clock path will report arrivals similar to the foillowing: % report_arrivals r1/CP (clk ^) r 0.00:0.00 f 0.00:0.00 (clk v) r 5.00:5.00 f 5.00:5.00 - Notice that each clock edge causes both rise and fall arrivals at the register clock pin. - If there are no paths to the register clock pin, nothing is printed. Use the report_edges -to command to find the gate driving the clock pin. - % report_edges -to r1/CPi1/ZN -> CP wire ^ -> ^ 0.00:0.00 v -> v 0.00:0.00 - This shows that the gate/pin i1/ZN is driving the clock pin. The report_edges -to commond can be used to walk backward or forward through the netlist one gate/net at a time. By checking the arrivals with the report_arrival command you can determine where the path is broken. + Notice that each clock edge causes both rise and fall arrivals at the register clock pin. + If there are no paths to the register clock pin, nothing is printed. Use the report_edges -to command to find the gate driving the clock pin. + % report_edges -to r1/CPi1/ZN -> CP wire ^ -> ^ 0.00:0.00 v -> v 0.00:0.00 + This shows that the gate/pin i1/ZN is driving the clock pin. The report_edges -to commond can be used to walk backward or forward through the netlist one gate/net at a time. By checking the arrivals with the report_arrival command you can determine where the path is broken. No path reported an endpoint - In order for a timing check to be reported, there must be an arrival time at the data pin (the constrained pin) as well as the timing check clock pin. If report_checks -to a register input does not report any paths, check that the input is constrained by a timing check with report_edges -to. + In order for a timing check to be reported, there must be an arrival time at the data pin (the constrained pin) as well as the timing check clock pin. If report_checks -to a register input does not report any paths, check that the input is constrained by a timing check with report_edges -to. % report_edges -to r1/DCP -> D hold ^ -> ^ -0.04:-0.04 ^ -> v -0.03:-0.03CP -> D setup ^ -> ^ 0.09:0.0 ^ -> v 0.08:0.08in1 -> D wire ^ -> ^ 0.00:0.00 v -> v 0.00:0.00 - This reports the setup and hold checks for the D pin of r1. - Next, check the arrival times at the D and CP pins of the register with report_arrivals. + This reports the setup and hold checks for the D pin of r1. + Next, check the arrival times at the D and CP pins of the register with report_arrivals. % report_arrivals r1/D (clk1 ^) r 1.00:1.00 f 1.00:1.00% report_arrivals r1/CP (clk1 ^) r 0.00:0.00 f INF:-INF (clk1 v) r INF:-INF f 5.00:5.00 - If there are no arrivals on an input port of the design, use the set_input_delay command to specify the arrival times on the port. - Commands + If there are no arrivals on an input port of the design, use the set_input_delay command to specify the arrival times on the port. + Commands - all_clocks + all_clocks - + @@ -6419,15 +6572,16 @@ - all_inputs + all_inputs - [-no_clocks] + [-no_clocks] + - -no_clocks + -no_clocks Exclude inputs defined as clock sources. @@ -6440,10 +6594,10 @@ - all_outputs + all_outputs - + @@ -6453,92 +6607,93 @@ - all_registers + all_registers - [-clock clock_names][-cells | -data_pins | -clock_pins | -async_pins | ‑output_pins][-level_sensitive][-edge_triggered] + [-clock clock_names][-cells | -data_pins | -clock_pins | -async_pins | ‑output_pins][-level_sensitive][-edge_triggered] - -clock clock_names + -clock clock_names - A list of clock names. Only registers clocked by these clocks are returned. + A list of clock names. Only registers clocked by these clocks are returned. - -cells + -cells - Return a list of register instances. + Return a list of register instances. - -data_pins + -data_pins - Return the register data pins. + Return the register data pins. - -clock_pins + -clock_pins - Return the register clock pins. + Return the register clock pins. - -async_pins + -async_pins - Return the register set/clear pins. + Return the register set/clear pins. - -output_pins + -output_pins - Return the register output pins. + Return the register output pins. - -level_sensitive + -level_sensitive - Return level-sensitive latches. + Return level-sensitive latches. - -edge_triggered + -edge_triggered - Return edge-triggered registers. + Return edge-triggered registers. - The all_registers command returns a list of register instances or register pins in the design. Options allow the list of registers to be restricted in various ways. The -clock keyword restrcts the registers to those that are clocked by a set of clocks. The -cells option returns the list of registers or latches (the default). The -‑data_pins, -clock_pins, -async_pins and -output_pins options cause all_registers to return a list of register pins rather than instances. + The all_registers command returns a list of register instances or register pins in the design. Options allow the list of registers to be restricted in various ways. The -clock keyword restrcts the registers to those that are clocked by a set of clocks. The -cells option returns the list of registers or latches (the default). The -‑data_pins, -clock_pins, -async_pins and -output_pins options cause all_registers to return a list of register pins rather than instances. + - check_setup + check_setup - [-verbose][-unconstrained_endpoints][-multiple_clock][-no_clock][-no_input_delay][-loops][-generated_clocks][> filename][>> filename] + [-verbose][-unconstrained_endpoints][-multiple_clock][-no_clock][-no_input_delay][-loops][-generated_clocks][> filename][>> filename] - -verbose + -verbose Show offending objects rather than just error counts. @@ -6546,7 +6701,7 @@ - -unconstrained_endpoints + -unconstrained_endpoints Check path endpoints for timing constraints (timing check or set_output_delay). @@ -6554,7 +6709,7 @@ - -multiple_clock + -multiple_clock Check register/latch clock pins for multiple clocks. @@ -6562,7 +6717,7 @@ - -no_clock + -no_clock Check register/latch clock pins for a clock. @@ -6570,7 +6725,7 @@ - -no_input_delay + -no_input_delay Check for inputs that do not have a set_input_delay command. @@ -6578,7 +6733,7 @@ - -loops + -loops Check for combinational logic loops. @@ -6586,28 +6741,28 @@ - -generated_clocks + -generated_clocks Check that generated clock source pins have been defined as clocks. - The check_setup command performs sanity checks on the design. Individual checks can be performed with the keywords. If no check keywords are specified all checks are performed. Checks that fail are reported as warnings. If no checks fail nothing is reported. The command returns 1 if there are no warnings for use in scripts. + The check_setup command performs sanity checks on the design. Individual checks can be performed with the keywords. If no check keywords are specified all checks are performed. Checks that fail are reported as warnings. If no checks fail nothing is reported. The command returns 1 if there are no warnings for use in scripts. - connect_pin + connect_pin - netport|pin + netport|pin - net + net A net to add connections to. @@ -6615,7 +6770,7 @@ - port + port A port to connect to net. @@ -6623,29 +6778,29 @@ - Pin + Pin A pin to connect to net. - The connect_pin command connects a port or instance pin to a net. + The connect_pin command connects a port or instance pin to a net. - create_clock + create_clock - -period period[-name clock_name][-waveform edge_list][-add][pin_list] + -period period[-name clock_name][-waveform edge_list][-add][pin_list] - -period period + -period period The clock period. @@ -6653,7 +6808,7 @@ - -name clock_name + -name clock_name The name of the clock. @@ -6661,7 +6816,7 @@ - -waveform edge_list + -waveform edge_list A list of edge rise and fall time. @@ -6669,15 +6824,15 @@ - -add + -add - Add this clock to the clocks on pin_list. + Add this clock to the clocks on pin_list. - pin_list + pin_list A list of pins driven by the clock. @@ -6685,29 +6840,28 @@ The create_clock command defines the waveform of a clock used by the design. - If no pin_list is specified the clock is virtual. A virtual clock can be refered to by name in input arrival and departure time commands but is not attached to any pins in the design. + If no pin_list is specified the clock is virtual. A virtual clock can be refered to by name in input arrival and departure time commands but is not attached to any pins in the design. If no clock name is specified the name of the first pin is used as the clock name. If a wavform is not specified the clock rises at zero and falls at half the clock period. The waveform is a list with time the clock rises as the first element and the time it falls as the second element. If a clock is already defined on a pin the clock is redefined using the new clock parameters. If multiple clocks drive the same pin, use the -add option to prevent the existing definition from being overwritten. The following command creates a clock with a period of 10 time units that rises at time 0 and falls at 5 time units on the pin named clk1. create_clock -period 10 clk1 The following command creates a clock with a period of 10 time units that is high at time zero, falls at time 2 and rises at time 8. The clock drives three pins named clk1, clk2, and clk3. - create_clock -period 10 -waveform {8 2} -name clk {clk1 clk2 clk3} + create_clock -period 10 -waveform {8 2} -name clk {clk1 clk2 clk3} - - create_generated_clock + create_generated_clock - [-name clock_name]-source master_pin[-master_clock master_clock][-divide_by divisor][-multiply_by multiplier][-duty_cycle duty_cycle][-invert][-edges edge_list][-edge_shift shift_list][-add]pin_list + [-name clock_name]-source master_pin[-master_clock master_clock][-divide_by divisor][-multiply_by multiplier][-duty_cycle duty_cycle][-invert][-edges edge_list][-edge_shift shift_list][-add]pin_list - -name clock_name + -name clock_name The name of the generated clock. @@ -6715,39 +6869,39 @@ - -source master_pin + -source master_pin - A pin or port in the fanout of the master clock that is the source of the generated clock. + A pin or port in the fanout of the master clock that is the source of the generated clock. - -master_clock master_clock + -master_clock master_clock - Use -master_clock to specify which source clock to use when multiple clocks are present on master_pin. + Use -master_clock to specify which source clock to use when multiple clocks are present on master_pin. - -divide_by divisor + -divide_by divisor - Divide the master clock period by divisor. + Divide the master clock period by divisor. - -multiply_by multiplier + -multiply_by multiplier - Multiply the master clock period by multiplier. + Multiply the master clock period by multiplier. - -duty_cycle duty_cycle + -duty_cycle duty_cycle The percent of the period that the generated clock is high (between 0 and 100). @@ -6755,7 +6909,7 @@ - -invert + -invert Invert the master clock. @@ -6763,15 +6917,15 @@ - -edges edge_list + -edges edge_list - List of master clock edges to use in the generated clock. Edges are numbered from 1. edge_list must be 3 edges long. + List of master clock edges to use in the generated clock. Edges are numbered from 1. edge_list must be 3 edges long. - -edge_shift shift_list + -edge_shift shift_list Not supported. @@ -6779,29 +6933,29 @@ - -add + -add - Add this clock to the existing clocks on pin_list. + Add this clock to the existing clocks on pin_list. - pin_list + pin_list - A list of pins driven by the generated clock. + A list of pins driven by the generated clock. The create_generated_clock command is used to generate a clock from an existing clock definition. It is used to model clock generation circuits such as clock dividers and phase locked loops. The -divide_by, -multiply_by and -edges arguments are mutually exclusive. - The -multiply_by option is used to generate a higher frequency clock from the source clock. The period of the generated clock is divided by multiplier. The clock multiplier must be a positive integer. If a duty cycle is specified the generated clock rises at zero and falls at period * duty_cycle / 100. If no duty cycle is specified the source clock edge times are divided by multiplier. - The -divide_by option is used to generate a lower frequency clock from the source clock. The clock divisor must be a positive integer. If the clock divisor is a power of two the source clock period is multiplied by divisor, the clock rise time is the same as the source clock, and the clock fall edge is one half period later. If the clock divisor is not a power of two the source clock waveform edge times are multiplied by divisor. + The -multiply_by option is used to generate a higher frequency clock from the source clock. The period of the generated clock is divided by multiplier. The clock multiplier must be a positive integer. If a duty cycle is specified the generated clock rises at zero and falls at period * duty_cycle / 100. If no duty cycle is specified the source clock edge times are divided by multiplier. + The -divide_by option is used to generate a lower frequency clock from the source clock. The clock divisor must be a positive integer. If the clock divisor is a power of two the source clock period is multiplied by divisor, the clock rise time is the same as the source clock, and the clock fall edge is one half period later. If the clock divisor is not a power of two the source clock waveform edge times are multiplied by divisor. The -edges option forms the generated clock waveform by selecting edges from the source clock waveform. If the -invert option is specified the waveform derived above is inverted. If a clock is already defined on a pin the clock is redefined using the new clock parameters. If multiple clocks drive the same pin, use the -add option to prevent the existing definition from being overwritten. - In the example show below generates a clock named gclk1 on register output pin r1/Q by dividing it by four. + In the example show below generates a clock named gclk1 on register output pin r1/Q by dividing it by four. create_clock -period 10 -waveform {1 8} clk1create_generated_clock -name gclk1 -source clk1 -divide_by 4 r1/Q The generated clock has a period of 40, rises at time 1 and falls at time 21. In the example shown below the duty cycle is used to define the derived clock waveform. @@ -6815,10 +6969,10 @@ - create_voltage_area + create_voltage_area - [-name name][-coordinate coordinates][-guard_band_x guard_x][-guard_band_y guard_y]cells + [-name name][-coordinate coordinates][-guard_band_x guard_x][-guard_band_y guard_y]cells @@ -6828,75 +6982,90 @@ - current_design + current_design - [design] + [design] - + - current_instance + current_instance - [instance] + [instance] - - instance + instance - Not supported. + Not supported. - - - - - - - define_corners + + + + + + + define_scene - - corner1 [corner2]... + + -mode mode_name -liberty liberty_files|-liberty_min liberty_min_files -liberty_max liberty_max_files-spef spef_file| -spef_min spef_min_file -spef_max spef_max_file - - - corner + + + mode_name - - The name of a delay calculation corner. + + The SDC mode to use. + + + + + liberty_files + + + List of Liberty files to use. + + + + + spef_file + + + The SPEF parasitics file to use. - Use the define_corners command to define the names of multiple process/temperature/voltage corners. The define_corners command must follow set_operating_conditions -analysis_type and precede any reference to the corner names and can only appear once in a command file. There is no support for re-defining corners. - For analysis type single, each corner has one delay calculation result and early/late path arrivals. For analysis type best_case/worst_case and on_chip_variation, each corner has min/max delay calculation results and early/late path arrivals. + The define_scene command defines a scene for a mode (SDC), liberty files and spef parasitics. Define scenes after reading Liberty libraries and SPEF parasitics. + Use get_scenes to find defined scenes. - delete_clock + delete_clock - [-all] clocks + [-all] clocks - clocks + clocks - A list of clocks to remove. + A list of clocks to remove. @@ -6906,26 +7075,26 @@ - delete_from_list + delete_from_list - list objects + list objects - list + list - A list of objects. + A list of objects. - objects + objects - A list of objects to delete from list. + A list of objects to delete from list. @@ -6935,18 +7104,19 @@ - delete_generated_clock + delete_generated_clock - [-all] clocks + [-all] clocks + - clocks + clocks - A list of generated clocks to remove. + A list of generated clocks to remove. @@ -6956,18 +7126,18 @@ - delete_instance + delete_instance - instance + instance - instance + instance - Instance to delete. + Instance to delete. @@ -6975,47 +7145,46 @@ - - delete_net + delete_net - net + net - net + net - Net to delete. + Net to delete. - The network editing command delete_net removes a net from the design. + The network editing command delete_net removes a net from the design. - disconnect_pin + disconnect_pin - netport | pin | -all + netport | pin | -all - net + net - The net to disconnect pins from. + The net to disconnect pins from. - port + port A port to connect to net. @@ -7023,7 +7192,7 @@ - pin + pin A pin to connect to net. @@ -7031,10 +7200,10 @@ - -all + -all - Disconnect all pins from the net. + Disconnect all pins from the net. @@ -7044,10 +7213,10 @@ - elapsed_run_time + elapsed_run_time - + @@ -7058,104 +7227,104 @@ - find_timing_paths + find_timing_paths - [-from from_list |-rise_from from_list |-fall_from from_list][-through through_list |-rise_through through_list |-fall_through through_list][-to to_list |-rise_to to_list |-fall_to to_list][-unconstrained][-path_delay min|min_rise|min_fall |max|max_rise|max_fall |min_max][-group_path_count path_count][-endpoint_path_count endpoint_path_count][-unique_paths_to_endpoint][-corner corner][-slack_max max_slack][-slack_min min_slack][-sort_by_slack][-path_group groups] + [-from from_list |-rise_from from_list |-fall_from from_list][-through through_list |-rise_through through_list |-fall_through through_list][-to to_list |-rise_to to_list |-fall_to to_list][-unconstrained][-path_delay min|min_rise|min_fall |max|max_rise|max_fall |min_max][-group_path_count path_count][-endpoint_path_count endpoint_path_count][-unique_paths_to_endpoint][-scene scene][-slack_max max_slack][-slack_min min_slack][-sort_by_slack][-path_group groups] - -from from_list + -from from_list - Return paths from a list of clocks, instances, ports, register clock pins, or latch data pins. + Return paths from a list of clocks, instances, ports, register clock pins, or latch data pins. - -rise_from from_list + -rise_from from_list - Return paths from the rising edge of clocks, instances, ports, register clock pins, or latch data pins. + Return paths from the rising edge of clocks, instances, ports, register clock pins, or latch data pins. - -fall_from from_list + -fall_from from_list - Return paths from the falling edge of clocks, instances, ports, register clock pins, or latch data pins. + Return paths from the falling edge of clocks, instances, ports, register clock pins, or latch data pins. - -through through_list + -through through_list - Return paths through a list of instances, pins or nets. + Return paths through a list of instances, pins or nets. - -rise_through through_list + -rise_through through_list - Return rising paths through a list of instances, pins or nets. + Return rising paths through a list of instances, pins or nets. - -fall_through through_list + -fall_through through_list - Return falling paths through a list of instances, pins or nets. + Return falling paths through a list of instances, pins or nets. - -to to_list + -to to_list - Return paths to a list of clocks, instances, ports or pins. + Return paths to a list of clocks, instances, ports or pins. - -rise_to to_list + -rise_to to_list - Return rising paths to a list of clocks, instances, ports or pins. + Return rising paths to a list of clocks, instances, ports or pins. - -fall_to to_list + -fall_to to_list - Return falling paths to a list of clocks, instances, ports or pins. + Return falling paths to a list of clocks, instances, ports or pins. - -unconstrained + -unconstrained - Report unconstrained paths also. + Report unconstrained paths also. + - -path_delay min + -path_delay min Return min path (hold) checks. - - -path_delay min_rise + -path_delay min_rise Return min path (hold) checks for rising endpoints. @@ -7163,7 +7332,7 @@ - -path_delay min_fall + -path_delay min_fall Return min path (hold) checks for falling endpoints. @@ -7171,7 +7340,7 @@ - -path_delay max + -path_delay max Return max path (setup) checks. @@ -7179,7 +7348,7 @@ - -path_delay max_rise + -path_delay max_rise Return max path (setup) checks for rising endpoints. @@ -7187,7 +7356,7 @@ - -path_delay max_fall + -path_delay max_fall Return max path (setup) checks for falling endpoints. @@ -7195,7 +7364,7 @@ - -path_delay min_max + -path_delay min_max Return max and max path (setup and hold) checks. @@ -7203,23 +7372,23 @@ - -group_path_count path_count + -group_path_count path_count - The number of paths to return in each path group. + The number of paths to return in each path group. - -endpoint_path_count endpoint_path_count + -endpoint_path_count endpoint_path_count - The number of paths to return for each endpoint. + The number of paths to return for each endpoint. - ‑unique_paths_to_endpoint + ‑unique_paths_to_endpoint Return multiple paths to an endpoint that traverse different pins without showing multiple paths with different rise/fall transitions. @@ -7227,7 +7396,7 @@ - -corner corner + -scene scene Return paths for one process corner. @@ -7235,109 +7404,109 @@ - -slack_max max_slack + -slack_max max_slack - Return paths with slack less than max_slack. + Return paths with slack less than max_slack. - -slack_min min_slack + -slack_min min_slack - Return paths with slack greater than min_slack. + Return paths with slack greater than min_slack. - -sort_by_slack + -sort_by_slack - Sort paths by slack rather than slack within path groups. + Sort paths by slack rather than slack within path groups. - -path_group groups + -path_group groups - Return paths in path groups. Paths in all groups are returned if this option is not specified. + Return paths in path groups. Paths in all groups are returned if this option is not specified. - The find_timing_paths command returns a list of path objects for scripting. Use the get_property function to access properties of the paths. + The find_timing_paths command returns a list of path objects for scripting. Use the get_property function to access properties of the paths. - - - get_cells - - - [-hierarchical][-hsc separator][-filter expr][-regexp][-nocase][-quiet][-of_objects objects][patterns] - - - - - -hierarchical - - - Searches hierarchy levels below the current instance for matches. - - - - -hsc separator + + get_cells - - Character to use to separate hierarchical instance names in patterns. + + [-hierarchical][-hsc separator][-filter expr][-regexp][-nocase][-quiet][-of_objects objects][patterns] - -filter expr + -hierarchical - A filter expression of the form “property==value”where property is a property supported by the get_property command. See the section “Filter Expressions” for additional forms. + Searches hierarchy levels below the current instance for matches. - -regexp + -hsc separator - Use regular expression matching instead of glob pattern matching. + Character to use to separate hierarchical instance names in patterns. - -nocase + -filter expr - Ignore case when matching. Only valid with –regexp. + A filter expression of the form “property==value”where property is a property supported by the get_property command. See the section “Filter Expressions” for additional forms. - -quiet + -regexp - Do not warn if no matches are found. + Use regular expression matching instead of glob pattern matching. - -of_objects objects + -nocase - The name of a pin or net, a list of pins returned by get_pins, or a list of nets returned by get_nets. The –hierarchical option cannot be used with ‑of_objects. + Ignore case when matching. Only valid with –regexp. - patterns + -quiet + + + Do not warn if no matches are found. + + + + + -of_objects objects + + + The name of a pin or net, a list of pins returned by get_pins, or a list of nets returned by get_nets. The –hierarchical option cannot be used with ‑of_objects. + + + + + patterns A list of instance name patterns. @@ -7350,47 +7519,48 @@ - get_clocks + get_clocks - [-regexp][-nocase][-filter expr][-quiet]patterns + [-regexp][-nocase][-filter expr][-quiet]patterns - -regexp + -regexp - Use regular expression matching instead of glob pattern matching. + Use regular expression matching instead of glob pattern matching. - -nocase + -nocase - Ignore case when matching. Only valid with –regexp. + Ignore case when matching. Only valid with –regexp. + + + + + + -filter expr + + + A filter expression of the form “property==value”where property is a property supported by the get_property command. See the section “Filter Expressions” for additional forms. - -filter expr + -quiet - A filter expression of the form “property==value”where property is a property supported by the get_property command. See the section “Filter Expressions” for additional forms. + Do not warn if no matches are found. - -quiet - - - Do not warn if no matches are found. - - - - - patterns + patterns A list of clock name patterns. @@ -7401,18 +7571,17 @@ - - get_fanin + get_fanin - -to sink_list[-flat][-only_cells][-startpoints_only][-levels level_count][-pin_levels pin_count][-trace_arcs timing|enabled|all] + -to sink_list[-flat][-only_cells][-startpoints_only][-levels level_count][-pin_levels pin_count][-trace_arcs timing|enabled|all] - -to sink_list + -to sink_list List of pins, ports, or nets to find the fanin of. For nets, the fanin of driver pins on the nets are returned. @@ -7420,15 +7589,15 @@ - -flat + -flat - With –flat pins in the fanin at any hierarchy level are returned. Without ‑flat only pins at the same hierarchy level as the sinks are returned. + With –flat pins in the fanin at any hierarchy level are returned. Without ‑flat only pins at the same hierarchy level as the sinks are returned. - -only_cells + -only_cells Return the instances connected to the pins in the fanin. @@ -7436,7 +7605,7 @@ - -startpoints_only + -startpoints_only Only return pins that are startpoints. @@ -7444,7 +7613,7 @@ - -level level_count + -level level_count Only return pins within level_count instance traversals. @@ -7452,7 +7621,7 @@ - -pin_levels pin_count + -pin_levels pin_count Only return pins within pin_count pin traversals. @@ -7460,44 +7629,45 @@ - -trace_arcs timing + -trace_arcs timing - Only trace through timing arcs that are not disabled. + Only trace through timing arcs that are not disabled. - -trace_arcs enabled + -trace_arcs enabled - Only trace through timing arcs that are not disabled. + Only trace through timing arcs that are not disabled. - -trace_arcs all + -trace_arcs all - Trace through all arcs, including disabled ones. + Trace through all arcs, including disabled ones. - The get_fanin command returns traverses the design from sink_list pins, ports or nets backwards and return the fanin pins or instances. + The get_fanin command returns traverses the design from sink_list pins, ports or nets backwards and return the fanin pins or instances. + - get_fanout + get_fanout - -from source_list[-flat][-only_cells][-endpoints_only][-levels level_count][-pin_levels pin_count][-trace_arcs timing|enabled|all] + -from source_list[-flat][-only_cells][-endpoints_only][-levels level_count][-pin_levels pin_count][-trace_arcs timing|enabled|all] - -from source_list + -from source_list List of pins, ports, or nets to find the fanout of. For nets, the fanout of load pins on the nets are returned. @@ -7505,24 +7675,23 @@ - -flat + -flat - With –flat pins in the fanin at any hierarchy level are returned. Without ‑flat only pins at the same hierarchy level as the sinks are returned. + With –flat pins in the fanin at any hierarchy level are returned. Without ‑flat only pins at the same hierarchy level as the sinks are returned. - -only_cells + -only_cells Return the instances connected to the pins in the fanout. - - -endpoints_only + -endpoints_only Only return pins that are endpoints. @@ -7530,7 +7699,7 @@ - -level level_count + -level level_count Only return pins within level_count instance traversals. @@ -7538,7 +7707,7 @@ - -pin_levels pin_count + -pin_levels pin_count Only return pins within pin_count pin traversals. @@ -7546,114 +7715,114 @@ - -trace_arcs timing + -trace_arcs timing - Only trace through timing arcs that are not disabled. + Only trace through timing arcs that are not disabled. - -trace_arcs enabled + -trace_arcs enabled - Only trace through timing arcs that are not disabled. + Only trace through timing arcs that are not disabled. - -trace_arcs all + -trace_arcs all - Trace through all arcs, including disabled ones. + Trace through all arcs, including disabled ones. - The get_fanout command returns traverses the design from source_list pins, ports or nets backwards and return the fanout pins or instances. + The get_fanout command returns traverses the design from source_list pins, ports or nets backwards and return the fanout pins or instances. - get_full_name + get_full_name - object + object - object + object - A library, cell, port, instance, pin or timing arc object. + A library, cell, port, instance, pin or timing arc object. - Return the name of object. Equivalent to [get_property object full_name]. + Return the name of object. Equivalent to [get_property object full_name]. - - - get_lib_cells - - - [-of_objects objects][-hsc separator][-filter expr][-regexp][-nocase][-quiet]patterns - - - - - -of_objects objects - - - A list of instance objects. - - - - - -hsc separator - - - Character that separates the library name and cell name in patterns. Defaults to ‘/’. - - - - - -filter expr - - - A filter expression of the form “property==value”where property is a property supported by the get_property command. See the section “Filter Expressions” for additional forms. - - - - - -regexp - - - Use regular expression matching instead of glob pattern matching. - - - - - -nocase - - - Ignore case when matching. Only valid with –regexp. - - - - -quiet + + get_lib_cells - - Do not warn if no matches are found. + + [-of_objects objects][-hsc separator][-filter expr][-regexp][-nocase][-quiet]patterns + + + + + -of_objects objects + + + A list of instance objects. - patterns + -hsc separator + + + Character that separates the library name and cell name in patterns. Defaults to ‘/’. + + + + + -filter expr + + + A filter expression of the form “property==value”where property is a property supported by the get_property command. See the section “Filter Expressions” for additional forms. + + + + + -regexp + + + Use regular expression matching instead of glob pattern matching. + + + + + -nocase + + + Ignore case when matching. Only valid with –regexp. + + + + + -quiet + + + Do not warn if no matches are found. + + + + + patterns A list of library cell name patterns of the form library_name/cell_name. @@ -7666,63 +7835,64 @@ - get_lib_pins + get_lib_pins - [-of_objects objects][-hsc separator][-filter expr][-regexp][-nocase][-quiet]patterns + [-of_objects objects][-hsc separator][-filter expr][-regexp][-nocase][-quiet]patterns - -of_objects objects + -of_objects objects - A list of library cell objects. + A list of library cell objects. - -hsc separator + -hsc separator - Character that separates the library name, cell name and port name in pattern. Defaults to ‘/’. + Character that separates the library name, cell name and port name in pattern. Defaults to ‘/’. + + + + + + -filter expr + + + A filter expression of the form “property==value”where property is a property supported by the get_property command. See the section “Filter Expressions” for additional forms. - -filter expr + -regexp - A filter expression of the form “property==value”where property is a property supported by the get_property command. See the section “Filter Expressions” for additional forms. + Use regular expression matching instead of glob pattern matching. - -regexp + -nocase - Use regular expression matching instead of glob pattern matching. + Ignore case when matching. Only valid with –regexp. - -nocase + -quiet - Ignore case when matching. Only valid with –regexp. + Do not warn if no matches are found. - -quiet - - - Do not warn if no matches are found. - - - - - patterns + patterns A list of library port name patterns of the form library_name/cell_name/port_name. @@ -7735,117 +7905,117 @@ - get_libs + get_libs - [-filter expr][-regexp][-nocase][-quiet]patterns + [-filter expr][-regexp][-nocase][-quiet]patterns - - -filter expr + -filter expr - A filter expression of the form “property==value”where property is a property supported by the get_property command. See the section “Filter Expressions” for additional forms. + A filter expression of the form “property==value”where property is a property supported by the get_property command. See the section “Filter Expressions” for additional forms. - -regexp + -regexp - Use regular expression matching instead of glob pattern matching. + Use regular expression matching instead of glob pattern matching. - -nocase + -nocase - Ignore case when matching. Only valid with –regexp. + Ignore case when matching. Only valid with –regexp. - -quiet + -quiet - Do not warn if no matches are found. + Do not warn if no matches are found. - patterns + patterns A list of library name patterns. - The get_libs command returns a list of clocks that match patterns. + The get_libs command returns a list of clocks that match patterns. + - get_nets + get_nets - [-hierarchical][-hsc separator][-filter expr][-regexp][-nocase][-quiet][-of_objects objects][patterns] + [-hierarchical][-hsc separator][-filter expr][-regexp][-nocase][-quiet][-of_objects objects][patterns] - -hierarchical + -hierarchical - Searches hierarchy levels below the current instance for matches. + Searches hierarchy levels below the current instance for matches. - -hsc separator + -hsc separator - Character that separates the library name, cell name and port name in pattern. Defaults to ‘/’. + Character that separates the library name, cell name and port name in pattern. Defaults to ‘/’. - -filter expr + -filter expr - A filter expression of the form “property==value”where property is a property supported by the get_property command. See the section “Filter Expressions” for additional forms. + A filter expression of the form “property==value”where property is a property supported by the get_property command. See the section “Filter Expressions” for additional forms. - -regexp + -regexp - Use regular expression matching instead of glob pattern matching. + Use regular expression matching instead of glob pattern matching. - -nocase + -nocase - Ignore case when matching. Only valid with –regexp. + Ignore case when matching. Only valid with –regexp. - -quiet + -quiet - Do not warn if no matches are found. + Do not warn if no matches are found. - -of_objects objects + -of_objects objects The name of a pin or instance, a list of pins returned by get_pins, or a list of instances returned by get_cells. The –hierarchical option cannot be used with –of_objects. @@ -7853,97 +8023,98 @@ - patterns + patterns A list of net name patterns. - The get_nets command returns a list of all nets that match patterns. + The get_nets command returns a list of all nets that match patterns. - get_name + get_name - object + object - object + object A library, cell, port, instance, pin or timing arc object. - Return the name of object. Equivalent to [get_property object name]. + Return the name of object. Equivalent to [get_property object name]. + - get_pins + get_pins - [-hierarchical][-hsc separator][-filter expr][-regexp][-nocase][-quiet][-of_objects objects][patterns] + [-hierarchical][-hsc separator][-filter expr][-regexp][-nocase][-quiet][-of_objects objects][patterns] - -hierarchical + -hierarchical - Searches hierarchy levels below the current instance for matches. + Searches hierarchy levels below the current instance for matches. - -hsc separator + -hsc separator - Character that separates the library name, cell name and port name in pattern. Defaults to ‘/’. + Character that separates the library name, cell name and port name in pattern. Defaults to ‘/’. - -filter expr + -filter expr - A filter expression of the form “property==value”where property is a property supported by the get_property command. See the section “Filter Expressions” for additional forms. + A filter expression of the form “property==value”where property is a property supported by the get_property command. See the section “Filter Expressions” for additional forms. - -nocase + -nocase - Ignore case when matching. Only valid with –regexp. + Ignore case when matching. Only valid with –regexp. - -quiet + -quiet - Do not warn if no matches are found. + Do not warn if no matches are found. - -of_objects objects + -of_objects objects - The name of a net or instance, a list of nets returned by get_nets, or a list of instances returned by get_cells. The –hierarchical option cannot be used with –of_objects. + The name of a net or instance, a list of nets returned by get_nets, or a list of instances returned by get_cells. The –hierarchical option cannot be used with –of_objects. - patterns + patterns A list of pin name patterns. @@ -7951,63 +8122,63 @@ The get_pins command returns a list of all instance pins that match patterns. - A useful idiom to find the driver pin for a net is the following. - get_pins -of_objects [get_net net_name] -filter “direction==output” + A useful idiom to find the driver pin for a net is the following. + get_pins -of_objects [get_net net_name] -filter “direction==output” + + + get_ports + + + [-filter expr][-regexp][-nocase][-quiet][-of_objects objects][patterns] + + - - get_ports + + -filter expr - - [-filter expr][-regexp][-nocase][-quiet][-of_objects objects][patterns] + + A filter expression of the form “property==value”where property is a property supported by the get_property command. See the section “Filter Expressions” for additional forms. - -filter expr + -regexp - A filter expression of the form “property==value”where property is a property supported by the get_property command. See the section “Filter Expressions” for additional forms. + Use regular expression matching instead of glob pattern matching. - -regexp + -nocase - Use regular expression matching instead of glob pattern matching. + Ignore case when matching. Only valid with –regexp. - -nocase + -quiet - Ignore case when matching. Only valid with –regexp. + Do not warn if no matches are found. - -quiet + -of_objects objects - Do not warn if no matches are found. + The name of net or a list of nets returned by get_nets. - -of_objects objects - - - The name of net or a list of nets returned by get_nets. - - - - - patterns + patterns A list of port name patterns. @@ -8020,31 +8191,31 @@ - get_property + get_property - [-object_type object_type]objectproperty + [-object_type object_type]objectproperty - -object_type object_type + -object_type object_type - The type of object when it is specified as a name.cell|pin|net|port|clock|library|library_cell|library_pin|timing_arc + The type of object when it is specified as a name.cell|pin|net|port|clock|library|library_cell|library_pin|timing_arc - object + object - An object returned by get_cells, get_pins, get_nets, get_ports, get_clocks, get_libs, get_lib_cells, get_lib_pins, or get_timing_arcs, or object name. ‑object_type is required if object is a name. + An object returned by get_cells, get_pins, get_nets, get_ports, get_clocks, get_libs, get_lib_cells, get_lib_pins, or get_timing_arcs, or object name. ‑object_type is required if object is a name. - property + property A property name. @@ -8052,89 +8223,119 @@ The properties for different objects types are shown below. - cell (SDC lib_cell) - base_namefilenamefull_namelibraryname - clock - full_nameis_generatedis_propagatedis_virtualnameperiodsources - edge - delay_max_falldelay_min_falldelay_max_risedelay_min_risefull_namefrom_pinsenseto_pin - instance (SDC cell) - cellfull_nameis_bufferis_clock_gateis_hierarchicalis_inverteris_macrois_memoryliberty_cellnameref_name - liberty_cell (SDC lib_cell) - areabase_namedont_usefilenamefull_nameis_bufferis_inverteris_memorylibraryname - liberty_port (SDC lib_pin) - capacitancedirectiondrive_resistancedrive_resistance_max_falldrive_resistance_max_risedrive_resistance_min_falldrive_resistance_min_risefull_nameintrinsic_delayintrinsic_delay_max_fallintrinsic_delay_max_riseintrinsic_delay_min_fallintrinsic_delay_min_riseis_register_clocklib_cellname - library - filename (Liberty library only)namefull_name - net - full_namename + cell (SDC lib_cell) + base_namefilenamefull_namelibraryname + clock + full_nameis_generatedis_propagatedis_virtualnameperiodsources + edge + delay_max_falldelay_min_falldelay_max_risedelay_min_risefull_namefrom_pinsenseto_pin + instance (SDC cell) + cellfull_nameis_bufferis_clock_gateis_hierarchicalis_inverteris_macrois_memoryliberty_cellnameref_name + liberty_cell (SDC lib_cell) + areabase_namedont_usefilenamefull_nameis_bufferis_inverteris_memorylibraryname + liberty_port (SDC lib_pin) + capacitancedirectiondrive_resistancedrive_resistance_max_falldrive_resistance_max_risedrive_resistance_min_falldrive_resistance_min_risefull_nameintrinsic_delayintrinsic_delay_max_fallintrinsic_delay_max_riseintrinsic_delay_min_fallintrinsic_delay_min_riseis_register_clocklib_cellname + library + filename (Liberty library only)namefull_name + net + full_namename path (PathEnd) endpointendpoint_clockendpoint_clock_pinslackstartpointstartpoint_clockpoints - pin - activity (activity in transitions per second, duty cycle, origin)slew_max_fallslew_max_riseslew_min_fallslew_min_riseclocksclock_domainsdirectionfull_nameis_hierarchicalis_portis_register_clocklib_pin_namenameslack_maxslack_max_fallslack_max_riseslack_minslack_min_fallslack_min_rise - port - activityslew_max_fallslew_max_riseslew_min_fallslew_min_risedirectionfull_nameliberty_portnameslack_maxslack_max_fallslack_max_riseslack_minslack_min_fallslack_min_rise - point (PathRef) - arrivalpinrequiredslack + pin + activity (activity in transitions per second, duty cycle, origin)slew_max_fallslew_max_riseslew_min_fallslew_min_riseclocksclock_domainsdirectionfull_nameis_hierarchicalis_portis_register_clocklib_pin_namenameslack_maxslack_max_fallslack_max_riseslack_minslack_min_fallslack_min_rise + port + activityslew_max_fallslew_max_riseslew_min_fallslew_min_risedirectionfull_nameliberty_portnameslack_maxslack_max_fallslack_max_riseslack_minslack_min_fallslack_min_rise + point (PathRef) + arrivalpinrequiredslack + + + + + + get_scenes + + + [-mode mode_name]scene_name + + + + + mode_name + + + Get the scenes for mode_name. + + + + + scene_name + + + A scene name pattern. + + + + The get_scenes command is used to find the scenes matching a pattern or that use an SDC mode. - get_timing_edges + get_timing_edges - [-from from_pins][-to to_pins][-of_objects objects][-filter expr][patterns] + [-from from_pins][-to to_pins][-of_objects objects][-filter expr][patterns] - -from from_pin + -from from_pin - A list of pins. + A list of pins. - -to to_pin + -to to_pin - A list of pins. + A list of pins. - -of_objects objects + -of_objects objects - A list of instances or library cells. The –from and -to options cannot be used with –of_objects. + A list of instances or library cells. The –from and -to options cannot be used with –of_objects. - -filter expr + -filter expr - A filter expression of the form “property==value”where property is a property supported by the get_property command. See the section “Filter Expressions” for additional forms. + A filter expression of the form “property==value”where property is a property supported by the get_property command. See the section “Filter Expressions” for additional forms. - The get_timing_edges command returns a list of timing edges (arcs) to, from or between pins. The result can be passed to get_property or set_disable_timing. + The get_timing_edges command returns a list of timing edges (arcs) to, from or between pins. The result can be passed to get_property or set_disable_timing. + - group_path + group_path - -name group_name[-weight weight][-critical_range range][-from from_list |-rise_from from_list |-fall_from from_list][-through through_list][-rise_through through_list][-fall_through through_list][-to to_list |-rise_to to_list |-fall_to to_list][-default] + -name group_name[-weight weight][-critical_range range][-from from_list |-rise_from from_list |-fall_from from_list][-through through_list][-rise_through through_list][-fall_through through_list][-to to_list |-rise_to to_list |-fall_to to_list][-default] - -name group_name + -name group_name The name of the path group. @@ -8142,7 +8343,7 @@ - -weight weight + -weight weight Not supported. @@ -8150,7 +8351,7 @@ - -critical_range range + -critical_range range Not supported. @@ -8158,216 +8359,215 @@ - -from from_list + -from from_list - Group paths from a list of clocks, instances, ports, register clock pins, or latch data pins. + Group paths from a list of clocks, instances, ports, register clock pins, or latch data pins. - -rise_from from_list + -rise_from from_list - Group paths from the rising edge of clocks, instances, ports, register clock pins, or latch data pins. + Group paths from the rising edge of clocks, instances, ports, register clock pins, or latch data pins. - -fall_from from_list + -fall_from from_list - Group paths from the falling edge of clocks, instances, ports, register clock pins, or latch data pins. + Group paths from the falling edge of clocks, instances, ports, register clock pins, or latch data pins. - -through through_list + -through through_list - Group paths through a list of instances, pins or nets. + Group paths through a list of instances, pins or nets. - -rise_through through_list + -rise_through through_list - Group rising paths through a list of instances, pins or nets. + Group rising paths through a list of instances, pins or nets. - -fall_through through_list + -fall_through through_list - Group falling paths through a list of instances, pins or nets. + Group falling paths through a list of instances, pins or nets. - -to to_list + -to to_list - Group paths to a list of clocks, instances, ports or pins. + Group paths to a list of clocks, instances, ports or pins. - -rise_to to_list + -rise_to to_list - Group rising paths to a list of clocks, instances, ports or pins. + Group rising paths to a list of clocks, instances, ports or pins. - -fall_to to_list + -fall_to to_list - Group falling paths to a list of clocks, instances, port-s or pins. + Group falling paths to a list of clocks, instances, port-s or pins. - - -default + -default - Restore the paths in the path group -from/-to/-through/-to to their default path group. + Restore the paths in the path group -from/-to/-through/-to to their default path group. - The group_path command is used to group paths reported by the report_checks command. See set_false_path for a description of allowed from_list, through_list and to_list objects. + The group_path command is used to group paths reported by the report_checks command. See set_false_path for a description of allowed from_list, through_list and to_list objects. - include + include - [-echo|-e][-verbose|-v]filename[> log_filename][>> log_filename] + [-echo|-e][-verbose|-v]filename[> log_filename][>> log_filename] - -echo|-e + -echo|-e - Print each command before evaluating it. + Print each command before evaluating it. - -verbose|-v + -verbose|-v - Print each command before evaluating it as well as the result it returns. + Print each command before evaluating it as well as the result it returns. - filename + filename - The name of the file containing commands to read. + The name of the file containing commands to read. - > log_filename + > log_filename - Redirect command output to log_filename. + Redirect command output to log_filename. - >> log_filename + >> log_filename - Redirect command output and append log_filename. + Redirect command output and append log_filename. - Read STA/SDC/Tcl commands from filename. - The include command stops and reports any errors encountered while reading a file unless sta_continue_on_error is 1. + Read STA/SDC/Tcl commands from filename. + The include command stops and reports any errors encountered while reading a file unless sta_continue_on_error is 1. - link_design + link_design - [-no_black_boxes][cell_name] + [-no_black_boxes][cell_name] - -no_black_boxes + -no_black_boxes - Do not make empty “black box” cells for instances that reference undefined cells. + Do not make empty “black box” cells for instances that reference undefined cells. - cell_name + cell_name - The top level module/cell name of the design hierarchy to link. + The top level module/cell name of the design hierarchy to link. - Link (elaborate, flatten) the the top level cell cell_name. The design must be linked after reading netlist and library files. The default value of cell_name is the current design. + Link (elaborate, flatten) the the top level cell cell_name. The design must be linked after reading netlist and library files. The default value of cell_name is the current design. The linker creates empty "block box" cells for instances the reference undefined cells when the variable link_create_black_boxes is true. When link_create_black_boxes is false an error is reported and the link fails. The link_design command returns 1 if the link succeeds and 0 if it fails. - - make_instance + make_instance - inst_pathlib_cell + inst_pathlib_cell - inst_path + inst_path A hierarchical instance name. + - lib_cell + lib_cell The library cell of the new instance. - The make_instance command makes an instance of library cell lib_cell. + The make_instance command makes an instance of library cell lib_cell. - make_net + make_net - net_name_list + net_name_list - net_name_list + net_name_list A list of net names. @@ -8380,48 +8580,48 @@ - read_liberty + read_liberty - [-corner corner][-min][-max][-infer_latches]filename + [-corner corner][-min][-max][-infer_latches]filename - -corner corner + -corner corner - Use the library for process corner corner delay calculation. + Use the library for process corner corner delay calculation. - -min + -min - Use library for min delay calculation. + Use library for min delay calculation. - -max + -max - Use library for max delay calculation. + Use library for max delay calculation. - filename + filename - The liberty file name to read. + The liberty file name to read. The read_liberty command reads a Liberty format library file. The first library that is read sets the units used by SDC/TCL commands and reporting. The include_file attribute is supported. - Some Liberty libraries do not include latch groups for cells that are describe transparent latches. In that situation the -infer_latches command flag can be used to infer the latches. The timing arcs required for a latch to be inferred should look like the following: - cell (infered_latch) { pin(D) { direction : input ; timing () { related_pin : "E" ; timing_type : setup_falling ; } timing () { related_pin : "E" ; timing_type : hold_falling ; } } pin(E) { direction : input; } pin(Q) { direction : output ; timing () { related_pin : "D" ; } timing () { related_pin : "E" ; timing_type : rising_edge ; } }} + Some Liberty libraries do not include latch groups for cells that are describe transparent latches. In that situation the -infer_latches command flag can be used to infer the latches. The timing arcs required for a latch to be inferred should look like the following: + cell (infered_latch) { pin(D) { direction : input ; timing () { related_pin : "E" ; timing_type : setup_falling ; } timing () { related_pin : "E" ; timing_type : hold_falling ; } } pin(E) { direction : input; } pin(Q) { direction : output ; timing () { related_pin : "D" ; } timing () { related_pin : "E" ; timing_type : rising_edge ; } }} In this example a positive level-sensitive latch is inferred. Files compressed with gzip are automatically uncompressed. @@ -8429,247 +8629,232 @@ - read_saif + read_saif - [-scope scope]filename + [-scope scope]filename - scope + scope - The SAIF scope of the current design to extract simulation data. Typically the test bench name and design under test instance name. Scope levels are separated with ‘/’. + The SAIF scope of the current design to extract simulation data. Typically the test bench name and design under test instance name. Scope levels are separated with ‘/’. - filename + filename - The name of the SAIF file to read. + The name of the SAIF file to read. - The read_saif command reads a SAIF (Switching Activity Interchange Format) file from a Verilog simulation and extracts pin activities and duty cycles for use in power estimation. Files compressed with gzip are supported. Annotated activities are propagated to the fanout of the annotated pins. + The read_saif command reads a SAIF (Switching Activity Interchange Format) file from a Verilog simulation and extracts pin activities and duty cycles for use in power estimation. Files compressed with gzip are supported. Annotated activities are propagated to the fanout of the annotated pins. + - read_sdc + read_sdc - [-echo]filename + [-mode mode_name][-echo]filename - -echo + mode_name - Print each command before evaluating it. + Mode for the SDC commands in the file. - filename + -echo - SDC command file. + Print each command before evaluating it. + + + + + filename + + + SDC command file. - Read SDC commands from filename. + Read SDC commands from filename. + If the mode does not exist it is created. Multiple SDC files can append commands to a mode by using the -mode_name argument for each one. If no -mode arguement is is used the commands are added to the current mode. The read_sdc command stops and reports any errors encountered while reading a file unless sta_continue_on_error is 1. Files compressed with gzip are automatically uncompressed. - - read_sdf + read_sdf - [-corner corner][-unescaped_dividers]filename + [-scene scene][-unescaped_dividers]filename - -corner corner + scene - Process corner delays to annotate. + Scene delays to annotate. - -unescaped_dividers + -unescaped_dividers - With this option path names in the SDF do not have to escape hierarchy dividers when the path name is escaped. For example, the escaped Verilog name "\inst1/inst2 " can be referenced as "inst1/inst2". The correct SDF name is "inst1\/inst2", since the divider does not represent a change in hierarchy in this case. + With this option path names in the SDF do not have to escape hierarchy dividers when the path name is escaped. For example, the escaped Verilog name "\inst1/inst2 " can be referenced as "inst1/inst2". The correct SDF name is "inst1\/inst2", since the divider does not represent a change in hierarchy in this case. - filename + filename - The name of the SDF file to read. + The name of the SDF file to read. - Read SDF delays from a file. The min and max values in the SDF tuples are used to annotate the delays for corner. The typical values in the SDF tuples are ignored. If multiple corners are defined -corner must be specified. + Read SDF delays from a file. The min and max values in the SDF tuples are used to annotate the delays for corner. The typical values in the SDF tuples are ignored. If multiple scenes are defined -scene must be specified. SDC annotation for mcmm analysis must follow the scene definitions. Files compressed with gzip are automatically uncompressed. INCREMENT is supported as an alias for INCREMENTAL. - The following SDF statements are not supported. + The following SDF statements are not supported. PORTINSTANCE wildcards - read_spef + read_spef - [-min][-max][-path path][-corner corner][-keep_capacitive_coupling][-coupling_reduction_factor factor][-reduce]filename + [-name name][-keep_capacitive_coupling][-coupling_reduction_factor factor][-reduce][-path path]filename - + - -min + name - Annotate parasitics for min delays. + The name of the SPEF parasitics to use for defining scenes. The default is the base name of filename. - + - -max + path - Annotate parasitics for max delays. + Hierarchical block instance path to annotate with parasitics. - + - path + ‑keep_capacitive_coupling - Hierarchical block instance path to annotate with parasitics. + Keep coupling capacitors in parasitic networks rather than converting them to grounded capacitors. - + - -corner corner + ‑coupling_reduction_factorfactor - Annotate parasitics for one process corner. + Factor to multiply coupling capacitance by when reducing parasitic networks. The default value is 1.0. - - + - ‑keep_capacitive_coupling + filename - Keep coupling capacitors in parasitic networks rather than converting them to grounded capacitors. - - - - - ‑coupling_reduction_factorfactor - - - Factor to multiply coupling capacitance by when reducing parasitic networks. The default value is 1.0. - - - - - -reduce - - - Reduce detailed parasitics and do not save the detailed parastic network. - - - - - filename - - - The name of the parasitics file to read. + The name of the parasitics file to read. - The read_spef command reads a file of net parasitics in SPEF format. Use the ‑report_parasitic_annotation command to check for nets that are not annotated. + The read_spef command reads a file of net parasitics in SPEF format. Use the ‑report_parasitic_annotation command to check for nets that are not annotated. Files compressed with gzip are automatically uncompressed. - Separate parasitics can be annotated for corners and min and max paths using the -corner, –min and -max arguments. To use the same parastiics for every corner and for min/max delay calculation read the SPEF without -corner, -min, and -max options. - read_spef spef1 - To use separate parastics for min/max delay, use the -min, and -max options for each SPEF file. - read_spef -min spef1read_spef -max spef2 - To use separate parastics for each corner, use the -corner option for each SPEF file. - read_spef -corner ss spef1read_spef -corner tt spef2read_spef -corner ff spef3 - To use separate parastics for each corner and separate min/max delay calculation, use the -corner option along with the -min, and -max options. - read_spef -corner ss -min spef1read_spef -corner ss -max spef2read_spef -corner ff -min spef3read_spef -corner ff -max spef4 - With the -reduce option, the current delay calculator reduces the parastic network to the appropriate type and deletes the parasitic network. This substantially reduces the memory required to store the parasitics. - Coupling capacitors are multiplied by the –coupling_reduction_factor when a parasitic network is reduced. + Separate min/max parasitics can be annotated for each scene mode/corner. + read_spef -name min spef1read_spef -name max spef2define_scene -mode mode1 -spef_min min -spef_max max + Coupling capacitors are multiplied by the –coupling_reduction_factor when a parasitic network is reduced. The following SPEF constructs are ignored. - *DESIGN_FLOW (all values are ignored)*S slews*D driving cell*I pin capacitances (library cell capacitances are used instead)*Q r_net load poles*K r_net load residues - If the SPEF file contains triplet values the first value is used. - Parasitic networks (DSPEF) can be annotated on hierarchical blocks using the -path argument to specify the instance path to the block. Parasitic networks in the higher level netlist are stitched together at the hierarchical pins of the blocks. + *DESIGN_FLOW (all values are ignored)*S slews*D driving cell*I pin capacitances (library cell capacitances are used instead)*Q r_net load poles*K r_net load residues + If the SPEF file contains triplet values the first value is used. + Parasitic networks (DSPEF) can be annotated on hierarchical blocks using the -path argument to specify the instance path to the block. Parasitic networks in the higher level netlist are stitched together at the hierarchical pins of the blocks. - read_vcd + read_vcd - [-scope scope]filename + [-scope scope][-mode mode_name]filename - scope + scope - The VCD scope of the current design to extract simulation data. Typically the test bench name and design under test instance name. Scope levels are separated with ‘/’. + The VCD scope of the current design to extract simulation data. Typically the test bench name and design under test instance name. Scope levels are separated with ‘/’. - filename + mode_name - The name of the VCD file to read. + Mode to annotate activities. + + + + + filename + + + The name of the VCD file to read. - The read_vcd command reads a VCD (Value Change Dump) file from a Verilog simulation and extracts pin activities and duty cycles for use in power estimation. Files compressed with gzip are supported. Annotated activities are propagated to the fanout of the annotated pins. + The read_vcd command reads a VCD (Value Change Dump) file from a Verilog simulation and extracts pin activities and duty cycles for use in power estimation. Files compressed with gzip are supported. Annotated activities are propagated to the fanout of the annotated pins. - read_verilog + read_verilog - filename + filename - filename + filename - The name of the verilog file to read. + The name of the verilog file to read. - The read_verilog command reads a gate level verilog netlist. After all verilog netlist and Liberty libraries are read the design must be linked with the link_design command. - Verilog 2001 module port declaratations are supported. An example is shown below. + The read_verilog command reads a gate level verilog netlist. After all verilog netlist and Liberty libraries are read the design must be linked with the link_design command. + Verilog 2001 module port declaratations are supported. An example is shown below. module top (input in1, in2, clk1, clk2, clk3, output out); Files compressed with gzip are automatically uncompressed. @@ -8677,699 +8862,707 @@ - replace_cell + replace_cell - instance_listreplacement_cell + instance_listreplacement_cell + + + + + + instance_list + + + A list of instances to swap the cell. - instance_list + replacement_cell - A list of instances to swap the cell. - - - - - replacement_cell - - - The replacement lib cell. + The replacement lib cell. - The replace_cell command changes the cell of an instance. The replacement cell must have the same port list (number, name, and order) as the instance's existing cell for the replacement to be successful. + The replace_cell command changes the cell of an instance. The replacement cell must have the same port list (number, name, and order) as the instance's existing cell for the replacement to be successful. - - replace_activity_annotation + replace_activity_annotation - [-report_unannotated][-report_annotated] + [-report_unannotated][-report_annotated] - -report_unannotated + -report_unannotated - Report unannotated pins. + Report unannotated pins. - -report_unannotated + -report_unannotated - Report annotated pins. + Report annotated pins. - Report a summary of pins that are annotated by read_vcd, read_saif or set_power_activity. Sequential internal pins and hierarchical pins are ignored. + Report a summary of pins that are annotated by read_vcd, read_saif or set_power_activity. Sequential internal pins and hierarchical pins are ignored. - report_annotated_check + report_annotated_check - [-setup][-hold][-recovery][-removal][-nochange][-width][-period][-max_skew][-max_line lines][-report_annotated][-report_unannotated][-constant_arcs] + [-setup][-hold][-recovery][-removal][-nochange][-width][-period][-max_skew][-max_line lines][-report_annotated][-report_unannotated][-constant_arcs] - -setup + -setup - Report annotated setup checks. + Report annotated setup checks. - -hold + -hold - Report annotated hold checks. + Report annotated hold checks. - -recovery + -recovery - Report annotated recovery checks. + Report annotated recovery checks. - -removal + -removal - Report annotated removal checks. + Report annotated removal checks. - -nochange + -nochange - Report annotated nochange checks. + Report annotated nochange checks. - -width + -width - Report annotated width checks. + Report annotated width checks. - -period + -period - Report annotated period checks. + Report annotated period checks. - -max_skew + -max_skew - Report annotated max skew checks. - - - - - -max_line lines - - - Maximum number of lines listed by the –report_annotated and ‑report_unannotated options. - - - - - -report_annotated - - - Report annotated timing arcs. - - - - - -report_unannotated - - - Report unannotated timing arcs. + Report annotated max skew checks. - -constant_arcs + -max_line lines - Report separate annotation counts for arcs disabled by logic constants (set_logic_one, set_logic_zero). + Maximum number of lines listed by the –report_annotated and ‑report_unannotated options. + + + + + -report_annotated + + + Report annotated timing arcs. + + + + + -report_unannotated + + + Report unannotated timing arcs. + + + + + -constant_arcs + + + Report separate annotation counts for arcs disabled by logic constants (set_logic_one, set_logic_zero). - The report_annotated_check command reports a summary of SDF timing check annotation. The -report_annotated and –report_annotated options can be used to list arcs that are annotated or not annotated. + The report_annotated_check command reports a summary of SDF timing check annotation. The -report_annotated and –report_annotated options can be used to list arcs that are annotated or not annotated. - report_annotated_delay + report_annotated_delay - [-cell][-net][-from_in_ports][-to_out_ports][-max_lines lines][-report_annotated][-report_unannotated][-constant_arcs] + [-cell][-net][-from_in_ports][-to_out_ports][-max_lines lines][-report_annotated][-report_unannotated][-constant_arcs] - -cell + -cell - Report annotated cell delays. + Report annotated cell delays. - -net + -net - Report annotated internal net delays. + Report annotated internal net delays. - -from_in_ports + -from_in_ports - Report annotated delays from input ports. + Report annotated delays from input ports. - -to_out_ports + -to_out_ports - Report annotated delays to output ports. + Report annotated delays to output ports. - -max_lines lines + -max_lines lines - Maximum number of lines listed by the –report_annotated and ‑report_unannotated options. + Maximum number of lines listed by the –report_annotated and ‑report_unannotated options. - -report_annotated + -report_annotated - Report annotated timing arcs. + Report annotated timing arcs. - -report_unannotated + -report_unannotated - Report unannotated timing arcs. + Report unannotated timing arcs. - -constant_arcs + -constant_arcs Report separate annotation counts for arcs disabled by logic constants (set_logic_one, set_logic_zero). - The report_annotated_delay command reports a summary of SDF delay annotation. Without the ‑from_in_ports and –to_out_ports options arcs to and from top level ports are not reported. The ‑report_annotated and –report_unannotated options can be used to list arcs that are annotated or not annotated. + The report_annotated_delay command reports a summary of SDF delay annotation. Without the ‑from_in_ports and –to_out_ports options arcs to and from top level ports are not reported. The ‑report_annotated and –report_unannotated options can be used to list arcs that are annotated or not annotated. - report_checks + report_checks - [-from from_list |-rise_from from_list |-fall_from from_list][-through through_list |-rise_through through_list |-fall_through through_list][-to to_list |-rise_to to_list |-fall_to to_list][-unconstrained][-path_delay min|min_rise|min_fall |max|max_rise|max_fall |min_max][-group_path_count path_count][-endpoint_path_count endpoint_path_count][-unique_paths_to_endpoint][-unique_edges_to_endpoint][-corner corner][-slack_max max_slack][-slack_min min_slack][-sort_by_slack][-path_group groups][-format end|full|short|summary |full_clock|full_clock_expanded |json][-fields fields][-digits digits][-no_line_split][> filename][>> filename] + [-from from_list |-rise_from from_list |-fall_from from_list][-through through_list |-rise_through through_list |-fall_through through_list][-to to_list |-rise_to to_list |-fall_to to_list][-unconstrained][-path_delay min|min_rise|min_fall |max|max_rise|max_fall |min_max][-group_path_count path_count][-endpoint_path_count endpoint_path_count][-unique_paths_to_endpoint][-unique_edges_to_endpoint][-scenes scenes][-slack_max max_slack][-slack_min min_slack][-sort_by_slack][-path_group groups][-format end|full|short|summary |full_clock|full_clock_expanded |json][-fields fields][-digits digits][-no_line_split][> filename][>> filename] - -from from_list + -from from_list - Report paths from a list of clocks, instances, ports, register clock pins, or latch data pins. + Report paths from a list of clocks, instances, ports, register clock pins, or latch data pins. - -rise_from from_list + -rise_from from_list - Report paths from the rising edge of clocks, instances, ports, register clock pins, or latch data pins. + Report paths from the rising edge of clocks, instances, ports, register clock pins, or latch data pins. - -fall_from from_list + -fall_from from_list - Report paths from the falling edge of clocks, instances, ports, register clock pins, or latch data pins. + Report paths from the falling edge of clocks, instances, ports, register clock pins, or latch data pins. - -through through_list + -through through_list - Report paths through a list of instances, pins or nets. + Report paths through a list of instances, pins or nets. - -rise_through through_list + -rise_through through_list - Report rising paths through a list of instances, pins or nets. + Report rising paths through a list of instances, pins or nets. - -fall_through through_list + -fall_through through_list - Report falling paths through a list of instances, pins or nets. + Report falling paths through a list of instances, pins or nets. - -to to_list + -to to_list - Report paths to a list of clocks, instances, ports or pins. + Report paths to a list of clocks, instances, ports or pins. - -rise_to to_list + -rise_to to_list - Report rising paths to a list of clocks, instances, ports or pins. + Report rising paths to a list of clocks, instances, ports or pins. - -fall_to to_list + -fall_to to_list - Report falling paths to a list of clocks, instances, ports or pins. + Report falling paths to a list of clocks, instances, ports or pins. - -unconstrained + -unconstrained - Report unconstrained paths also. The unconstrained path group is not reported without this option. + Report unconstrained paths also. The unconstrained path group is not reported without this option. - -path_delay min + -path_delay min - Report min path (hold) checks. + Report min path (hold) checks. - -path_delay min_rise + -path_delay min_rise - Report min path (hold) checks for rising endpoints. + Report min path (hold) checks for rising endpoints. - -path_delay min_fall + -path_delay min_fall - Report min path (hold) checks for falling endpoints. + Report min path (hold) checks for falling endpoints. - -path_delay max + -path_delay max - Report max path (setup) checks. + Report max path (setup) checks. - -path_delay max_rise + -path_delay max_rise - Report max path (setup) checks for rising endpoints. + Report max path (setup) checks for rising endpoints. - -path_delay max_fall + -path_delay max_fall - Report max path (setup) checks for falling endpoints. + Report max path (setup) checks for falling endpoints. - -path_delay min_max + -path_delay min_max - Report max and max path (setup and hold) checks. + Report max and max path (setup and hold) checks. - -group_path_count path_count + -group_path_count path_count - The number of paths to report in each path group. The default is 1. + The number of paths to report in each path group. The default is 1. - -endpoint_path_count endpoint_path_count + -endpoint_path_count endpoint_path_count - The number of paths to report for each endpoint. The default is 1. + The number of paths to report for each endpoint. The default is 1. - ‑unique_paths_to_endpoint + ‑unique_paths_to_endpoint - When multiple paths to an endpoint are specified with ‑endpoint_path_count, many of the paths may differ only in the rise/fall edges of the pins in the paths. With this option only the worst path through the set of pins is reported. + When multiple paths to an endpoint are specified with ‑endpoint_path_count, many of the paths may differ only in the rise/fall edges of the pins in the paths. With this option only the worst path through the set of pins is reported. - ‑unique_edges_to_endpoint + ‑unique_edges_to_endpoint - When multiple paths to an endpoint are specified with ‑endpoint_path_count, conditional timing arcs result in paths that through the same pins and rise/fall edges. With this option only the worst path through the set of pins and rise/fall edges is reported. + When multiple paths to an endpoint are specified with ‑endpoint_path_count, conditional timing arcs result in paths that through the same pins and rise/fall edges. With this option only the worst path through the set of pins and rise/fall edges is reported. - -corner corner + scenes - Report paths for one process corner. The default is to report paths for all process corners. - - - - - -slack_max max_slack - - - Only report paths with less slack than max_slack. + Report paths for one process corner. The default is to report paths for all process corners. - -slack_min min_slack + max_slack - Only report paths with more slack than min_slack. + Only report paths with less slack than max_slack. - -sort_by_slack + min_slack - Sort paths by slack rather than slack grouped by path group. + Only report paths with more slack than min_slack. - -path_group groups + -sort_by_slack - List of path groups to report. The default is to report all path groups. + Sort paths by slack rather than slack grouped by path group. - -format end + groups - Report path ends in one line with delay, required time and slack. + List of path groups to report. The default is to report all path groups. - -format full + -format end - Report path start and end points and the path. This is the default path type. + Report path ends in one line with delay, required time and slack. - -format full_clock + -format full - Report path start and end points, the path, and the source and and target clock paths. + Report path start and end points and the path. This is the default path type. - -format full_clock_expanded + -format full_clock - Report path start and end points, the path, and the source and and target clock paths. If the clock is generated and propagated, the path from the clock source pin is also reported. + Report path start and end points, the path, and the source and and target clock paths. - -format short + -format full_clock_expanded - Report only path start and end points. + Report path start and end points, the path, and the source and and target clock paths. If the clock is generated and propagated, the path from the clock source pin is also reported. - -format summary + -format short - Report only path ends with delay. + Report only path start and end points. - -format json + -format summary - Report in json format. -fields is ignored. + Report only path ends with delay. - -fields fields + -format json - List of capacitance|slew|input_pins|hierarchical_pins|nets|fanout|src_attr + Report in json format. -fields is ignored. - -digits digits + fields - The number of digits after the decimal point to report. The default value is the variable sta_report_default_digits. + List of capacitance|slew|input_pins|hierarchical_pins|nets|fanout|src_attr - -no_line_splits + digits - Do not split long lines into multiple lines. + The number of digits after the decimal point to report. The default value is the variable sta_report_default_digits. + + + + + -no_line_splits + + + Do not split long lines into multiple lines. - The report_checks command reports paths in the design. Paths are reported in groups by capture clock, unclocked path delays, gated clocks and unconstrained. - See set_false_path for a description of allowed from_list, through_list and to_list objects. + The report_checks command reports paths in the design. Paths are reported in groups by capture clock, unclocked path delays, gated clocks and unconstrained. + See set_false_path for a description of allowed from_list, through_list and to_list objects. - report_check_types + report_check_types - [-violators][-verbose][-format slack_only|end][-max_delay][-min_delay][-recovery][-removal][-clock_gating_setup][-clock_gating_hold][-max_slew][-min_slew][-min_pulse_width][-min_period][-digits digits][-no_split_lines][> filename][>> filename] + [-scenes scenes][-violators][-verbose][-format slack_only|end][-max_delay][-min_delay][-recovery][-removal][-clock_gating_setup][-clock_gating_hold][-max_slew][-min_slew][-min_pulse_width][-min_period][-digits digits][-no_split_lines][> filename][>> filename] - -violators + scenes - Report all violated timing and design rule constraints. + Report checks for some scens. The default value is all scenes. - -verbose + -violators - Use a verbose output format. + Report all violated timing and design rule constraints. - -format slack_only + -verbose - Report the minimum slack for each timing check. + Use a verbose output format. - -format end + -format slack_only - Report the endpoint for each check. + Report the minimum slack for each timing check. - -max_delay + -format end - Report setup and max delay path delay constraints. + Report the endpoint for each check. - -min_delay + -max_delay - Report hold and min delay path delay constraints. + Report setup and max delay path delay constraints. - -recovery + -min_delay - Report asynchronous recovery checks. + Report hold and min delay path delay constraints. - -removal + -recovery - Report asynchronous removal checks. + Report asynchronous recovery checks. - -clock_gating_setup + -removal - Report gated clock enable setup checks. + Report asynchronous removal checks. - -clock_gating_hold + -clock_gating_setup - Report gated clock hold setup checks. + Report gated clock enable setup checks. - -max_slew + -clock_gating_hold - Report max transition design rule checks. + Report gated clock hold setup checks. - -max_skew + -max_slew - Report max skew design rule checks. - - - - - -min_pulse_width - - - Report min pulse width design rule checks. + Report max transition design rule checks. - -min_period + -max_skew - Report min period design rule checks. + Report max skew design rule checks. - -min_slew + -min_pulse_width - Report min slew design rule checks. + Report min pulse width design rule checks. - -digits digits + -min_period - The number of digits after the decimal point to report. The default value is the variable sta_report_default_digits. + Report min period design rule checks. - -no_split_lines + -min_slew - Do not split long lines into multiple lines. + Report min slew design rule checks. + + + + + -digits digits + + + The number of digits after the decimal point to report. The default value is the variable sta_report_default_digits. + + + + + -no_split_lines + + + Do not split long lines into multiple lines. @@ -9379,84 +9572,93 @@ - report_clock_latency + report_clock_latency - [-clock clocks][-include_internal_latency][-digits digits] + [-clocks clocks][-scenes scenes][-include_internal_latency][-digits digits] - -clock clocks + clocks - The clocks to report. + The clocks to report. The default value is all c - -include_internal_latency + scenes - Include internal clock latency from liberty min/max_clock_tree_path timing groups. + Report clocks for scenes. The default value is all clocks in scenes modes. - -digits digits + -include_internal_latency - The number of digits to report for delays. + Include internal clock latency from liberty min/max_clock_tree_path timing groups. + + + + + digits + + + The number of digits to report for delays. - Report the clock network latency. + Report the clock network latency. - report_clock_min_period + report_clock_min_period - [-clocks clocks][-include_port_paths] + [-clocks clocks][-scenes scenes][-include_port_paths] - -clocks clocks + clocks - The clocks to report. + The clocks to report. - -include_port_paths + -include_port_paths - Include paths from input port and to output ports. + Include paths from input port and to output ports. - Report the minimum period and maximum frequency for clocks. If the -clocks argument is not specified all clocks are reported. The minimum period is determined by examining the smallest slack paths between registers the rising edges of the clock or between falling edges of the clock. Paths between different clocks, different clock edges of the same clock, level sensitive latches, or paths constrained by set_multicycle_path, set_max_path are not considered. + Report the minimum period and maximum frequency for clocks. If the -clocks argument is not specified all clocks are reported. The minimum period is determined by examining the smallest slack paths between registers the rising edges of the clock or between falling edges of the clock. Paths between different clocks, different clock edges of the same clock, level sensitive latches, or paths constrained by set_multicycle_path, set_max_path are not considered. + - report_clock_properties + report_clock_properties - [clock_names] + [clock_names] - clock_names + clock_names - List of clock names to report. + List of clock names to report. @@ -9464,114 +9666,122 @@ - - report_clock_skew + report_clock_skew - [-setup|-hold][-clock clocks][-include_internal_latency][-digits digits] + [-setup|-hold][-clocks clocks][-scenes scenes][-include_internal_latency][-digits digits] - -setup + -setup - Report skew for setup checks. + Report skew for setup checks. - -hold + -hold - Report skew for hold checks. + Report skew for hold checks. - -clock clocks + clocks - The clocks to report. + The clocks to report. The default value is all clocks in scenes modes. - -include_internal_latency + scenes - Include internal clock latency from liberty min/max_clock_tree_path timing groups. + Report clocks for scenes. The default value is all scenes. - -digits digits + -include_internal_latency - The number of digits to report for delays. + Include internal clock latency from liberty min/max_clock_tree_path timing groups. + + + + + -digits digits + + + The number of digits to report for delays. - Report the maximum difference in clock arrival between every source and target register that has a path between the source and target registers. + Report the maximum difference in clock arrival between every source and target register that has a path between the source and target registers. - report_dcalc + report_dcalc - [-from from_pin][-to to_pin][-corner corner][-min][-max][-digits digits][> filename][>> filename] + [-from from_pin][-to to_pin][-scene scene][-min][-max][-digits digits][> filename][>> filename] - -from from_pin + from_pin - Report delay calculations for timing arcs from instance input pin from_pin. + Report delay calculations for timing arcs from instance input pin from_pin. - -to to_pin + to_pin - Report delay calculations for timing arcs to instance output pin to_pin. + Report delay calculations for timing arcs to instance output pin to_pin. - -corner corner + scene - Report paths for process corner. The -corner keyword is required if more than one process corner is defined. + Report paths for process scene. The -scene keyword is required if more than one process corner is defined. + + + + + + -min + + + Report delay calculation for min delays. - -min + -max - Report delay calculation for min delays. + Report delay calculation for max delays. - -max + -digits digits - Report delay calculation for max delays. - - - - - -digits digits - - - The number of digits after the decimal point to report. The default is sta_report_default_digits. + The number of digits after the decimal point to report. The default is sta_report_default_digits. @@ -9579,64 +9789,63 @@ - - report_disabled_edges + report_disabled_edges - + The report_disabled_edges command reports disabled timing arcs along with the reason they are disabled. Each disabled timing arc is reported as the instance name along with the from and to ports of the arc. The disable reason is shown next. Arcs that are disabled with set_disable_timing are reported with constraint as the reason. Arcs that are disabled by constants are reported with constant as the reason along with the constant instance pin and value. Arcs that are disabled to break combinational feedback loops are reported with loop as the reason. - > report_disabled_edgesu1 A B constant B=0 + > report_disabled_edgesu1 A B constant B=0 - report_edges + report_edges - [-from from_pin][-to to_pin] + [-from from_pin][-to to_pin] - -from from_pin + -from from_pin - Report edges/timing arcs from pin from_pin. + Report edges/timing arcs from pin from_pin. - -to to_pin + -to to_pin - Report edges/timing arcs to pin to_pin. + Report edges/timing arcs to pin to_pin. - Report the edges/timing arcs and their delays in the timing graph from/to/between pins. + Report the edges/timing arcs and their delays in the timing graph from/to/between pins. - report_instance + report_instance - instance_path[> filename][>> filename] + instance_path[> filename][>> filename] - instance_path + instance_path - Hierarchical path to an instance. + Hierarchical path to an instance. @@ -9646,307 +9855,262 @@ - report_lib_cell + report_lib_cell - cell_name[> filename][>> filename] + cell_name[> filename][>> filename] + - cell_name + cell_name - The name of a library cell. + The name of a library cell. - Describe the liberty library cell cell_name. + Describe the liberty library cell cell_name. - report_net + report_net - [-digits digits]net_path[> filename][>> filename] - - - - - - -digits digits - - - The number of digits after the decimal point to report. The default value is the variable sta_report_default_digits. + [-digits digits]net_path[> filename][>> filename] - net_path + -digits digits - Hierarchical path to a net. + The number of digits after the decimal point to report. The default value is the variable sta_report_default_digits. + + + + + net_path + + + Hierarchical path to a net. - Report the connections and capacitance of a net. + Report the connections and capacitance of a net. - report_parasitic_annotation + report_parasitic_annotation - [-report_unannotated][> filename][>> filename] + [-report_unannotated][> filename][>> filename] - -report_unannotated + -report_unannotated - Report unannotated and partially annotated nets. + Report unannotated and partially annotated nets. - Report SPEF parasitic annotation completeness. + Report SPEF parasitic annotation completeness. - report_power + report_power - [-instances instances][-highest_power_instances count][-digits digits][> filename][>> filename] + [-instances instances][-highest_power_instances count][-digits digits][> filename][>> filename] - -instances instances + -instances instances - Report the power for each instance of instances. If the instance is hierarchical the total power for the instances inside the hierarchical instance is reported. + Report the power for each instance of instances. If the instance is hierarchical the total power for the instances inside the hierarchical instance is reported. - -highest_power_instances count + -highest_power_instances count - Report the power for the count highest power instances. + Report the power for the count highest power instances. - -digits digits + -digits digits - The number of digits after the decimal point to report. The default value is the variable sta_report_default_digits. + The number of digits after the decimal point to report. The default value is the variable sta_report_default_digits. - The report_power command uses static power analysis based on propagated or annotated pin activities in the circuit using Liberty power models. The internal, switching, leakage and total power are reported. Design power is reported separately for combinational, sequential, macro and pad groups. Power values are reported in watts. - The read_vcd or read_saif commands can be used to read activities from a file based on simulation. If no simulation activities are available, the set_power_activity command should be used to set the activity of input ports or pins in the design. The default input activity and duty for inputs are 0.1 and 0.5 respectively. The activities are propagated from annotated input ports or pins through gates and used in the power calculations. - Group Internal Switching Leakage Total Power Power Power Power----------------------------------------------------------------Sequential 3.29e-06 3.41e-08 2.37e-07 3.56e-06 92.4%Combinational 1.86e-07 3.31e-08 7.51e-08 2.94e-07 7.6%Macro 0.00e+00 0.00e+00 0.00e+00 0.00e+00 0.0%Pad 0.00e+00 0.00e+00 0.00e+00 0.00e+00 0.0%---------------------------------------------------------------Total 3.48e-06 6.72e-08 3.12e-07 3.86e-06 100.0% 90.2% 1.7% 8.1% - - - - - - report_pulse_width_checks - - - [-verbose][-digits digits][-no_line_splits][pins][> filename][>> filename] - - - - - -verbose - - - Use a verbose output format. - - - - - -digits digits - - - The number of digits after the decimal point to report. The default value is the variable sta_report_default_digits. - - - - - -no_line_splits - - - - - - - - pins - - - List of pins or ports to report. - - - - The report_pulse_width_checks command reports min pulse width checks for pins in the clock network. If pins is not specified all clock network pins are reported. + The report_power command uses static power analysis based on propagated or annotated pin activities in the circuit using Liberty power models. The internal, switching, leakage and total power are reported. Design power is reported separately for combinational, sequential, macro and pad groups. Power values are reported in watts. + The read_vcd or read_saif commands can be used to read activities from a file based on simulation. If no simulation activities are available, the set_power_activity command should be used to set the activity of input ports or pins in the design. The default input activity and duty for inputs are 0.1 and 0.5 respectively. The activities are propagated from annotated input ports or pins through gates and used in the power calculations. + Group Internal Switching Leakage Total Power Power Power Power----------------------------------------------------------------Sequential 3.29e-06 3.41e-08 2.37e-07 3.56e-06 92.4%Combinational 1.86e-07 3.31e-08 7.51e-08 2.94e-07 7.6%Macro 0.00e+00 0.00e+00 0.00e+00 0.00e+00 0.0%Pad 0.00e+00 0.00e+00 0.00e+00 0.00e+00 0.0%---------------------------------------------------------------Total 3.48e-06 6.72e-08 3.12e-07 3.86e-06 100.0% 90.2% 1.7% 8.1% - report_slews + report_slews - [-corner corner]pin + [-scenes scenes]pin - -corner corner + scenes - Report paths for process corner. The -corner keyword is required if more than one process corner is defined. + Report slews for process for scenes process corners.. - pin + pin - + - Report the slews at pin + Report the slews at pin - report_tns + report_tns - [-min][-max][-digits digits] + [-min][-max][-digits digits] - -max + -max - Report the total max/setup slack. + Report the total max/setup slack. - -min + -min - Report the total min/hold slack. + Report the total min/hold slack. - -digits digits + -digits digits - The number of digits after the decimal point to report. The default value is the variable sta_report_default_digits. + The number of digits after the decimal point to report. The default value is the variable sta_report_default_digits. - Report the total negative slack. + Report the total negative slack. - report_units + report_units - + - Report the units used for command arguments and reporting. - report_units time 1ns capacitance 1pF resistance 1kohm voltage 1v current 1A power 1pW distance 1um + Report the units used for command arguments and reporting. + report_units time 1ns capacitance 1pF resistance 1kohm voltage 1v current 1A power 1pW distance 1um - report_wns + report_wns - [-min][-max][-digits digits] + [-min][-max][-digits digits] - -max + -max - Report the worst max/setup slack. + Report the worst max/setup slack. - -min + -min - Report the worst min/hold slack. + Report the worst min/hold slack. - -digits digits + -digits digits - The number of digits after the decimal point to report. The default value is the variable sta_report_default_digits. + The number of digits after the decimal point to report. The default value is the variable sta_report_default_digits. - Report the worst negative slack. If the worst slack is positive, zero is reported. + Report the worst negative slack. If the worst slack is positive, zero is reported. - report_worst_slack + report_worst_slack - [-min][-max][-digits digits] + [-min][-max][-digits digits] - -max + -max - Report the worst max/setup slack. + Report the worst max/setup slack. - -min + -min - Report the worst min/hold slack. + Report the worst min/hold slack. - -digits digits + -digits digits - The number of digits after the decimal point to report. The default value is the variable sta_report_default_digits. + The number of digits after the decimal point to report. The default value is the variable sta_report_default_digits. @@ -9957,114 +10121,114 @@ - set_assigned_check + set_assigned_check - -setup|-hold|-recovery|-removal[-rise][-fall][-corner corner][-min][-max][-from from_pins][-to to_pins][-clock rise|fall][-cond sdf_cond][-worst]margin + -setup|-hold|-recovery|-removal[-rise][-fall][-scene scene][-min][-max][-from from_pins][-to to_pins][-clock rise|fall][-cond sdf_cond][-worst]margin - -setup + -setup - Annotate setup timing checks. + Annotate setup timing checks. - -hold + -hold - Annotate hold timing checks. + Annotate hold timing checks. - -recovery + -recovery - Annotate recovery timing checks. + Annotate recovery timing checks. - -removal + -removal - Annotate removal timing checks. + Annotate removal timing checks. - -rise + -rise - Annotate rising delays. + Annotate rising delays. - -fall + -fall - Annotate falling delays. + Annotate falling delays. - -corner corner + scene - The name of a process corner. The -corner keyword is required if more than one process corner is defined. + The name of a scene. The -scene keyword is required if more than one scene is defined. - -min + -min - Annotate the minimum value of the process corner. + Annotate the minimum value of the process corner. - -max + -max - Annotate the maximum value of the process corner. + Annotate the maximum value of the process corner. - -from from_pins + from_pins - A list of pins for the clock. + A list of pins for the clock. - -to to_pins + to_pins - A list of pins for the data. + A list of pins for the data. - -clock rise|fall + -clock rise|fall - The timing check clock pin transition. + The timing check clock pin transition. - margin + margin - The timing check margin. + The timing check margin. @@ -10075,161 +10239,160 @@ - set_assigned_delay + set_assigned_delay - -cell|-net[-rise][-fall][-corner corner][-min][-max][-from from_pins][-to to_pins]delay + -cell|-net[-rise][-fall][-scene scene][-min][-max][-from from_pins][-to to_pins]delay - -cell + -cell - Annotate the delays between two pins on an instance. + Annotate the delays between two pins on an instance. - -net + -net - Annotate the delays between two pins on a net. + Annotate the delays between two pins on a net. - -rise + -rise - Annotate the rising delays. + Annotate the rising delays. - -fall + -fall - Annotate the falling delays. + Annotate the falling delays. - -corner corner + scene - The name of a process corner. The -corner keyword is required if more than one process corner is defined. + The name of a scene. The -scene keyword is required if more than one scene is defined. - -min + -min - Annotate the minimum delays. + Annotate the minimum delays. - -max + -max - Annotate the maximum delays. + Annotate the maximum delays. - -from from_pins + from_pins - A list of pins. + A list of pins. - -to to_pins + to_pins - A list of pins. + A list of pins. - delay + delay - The delay between from_pins and to_pins. + The delay between from_pins and to_pins. The set_assigned_delay command is used to annotate the delays between two pins on an instance or net. The annotated delay overrides the calculated delay. This command is an interactive way to back-annotate delays like an SDF file. - Use the -corner keyword to specify a process corner. The -corner keyword is required if more than one process corner is defined. - set_assigned_transition + set_assigned_transition - [-rise][-fall][-corner corner][-min][-max]slewpin_list + [-rise][-fall][-scene scene][-min][-max]slewpin_list + + + + + -rise + + + Annotate the rising transition. - -rise + -fall - Annotate the rising transition. + Annotate the falling transition. - -fall + scene - Annotate the falling transition. + Annotate delays for scene. - -corner corner + -min - Annotate delays for process corner. + Annotate the minimum transition time. - -min + -max - Annotate the minimum transition time. + Annotate the maximum transition time. - -max + slew - Annotate the maximum transition time. + The pin transition time. - slew + pin_list - The pin transition time. - - - - - pin_list - - - A list of pins. + A list of pins. @@ -10239,89 +10402,89 @@ - set_case_analysis + set_case_analysis - 0|1|zero|one|rise|rising|fall|fallingport_or_pin_list + 0|1|zero|one|rise|rising|fall|fallingport_or_pin_list - port_or_pin_list + port_or_pin_list - A list of ports or pins. + A list of ports or pins. The set_case_analysis command sets the signal on a port or pin to a constant logic value. No paths are propagated from constant pins. Constant values set with the set_case_analysis command are propagated through downstream gates. - Conditional timing arcs with mode groups are controlled by logic values on the instance pins. + Conditional timing arcs with mode groups are controlled by logic values on the instance pins. - set_clock_gating_check + set_clock_gating_check - [-setup setup_time][-hold hold_time][-rise][-fall][-high][-low][objects] + [-setup setup_time][-hold hold_time][-rise][-fall][-high][-low][objects] - -setup setup_time + -setup setup_time - Clock enable setup margin. + Clock enable setup margin. - -hold hold_time + -hold hold_time - Clock enable hold margin. + Clock enable hold margin. - -rise + -rise - The setup/hold margin is for the rising edge of the clock enable. + The setup/hold margin is for the rising edge of the clock enable. - -fall + -fall - The setup/hold margin is for the falling edge of the clock enable. + The setup/hold margin is for the falling edge of the clock enable. + + + + + -high + + + The gating clock is active high (pin and instance objects only). - -high + -low - The gating clock is active high (pin and instance objects only). + The gating clock is active low (pin and instance objects only). - -low + objects - The gating clock is active low (pin and instance objects only). - - - - - objects - - - A list of clocks, instances, pins or ports. + A list of clocks, instances, pins or ports. @@ -10335,58 +10498,58 @@ - set_clock_groups + set_clock_groups - [-name name][-logically_exclusive][-physically_exclusive][-asynchronous][-allow_paths]-group clocks + [-name name][-logically_exclusive][-physically_exclusive][-asynchronous][-allow_paths]-group clocks - -name name + -name name - The clock group name. + The clock group name. - -logically_exclusive + -logically_exclusive - The clocks in different groups do not interact logically but can be physically present on the same chip. Paths between clock groups are considered for noise analysis. + The clocks in different groups do not interact logically but can be physically present on the same chip. Paths between clock groups are considered for noise analysis. - -physically_exclusive + -physically_exclusive - The clocks in different groups cannot be present at the same time on a chip. Paths between clock groups are not considered for noise analysis. + The clocks in different groups cannot be present at the same time on a chip. Paths between clock groups are not considered for noise analysis. - -asynchronous + -asynchronous - The clock groups are asynchronous. Paths between clock groups are considered for noise analysis. + The clock groups are asynchronous. Paths between clock groups are considered for noise analysis. - -allow_paths + -allow_paths - + - clocks + clocks - A list of clocks in the group. + A list of clocks in the group. @@ -10396,74 +10559,74 @@ - set_clock_latency + set_clock_latency - [-source][-clock clock][-rise][-fall][-min][-max]delayobjects + [-source][-clock clock][-rise][-fall][-min][-max]delayobjects - -source + -source - The latency is at the clock source. + The latency is at the clock source. - -clock clock + -clock clock - If multiple clocks are defined at a pin this use this option to specify the latency for a specific clock. + If multiple clocks are defined at a pin this use this option to specify the latency for a specific clock. - -rise + -rise - The latency is for the rising edge of the clock. + The latency is for the rising edge of the clock. - -fall + -fall - The latency is for the falling edge of the clock. + The latency is for the falling edge of the clock. - -min + -min - delay is the minimum latency. + delay is the minimum latency. - -max + -max - delay is the maximum latency. + delay is the maximum latency. - delay + delay - Clock source or insertion delay. + Clock source or insertion delay. - objects + objects - A list of clocks, pins or ports. + A list of clocks, pins or ports. @@ -10473,59 +10636,59 @@ - set_clock_transition + set_clock_transition - [-rise][-fall][-min][-max]transitionclocks + [-rise][-fall][-min][-max]transitionclocks - -rise + -rise - Set the transition time for the rising edge of the clock. + Set the transition time for the rising edge of the clock. - -fall + -fall - Set the transition time for the falling edge of the clock. + Set the transition time for the falling edge of the clock. - -min + -min - Set the min transition time. + Set the min transition time. - -max + -max - Set the min transition time. + Set the min transition time. - transition + transition - Clock transition time (slew). + Clock transition time (slew). - clocks + clocks - A list of clocks. + A list of clocks. @@ -10535,214 +10698,213 @@ - set_clock_uncertainty + set_clock_uncertainty - [-from|-rise_from|-fall_from from_clock][-to|-rise_to|-fall_to to_clock][-rise][-fall][-setup][-hold]uncertainty[objects] + [-from|-rise_from|-fall_from from_clock][-to|-rise_to|-fall_to to_clock][-rise][-fall][-setup][-hold]uncertainty[objects] - -from from_clock + -from from_clock - Inter-clock uncertainty source clock. + Inter-clock uncertainty source clock. - -to to_clock + -to to_clock - Inter-clock uncertainty target clock. + Inter-clock uncertainty target clock. - -rise + -rise - Inter-clock target clock rise edge, alternative to ‑rise_to.Inter-clock target clock rise edge, alternative to ‑rise_to. + Inter-clock target clock rise edge, alternative to ‑rise_to.Inter-clock target clock rise edge, alternative to ‑rise_to. - -fall + -fall - Inter-clock target clock rise edge, alternative to ‑fall_to. + Inter-clock target clock rise edge, alternative to ‑fall_to. - -setup + -setup - uncertainty is for setup checks. + uncertainty is for setup checks. - -hold + -hold - uncertainty is for hold checks. + uncertainty is for hold checks. - uncertainty + uncertainty - Clock uncertainty. + Clock uncertainty. - objects + objects - A list of clocks, ports or pins. + A list of clocks, ports or pins. - The set_clock_uncertainty command specifies the uncertainty or jitter in a clock. The uncertainty for a clock can be specified on its source pin or port, or the clock itself. - set_clock_uncertainty .1 [get_clock clk1] - Inter-clock uncertainty between the source and target clocks of timing checks is specified with the ‑from|‑rise_from|-fall_from and ‑to|‑rise_to|-fall_to arguments . - set_clock_uncertainty -from [get_clock clk1] -to [get_clocks clk2] .1 - The following commands are equivalent. - set_clock_uncertainty -from [get_clock clk1] -rise_to [get_clocks clk2] .1set_clock_uncertainty -from [get_clock clk1] -to [get_clocks clk2] -rise .1 + The set_clock_uncertainty command specifies the uncertainty or jitter in a clock. The uncertainty for a clock can be specified on its source pin or port, or the clock itself. + set_clock_uncertainty .1 [get_clock clk1] + Inter-clock uncertainty between the source and target clocks of timing checks is specified with the ‑from|‑rise_from|-fall_from and ‑to|‑rise_to|-fall_to arguments . + set_clock_uncertainty -from [get_clock clk1] -to [get_clocks clk2] .1 + The following commands are equivalent. + set_clock_uncertainty -from [get_clock clk1] -rise_to [get_clocks clk2] .1set_clock_uncertainty -from [get_clock clk1] -to [get_clocks clk2] -rise .1 - set_cmd_units + set_cmd_units - [-capacitance cap_unit][-resistance res_unit][-time time_unit][-voltage voltage_unit][-current current_unit][-power power_unit][-distance distance_unit] + [-capacitance cap_unit][-resistance res_unit][-time time_unit][-voltage voltage_unit][-current current_unit][-power power_unit][-distance distance_unit] - -capacitance cap_unit + -capacitance cap_unit - The capacitance scale factor followed by 'f'. + The capacitance scale factor followed by 'f'. - -resistance res_unit + -resistance res_unit - The resistance scale factor followed by 'ohm'. + The resistance scale factor followed by 'ohm'. - -time time_unit + -time time_unit - The time scale factor followed by 's'. + The time scale factor followed by 's'. - -voltage voltage_unit + -voltage voltage_unit - The voltage scale factor followed by 'v'. + The voltage scale factor followed by 'v'. - -current current_unit + -current current_unit - The current scale factor followed by 'A'. + The current scale factor followed by 'A'. - -power power_unit + -power power_unit - The power scale factor followed by 'w'. + The power scale factor followed by 'w'. - -distance distance_unit + -distance distance_unit - The distance scale factor followed by 'm'. + The distance scale factor followed by 'm'. - The set_cmd_units command is used to change the units used by the STA command interpreter when parsing commands and reporting results. The default units are the units specified in the first Liberty library file that is read. + The set_cmd_units command is used to change the units used by the STA command interpreter when parsing commands and reporting results. The default units are the units specified in the first Liberty library file that is read. Units are specified as a scale factor followed by a unit name. The scale factors are as follows. M 1E+6k 1E+3m 1E-3u 1E-6n 1E-9p 1E-12f 1E-15 An example of the set_units command is shown below. - set_cmd_units -time ns -capacitance pF -current mA -voltage V -resistance kOhm -distance um + set_cmd_units -time ns -capacitance pF -current mA -voltage V -resistance kOhm -distance um - - set_data_check + set_data_check - [-from|-rise_from|-fall_from from_pin][-to|-rise_to|-fall_to to_pin][-setup][-hold][-clock clock]margin + [-from|-rise_from|-fall_from from_pin][-to|-rise_to|-fall_to to_pin][-setup][-hold][-clock clock]margin - -from from_pin + -from from_pin - A pin used as the timing check reference. + A pin used as the timing check reference. - -to to_pin + -to to_pin - A pin that the setup/hold check is applied to. + A pin that the setup/hold check is applied to. - -setup + -setup - Add a setup timing check. + Add a setup timing check. - -hold + -hold - Add a hold timing check. + Add a hold timing check. - -clock clock + -clock clock - The setup/hold check clock. + The setup/hold check clock. - margin + margin - The setup or hold time margin. + The setup or hold time margin. @@ -10752,61 +10914,61 @@ - set_disable_inferred_clock_gating + set_disable_inferred_clock_gating - objects + objects - objects + objects - A list of clock gating instances, clock gating pins, or clock enable pins. + A list of clock gating instances, clock gating pins, or clock enable pins. - The set_disable_inferred_clock_gating command disables clock gating checks on a clock gating instance, clock gating pin, or clock gating enable pin. + The set_disable_inferred_clock_gating command disables clock gating checks on a clock gating instance, clock gating pin, or clock gating enable pin. - set_disable_timing + set_disable_timing - [-from from_port][-to to_port]objects + [-from from_port][-to to_port]objects - -from from_port + -from from_port - + - -to to_port + -to to_port - + - objects + objects - A list of instances, ports, pins, cells, cell/port, or library/cell/port. + A list of instances, ports, pins, cells, cell/port, or library/cell/port. - The set_disable_timing command is used to disable paths though pins in the design. There are many different forms of the command depending on the objects specified in objects. - All timing paths though an instance are disabled when objects contains an instance. Timing checks in the instance are not disabled. - set_disable_timing u2 + The set_disable_timing command is used to disable paths though pins in the design. There are many different forms of the command depending on the objects specified in objects. + All timing paths though an instance are disabled when objects contains an instance. Timing checks in the instance are not disabled. + set_disable_timing u2 The -from and -to options can be used to restrict the disabled path to those from, to or between specific pins on the instance. set_disable_timing -from A u2set_disable_timing -to Z u2set_disable_timing -from A -to Z u2 A list of top level ports or instance pins can also be disabled. @@ -10818,157 +10980,156 @@ - set_drive + set_drive - [-rise][-fall][-max][-min]resistanceports + [-rise][-fall][-max][-min]resistanceports - -rise + -rise - Set the drive rise resistance. + Set the drive rise resistance. - -fall + -fall - Set the drive fall resistance. + Set the drive fall resistance. - -max + -max - Set the maximum resistance. + Set the maximum resistance. - -min + -min - Set the minimum resistance. + Set the minimum resistance. - resistance + resistance - The external drive resistance. + The external drive resistance. - ports + ports A list of ports. - The set_drive command describes the resistance of an input port external driver. + The set_drive command describes the resistance of an input port external driver. - - set_driving_cell + set_driving_cell - [-lib_cell cell_name][-library library][-rise][-fall][-min][-max][-pin pin][-from_pin from_pin][-input_transition_rise trans_rise][-input_transition_fall trans_fall]ports + [-lib_cell cell_name][-library library][-rise][-fall][-min][-max][-pin pin][-from_pin from_pin][-input_transition_rise trans_rise][-input_transition_fall trans_fall]ports - -lib_cell cell_name + -lib_cell cell_name - The driving cell. + The driving cell. - -library library + -library library - The driving cell library. + The driving cell library. - -rise + -rise - Set the driving cell for a rising edge. + Set the driving cell for a rising edge. - -fall + -fall - Set the driving cell for a falling edge. + Set the driving cell for a falling edge. - -max + -max - Set the driving cell for max delays. + Set the driving cell for max delays. - -min + -min - Set the driving cell for min delays. + Set the driving cell for min delays. - -pin pin + -pin pin - The output port of the driving cell. + The output port of the driving cell. - -from_pin from_pin + -from_pin from_pin - Use timing arcs from from_pin to the output pin. + Use timing arcs from from_pin to the output pin. - -input_transition_rise trans_rise + -input_transition_rise trans_rise - The transition time for a rising input at from_pin. + The transition time for a rising input at from_pin. - -input_transition_fall trans_fall + -input_transition_fall trans_fall - The transition time for a falling input at from_pin. + The transition time for a falling input at from_pin. - ports + ports A list of ports. @@ -10982,47 +11143,47 @@ - set_false_path + set_false_path - [-setup][-hold][-rise][-fall][-from from_list][-rise_from from_list][-fall_from from_list][-through through_list][-rise_through through_list][-fall_through through_list][-to to_list][-rise_to to_list][-fall_to to_list][-reset_path] + [-setup][-hold][-rise][-fall][-from from_list][-rise_from from_list][-fall_from from_list][-through through_list][-rise_through through_list][-fall_through through_list][-to to_list][-rise_to to_list][-fall_to to_list][-reset_path] - -setup + -setup - Apply to setup checks. + Apply to setup checks. - -hold + -hold - Apply to hold checks. + Apply to hold checks. - -rise + -rise - Apply to rising path edges. + Apply to rising path edges. - -fall + -fall - Apply to falling path edges. + Apply to falling path edges. - -reset_path + -reset_path Remove any matching set_false_path, set_multicycle_path, set_max_delay, set_min_delay exceptions first. @@ -11030,7 +11191,7 @@ - -from from_list + -from from_list A list of clocks, instances, ports or pins. @@ -11038,7 +11199,7 @@ - -through through_list + -through through_list A list of instances, pins or nets. @@ -11046,7 +11207,7 @@ - -to to_list + -to to_list A list of clocks, instances, ports or pins. @@ -11063,10 +11224,10 @@ - set_fanout_load + set_fanout_load - fanoutport_list + fanoutport_list @@ -11076,18 +11237,18 @@ - set_hierarchy_separator + set_hierarchy_separator - separator + separator - separator + separator - Character used to separate hierarchical names. + Character used to separate hierarchical names. @@ -11097,10 +11258,10 @@ - set_ideal_latency + set_ideal_latency - [-rise] [-fall] [-min] [-max] delay objects + [-rise] [-fall] [-min] [-max] delay objects @@ -11110,10 +11271,10 @@ - set_ideal_network + set_ideal_network - [-no_propagation] objects + [-no_propagation] objects @@ -11123,10 +11284,10 @@ - set_ideal_transition + set_ideal_transition - [-rise] [-fall] [-min] [-max] transition_time objects + [-rise] [-fall] [-min] [-max] transition_time objects @@ -11136,175 +11297,175 @@ - set_input_delay + set_input_delay - [-rise][-fall][-max][-min][-clock clock][-clock_fall][-reference_pin ref_pin][-source_latency_included][-network_latency_included][-add_delay]delayport_pin_list + [-rise][-fall][-max][-min][-clock clock][-clock_fall][-reference_pin ref_pin][-source_latency_included][-network_latency_included][-add_delay]delayport_pin_list - -rise + -rise - Set the arrival time for the rising edge of the input. + Set the arrival time for the rising edge of the input. - -fall + -fall - Set the arrival time for the falling edge of the input. + Set the arrival time for the falling edge of the input. - -max + -max - Set the maximum arrival time. + Set the maximum arrival time. - -min + -min - Set the minimum arrival time. + Set the minimum arrival time. - -clock clock + -clock clock - The arrival time is from clock. + The arrival time is from clock. - -clock_fall + -clock_fall - The arrival time is from the falling edge of clock. + The arrival time is from the falling edge of clock. - -reference_pin ref_pin + -reference_pin ref_pin - The arrival time is with respect to the clock that arrives at ref_pin. + The arrival time is with respect to the clock that arrives at ref_pin. - -source_latency_included + -source_latency_included - D no add the clock source latency (insertion delay) to the delay value. + D no add the clock source latency (insertion delay) to the delay value. - -network_latency_included + -network_latency_included - Do not add the clock latency to the delay value when the clock is ideal. + Do not add the clock latency to the delay value when the clock is ideal. - -add_delay + -add_delay - Add this arrival to any existing arrivals. + Add this arrival to any existing arrivals. - delay + delay - The arrival time after clock. + The arrival time after clock. - pin_port_list + pin_port_list - A list of pins or ports. + A list of pins or ports. - The set_input_delay command is used to specify the arrival time of an input signal. - The following command sets the min, max, rise and fall times on the in1 input port 1.0 time units after the rising edge of clk1. - set_input_delay -clock clk1 1.0 [get_ports in1] - Use multiple commands with the -add_delay option to specify separate arrival times for min, max, rise and fall times or multiple clocks. For example, the following specifies separate arrival times with respect to clocks clk1 and clk2. - set_input_delay -clock clk1 1.0 [get_ports in1]set_input_delay -add_delay -clock clk2 2.0 [get_ports in1] - The –reference_pin option is used to specify an arrival time with respect to the arrival on a pin in the clock network. For propagated clocks, the input arrival time is relative to the clock arrival time at the reference pin (the clock source latency and network latency from the clock source to the reference pin). For ideal clocks, input arrival time is relative to the reference pin clock source latency. With the -clock_fall flag the arrival time is relative to the falling transition at the reference pin. If no clocks arrive at the reference pin the set_input_delay command is ignored. If no -clock is specified the arrival time is with respect to all clocks that arrive at the reference pin. The -source_latency_included and -network_latency_included options cannot be used with -reference_pin. - Paths from inputs that do not have an arrival time defined by set_input_delay are not reported. Set the sta_input_port_default_clock variable to 1 to report paths from inputs without a set_input_delay. + The set_input_delay command is used to specify the arrival time of an input signal. + The following command sets the min, max, rise and fall times on the in1 input port 1.0 time units after the rising edge of clk1. + set_input_delay -clock clk1 1.0 [get_ports in1] + Use multiple commands with the -add_delay option to specify separate arrival times for min, max, rise and fall times or multiple clocks. For example, the following specifies separate arrival times with respect to clocks clk1 and clk2. + set_input_delay -clock clk1 1.0 [get_ports in1]set_input_delay -add_delay -clock clk2 2.0 [get_ports in1] + The –reference_pin option is used to specify an arrival time with respect to the arrival on a pin in the clock network. For propagated clocks, the input arrival time is relative to the clock arrival time at the reference pin (the clock source latency and network latency from the clock source to the reference pin). For ideal clocks, input arrival time is relative to the reference pin clock source latency. With the -clock_fall flag the arrival time is relative to the falling transition at the reference pin. If no clocks arrive at the reference pin the set_input_delay command is ignored. If no -clock is specified the arrival time is with respect to all clocks that arrive at the reference pin. The -source_latency_included and -network_latency_included options cannot be used with -reference_pin. + Paths from inputs that do not have an arrival time defined by set_input_delay are not reported. Set the sta_input_port_default_clock variable to 1 to report paths from inputs without a set_input_delay. - set_input_transition + set_input_transition - [-rise][-fall][-max][-min]transitionport_list + [-rise][-fall][-max][-min]transitionport_list - -rise + -rise - Set the rising edge transition. + Set the rising edge transition. - -fall + -fall - Set the falling edge transition. + Set the falling edge transition. - -max + -max - Set the minimum transition time. + Set the minimum transition time. - -min + -min - Set the maximum transition time. + Set the maximum transition time. - transition + transition - The transition time (slew). + The transition time (slew). - port_list + port_list - A list of ports. + A list of ports. @@ -11314,10 +11475,10 @@ - set_level_shifter_strategy + set_level_shifter_strategy - [-rule rule_type] + [-rule rule_type] @@ -11327,10 +11488,10 @@ - set_level_shifter_threshold + set_level_shifter_threshold - [-voltage voltage] + [-voltage voltage] @@ -11340,56 +11501,56 @@ - set_load + set_load - [-rise][-fall][-max][-min][-subtract_pin_load][-pin_load][-wire_load]capacitanceobjects + [-rise][-fall][-max][-min][-subtract_pin_load][-pin_load][-wire_load]capacitanceobjects - -rise + -rise - Set the external port rising capacitance (ports only). + Set the external port rising capacitance (ports only). - -fall + -fall - Set the external port falling capacitance (ports only). + Set the external port falling capacitance (ports only). - -max + -max - Set the max capacitance. + Set the max capacitance. - -min + -min - Set the min capacitance. + Set the min capacitance. - -subtract_pin_load + -subtract_pin_load - Subtract the capacitance of all instance pins connected to the net from capacitance (nets only). If the resulting capacitance is negative, zero is used. Pin capacitances are ignored by delay calculation when this option is used. + Subtract the capacitance of all instance pins connected to the net from capacitance (nets only). If the resulting capacitance is negative, zero is used. Pin capacitances are ignored by delay calculation when this option is used. - -pin_load + -pin_load capacitance is external instance pin capacitance (ports only). @@ -11397,7 +11558,7 @@ - -wire_load + -wire_load capacitance is external wire capacitance (ports only). @@ -11405,7 +11566,7 @@ - capacitance + capacitance The capacitance, in library capacitance units. @@ -11413,34 +11574,34 @@ - objects + objects A list of nets or ports. - The set_load command annotates wire capacitance on a net or external capacitance on a port. There are four different uses for the set_load commanc: - set_load -wire_load port external port wire capacitanceset_load -pin_load port external port pin capacitanceset_load port same as -pin_loadset_load net net wire capacitance - External port capacitance can be annotated separately with the -pin_load and ‑wire_load options. Without the -pin_load and -wire_load options pin capacitance is annotated. - When annotating net wire capacitance with the -subtract_pin_load option the capacitance of all instance pins connected to the net is subtracted from capacitance. Setting the capacitance on a net overrides SPEF parasitics for delay calculation. + The set_load command annotates wire capacitance on a net or external capacitance on a port. There are four different uses for the set_load commanc: + set_load -wire_load port external port wire capacitanceset_load -pin_load port external port pin capacitanceset_load port same as -pin_loadset_load net net wire capacitance + External port capacitance can be annotated separately with the -pin_load and ‑wire_load options. Without the -pin_load and -wire_load options pin capacitance is annotated. + When annotating net wire capacitance with the -subtract_pin_load option the capacitance of all instance pins connected to the net is subtracted from capacitance. Setting the capacitance on a net overrides SPEF parasitics for delay calculation. - set_logic_dc + set_logic_dc - port_list + port_list - port_pin_list + port_pin_list - List of ports or pins. + List of ports or pins. @@ -11450,61 +11611,61 @@ - set_logic_one + set_logic_one - port_list + port_list - port_pin_list + port_pin_list - List of ports or pins. + List of ports or pins. - Set a port or pin to a constant logic one value. No paths are propagated from constant pins. Constant values set with the set_logic_one command are not propagated through downstream gates. + Set a port or pin to a constant logic one value. No paths are propagated from constant pins. Constant values set with the set_logic_one command are not propagated through downstream gates. - set_logic_zero + set_logic_zero - port_list + port_list - port_pin_list + port_pin_list - List of ports or pins. + List of ports or pins. - Set a port or pin to a constant logic zero value. No paths are propagated from constant pins. Constant values set with the set_logic_zero command are not propagated through downstream gates. + Set a port or pin to a constant logic zero value. No paths are propagated from constant pins. Constant values set with the set_logic_zero command are not propagated through downstream gates. - set_max_area + set_max_area - area + area - area + area - + @@ -11514,26 +11675,26 @@ - set_max_capacitance + set_max_capacitance - capacitanceobjects + capacitanceobjects - capacitance + capacitance - + - objects + objects - List of ports or cells. + List of ports or cells. @@ -11543,32 +11704,32 @@ - set_max_delay + set_max_delay - [-rise][-fall][-from from_list][-rise_from from_list][-fall_from from_list][-through through_list][-rise_through through_list][-fall_through through_list][-to to_list][-rise_to to_list][-fall_to to_list][-ignore_clock_latency][-probe][-reset_path]delay + [-rise][-fall][-from from_list][-rise_from from_list][-fall_from from_list][-through through_list][-rise_through through_list][-fall_through through_list][-to to_list][-rise_to to_list][-fall_to to_list][-ignore_clock_latency][-probe][-reset_path]delay - -rise + -rise - Set max delay for rising paths. + Set max delay for rising paths. - -fall + -fall - Set max delay for falling paths. + Set max delay for falling paths. - -from from_list + -from from_list A list of clocks, instances, ports or pins. @@ -11576,7 +11737,7 @@ - -through through_list + -through through_list A list of instances, pins or nets. @@ -11584,7 +11745,7 @@ - -to to_list + -to to_list A list of clocks, instances, ports or pins. @@ -11592,7 +11753,7 @@ - -ignore_clock_latency + -ignore_clock_latency Ignore clock latency at the source and target registers. @@ -11600,15 +11761,15 @@ - -probe + -probe - Do not break paths at internal pins (non startpoints). + Do not break paths at internal pins (non startpoints). - -reset_path + -reset_path Remove any matching set_false_path, set_multicycle_path, set_max_delay, set_min_delay exceptions first. @@ -11616,7 +11777,7 @@ - delay + delay The maximum delay. @@ -11624,16 +11785,16 @@ The set_max_delay command constrains the maximum delay through combinational logic paths. See set_false_path for a description of allowed from_list, through_list and to_list objects. If the to_list ends at a timing check the setup/hold time is included in the path delay. - When the -ignore_clock_latency option is used clock latency at the source and destination of the path delay is ignored. The constraint is reported in the default path group (**default**) rather than the clock path group when the path ends at a timing check. + When the -ignore_clock_latency option is used clock latency at the source and destination of the path delay is ignored. The constraint is reported in the default path group (**default**) rather than the clock path group when the path ends at a timing check. - set_max_dynamic_power + set_max_dynamic_power - power [unit] + power [unit] @@ -11643,26 +11804,26 @@ - set_max_fanout + set_max_fanout - fanoutobjects + fanoutobjects - fanout + fanout - + - objects + objects - List of ports or cells. + List of ports or cells. @@ -11672,10 +11833,10 @@ - set_max_leakage_power + set_max_leakage_power - power [unit] + power [unit] @@ -11685,92 +11846,92 @@ - set_max_time_borrow + set_max_time_borrow - delayobjects + delayobjects - delay + delay - The maximum time the latches can borrow. + The maximum time the latches can borrow. - objects + objects - List of clocks, instances or pins. + List of clocks, instances or pins. - The set_max_time_borrow command specifies the maximum amount of time that latches can borrow. Time borrowing is the time that a data input to a transparent latch arrives after the latch opens. + The set_max_time_borrow command specifies the maximum amount of time that latches can borrow. Time borrowing is the time that a data input to a transparent latch arrives after the latch opens. - set_max_transition + set_max_transition - [-data_path][-clock_path][-rise][-fall]transitionobjects + [-data_path][-clock_path][-rise][-fall]transitionobjects - -data_path + -data_path - Set the max slew for data paths. + Set the max slew for data paths. - -clock_path + -clock_path - Set the max slew for clock paths. + Set the max slew for clock paths. - -rise + -rise - Set the max slew for rising paths. + Set the max slew for rising paths. - -fall + -fall - Set the max slew for falling paths. + Set the max slew for falling paths. - transition + transition - The maximum slew/transition time. + The maximum slew/transition time. - objects + objects - List of clocks, ports or designs. + List of clocks, ports or designs. - The set_max_transition command is specifies the maximum transition time (slew) design rule checked by the report_check_types –max_transition command. + The set_max_transition command is specifies the maximum transition time (slew) design rule checked by the report_check_types –max_transition command. If specified for a design, the default maximum transition is set for the design. If specified for a clock, the maximum transition is applied to all pins in the clock domain. The –clock_path option restricts the maximum transition to clocks in clock paths. The -data_path option restricts the maximum transition to clocks data paths. The –clock_path, -data_path, -rise and –fall options only apply to clock objects. @@ -11778,26 +11939,26 @@ - set_min_capacitance + set_min_capacitance - capacitanceobjects + capacitanceobjects - capacitance + capacitance - Minimum capacitance. + Minimum capacitance. - objects + objects - List of ports or cells. + List of ports or cells. @@ -11808,31 +11969,31 @@ - set_min_delay + set_min_delay - [-rise][-fall][-from from_list][-rise_from from_list][-fall_from from_list][-through through_list][-rise_through through_list][-fall_through through_list][-to to_list][-rise_to to_list][-fall_to to_list][-ignore_clock_latency][-probe][-reset_path]delay + [-rise][-fall][-from from_list][-rise_from from_list][-fall_from from_list][-through through_list][-rise_through through_list][-fall_through through_list][-to to_list][-rise_to to_list][-fall_to to_list][-ignore_clock_latency][-probe][-reset_path]delay - -rise + -rise - Set min delay for rising paths. + Set min delay for rising paths. - -fall + -fall - Set min delay for falling paths. + Set min delay for falling paths. - -from from_list + -from from_list A list of clocks, instances, ports or pins. @@ -11840,7 +12001,7 @@ - -through through_list + -through through_list A list of instances, pins or nets. @@ -11848,7 +12009,7 @@ - -to to_list + -to to_list A list of clocks, instances, ports or pins. @@ -11856,7 +12017,7 @@ - -ignore_clock_latency + -ignore_clock_latency Ignore clock latency at the source and target registers. @@ -11864,15 +12025,15 @@ - -probe + -probe - Do not break paths at internal pins (non startpoints). + Do not break paths at internal pins (non startpoints). - -reset_path + -reset_path Remove any matching set_false_path, set_multicycle_path, set_max_delay, set_min_delay exceptions first. @@ -11880,107 +12041,121 @@ - delay + delay - The minimum delay. + The minimum delay. The set_min_delay command constrains the minimum delay through combinational logic. See set_false_path for a description of allowed from_list, through_list and to_list objects. If the to_list ends at a timing check the setup/hold time is included in the path delay. - When the -ignore_clock_latency option is used clock latency at the source and destination of the path delay is ignored. The constraint is reported in the default path group (**default**) rather than the clock path group when the path ends at a timing check. + When the -ignore_clock_latency option is used clock latency at the source and destination of the path delay is ignored. The constraint is reported in the default path group (**default**) rather than the clock path group when the path ends at a timing check. - set_min_pulse_width + set_min_pulse_width - [-high][-low]min_widthobjects + [-high][-low]min_widthobjects - -high + -high - Set the minimum high pulse width. + Set the minimum high pulse width. - -low + -low - Set the minimum low pulse width. + Set the minimum low pulse width. - min_width + min_width - + - objects + objects - List of pins, instances or clocks. + List of pins, instances or clocks. If -low and -high are not specified the minimum width applies to both high and low pulses. + + + + + + set_mode + + + mode_name + + + + The the mode for SDC c ommands in the TCL interpreter. If mode mode_name does not exist, it is created. When modes are created the default mode is deleted. - set_multicycle_path + set_multicycle_path - [-setup][-hold][-rise][-fall][-start][-end][-from from_list][-rise_from from_list][-fall_from from_list][-through through_list][-rise_through through_list][-fall_through through_list][-to to_list][-rise_to to_list][-fall_to to_list][-reset_path]path_multiplier + [-setup][-hold][-rise][-fall][-start][-end][-from from_list][-rise_from from_list][-fall_from from_list][-through through_list][-rise_through through_list][-fall_through through_list][-to to_list][-rise_to to_list][-fall_to to_list][-reset_path]path_multiplier - -setup + -setup - Set cycle count for setup checks. + Set cycle count for setup checks. - -hold + -hold - Set cycle count for hold checks. + Set cycle count for hold checks. - -rise + -rise - Set cycle count for rising path edges. + Set cycle count for rising path edges. + + + + + + -fall + + + Set cycle count for falling path edges. - -fall - - - Set cycle count for falling path edges. - - - - - -start + -start Multiply the source clock period by period_multiplier. @@ -11988,16 +12163,15 @@ - -end + -end Multiply the target clock period by period_multiplier. - - -from from_list + -from from_list A list of clocks, instances, ports or pins. @@ -12005,7 +12179,7 @@ - -through through_list + -through through_list A list of instances, pins or nets. @@ -12013,7 +12187,7 @@ - -to to_list + -to to_list A list of clocks, instances, ports or pins. @@ -12021,7 +12195,7 @@ - -reset_path + -reset_path Remove any matching set_false_path, set_multicycle_path, set_max_delay, set_min_delay exceptions first. @@ -12029,7 +12203,7 @@ - path_multiplier + path_multiplier The number of clock periods to add to the path required time. @@ -12042,321 +12216,323 @@ - set_operating_conditions + set_operating_conditions - [-analysis_type single|bc_wc|on_chip_variation][-library lib][condition][-min min_condition][-max max_condition][-min_library min_lib][-max_library max_lib] + [-analysis_type single|bc_wc|on_chip_variation][-library lib][condition][-min min_condition][-max max_condition][-min_library min_lib][-max_library max_lib] - -analysis_type single + -analysis_type single - Use one operating condition for min and max paths. + Use one operating condition for min and max paths. - -analysis_type bc_wc + -analysis_type bc_wc - Best case, worst case analysis. Setup checks use max_condition for clock and data paths. Hold checks use the min_condition for clock and data paths. + Best case, worst case analysis. Setup checks use max_condition for clock and data paths. Hold checks use the min_condition for clock and data paths. - ‑analysis_type on_chip_variation + ‑analysis_type on_chip_variation - The min and max operating conditions represent variations on the chip that can occur simultaneously. Setup checks use max_condition for data paths and min_condition for clock paths. Hold checks use min_condition for data paths and max_condition for clock paths. This is the default analysis type. + The min and max operating conditions represent variations on the chip that can occur simultaneously. Setup checks use max_condition for data paths and min_condition for clock paths. Hold checks use min_condition for data paths and max_condition for clock paths. This is the default analysis type. - -library lib + -library lib - The name of the library that contains condition. + The name of the library that contains condition. - condition + condition - The operating condition for analysis type single. + The operating condition for analysis type single. - -min min_condition + -min min_condition - The operating condition to use for min paths and hold checks. + The operating condition to use for min paths and hold checks. + + + + + + -max max_condition + + + The operating condition to use for max paths and setup checks. - -max max_condition + -min_library min_lib - The operating condition to use for max paths and setup checks. + The name of the library that contains min_condition. - -min_library min_lib + -max_library max_lib - The name of the library that contains min_condition. - - - - - -max_library max_lib - - - The name of the library that contains max_condition. + The name of the library that contains max_condition. - The set_operating_conditions command is used to specify the type of analysis performed and the operating conditions used to derate library data. + The set_operating_conditions command is used to specify the type of analysis performed and the operating conditions used to derate library data. - set_output_delay + set_output_delay - [-rise][-fall][-max][-min][-clock clock][-clock_fall][-reference_pin ref_pin][-source_latency_included][-network_latency_included][-add_delay]delayport_pin_list + [-rise][-fall][-max][-min][-clock clock][-clock_fall][-reference_pin ref_pin][-source_latency_included][-network_latency_included][-add_delay]delayport_pin_list - -rise + -rise - Set the output delay for the rising edge of the input. + Set the output delay for the rising edge of the input. - -fall + -fall - Set the output delay for the falling edge of the input. + Set the output delay for the falling edge of the input. - -max + -max - Set the maximum output delay. + Set the maximum output delay. - -min + -min - Set the minimum output delay. + Set the minimum output delay. - -clock clock + -clock clock - The external check is to clock. The default clock edge is rising. + The external check is to clock. The default clock edge is rising. - -clock_fall + -clock_fall - The external check is to the falling edge of clock. + The external check is to the falling edge of clock. - -reference_pin ref_pin + -reference_pin ref_pin - The external check is clocked by the clock that arrives at ref_pin. + The external check is clocked by the clock that arrives at ref_pin. - -add_delay + -add_delay - Add this output delay to any existing output delays. + Add this output delay to any existing output delays. - delay + delay - The external delay to the check clocked by clock. + The external delay to the check clocked by clock. - pin_port_list + pin_port_list - A list of pins or ports. + A list of pins or ports. - The set_output_delay command is used to specify the external delay to a setup/hold check on an output port or internal pin that is clocked by clock. Unless the -add_delay option is specified any existing output delays are replaced. - The –reference_pin option is used to specify a timing check with respect to the arrival on a pin in the clock network. For propagated clocks, the timing check is relative to the clock arrival time at the reference pin (the clock source latency and network latency from the clock source to the reference pin). For ideal clocks, the timing check is relative to the reference pin clock source latency. With the -clock_fall flag the timing check is relative to the falling edge of the reference pin. If no clocks arrive at the reference pin the set_output_delay command is ignored. If no -clock is specified the timing check is with respect to all clocks that arrive at the reference pin. The -source_latency_included and -network_latency_included options cannot be used with -reference_pin. + The set_output_delay command is used to specify the external delay to a setup/hold check on an output port or internal pin that is clocked by clock. Unless the -add_delay option is specified any existing output delays are replaced. + The –reference_pin option is used to specify a timing check with respect to the arrival on a pin in the clock network. For propagated clocks, the timing check is relative to the clock arrival time at the reference pin (the clock source latency and network latency from the clock source to the reference pin). For ideal clocks, the timing check is relative to the reference pin clock source latency. With the -clock_fall flag the timing check is relative to the falling edge of the reference pin. If no clocks arrive at the reference pin the set_output_delay command is ignored. If no -clock is specified the timing check is with respect to all clocks that arrive at the reference pin. The -source_latency_included and -network_latency_included options cannot be used with -reference_pin. - set_port_fanout_number + set_port_fanout_number - [-min][-max]fanoutports + [-min][-max]fanoutports - -min + -min - Set the min fanout. + Set the min fanout. - -max + -max - Set the max fanout. + Set the max fanout. - fanout + fanout - The external fanout of the ports. + The external fanout of the ports. - port_list + port_list - A list of ports. + A list of ports. - Set the external fanout for ports. + Set the external fanout for ports. - set_power_activity + set_power_activity - [-global][-input][-input_ports ports][-pins pins][-activity activity | -density density][-duty duty][-clock clock] + [-global][-input][-input_ports ports][-pins pins][-activity activity | -density density][-duty duty][-clock clock] - -global + -global - Set the activity/duty for all non-clock pins. + Set the activity/duty for all non-clock pins. - -input + -input - Set the default input port activity/duty. + Set the default input port activity/duty. - -input_ports input_ports + -input_ports input_ports - Set the input port activity/duty. + Set the input port activity/duty. - -pins pins + -pins pins - Set the pin activity/duty. + Set the pin activity/duty. + + + + + + -activity activity + + + The activity, or number of transitions per clock cycle. If clock is not specified the clock with the minimum period is used. If no clocks are defined an error is reported. - -activity activity + -density density - The activity, or number of transitions per clock cycle. If clock is not specified the clock with the minimum period is used. If no clocks are defined an error is reported. + Transitions per library time unit. - -density density + -duty duty - Transitions per library time unit. + The duty, or probability the signal is high (0 <= duty <= 1.0). Defaults to 0.5. - -duty duty + -clock clock - The duty, or probability the signal is high (0 <= duty <= 1.0). Defaults to 0.5. - - - - - -clock clock - - - The clock to use for the period with -activity. This option is ignored if -density is used. + The clock to use for the period with -activity. This option is ignored if -density is used. - The set_power_activity command is used to set the activity and duty used for power analysis globally or for input ports or pins in the design. - The default input activity for inputs is 0.1 transitions per minimum clock period if a clock is defined or 0.0 if there are no clocks defined. The default input duty is 0.5. This is equivalent to the following command: - set_power_activity -input -activity 0.1 -duty 0.5 + The set_power_activity command is used to set the activity and duty used for power analysis globally or for input ports or pins in the design. + The default input activity for inputs is 0.1 transitions per minimum clock period if a clock is defined or 0.0 if there are no clocks defined. The default input duty is 0.5. This is equivalent to the following command: + set_power_activity -input -activity 0.1 -duty 0.5 - set_propagated_clock + set_propagated_clock - objects + objects - objects + objects - A list of clocks, ports or pins. + A list of clocks, ports or pins. @@ -12366,59 +12542,60 @@ - set_pvt + set_pvt - [-min][-max][-process process][-voltage voltage] - [-temperature temperature]instances + [-min][-max][-process process][-voltage voltage] + [-temperature temperature]instances - -min + -min - Set the PVT values for max delays. + Set the PVT values for max delays. - -max + -max - Set the PVT values for min delays. + Set the PVT values for min delays. - -process process + -process process - A process value (float). + A process value (float). - -voltage voltage + -voltage voltage - A voltage value (float). + A voltage value (float). + - -temperature temperature + -temperature temperature - A temperature value (float). + A temperature value (float). - instances + instances - A list instances. + A list instances. @@ -12426,226 +12603,225 @@ - - set_sense + set_sense - [-type clock|data][-positive][-negative][-pulse pulse_type][-stop_propagation][-clock clocks]pins + [-type clock|data][-positive][-negative][-pulse pulse_type][-stop_propagation][-clock clocks]pins - -type clock + -type clock - Set the sense for clock paths. + Set the sense for clock paths. - -type data + -type data - Set the sense for data paths (not supported). + Set the sense for data paths (not supported). - -positive + -positive - The clock sense is positive unate. + The clock sense is positive unate. - -negative + -negative - The clock sense is negative unate. + The clock sense is negative unate. - -pulse pulse_type + -pulse pulse_type - rise_triggered_high_pulserise_triggered_low_pulsefall_triggered_high_pulsefall_triggered_low_pulseNot supported. + rise_triggered_high_pulserise_triggered_low_pulsefall_triggered_high_pulsefall_triggered_low_pulseNot supported. - -stop_propagation + -stop_propagation - Stop propagating clocks at pins. + Stop propagating clocks at pins. - clocks + clocks - A list of clocks to apply the sense. + A list of clocks to apply the sense. - pins + pins - A list of pins. + A list of pins. - The set_sense command is used to modify the propagation of a clock signal. The clock sense is set with the ‑positive and –negative flags. Use the –stop_propagation flag to stop the clock from propagating beyond a pin. The –positive, -negative, -stop_propagation, and –pulse options are mutually exclusive. If the –clock option is not used the command applies to all clocks that traverse pins. The –pulse option is currently not supported. + The set_sense command is used to modify the propagation of a clock signal. The clock sense is set with the ‑positive and –negative flags. Use the –stop_propagation flag to stop the clock from propagating beyond a pin. The –positive, -negative, -stop_propagation, and –pulse options are mutually exclusive. If the –clock option is not used the command applies to all clocks that traverse pins. The –pulse option is currently not supported. - set_timing_derate + set_timing_derate - [-rise][-fall][-early][-late][-clock][-data][-net_delay][-cell_delay][-cell_check]derate[objects] + [-rise][-fall][-early][-late][-clock][-data][-net_delay][-cell_delay][-cell_check]derate[objects] - -rise + -rise - Set the derating for rising delays. + Set the derating for rising delays. - -fall + -fall - Set the derating for falling delays. + Set the derating for falling delays. - -early + -early - Derate early (min) paths. + Derate early (min) paths. - -late + -late - Derate late (max) paths. + Derate late (max) paths. - -clock + -clock - Derate paths in the clock network. + Derate paths in the clock network. - -data + -data - Derate data paths. + Derate data paths. - -net_delay + -net_delay - Derate net (interconnect) delays. + Derate net (interconnect) delays. - -cell_delay + -cell_delay - Derate cell delays. + Derate cell delays. - -cell_check + -cell_check - Derate cell timing check margins. + Derate cell timing check margins. - derate + derate - The derating factor to apply to delays. + The derating factor to apply to delays. - objects + objects - A list of instances, library cells, or nets. + A list of instances, library cells, or nets. The set_timing_derate command is used to derate delay calculation results used by the STA. If the –early and –late flags are omitted the both min and max paths are derated. If the –clock and –data flags are not used the derating both clock and data paths are derated. - Use the unset_timing_derate command to remove all derating factors. + Use the unset_timing_derate command to remove all derating factors. - set_resistance + set_resistance - [-max][-min]resistancenets + [-max][-min]resistancenets - -min + -min - The resistance for minimum path delay calculation. + The resistance for minimum path delay calculation. - -max + -max - The resistance for maximum path delay calculation. + The resistance for maximum path delay calculation. - resistance + resistance - The net resistance. + The net resistance. - nets + nets - A list of nets. + A list of nets. @@ -12655,75 +12831,75 @@ - set_units + set_units - [-capacitance cap_unit][-resistance res_unit][-time time_unit][-voltage voltage_unit][-current current_unit][-power power_unit][-distance distance_unit] + [-capacitance cap_unit][-resistance res_unit][-time time_unit][-voltage voltage_unit][-current current_unit][-power power_unit][-distance distance_unit] - -capacitance cap_unit + -capacitance cap_unit - The capacitance scale factor followed by 'f'. + The capacitance scale factor followed by 'f'. - -resistance res_unit + -resistance res_unit - The resistance scale factor followed by 'ohm'. + The resistance scale factor followed by 'ohm'. - -time time_unit + -time time_unit - The time scale factor followed by 's'. + The time scale factor followed by 's'. - -voltage voltage_unit + -voltage voltage_unit - The voltage scale factor followed by 'v'. + The voltage scale factor followed by 'v'. - -current current_unit + -current current_unit - The current scale factor followed by 'A'. + The current scale factor followed by 'A'. - -power power_unit + -power power_unit - The power scale factor followed by 'w'. + The power scale factor followed by 'w'. - The set_units command is used to check the units used by the STA command interpreter when parsing commands and reporting results. If the current units differ from the set_unit value a warning is printed. Use the set_cmd_units command to change the command units. + The set_units command is used to check the units used by the STA command interpreter when parsing commands and reporting results. If the current units differ from the set_unit value a warning is printed. Use the set_cmd_units command to change the command units. Units are specified as a scale factor followed by a unit name. The scale factors are as follows. - M 1E+6k 1E+3m 1E-3u 1E-6n 1E-9p 1E-12f 1E-15 + M 1E+6k 1E+3m 1E-3u 1E-6n 1E-9p 1E-12f 1E-15 An example of the set_units command is shown below. - set_units -time ns -capacitance pF -current mA -voltage V -resistance kOhm + set_units -time ns -capacitance pF -current mA -voltage V -resistance kOhm - set_wire_load_min_block_size + set_wire_load_min_block_size - size + size @@ -12733,34 +12909,34 @@ - set_wire_load_mode + set_wire_load_mode - top|enclosed|segmented + top|enclosed|segmented - top + top - + - enclosed + enclosed - + - segmented + segmented - + @@ -12770,50 +12946,50 @@ - set_wire_load_model + set_wire_load_model - -name model_name[-library library][-max][-min][objects] + -name model_name[-library library][-max][-min][objects] - -name model_name + -name model_name - The name of a wire load model. + The name of a wire load model. - -library library + -library library - Library to look for model_name. + Library to look for model_name. - -max + -max - The wire load model is for maximum path delays. + The wire load model is for maximum path delays. - -min + -min - The wire load model is for minimum path delays. + The wire load model is for minimum path delays. - objects + objects - Not supported. + Not supported. @@ -12823,51 +12999,51 @@ - set_wire_load_selection_group + set_wire_load_selection_group - [-library library][-max][-min]group_name[objects] + [-library library][-max][-min]group_name[objects] - library + library - Library to look for group_name. + Library to look for group_name. - -max + -max - The wire load selection is for maximum path delays. + The wire load selection is for maximum path delays. - -min + -min - The wire load selection is for minimum path delays. + The wire load selection is for minimum path delays. - group_name + group_name - A wire load selection group name. + A wire load selection group name. - objects + objects - Not supported. + Not supported. @@ -12877,68 +13053,68 @@ - suppress_msg + suppress_msg - msg_ids + msg_ids - msg_ids + msg_ids - A list of error/warning message IDs to suppress. + A list of error/warning message IDs to suppress. - The suppress_msg command suppresses specified error/warning messages by ID. The list of message IDs can be found in doc/messages.txt. + The suppress_msg command suppresses specified error/warning messages by ID. The list of message IDs can be found in doc/messages.txt. - unset_case_analysis + unset_case_analysis - port_or_pin_list + port_or_pin_list - port_or_pin_list + port_or_pin_list - A list of ports or pins. + A list of ports or pins. - The unset_case_analysis command removes the constant values defined by the set_case_analysis command. + The unset_case_analysis command removes the constant values defined by the set_case_analysis command. - unset_clock_latency + unset_clock_latency - [-source]objects + [-source]objects - -source + -source - Specifies source clock latency (clock insertion delay). + Specifies source clock latency (clock insertion delay). - objects + objects - A list of clocks, pins or ports. + A list of clocks, pins or ports. @@ -12948,18 +13124,18 @@ - unset_clock_transition + unset_clock_transition - clocks + clocks - clocks + clocks - A list of clocks. + A list of clocks. @@ -12970,74 +13146,74 @@ - unset_clock_uncertainty + unset_clock_uncertainty - [-from|-rise_from|-fall_from from_clock][-to|-rise_to|-fall_to to_clock][-rise][-fall][-setup][-hold][objects] + [-from|-rise_from|-fall_from from_clock][-to|-rise_to|-fall_to to_clock][-rise][-fall][-setup][-hold][objects] - -from from_clock + -from from_clock - + - -to to_clock + -to to_clock - + - -rise + -rise - The uncertainty is for the rising edge of the clock. + The uncertainty is for the rising edge of the clock. - -fall + -fall - The uncertainty is for the falling edge of the clock. + The uncertainty is for the falling edge of the clock. - -setup + -setup - uncertainty is the setup check uncertainty. + uncertainty is the setup check uncertainty. - -hold + -hold - uncertainty is the hold uncertainty. + uncertainty is the hold uncertainty. - uncertainty + uncertainty - Clock uncertainty. + Clock uncertainty. - objects + objects - A list of clocks, ports or pins. + A list of clocks, ports or pins. @@ -13047,50 +13223,50 @@ - unset_data_check + unset_data_check - [-from|-rise_from|-fall_from from_object][-to|-rise_to|-fall_to to_object][-setup][-hold][-clock clock] + [-from|-rise_from|-fall_from from_object][-to|-rise_to|-fall_to to_object][-setup][-hold][-clock clock] - -from from_object + -from from_object - A pin used as the timing check reference. + A pin used as the timing check reference. - -to to_object + -to to_object - A pin that the setup/hold check is applied to. + A pin that the setup/hold check is applied to. - -setup + -setup - Add a setup timing check. + Add a setup timing check. - -hold + -hold - Add a hold timing check. + Add a hold timing check. - clock + clock - The setup/hold check clock. + The setup/hold check clock. @@ -13100,52 +13276,52 @@ - unset_disable_inferred_clock_gating + unset_disable_inferred_clock_gating - objects + objects - objects + objects - A list of clock gating instances, clock gating pins, or clock enable pins. + A list of clock gating instances, clock gating pins, or clock enable pins. - The unset_disable_inferred_clock_gating command removes a previous set_disable_inferred_clock_gating command. + The unset_disable_inferred_clock_gating command removes a previous set_disable_inferred_clock_gating command. - unset_disable_timing + unset_disable_timing - [-from from_port][-to to_port]objects + [-from from_port][-to to_port]objects - from_port + from_port - + - to_port + to_port - + - objects + objects A list of instances, ports, pins, cells or [library/]cell/port. @@ -13158,67 +13334,67 @@ - unset_input_delay + unset_input_delay - [-rise][-fall][-max][-min][-clock clock][-clock_fall]port_pin_list + [-rise][-fall][-max][-min][-clock clock][-clock_fall]port_pin_list - -rise + -rise - Unset the arrival time for the rising edge of the input. + Unset the arrival time for the rising edge of the input. - -fall + -fall - Unset the arrival time for the falling edge of the input. + Unset the arrival time for the falling edge of the input. - -max + -max - Unset the minimum arrival time. + Unset the minimum arrival time. - -min + -min - Unset the maximum arrival time. + Unset the maximum arrival time. - clock + clock - Unset the arrival time from clock. + Unset the arrival time from clock. - -clock_fall + -clock_fall - Unset the arrival time from the falling edge of clock + Unset the arrival time from the falling edge of clock - pin_port_list + pin_port_list - A list of pins or ports. + A list of pins or ports. @@ -13228,66 +13404,66 @@ - unset_output_delay + unset_output_delay - [-rise][-fall][-max][-min][-clock clock][-clock_fall]port_pin_list + [-rise][-fall][-max][-min][-clock clock][-clock_fall]port_pin_list - -rise + -rise - This is the arrival time for the rising edge of the input. + This is the arrival time for the rising edge of the input. - -fall + -fall - This is the arrival time for the falling edge of the input. + This is the arrival time for the falling edge of the input. - -max + -max - This is the minimum arrival time. + This is the minimum arrival time. - -min + -min - This is the maximum arrival time. + This is the maximum arrival time. - clock + clock - The arrival time is from this clock. + The arrival time is from this clock. - -clock_fall + -clock_fall - The arrival time is from the falling edge of clock + The arrival time is from the falling edge of clock - pin_port_list + pin_port_list - A list of pins or ports. + A list of pins or ports. @@ -13297,48 +13473,48 @@ - unset_path_exceptions + unset_path_exceptions - [-setup][-hold][-rise][-fall][-from|-rise_from|-fall_from from][-through|-rise_through|-fall_through through][-to|-rise_to|-fall_to to] + [-setup][-hold][-rise][-fall][-from|-rise_from|-fall_from from][-through|-rise_through|-fall_through through][-to|-rise_to|-fall_to to] - -setup + -setup - Unset path exceptions for setup checks. + Unset path exceptions for setup checks. - -hold + -hold - Unset path exceptions for hold checks. + Unset path exceptions for hold checks. - -rise + -rise - Unset path exceptions for rising path edges. + Unset path exceptions for rising path edges. - -fall + -fall - Unset path exceptions for falling path edges. + Unset path exceptions for falling path edges. - -from from + -from from A list of clocks, instances, ports or pins. @@ -13346,7 +13522,7 @@ - -through through + -through through A list of instances, pins or nets. @@ -13354,7 +13530,7 @@ - -to to + -to to A list of clocks, instances, ports or pins. @@ -13362,74 +13538,74 @@ The unset_path_exceptions command removes any matching set_false_path, set_multicycle_path, set_max_delay, and set_min_delay exceptions. - + - unset_power_activity + unset_power_activity - [-global][-input][-input_ports ports][-pins pins] + [-global][-input][-input_ports ports][-pins pins] - -global + -global - Set the activity/duty for all non-clock pins. + Set the activity/duty for all non-clock pins. - -input + -input - Set the default input port activity/duty. + Set the default input port activity/duty. - -input_ports input_ports + -input_ports input_ports - Set the input port activity/duty. + Set the input port activity/duty. - -pins pins + -pins pins - Set the pin activity/duty. + Set the pin activity/duty. - -activity activity + -activity activity - The activity, or number of transitions per clock cycle. If clock is not specified the clock with the minimum period is used. If no clocks are defined an error is reported. + The activity, or number of transitions per clock cycle. If clock is not specified the clock with the minimum period is used. If no clocks are defined an error is reported. - The unset_power_activity_command is used to undo the effects of the set_power_activity command. + The unset_power_activity_command is used to undo the effects of the set_power_activity command. - unset_propagated_clock + unset_propagated_clock - objects + objects - objects + objects A list of clocks, ports or pins. @@ -13442,45 +13618,45 @@ - unset_timing_derate + unset_timing_derate - + - Remove all derating factors set with the set_timing_derate command. + Remove all derating factors set with the set_timing_derate command. - unsuppress_msg + unsuppress_msg - msg_ids + msg_ids - msg_ids + msg_ids - A list of error/warning message IDs to unsuppress. + A list of error/warning message IDs to unsuppress. - The unsuppress_msg command removes suppressions for the specified error/warning messages by ID. The list of message IDs can be found in doc/messages.txt. + The unsuppress_msg command removes suppressions for the specified error/warning messages by ID. The list of message IDs can be found in doc/messages.txt. - user_run_time + user_run_time - + @@ -13490,145 +13666,145 @@ - with_output_to_variable + with_output_to_variable - var { commands } + var { commands } - var + var - The name of a variable to save the output of commands to. + The name of a variable to save the output of commands to. - commands + commands - TCL commands that the output will be redirected from. + TCL commands that the output will be redirected from. - The with_output_to_variable command redirects the output of TCL commands to a variable. + The with_output_to_variable command redirects the output of TCL commands to a variable. - write_path_spice + write_path_spice - -path_args path_args-spice_directory spice_directory-lib_subckt_file lib_subckts_file-model_file model_file-power power-ground ground[-simulator hspice|ngspice|xyce] + -path_args path_args-spice_directory spice_directory-lib_subckt_file lib_subckts_file-model_file model_file-power power-ground ground[-simulator hspice|ngspice|xyce] - path_args + path_args - -from|-through|-to arguments as in report_checks. + -from|-through|-to arguments as in report_checks. - spice_directory + spice_directory - Directory for spice to write output files. + Directory for spice to write output files. - lib_subckts_file + lib_subckts_file - Cell transistor level subckts. + Cell transistor level subckts. - model_file + model_file - Transistor model definitions .included by spice_file. + Transistor model definitions .included by spice_file. - power + power - Voltage supply name in voltage_map of the default liberty library. + Voltage supply name in voltage_map of the default liberty library. - ground + ground - Ground supply name in voltage_map of the default liberty library. + Ground supply name in voltage_map of the default liberty library. - -simulator + -simulator - Simulator that will read the spice netlist. + Simulator that will read the spice netlist. - The write_path_spice command writes a spice netlist for timing paths. Use path_args to specify -from/-through/-to as arguments to the find_timing_paths command. For each path, a spice netlist and the subckts referenced by the path are written in spice_directory. The spice netlist is written in path_<id>.sp and subckt file is path_<id>.subckt. - The spice netlists used by the path are written to subckt_file, which spice_file .includes. The device models used by the spice subckt netlists in model_file are also .included in spice_file. Power and ground names are specified with the -power and -ground arguments. The spice netlist includes a piecewise linear voltage source at the input and .measure statement for each gate delay and pin slew. - Example command: - write_path_spice -path_args {-from "in0" -to "out1" -unconstrained} \ -spice_directory $result_dir \ -lib_subckt_file "write_spice1.subckt" \ -model_file "write_spice1.models" \ -power VDD -ground VSS - When the simulator is hspice, .measure statements will be added to the spice netlist. - When the simulator is Xyce, the .print statement selects the CSV format and writes the waveform data to a file name path_<id>.csv so the results can be used by gnuplot. + The write_path_spice command writes a spice netlist for timing paths. Use path_args to specify -from/-through/-to as arguments to the find_timing_paths command. For each path, a spice netlist and the subckts referenced by the path are written in spice_directory. The spice netlist is written in path_<id>.sp and subckt file is path_<id>.subckt. + The spice netlists used by the path are written to subckt_file, which spice_file .includes. The device models used by the spice subckt netlists in model_file are also .included in spice_file. Power and ground names are specified with the -power and -ground arguments. The spice netlist includes a piecewise linear voltage source at the input and .measure statement for each gate delay and pin slew. + Example command: + write_path_spice -path_args {-from "in0" -to "out1" -unconstrained} \ -spice_directory $result_dir \ -lib_subckt_file "write_spice1.subckt" \ -model_file "write_spice1.models" \ -power VDD -ground VSS + When the simulator is hspice, .measure statements will be added to the spice netlist. + When the simulator is Xyce, the .print statement selects the CSV format and writes the waveform data to a file name path_<id>.csv so the results can be used by gnuplot. - write_sdc + write_sdc - [-digits digits][-gzip][-no_timestamp]filename + [-digits digits][-gzip][-no_timestamp]filename - digits + digits - The number of digits after the decimal point to report. The default is 4. + The number of digits after the decimal point to report. The default is 4. - -gzip + -gzip - Compress the SDC with gzip. + Compress the SDC with gzip. - -no_timestamp + -no_timestamp - Do not include a time and date in the SDC file. + Do not include a time and date in the SDC file. - filename + filename - The name of the file to write the constraints to. + The name of the file to write the constraints to. @@ -13638,295 +13814,281 @@ - write_sdf + write_sdf - [-corner corner][-divider /|.][-include_typ][-digits digits][-gzip][-no_timestamp][-no_version]filename + [-scene scene][-divider /|.][-include_typ][-digits digits][-gzip][-no_timestamp][-no_version]filename - corner + scene - Write delays for corner. + Write delays for scene. - -divider + -divider - Divider to use between hierarchy levels in pin and instance names. + Divider to use between hierarchy levels in pin and instance names. - -include_typ + -include_typ - Include a 'typ' value in the SDF triple that is the average of min and max delays to satisfy some Verilog simulators that require three values in the delay triples. + Include a 'typ' value in the SDF triple that is the average of min and max delays to satisfy some Verilog simulators that require three values in the delay triples. - -digits digits + -digits digits - The number of digits after the decimal point to report. The default is 4. + The number of digits after the decimal point to report. The default is 4. - -gzip + -gzip - Compress the SDF using gzip. + Compress the SDF using gzip. - -no_timestamp + -no_timestamp - Do not write a DATE statement. + Do not write a DATE statement. - -no_version + -no_version - Do not write a VERSION statement. + Do not write a VERSION statement. - filename + filename - The SDF filename to write. + The SDF filename to write. - Write the delay calculation delays for the design in SDF format to filename. If -corner is not specified the min/max delays are across all corners. With -corner the min/max delays for corner are written. The SDF TIMESCALE is same as the time_unit in the first liberty file read. + Write the delay calculation delays for the design in SDF format to filename. If -corner is not specified the min/max delays are across all corners. With -corner the min/max delays for corner are written. The SDF TIMESCALE is same as the time_unit in the first liberty file read. - write_timing_model + write_timing_model - [-library_name lib_name][-cell_name cell_name] - [-corner corner]filename + [-library_name lib_name][-cell_name cell_name] + [-scene scene]filename - -library_name lib_name + lib_name - The name to use for the liberty library. Defaults to cell_name. + The name to use for the liberty library. Defaults to cell_name. - -cell_name cell_name + cell_name - The name to use for the liberty cell. Defaults to the top level module name. + The name to use for the liberty cell. Defaults to the top level module name. - -corner corner + scene - The process corner to use for extracting the model. + The scene to use for extracting the model. - filename + filename - Filename for the liberty timing model. + Filename for the liberty timing model. - The write_timing_model command constructs a liberty timing model for the current design and writes it to filename. cell_name defaults to the cell name of the top level block in the design. - The SDC used to extract the block should include the clock definitions. If the block contains a clock network set_propagated_clock should be used so the clock delays are included in the timing model. The following SDC commands are ignored when building the timing model. - set_input_delayset_output_delayset_loadset_timing_derate - Using set_input_transition with the slew from the block context will be used will improve the match between the timing model and the block netlist. Paths defined on clocks that are defined on internal pins are ignored because the model has no way to include the clock definition. + The write_timing_model command constructs a liberty timing model for the current design and writes it to filename. cell_name defaults to the cell name of the top level block in the design. + The SDC used to extract the block should include the clock definitions. If the block contains a clock network set_propagated_clock should be used so the clock delays are included in the timing model. The following SDC commands are ignored when building the timing model. + set_input_delayset_output_delayset_loadset_timing_derate + Using set_input_transition with the slew from the block context will be used will improve the match between the timing model and the block netlist. Paths defined on clocks that are defined on internal pins are ignored because the model has no way to include the clock definition. The resulting timing model can be used in a hierarchical timing flow as a replacement for the block to speed up timing analysis. This hierarchical timing methodology does not handle timing exceptions that originate or terminate inside the block. The timing model includes: - combinational paths between inputs and outputssetup and hold timing constraints on inputsclock to output timing paths - Resistance of long wires on inputs and outputs of the block cannot be modeled in Liberty. To reduce inaccuracies from wire resistance in technologies with resistive wires place buffers on inputs and ouputs. + combinational paths between inputs and outputssetup and hold timing constraints on inputsclock to output timing paths + Resistance of long wires on inputs and outputs of the block cannot be modeled in Liberty. To reduce inaccuracies from wire resistance in technologies with resistive wires place buffers on inputs and ouputs. The extracted timing model setup/hold checks are scalar (no input slew dependence). Delay timing arcs are load dependent but do not include input slew dependency. - write_verilog + write_verilog - [-include_pwr_gnd][-remove_cells lib_cells]filename + [-include_pwr_gnd][-remove_cells lib_cells]filename - -include_pwr_gnd + -include_pwr_gnd - Include power and ground pins on instances. + Include power and ground pins on instances. - -remove_cells lib_cells + -remove_cells lib_cells - Liberty cells to remove from the Verilog netlist. Use get_lib_cells, a list of cells names, or a cell name with wildcards. + Liberty cells to remove from the Verilog netlist. Use get_lib_cells, a list of cells names, or a cell name with wildcards. - filename + filename - Filename for the liberty library. + Filename for the liberty library. - The write_verilog command writes a Verilog netlist to filename. Instances are always sorted so the results are reproducible across operating systems. Use -remove_cells to remove instances of lib_cells from the netlist. - Filter Expressions - The get_cells, get_pins, get_ports and get_timing_edges functions support filtering the returned objects by property values. Supported filter expressions are shown below. + The write_verilog command writes a Verilog netlist to filename. Use -sort to sort the instances so the results are reproducible across operating systems. Use -remove_cells to remove instances of lib_cells from the netlist. + Filter Expressions + The get_cells, get_pins, get_ports and get_timing_edges functions support filtering the returned objects by property values. Supported filter expressions are shown below. - property + property - Return objects with property value equal to 1. + Return objects with property value equal to 1. - property==value + property==value - Return objects with property value equal to value. + Return objects with property value equal to value. - property=~pattern + property=~pattern - Return objects with property value that matches pattern. + Return objects with property value that matches pattern. - property!=value + property!=value - Return objects with property value not equal to value. + Return objects with property value not equal to value. - property!~value + property!~value - Return objects with property value that does not match pattern. + Return objects with property value that does not match pattern. - expr1&&expr2 + expr1&&expr2 - Return objects with expr1 and expr2. expr1 and expr2 are one of the first three property value forms shown above. + Return objects with expr1 and expr2. expr1 and expr2 are one of the first three property value forms shown above. - - expr1||expr2 + expr1||expr2 - Return objects with expr1 or expr2. expr1 and expr2 are one of the first three property value forms shown above. + Return objects with expr1 or expr2. expr1 and expr2 are one of the first three property value forms shown above. - Where property is a property supported by the get_property command. Note that if there are spaces in the expression it must be enclosed in quotes so that it is a single argument. - Variables + Where property is a property supported by the get_property command. Note that if there are spaces in the expression it must be enclosed in quotes so that it is a single argument. + Variables - hierarchy_separator + hierarchy_separator - Any character. + Any character. The hierarchy_separator separates instance names in a hierarchical instance, net, or pin name. The default value is '/'. - - - - - - sta_bidirect_net_paths_enabled - - - 0|1 - - - - When set to 0, paths from bidirectional (inout) ports back through nets are disabled. When set to 1, paths from bidirectional paths from the net back into the instance are enabled. The default value is 0. - sta_continue_on_error + sta_continue_on_error - 0|1 + 0|1 - The include and read_sdc commands stop and report any errors encountered while reading a file unless sta_continue_on_error is 1. The default value is 0. + The include and read_sdc commands stop and report any errors encountered while reading a file unless sta_continue_on_error is 1. The default value is 0. - sta_crpr_mode + sta_crpr_mode - same_pin|same_transition + same_pin|same_transition - When the data and clock paths of a timing check overlap (see sta_crpr_enabled), pessimism is removed independent of whether of the path rise/fall transitions. When sta_crpr_mode is same_transition, the pessimism is only removed if the path rise/fall transitions are the same. The default value is same_pin. + When the data and clock paths of a timing check overlap (see sta_crpr_enabled), pessimism is removed independent of whether of the path rise/fall transitions. When sta_crpr_mode is same_transition, the pessimism is only removed if the path rise/fall transitions are the same. The default value is same_pin. - sta_cond_default_arcs_enabled + sta_cond_default_arcs_enabled - 0|1 + 0|1 @@ -13936,49 +14098,49 @@ - sta_crpr_enabled + sta_crpr_enabled - 0|1 + 0|1 - During min/max timing analysis for on_chip_variation the data and clock paths may overlap. For a setup check the maximum path delays are used for the data and the minimum path delays are used for the clock. Because the gates cannot simultaneously have minimum and maximum delays the timing check slack is pessimistic. This pessimism is known as Common Reconvergent Pessimism Removal, or “CRPR”. Enabling CRPR slows down the analysis. The default value is 1. + During min/max timing analysis for on_chip_variation the data and clock paths may overlap. For a setup check the maximum path delays are used for the data and the minimum path delays are used for the clock. Because the gates cannot simultaneously have minimum and maximum delays the timing check slack is pessimistic. This pessimism is known as Common Reconvergent Pessimism Removal, or “CRPR”. Enabling CRPR slows down the analysis. The default value is 1. - sta_dynamic_loop_breaking + sta_dynamic_loop_breaking - 0|1 + 0|1 - When sta_dynamic_loop_breaking is 0, combinational logic loops are disabled by disabling a timing arc that closes the loop. When sta_dynamic_loop_breaking is 1, all paths around the loop are reported. The default value is 0. + When sta_dynamic_loop_breaking is 0, combinational logic loops are disabled by disabling a timing arc that closes the loop. When sta_dynamic_loop_breaking is 1, all paths around the loop are reported. The default value is 0. - sta_gated_clock_checks_enabled + sta_gated_clock_checks_enabled - 0|1 + 0|1 - When sta_gated_clock_checks_enabled is 1, clock gating setup and hold timing checks are checked. The default value is 1. + When sta_gated_clock_checks_enabled is 1, clock gating setup and hold timing checks are checked. The default value is 1. - sta_input_port_default_clock + sta_input_port_default_clock - 0|1 + 0|1 @@ -13988,10 +14150,10 @@ - sta_internal_bidirect_instance_paths_enabled + sta_internal_bidirect_instance_paths_enabled - 0|1 + 0|1 @@ -14001,10 +14163,10 @@ - sta_pocv_enabled + sta_pocv_enabled - 0|1 + 0|1 @@ -14014,14 +14176,14 @@ - sta_propagate_all_clocks + sta_propagate_all_clocks - 0|1 + 0|1 - All clocks defined after sta_propagate_all_clocks is set to 1 are propagated. If it is set before any clocks are defined it has the same effect as + All clocks defined after sta_propagate_all_clocks is set to 1 are propagated. If it is set before any clocks are defined it has the same effect as set_propagated_clock [all_clocks] After all clocks have been defined. The default value is 0. @@ -14029,37 +14191,36 @@ - sta_propagate_gated_clock_enable + sta_propagate_gated_clock_enable - 0|1 + 0|1 - When set to 1, paths of gated clock enables are propagated through the clock gating instances. If the gated clock controls sequential elements setting sta_propagate_gated_clock_enable to 0 prevents spurious paths from the clock enable. The default value is 1. + When set to 1, paths of gated clock enables are propagated through the clock gating instances. If the gated clock controls sequential elements setting sta_propagate_gated_clock_enable to 0 prevents spurious paths from the clock enable. The default value is 1. - sta_recovery_removal_checks_enabled + sta_recovery_removal_checks_enabled - 0|1 + 0|1 - When sta_recovery_removal_checks_enabled is 0, recovery and removal timing checks are disabled. The default value is 1. + When sta_recovery_removal_checks_enabled is 0, recovery and removal timing checks are disabled. The default value is 1. - - sta_report_default_digits + sta_report_default_digits - integer + integer @@ -14067,12 +14228,13 @@ + - sta_preset_clear_arcs_enabled + sta_preset_clear_arcs_enabled - 0|1 + 0|1 @@ -14102,184 +14264,186 @@ - Alphabetical Index + Alphabetical Index - all_clocks6 - all_inputs6 - all_outputs6 - all_registers6 - check_setup7 - Command Line Arguments1 - Commands6 - connect_pin7 - create_generated_clock9 - create_voltage_area10 - current_design10 - current_instance10 - define_corners11 - delete_clock11 - delete_from_list11 - delete_generated_clock11 - delete_instance11 - delete_net12 - disconnect_pin12 - elapsed_run_time12 - Example Command Scripts1 - Filter Expressions80 - find_timing_paths13 - get_cells14 - get_clocks15 - get_fanin16 - get_fanout16 - get_full_name17 - get_lib_pins18 - get_libs18 - get_name20 - get_nets19 - get_pins20 - get_ports21 - get_property21 - get_timing_edges24 - group_path25 - hierarchy_separator80 - include26 - link_design26 - make_instance26 - make_net27 - Power Analysis2 - read_liberty27 - read_saif28 - read_sdc28 - read_sdf28 - read_spef29 - read_vcd31 - read_verilog31 - redirection4 - replace_activity_annotation31 - replace_cell31 - report_annotated_check32 - report_annotated_delay33 - report_check_types36 - report_checks34 - report_clock_latency37 - report_clock_min_period38 - report_clock_properties38 - report_clock_skew38 - report_dcalc39 - report_disabled_edges39 - report_edges39 - report_instance40 - report_lib_cell40 - report_net40 - report_parasitic_annotation40 - report_power41 - report_pulse_width_checks41 - report_slews42 - report_tns42 - report_units42 - report_wns43 - report_worst_slack43 - set_assigned_check43 - set_assigned_delay44 - set_assigned_transition45 - set_case_analysis46 - set_clock_gating_check46 - set_clock_groups47 - set_clock_latency47 - set_clock_transition48 - set_clock_uncertainty49 - set_cmd_units50 - set_data_check51 - set_disable_inferred_clock_gating51 - set_disable_timing51 - set_drive52 - set_driving_cell53 - set_false_path54 - set_fanout_load55 - set_hierarchy_separator55 - set_ideal_latency55 - set_ideal_network55 - set_ideal_transition55 - set_input_delay55 - set_input_transition57 - set_level_shifter_strategy57 - set_level_shifter_threshold57 - set_load57 - set_logic_dc58 - set_logic_one58 - set_logic_zero59 - set_max_area59 - set_max_capacitance59 - set_max_delay59 - set_max_dynamic_power60 - set_max_fanout60 - set_max_leakage_power60 - set_max_time_borrow60 - set_max_transition61 - set_min_capacitance61 - set_min_delay62 - set_min_pulse_width62 - set_multicycle_path63 - set_operating_conditions64 - set_output_delay65 - set_port_fanout_number66 - set_power_activity66 - set_propagated_clock67 - set_pvt67 - set_resistance69 - set_sense68 - set_timing_derate69 - set_units70 - set_wire_load_min_block_size71 - set_wire_load_mode71 - set_wire_load_model71 - set_wire_load_selection_group71 - SPEF30 - sta_bidirect_net_paths_enabled80 - sta_cond_default_arcs_enabled81 - sta_continue_on_error80 - sta_crpr_enabled81 - sta_crpr_mode81 - sta_dynamic_loop_breaking81 - sta_gated_clock_checks_enabled81 - sta_input_port_default_clock81 - sta_internal_bidirect_instance_paths_enabled81 - sta_pocv_enabled82 - sta_preset_clear_arcs_enabled82 - sta_propagate_all_clocks82 - sta_propagate_gated_clock_enable82 - sta_recovery_removal_checks_enabled82 - sta_report_default_digits82 - suppress_msg72 - TCL Interpreter3 - Timing Analysis using SDF2 - Timing Analysis with Multiple Process Corners2 - unset_case_analysis72 - unset_clock_latency72 - unset_clock_transition72 - unset_clock_uncertainty73 - unset_data_check73 - unset_disable_inferred_clock_gating74 - unset_disable_timing74 - unset_input_delay74 - unset_output_delay75 - unset_path_exceptions75 - unset_propagated_clock76 - unset_timing_derate76 - unsuppress_msg76 - user_run_time76 - Variables80 - verilog netlist31 - with_output_to_variable76 - write_path_spice77 - write_sdc77 - write_sdf78 - write_timing_model78 - write_verilog79 + all_clocks7 + all_inputs7 + all_outputs8 + all_registers8 + check_setup9 + Command Line Arguments1 + Commands7 + connect_pin9 + create_generated_clock11 + create_voltage_area12 + current_design12 + current_instance13 + define_scene13 + delete_clock13 + delete_from_list13 + delete_generated_clock13 + delete_instance14 + delete_net14 + disconnect_pin14 + elapsed_run_time14 + Example Command Scripts1 + Filter Expressions84 + find_timing_paths15 + get_cells17 + get_clocks17 + get_fanin18 + get_fanout19 + get_full_name19 + get_lib_pins20 + get_libs21 + get_name22 + get_nets22 + get_pins23 + get_ports23 + get_property24 + get_scenes28 + get_timing_edges28 + group_path29 + hierarchy_separator85 + include30 + link_design30 + make_instance30 + make_net31 + Power Analysis3 + read_liberty31 + read_saif32 + read_sdc33 + read_sdf33 + read_spef34 + read_vcd35 + read_verilog35 + redirection5 + replace_activity_annotation36 + replace_cell35 + report_annotated_check36 + report_annotated_delay37 + report_check_types41 + report_checks38 + report_clock_latency42 + report_clock_min_period42 + report_clock_properties43 + report_clock_skew43 + report_dcalc43 + report_disabled_edges44 + report_edges44 + report_instance44 + report_lib_cell44 + report_net45 + report_parasitic_annotation45 + report_power45 + report_slews46 + report_tns46 + report_units46 + report_wns47 + report_worst_slack47 + set_assigned_check48 + set_assigned_delay49 + set_assigned_transition49 + set_case_analysis50 + set_clock_gating_check50 + set_clock_groups51 + set_clock_latency52 + set_clock_transition52 + set_clock_uncertainty53 + set_cmd_units54 + set_data_check55 + set_disable_inferred_clock_gating55 + set_disable_timing55 + set_drive56 + set_driving_cell57 + set_false_path58 + set_fanout_load59 + set_hierarchy_separator59 + set_ideal_latency59 + set_ideal_network59 + set_ideal_transition59 + set_input_delay59 + set_input_transition61 + set_level_shifter_strategy61 + set_level_shifter_threshold61 + set_load61 + set_logic_dc62 + set_logic_one62 + set_logic_zero63 + set_max_area63 + set_max_capacitance63 + set_max_delay63 + set_max_dynamic_power64 + set_max_fanout64 + set_max_leakage_power64 + set_max_time_borrow64 + set_max_transition65 + set_min_capacitance65 + set_min_delay66 + set_min_pulse_width67 + set_mode67 + set_multicycle_path67 + set_operating_conditions68 + set_output_delay69 + set_port_fanout_number70 + set_power_activity70 + set_propagated_clock71 + set_pvt71 + set_resistance73 + set_sense72 + set_timing_derate73 + set_units74 + set_wire_load_min_block_size75 + set_wire_load_mode75 + set_wire_load_model75 + set_wire_load_selection_group75 + SPEF34 + sta_cond_default_arcs_enabled85 + sta_continue_on_error85 + sta_crpr_enabled85 + sta_crpr_mode85 + sta_dynamic_loop_breaking85 + sta_gated_clock_checks_enabled85 + sta_input_port_default_clock86 + sta_internal_bidirect_instance_paths_enabled86 + sta_pocv_enabled86 + sta_preset_clear_arcs_enabled87 + sta_propagate_all_clocks86 + sta_propagate_gated_clock_enable86 + sta_recovery_removal_checks_enabled86 + sta_report_default_digits86 + suppress_msg76 + TCL Interpreter5 + Timing Analysis using SDF2 + Timing Analysis with Multiple Modes3 + Timing Analysis with Multiple Process Corners2 + unset_case_analysis76 + unset_clock_latency76 + unset_clock_transition76 + unset_clock_uncertainty77 + unset_data_check77 + unset_disable_inferred_clock_gating78 + unset_disable_timing78 + unset_input_delay78 + unset_output_delay79 + unset_path_exceptions79 + unset_power_activity80 + unset_propagated_clock80 + unset_timing_derate80 + unsuppress_msg81 + user_run_time81 + Variables85 + verilog netlist35 + with_output_to_variable81 + write_path_spice81 + write_sdc82 + write_sdf82 + write_timing_model83 + write_verilog84 - - Version 2.6.0, Sep 23, 2024Copyright (c) 2024, Parallax Software, Inc. + + Version 2.6.0, Sep 23, 2024Copyright (c) 2024, Parallax Software, Inc. This program is free software: you can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free Software Foundation, either version 3 of the License, or (at your option) any later version. This program is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details. You should have received a copy of the GNU General Public License along with this program. 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zM68igfduu_w!R6>DP>ToG&%1oS75x0`3+&SuJL88tPdJ(6HL==Q2(WDN}j zx!Z_`gtFFNSOq$T&s$A;G`ZaGUt%Fsr93icI!6A~Xm2Sj?YhANNux^}%PRK8%084> zOs@gHpF>#*)##)hHPE%3+Dm{-WBHQHV4(nBTZ6r}jHV%lT((a*-_L9|7gc@?b;PKA zCy;D2sw24!E!icA2a8?Cru#0S_g=>l@PONcjZ9xpfNC#s8d8A%VYrc$Y+Bgcxd3cfG z%XV<2qOD+PuT*dm$IQ(dH-__i@q9l8_d7csAg(Sja_r7DxnIS1x#=w3;7_ zLi!Zb>~>XyHcBS<8yh`t@UK zF+Q}7P5=LoKYsJwzy0~ezy0}tZr_Z=OJWP}J~@HjzW$GoFF$;gXK{1DT%Xeq?|ysx u^2cA_dgsC)zx!7F%%8sb&)<9}*5qw8c;A2g;U9na!~X|^UIcx{TLb{k?yA24 literal 0 HcmV?d00001 diff --git a/examples/mcmm2_mode1.sdc b/examples/mcmm2_mode1.sdc new file mode 100644 index 00000000..d84bb579 --- /dev/null +++ b/examples/mcmm2_mode1.sdc @@ -0,0 +1,2 @@ +create_clock -name m1_clk -period 1000 {clk1 clk2 clk3} +set_input_delay -clock m1_clk 100 {in1 in2} diff --git a/examples/mcmm2_mode2.sdc b/examples/mcmm2_mode2.sdc new file mode 100644 index 00000000..1eee9b1f --- /dev/null +++ b/examples/mcmm2_mode2.sdc @@ -0,0 +1,2 @@ +create_clock -name m2_clk -period 500 {clk1 clk3} +set_output_delay -clock m2_clk 100 out diff --git a/examples/mcmm3.tcl b/examples/mcmm3.tcl new file mode 100644 index 00000000..a846c2e2 --- /dev/null +++ b/examples/mcmm3.tcl @@ -0,0 +1,18 @@ +# mmcm reg1 parasitics +read_liberty asap7_small_ff.lib.gz +read_liberty asap7_small_ss.lib.gz +read_verilog reg1_asap7.v +link_design top + +read_sdc -mode mode1 mcmm2_mode1.sdc +read_sdc -mode mode2 mcmm2_mode2.sdc + +read_spef -name reg1_ff reg1_asap7.spef +read_spef -name reg1_ss reg1_asap7_ss.spef + +define_scene scene1 -mode mode1 -liberty asap7_small_ff -spef reg1_ff +define_scene scene2 -mode mode2 -liberty asap7_small_ss -spef reg1_ss + +report_checks -scenes scene1 +report_checks -scenes scene2 +report_checks -group_path_count 4 diff --git a/examples/multi_corner.tcl b/examples/multi_corner.tcl index 589ca9b7..f75c1528 100644 --- a/examples/multi_corner.tcl +++ b/examples/multi_corner.tcl @@ -1,15 +1,20 @@ -# 3 corners with +/- 10% derating example -define_corners ss tt ff -read_liberty -corner ss nangate45_slow.lib.gz -read_liberty -corner tt nangate45_typ.lib.gz -read_liberty -corner ff nangate45_fast.lib.gz +# 3 liberty corners with +/- 10% derating example +read_liberty nangate45_slow.lib.gz +read_liberty nangate45_typ.lib.gz +read_liberty nangate45_fast.lib.gz read_verilog example1.v link_design top set_timing_derate -early 0.9 set_timing_derate -late 1.1 create_clock -name clk -period 10 {clk1 clk2 clk3} set_input_delay -clock clk 0 {in1 in2} -# report all corners + +define_scene ss -liberty nangate45_slow +define_scene tt -liberty nangate45_typ +define_scene ff -liberty nangate45_fast + +# report all scenes report_checks -path_delay min_max -# report typical corner -report_checks -corner tt +# report typical scene +report_checks -scene tt + diff --git a/examples/reg1_asap7.spef b/examples/reg1_asap7.spef new file mode 100644 index 00000000..14bc4d6b --- /dev/null +++ b/examples/reg1_asap7.spef @@ -0,0 +1,135 @@ +*SPEF "IEEE 1481-1998" +*DESIGN "reg1" +*DATE "Fri Nov 20 13:23:00 2002" +*VENDOR "Parallax Software, Inc" +*PROGRAM "Handjob" +*VERSION "1.0.1c" +*DESIGN_FLOW "MISSING_NETS" +*DIVIDER / +*DELIMITER : +*BUS_DELIMITER [ ] +*T_UNIT 1.0 PS +*C_UNIT 1.0 FF +*R_UNIT 1.0 KOHM +*L_UNIT 1.0 UH + +*POWER_NETS VDD +*GROUND_NETS VSS + +*PORTS +in1 I +in2 I +clk1 I +clk2 I +clk3 I +out O + +*D_NET in1 13.4 +*CONN +*P in1 I +*I r1:D I *L .0036 +*CAP +1 in1 6.7 +2 r1:D 6.7 +*RES +3 in1 r1:D 2.42 +*END + +*D_NET in2 13.4 +*CONN +*P in2 I +*I r2:D I *L .0036 +*CAP +1 in2 6.7 +2 r2:D 6.7 +*RES +3 in2 r2:D 2.42 +*END + +*D_NET clk1 13.4 +*CONN +*P clk1 I +*I r1:CLK I *L .0036 +*CAP +1 clk1 6.7 +2 r1:CLK 6.7 +*RES +3 clk1 r1:CLK 2.42 +*END + +*D_NET clk2 13.4 +*CONN +*P clk2 I +*I r2:CLK I *L .0036 +*CAP +1 clk2 6.7 +2 r2:CLK 6.7 +*RES +3 clk2 r2:CLK 2.42 +*END + +*D_NET clk3 13.4 +*CONN +*P clk3 I +*I r3:CLK I *L .0036 +*CAP +1 clk3 6.7 +2 r3:CLK 6.7 +*RES +3 clk3 r3:CLK 2.42 +*END + +*D_NET r1q 13.4 +*CONN +*I r1:Q O +*I u2:A I *L .0086 +*CAP +1 r1:Q 6.7 +2 u2:A 6.7 +*RES +3 r1:Q u2:A 2.42 +*END + +*D_NET r2q 13.4 +*CONN +*I r2:Q O +*I u1:A I *L .0086 +*CAP +1 r2:Q 6.7 +2 u1:A 6.7 +*RES +3 r2:Q u1:A 2.42 +*END + +*D_NET u1z 13.4 +*CONN +*I u1:Y O +*I u2:B I *L .0086 +*CAP +1 u1:Y 6.7 +2 u2:B 6.7 +*RES +3 u1:Y u2:B 2.42 +*END + +*D_NET u2z 13.4 +*CONN +*I u2:Y O +*I r3:D I *L .0086 +*CAP +1 u2:Y 6.7 +2 r3:D 6.7 +*RES +3 u2:Y r3:D 2.42 +*END + +*D_NET out 13.4 +*CONN +*I r3:Q O +*P out O +*CAP +1 r3:Q 6.7 +2 out 6.7 +*RES +3 r3:Q out 2.42 +*END diff --git a/examples/reg1_asap7.v b/examples/reg1_asap7.v new file mode 100644 index 00000000..5eb10b46 --- /dev/null +++ b/examples/reg1_asap7.v @@ -0,0 +1,11 @@ +module top (in1, in2, clk1, clk2, clk3, out); + input in1, in2, clk1, clk2, clk3; + output out; + wire r1q, r2q, u1z, u2z; + + DFFHQx4_ASAP7_75t_R r1 (.D(in1), .CLK(clk1), .Q(r1q)); + DFFHQx4_ASAP7_75t_R r2 (.D(in2), .CLK(clk2), .Q(r2q)); + BUFx2_ASAP7_75t_R u1 (.A(r2q), .Y(u1z)); + AND2x2_ASAP7_75t_R u2 (.A(r1q), .B(u1z), .Y(u2z)); + DFFHQx4_ASAP7_75t_R r3 (.D(u2z), .CLK(clk3), .Q(out)); +endmodule // top diff --git a/examples/reg1_asap7_ss.spef b/examples/reg1_asap7_ss.spef new file mode 100644 index 00000000..fe49a5e5 --- /dev/null +++ b/examples/reg1_asap7_ss.spef @@ -0,0 +1,135 @@ +*SPEF "IEEE 1481-1998" +*DESIGN "reg1" +*DATE "Fri Nov 20 13:23:00 2002" +*VENDOR "Parallax Software, Inc" +*PROGRAM "Handjob" +*VERSION "1.0.1c" +*DESIGN_FLOW "MISSING_NETS" +*DIVIDER / +*DELIMITER : +*BUS_DELIMITER [ ] +*T_UNIT 1.0 PS +*C_UNIT 1.0 FF +*R_UNIT 1.0 KOHM +*L_UNIT 1.0 UH + +*POWER_NETS VDD +*GROUND_NETS VSS + +*PORTS +in1 I +in2 I +clk1 I +clk2 I +clk3 I +out O + +*D_NET in1 13.4 +*CONN +*P in1 I +*I r1:D I *L .0036 +*CAP +1 in1 8.1 +2 r1:D 8.1 +*RES +3 in1 r1:D 2.7 +*END + +*D_NET in2 13.4 +*CONN +*P in2 I +*I r2:D I *L .0036 +*CAP +1 in2 8.1 +2 r2:D 8.1 +*RES +3 in2 r2:D 2.7 +*END + +*D_NET clk1 13.4 +*CONN +*P clk1 I +*I r1:CLK I *L .0036 +*CAP +1 clk1 8.1 +2 r1:CLK 8.1 +*RES +3 clk1 r1:CLK 2.7 +*END + +*D_NET clk2 13.4 +*CONN +*P clk2 I +*I r2:CLK I *L .0036 +*CAP +1 clk2 8.1 +2 r2:CLK 8.1 +*RES +3 clk2 r2:CLK 2.7 +*END + +*D_NET clk3 13.4 +*CONN +*P clk3 I +*I r3:CLK I *L .0036 +*CAP +1 clk3 8.1 +2 r3:CLK 8.1 +*RES +3 clk3 r3:CLK 2.7 +*END + +*D_NET r1q 13.4 +*CONN +*I r1:Q O +*I u2:A I *L .0086 +*CAP +1 r1:Q 8.1 +2 u2:A 8.1 +*RES +3 r1:Q u2:A 2.7 +*END + +*D_NET r2q 13.4 +*CONN +*I r2:Q O +*I u1:A I *L .0086 +*CAP +1 r2:Q 8.1 +2 u1:A 8.1 +*RES +3 r2:Q u1:A 2.7 +*END + +*D_NET u1z 13.4 +*CONN +*I u1:Y O +*I u2:B I *L .0086 +*CAP +1 u1:Y 8.1 +2 u2:B 8.1 +*RES +3 u1:Y u2:B 2.7 +*END + +*D_NET u2z 13.4 +*CONN +*I u2:Y O +*I r3:D I *L .0086 +*CAP +1 u2:Y 8.1 +2 r3:D 8.1 +*RES +3 u2:Y r3:D 2.7 +*END + +*D_NET out 13.4 +*CONN +*I r3:Q O +*P out O +*CAP +1 r3:Q 8.1 +2 out 8.1 +*RES +3 r3:Q out 2.7 +*END diff --git a/graph/Delay.cc b/graph/Delay.cc index cfe32cff..2f538a30 100644 --- a/graph/Delay.cc +++ b/graph/Delay.cc @@ -32,7 +32,7 @@ namespace sta { const char * delayAsString(const Delay &delay, - const StaState *sta) + const StaState *sta) { return delayAsString(delay, sta, sta->units()->timeUnit()->digits()); } diff --git a/graph/DelayFloat.cc b/graph/DelayFloat.cc index a9a90dcf..73b877df 100644 --- a/graph/DelayFloat.cc +++ b/graph/DelayFloat.cc @@ -45,24 +45,24 @@ initDelayConstants() const char * delayAsString(const Delay &delay, - const StaState *sta) + const StaState *sta) { return delayAsString(delay, sta, sta->units()->timeUnit()->digits()); } const char * delayAsString(const Delay &delay, - const StaState *sta, - int digits) + const StaState *sta, + int digits) { return sta->units()->timeUnit()->asString(delay, digits); } const char * delayAsString(const Delay &delay, - const EarlyLate *, - const StaState *sta, - int digits) + const EarlyLate *, + const StaState *sta, + int digits) { const Unit *unit = sta->units()->timeUnit(); return unit->asString(delay, digits); @@ -76,7 +76,7 @@ delayInitValue(const MinMax *min_max) bool delayIsInitValue(const Delay &delay, - const MinMax *min_max) + const MinMax *min_max) { return fuzzyEqual(delay, min_max->initValue()); } @@ -95,24 +95,24 @@ delayInf(const Delay &delay) bool delayEqual(const Delay &delay1, - const Delay &delay2) + const Delay &delay2) { return fuzzyEqual(delay1, delay2); } bool delayLess(const Delay &delay1, - const Delay &delay2, - const StaState *) + const Delay &delay2, + const StaState *) { return fuzzyLess(delay1, delay2); } bool delayLess(const Delay &delay1, - const Delay &delay2, - const MinMax *min_max, - const StaState *) + const Delay &delay2, + const MinMax *min_max, + const StaState *) { if (min_max == MinMax::max()) return fuzzyLess(delay1, delay2); @@ -122,17 +122,17 @@ delayLess(const Delay &delay1, bool delayLessEqual(const Delay &delay1, - const Delay &delay2, - const StaState *) + const Delay &delay2, + const StaState *) { return fuzzyLessEqual(delay1, delay2); } bool delayLessEqual(const Delay &delay1, - const Delay &delay2, - const MinMax *min_max, - const StaState *) + const Delay &delay2, + const MinMax *min_max, + const StaState *) { if (min_max == MinMax::max()) return fuzzyLessEqual(delay1, delay2); @@ -142,17 +142,17 @@ delayLessEqual(const Delay &delay1, bool delayGreater(const Delay &delay1, - const Delay &delay2, - const StaState *) + const Delay &delay2, + const StaState *) { return fuzzyGreater(delay1, delay2); } bool delayGreater(const Delay &delay1, - const Delay &delay2, - const MinMax *min_max, - const StaState *) + const Delay &delay2, + const MinMax *min_max, + const StaState *) { if (min_max == MinMax::max()) return fuzzyGreater(delay1, delay2); @@ -162,17 +162,17 @@ delayGreater(const Delay &delay1, bool delayGreaterEqual(const Delay &delay1, - const Delay &delay2, - const StaState *) + const Delay &delay2, + const StaState *) { return fuzzyGreaterEqual(delay1, delay2); } bool delayGreaterEqual(const Delay &delay1, - const Delay &delay2, - const MinMax *min_max, - const StaState *) + const Delay &delay2, + const MinMax *min_max, + const StaState *) { if (min_max == MinMax::max()) return fuzzyGreaterEqual(delay1, delay2); @@ -182,14 +182,14 @@ delayGreaterEqual(const Delay &delay1, Delay delayRemove(const Delay &delay1, - const Delay &delay2) + const Delay &delay2) { return delay1 - delay2; } float delayRatio(const Delay &delay1, - const Delay &delay2) + const Delay &delay2) { return delay1 / delay2; } diff --git a/graph/DelayNormal1.cc b/graph/DelayNormal1.cc index d50db11f..2e855586 100644 --- a/graph/DelayNormal1.cc +++ b/graph/DelayNormal1.cc @@ -85,7 +85,7 @@ Delay::Delay(float mean) : } Delay::Delay(float mean, - float sigma2) : + float sigma2) : mean_(mean), sigma2_(sigma2) { @@ -139,7 +139,7 @@ Delay Delay::operator+(const Delay &delay) const { return Delay(mean_ + delay.mean_, - sigma2_ + delay.sigma2_); + sigma2_ + delay.sigma2_); } Delay @@ -152,7 +152,7 @@ Delay Delay::operator-(const Delay &delay) const { return Delay(mean_ - delay.mean_, - sigma2_ + delay.sigma2_); + sigma2_ + delay.sigma2_); } Delay @@ -219,24 +219,24 @@ DelayDbl::operator-=(const Delay &delay) Delay makeDelay(float delay, - float sigma, - float) + float sigma, + float) { return Delay(delay, square(sigma)); } Delay makeDelay2(float delay, - float sigma2, - float ) + float sigma2, + float ) { return Delay(delay, sigma2); } float delayAsFloat(const Delay &delay, - const EarlyLate *early_late, - const StaState *sta) + const EarlyLate *early_late, + const StaState *sta) { if (sta->variables()->pocvEnabled()) { if (early_late == EarlyLate::early()) @@ -251,29 +251,29 @@ delayAsFloat(const Delay &delay, float delaySigma2(const Delay &delay, - const EarlyLate *) + const EarlyLate *) { return delay.sigma2(); } const char * delayAsString(const Delay &delay, - const StaState *sta) + const StaState *sta) { return delayAsString(delay, sta, sta->units()->timeUnit()->digits()); } const char * delayAsString(const Delay &delay, - const StaState *sta, - int digits) + const StaState *sta, + int digits) { const Unit *unit = sta->units()->timeUnit(); if (sta->variables()->pocvEnabled()) { float sigma = delay.sigma(); return stringPrintTmp("%s[%s]", - unit->asString(delay.mean(), digits), - unit->asString(sigma, digits)); + unit->asString(delay.mean(), digits), + unit->asString(sigma, digits)); } else return unit->asString(delay.mean(), digits); @@ -281,9 +281,9 @@ delayAsString(const Delay &delay, const char * delayAsString(const Delay &delay, - const EarlyLate *early_late, - const StaState *sta, - int digits) + const EarlyLate *early_late, + const StaState *sta, + int digits) { float mean_sigma = delayAsFloat(delay, early_late, sta); return sta->units()->timeUnit()->asString(mean_sigma, digits); @@ -291,7 +291,7 @@ delayAsString(const Delay &delay, bool delayIsInitValue(const Delay &delay, - const MinMax *min_max) + const MinMax *min_max) { return fuzzyEqual(delay.mean(), min_max->initValue()) && delay.sigma2() == 0.0; @@ -312,7 +312,7 @@ delayInf(const Delay &delay) bool delayEqual(const Delay &delay1, - const Delay &delay2) + const Delay &delay2) { return fuzzyEqual(delay1.mean(), delay2.mean()) && fuzzyEqual(delay1.sigma2(), delay2.sigma2()); @@ -320,27 +320,27 @@ delayEqual(const Delay &delay1, bool delayLess(const Delay &delay1, - const Delay &delay2, - const StaState *sta) + const Delay &delay2, + const StaState *sta) { return fuzzyLess(delayAsFloat(delay1, EarlyLate::early(), sta), - delayAsFloat(delay2, EarlyLate::early(), sta)); + delayAsFloat(delay2, EarlyLate::early(), sta)); } bool delayLess(const Delay &delay1, - float delay2, - const StaState *sta) + float delay2, + const StaState *sta) { return fuzzyLess(delayAsFloat(delay1, EarlyLate::early(), sta), - delay2); + delay2); } bool delayLess(const Delay &delay1, - const Delay &delay2, - const MinMax *min_max, - const StaState *sta) + const Delay &delay2, + const MinMax *min_max, + const StaState *sta) { if (min_max == MinMax::max()) return delayLess(delay1, delay2, sta); @@ -350,27 +350,27 @@ delayLess(const Delay &delay1, bool delayLessEqual(const Delay &delay1, - const Delay &delay2, - const StaState *sta) + const Delay &delay2, + const StaState *sta) { return fuzzyLessEqual(delayAsFloat(delay1, EarlyLate::early(), sta), - delayAsFloat(delay2, EarlyLate::early(), sta)); + delayAsFloat(delay2, EarlyLate::early(), sta)); } bool delayLessEqual(const Delay &delay1, - float delay2, - const StaState *sta) + float delay2, + const StaState *sta) { return fuzzyLessEqual(delayAsFloat(delay1, EarlyLate::early(), sta), - delay2); + delay2); } bool delayLessEqual(const Delay &delay1, - const Delay &delay2, - const MinMax *min_max, - const StaState *sta) + const Delay &delay2, + const MinMax *min_max, + const StaState *sta) { if (min_max == MinMax::max()) return delayLessEqual(delay1, delay2, sta); @@ -380,46 +380,46 @@ delayLessEqual(const Delay &delay1, bool delayGreater(const Delay &delay1, - const Delay &delay2, - const StaState *sta) + const Delay &delay2, + const StaState *sta) { return fuzzyGreater(delayAsFloat(delay1, EarlyLate::late(), sta), - delayAsFloat(delay2, EarlyLate::late(), sta)); + delayAsFloat(delay2, EarlyLate::late(), sta)); } bool delayGreater(const Delay &delay1, - float delay2, - const StaState *sta) + float delay2, + const StaState *sta) { return fuzzyGreater(delayAsFloat(delay1, EarlyLate::late(), sta), - delay2); + delay2); } bool delayGreaterEqual(const Delay &delay1, - const Delay &delay2, - const StaState *sta) + const Delay &delay2, + const StaState *sta) { return fuzzyGreaterEqual(delayAsFloat(delay1, EarlyLate::late(), sta), - delayAsFloat(delay2, EarlyLate::late(), sta)); + delayAsFloat(delay2, EarlyLate::late(), sta)); } bool delayGreaterEqual(const Delay &delay1, - float delay2, - const StaState *sta) + float delay2, + const StaState *sta) { return fuzzyGreaterEqual(delayAsFloat(delay1, EarlyLate::late(), sta), - delay2); + delay2); } bool delayGreater(const Delay &delay1, - const Delay &delay2, - const MinMax *min_max, - const StaState *sta) + const Delay &delay2, + const MinMax *min_max, + const StaState *sta) { if (min_max == MinMax::max()) return delayGreater(delay1, delay2, sta); @@ -429,9 +429,9 @@ delayGreater(const Delay &delay1, bool delayGreaterEqual(const Delay &delay1, - const Delay &delay2, - const MinMax *min_max, - const StaState *sta) + const Delay &delay2, + const MinMax *min_max, + const StaState *sta) { if (min_max == MinMax::max()) return delayGreaterEqual(delay1, delay2, sta); @@ -441,41 +441,41 @@ delayGreaterEqual(const Delay &delay1, Delay delayRemove(const Delay &delay1, - const Delay &delay2) + const Delay &delay2) { return Delay(delay1.mean() - delay2.mean(), - delay1.sigma2() - delay2.sigma2()); + delay1.sigma2() - delay2.sigma2()); } float delayRatio(const Delay &delay1, - const Delay &delay2) + const Delay &delay2) { return delay1.mean() / delay2.mean(); } Delay operator+(float delay1, - const Delay &delay2) + const Delay &delay2) { return Delay(delay1 + delay2.mean(), - delay2.sigma2()); + delay2.sigma2()); } Delay operator/(float delay1, - const Delay &delay2) + const Delay &delay2) { return Delay(delay1 / delay2.mean(), - delay2.sigma2()); + delay2.sigma2()); } Delay operator*(const Delay &delay1, - float delay2) + float delay2) { return Delay(delay1.mean() * delay2, - delay1.sigma2() * delay2 * delay2); + delay1.sigma2() * delay2 * delay2); } } // namespace diff --git a/graph/DelayNormal2.cc b/graph/DelayNormal2.cc index 9d445559..b6d74df6 100644 --- a/graph/DelayNormal2.cc +++ b/graph/DelayNormal2.cc @@ -86,8 +86,8 @@ Delay::Delay(float mean) : } Delay::Delay(float mean, - float sigma2_early, - float sigma2_late) : + float sigma2_early, + float sigma2_late) : mean_(mean), sigma2_{sigma2_early, sigma2_late} { @@ -157,8 +157,8 @@ Delay Delay::operator+(const Delay &delay) const { return Delay(mean_ + delay.mean_, - sigma2_[early_index] + delay.sigma2_[early_index], - sigma2_[late_index] + delay.sigma2_[late_index]); + sigma2_[early_index] + delay.sigma2_[early_index], + sigma2_[late_index] + delay.sigma2_[late_index]); } Delay @@ -171,8 +171,8 @@ Delay Delay::operator-(const Delay &delay) const { return Delay(mean_ - delay.mean_, - sigma2_[early_index] + delay.sigma2_[late_index], - sigma2_[late_index] + delay.sigma2_[early_index]); + sigma2_[early_index] + delay.sigma2_[late_index], + sigma2_[late_index] + delay.sigma2_[early_index]); } Delay @@ -245,23 +245,23 @@ DelayDbl::operator-=(const Delay &delay) Delay makeDelay(float delay, - float sigma_early, - float sigma_late) + float sigma_early, + float sigma_late) { return Delay(delay, square(sigma_early), square(sigma_late)); } Delay makeDelay2(float delay, - float sigma2_early, - float sigma2_late) + float sigma2_early, + float sigma2_late) { return Delay(delay, sigma2_early, sigma2_late); } bool delayIsInitValue(const Delay &delay, - const MinMax *min_max) + const MinMax *min_max) { return fuzzyEqual(delay.mean(), min_max->initValue()) && fuzzyZero(delay.sigma2Early()) @@ -284,7 +284,7 @@ delayInf(const Delay &delay) bool delayEqual(const Delay &delay1, - const Delay &delay2) + const Delay &delay2) { return fuzzyEqual(delay1.mean(), delay2.mean()) && fuzzyEqual(delay1.sigma2Early(), delay2.sigma2Early()) @@ -293,27 +293,27 @@ delayEqual(const Delay &delay1, bool delayLess(const Delay &delay1, - const Delay &delay2, - const StaState *sta) + const Delay &delay2, + const StaState *sta) { return fuzzyLess(delayAsFloat(delay1, EarlyLate::early(), sta), - delayAsFloat(delay2, EarlyLate::early(), sta)); + delayAsFloat(delay2, EarlyLate::early(), sta)); } bool delayLess(const Delay &delay1, - float delay2, - const StaState *sta) + float delay2, + const StaState *sta) { return fuzzyLess(delayAsFloat(delay1, EarlyLate::early(), sta), - delay2); + delay2); } bool delayLess(const Delay &delay1, - const Delay &delay2, - const MinMax *min_max, - const StaState *sta) + const Delay &delay2, + const MinMax *min_max, + const StaState *sta) { if (min_max == MinMax::max()) return delayLess(delay1, delay2, sta); @@ -323,27 +323,27 @@ delayLess(const Delay &delay1, bool delayLessEqual(const Delay &delay1, - const Delay &delay2, - const StaState *sta) + const Delay &delay2, + const StaState *sta) { return fuzzyLessEqual(delayAsFloat(delay1, EarlyLate::early(), sta), - delayAsFloat(delay2, EarlyLate::early(), sta)); + delayAsFloat(delay2, EarlyLate::early(), sta)); } bool delayLessEqual(const Delay &delay1, - float delay2, - const StaState *sta) + float delay2, + const StaState *sta) { return fuzzyLessEqual(delayAsFloat(delay1, EarlyLate::early(), sta), - delay2); + delay2); } bool delayLessEqual(const Delay &delay1, - const Delay &delay2, - const MinMax *min_max, - const StaState *sta) + const Delay &delay2, + const MinMax *min_max, + const StaState *sta) { if (min_max == MinMax::max()) return delayLessEqual(delay1, delay2, sta); @@ -353,45 +353,45 @@ delayLessEqual(const Delay &delay1, bool delayGreater(const Delay &delay1, - const Delay &delay2, - const StaState *sta) + const Delay &delay2, + const StaState *sta) { return fuzzyGreater(delayAsFloat(delay1, EarlyLate::late(), sta), - delayAsFloat(delay2, EarlyLate::late(), sta)); + delayAsFloat(delay2, EarlyLate::late(), sta)); } bool delayGreater(const Delay &delay1, - float delay2, - const StaState *sta) + float delay2, + const StaState *sta) { return fuzzyGreaterEqual(delayAsFloat(delay1, EarlyLate::late(), sta), - delayAsFloat(delay2, EarlyLate::late(), sta)); + delayAsFloat(delay2, EarlyLate::late(), sta)); } bool delayGreaterEqual(const Delay &delay1, - const Delay &delay2, - const StaState *sta) + const Delay &delay2, + const StaState *sta) { return fuzzyGreaterEqual(delayAsFloat(delay1, EarlyLate::late(), sta), - delayAsFloat(delay2, EarlyLate::late(), sta)); + delayAsFloat(delay2, EarlyLate::late(), sta)); } bool delayGreaterEqual(const Delay &delay1, - float delay2, - const StaState *sta) + float delay2, + const StaState *sta) { return fuzzyGreaterEqual(delayAsFloat(delay1, EarlyLate::late(), sta), - delay2); + delay2); } bool delayGreater(const Delay &delay1, - const Delay &delay2, - const MinMax *min_max, - const StaState *sta) + const Delay &delay2, + const MinMax *min_max, + const StaState *sta) { if (min_max == MinMax::max()) return delayGreater(delay1, delay2, sta); @@ -401,9 +401,9 @@ delayGreater(const Delay &delay1, bool delayGreaterEqual(const Delay &delay1, - const Delay &delay2, - const MinMax *min_max, - const StaState *sta) + const Delay &delay2, + const MinMax *min_max, + const StaState *sta) { if (min_max == MinMax::max()) return delayGreaterEqual(delay1, delay2, sta); @@ -413,8 +413,8 @@ delayGreaterEqual(const Delay &delay1, float delayAsFloat(const Delay &delay, - const EarlyLate *early_late, - const StaState *sta) + const EarlyLate *early_late, + const StaState *sta) { if (sta->pocvEnabled()) { if (early_late == EarlyLate::early()) @@ -429,31 +429,31 @@ delayAsFloat(const Delay &delay, float delaySigma2(const Delay &delay, - const EarlyLate *early_late) + const EarlyLate *early_late) { return delay.sigma2(early_late); } const char * delayAsString(const Delay &delay, - const StaState *sta) + const StaState *sta) { return delayAsString(delay, sta, sta->units()->timeUnit()->digits()); } const char * delayAsString(const Delay &delay, - const StaState *sta, - int digits) + const StaState *sta, + int digits) { const Unit *unit = sta->units()->timeUnit(); if (sta->pocvEnabled()) { float sigma_early = delay.sigma(EarlyLate::early()); float sigma_late = delay.sigma(EarlyLate::late()); return stringPrintTmp("%s[%s:%s]", - unit->asString(delay.mean(), digits), - unit->asString(sigma_early, digits), - unit->asString(sigma_late, digits)); + unit->asString(delay.mean(), digits), + unit->asString(sigma_early, digits), + unit->asString(sigma_late, digits)); } else return unit->asString(delay.mean(), digits); @@ -461,9 +461,9 @@ delayAsString(const Delay &delay, const char * delayAsString(const Delay &delay, - const EarlyLate *early_late, - const StaState *sta, - int digits) + const EarlyLate *early_late, + const StaState *sta, + int digits) { float mean_sigma = delayAsFloat(delay, early_late, sta); return sta->units()->timeUnit()->asString(mean_sigma, digits); @@ -471,45 +471,45 @@ delayAsString(const Delay &delay, Delay delayRemove(const Delay &delay1, - const Delay &delay2) + const Delay &delay2) { return Delay(delay1.mean() - delay2.mean(), - delay1.sigma2Early() - delay2.sigma2Early(), - delay1.sigma2Late() - delay2.sigma2Late()); + delay1.sigma2Early() - delay2.sigma2Early(), + delay1.sigma2Late() - delay2.sigma2Late()); } float delayRatio(const Delay &delay1, - const Delay &delay2) + const Delay &delay2) { return delay1.mean() / delay2.mean(); } Delay operator+(float delay1, - const Delay &delay2) + const Delay &delay2) { return Delay(delay1 + delay2.mean(), - delay2.sigma2Early(), - delay2.sigma2Late()); + delay2.sigma2Early(), + delay2.sigma2Late()); } Delay operator/(float delay1, - const Delay &delay2) + const Delay &delay2) { return Delay(delay1 / delay2.mean(), - delay2.sigma2Early(), - delay2.sigma2Late()); + delay2.sigma2Early(), + delay2.sigma2Late()); } Delay operator*(const Delay &delay1, - float delay2) + float delay2) { return Delay(delay1.mean() * delay2, - delay1.sigma2Early() * delay2 * delay2, - delay1.sigma2Late() * delay2 * delay2); + delay1.sigma2Early() * delay2 * delay2, + delay1.sigma2Late() * delay2 * delay2); } } // namespace diff --git a/graph/Graph.cc b/graph/Graph.cc index 713fa2e5..2fe4d934 100644 --- a/graph/Graph.cc +++ b/graph/Graph.cc @@ -24,6 +24,7 @@ #include "Graph.hh" +#include "ContainerHelpers.hh" #include "Debug.hh" #include "Stats.hh" #include "MinMax.hh" @@ -34,7 +35,6 @@ #include "Liberty.hh" #include "PortDirection.hh" #include "Network.hh" -#include "DcalcAnalysisPt.hh" #include "FuncExpr.hh" namespace sta { @@ -48,15 +48,15 @@ using std::string; //////////////////////////////////////////////////////////////// Graph::Graph(StaState *sta, - int slew_rf_count, - DcalcAPIndex ap_count) : + int slew_rf_count, + DcalcAPIndex ap_count) : StaState(sta), vertices_(nullptr), edges_(nullptr), slew_rf_count_(slew_rf_count), ap_count_(ap_count), period_check_annotations_(nullptr), - reg_clk_vertices_(new VertexSet(graph_)) + reg_clk_vertices_(makeVertexSet(this)) { // For the benifit of reg_clk_vertices_ that references graph_. graph_ = this; @@ -68,7 +68,6 @@ Graph::~Graph() delete edges_; vertices_->clear(); delete vertices_; - delete reg_clk_vertices_; removePeriodCheckAnnotations(); } @@ -105,11 +104,11 @@ class FindNetDrvrLoadCounts : public PinVisitor { public: FindNetDrvrLoadCounts(Pin *drvr_pin, - PinSet &visited_drvrs, - int &drvr_count, - int &bidirect_count, - int &load_count, - const Network *network); + PinSet &visited_drvrs, + int &drvr_count, + int &bidirect_count, + int &load_count, + const Network *network); virtual void operator()(const Pin *pin); protected: @@ -122,11 +121,11 @@ protected: }; FindNetDrvrLoadCounts::FindNetDrvrLoadCounts(Pin *drvr_pin, - PinSet &visited_drvrs, - int &drvr_count, - int &bidirect_count, - int &load_count, - const Network *network) : + PinSet &visited_drvrs, + int &drvr_count, + int &bidirect_count, + int &load_count, + const Network *network) : drvr_pin_(drvr_pin), visited_drvrs_(visited_drvrs), drvr_count_(drvr_count), @@ -186,48 +185,48 @@ Graph::makePinInstanceEdges(const Pin *pin) void Graph::makePortInstanceEdges(const Instance *inst, - LibertyCell *cell, - LibertyPort *from_to_port) + LibertyCell *cell, + LibertyPort *from_to_port) { for (TimingArcSet *arc_set : cell->timingArcSets()) { LibertyPort *from_port = arc_set->from(); LibertyPort *to_port = arc_set->to(); if ((from_to_port == nullptr - || from_port == from_to_port - || to_port == from_to_port) - && from_port) { + || from_port == from_to_port + || to_port == from_to_port) + && from_port) { Pin *from_pin = network_->findPin(inst, from_port); Pin *to_pin = network_->findPin(inst, to_port); if (from_pin && to_pin) { - Vertex *from_vertex, *from_bidirect_drvr_vertex; - Vertex *to_vertex, *to_bidirect_drvr_vertex; - pinVertices(from_pin, from_vertex, from_bidirect_drvr_vertex); - pinVertices(to_pin, to_vertex, to_bidirect_drvr_vertex); - // From pin and/or to pin can be bidirect. - // For combinational arcs edge is to driver. - // For timing checks edge is to load. - // Vertices can be missing from the graph if the pins - // are power or ground. - if (from_vertex) { + Vertex *from_vertex, *from_bidirect_drvr_vertex; + Vertex *to_vertex, *to_bidirect_drvr_vertex; + pinVertices(from_pin, from_vertex, from_bidirect_drvr_vertex); + pinVertices(to_pin, to_vertex, to_bidirect_drvr_vertex); + // From pin and/or to pin can be bidirect. + // For combinational arcs edge is to driver. + // For timing checks edge is to load. + // Vertices can be missing from the graph if the pins + // are power or ground. + if (from_vertex) { const TimingRole *role = arc_set->role(); - bool is_check = role->isTimingCheckBetween(); - if (to_bidirect_drvr_vertex && !is_check) - makeEdge(from_vertex, to_bidirect_drvr_vertex, arc_set); - else if (to_vertex) { - makeEdge(from_vertex, to_vertex, arc_set); - if (is_check) { - to_vertex->setHasChecks(true); - from_vertex->setIsCheckClk(true); - } - } - if (from_bidirect_drvr_vertex && to_vertex) { - // Internal path from bidirect output back into the - // instance. - Edge *edge = makeEdge(from_bidirect_drvr_vertex, to_vertex, - arc_set); - edge->setIsBidirectInstPath(true); - } - } + bool is_check = role->isTimingCheckBetween(); + if (to_bidirect_drvr_vertex && !is_check) + makeEdge(from_vertex, to_bidirect_drvr_vertex, arc_set); + else if (to_vertex) { + makeEdge(from_vertex, to_vertex, arc_set); + if (is_check) { + to_vertex->setHasChecks(true); + from_vertex->setIsCheckClk(true); + } + } + if (from_bidirect_drvr_vertex && to_vertex) { + // Internal path from bidirect output back into the + // instance. + Edge *edge = makeEdge(from_bidirect_drvr_vertex, to_vertex, + arc_set); + edge->setIsBidirectInstPath(true); + } + } } } } @@ -248,13 +247,13 @@ Graph::makeWireEdges() void Graph::makeInstDrvrWireEdges(const Instance *inst, - PinSet &visited_drvrs) + PinSet &visited_drvrs) { InstancePinIterator *pin_iter = network_->pinIterator(inst); while (pin_iter->hasNext()) { Pin *pin = pin_iter->next(); if (network_->isDriver(pin) - && !visited_drvrs.hasKey(pin)) + && !visited_drvrs.contains(pin)) makeWireEdgesFromPin(pin, visited_drvrs); } delete pin_iter; @@ -276,7 +275,7 @@ Graph::makeWireEdgesFromPin(const Pin *drvr_pin) void Graph::makeWireEdgesFromPin(const Pin *drvr_pin, - PinSet &visited_drvrs) + PinSet &visited_drvrs) { // Find all drivers and loads on the net to avoid N*M run time // for large fanin/fanout nets. @@ -296,7 +295,7 @@ Graph::makeWireEdgesFromPin(const Pin *drvr_pin, for (auto drvr_pin : drvrs) { for (auto load_pin : loads) { if (drvr_pin != load_pin) - makeWireEdge(drvr_pin, load_pin); + makeWireEdge(drvr_pin, load_pin); } } } @@ -337,7 +336,7 @@ Graph::makeWireEdgesToPin(const Pin *to_pin) if (drvrs) { for (auto drvr : *drvrs) { if (drvr != to_pin) - makeWireEdge(drvr, to_pin); + makeWireEdge(drvr, to_pin); } } } @@ -349,7 +348,7 @@ public: private: virtual void visit(const Pin *drvr, - const Pin *load); + const Pin *load); Graph *graph_; }; @@ -362,7 +361,7 @@ MakeEdgesThruHierPin::MakeEdgesThruHierPin(Graph *graph) : void MakeEdgesThruHierPin::visit(const Pin *drvr, - const Pin *load) + const Pin *load) { graph_->makeWireEdge(drvr, load); } @@ -376,7 +375,7 @@ Graph::makeWireEdgesThruPin(const Pin *hpin) void Graph::makeWireEdge(const Pin *from_pin, - const Pin *to_pin) + const Pin *to_pin) { TimingArcSet *arc_set = TimingArcSet::wireTimingArcSet(); Vertex *from_vertex, *from_bidirect_drvr_vertex; @@ -391,6 +390,13 @@ Graph::makeWireEdge(const Pin *from_pin, } } +void +Graph::makeSceneAfter() +{ + ap_count_ = dcalcAnalysisPtCount(); + initSlews(); +} + //////////////////////////////////////////////////////////////// Vertex * @@ -414,8 +420,8 @@ Graph::makePinVertices(Pin *pin) void Graph::makePinVertices(Pin *pin, - Vertex *&vertex, - Vertex *&bidir_drvr_vertex) + Vertex *&vertex, + Vertex *&bidir_drvr_vertex) { PortDirection *dir = network_->direction(pin); if (!dir->isPowerGround()) { @@ -433,26 +439,26 @@ Graph::makePinVertices(Pin *pin, Vertex * Graph::makeVertex(Pin *pin, - bool is_bidirect_drvr, - bool is_reg_clk) + bool is_bidirect_drvr, + bool is_reg_clk) { Vertex *vertex = vertices_->make(); vertex->init(pin, is_bidirect_drvr, is_reg_clk); initSlews(vertex); if (is_reg_clk) - reg_clk_vertices_->insert(vertex); + reg_clk_vertices_.insert(vertex); return vertex; } void Graph::pinVertices(const Pin *pin, - // Return values. - Vertex *&vertex, - Vertex *&bidirect_drvr_vertex) const + // Return values. + Vertex *&vertex, + Vertex *&bidirect_drvr_vertex) const { vertex = Graph::vertex(network_->vertexId(pin)); if (network_->direction(pin)->isBidirect()) - bidirect_drvr_vertex = pin_bidirect_drvr_vertex_map_.findKey(pin); + bidirect_drvr_vertex = findKey(pin_bidirect_drvr_vertex_map_, pin); else bidirect_drvr_vertex = nullptr; } @@ -461,7 +467,7 @@ Vertex * Graph::pinDrvrVertex(const Pin *pin) const { if (network_->direction(pin)->isBidirect()) - return pin_bidirect_drvr_vertex_map_.findKey(pin); + return findKey(pin_bidirect_drvr_vertex_map_, pin); else return Graph::vertex(network_->vertexId(pin)); } @@ -476,11 +482,11 @@ void Graph::deleteVertex(Vertex *vertex) { if (vertex->isRegClk()) - reg_clk_vertices_->erase(vertex); + reg_clk_vertices_.erase(vertex); Pin *pin = vertex->pin_; if (vertex->isBidirectDriver()) pin_bidirect_drvr_vertex_map_.erase(pin_bidirect_drvr_vertex_map_ - .find(pin)); + .find(pin)); else network_->setVertexId(pin, vertex_id_null); // Delete edges to vertex. @@ -513,7 +519,7 @@ Graph::hasFaninOne(Vertex *vertex) const void Graph::deleteInEdge(Vertex *vertex, - Edge *edge) + Edge *edge) { EdgeId edge_id = id(edge); EdgeId prev = 0; @@ -529,7 +535,7 @@ Graph::deleteInEdge(Vertex *vertex, void Graph::deleteOutEdge(Vertex *vertex, - Edge *edge) + Edge *edge) { EdgeId next = edge->vertex_out_next_; EdgeId prev = edge->vertex_out_prev_; @@ -574,30 +580,6 @@ Graph::gateEdgeArc(const Pin *in_pin, //////////////////////////////////////////////////////////////// -Path * -Graph::makePaths(Vertex *vertex, - uint32_t count) -{ - Path *paths = new Path[count]; - vertex->setPaths(paths); - return paths; -} - -Path * -Graph::paths(const Vertex *vertex) const -{ - return vertex->paths(); -} - -void -Graph::deletePaths(Vertex *vertex) -{ - vertex->setPaths(nullptr); - vertex->tag_group_index_ = tag_group_index_max; -} - -//////////////////////////////////////////////////////////////// - const Slew & Graph::slew(const Vertex *vertex, const RiseFall *rf, @@ -652,8 +634,8 @@ Graph::id(const Edge *edge) const Edge * Graph::makeEdge(Vertex *from, - Vertex *to, - TimingArcSet *arc_set) + Vertex *to, + TimingArcSet *arc_set) { Edge *edge = edges_->make(); edge->init(id(from), id(to), arc_set); @@ -687,8 +669,8 @@ Graph::deleteEdge(Edge *edge) ArcDelay Graph::arcDelay(const Edge *edge, - const TimingArc *arc, - DcalcAPIndex ap_index) const + const TimingArc *arc, + DcalcAPIndex ap_index) const { ArcDelay *delays = edge->arcDelays(); size_t index = arc->index() * ap_count_ + ap_index; @@ -697,9 +679,9 @@ Graph::arcDelay(const Edge *edge, void Graph::setArcDelay(Edge *edge, - const TimingArc *arc, - DcalcAPIndex ap_index, - ArcDelay delay) + const TimingArc *arc, + DcalcAPIndex ap_index, + ArcDelay delay) { ArcDelay *arc_delays = edge->arcDelays(); size_t index = arc->index() * ap_count_ + ap_index; @@ -708,8 +690,8 @@ Graph::setArcDelay(Edge *edge, const ArcDelay & Graph::wireArcDelay(const Edge *edge, - const RiseFall *rf, - DcalcAPIndex ap_index) + const RiseFall *rf, + DcalcAPIndex ap_index) { ArcDelay *delays = edge->arcDelays(); size_t index = rf->index() * ap_count_ + ap_index; @@ -718,9 +700,9 @@ Graph::wireArcDelay(const Edge *edge, void Graph::setWireArcDelay(Edge *edge, - const RiseFall *rf, - DcalcAPIndex ap_index, - const ArcDelay &delay) + const RiseFall *rf, + DcalcAPIndex ap_index, + const ArcDelay &delay) { ArcDelay *delays = edge->arcDelays(); size_t index = rf->index() * ap_count_ + ap_index; @@ -731,25 +713,25 @@ Graph::setWireArcDelay(Edge *edge, bool Graph::arcDelayAnnotated(const Edge *edge, - const TimingArc *arc, - DcalcAPIndex ap_index) const + const TimingArc *arc, + DcalcAPIndex ap_index) const { return edge->arcDelayAnnotated(arc, ap_index, ap_count_); } void Graph::setArcDelayAnnotated(Edge *edge, - const TimingArc *arc, - DcalcAPIndex ap_index, - bool annotated) + const TimingArc *arc, + DcalcAPIndex ap_index, + bool annotated) { return edge->setArcDelayAnnotated(arc, ap_index, ap_count_, annotated); } bool Graph::wireDelayAnnotated(const Edge *edge, - const RiseFall *rf, - DcalcAPIndex ap_index) const + const RiseFall *rf, + DcalcAPIndex ap_index) const { int arc_index = TimingArcSet::wireArcIndex(rf); TimingArc *arc = TimingArcSet::wireTimingArcSet()->findTimingArc(arc_index); @@ -758,9 +740,9 @@ Graph::wireDelayAnnotated(const Edge *edge, void Graph::setWireDelayAnnotated(Edge *edge, - const RiseFall *rf, - DcalcAPIndex ap_index, - bool annotated) + const RiseFall *rf, + DcalcAPIndex ap_index, + bool annotated) { int arc_index = TimingArcSet::wireArcIndex(rf); TimingArc *arc = TimingArcSet::wireTimingArcSet()->findTimingArc(arc_index); @@ -831,19 +813,6 @@ Graph::initArcDelays(Edge *edge) arc_delays[i] = 0.0; } -bool -Graph::delayAnnotated(Edge *edge) -{ - TimingArcSet *arc_set = edge->timingArcSet(); - for (TimingArc *arc : arc_set->arcs()) { - for (DcalcAPIndex ap_index = 0; ap_index < ap_count_; ap_index++) { - if (!arcDelayAnnotated(edge, arc, ap_index)) - return false; - } - } - return true; -} - //////////////////////////////////////////////////////////////// void @@ -873,10 +842,10 @@ Graph::minPulseWidthArc(Vertex *vertex, void Graph::minPeriodArc(Vertex *vertex, - const RiseFall *rf, - // Return values. - Edge *&edge, - TimingArc *&arc) + const RiseFall *rf, + // Return values. + Edge *&edge, + TimingArc *&arc) { VertexOutEdgeIterator edge_iter(vertex, this); while (edge_iter.hasNext()) { @@ -899,30 +868,30 @@ Graph::minPeriodArc(Vertex *vertex, void Graph::periodCheckAnnotation(const Pin *pin, - DcalcAPIndex ap_index, - // Return values. - float &period, - bool &exists) + DcalcAPIndex ap_index, + // Return values. + float &period, + bool &exists) { exists = false; if (period_check_annotations_) { - float *periods = period_check_annotations_->findKey(pin); + float *periods = findKey(period_check_annotations_, pin); if (periods) { period = periods[ap_index]; if (period >= 0.0) - exists = true; + exists = true; } } } void Graph::setPeriodCheckAnnotation(const Pin *pin, - DcalcAPIndex ap_index, - float period) + DcalcAPIndex ap_index, + float period) { if (period_check_annotations_ == nullptr) period_check_annotations_ = new PeriodCheckAnnotations(network_); - float *periods = period_check_annotations_->findKey(pin); + float *periods = findKey(period_check_annotations_, pin); if (periods == nullptr) { periods = new float[ap_count_]; // Use negative (illegal) period values to indicate unannotated checks. @@ -974,8 +943,8 @@ Vertex::Vertex() void Vertex::init(Pin *pin, - bool is_bidirect_drvr, - bool is_reg_clk) + bool is_bidirect_drvr, + bool is_reg_clk) { pin_ = pin; is_reg_clk_ = is_reg_clk; @@ -986,16 +955,13 @@ Vertex::init(Pin *pin, paths_ = nullptr; tag_group_index_ = tag_group_index_max; slew_annotated_ = false; - sim_value_ = unsigned(LogicValue::unknown); - is_disabled_constraint_ = false; - is_gated_clk_enable_ = false; has_checks_ = false; is_check_clk_ = false; - is_constrained_ = false; has_downstream_clk_pin_ = false; level_ = 0; visited1_ = false; visited2_ = false; + has_sim_value_ = false; bfs_in_queue_ = 0; } @@ -1046,15 +1012,15 @@ Vertex::isDriver(const Network *network) const PortDirection *dir = network->direction(pin_); bool top_level_port = network->isTopLevelPort(pin_); return ((top_level_port - && (dir->isInput() - || (dir->isBidirect() - && is_bidirect_drvr_))) - || (!top_level_port - && (dir->isOutput() - || dir->isTristate() - || (dir->isBidirect() - && is_bidirect_drvr_) - || dir->isInternal()))); + && (dir->isInput() + || (dir->isBidirect() + && is_bidirect_drvr_))) + || (!top_level_port + && (dir->isOutput() + || dir->isTristate() + || (dir->isBidirect() + && is_bidirect_drvr_) + || dir->isInternal()))); } void @@ -1082,11 +1048,17 @@ Vertex::setSlews(Slew *slews) slews_ = slews; } +void +Vertex::setHasSimValue(bool has_sim) +{ + has_sim_value_ = has_sim; +} + bool Vertex::slewAnnotated(const RiseFall *rf, - const MinMax *min_max) const + const MinMax *min_max) const { - int index = min_max->index() * transitionCount() + rf->index(); + int index = min_max->index() * RiseFall::index_count+ rf->index(); return ((1 << index) & slew_annotated_) != 0; } @@ -1098,14 +1070,14 @@ Vertex::slewAnnotated() const void Vertex::setSlewAnnotated(bool annotated, - const RiseFall *rf, - DcalcAPIndex ap_index) + const RiseFall *rf, + DcalcAPIndex ap_index) { // Track rise/fall/min/max annotations separately, but after that // only rise/fall. if (ap_index > 1) ap_index = 0; - int index = ap_index * transitionCount() + rf->index(); + int index = ap_index * RiseFall::index_count + rf->index(); if (annotated) slew_annotated_ |= (1 << index); else @@ -1130,6 +1102,15 @@ Vertex::setTagGroupIndex(TagGroupIndex tag_index) tag_group_index_ = tag_index; } +Path * +Vertex::makePaths(uint32_t count) +{ + delete [] paths_; + Path *paths = new Path[count]; + paths_ = paths; + return paths; +} + void Vertex::setPaths(Path *paths) { @@ -1137,30 +1118,12 @@ Vertex::setPaths(Path *paths) paths_ = paths; } -LogicValue -Vertex::simValue() const -{ - return static_cast(sim_value_); -} - void -Vertex::setSimValue(LogicValue value) +Vertex::deletePaths() { - sim_value_ = unsigned(value); -} - -bool -Vertex::isConstant() const -{ - LogicValue value = static_cast(sim_value_); - return value == LogicValue::zero - || value == LogicValue::one; -} - -void -Vertex::setIsDisabledConstraint(bool disabled) -{ - is_disabled_constraint_ = disabled; + delete [] paths_; + paths_ = nullptr; + tag_group_index_ = tag_group_index_max; } bool @@ -1187,18 +1150,6 @@ Vertex::setIsCheckClk(bool is_check_clk) is_check_clk_ = is_check_clk; } -void -Vertex::setIsGatedClkEnable(bool enable) -{ - is_gated_clk_enable_ = enable; -} - -void -Vertex::setIsConstrained(bool constrained) -{ - is_constrained_ = constrained; -} - void Vertex::setHasDownstreamClkPin(bool has_clk_pin) { @@ -1213,7 +1164,7 @@ Vertex::bfsInQueue(BfsIndex index) const void Vertex::setBfsInQueue(BfsIndex index, - bool value) + bool value) { if (value) bfs_in_queue_ |= 1 << int(index); @@ -1235,8 +1186,8 @@ Edge::Edge() void Edge::init(VertexId from, - VertexId to, - TimingArcSet *arc_set) + VertexId to, + TimingArcSet *arc_set) { from_ = from; to_ = to; @@ -1251,10 +1202,9 @@ Edge::init(VertexId from, arc_delay_annotated_is_bits_ = true; arc_delay_annotated_.bits_ = 0; delay_annotation_is_incremental_ = false; - sim_timing_sense_ = unsigned(TimingSense::unknown); - is_disabled_constraint_ = false; - is_disabled_cond_ = false; is_disabled_loop_ = false; + has_sim_sense_ = false; + has_disabled_cond_ = false; } Edge::~Edge() @@ -1377,55 +1327,13 @@ Edge::isWire() const { return arc_set_->role()->isWire(); } - + TimingSense Edge::sense() const { return arc_set_->sense(); } - -TimingSense -Edge::simTimingSense() const -{ - return static_cast(sim_timing_sense_); -} - -void -Edge::setSimTimingSense(TimingSense sense) -{ - sim_timing_sense_ = unsigned(sense); -} - -bool -Edge::isDisabledConstraint() const -{ - const TimingRole *role = arc_set_->role(); - bool is_wire = role->isWire(); - return is_disabled_constraint_ - || arc_set_->isDisabledConstraint() - // set_disable_timing cell does not disable timing checks. - || (!(role->isTimingCheck() || is_wire) - && arc_set_->libertyCell()->isDisabledConstraint()) - || (!is_wire - && arc_set_->from()->isDisabledConstraint()) - || (!is_wire - && arc_set_->to()->isDisabledConstraint()); -} - - -void -Edge::setIsDisabledConstraint(bool disabled) -{ - is_disabled_constraint_ = disabled; -} - -void -Edge::setIsDisabledCond(bool disabled) -{ - is_disabled_cond_ = disabled; -} - void Edge::setIsDisabledLoop(bool disabled) { @@ -1444,6 +1352,18 @@ Edge::setIsBidirectNetPath(bool is_bidir) is_bidirect_net_path_ = is_bidir; } +void +Edge::setHasSimSense(bool has_sense) +{ + has_sim_sense_ = has_sense; +} + +void +Edge::setHasDisabledCond(bool has_disabled) +{ + has_disabled_cond_ = has_disabled; +} + //////////////////////////////////////////////////////////////// VertexIterator::VertexIterator(Graph *graph) : @@ -1483,7 +1403,7 @@ VertexIterator::findNextPin() Pin *pin = pin_iter_->next(); vertex_ = graph_->vertex(network_->vertexId(pin)); bidir_vertex_ = network_->direction(pin)->isBidirect() - ? graph_->pin_bidirect_drvr_vertex_map_.findKey(pin) + ? findKey(graph_->pin_bidirect_drvr_vertex_map_, pin) : nullptr; if (vertex_ || bidir_vertex_) return true; @@ -1518,14 +1438,14 @@ VertexIterator::findNext() } VertexInEdgeIterator::VertexInEdgeIterator(Vertex *vertex, - const Graph *graph) : + const Graph *graph) : next_(graph->edge(vertex->in_edges_)), graph_(graph) { } VertexInEdgeIterator::VertexInEdgeIterator(VertexId vertex_id, - const Graph *graph) : + const Graph *graph) : next_(graph->edge(graph->vertex(vertex_id)->in_edges_)), graph_(graph) { @@ -1541,7 +1461,7 @@ VertexInEdgeIterator::next() } VertexOutEdgeIterator::VertexOutEdgeIterator(Vertex *vertex, - const Graph *graph) : + const Graph *graph) : next_(graph->edge(vertex->out_edges_)), graph_(graph) { @@ -1562,9 +1482,9 @@ class FindEdgesThruHierPinVisitor : public HierPinThruVisitor { public: FindEdgesThruHierPinVisitor(EdgeSet &edges, - Graph *graph); + Graph *graph); virtual void visit(const Pin *drvr, - const Pin *load); + const Pin *load); protected: EdgeSet &edges_; @@ -1572,7 +1492,7 @@ protected: }; FindEdgesThruHierPinVisitor::FindEdgesThruHierPinVisitor(EdgeSet &edges, - Graph *graph) : + Graph *graph) : HierPinThruVisitor(), edges_(edges), graph_(graph) @@ -1581,7 +1501,7 @@ FindEdgesThruHierPinVisitor::FindEdgesThruHierPinVisitor(EdgeSet &edges, void FindEdgesThruHierPinVisitor::visit(const Pin *drvr, - const Pin *load) + const Pin *load) { Vertex *drvr_vertex = graph_->pinDrvrVertex(drvr); Vertex *load_vertex = graph_->pinLoadVertex(load); @@ -1595,12 +1515,24 @@ FindEdgesThruHierPinVisitor::visit(const Pin *drvr, } EdgesThruHierPinIterator::EdgesThruHierPinIterator(const Pin *hpin, - Network *network, - Graph *graph) + Network *network, + Graph *graph) { FindEdgesThruHierPinVisitor visitor(edges_, graph); visitDrvrLoadsThruHierPin(hpin, network, &visitor); - edge_iter_.init(edges_); + edge_iter_ = edges_.begin(); +} + +bool +EdgesThruHierPinIterator::hasNext() +{ + return edge_iter_ != edges_.end(); +} + +Edge * +EdgesThruHierPinIterator::next() +{ + return *edge_iter_++; } //////////////////////////////////////////////////////////////// @@ -1617,9 +1549,5 @@ VertexIdLess::operator()(const Vertex *vertex1, return graph_->id(vertex1) < graph_->id(vertex2); } -VertexSet::VertexSet(Graph *&graph) : - Set(VertexIdLess(graph)) -{ -} } // namespace diff --git a/graph/Graph.i b/graph/Graph.i index 032c056a..da7be0ee 100644 --- a/graph/Graph.i +++ b/graph/Graph.i @@ -31,8 +31,9 @@ #include "Liberty.hh" #include "Network.hh" #include "Clock.hh" -#include "Corner.hh" +#include "Scene.hh" #include "Search.hh" +#include "Sdc.hh" #include "Sta.hh" using namespace sta; @@ -92,22 +93,22 @@ vertex_iterator() void set_arc_delay(Edge *edge, - TimingArc *arc, - const Corner *corner, - const MinMaxAll *min_max, - float delay) + TimingArc *arc, + const Scene *scene, + const MinMaxAll *min_max, + float delay) { - Sta::sta()->setArcDelay(edge, arc, corner, min_max, delay); + Sta::sta()->setArcDelay(edge, arc, scene, min_max, delay); } void set_annotated_slew(Vertex *vertex, - const Corner *corner, - const MinMaxAll *min_max, - const RiseFallBoth *rf, - float slew) + const Scene *scene, + const MinMaxAll *min_max, + const RiseFallBoth *rf, + float slew) { - Sta::sta()->setAnnotatedSlew(vertex, corner, min_max, rf, slew); + Sta::sta()->setAnnotatedSlew(vertex, scene, min_max, rf, slew); } // Remove all delay and slew annotations. @@ -132,20 +133,20 @@ int level() { return Sta::sta()->vertexLevel(self); } int tag_group_index() { return self->tagGroupIndex(); } Slew -slew(const RiseFall *rf, +slew(const RiseFallBoth *rf, const MinMax *min_max) { Sta *sta = Sta::sta(); - return sta->vertexSlew(self, rf, min_max); + return sta->slew(self, rf, sta->scenes(), min_max); } Slew -slew_corner(const RiseFall *rf, - const Corner *corner, +slew_scenes(const RiseFallBoth *rf, + const SceneSeq scenes, const MinMax *min_max) { Sta *sta = Sta::sta(); - return sta->vertexSlew(self, rf, corner, min_max); + return sta->slew(self, rf, scenes, min_max); } VertexOutEdgeIterator * @@ -160,162 +161,13 @@ in_edge_iterator() return new VertexInEdgeIterator(self, Sta::sta()->graph()); } -FloatSeq -arrivals_clk(const RiseFall *rf, - Clock *clk, - const RiseFall *clk_rf) -{ - Sta *sta = Sta::sta(); - FloatSeq arrivals; - const ClockEdge *clk_edge = nullptr; - if (clk) - clk_edge = clk->edge(clk_rf); - for (auto path_ap : sta->corners()->pathAnalysisPts()) { - arrivals.push_back(delayAsFloat(sta->vertexArrival(self, rf, clk_edge, - path_ap, nullptr))); - } - return arrivals; -} - -float -arrival(const MinMax *min_max) -{ - Sta *sta = Sta::sta(); - return delayAsFloat(sta->vertexArrival(self, min_max)); -} - -StringSeq -arrivals_clk_delays(const RiseFall *rf, - Clock *clk, - const RiseFall *clk_rf, - int digits) -{ - Sta *sta = Sta::sta(); - StringSeq arrivals; - const ClockEdge *clk_edge = nullptr; - if (clk) - clk_edge = clk->edge(clk_rf); - for (auto path_ap : sta->corners()->pathAnalysisPts()) { - arrivals.push_back(delayAsString(sta->vertexArrival(self, rf, clk_edge, - path_ap, nullptr), - sta, digits)); - } - return arrivals; -} - -FloatSeq -requireds_clk(const RiseFall *rf, - Clock *clk, - const RiseFall *clk_rf) -{ - Sta *sta = Sta::sta(); - FloatSeq reqs; - const ClockEdge *clk_edge = nullptr; - if (clk) - clk_edge = clk->edge(clk_rf); - for (auto path_ap : sta->corners()->pathAnalysisPts()) { - reqs.push_back(delayAsFloat(sta->vertexRequired(self, rf, clk_edge, - path_ap))); - } - return reqs; -} - -StringSeq -requireds_clk_delays(const RiseFall *rf, - Clock *clk, - const RiseFall *clk_rf, - int digits) -{ - Sta *sta = Sta::sta(); - StringSeq reqs; - const ClockEdge *clk_edge = nullptr; - if (clk) - clk_edge = clk->edge(clk_rf); - for (auto path_ap : sta->corners()->pathAnalysisPts()) { - reqs.push_back(delayAsString(sta->vertexRequired(self, rf, clk_edge, path_ap), - sta, digits)); - } - return reqs; -} - -Slack -slack(MinMax *min_max) -{ - Sta *sta = Sta::sta(); - return sta->vertexSlack(self, min_max); -} - -FloatSeq -slacks(RiseFall *rf) -{ - Sta *sta = Sta::sta(); - FloatSeq slacks; - for (auto path_ap : sta->corners()->pathAnalysisPts()) { - slacks.push_back(delayAsFloat(sta->vertexSlack(self, rf, path_ap))); - } - return slacks; -} - -// Slack with respect to a clock rise/fall edge. -FloatSeq -slacks_clk(const RiseFall *rf, - Clock *clk, - const RiseFall *clk_rf) -{ - Sta *sta = Sta::sta(); - FloatSeq slacks; - const ClockEdge *clk_edge = nullptr; - if (clk) - clk_edge = clk->edge(clk_rf); - for (auto path_ap : sta->corners()->pathAnalysisPts()) { - slacks.push_back(delayAsFloat(sta->vertexSlack(self, rf, clk_edge, - path_ap))); - } - return slacks; -} - -StringSeq -slacks_clk_delays(const RiseFall *rf, - Clock *clk, - const RiseFall *clk_rf, - int digits) -{ - Sta *sta = Sta::sta(); - StringSeq slacks; - const ClockEdge *clk_edge = nullptr; - if (clk) - clk_edge = clk->edge(clk_rf); - for (auto path_ap : sta->corners()->pathAnalysisPts()) { - slacks.push_back(delayAsString(sta->vertexSlack(self, rf, clk_edge, - path_ap), - sta, digits)); - } - return slacks; -} - VertexPathIterator * path_iterator(const RiseFall *rf, - const MinMax *min_max) + const MinMax *min_max) { - return Sta::sta()->vertexPathIterator(self, rf, min_max); + return new VertexPathIterator(self, rf, min_max, Sta::sta()); } -bool -has_downstream_clk_pin() -{ - return self->hasDownstreamClkPin(); -} - -bool -is_clock() -{ - Sta *sta = Sta::sta(); - Search *search = sta->search(); - return search->isClock(self); -} - -bool is_disabled_constraint() { return self->isDisabledConstraint(); } - } // Vertex methods %extend Edge { @@ -328,62 +180,85 @@ const char *sense() { return to_string(self->sense()); } TimingArcSeq & timing_arcs() { return self->timingArcSet()->arcs(); } bool is_disabled_loop() { return Sta::sta()->isDisabledLoop(self); } -bool is_disabled_constraint() { return Sta::sta()->isDisabledConstraint(self);} -bool is_disabled_constant() { return Sta::sta()->isDisabledConstant(self); } + +bool is_disabled_constraint() +{ + Sta *sta = Sta::sta(); + const Sdc *sdc = sta->cmdSdc(); + return sta->isDisabledConstraint(self, sdc); +} + +bool is_disabled_constant() +{ + Sta *sta = Sta::sta(); + const Mode *mode = sta->cmdMode(); + return sta->isDisabledConstant(self, mode); +} + bool is_disabled_cond_default() { return Sta::sta()->isDisabledCondDefault(self); } + PinSet -disabled_constant_pins() { return Sta::sta()->disabledConstantPins(self); } +disabled_constant_pins() +{ + Sta *sta = Sta::sta(); + const Mode *mode = sta->cmdMode(); + return sta->disabledConstantPins(self, mode); +} + bool is_disabled_bidirect_inst_path() { return Sta::sta()->isDisabledBidirectInstPath(self); } -bool is_disabled_bidirect_net_path() -{ return Sta::sta()->isDisabledBidirectNetPath(self); } bool is_disabled_preset_clear() { return Sta::sta()->isDisabledPresetClr(self); } const char * -sim_timing_sense(){return to_string(Sta::sta()->simTimingSense(self));} +sim_timing_sense(){ + Sta *sta = Sta::sta(); + const Mode *mode = sta->cmdMode(); + return to_string(sta->simTimingSense(self, mode)); +} FloatSeq arc_delays(TimingArc *arc) { Sta *sta = Sta::sta(); FloatSeq delays; - for (auto dcalc_ap : sta->corners()->dcalcAnalysisPts()) - delays.push_back(delayAsFloat(sta->arcDelay(self, arc, dcalc_ap))); + DcalcAPIndex ap_count = sta->dcalcAnalysisPtCount(); + for (DcalcAPIndex ap_index = 0; ap_index < ap_count; ap_index++) + delays.push_back(delayAsFloat(sta->arcDelay(self, arc, ap_index))); return delays; } StringSeq arc_delay_strings(TimingArc *arc, - int digits) + int digits) { Sta *sta = Sta::sta(); StringSeq delays; - for (auto dcalc_ap : sta->corners()->dcalcAnalysisPts()) - delays.push_back(delayAsString(sta->arcDelay(self, arc, dcalc_ap), + DcalcAPIndex ap_count = sta->dcalcAnalysisPtCount(); + for (DcalcAPIndex ap_index = 0; ap_index < ap_count; ap_index++) + delays.push_back(delayAsString(sta->arcDelay(self, arc, ap_index), sta, digits)); return delays; } bool delay_annotated(TimingArc *arc, - const Corner *corner, - const MinMax *min_max) + const Scene *scene, + const MinMax *min_max) { - DcalcAnalysisPt *dcalc_ap = corner->findDcalcAnalysisPt(min_max); - return Sta::sta()->arcDelayAnnotated(self, arc, dcalc_ap); + return Sta::sta()->arcDelayAnnotated(self, arc, scene, min_max); } float arc_delay(TimingArc *arc, - const Corner *corner, - const MinMax *min_max) + const Scene *scene, + const MinMax *min_max) { - DcalcAnalysisPt *dcalc_ap = corner->findDcalcAnalysisPt(min_max); - return delayAsFloat(Sta::sta()->arcDelay(self, arc, dcalc_ap)); + DcalcAPIndex ap_index = scene->dcalcAnalysisPtIndex(min_max); + return delayAsFloat(Sta::sta()->arcDelay(self, arc, ap_index)); } -string +std::string cond() { FuncExpr *cond = self->timingArcSet()->cond(); diff --git a/graph/Graph.tcl b/graph/Graph.tcl index 331fcc73..72c72e42 100644 --- a/graph/Graph.tcl +++ b/graph/Graph.tcl @@ -37,20 +37,20 @@ proc report_edges { args } { set to_pin [get_port_pin_error "to_pin" $keys(-to)] foreach from_vertex [$from_pin vertices] { foreach to_vertex [$to_pin vertices] { - report_edges_between_ $from_vertex $to_vertex + report_edges_between_ $from_vertex $to_vertex } } } elseif [info exists keys(-from)] { set from_pin [get_port_pin_error "from_pin" $keys(-from)] foreach from_vertex [$from_pin vertices] { report_edges_ $from_vertex out_edge_iterator \ - vertex_port_name vertex_path_name + vertex_port_name vertex_path_name } } elseif [info exists keys(-to)] { set to_pin [get_port_pin_error "to_pin" $keys(-to)] foreach to_vertex [$to_pin vertices] { report_edges_ $to_vertex in_edge_iterator \ - vertex_path_name vertex_port_name + vertex_path_name vertex_port_name } } } @@ -61,9 +61,9 @@ proc report_edges_between_ { from_vertex to_vertex } { set edge [$iter next] if { [$edge to] == $to_vertex } { if { [$edge role] == "wire" } { - report_edge_ $edge vertex_path_name vertex_path_name + report_edge_ $edge vertex_path_name vertex_path_name } else { - report_edge_ $edge vertex_port_name vertex_port_name + report_edge_ $edge vertex_port_name vertex_port_name } } } @@ -78,11 +78,11 @@ proc report_edges_ { vertex iter_proc wire_from_name_proc wire_to_name_proc } { set edge [$iter next] if { [$edge role] != "wire" } { if { !$device_header } { - set pin [$vertex pin] - if { ![$pin is_top_level_port] } { - set inst [$pin instance] - } - set device_header 1 + set pin [$vertex pin] + if { ![$pin is_top_level_port] } { + set inst [$pin instance] + } + set device_header 1 } report_edge_ $edge vertex_port_name vertex_port_name } @@ -180,10 +180,6 @@ proc edge_disable_reason { edge } { if { $disables != "" } { append disables ", " } append disables "bidirect instance path" } - if [$edge is_disabled_bidirect_net_path] { - if { $disables != "" } { append disables ", " } - append disables "bidirect net path" - } if { [$edge is_disabled_preset_clear] } { if { $disables != "" } { append disables ", " } append disables "sta_preset_clear_arcs_enabled" @@ -252,7 +248,7 @@ proc_redirect report_disabled_edges { set to_port_name [get_name [$to_pin port]] set cond [$edge cond] if { $cond != "" } { - set when " when: $cond" + set when " when: $cond" } else { set when "" } @@ -295,28 +291,6 @@ proc edge_disable_reason_verbose { edge } { return $disables } -################################################################ - -define_cmd_args "report_slews" {[-corner corner] pin} - -proc report_slews { args } { - global sta_report_default_digits - - parse_key_args "report_slews" args keys {-corner} flags {} - check_argc_eq1 "report_slews" $args - - set corner [parse_corner_or_all keys] - set pin [get_port_pin_error "pin" [lindex $args 0]] - set digits $sta_report_default_digits - foreach vertex [$pin vertices] { - if { $corner == "NULL" } { - report_line "[vertex_path_name $vertex] [rise_short_name] [format_time [$vertex slew rise min] $digits]:[format_time [$vertex slew rise max] $digits] [fall_short_name] [format_time [$vertex slew fall min] $digits]:[format_time [$vertex slew fall max] $digits]" - } else { - report_line "[vertex_path_name $vertex] [rise_short_name] [format_time [$vertex slew_corner rise $corner min] $digits]:[format_time [$vertex slew_corner rise $corner max] $digits] [fall_short_name] [format_time [$vertex slew_corner fall $corner min] $digits]:[format_time [$vertex slew_corner fall $corner max] $digits]" - } - } -} - proc vertex_path_name { vertex } { set pin [$vertex pin] set pin_name [get_full_name $pin] @@ -348,8 +322,8 @@ proc hier_pins_crossed_by_edge { edge } { set to_pins [hier_pins_above [[$edge to] pin]] foreach p $to_pins { report_line [$p path_name] } while { [llength $from_pins] > 0 \ - && [llength $to_pins] > 0 \ - && [lindex $from_pins 0] == [lindex $to_pins 0] } { + && [llength $to_pins] > 0 \ + && [lindex $from_pins 0] == [lindex $to_pins 0] } { set from_pins [lrange $from_pins 1 end] set to_pins [lrange $to_pins 1 end] } @@ -367,9 +341,9 @@ proc hier_pins_above { pin } { while {[$parent_pin_iter has_next]} { set parent_pin [$parent_pin_iter next] if {[$parent_pin net] == $net} { - set pins_above [concat [list $parent_pin] $pins_above] - set found 1 - break + set pins_above [concat [list $parent_pin] $pins_above] + set found 1 + break } } $parent_pin_iter finish diff --git a/graph/GraphCmp.cc b/graph/GraphCmp.cc index 4001fb82..92aa24d0 100644 --- a/graph/GraphCmp.cc +++ b/graph/GraphCmp.cc @@ -22,6 +22,7 @@ // // This notice may not be removed or altered from any source distribution. +#include "ContainerHelpers.hh" #include "StringUtil.hh" #include "Network.hh" #include "NetworkCmp.hh" @@ -37,7 +38,7 @@ VertexNameLess::VertexNameLess(Network *network) : bool VertexNameLess::operator()(const Vertex *vertex1, - const Vertex *vertex2) + const Vertex *vertex2) { return network_->pathNameLess(vertex1->pin(), vertex2->pin()); } @@ -45,7 +46,7 @@ VertexNameLess::operator()(const Vertex *vertex1, //////////////////////////////////////////////////////////////// EdgeLess::EdgeLess(const Network *network, - Graph *&graph) : + Graph *&graph) : pin_less_(network), graph_(graph) { @@ -53,7 +54,7 @@ EdgeLess::EdgeLess(const Network *network, bool EdgeLess::operator()(const Edge *edge1, - const Edge *edge2) const + const Edge *edge2) const { const Pin *from1 = edge1->from(graph_)->pin(); const Pin *from2 = edge2->from(graph_)->pin(); @@ -61,13 +62,13 @@ EdgeLess::operator()(const Edge *edge1, const Pin *to2 = edge2->to(graph_)->pin(); return pin_less_(from1, from2) || (from1 == from2 - && pin_less_(to1, to2)); + && pin_less_(to1, to2)); } void sortEdges(EdgeSeq *edges, - Network *network, - Graph *graph) + Network *network, + Graph *graph) { sort(edges, EdgeLess(network, graph)); } diff --git a/include/sta/ArcDelayCalc.hh b/include/sta/ArcDelayCalc.hh index aaf0bf05..59e431fc 100644 --- a/include/sta/ArcDelayCalc.hh +++ b/include/sta/ArcDelayCalc.hh @@ -40,17 +40,16 @@ namespace sta { -class Corner; +class Scene; class Parasitic; -class DcalcAnalysisPt; class MultiDrvrNet; class ArcDcalcArg; -typedef std::vector ArcDcalcArgPtrSeq; -typedef std::vector ArcDcalcArgSeq; +using ArcDcalcArgPtrSeq = std::vector; +using ArcDcalcArgSeq = std::vector; // Driver load pin -> index in driver loads. -typedef std::map LoadPinIndexMap; +using LoadPinIndexMap = std::map; // Arguments for gate delay calculation delay/slew at one driver pin // through one timing arc at one delay calc analysis point. @@ -81,7 +80,7 @@ public: const Net *drvrNet(const Network *network) const; Edge *edge() const { return edge_; } const TimingArc *arc() const { return arc_; } - Slew inSlew() const { return in_slew_; } + const Slew &inSlew() const { return in_slew_; } float inSlewFlt() const; void setInSlew(Slew in_slew); const Parasitic *parasitic() const { return parasitic_; } @@ -138,8 +137,7 @@ protected: std::vector load_slews_; }; -typedef std::vector ArcDcalcArgSeq; -typedef std::vector ArcDcalcResultSeq; +using ArcDcalcResultSeq = std::vector; // Delay calculator class hierarchy. // ArcDelayCalc @@ -160,7 +158,7 @@ typedef std::vector ArcDcalcResultSeq; class ArcDelayCalc : public StaState { public: - explicit ArcDelayCalc(StaState *sta); + ArcDelayCalc(StaState *sta); virtual ~ArcDelayCalc() {} virtual ArcDelayCalc *copy() = 0; virtual const char *name() const = 0; @@ -168,26 +166,30 @@ public: // Find the parasitic for drvr_pin that is acceptable to the delay // calculator by probing parasitics_. virtual Parasitic *findParasitic(const Pin *drvr_pin, - const RiseFall *rf, - const DcalcAnalysisPt *dcalc_ap) = 0; + const RiseFall *rf, + const Scene *scene, + const MinMax *min_max) = 0; virtual bool reduceSupported() const = 0; // Reduce parasitic_network to a representation acceptable to the delay calculator. virtual Parasitic *reduceParasitic(const Parasitic *parasitic_network, const Pin *drvr_pin, const RiseFall *rf, - const DcalcAnalysisPt *dcalc_ap) = 0; + const Scene *scene, + const MinMax *min_max) = 0; // Reduce parasitic_network to a representation acceptable to the delay calculator - // for one or more corners and min/max rise/fall. - // Null corner means reduce all corners. + // for one or more scenes and min/max rise/fall. + // Null scene means reduce all scenes. virtual void reduceParasitic(const Parasitic *parasitic_network, const Net *net, - const Corner *corner, + const Scene *scene, const MinMaxAll *min_max) = 0; // Set the in_slew, load_cap, parasitic for gates. virtual void setDcalcArgParasiticSlew(ArcDcalcArg &gate, - const DcalcAnalysisPt *dcalc_ap) = 0; + const Scene *scene, + const MinMax *min_max) = 0; virtual void setDcalcArgParasiticSlew(ArcDcalcArgSeq &gates, - const DcalcAnalysisPt *dcalc_ap) = 0; + const Scene *scene, + const MinMax *min_max) = 0; // Find the wire delays and slews for an input port without a driving cell. // This call primarily initializes the load delay/slew iterator. virtual ArcDcalcResult inputPortDelay(const Pin *port_pin, @@ -195,7 +197,8 @@ public: const RiseFall *rf, const Parasitic *parasitic, const LoadPinIndexMap &load_pin_index_map, - const DcalcAnalysisPt *dcalc_ap) = 0; + const Scene *scene, + const MinMax *min_max) = 0; // Find the delay and slew for arc driving drvr_pin. virtual ArcDcalcResult gateDelay(const Pin *drvr_pin, @@ -205,23 +208,26 @@ public: float load_cap, const Parasitic *parasitic, const LoadPinIndexMap &load_pin_index_map, - const DcalcAnalysisPt *dcalc_ap) = 0; + const Scene *scene, + const MinMax *min_max) = 0; // deprecated 2024-02-27 virtual void gateDelay(const TimingArc *arc, - const Slew &in_slew, - float load_cap, - const Parasitic *parasitic, - float related_out_cap, - const Pvt *pvt, - const DcalcAnalysisPt *dcalc_ap, - // Return values. - ArcDelay &gate_delay, - Slew &drvr_slew) __attribute__ ((deprecated)); + const Slew &in_slew, + float load_cap, + const Parasitic *parasitic, + float related_out_cap, + const Pvt *pvt, + const Scene *scene, + const MinMax *min_max, + // Return values. + ArcDelay &gate_delay, + Slew &drvr_slew) __attribute__ ((deprecated)); // Find gate delays and slews for parallel gates. virtual ArcDcalcResultSeq gateDelays(ArcDcalcArgSeq &args, const LoadPinIndexMap &load_pin_index_map, - const DcalcAnalysisPt *dcalc_ap) = 0; + const Scene *scene, + const MinMax *min_max) = 0; // Find the delay for a timing check arc given the arc's // from/clock, to/data slews and related output pin parasitic. @@ -230,7 +236,8 @@ public: const Slew &from_slew, const Slew &to_slew, float related_out_cap, - const DcalcAnalysisPt *dcalc_ap) = 0; + const Scene *scene, + const MinMax *min_max) = 0; // Report delay and slew calculation. virtual std::string reportGateDelay(const Pin *drvr_pin, const TimingArc *arc, @@ -238,7 +245,8 @@ public: float load_cap, const Parasitic *parasitic, const LoadPinIndexMap &load_pin_index_map, - const DcalcAnalysisPt *dcalc_ap, + const Scene *scene, + const MinMax *min_max, int digits) = 0; // Report timing check delay calculation. virtual std::string reportCheckDelay(const Pin *check_pin, @@ -247,7 +255,8 @@ public: const char *from_slew_annotation, const Slew &to_slew, float related_out_cap, - const DcalcAnalysisPt *dcalc_ap, + const Scene *scene, + const MinMax *min_max, int digits) = 0; virtual void finishDrvrPin() = 0; }; diff --git a/include/sta/Bdd.hh b/include/sta/Bdd.hh index b0497d25..ee224975 100644 --- a/include/sta/Bdd.hh +++ b/include/sta/Bdd.hh @@ -34,8 +34,8 @@ struct DdManager; namespace sta { -typedef std::map BddPortVarMap; -typedef std::map BddVarIdxPortMap; +using BddPortVarMap = std::map; +using BddVarIdxPortMap = std::map; class Bdd : public StaState { diff --git a/include/sta/Bfs.hh b/include/sta/Bfs.hh index c95fc5cb..9b639624 100644 --- a/include/sta/Bfs.hh +++ b/include/sta/Bfs.hh @@ -25,9 +25,9 @@ #pragma once #include +#include #include "Iterator.hh" -#include "Set.hh" #include "GraphClass.hh" #include "VertexVisitor.hh" #include "StaState.hh" @@ -39,7 +39,7 @@ class BfsFwdIterator; class BfsBkwdIterator; // LevelQueue is a vector of vertex vectors indexed by logic level. -typedef Vector LevelQueue; +using LevelQueue = std::vector; // Abstract base class for forward and backward breadth first search iterators. // Visit all of the vertices at a level before moving to the next. @@ -58,19 +58,19 @@ public: void ensureSize(); // Reset to virgin state. void clear(); - bool empty() const; + [[nodiscard]] bool empty() const; // Enqueue a vertex to search from. void enqueue(Vertex *vertex); // Enqueue vertices adjacent to a vertex. void enqueueAdjacentVertices(Vertex *vertex); - void enqueueAdjacentVertices(Vertex *vertex, - SearchPred *search_pred); - void enqueueAdjacentVertices(Vertex *vertex, - Level to_level); + virtual void enqueueAdjacentVertices(Vertex *vertex, + const Mode *mode); virtual void enqueueAdjacentVertices(Vertex *vertex, SearchPred *search_pred, - Level to_level) = 0; - bool inQueue(Vertex *vertex); + const Mode *mode) = 0; + virtual void enqueueAdjacentVertices(Vertex *vertex, + SearchPred *search_pred) = 0; + [[nodiscard]] bool inQueue(Vertex *vertex); void checkInQueue(Vertex *vertex); // Notify iterator that vertex will be deleted. void deleteVertexBefore(Vertex *vertex); @@ -131,9 +131,11 @@ public: SearchPred *search_pred, StaState *sta); virtual ~BfsFwdIterator(); + virtual void enqueueAdjacentVertices(Vertex *vertex, + SearchPred *search_pred); virtual void enqueueAdjacentVertices(Vertex *vertex, SearchPred *search_pred, - Level to_level); + const Mode *mode); using BfsIterator::enqueueAdjacentVertices; protected: @@ -151,9 +153,11 @@ public: SearchPred *search_pred, StaState *sta); virtual ~BfsBkwdIterator(); + virtual void enqueueAdjacentVertices(Vertex *vertex, + SearchPred *search_pred); virtual void enqueueAdjacentVertices(Vertex *vertex, SearchPred *search_pred, - Level to_level); + const Mode *mode); using BfsIterator::enqueueAdjacentVertices; protected: diff --git a/include/sta/BoundedHeap.hh b/include/sta/BoundedHeap.hh new file mode 100644 index 00000000..45bfdeed --- /dev/null +++ b/include/sta/BoundedHeap.hh @@ -0,0 +1,256 @@ +// OpenSTA, Static Timing Analyzer +// Copyright (c) 2025, Parallax Software, Inc. +// +// This program is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see . +// +// The origin of this software must not be misrepresented; you must not +// claim that you wrote the original software. +// +// Altered source versions must be plainly marked as such, and must not be +// misrepresented as being the original software. +// +// This notice may not be removed or altered from any source distribution. + +#pragma once + +#include +#include +#include + +namespace sta { + +// BoundedHeap: A container that maintains the top N elements using a min-heap. +// This provides O(log n) insertion when the heap is full, O(1) when not full, +// and O(n log n) extraction of all elements. Useful for maintaining top K +// elements without storing all elements. +// +// The heap maintains the "worst" (minimum according to Compare) element at +// the root, so new elements that are better than the worst can replace it. +// For example, with Compare = std::greater, this maintains the N largest +// values (greater values are "better"). +// +// Template parameters: +// T: The element type +// Compare: Comparison function object type (default: std::less) +// For top N largest, use std::greater +// For top N smallest, use std::less +template > +class BoundedHeap { +public: + using value_type = T; + using size_type = size_t; + using const_reference = const T&; + using compare_type = Compare; + + // Constructors + explicit BoundedHeap(size_type max_size, + const Compare& comp = Compare()) : + max_size_(max_size), + comp_(comp), + min_heap_comp_(comp) + { + heap_.reserve(max_size); + } + + // Copy constructor + BoundedHeap(const BoundedHeap& other) : + heap_(other.heap_), + max_size_(other.max_size_), + comp_(other.comp_), + min_heap_comp_(other.comp_) + {} + + // Assignment operator + BoundedHeap& operator=(const BoundedHeap& other) + { + if (this != &other) { + heap_ = other.heap_; + max_size_ = other.max_size_; + comp_ = other.comp_; + min_heap_comp_ = MinHeapCompare(other.comp_); + } + return *this; + } + + // Move constructor + BoundedHeap(BoundedHeap&& other) noexcept : + heap_(std::move(other.heap_)), + max_size_(other.max_size_), + comp_(std::move(other.comp_)), + min_heap_comp_(comp_) + {} + + // Move assignment operator + BoundedHeap& operator=(BoundedHeap&& other) noexcept + { + if (this != &other) { + heap_ = std::move(other.heap_); + max_size_ = other.max_size_; + comp_ = std::move(other.comp_); + min_heap_comp_ = MinHeapCompare(comp_); + } + return *this; + } + + void + setMaxSize(size_t max_size) + { + max_size_ = max_size; + heap_.reserve(max_size); + } + + // Insert an element into the heap. + // If the heap is not full, the element is added. + // If the heap is full and the new element is better than the worst element, + // the worst element is replaced. Otherwise, the element is ignored. + // Returns true if the element was inserted, false if it was ignored. + bool + insert(const T& value) { + if (heap_.size() < max_size_) { + heap_.push_back(value); + std::push_heap(heap_.begin(), heap_.end(), min_heap_comp_); + return true; + } + else if (!heap_.empty()) { + // When keeping N worst (smallest) values: if new value is smaller than worst, + // we should keep it and remove the largest element to make room. + // If new value is larger than worst, we reject it (already have worse values). + // comp_(value, worst) is true when value < worst (value is smaller/worse) + if (comp_(value, heap_.front())) { + // New value is smaller than worst - find and replace the largest element + auto max_it = std::max_element(heap_.begin(), heap_.end(), comp_); + *max_it = value; + // Rebuild heap since we modified an internal element + std::make_heap(heap_.begin(), heap_.end(), min_heap_comp_); + return true; + } + // Otherwise, new value is >= worst, so we already have worse values - reject it + } + return false; + } + + // Insert an element using move semantics + bool insert(T&& value) + { + if (heap_.size() < max_size_) { + heap_.push_back(std::move(value)); + std::push_heap(heap_.begin(), heap_.end(), min_heap_comp_); + return true; + } + else if (!heap_.empty()) { + // When keeping N worst (smallest) values: if new value is smaller than worst, + // we should keep it and remove the largest element to make room. + // If new value is larger than worst, we reject it (already have worse values). + // comp_(value, worst) is true when value < worst (value is smaller/worse) + if (comp_(value, heap_.front())) { + // New value is smaller than worst - find and replace the largest element + auto max_it = std::max_element(heap_.begin(), heap_.end(), comp_); + *max_it = std::move(value); + // Rebuild heap since we modified an internal element + std::make_heap(heap_.begin(), heap_.end(), min_heap_comp_); + return true; + } + // Otherwise, new value is >= worst, so we already have worse values - reject it + } + return false; + } + + // Extract all elements sorted from best to worst. + // This destroys the heap structure but preserves the elements. + std::vector extract() + { + // Convert heap to sorted vector (best to worst) + std::sort_heap(heap_.begin(), heap_.end(), min_heap_comp_); + // Reverse to get best first (according to user's comparison) + std::reverse(heap_.begin(), heap_.end()); + std::vector result = std::move(heap_); + heap_.clear(); + return result; + } + + // Extract all elements sorted from best to worst (const version). + // Creates a copy since we can't modify the heap. + std::vector extract() const + { + std::vector temp_heap = heap_; + std::sort_heap(temp_heap.begin(), temp_heap.end(), min_heap_comp_); + std::reverse(temp_heap.begin(), temp_heap.end()); + return temp_heap; + } + + // Get the worst element (the one that would be replaced next). + // Requires !empty() + const_reference worst() const + { + return heap_.front(); + } + + // Check if the heap is empty + bool empty() const + { + return heap_.empty(); + } + + // Get the current number of elements in the heap + size_type size() const + { + return heap_.size(); + } + + // Get the maximum size of the heap + size_type max_size() const + { + return max_size_; + } + + // Check if the heap is full + bool full() const + { + return heap_.size() >= max_size_; + } + + // Clear all elements from the heap + void clear() + { + heap_.clear(); + } + + // Get the comparison function + Compare compare() const + { + return comp_; + } + +private: + std::vector heap_; + size_type max_size_; + Compare comp_; + + // Helper comparator for min-heap: we want the worst element at root + // so we can easily remove it when adding better elements. + // This is the inverse of the user's comparison. + struct MinHeapCompare + { + Compare comp_; + explicit MinHeapCompare(const Compare& c) : comp_(c) {} + bool operator()(const T& a, const T& b) const { + return comp_(b, a); // Inverted: worst is at root + } + }; + + MinHeapCompare min_heap_comp_; +}; + +} // namespace sta + diff --git a/include/sta/ClkNetwork.hh b/include/sta/ClkNetwork.hh index 62d89a78..8b4692fd 100644 --- a/include/sta/ClkNetwork.hh +++ b/include/sta/ClkNetwork.hh @@ -24,8 +24,8 @@ #pragma once -#include "Map.hh" -#include "Set.hh" +#include + #include "StaState.hh" #include "NetworkClass.hh" #include "GraphClass.hh" @@ -33,31 +33,34 @@ namespace sta { -typedef Map PinClksMap; -typedef Map ClkPinsMap; +using PinClksMap = std::map; +using ClkPinsMap = std::map; class Sta; // Find clock network pins. -// This is not as reliable as Search::isClock but is much cheaper. class ClkNetwork : public StaState { public: - ClkNetwork(StaState *sta); + ClkNetwork(Mode *mode, + StaState *sta); ~ClkNetwork(); void ensureClkNetwork(); void clear(); bool isClock(const Pin *pin) const; + bool isClock(const Vertex *vertex) const; bool isClock(const Net *net) const; bool isIdealClock(const Pin *pin) const; + bool isIdealClock(const Vertex *vertex) const; bool isPropagatedClock(const Pin *pin) const; - const ClockSet *clocks(const Pin *pin); - const ClockSet *idealClocks(const Pin *pin); + const ClockSet *clocks(const Pin *pin) const; + const ClockSet *clocks(const Vertex *vertex) const; + const ClockSet *idealClocks(const Pin *pin) const; const PinSet *pins(const Clock *clk); void clkPinsInvalid(); float idealClkSlew(const Pin *pin, const RiseFall *rf, - const MinMax *min_max); + const MinMax *min_max) const; protected: void deletePinBefore(const Pin *pin); @@ -66,9 +69,11 @@ protected: friend class Sta; private: + Mode *mode_; + void findClkPins(); void findClkPins(bool ideal_only, - PinClksMap &clk_pin_map); + PinClksMap &clk_pin_map); bool clk_pins_valid_; // pin -> clks diff --git a/include/sta/Clock.hh b/include/sta/Clock.hh index d372aab2..25dd9244 100644 --- a/include/sta/Clock.hh +++ b/include/sta/Clock.hh @@ -24,6 +24,8 @@ #pragma once +#include + #include "MinMax.hh" #include "RiseFallMinMax.hh" #include "SdcClass.hh" @@ -32,7 +34,7 @@ namespace sta { -typedef Map ClkHpinEdgeMap; +using ClkHpinEdgeMap = std::map; class Clock : public SdcCmdComment { @@ -63,40 +65,40 @@ public: bool isIdeal() const { return !is_propagated_; } // Ideal clock slew. void slew(const RiseFall *rf, - const MinMax *min_max, - // Return values. - float &slew, - bool &exists) const; + const MinMax *min_max, + // Return values. + float &slew, + bool &exists) const; // Return zero (default) if no slew exists. float slew(const RiseFall *rf, - const MinMax *min_max) const; + const MinMax *min_max) const; void setSlew(const RiseFall *rf, - const MinMax *min_max, - float slew); + const MinMax *min_max, + float slew); void setSlew(const RiseFallBoth *rf, - const MinMaxAll *min_max, - float slew); + const MinMaxAll *min_max, + float slew); void removeSlew(); const RiseFallMinMax &slews() const { return slews_; } void setSlewLimit(const RiseFallBoth *rf, - const PathClkOrData clk_data, - const MinMax *min_max, - float slew); + const PathClkOrData clk_data, + const MinMax *min_max, + float slew); void slewLimit(const RiseFall *rf, - const PathClkOrData clk_data, - const MinMax *min_max, - // Return values. - float &slew, - bool &exists) const; + const PathClkOrData clk_data, + const MinMax *min_max, + // Return values. + float &slew, + bool &exists) const; ClockUncertainties *uncertainties() const { return uncertainties_; } void uncertainty(const SetupHold *setup_hold, - // Return values. - float &uncertainty, - bool &exists) const; + // Return values. + float &uncertainty, + bool &exists) const; void setUncertainty(const SetupHoldAll *setup_hold, - float uncertainty); + float uncertainty); void setUncertainty(const SetupHold *setup_hold, - float uncertainty); + float uncertainty); void removeUncertainty(const SetupHoldAll *setup_hold); void setPeriod(float period); @@ -124,8 +126,8 @@ public: bool isDivideByOneCombinational() const; bool generatedUpToDate() const; void srcPinVertices(VertexSet &src_vertices, - const Network *network, - Graph *graph); + const Network *network, + Graph *graph); // True if the generated clock waveform is up to date. bool waveformValid() const { return waveform_valid_; } void waveformInvalid(); @@ -133,36 +135,36 @@ public: protected: // Private to Sdc::makeClock. Clock(const char *name, - int index, + int index, const Network *network); void initClk(PinSet *pins, - bool add_to_pins, - float period, - FloatSeq *waveform, - const char *comment, - const Network *network); + bool add_to_pins, + float period, + FloatSeq *waveform, + const char *comment, + const Network *network); void initGeneratedClk(PinSet *pins, - bool add_to_pins, - Pin *src_pin, - Clock *master_clk, - int divide_by, - int multiply_by, - float duty_cycle, - bool invert, - bool combinational, - IntSeq *edges, - FloatSeq *edge_shifts, - bool is_propagated, - const char *comment, - const Network *network); + bool add_to_pins, + Pin *src_pin, + Clock *master_clk, + int divide_by, + int multiply_by, + float duty_cycle, + bool invert, + bool combinational, + IntSeq *edges, + FloatSeq *edge_shifts, + bool is_propagated, + const char *comment, + const Network *network); void setPins(PinSet *pins, - const Network *network); + const Network *network); void setMasterClk(Clock *master); void makeClkEdges(); void setClkEdgeTimes(); void setClkEdgeTime(const RiseFall *rf); void generateScaledClk(const Clock *src_clk, - float scale); + float scale); void generateEdgesClk(const Clock *src_clk); const char *name_; @@ -229,10 +231,10 @@ clkCmp(const Clock *clk1, const Clock *clk2); int clkEdgeCmp(const ClockEdge *clk_edge1, - const ClockEdge *clk_edge2); + const ClockEdge *clk_edge2); bool clkEdgeLess(const ClockEdge *clk_edge1, - const ClockEdge *clk_edge2); + const ClockEdge *clk_edge2); class ClockNameLess { @@ -247,24 +249,24 @@ class InterClockUncertainty { public: InterClockUncertainty(const Clock *src, - const Clock *target); + const Clock *target); const Clock *src() const { return src_; } const Clock *target() const { return target_; } void uncertainty(const RiseFall *src_rf, - const RiseFall *tgt_rf, - const SetupHold *setup_hold, - // Return values. - float &uncertainty, - bool &exists) const; + const RiseFall *tgt_rf, + const SetupHold *setup_hold, + // Return values. + float &uncertainty, + bool &exists) const; void setUncertainty(const RiseFallBoth *src_rf, - const RiseFallBoth *tgt_rf, - const SetupHoldAll *setup_hold, - float uncertainty); + const RiseFallBoth *tgt_rf, + const SetupHoldAll *setup_hold, + float uncertainty); void removeUncertainty(const RiseFallBoth *src_rf, - const RiseFallBoth *tgt_rf, - const SetupHoldAll *setup_hold); + const RiseFallBoth *tgt_rf, + const SetupHoldAll *setup_hold); const RiseFallMinMax *uncertainties(const RiseFall *src_rf) const; - bool empty() const; + [[nodiscard]] bool empty() const; private: const Clock *src_; @@ -276,14 +278,14 @@ class InterClockUncertaintyLess { public: bool operator()(const InterClockUncertainty *inter1, - const InterClockUncertainty *inter2) const; + const InterClockUncertainty *inter2) const; }; class ClkNameLess { public: bool operator()(const Clock *clk1, - const Clock *clk2) const + const Clock *clk2) const { return stringLess(clk1->name(), clk2->name()); } diff --git a/include/sta/ClockGroups.hh b/include/sta/ClockGroups.hh index 50944034..38e905c1 100644 --- a/include/sta/ClockGroups.hh +++ b/include/sta/ClockGroups.hh @@ -33,11 +33,11 @@ class ClockGroups : public SdcCmdComment { public: ClockGroups(const char *name, - bool logically_exclusive, - bool physically_exclusive, - bool asynchronous, - bool allow_paths, - const char *comment); + bool logically_exclusive, + bool physically_exclusive, + bool asynchronous, + bool allow_paths, + const char *comment); ~ClockGroups(); void makeClockGroup(ClockSet *clks); const char *name() const { return name_; } diff --git a/include/sta/ClockInsertion.hh b/include/sta/ClockInsertion.hh index 1496deda..43fc4899 100644 --- a/include/sta/ClockInsertion.hh +++ b/include/sta/ClockInsertion.hh @@ -39,16 +39,16 @@ public: const Clock *clock() const { return clk_; } const Pin *pin() const { return pin_; } float delay(const RiseFall *rf, const MinMax *min_max, - const EarlyLate *early_late); + const EarlyLate *early_late); void delay(const RiseFall *rf, const MinMax *min_max, - const EarlyLate *early_late, - // Return values. - float &insertion, bool &exists); + const EarlyLate *early_late, + // Return values. + float &insertion, bool &exists); RiseFallMinMax *delays(const EarlyLate *early_late); void setDelay(const RiseFall *rf, const MinMax *min_max, - const EarlyLate *early_late, float delay); + const EarlyLate *early_late, float delay); void setDelay(const RiseFallBoth *rf, const MinMaxAll *min_max, - const EarlyLateAll *early_late, float delay); + const EarlyLateAll *early_late, float delay); void setDelays(RiseFallMinMax *delays); private: diff --git a/include/sta/ClockLatency.hh b/include/sta/ClockLatency.hh index 9e05680b..9972bdc4 100644 --- a/include/sta/ClockLatency.hh +++ b/include/sta/ClockLatency.hh @@ -36,23 +36,23 @@ class ClockLatency { public: ClockLatency(const Clock *clk, - const Pin *pin); + const Pin *pin); const Clock *clock() const { return clk_; } const Pin *pin() const { return pin_; } float delay(const RiseFall *rf, - const MinMax *min_max); + const MinMax *min_max); void delay(const RiseFall *rf, - const MinMax *min_max, - // Return values. - float &latency, - bool &exists); + const MinMax *min_max, + // Return values. + float &latency, + bool &exists); RiseFallMinMax *delays(); void setDelay(const RiseFall *rf, - const MinMax *min_max, - float delay); + const MinMax *min_max, + float delay); void setDelay(const RiseFallBoth *rf, - const MinMaxAll *min_max, - float delay); + const MinMaxAll *min_max, + float delay); void setDelays(RiseFallMinMax *delays); private: diff --git a/include/sta/ConcreteLibrary.hh b/include/sta/ConcreteLibrary.hh index d4eb6ff8..48c4db06 100644 --- a/include/sta/ConcreteLibrary.hh +++ b/include/sta/ConcreteLibrary.hh @@ -25,9 +25,9 @@ #pragma once #include +#include +#include -#include "Vector.hh" -#include "Map.hh" #include "StringUtil.hh" #include "NetworkClass.hh" @@ -45,19 +45,19 @@ class PatternMatch; class LibertyCell; class LibertyPort; -typedef Map ConcreteCellMap; -typedef Vector ConcretePortSeq; -typedef Map ConcretePortMap; -typedef ConcreteCellMap::ConstIterator ConcreteLibraryCellIterator; -typedef ConcretePortSeq::ConstIterator ConcreteCellPortIterator; -typedef ConcretePortSeq::ConstIterator ConcretePortMemberIterator; +using ConcreteCellMap = std::map; +using ConcretePortSeq = std::vector; +using ConcretePortMap = std::map; +using ConcreteLibraryCellIterator = MapIterator; +using ConcreteCellPortIterator = VectorIterator; +using ConcretePortMemberIterator = VectorIterator; class ConcreteLibrary { public: - explicit ConcreteLibrary(const char *name, - const char *filename, - bool is_liberty); + ConcreteLibrary(const char *name, + const char *filename, + bool is_liberty); virtual ~ConcreteLibrary(); const char *name() const { return name_.c_str(); } void setName(const char *name); @@ -66,8 +66,8 @@ public: const char *filename() const { return filename_.c_str(); } void addCell(ConcreteCell *cell); ConcreteCell *makeCell(const char *name, - bool is_leaf, - const char *filename); + bool is_leaf, + const char *filename); void deleteCell(ConcreteCell *cell); ConcreteLibraryCellIterator *cellIterator() const; ConcreteCell *findCell(const char *name) const; @@ -75,11 +75,11 @@ public: char busBrktLeft() const { return bus_brkt_left_; } char busBrktRight() const { return bus_brkt_right_; } void setBusBrkts(char left, - char right); + char right); protected: void renameCell(ConcreteCell *cell, - const char *cell_name); + const char *cell_name); std::string name_; ObjectId id_; @@ -122,14 +122,14 @@ public: ConcretePort *makePort(const char *name); // Bus port. ConcretePort *makeBusPort(const char *name, - int from_index, - int to_index); + int from_index, + int to_index); // Bundle port. ConcretePort *makeBundlePort(const char *name, - ConcretePortSeq *members); + ConcretePortSeq *members); // Group previously defined bus bit ports together. void groupBusPorts(const char bus_brkt_left, - const char bus_brkt_right, + const char bus_brkt_right, std::function port_msb_first); size_t portCount() const; void setName(const char *name); @@ -138,23 +138,23 @@ public: protected: ConcreteCell(const char *name, - const char *filename, + const char *filename, bool is_leaf, ConcreteLibrary *library); ConcretePort *makeBusPort(const char *name, - int from_index, - int to_index, - ConcretePortSeq *members); + int from_index, + int to_index, + ConcretePortSeq *members); void makeBusPortBits(ConcretePort *bus_port, - const char *name, - int from_index, - int to_index); + const char *name, + int from_index, + int to_index); // Bus port bit (internal to makeBusPortBits). ConcretePort *makePort(const char *bit_name, - int bit_index); + int bit_index); void makeBusPortBit(ConcretePort *bus_port, - const char *name, - int index); + const char *name, + int index); std::string name_; ObjectId id_; @@ -233,10 +233,10 @@ protected: // Constructors for factory in cell class. ConcretePort(const char *name, bool is_bus, - int from_index, - int to_index, - bool is_bundle, - ConcretePortSeq *member_ports, + int from_index, + int to_index, + bool is_bundle, + ConcretePortSeq *member_ports, ConcreteCell *cell); std::string name_; @@ -263,14 +263,15 @@ private: class ConcreteCellPortBitIterator : public Iterator { public: - explicit ConcreteCellPortBitIterator(const ConcreteCell *cell); + ConcreteCellPortBitIterator(const ConcreteCell *cell); virtual bool hasNext(); virtual ConcretePort *next(); private: void findNext(); - ConcretePortSeq::ConstIterator port_iter_; + const ConcretePortSeq &ports_; + ConcretePortSeq::const_iterator port_iter_; ConcretePortMemberIterator *member_iter_; ConcretePort *next_; }; diff --git a/include/sta/ConcreteNetwork.hh b/include/sta/ConcreteNetwork.hh index 16259873..fe2b76c3 100644 --- a/include/sta/ConcreteNetwork.hh +++ b/include/sta/ConcreteNetwork.hh @@ -25,9 +25,10 @@ #pragma once #include +#include +#include +#include -#include "Map.hh" -#include "Set.hh" #include "StringUtil.hh" #include "Network.hh" #include "LibertyClass.hh" @@ -45,16 +46,14 @@ class ConcretePort; class ConcreteBindingTbl; class ConcreteLibertyLibraryIterator; -typedef Vector ConcreteLibrarySeq; -typedef Map ConcreteLibraryMap; -typedef ConcreteLibrarySeq::ConstIterator ConcreteLibraryIterator; -typedef Map ConcreteInstanceChildMap; -typedef Map ConcreteInstanceNetMap; -typedef Vector ConcreteNetSeq; -typedef Vector ConcretePinSeq; -typedef Map CellNetworkViewMap; -typedef Set ConcreteNetSet; +using ConcreteLibrarySeq = std::vector; +using ConcreteLibraryMap = std::map; +using ConcreteInstanceChildMap = std::map; +using ConcreteInstanceNetMap = std::map; +using ConcreteNetSeq = std::vector; +using ConcretePinSeq = std::vector; +using CellNetworkViewMap = std::map; +using ConcreteNetSet = std::set; // This adapter implements the network api for the concrete network. // A superset of the Network api methods are implemented in the interface. @@ -172,7 +171,7 @@ public: ConstantPinIterator *constantPinIterator() override; void addConstantNet(Net *net, - LogicValue value) override; + LogicValue value) override; // Edit methods. Library *makeLibrary(const char *name, @@ -270,12 +269,12 @@ protected: PinVisitor &visitor, NetSet &visited_nets) const override; Instance *makeConcreteInstance(ConcreteCell *cell, - const char *name, - Instance *parent); + const char *name, + Instance *parent); void disconnectNetPin(ConcreteNet *cnet, - ConcretePin *cpin); + ConcretePin *cpin); void connectNetPin(ConcreteNet *cnet, - ConcretePin *cpin); + ConcretePin *cpin); // Cell lookup search order sequence. ConcreteLibrarySeq library_seq_; @@ -315,14 +314,14 @@ public: void deletePin(ConcretePin *pin); void addNet(ConcreteNet *net); void addNet(const char *name, - ConcreteNet *net); + ConcreteNet *net); void deleteNet(ConcreteNet *net); void setCell(ConcreteCell *cell); void initPins(); protected: ConcreteInstance(const char *name, - ConcreteCell *cell, + ConcreteCell *cell, ConcreteInstance *parent); ~ConcreteInstance(); @@ -356,8 +355,8 @@ public: protected: ~ConcretePin() {} ConcretePin(ConcreteInstance *instance, - ConcretePort *port, - ConcreteNet *net); + ConcretePort *port, + ConcreteNet *net); ConcreteInstance *instance_; ConcretePort *port_; @@ -386,7 +385,7 @@ public: protected: ~ConcreteTerm() {} ConcreteTerm(ConcretePin *pin, - ConcreteNet *net); + ConcreteNet *net); ConcretePin *pin_; ConcreteNet *net_; @@ -415,7 +414,7 @@ public: protected: ConcreteNet(const char *name, - ConcreteInstance *instance); + ConcreteInstance *instance); ~ConcreteNet(); const char *name_; ObjectId id_; diff --git a/include/sta/ContainerHelpers.hh b/include/sta/ContainerHelpers.hh new file mode 100644 index 00000000..49268ce8 --- /dev/null +++ b/include/sta/ContainerHelpers.hh @@ -0,0 +1,381 @@ +// OpenSTA, Static Timing Analyzer +// Copyright (c) 2025, Parallax Software, Inc. +// +// This program is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see . +// +// The origin of this software must not be misrepresented; you must not +// claim that you wrote the original software. +// +// Altered source versions must be plainly marked as such, and must not be +// misrepresented as being the original software. +// +// This notice may not be removed or altered from any source distribution. + +#pragma once + +#include +#include // for std::declval +#include +#include +#include +#include +#include +#include + +namespace sta { + +// C++ kung foo courtesy of chat gtp. + +// ------------------------------------------------------------ +// 1. Sequence containers (vector, list, deque, …) +// ------------------------------------------------------------ +template +std::enable_if_t> +deleteContents(Container& c) +{ + for (auto ptr : c) + delete ptr; + c.clear(); +} + +template +std::enable_if_t> +deleteContents(Container *c) +{ + for (auto ptr : *c) + delete ptr; + c->clear(); +} + +// ------------------------------------------------------------ +// 2. Maps (map, unordered_map) +// ------------------------------------------------------------ +template +std::enable_if_t +> +deleteContents(Map& m) +{ + for (auto& kv : m) + delete kv.second; + m.clear(); +} + +template +std::enable_if_t +> +deleteContents(Map *m) +{ + for (auto& kv : *m) + delete kv.second; + m->clear(); +} + +// ------------------------------------------------------------ +// 3. Sets (set, unordered_set) +// ------------------------------------------------------------ +template +std::enable_if_t< + std::is_pointer_v && + !std::is_same_v +> +deleteContents(Set& s) +{ + for (auto ptr : s) + delete ptr; + s.clear(); +} + +//////////////////////////////////////////////////////////////// + +// detect whether container has mapped_type +template +struct has_mapped_type : std::false_type {}; + +template +struct has_mapped_type> + : std::true_type {}; + +// handle pointer types +template +struct has_mapped_type : has_mapped_type {}; + +// return-type chooser: use struct, NOT alias template +template::value> +struct find_return; + +// pointer to map +template +struct find_return +{ + using type = typename C::mapped_type; +}; + +// pointer to set +template +struct find_return +{ + using type = typename C::key_type; +}; + +// map ref +template +struct find_return +{ + using type = typename C::mapped_type; +}; + +// set ref +template +struct find_return +{ + using type = typename C::key_type; +}; + + +// Find an value in a contaiiner of pointers. +// return nullptr if not found. +template +auto +findKey(const AssocContainer& c, + typename AssocContainer::key_type key) + -> typename find_return::type +{ + using ReturnType = typename find_return::type; + + static_assert(std::is_pointer_v, + "findKey requires pointer types"); + + auto it = c.find(key); + if (it == c.end()) + return nullptr; + + if constexpr (has_mapped_type::value) + return it->second; // map + else + return *it; // set +} + +// Find an value in a contaiiner of pointers. +// return nullptr if not found. +template +auto +findKey(const AssocContainer* c, + typename AssocContainer::key_type key) + -> typename find_return::type +{ + using ReturnType = typename find_return::type; + + static_assert(std::is_pointer_v, + "findKey requires pointer types"); + + auto it = c->find(key); + if (it == c->end()) + return nullptr; + + if constexpr (has_mapped_type::value) + // map + return it->second; + else + // set + return *it; +} + +template +void +findKeyValue(const AssocContainer& c, + typename AssocContainer::key_type key, + typename find_return::type &value, + bool &exists) +{ + auto it = c.find(key); + if (it == c.end()) { + exists = false; + return; + } + + if constexpr (has_mapped_type::value) { + // map + value = it->second; + exists = true; + } + else { + // set + value = *it; + exists = true; + } +} + +template +void +findKeyValue(const AssocContainer *c, + typename AssocContainer::key_type key, + typename find_return::type &value, + bool &exists) +{ + auto it = c->find(key); + if (it == c->end()) { + exists = false; + return; + } + + if constexpr (has_mapped_type::value) { + // map + value = it->second; + exists = true; + } + else { + // set + value = *it; + exists = true; + } +} + +template +auto +findKeyValuePtr(AssocContainer& c, + typename AssocContainer::key_type key) + -> typename find_return::type* +{ + auto it = c.find(key); + if (it == c.end()) + return nullptr; + + if constexpr (has_mapped_type::value) + // map + return &it->second; + else + // set + return *it; +} + +//////////////////////////////////////////////////////////////// + +// Determine if two std::set's intersect. +// Returns true if there is at least one common element. +template +bool +intersects(const Set &set1, + const Set &set2, + typename Set::key_compare key_less) +{ + auto iter1 = set1.begin(); + auto end1 = set1.end(); + auto iter2 = set2.begin(); + auto end2 = set2.end(); + + while (iter1 != end1 && iter2 != end2) { + if (key_less(*iter1, *iter2)) + iter1++; + else if (key_less(*iter2, *iter1)) + iter2++; + else + return true; + } + return false; +} + +// Determine if two std::set's intersect (pointer version). +// Returns true if there is at least one common element. +template +bool +intersects(const Set *set1, + const Set *set2, + typename Set::key_compare key_less) +{ + if (set1 && set2) { + auto iter1 = set1->begin(); + auto end1 = set1->end(); + auto iter2 = set2->begin(); + auto end2 = set2->end(); + + while (iter1 != end1 && iter2 != end2) { + if (key_less(*iter1, *iter2)) + iter1++; + else if (key_less(*iter2, *iter1)) + iter2++; + else + return true; + } + } + return false; +} + +//////////////////////////////////////////////////////////////// + +// Compare set contents. +template +int +compare(const Set *set1, + const Set *set2, + typename Set::key_compare key_less) +{ + size_t size1 = set1 ? set1->size() : 0; + size_t size2 = set2 ? set2->size() : 0; + if (size1 == size2) { + if (set1 == nullptr || set2 == nullptr) { + // Both are null or empty, so they're equal + return 0; + } + auto iter1 = set1->begin(); + auto iter2 = set2->begin(); + auto end1 = set1->end(); + auto end2 = set2->end(); + while (iter1 != end1 && iter2 != end2) { + if (key_less(*iter1, *iter2)) + return -1; + else if (key_less(*iter2, *iter1)) + return 1; + ++iter1; + ++iter2; + } + // Sets are equal. + return 0; + } + else + return (size1 > size2) ? 1 : -1; +} + +//////////////////////////////////////////////////////////////// + +// Sort functions that do not require begin()/end() range. + +// reference arg +template> +requires std::predicate, + std::ranges::range_reference_t> +void +sort(Range& r, + Comp comp = Comp{}) +{ + std::sort(std::ranges::begin(r), std::ranges::end(r), comp); +} + + +// pointer arg +template> +requires std::ranges::random_access_range && + std::predicate, + std::ranges::range_reference_t> +void +sort(Range* r, + Comp comp = Comp{}) +{ + std::sort(std::ranges::begin(*r), std::ranges::end(*r), comp); +} + +} // namespace diff --git a/include/sta/Corner.hh b/include/sta/Corner.hh deleted file mode 100644 index bee765d0..00000000 --- a/include/sta/Corner.hh +++ /dev/null @@ -1,139 +0,0 @@ -// OpenSTA, Static Timing Analyzer -// Copyright (c) 2025, Parallax Software, Inc. -// -// This program is free software: you can redistribute it and/or modify -// it under the terms of the GNU General Public License as published by -// the Free Software Foundation, either version 3 of the License, or -// (at your option) any later version. -// -// This program is distributed in the hope that it will be useful, -// but WITHOUT ANY WARRANTY; without even the implied warranty of -// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -// GNU General Public License for more details. -// -// You should have received a copy of the GNU General Public License -// along with this program. If not, see . -// -// The origin of this software must not be misrepresented; you must not -// claim that you wrote the original software. -// -// Altered source versions must be plainly marked as such, and must not be -// misrepresented as being the original software. -// -// This notice may not be removed or altered from any source distribution. - -#pragma once - -#include "MinMax.hh" -#include "Vector.hh" -#include "StringSet.hh" -#include "GraphClass.hh" -#include "SearchClass.hh" -#include "StaState.hh" - -namespace sta { - -class ParasiticAnalysisPt; -class DcalcAnalysisPt; -class PathAnalysisPt; -class Corner; -class Corners; -class LibertyLibrary; - -typedef Vector CornerSeq; -typedef Map CornerMap; -typedef Vector ParasiticAnalysisPtSeq; -typedef Vector DcalcAnalysisPtSeq; -typedef Vector PathAnalysisPtSeq; -typedef Vector LibertySeq; - -class Corners : public StaState -{ -public: - explicit Corners(StaState *sta); - ~Corners(); - void clear(); - int count() const; - void copy(Corners *corners); - bool multiCorner() const; - Corner *findCorner(const char *corner); - Corner *findCorner(int corner_index); - void makeCorners(StringSet *corner_names); - void analysisTypeChanged(); - void operatingConditionsChanged(); - - // Make one parasitic analysis points. - void makeParasiticAnalysisPts(bool per_corner); - int parasiticAnalysisPtCount() const; - ParasiticAnalysisPtSeq ¶siticAnalysisPts(); - - DcalcAPIndex dcalcAnalysisPtCount() const; - DcalcAnalysisPtSeq &dcalcAnalysisPts(); - const DcalcAnalysisPtSeq &dcalcAnalysisPts() const; - - PathAPIndex pathAnalysisPtCount() const; - PathAnalysisPt *findPathAnalysisPt(PathAPIndex path_index) const; - PathAnalysisPtSeq &pathAnalysisPts(); - const PathAnalysisPtSeq &pathAnalysisPts() const; - CornerSeq &corners() { return corners_; } - // Iterators for range iteration. - // for (auto corner : *sta->corners()) {} - CornerSeq::iterator begin() { return corners_.begin(); } - CornerSeq::iterator end() { return corners_.end(); } - -protected: - void makeAnalysisPts(); - void makeDcalcAnalysisPts(Corner *corner); - DcalcAnalysisPt *makeDcalcAnalysisPt(Corner *corner, - const MinMax *min_max, - const MinMax *check_clk_slew_min_max); - void makePathAnalysisPts(Corner *corner); - void makePathAnalysisPts(Corner *corner, - bool swap_clk_min_max, - DcalcAnalysisPt *dcalc_ap_min, - DcalcAnalysisPt *dcalc_ap_max); - -private: - CornerMap corner_map_; - CornerSeq corners_; - ParasiticAnalysisPtSeq parasitic_analysis_pts_; - DcalcAnalysisPtSeq dcalc_analysis_pts_; - PathAnalysisPtSeq path_analysis_pts_; -}; - -class Corner -{ -public: - Corner(const char *name, - int index); - const char *name() const { return name_.c_str(); } - int index() const { return index_; } - ParasiticAnalysisPt *findParasiticAnalysisPt(const MinMax *min_max) const; - int parasiticAnalysisPtcount(); - DcalcAnalysisPt *findDcalcAnalysisPt(const MinMax *min_max) const; - PathAnalysisPt *findPathAnalysisPt(const MinMax *min_max) const; - void addLiberty(LibertyLibrary *lib, - const MinMax *min_max); - const LibertySeq &libertyLibraries(const MinMax *min_max) const; - int libertyIndex(const MinMax *min_max) const; - -protected: - void setParasiticAnalysisPtcount(int ap_count); - void setParasiticAP(ParasiticAnalysisPt *path_ap, - int mm_index); - void setDcalcAnalysisPtcount(DcalcAPIndex ap_count); - void addDcalcAP(DcalcAnalysisPt *dcalc_ap); - void addPathAP(PathAnalysisPt *path_ap); - -private: - std::string name_; - int index_; - ParasiticAnalysisPtSeq parasitic_analysis_pts_; - DcalcAnalysisPtSeq dcalc_analysis_pts_; - PathAnalysisPtSeq path_analysis_pts_; - LibertySeq liberty_[MinMax::index_count]; - - friend class Corners; -}; - -} // namespace diff --git a/include/sta/CycleAccting.hh b/include/sta/CycleAccting.hh index 3cc5a045..867d620c 100644 --- a/include/sta/CycleAccting.hh +++ b/include/sta/CycleAccting.hh @@ -24,7 +24,8 @@ #pragma once -#include "UnorderedSet.hh" +#include + #include "MinMax.hh" #include "TimingRole.hh" #include "StaState.hh" @@ -42,17 +43,19 @@ class CycleAcctingEqual { public: bool operator()(const CycleAccting *acct1, - const CycleAccting *acct2) const; + const CycleAccting *acct2) const; }; class CycleAcctingLess { public: bool operator()(const CycleAccting *acct1, - const CycleAccting *acct2) const; + const CycleAccting *acct2) const; }; -typedef UnorderedSet CycleAcctingSet; +using CycleAcctingSet = std::unordered_set; class CycleAcctings { @@ -63,7 +66,7 @@ public: // Find the cycle accounting info for paths that start at src clock // edge and end at target clock edge. CycleAccting *cycleAccting(const ClockEdge *src, - const ClockEdge *tgt); + const ClockEdge *tgt); void reportClkToClkMaxCycleWarnings(Report *report); private: @@ -75,7 +78,7 @@ class CycleAccting { public: CycleAccting(const ClockEdge *src, - const ClockEdge *tgt); + const ClockEdge *tgt); // Fill in required times. void findDelays(StaState *sta); // Find delays when source clk edge is the default arrival clock edge @@ -92,26 +95,26 @@ public: private: void setHoldAccting(int src_cycle, - int tgt_cycle, - float delay, - float req); + int tgt_cycle, + float delay, + float req); void setAccting(const TimingRole *role, - int src_cycle, - int tgt_cycle, - float delay, - float req); + int src_cycle, + int tgt_cycle, + float delay, + float req); void setSetupAccting(int src_cycle, - int tgt_cycle, - float delay, - float req); + int tgt_cycle, + float delay, + float req); void setDefaultSetupAccting(int src_cycle, - int tgt_cycle, - float delay, - float req); + int tgt_cycle, + float delay, + float req); void setDefaultHoldAccting(int src_cycle, - int tgt_cycle, - float delay, - float req); + int tgt_cycle, + float delay, + float req); int firstCycle(const ClockEdge *clk_edge) const; const ClockEdge *src_; diff --git a/include/sta/DataCheck.hh b/include/sta/DataCheck.hh index 3e55f4a8..23ed758b 100644 --- a/include/sta/DataCheck.hh +++ b/include/sta/DataCheck.hh @@ -37,29 +37,29 @@ class DataCheck { public: DataCheck(Pin *from, - Pin *to, - Clock *clk); + Pin *to, + Clock *clk); Pin *from() const { return from_; } Pin *to() const { return to_; } Clock *clk() const { return clk_; } void margin(const RiseFall *from_rf, - const RiseFall *to_rf, - const SetupHold *setup_hold, - // Return values. - float &margin, - bool &exists) const; + const RiseFall *to_rf, + const SetupHold *setup_hold, + // Return values. + float &margin, + bool &exists) const; void setMargin(const RiseFallBoth *from_rf, - const RiseFallBoth *to_rf, - const SetupHoldAll *setup_hold, - float margin); + const RiseFallBoth *to_rf, + const SetupHoldAll *setup_hold, + float margin); void removeMargin(const RiseFallBoth *from_rf, - const RiseFallBoth *to_rf, - const SetupHoldAll *setup_hold); - bool empty() const; + const RiseFallBoth *to_rf, + const SetupHoldAll *setup_hold); + [[nodiscard]] bool empty() const; void marginIsOneValue(const SetupHold *setup_hold, - // Return values. - float &value, - bool &one_value) const; + // Return values. + float &value, + bool &one_value) const; private: Pin *from_; @@ -73,7 +73,7 @@ class DataCheckLess public: DataCheckLess(const Network *network); bool operator()(const DataCheck *check1, - const DataCheck *check2) const; + const DataCheck *check2) const; private: const Network *network_; diff --git a/include/sta/DcalcAnalysisPt.hh b/include/sta/DcalcAnalysisPt.hh deleted file mode 100644 index 76af5fe8..00000000 --- a/include/sta/DcalcAnalysisPt.hh +++ /dev/null @@ -1,81 +0,0 @@ -// OpenSTA, Static Timing Analyzer -// Copyright (c) 2025, Parallax Software, Inc. -// -// This program is free software: you can redistribute it and/or modify -// it under the terms of the GNU General Public License as published by -// the Free Software Foundation, either version 3 of the License, or -// (at your option) any later version. -// -// This program is distributed in the hope that it will be useful, -// but WITHOUT ANY WARRANTY; without even the implied warranty of -// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -// GNU General Public License for more details. -// -// You should have received a copy of the GNU General Public License -// along with this program. If not, see . -// -// The origin of this software must not be misrepresented; you must not -// claim that you wrote the original software. -// -// Altered source versions must be plainly marked as such, and must not be -// misrepresented as being the original software. -// -// This notice may not be removed or altered from any source distribution. - -#pragma once - -#include "Iterator.hh" -#include "MinMax.hh" -#include "LibertyClass.hh" -#include "SdcClass.hh" -#include "ParasiticsClass.hh" -#include "GraphClass.hh" -#include "StaState.hh" - -namespace sta { - -class Corner; - -// Delay calculation analysis point. -// This collects all of the parameters used to find one set of -// delay calculation results. -class DcalcAnalysisPt -{ -public: - DcalcAnalysisPt(Corner *corner, - DcalcAPIndex index, - const OperatingConditions *op_cond, - const MinMax *min_max, - const MinMax *check_clk_slew_min_max); - Corner *corner() const { return corner_; } - // Which of the delay_count results this analysis point corresponds to. - DcalcAPIndex index() const { return index_; } - // Slew index of timing check data. - DcalcAPIndex checkDataSlewIndex() const { return index_; } - // Slew index of timing check clock. - DcalcAPIndex checkClkSlewIndex() const { return check_clk_slew_index_; } - // Slew min/max of timing check clock. - const MinMax *checkClkSlewMinMax() const { return check_clk_slew_min_max_; } - // Constraint min/max values to use. - const MinMax *constraintMinMax() const { return min_max_; } - // Constraints::operatingCondition(cnst_min_max_) - const OperatingConditions *operatingConditions() const { return op_cond_; } - void setOperatingConditions(const OperatingConditions *op_cond); - // Delay merging min/max operator (for wires). - const MinMax *delayMinMax() const { return min_max_; } - // Merge min/max slews across timing arcs. - const MinMax *slewMinMax() const { return min_max_; } - ParasiticAnalysisPt *parasiticAnalysisPt() const; - void setCheckClkSlewIndex(DcalcAPIndex index); - int libertyIndex() const; - -private: - Corner *corner_; - DcalcAPIndex index_; - DcalcAPIndex check_clk_slew_index_; - const OperatingConditions *op_cond_; - const MinMax *min_max_; - const MinMax *check_clk_slew_min_max_; -}; - -} // namespace diff --git a/include/sta/Debug.hh b/include/sta/Debug.hh index 0f3923ae..4c958065 100644 --- a/include/sta/Debug.hh +++ b/include/sta/Debug.hh @@ -24,10 +24,11 @@ #pragma once +#include #include +#include #include -#include "Map.hh" #include "StringUtil.hh" namespace sta { @@ -35,18 +36,17 @@ namespace sta { class Report; class Pin; -typedef Map DebugMap; +using DebugMap = std::map; class Debug { public: - explicit Debug(Report *report); - ~Debug(); + Debug(Report *report); int level(const char *what); void setLevel(const char *what, - int level); + int level); bool check(const char *what, - int level) const; + int level) const; int statsLevel() const { return stats_level_; } void reportLine(const char *what, const char *fmt, @@ -57,18 +57,15 @@ protected: Report *report_; std::mutex buffer_lock_; bool debug_on_; - DebugMap *debug_map_; + DebugMap debug_map_; int stats_level_; }; // Inlining a varargs function would eval the args, which can // be expensive, so use a macro. -// Note that "##__VA_ARGS__" is a gcc extension to support zero arguments (no comma). -// clang -Wno-gnu-zero-variadic-macro-arguments suppresses the warning. -// c++20 has "__VA_OPT__" to deal with the zero arg case so this is temporary. #define debugPrint(debug, what, level, ...) \ if (debug->check(what, level)) { \ - debug->reportLine(what, ##__VA_ARGS__); \ + debug->reportLine(what __VA_OPT__(,) __VA_ARGS__); \ } } // namespace diff --git a/include/sta/Delay.hh b/include/sta/Delay.hh index 236158c9..1711f78e 100644 --- a/include/sta/Delay.hh +++ b/include/sta/Delay.hh @@ -41,10 +41,10 @@ namespace sta { -typedef Delay ArcDelay; -typedef Delay Slew; -typedef Delay Arrival; -typedef Delay Required; -typedef Delay Slack; +using ArcDelay = Delay; +using Slew = Delay; +using Arrival = Delay; +using Required = Delay; +using Slack = Delay; } // namespace diff --git a/include/sta/DelayCalc.hh b/include/sta/DelayCalc.hh index ff1c9629..dbadf0b6 100644 --- a/include/sta/DelayCalc.hh +++ b/include/sta/DelayCalc.hh @@ -31,7 +31,7 @@ namespace sta { class ArcDelayCalc; class StaState; -typedef ArcDelayCalc *(*MakeArcDelayCalc)(StaState *sta); +using MakeArcDelayCalc = ArcDelayCalc *(*)(StaState *sta); // Register builtin delay calculators. void @@ -39,7 +39,7 @@ registerDelayCalcs(); // Register a delay calculator for the set_delay_calc command. void registerDelayCalc(const char *name, - MakeArcDelayCalc maker); + MakeArcDelayCalc maker); bool isDelayCalcName(const char *name); StringSeq @@ -50,6 +50,6 @@ deleteDelayCalcs(); // Make a registered delay calculator by name. ArcDelayCalc * makeDelayCalc(const char *name, - StaState *sta); + StaState *sta); } // namespace diff --git a/include/sta/DelayFloat.hh b/include/sta/DelayFloat.hh index 88aeca96..a834bb57 100644 --- a/include/sta/DelayFloat.hh +++ b/include/sta/DelayFloat.hh @@ -32,9 +32,9 @@ namespace sta { class StaState; -typedef float Delay; +using Delay = float; // Delay double for accumulating Delays. -typedef double DelayDbl; +using DelayDbl = double; const Delay delay_zero = 0.0; @@ -43,29 +43,29 @@ initDelayConstants(); const char * delayAsString(const Delay &delay, - const StaState *sta); + const StaState *sta); const char * delayAsString(const Delay &delay, - const StaState *sta, - int digits); + const StaState *sta, + int digits); const char * delayAsString(const Delay &delay, - const EarlyLate *early_late, - const StaState *sta, - int digits); + const EarlyLate *early_late, + const StaState *sta, + int digits); inline Delay makeDelay(float delay, - float, - float) + float, + float) { return delay; } inline Delay makeDelay2(float delay, - float, - float) + float, + float) { return delay; } @@ -79,15 +79,15 @@ delayAsFloat(const Delay &delay) // mean late+/early- sigma inline float delayAsFloat(const Delay &delay, - const EarlyLate *, - const StaState *) + const EarlyLate *, + const StaState *) { return delay; } inline float delaySigma2(const Delay &, - const EarlyLate *) + const EarlyLate *) { return 0.0; } @@ -96,57 +96,57 @@ const Delay & delayInitValue(const MinMax *min_max); bool delayIsInitValue(const Delay &delay, - const MinMax *min_max); + const MinMax *min_max); bool delayZero(const Delay &delay); bool delayInf(const Delay &delay); bool delayEqual(const Delay &delay1, - const Delay &delay2); + const Delay &delay2); bool delayLess(const Delay &delay1, - const Delay &delay2, - const StaState *sta); + const Delay &delay2, + const StaState *sta); bool delayLess(const Delay &delay1, - const Delay &delay2, - const MinMax *min_max, - const StaState *sta); + const Delay &delay2, + const MinMax *min_max, + const StaState *sta); bool delayLessEqual(const Delay &delay1, - const Delay &delay2, - const StaState *sta); + const Delay &delay2, + const StaState *sta); bool delayLessEqual(const Delay &delay1, - const Delay &delay2, - const MinMax *min_max, - const StaState *sta); + const Delay &delay2, + const MinMax *min_max, + const StaState *sta); bool delayGreater(const Delay &delay1, - const Delay &delay2, - const StaState *sta); + const Delay &delay2, + const StaState *sta); bool delayGreaterEqual(const Delay &delay1, - const Delay &delay2, - const StaState *sta); + const Delay &delay2, + const StaState *sta); bool delayGreaterEqual(const Delay &delay1, - const Delay &delay2, - const MinMax *min_max, - const StaState *sta); + const Delay &delay2, + const MinMax *min_max, + const StaState *sta); bool delayGreater(const Delay &delay1, - const Delay &delay2, - const MinMax *min_max, - const StaState *sta); + const Delay &delay2, + const MinMax *min_max, + const StaState *sta); // delay1-delay2 subtracting sigma instead of addiing. Delay delayRemove(const Delay &delay1, - const Delay &delay2); + const Delay &delay2); float delayRatio(const Delay &delay1, - const Delay &delay2); + const Delay &delay2); } // namespace diff --git a/include/sta/DelayNormal1.hh b/include/sta/DelayNormal1.hh index e722bc4e..87beef23 100644 --- a/include/sta/DelayNormal1.hh +++ b/include/sta/DelayNormal1.hh @@ -41,7 +41,7 @@ public: Delay(const DelayDbl &delay); Delay(float mean); Delay(float mean, - float sigma2); + float sigma2); float mean() const { return mean_; } float sigma() const; // sigma^2 @@ -95,27 +95,27 @@ initDelayConstants(); const char * delayAsString(const Delay &delay, - const StaState *sta); + const StaState *sta); const char * delayAsString(const Delay &delay, - const StaState *sta, - int digits); + const StaState *sta, + int digits); const char * delayAsString(const Delay &delay, - const EarlyLate *early_late, - const StaState *sta, - int digits); + const EarlyLate *early_late, + const StaState *sta, + int digits); Delay makeDelay(float delay, - float sigma_early, - float sigma_late); + float sigma_early, + float sigma_late); Delay makeDelay2(float delay, - // sigma^2 - float sigma_early, - float sigma_late); + // sigma^2 + float sigma_early, + float sigma_late); inline float delayAsFloat(const Delay &delay) @@ -126,78 +126,78 @@ delayAsFloat(const Delay &delay) // mean late+/early- sigma float delayAsFloat(const Delay &delay, - const EarlyLate *early_late, - const StaState *sta); + const EarlyLate *early_late, + const StaState *sta); float delaySigma2(const Delay &delay, - const EarlyLate *early_late); + const EarlyLate *early_late); const Delay & delayInitValue(const MinMax *min_max); bool delayIsInitValue(const Delay &delay, - const MinMax *min_max); + const MinMax *min_max); bool delayZero(const Delay &delay); bool delayInf(const Delay &delay); bool delayEqual(const Delay &delay1, - const Delay &delay2); + const Delay &delay2); bool delayLess(const Delay &delay1, - const Delay &delay2, - const StaState *sta); + const Delay &delay2, + const StaState *sta); bool delayLess(const Delay &delay1, - const Delay &delay2, - const MinMax *min_max, - const StaState *sta); + const Delay &delay2, + const MinMax *min_max, + const StaState *sta); bool delayLessEqual(const Delay &delay1, - const Delay &delay2, - const StaState *sta); + const Delay &delay2, + const StaState *sta); bool delayLessEqual(const Delay &delay1, - const Delay &delay2, - const MinMax *min_max, - const StaState *sta); + const Delay &delay2, + const MinMax *min_max, + const StaState *sta); bool delayGreater(const Delay &delay1, - const Delay &delay2, - const StaState *sta); + const Delay &delay2, + const StaState *sta); bool delayGreaterEqual(const Delay &delay1, - const Delay &delay2, - const StaState *sta); + const Delay &delay2, + const StaState *sta); bool delayGreaterEqual(const Delay &delay1, - const Delay &delay2, - const MinMax *min_max, - const StaState *sta); + const Delay &delay2, + const MinMax *min_max, + const StaState *sta); bool delayGreater(const Delay &delay1, - const Delay &delay2, - const MinMax *min_max, - const StaState *sta); + const Delay &delay2, + const MinMax *min_max, + const StaState *sta); // delay1-delay2 subtracting sigma instead of addiing. Delay delayRemove(const Delay &delay1, - const Delay &delay2); + const Delay &delay2); float delayRatio(const Delay &delay1, - const Delay &delay2); + const Delay &delay2); // Most non-operator functions on Delay are not defined as member // functions so they can be defined on floats, where there is no class // to define them. Delay operator+(float delay1, - const Delay &delay2); + const Delay &delay2); // Used for parallel gate delay calc. Delay operator/(float delay1, - const Delay &delay2); + const Delay &delay2); // Used for parallel gate delay calc. Delay operator*(const Delay &delay1, - float delay2); + float delay2); } // namespace diff --git a/include/sta/DelayNormal2.hh b/include/sta/DelayNormal2.hh index 10e7a965..f19a6411 100644 --- a/include/sta/DelayNormal2.hh +++ b/include/sta/DelayNormal2.hh @@ -41,8 +41,8 @@ public: Delay(const DelayDbl &delay); Delay(float mean); Delay(float mean, - float sigma2_early, - float sigma2_late); + float sigma2_early, + float sigma2_late); float mean() const { return mean_; } float sigma(const EarlyLate *early_late) const; // sigma^2 @@ -106,27 +106,27 @@ initDelayConstants(); const char * delayAsString(const Delay &delay, - const StaState *sta); + const StaState *sta); const char * delayAsString(const Delay &delay, - const StaState *sta, - int digits); + const StaState *sta, + int digits); const char * delayAsString(const Delay &delay, - const EarlyLate *early_late, - const StaState *sta, - int digits); + const EarlyLate *early_late, + const StaState *sta, + int digits); Delay makeDelay(float delay, - float sigma_early, - float sigma_late); + float sigma_early, + float sigma_late); Delay makeDelay2(float delay, - // sigma^2 - float sigma_early, - float sigma_late); + // sigma^2 + float sigma_early, + float sigma_late); inline float delayAsFloat(const Delay &delay) @@ -137,78 +137,78 @@ delayAsFloat(const Delay &delay) // mean late+/early- sigma float delayAsFloat(const Delay &delay, - const EarlyLate *early_late, - const StaState *sta); + const EarlyLate *early_late, + const StaState *sta); float delaySigma2(const Delay &delay, - const EarlyLate *early_late); + const EarlyLate *early_late); const Delay & delayInitValue(const MinMax *min_max); bool delayIsInitValue(const Delay &delay, - const MinMax *min_max); + const MinMax *min_max); bool delayZero(const Delay &delay); bool delayInf(const Delay &delay); bool delayEqual(const Delay &delay1, - const Delay &delay2); + const Delay &delay2); bool delayLess(const Delay &delay1, - const Delay &delay2, - const StaState *sta); + const Delay &delay2, + const StaState *sta); bool delayLess(const Delay &delay1, - const Delay &delay2, - const MinMax *min_max, - const StaState *sta); + const Delay &delay2, + const MinMax *min_max, + const StaState *sta); bool delayLessEqual(const Delay &delay1, - const Delay &delay2, - const StaState *sta); + const Delay &delay2, + const StaState *sta); bool delayLessEqual(const Delay &delay1, - const Delay &delay2, - const MinMax *min_max, - const StaState *sta); + const Delay &delay2, + const MinMax *min_max, + const StaState *sta); bool delayGreater(const Delay &delay1, - const Delay &delay2, - const StaState *sta); + const Delay &delay2, + const StaState *sta); bool delayGreaterEqual(const Delay &delay1, - const Delay &delay2, - const StaState *sta); + const Delay &delay2, + const StaState *sta); bool delayGreaterEqual(const Delay &delay1, - const Delay &delay2, - const MinMax *min_max, - const StaState *sta); + const Delay &delay2, + const MinMax *min_max, + const StaState *sta); bool delayGreater(const Delay &delay1, - const Delay &delay2, - const MinMax *min_max, - const StaState *sta); + const Delay &delay2, + const MinMax *min_max, + const StaState *sta); // delay1-delay2 subtracting sigma instead of addiing. Delay delayRemove(const Delay &delay1, - const Delay &delay2); + const Delay &delay2); float delayRatio(const Delay &delay1, - const Delay &delay2); + const Delay &delay2); // Most non-operator functions on Delay are not defined as member // functions so they can be defined on floats, where there is no class // to define them. Delay operator+(float delay1, - const Delay &delay2); + const Delay &delay2); // Used for parallel gate delay calc. Delay operator/(float delay1, - const Delay &delay2); + const Delay &delay2); // Used for parallel gate delay calc. Delay operator*(const Delay &delay1, - float delay2); + float delay2); } // namespace diff --git a/include/sta/DeratingFactors.hh b/include/sta/DeratingFactors.hh index aa4808a0..dcc6b344 100644 --- a/include/sta/DeratingFactors.hh +++ b/include/sta/DeratingFactors.hh @@ -36,22 +36,22 @@ class DeratingFactors public: DeratingFactors(); void setFactor(PathClkOrData clk_data, - const RiseFallBoth *rf, - const EarlyLate *early_late, - float factor); + const RiseFallBoth *rf, + const EarlyLate *early_late, + float factor); void factor(PathClkOrData clk_data, - const RiseFall *rf, - const EarlyLate *early_late, - float &factor, - bool &exists) const; + const RiseFall *rf, + const EarlyLate *early_late, + float &factor, + bool &exists) const; void clear(); void isOneValue(const EarlyLate *early_late, - bool &is_one_value, - float &value) const; + bool &is_one_value, + float &value) const; void isOneValue(PathClkOrData clk_data, - const EarlyLate *early_late, - bool &is_one_value, - float &value) const; + const EarlyLate *early_late, + bool &is_one_value, + float &value) const; bool hasValue() const; private: @@ -63,22 +63,22 @@ class DeratingFactorsGlobal public: DeratingFactorsGlobal(); void setFactor(TimingDerateType type, - PathClkOrData clk_data, - const RiseFallBoth *rf, - const EarlyLate *early_late, - float factor); + PathClkOrData clk_data, + const RiseFallBoth *rf, + const EarlyLate *early_late, + float factor); void factor(TimingDerateType type, - PathClkOrData clk_data, - const RiseFall *rf, - const EarlyLate *early_late, - float &factor, - bool &exists) const; + PathClkOrData clk_data, + const RiseFall *rf, + const EarlyLate *early_late, + float &factor, + bool &exists) const; void factor(TimingDerateCellType type, - PathClkOrData clk_data, - const RiseFall *rf, - const EarlyLate *early_late, - float &factor, - bool &exists) const; + PathClkOrData clk_data, + const RiseFall *rf, + const EarlyLate *early_late, + float &factor, + bool &exists) const; DeratingFactors *factors(TimingDerateType type); void clear(); @@ -91,21 +91,21 @@ class DeratingFactorsCell public: DeratingFactorsCell(); void setFactor(TimingDerateCellType type, - PathClkOrData clk_data, - const RiseFallBoth *rf, - const EarlyLate *early_late, - float factor); + PathClkOrData clk_data, + const RiseFallBoth *rf, + const EarlyLate *early_late, + float factor); void factor(TimingDerateCellType type, - PathClkOrData clk_data, - const RiseFall *rf, - const EarlyLate *early_late, - float &factor, - bool &exists) const; + PathClkOrData clk_data, + const RiseFall *rf, + const EarlyLate *early_late, + float &factor, + bool &exists) const; DeratingFactors *factors(TimingDerateCellType type); void clear(); void isOneValue(const EarlyLate *early_late, - bool &is_one_value, - float &value) const; + bool &is_one_value, + float &value) const; private: DeratingFactors factors_[timing_derate_cell_type_count]; diff --git a/include/sta/DisabledPorts.hh b/include/sta/DisabledPorts.hh index 6168247c..d41661d4 100644 --- a/include/sta/DisabledPorts.hh +++ b/include/sta/DisabledPorts.hh @@ -24,7 +24,9 @@ #pragma once -#include "Map.hh" +#include +#include + #include "NetworkClass.hh" #include "LibertyClass.hh" #include "SdcClass.hh" @@ -35,10 +37,10 @@ class TimingRole; class DisabledCellPorts; class DisabledInstancePorts; -typedef Vector DisabledInstancePortsSeq; -typedef Vector DisabledCellPortsSeq; -typedef Vector LibertyPortPairSeq; -typedef Set TimingArcSetSet; +using DisabledInstancePortsSeq = std::vector; +using DisabledCellPortsSeq = std::vector; +using LibertyPortPairSeq = std::vector; +using TimingArcSetSet = std::set; // Base class for disabled cell and instance ports. class DisabledPorts @@ -56,13 +58,13 @@ public: LibertyPort *to); void removeDisabledFromTo(LibertyPort *from, LibertyPort *to); - bool isDisabled(LibertyPort *from, - LibertyPort *to, - const TimingRole *role); + [[nodiscard]] bool isDisabled(LibertyPort *from, + LibertyPort *to, + const TimingRole *role); LibertyPortPairSet *fromTo() const { return from_to_; } LibertyPortSet *from() const { return from_; } LibertyPortSet *to() const { return to_; } - bool all() const { return all_; } + [[nodiscard]] bool all() const { return all_; } private: bool all_; @@ -80,7 +82,7 @@ public: LibertyCell *cell() const { return cell_; } void setDisabled(TimingArcSet *arc_set); void removeDisabled(TimingArcSet *arc_set); - bool isDisabled(TimingArcSet *arc_set) const; + [[nodiscard]] bool isDisabled(TimingArcSet *arc_set) const; TimingArcSetSet *timingArcSets() const { return arc_sets_; } using DisabledPorts::isDisabled; @@ -102,7 +104,7 @@ private: }; DisabledCellPortsSeq -sortByName(DisabledCellPortsMap *cell_map); +sortByName(const DisabledCellPortsMap *cell_map); DisabledInstancePortsSeq sortByPathName(const DisabledInstancePortsMap *inst_map, const Network *network); diff --git a/include/sta/EnumNameMap.hh b/include/sta/EnumNameMap.hh index d7c60c38..50ef13e6 100644 --- a/include/sta/EnumNameMap.hh +++ b/include/sta/EnumNameMap.hh @@ -37,11 +37,11 @@ public: EnumNameMap(std::initializer_list> enum_names); const char *find(ENUM key) const; ENUM find(std::string name, - ENUM unknown_key) const; + ENUM unknown_key) const; void find(std::string name, - // Return values. - ENUM &key, - bool &exists) const; + // Return values. + ENUM &key, + bool &exists) const; private: std::map enum_map_; @@ -70,9 +70,9 @@ EnumNameMap::find(ENUM key) const template void EnumNameMap::find(std::string name, - // Return values. - ENUM &key, - bool &exists) const + // Return values. + ENUM &key, + bool &exists) const { auto find_iter = name_map_.find(name); if (find_iter != name_map_.end()) { @@ -86,7 +86,7 @@ EnumNameMap::find(std::string name, template ENUM EnumNameMap::find(std::string name, - ENUM unknown_key) const + ENUM unknown_key) const { auto find_iter = name_map_.find(name); if (find_iter != name_map_.end()) diff --git a/include/sta/EquivCells.hh b/include/sta/EquivCells.hh index 4a337b0c..3ceadeb7 100644 --- a/include/sta/EquivCells.hh +++ b/include/sta/EquivCells.hh @@ -24,15 +24,15 @@ #pragma once -#include "Vector.hh" -#include "Map.hh" -#include "UnorderedMap.hh" +#include +#include + #include "LibertyClass.hh" namespace sta { -typedef Map EquivCellMap; -typedef UnorderedMap LibertyCellHashMap; +using EquivCellMap = std::map; +using LibertyCellHashMap = std::unordered_map; class EquivCells { @@ -40,16 +40,16 @@ public: // Find equivalent cells in equiv_libs. // Optionally add mappings for cells in map_libs. EquivCells(LibertyLibrarySeq *equiv_libs, - LibertyLibrarySeq *map_libs); + LibertyLibrarySeq *map_libs); ~EquivCells(); // Find equivalents for cell (member of from_libs) in to_libs. LibertyCellSeq *equivs(LibertyCell *cell); protected: void findEquivCells(const LibertyLibrary *library, - LibertyCellHashMap &hash_matches); + LibertyCellHashMap &hash_matches); void mapEquivCells(const LibertyLibrary *library, - LibertyCellHashMap &hash_matches); + LibertyCellHashMap &hash_matches); EquivCellMap equiv_cells_; // Unique cell for each equiv cell group. @@ -60,7 +60,7 @@ protected: // functions or timing arcs match. bool equivCells(const LibertyCell *cell1, - const LibertyCell *cell2); + const LibertyCell *cell2); // Predicate that is true when the ports, functions, sequentials and // timing arcs match. @@ -71,7 +71,7 @@ equivCellsArcs(const LibertyCell *cell1, // Predicate that is true when the ports match. bool equivCellPorts(const LibertyCell *cell1, - const LibertyCell *cell2); + const LibertyCell *cell2); // Predicate that is true cell functions match. bool @@ -81,10 +81,10 @@ equivCellFuncs(const LibertyCell *cell1, // Predicate that is true when the timing arc sets match. bool equivCellTimingArcSets(const LibertyCell *cell1, - const LibertyCell *cell2); + const LibertyCell *cell2); bool equivCellSequentials(const LibertyCell *cell1, - const LibertyCell *cell2); + const LibertyCell *cell2); } // namespace diff --git a/include/sta/Error.hh b/include/sta/Error.hh index e5dc3b8f..2230f45f 100644 --- a/include/sta/Error.hh +++ b/include/sta/Error.hh @@ -56,7 +56,7 @@ class ExceptionLine : public Exception { public: ExceptionLine(const char *filename, - int line); + int line); protected: const char *filename_; @@ -67,7 +67,7 @@ protected: class FileNotReadable : public Exception { public: - explicit FileNotReadable(const char *filename); + FileNotReadable(const char *filename); virtual const char *what() const noexcept; protected: @@ -78,7 +78,7 @@ protected: class FileNotWritable : public Exception { public: - explicit FileNotWritable(const char *filename); + FileNotWritable(const char *filename); virtual const char *what() const noexcept; protected: diff --git a/include/sta/ExceptionPath.hh b/include/sta/ExceptionPath.hh index c1c09978..f5b89f14 100644 --- a/include/sta/ExceptionPath.hh +++ b/include/sta/ExceptionPath.hh @@ -24,8 +24,9 @@ #pragma once +#include + #include "Error.hh" -#include "Set.hh" #include "SdcCmdComment.hh" #include "SdcClass.hh" @@ -44,18 +45,18 @@ class ExceptionThru; class ExceptionTo; class ExceptionState; -typedef Vector ExceptionPathSeq; +using ExceptionPathSeq = std::vector; class ExceptionPath : public SdcCmdComment { public: ExceptionPath(ExceptionFrom *from, - ExceptionThruSeq *thrus, - ExceptionTo *to, - const MinMaxAll *min_max, - bool own_pts, - int priority, - const char *comment); + ExceptionThruSeq *thrus, + ExceptionTo *to, + const MinMaxAll *min_max, + bool own_pts, + int priority, + const char *comment); virtual ~ExceptionPath(); size_t id() const { return id_; } void setId(size_t id); @@ -75,14 +76,14 @@ public: const Network *network) const; const MinMaxAll *minMax() const { return min_max_; } virtual bool matches(const MinMax *min_max, - bool exact) const; + bool exact) const; bool matchesFirstPt(const RiseFall *to_rf, - const MinMax *min_max); + const MinMax *min_max); ExceptionState *firstState(); virtual bool resetMatch(ExceptionFrom *from, - ExceptionThruSeq *thrus, - ExceptionTo *to, - const MinMaxAll *min_max, + ExceptionThruSeq *thrus, + ExceptionTo *to, + const MinMaxAll *min_max, const Network *network); // The priority remains the same even though pin/clock/net/inst objects // are added to the exceptions points during exception merging because @@ -103,22 +104,22 @@ public: // they cannot be coded into the priority. virtual bool tighterThan(ExceptionPath *exception) const = 0; static int fromThruToPriority(ExceptionFrom *from, - ExceptionThruSeq *thrus, - ExceptionTo *to); + ExceptionThruSeq *thrus, + ExceptionTo *to); size_t hash() const; size_t hash(ExceptionPt *missing_pt) const; // Mergeable properties (independent of exception points). virtual bool mergeable(ExceptionPath *exception) const; bool mergeablePts(ExceptionPath *exception) const; bool mergeablePts(ExceptionPath *exception2, - ExceptionPt *missing_pt2, - ExceptionPt *&missing_pt) const; + ExceptionPt *missing_pt2, + ExceptionPt *&missing_pt) const; // Overrides properties (independent of exception points). virtual bool overrides(ExceptionPath *exception) const = 0; virtual ExceptionPath *clone(ExceptionFrom *from, - ExceptionThruSeq *thrus, - ExceptionTo *to, - bool own_pts) = 0; + ExceptionThruSeq *thrus, + ExceptionTo *to, + bool own_pts) = 0; void deleteInstance(const Instance *inst, const Network *network); @@ -151,22 +152,22 @@ class FalsePath : public ExceptionPath { public: FalsePath(ExceptionFrom *from, - ExceptionThruSeq *thrus, - ExceptionTo *to, - const MinMaxAll *min_max, - bool own_pts, - const char *comment); + ExceptionThruSeq *thrus, + ExceptionTo *to, + const MinMaxAll *min_max, + bool own_pts, + const char *comment); FalsePath(ExceptionFrom *from, - ExceptionThruSeq *thrus, - ExceptionTo *to, - const MinMaxAll *min_max, - bool own_pts, - int priority, - const char *comment); + ExceptionThruSeq *thrus, + ExceptionTo *to, + const MinMaxAll *min_max, + bool own_pts, + int priority, + const char *comment); virtual ExceptionPath *clone(ExceptionFrom *from, - ExceptionThruSeq *thrus, - ExceptionTo *to, - bool own_pts); + ExceptionThruSeq *thrus, + ExceptionTo *to, + bool own_pts); virtual bool isFalse() const { return true; } virtual ExceptionPathType type() const { return ExceptionPathType::false_path; } virtual const char *typeString() const; @@ -182,7 +183,7 @@ class LoopPath : public FalsePath { public: LoopPath(ExceptionThruSeq *thrus, - bool own_pts); + bool own_pts); virtual bool isLoop() const { return true; } virtual ExceptionPathType type() const { return ExceptionPathType::loop; } virtual const char *typeString() const; @@ -194,18 +195,18 @@ class PathDelay : public ExceptionPath { public: PathDelay(ExceptionFrom *from, - ExceptionThruSeq *thrus, - ExceptionTo *to, - const MinMax *min_max, - bool ignore_clk_latency, + ExceptionThruSeq *thrus, + ExceptionTo *to, + const MinMax *min_max, + bool ignore_clk_latency, bool break_path, - float delay, - bool own_pts, - const char *comment); + float delay, + bool own_pts, + const char *comment); virtual ExceptionPath *clone(ExceptionFrom *from, - ExceptionThruSeq *thrus, - ExceptionTo *to, - bool own_pts); + ExceptionThruSeq *thrus, + ExceptionTo *to, + bool own_pts); virtual bool isPathDelay() const { return true; } virtual ExceptionPathType type() const { return ExceptionPathType::path_delay; } virtual const char *asString(const Network *network) const; @@ -229,21 +230,21 @@ class MultiCyclePath : public ExceptionPath { public: MultiCyclePath(ExceptionFrom *from, - ExceptionThruSeq *thrus, - ExceptionTo *to, - const MinMaxAll *min_max, - bool use_end_clk, - int path_multiplier, - bool own_pts, - const char *comment); + ExceptionThruSeq *thrus, + ExceptionTo *to, + const MinMaxAll *min_max, + bool use_end_clk, + int path_multiplier, + bool own_pts, + const char *comment); virtual ExceptionPath *clone(ExceptionFrom *from, - ExceptionThruSeq *thrus, - ExceptionTo *to, - bool own_pts); + ExceptionThruSeq *thrus, + ExceptionTo *to, + bool own_pts); virtual bool isMultiCycle() const { return true; } virtual ExceptionPathType type() const { return ExceptionPathType::multi_cycle; } virtual bool matches(const MinMax *min_max, - bool exactly) const; + bool exactly) const; virtual const char *asString(const Network *network) const; virtual const char *typeString() const; virtual bool mergeable(ExceptionPath *exception) const; @@ -267,22 +268,22 @@ class FilterPath : public ExceptionPath { public: FilterPath(ExceptionFrom *from, - ExceptionThruSeq *thrus, - ExceptionTo *to, - bool own_pts); + ExceptionThruSeq *thrus, + ExceptionTo *to, + bool own_pts); virtual ExceptionPath *clone(ExceptionFrom *from, - ExceptionThruSeq *thrus, - ExceptionTo *to, - bool own_pts); + ExceptionThruSeq *thrus, + ExceptionTo *to, + bool own_pts); virtual bool isFilter() const { return true; } virtual ExceptionPathType type() const { return ExceptionPathType::filter; } virtual const char *typeString() const; virtual bool mergeable(ExceptionPath *exception) const; virtual bool overrides(ExceptionPath *exception) const; virtual bool resetMatch(ExceptionFrom *from, - ExceptionThruSeq *thrus, - ExceptionTo *to, - const MinMaxAll *min_max, + ExceptionThruSeq *thrus, + ExceptionTo *to, + const MinMaxAll *min_max, const Network *network); virtual int typePriority() const; virtual bool tighterThan(ExceptionPath *exception) const; @@ -292,17 +293,17 @@ class GroupPath : public ExceptionPath { public: GroupPath(const char *name, - bool is_default, - ExceptionFrom *from, - ExceptionThruSeq *thrus, - ExceptionTo *to, - bool own_pts, - const char *comment); + bool is_default, + ExceptionFrom *from, + ExceptionThruSeq *thrus, + ExceptionTo *to, + bool own_pts, + const char *comment); virtual ~GroupPath(); virtual ExceptionPath *clone(ExceptionFrom *from, - ExceptionThruSeq *thrus, - ExceptionTo *to, - bool own_pts); + ExceptionThruSeq *thrus, + ExceptionTo *to, + bool own_pts); virtual bool isGroupPath() const { return true; } virtual ExceptionPathType type() const { return ExceptionPathType::group_path; } virtual const char *typeString() const; @@ -323,7 +324,7 @@ class ExceptionPt { public: ExceptionPt(const RiseFallBoth *rf, - bool own_pts); + bool own_pts); virtual ~ExceptionPt() {}; virtual bool isFrom() const { return false; } virtual bool isThru() const { return false; } @@ -379,9 +380,9 @@ class ExceptionFromTo : public ExceptionPt public: ExceptionFromTo(PinSet *pins, ClockSet *clks, - InstanceSet *insts, - const RiseFallBoth *rf, - bool own_pts, + InstanceSet *insts, + const RiseFallBoth *rf, + bool own_pts, const Network *network); ~ExceptionFromTo(); virtual PinSet *pins() { return pins_; } @@ -398,7 +399,7 @@ public: virtual PinSet allPins(const Network *network); bool equal(ExceptionFromTo *from_to) const; virtual int compare(ExceptionPt *pt, - const Network *network) const; + const Network *network) const; virtual void mergeInto(ExceptionPt *pt, const Network *network); virtual const char *asString(const Network *network) const; @@ -436,10 +437,10 @@ class ExceptionFrom : public ExceptionFromTo { public: ExceptionFrom(PinSet *pins, - ClockSet *clks, - InstanceSet *insts, - const RiseFallBoth *rf, - bool own_pts, + ClockSet *clks, + InstanceSet *insts, + const RiseFallBoth *rf, + bool own_pts, const Network *network); ExceptionFrom *clone(const Network *network); virtual bool isFrom() const { return true; } @@ -456,13 +457,13 @@ class ExceptionTo : public ExceptionFromTo { public: ExceptionTo(PinSet *pins, - ClockSet *clks, - InstanceSet *insts, - // -to|-rise_to|-fall_to - const RiseFallBoth *rf, - // -rise|-fall endpoint transition. - const RiseFallBoth *end_rf, - bool own_pts, + ClockSet *clks, + InstanceSet *insts, + // -to|-rise_to|-fall_to + const RiseFallBoth *rf, + // -rise|-fall endpoint transition. + const RiseFallBoth *end_rf, + bool own_pts, const Network *network); ExceptionTo *clone(const Network *network); virtual bool isTo() const { return true; } @@ -472,28 +473,28 @@ public: const Network *network) const; virtual int typePriority() const { return 1; } bool matches(const Pin *pin, - const ClockEdge *clk_edge, - const RiseFall *end_rf, - const Network *network) const; + const ClockEdge *clk_edge, + const RiseFall *end_rf, + const Network *network) const; bool matches(const Pin *pin, - const RiseFall *end_rf) const; + const RiseFall *end_rf) const; bool matches(const Clock *clk) const; bool matches(const Pin *pin, const RiseFall *end_rf, const Network *network) const; bool matchesFilter(const Pin *pin, - const ClockEdge *clk_edge, - const RiseFall *end_rf, - const Network *network) const; + const ClockEdge *clk_edge, + const RiseFall *end_rf, + const Network *network) const; virtual int compare(ExceptionPt *pt, const Network *network) const; protected: bool matches(const Pin *pin, - const ClockEdge *clk_edge, - const RiseFall *end_rf, - bool inst_matches_reg_clk_pin, - const Network *network) const; + const ClockEdge *clk_edge, + const RiseFall *end_rf, + bool inst_matches_reg_clk_pin, + const Network *network) const; virtual const char *cmdKeyword() const; // -rise|-fall endpoint transition. @@ -504,11 +505,11 @@ class ExceptionThru : public ExceptionPt { public: ExceptionThru(PinSet *pins, - NetSet *nets, - InstanceSet *insts, - const RiseFallBoth *rf, - bool own_pts, - const Network *network); + NetSet *nets, + InstanceSet *insts, + const RiseFallBoth *rf, + bool own_pts, + const Network *network); ~ExceptionThru(); ExceptionThru *clone(const Network *network); virtual const char *asString(const Network *network) const; @@ -523,12 +524,12 @@ public: const Network *network); virtual PinSet allPins(const Network *network); bool matches(const Pin *from_pin, - const Pin *to_pin, - const RiseFall *to_rf, - const Network *network); + const Pin *to_pin, + const RiseFall *to_rf, + const Network *network); bool equal(ExceptionThru *thru) const; virtual int compare(ExceptionPt *pt, - const Network *network) const; + const Network *network) const; virtual void mergeInto(ExceptionPt *pt, const Network *network); bool intersectsPts(ExceptionThru *thru, @@ -563,19 +564,19 @@ protected: void makeNetEdges(const Network *network); void makeInstEdges(const Network *network); void makeHpinEdges(const Pin *pin, - const Network *network); + const Network *network); void makePinEdges(const Pin *pin, - const Network *network); + const Network *network); void makeNetEdges(const Net *net, - const Network *network); + const Network *network); void makeInstEdges(Instance *inst, - Network *network); + Network *network); void deletePinEdges(const Pin *pin, - Network *network); + Network *network); void deleteNetEdges(Net *net, - const Network *network); + const Network *network); void deleteInstEdges(Instance *inst, - Network *network); + Network *network); // Leaf/port pins. PinSet *pins_; @@ -587,20 +588,20 @@ protected: ExceptionThruSeq * exceptionThrusClone(ExceptionThruSeq *thrus, - const Network *network); + const Network *network); // Iterate uniformly across exception from/thru/to's. class ExceptionPtIterator { public: - explicit ExceptionPtIterator(const ExceptionPath *exception); + ExceptionPtIterator(const ExceptionPath *exception); bool hasNext(); ExceptionPt *next(); private: const ExceptionPath *exception_; bool from_done_; - ExceptionThruSeq::Iterator thru_iter_; + ExceptionThruSeq::iterator thru_iter_; bool to_done_; }; @@ -616,13 +617,13 @@ class ExpandedExceptionVisitor { public: ExpandedExceptionVisitor(ExceptionPath *exception, - const Network *network); + const Network *network); virtual ~ExpandedExceptionVisitor() {} void visitExpansions(); // From/thrus/to have a single exception point (pin/instance/net/clock). virtual void visit(ExceptionFrom *from, - ExceptionThruSeq *thrus, - ExceptionTo *to) = 0; + ExceptionThruSeq *thrus, + ExceptionTo *to) = 0; protected: ExceptionPath *exception_; @@ -632,10 +633,10 @@ private: void expandFrom(); void expandThrus(ExceptionFrom *expanded_from); void expandThru(ExceptionFrom *expanded_from, - size_t next_thru_idx, - ExceptionThruSeq *expanded_thrus); + size_t next_thru_idx, + ExceptionThruSeq *expanded_thrus); void expandTo(ExceptionFrom *expanded_from, - ExceptionThruSeq *expanded_thrus); + ExceptionThruSeq *expanded_thrus); }; // States used by tags to know what exception points have been seen @@ -644,15 +645,15 @@ class ExceptionState { public: ExceptionState(ExceptionPath *exception, - ExceptionThru *next_thru, - int index); + ExceptionThru *next_thru, + int index); ExceptionPath *exception() { return exception_; } const ExceptionPath *exception() const { return exception_; } bool matchesNextThru(const Pin *from_pin, - const Pin *to_pin, - const RiseFall *to_rf, - const MinMax *min_max, - const Network *network) const; + const Pin *to_pin, + const RiseFall *to_rf, + const MinMax *min_max, + const Network *network) const; bool isComplete() const; ExceptionThru *nextThru() const { return next_thru_; } ExceptionState *nextState() const { return next_state_; } @@ -667,9 +668,9 @@ private: int index_; }; -bool -exceptionStateLess(const ExceptionState *state1, - const ExceptionState *state2); +int +exceptionStateCmp(const ExceptionState *state1, + const ExceptionState *state2); // Exception thrown by check. class EmptyExpceptionPt : public Exception @@ -683,7 +684,7 @@ class ExceptionPathLess public: ExceptionPathLess(const Network *network); bool operator()(const ExceptionPath *except1, - const ExceptionPath *except2) const; + const ExceptionPath *except2) const; private: const Network *network_; @@ -692,7 +693,7 @@ private: // Throws EmptyExpceptionPt it finds an empty exception point. void checkFromThrusTo(ExceptionFrom *from, - ExceptionThruSeq *thrus, - ExceptionTo *to); + ExceptionThruSeq *thrus, + ExceptionTo *to); } // namespace diff --git a/include/sta/FuncExpr.hh b/include/sta/FuncExpr.hh index ae7a0bc1..3f537f52 100644 --- a/include/sta/FuncExpr.hh +++ b/include/sta/FuncExpr.hh @@ -26,7 +26,6 @@ #include -#include "Set.hh" #include "NetworkClass.hh" #include "LibertyClass.hh" @@ -35,46 +34,47 @@ namespace sta { class FuncExpr { public: - enum Operator {op_port, - op_not, - op_or, - op_and, - op_xor, - op_one, - op_zero}; + enum class Op {port, + not_, + or_, + and_, + xor_, + one, + zero}; // Constructors. - FuncExpr(Operator op, - FuncExpr *left, - FuncExpr *right, - LibertyPort *port); + FuncExpr(Op op, + FuncExpr *left, + FuncExpr *right, + LibertyPort *port); static FuncExpr *makePort(LibertyPort *port); static FuncExpr *makeNot(FuncExpr *expr); static FuncExpr *makeAnd(FuncExpr *left, - FuncExpr *right); + FuncExpr *right); static FuncExpr *makeOr(FuncExpr *left, - FuncExpr *right); + FuncExpr *right); static FuncExpr *makeXor(FuncExpr *left, - FuncExpr *right); + FuncExpr *right); static FuncExpr *makeZero(); static FuncExpr *makeOne(); static bool equiv(const FuncExpr *expr1, - const FuncExpr *expr2); + const FuncExpr *expr2); static bool less(const FuncExpr *expr1, - const FuncExpr *expr2); + const FuncExpr *expr2); // Deep copy. FuncExpr *copy(); // Delete expression and all of its subexpressions. void deleteSubexprs(); - // op == op_port + // op == port LibertyPort *port() const; - Operator op() const { return op_; } + Op op() const { return op_; } // When operator is NOT left is the only operand. FuncExpr *left() const { return left_; } - // nullptr when op == op_not + // nullptr when op == not_ FuncExpr *right() const { return right_; } TimingSense portTimingSense(const LibertyPort *port) const; + LibertyPortSet ports() const; // Return true if expression has port as an input. bool hasPort(const LibertyPort *port) const; std::string to_string() const; @@ -86,11 +86,14 @@ public: bool checkSize(LibertyPort *port); private: + void findPorts(const FuncExpr *expr, + LibertyPortSet &ports) const; + std::string to_string(bool with_parens) const; std::string to_string(bool with_parens, char op) const; - Operator op_; + Op op_; FuncExpr *left_; FuncExpr *right_; LibertyPort *port_; @@ -100,18 +103,4 @@ private: FuncExpr * funcExprNot(FuncExpr *expr); -class FuncExprPortIterator : public Iterator -{ -public: - explicit FuncExprPortIterator(const FuncExpr *expr); - virtual bool hasNext() { return iter_.hasNext(); } - virtual LibertyPort *next() { return iter_.next(); } - -private: - void findPorts(const FuncExpr *expr); - - LibertyPortSet ports_; - LibertyPortSet::ConstIterator iter_; -}; - } // namespace diff --git a/include/sta/Fuzzy.hh b/include/sta/Fuzzy.hh index ac4280f0..0ae490aa 100644 --- a/include/sta/Fuzzy.hh +++ b/include/sta/Fuzzy.hh @@ -30,21 +30,21 @@ namespace sta { bool fuzzyEqual(float v1, - float v2); + float v2); bool fuzzyZero(float v); bool fuzzyLess(float v1, - float v2); + float v2); bool fuzzyLessEqual(float v1, - float v2); + float v2); bool fuzzyGreater(float v1, - float v2); + float v2); bool fuzzyGreaterEqual(float v1, - float v2); + float v2); bool fuzzyInf(float value); diff --git a/include/sta/Graph.hh b/include/sta/Graph.hh index 6bf86cfe..28625854 100644 --- a/include/sta/Graph.hh +++ b/include/sta/Graph.hh @@ -26,10 +26,9 @@ #include #include +#include #include "Iterator.hh" -#include "Map.hh" -#include "Vector.hh" #include "ObjectTable.hh" #include "LibertyClass.hh" #include "NetworkClass.hh" @@ -44,12 +43,12 @@ namespace sta { class MinMax; class Sdc; -typedef ObjectTable VertexTable; -typedef ObjectTable EdgeTable; -typedef Map PinVertexMap; -typedef Iterator VertexEdgeIterator; -typedef Map PeriodCheckAnnotations; -typedef ObjectId EdgeId; +using VertexTable = ObjectTable; +using EdgeTable = ObjectTable; +using PinVertexMap = std::map; +using VertexEdgeIterator = Iterator; +using PeriodCheckAnnotations = std::map; +using EdgeId = ObjectId; static constexpr EdgeId edge_id_null = object_id_null; static constexpr ObjectIdx edge_idx_null = object_id_null; @@ -65,8 +64,8 @@ public: // 2 rise/fall slews // ap_count is the dcalc analysis point count. Graph(StaState *sta, - int slew_rf_count, - DcalcAPIndex ap_count); + int slew_rf_count, + DcalcAPIndex ap_count); void makeGraph(); ~Graph(); @@ -80,13 +79,13 @@ public: VertexId id(const Vertex *vertex) const; void makePinVertices(Pin *pin); void makePinVertices(Pin *pin, - Vertex *&vertex, - Vertex *&bidir_drvr_vertex); + Vertex *&vertex, + Vertex *&bidir_drvr_vertex); // Both vertices for bidirects. void pinVertices(const Pin *pin, - // Return values. - Vertex *&vertex, - Vertex *&bidirect_drvr_vertex) const; + // Return values. + Vertex *&vertex, + Vertex *&bidirect_drvr_vertex) const; // Driver vertex for bidirects. Vertex *pinDrvrVertex(const Pin *pin) const; // Load vertex for bidirects. @@ -94,10 +93,6 @@ public: void deleteVertex(Vertex *vertex); bool hasFaninOne(Vertex *vertex) const; VertexId vertexCount() { return vertices_->size(); } - Path *makePaths(Vertex *vertex, - uint32_t count); - Path *paths(const Vertex *vertex) const; - void deletePaths(Vertex *vertex); // Reported slew are the same as those in the liberty tables. // reported_slews = measured_slews / slew_derate_from_library @@ -150,21 +145,19 @@ public: const ArcDelay &delay); // Is timing arc delay annotated. bool arcDelayAnnotated(const Edge *edge, - const TimingArc *arc, - DcalcAPIndex ap_index) const; + const TimingArc *arc, + DcalcAPIndex ap_index) const; void setArcDelayAnnotated(Edge *edge, - const TimingArc *arc, - DcalcAPIndex ap_index, - bool annotated); + const TimingArc *arc, + DcalcAPIndex ap_index, + bool annotated); bool wireDelayAnnotated(const Edge *edge, - const RiseFall *rf, - DcalcAPIndex ap_index) const; + const RiseFall *rf, + DcalcAPIndex ap_index) const; void setWireDelayAnnotated(Edge *edge, - const RiseFall *rf, - DcalcAPIndex ap_index, - bool annotated); - // True if any edge arc is annotated. - bool delayAnnotated(Edge *edge); + const RiseFall *rf, + DcalcAPIndex ap_index, + bool annotated); void minPulseWidthArc(Vertex *vertex, const RiseFall *hi_low, @@ -172,23 +165,24 @@ public: Edge *&edge, TimingArc *&arc); void minPeriodArc(Vertex *vertex, - const RiseFall *rf, - // Return values. - Edge *&edge, - TimingArc *&arc); + const RiseFall *rf, + // Return values. + Edge *&edge, + TimingArc *&arc); // Sdf period check annotation. void periodCheckAnnotation(const Pin *pin, - DcalcAPIndex ap_index, - // Return values. - float &period, - bool &exists); + DcalcAPIndex ap_index, + // Return values. + float &period, + bool &exists); void setPeriodCheckAnnotation(const Pin *pin, - DcalcAPIndex ap_index, - float period); + DcalcAPIndex ap_index, + float period); // Remove all delay and slew annotations. void removeDelaySlewAnnotations(); - VertexSet *regClkVertices() { return reg_clk_vertices_; } + VertexSet ®ClkVertices() { return reg_clk_vertices_; } + void makeSceneAfter(); static constexpr int vertex_level_bits = 24; static constexpr int vertex_level_max = (1< { public: - explicit VertexIterator(Graph *graph); + VertexIterator(Graph *graph); virtual bool hasNext() { return vertex_ || bidir_vertex_; } virtual Vertex *next(); @@ -477,9 +447,9 @@ class VertexInEdgeIterator : public VertexEdgeIterator { public: VertexInEdgeIterator(Vertex *vertex, - const Graph *graph); + const Graph *graph); VertexInEdgeIterator(VertexId vertex_id, - const Graph *graph); + const Graph *graph); bool hasNext() { return (next_ != nullptr); } Edge *next(); @@ -492,7 +462,7 @@ class VertexOutEdgeIterator : public VertexEdgeIterator { public: VertexOutEdgeIterator(Vertex *vertex, - const Graph *graph); + const Graph *graph); bool hasNext() { return (next_ != nullptr); } Edge *next(); @@ -506,31 +476,21 @@ class EdgesThruHierPinIterator : public Iterator { public: EdgesThruHierPinIterator(const Pin *hpin, - Network *network, - Graph *graph); - virtual bool hasNext() { return edge_iter_.hasNext(); } - virtual Edge *next() { return edge_iter_.next(); } + Network *network, + Graph *graph); + virtual bool hasNext(); + virtual Edge *next(); private: EdgeSet edges_; - EdgeSet::Iterator edge_iter_; + EdgeSet::iterator edge_iter_; }; -class VertexIdLess +// Helper function to create a VertexSet with the comparator initialized +inline VertexSet +makeVertexSet(StaState *sta) { -public: - VertexIdLess(Graph *&graph); - bool operator()(const Vertex *vertex1, - const Vertex *vertex2) const; - -private: - Graph *&graph_; -}; - -class VertexSet : public Set -{ -public: - VertexSet(Graph *&graph); -}; + return VertexSet(VertexIdLess(sta->graphRef())); +} } // namespace diff --git a/include/sta/GraphClass.hh b/include/sta/GraphClass.hh index 381a9b8b..ebe184c8 100644 --- a/include/sta/GraphClass.hh +++ b/include/sta/GraphClass.hh @@ -25,10 +25,10 @@ #pragma once #include +#include +#include #include "ObjectId.hh" -#include "Set.hh" -#include "Vector.hh" #include "MinMax.hh" #include "Transition.hh" #include "Delay.hh" @@ -42,19 +42,29 @@ class Edge; class VertexIterator; class VertexInEdgeIterator; class VertexOutEdgeIterator; -class GraphLoop; -class VertexSet; -typedef ObjectId VertexId; -typedef ObjectId EdgeId; -typedef Vector VertexSeq; -typedef Vector EdgeSeq; -typedef Set EdgeSet; -typedef int Level; -typedef int DcalcAPIndex; -typedef int TagGroupIndex; -typedef Vector GraphLoopSeq; -typedef std::vector SlewSeq; +class VertexIdLess +{ +public: + VertexIdLess() = delete; + VertexIdLess(Graph *&graph); + bool operator()(const Vertex *vertex1, + const Vertex *vertex2) const; + +private: + Graph *&graph_; +}; + +using VertexId = ObjectId; +using EdgeId = ObjectId; +using VertexSeq = std::vector; +using VertexSet = std::set; +using EdgeSeq = std::vector; +using EdgeSet = std::set; +using Level = int; +using DcalcAPIndex = int; +using TagGroupIndex = int; +using SlewSeq = std::vector; static constexpr int level_max = std::numeric_limits::max(); diff --git a/include/sta/GraphCmp.hh b/include/sta/GraphCmp.hh index 1cafb081..7f51b87f 100644 --- a/include/sta/GraphCmp.hh +++ b/include/sta/GraphCmp.hh @@ -33,9 +33,9 @@ namespace sta { class VertexNameLess { public: - explicit VertexNameLess(Network *network); + VertexNameLess(Network *network); bool operator()(const Vertex *vertex1, - const Vertex *vertex2); + const Vertex *vertex2); private: Network *network_; @@ -45,9 +45,9 @@ class EdgeLess { public: EdgeLess(const Network *network, - Graph *&graph); + Graph *&graph); bool operator()(const Edge *edge1, - const Edge *edge2) const; + const Edge *edge2) const; private: const PinPathNameLess pin_less_; @@ -56,7 +56,7 @@ private: void sortEdges(EdgeSeq *edges, - Network *network, - Graph *graph); + Network *network, + Graph *graph); } // namespace diff --git a/include/sta/GraphDelayCalc.hh b/include/sta/GraphDelayCalc.hh index 6a746fc4..aea61fcb 100644 --- a/include/sta/GraphDelayCalc.hh +++ b/include/sta/GraphDelayCalc.hh @@ -24,15 +24,15 @@ #pragma once -#include -#include #include +#include +#include +#include -#include "Map.hh" #include "NetworkClass.hh" #include "GraphClass.hh" #include "SearchClass.hh" -#include "DcalcAnalysisPt.hh" +#include "SdcClass.hh" #include "StaState.hh" #include "ArcDelayCalc.hh" @@ -42,9 +42,10 @@ class DelayCalcObserver; class MultiDrvrNet; class FindVertexDelays; class NetCaps; +class SearchPred; -typedef Map MultiDrvrNetMap; -typedef std::vector DrvrLoadSlews; +using MultiDrvrNetMap = std::map; +using DrvrLoadSlews = std::vector; // This class traverses the graph calling the arc delay calculator and // annotating delays on graph edges. @@ -73,7 +74,7 @@ public: // Returned string is owned by the caller. virtual std::string reportDelayCalc(const Edge *edge, const TimingArc *arc, - const Corner *corner, + const Scene *scene, const MinMax *min_max, int digits); // Percentage (0.0:1.0) change in delay that causes downstream @@ -82,19 +83,23 @@ public: virtual void setIncrementalDelayTolerance(float tol); float loadCap(const Pin *drvr_pin, - const DcalcAnalysisPt *dcalc_ap) const; + const Scene *scene, + const MinMax *min_max) const; float loadCap(const Pin *drvr_pin, const RiseFall *rf, - const DcalcAnalysisPt *dcalc_ap) const; + const Scene *scene, + const MinMax *min_max) const; void loadCap(const Pin *drvr_pin, const RiseFall *rf, - const DcalcAnalysisPt *dcalc_ap, + const Scene *scene, + const MinMax *min_max, // Return values. float &pin_cap, float &wire_cap) const; void netCaps(const Pin *drvr_pin, const RiseFall *rf, - const DcalcAnalysisPt *dcalc_ap, + const Scene *scene, + const MinMax *min_max, // Return values. float &pin_cap, float &wire_cap, @@ -102,7 +107,8 @@ public: bool &has_set_load) const; void parasiticLoad(const Pin *drvr_pin, const RiseFall *rf, - const DcalcAnalysisPt *dcalc_ap, + const Scene *scene, + const MinMax *min_max, const MultiDrvrNet *multi_drvr, ArcDelayCalc *arc_delay_calc, // Return values. @@ -112,14 +118,15 @@ public: void findDriverArcDelays(Vertex *drvr_vertex, Edge *edge, const TimingArc *arc, - const DcalcAnalysisPt *dcalc_ap, + const Scene *scene, + const MinMax *min_max, ArcDelayCalc *arc_delay_calc); // Precedence: // SDF annotation // Liberty port timing group timing_type minimum_period. // Liberty port min_period attribute. void minPeriod(const Pin *pin, - const Corner *corner, + const Scene *scene, // Return values. float &min_period, bool &exists); @@ -127,11 +134,13 @@ public: Slew edgeFromSlew(const Vertex *from_vertex, const RiseFall *from_rf, const Edge *edge, - const DcalcAnalysisPt *dcalc_ap); + const Scene *scene, + const MinMax *min_max); Slew edgeFromSlew(const Vertex *from_vertex, const RiseFall *from_rf, const TimingRole *role, - const DcalcAnalysisPt *dcalc_ap); + const Scene *scene, + const MinMax *min_max); bool bidirectDrvrSlewFromLoad(const Pin *pin) const; protected: @@ -145,13 +154,15 @@ protected: void seedNoDrvrSlew(Vertex *drvr_vertex, const Pin *drvr_pin, const RiseFall *rf, - const DcalcAnalysisPt *dcalc_ap, + const Scene *scene, + const MinMax *min_max, ArcDelayCalc *arc_delay_calc); void seedNoDrvrCellSlew(Vertex *drvr_vertex, const Pin *drvr_pin, const RiseFall *rf, const InputDrive *drive, - const DcalcAnalysisPt *dcalc_ap, + const Scene *scene, + const MinMax *min_max, ArcDelayCalc *arc_delay_calc); void seedLoadSlew(Vertex *vertex); void setInputPortWireDelays(Vertex *vertex); @@ -162,7 +173,8 @@ protected: const LibertyPort *from_port, float *from_slews, const LibertyPort *to_port, - const DcalcAnalysisPt *dcalc_ap); + const Scene *scene, + const MinMax *min_max); LibertyPort *driveCellDefaultFromPort(const LibertyCell *cell, const LibertyPort *to_port); int findPortIndex(const LibertyCell *cell, @@ -171,7 +183,8 @@ protected: Vertex *drvr_vertex, const TimingArc *arc, float from_slew, - const DcalcAnalysisPt *dcalc_ap); + const Scene *scene, + const MinMax *min_max); void findDriverDelays(Vertex *drvr_vertex, ArcDelayCalc *arc_delay_calc, LoadPinIndexMap &load_pin_index_map); @@ -196,14 +209,16 @@ protected: const MultiDrvrNet *multi_drvr, Edge *edge, const TimingArc *arc, - const DcalcAnalysisPt *dcalc_ap, + const Scene *scene, + const MinMax *min_max, ArcDelayCalc *arc_delay_calc, LoadPinIndexMap &load_pin_index_map); ArcDcalcArgSeq makeArcDcalcArgs(Vertex *drvr_vertex, const MultiDrvrNet *multi_drvr, Edge *edge, const TimingArc *arc, - const DcalcAnalysisPt *dcalc_ap, + const Scene *scene, + const MinMax *min_max, ArcDelayCalc *arc_delay_calc); void findParallelEdge(Vertex *vertex, const TimingArc *drvr_arc, @@ -225,34 +240,40 @@ protected: const TimingArc *arc, ArcDcalcResult &dcalc_result, LoadPinIndexMap &load_pin_index_map, - const DcalcAnalysisPt *dcalc_ap); + const Scene *scene, + const MinMax *min_max); bool annotateDelaySlew(Edge *edge, const TimingArc *arc, ArcDelay &gate_delay, Slew &gate_slew, - const DcalcAnalysisPt *dcalc_ap); + const Scene *scene, + const MinMax *min_max); bool annotateLoadDelays(Vertex *drvr_vertex, const RiseFall *drvr_rf, ArcDcalcResult &dcalc_result, LoadPinIndexMap &load_pin_index_map, const ArcDelay &extra_delay, bool merge, - const DcalcAnalysisPt *dcalc_ap); + const Scene *scene, + const MinMax *min_max); void findLatchEdgeDelays(Edge *edge); void findCheckEdgeDelays(Edge *edge, ArcDelayCalc *arc_delay_calc); void deleteMultiDrvrNets(); Slew checkEdgeClkSlew(const Vertex *from_vertex, const RiseFall *from_rf, - const DcalcAnalysisPt *dcalc_ap); + const Scene *scene, + const MinMax *min_max); float loadCap(const Pin *drvr_pin, const RiseFall *rf, - const DcalcAnalysisPt *dcalc_ap, + const Scene *scene, + const MinMax *min_max, ArcDelayCalc *arc_delay_calc) const; void parasiticLoad(const Pin *drvr_pin, const RiseFall *rf, - const DcalcAnalysisPt *dcalc_ap, + const Scene *scene, + const MinMax *min_max, const MultiDrvrNet *multi_drvr, ArcDelayCalc *arc_delay_calc, // Return values. @@ -261,7 +282,8 @@ protected: const Parasitic *¶sitic) const; void netCaps(const Pin *drvr_pin, const RiseFall *rf, - const DcalcAnalysisPt *dcalc_ap, + const Scene *scene, + const MinMax *min_max, const MultiDrvrNet *multi_drvr, // Return values. float &pin_cap, @@ -275,7 +297,7 @@ protected: bool incremental_; bool delays_exist_; // Vertices with invalid -to delays. - VertexSet *invalid_delays_; + VertexSet invalid_delays_; // Timing check edges with invalid delays. EdgeSet invalid_check_edges_; // Latch D->Q edges with invalid delays. @@ -284,7 +306,6 @@ protected: std::mutex invalid_edge_lock_; SearchPred *search_pred_; SearchPred *search_non_latch_pred_; - SearchPred *clk_pred_; BfsFwdIterator *iter_; MultiDrvrNetMap multi_drvr_net_map_; std::mutex multi_drvr_lock_; @@ -319,13 +340,14 @@ public: Vertex *dcalcDrvr() const { return dcalc_drvr_; } void setDcalcDrvr(Vertex *drvr); void netCaps(const RiseFall *rf, - const DcalcAnalysisPt *dcalc_ap, + const Scene *scene, + const MinMax *min_max, // Return values. float &pin_cap, float &wire_cap, float &fanout, bool &has_net_load) const; - void findCaps(const Sdc *sdc); + void findCaps(const StaState *sta); private: // Driver that triggers delay calculation for all the drivers on the net. diff --git a/include/sta/Hash.hh b/include/sta/Hash.hh index 4389d7ce..be6d5375 100644 --- a/include/sta/Hash.hh +++ b/include/sta/Hash.hh @@ -34,7 +34,7 @@ const size_t hash_init_value = 5381; // Dan Bernstein, comp.lang.c. inline size_t hashSum(size_t hash, - size_t add) + size_t add) { // hash * 31 ^ add. return ((hash << 5) + hash) ^ add; @@ -42,7 +42,7 @@ hashSum(size_t hash, inline void hashIncr(size_t &hash, - size_t add) + size_t add) { // hash * 31 ^ add. hash = ((hash << 5) + hash) ^ add; diff --git a/include/sta/HpinDrvrLoad.hh b/include/sta/HpinDrvrLoad.hh index dba934cc..995e6e14 100644 --- a/include/sta/HpinDrvrLoad.hh +++ b/include/sta/HpinDrvrLoad.hh @@ -24,7 +24,6 @@ #pragma once -#include "Set.hh" #include "NetworkClass.hh" namespace sta { @@ -34,14 +33,14 @@ class HpinDrvrLoadVisitor; void visitHpinDrvrLoads(const Pin *pin, - const Network *network, - HpinDrvrLoadVisitor *visitor); + const Network *network, + HpinDrvrLoadVisitor *visitor); class HpinDrvrLoadLess { public: bool operator()(const HpinDrvrLoad *drvr_load1, - const HpinDrvrLoad *drvr_load2) const; + const HpinDrvrLoad *drvr_load2) const; }; // Abstract base class for visitDrvrLoadsThruHierPin visitor. @@ -57,13 +56,13 @@ class HpinDrvrLoad { public: HpinDrvrLoad(const Pin *drvr, - const Pin *load, - PinSet *hpins_from_drvr, - PinSet *hpins_to_load); + const Pin *load, + PinSet *hpins_from_drvr, + PinSet *hpins_to_load); ~HpinDrvrLoad(); void report(const Network *network); HpinDrvrLoad(const Pin *drvr, - const Pin *load); + const Pin *load); const Pin *drvr() const { return drvr_; } const Pin *load() const { return load_; } PinSet *hpinsFromDrvr() { return hpins_from_drvr_; } diff --git a/include/sta/InputDrive.hh b/include/sta/InputDrive.hh index 1da22817..9a3e3119 100644 --- a/include/sta/InputDrive.hh +++ b/include/sta/InputDrive.hh @@ -40,45 +40,45 @@ class InputDriveCell; class InputDrive { public: - explicit InputDrive(); + InputDrive(); ~InputDrive(); void setSlew(const RiseFallBoth *rf, - const MinMaxAll *min_max, - float slew); + const MinMaxAll *min_max, + float slew); void setDriveResistance(const RiseFallBoth *rf, - const MinMaxAll *min_max, - float res); + const MinMaxAll *min_max, + float res); void driveResistance(const RiseFall *rf, - const MinMax *min_max, - float &res, - bool &exists) const; + const MinMax *min_max, + float &res, + bool &exists) const; bool hasDriveResistance(const RiseFall *rf, - const MinMax *min_max) const; + const MinMax *min_max) const; bool driveResistanceMinMaxEqual(const RiseFall *rf) const; void setDriveCell(const LibertyLibrary *library, - const LibertyCell *cell, - const LibertyPort *from_port, - float *from_slews, - const LibertyPort *to_port, - const RiseFallBoth *rf, - const MinMaxAll *min_max); + const LibertyCell *cell, + const LibertyPort *from_port, + float *from_slews, + const LibertyPort *to_port, + const RiseFallBoth *rf, + const MinMaxAll *min_max); void driveCell(const RiseFall *rf, - const MinMax *min_max, + const MinMax *min_max, // Return values. - const LibertyCell *&cell, - const LibertyPort *&from_port, - float *&from_slews, - const LibertyPort *&to_port) const; + const LibertyCell *&cell, + const LibertyPort *&from_port, + float *&from_slews, + const LibertyPort *&to_port) const; InputDriveCell *driveCell(const RiseFall *rf, - const MinMax *min_max) const; + const MinMax *min_max) const; bool hasDriveCell(const RiseFall *rf, - const MinMax *min_max) const; + const MinMax *min_max) const; // True if rise/fall/min/max drive cells are equal. bool driveCellsEqual() const; void slew(const RiseFall *rf, - const MinMax *min_max, - float &slew, - bool &exists) const; + const MinMax *min_max, + float &slew, + bool &exists) const; const RiseFallMinMax *slews() const { return &slews_; } private: @@ -92,10 +92,10 @@ class InputDriveCell { public: InputDriveCell(const LibertyLibrary *library, - const LibertyCell *cell, - const LibertyPort *from_port, - float *from_slews, - const LibertyPort *to_port); + const LibertyCell *cell, + const LibertyPort *from_port, + float *from_slews, + const LibertyPort *to_port); const LibertyLibrary *library() const { return library_; } void setLibrary(const LibertyLibrary *library); const LibertyCell *cell() const { return cell_; } diff --git a/include/sta/InternalPower.hh b/include/sta/InternalPower.hh index 0c30a38d..408e946b 100644 --- a/include/sta/InternalPower.hh +++ b/include/sta/InternalPower.hh @@ -41,7 +41,7 @@ public: FuncExpr *when() const { return when_; } void setWhen(FuncExpr *when); void setModel(const RiseFall *rf, - InternalPowerModel *model); + InternalPowerModel *model); InternalPowerModel *model(const RiseFall *rf) const; const char *relatedPgPin() const { return related_pg_pin_; } void setRelatedPgPin(const char *related_pg_pin); @@ -56,9 +56,9 @@ class InternalPower { public: InternalPower(LibertyCell *cell, - LibertyPort *port, - LibertyPort *related_port, - InternalPowerAttrs *attrs); + LibertyPort *port, + LibertyPort *related_port, + InternalPowerAttrs *attrs); ~InternalPower(); LibertyCell *libertyCell() const; LibertyPort *port() const { return port_; } @@ -66,9 +66,9 @@ public: FuncExpr *when() const { return when_; } const char *relatedPgPin() const { return related_pg_pin_; } float power(const RiseFall *rf, - const Pvt *pvt, - float in_slew, - float load_cap); + const Pvt *pvt, + float in_slew, + float load_cap); protected: LibertyPort *port_; @@ -81,12 +81,12 @@ protected: class InternalPowerModel { public: - explicit InternalPowerModel(TableModel *model); + InternalPowerModel(TableModel *model); ~InternalPowerModel(); float power(const LibertyCell *cell, - const Pvt *pvt, - float in_slew, - float load_cap) const; + const Pvt *pvt, + float in_slew, + float load_cap) const; std::string reportPower(const LibertyCell *cell, const Pvt *pvt, float in_slew, @@ -95,14 +95,14 @@ public: protected: void findAxisValues(float in_slew, - float load_cap, - // Return values. - float &axis_value1, - float &axis_value2, - float &axis_value3) const; + float load_cap, + // Return values. + float &axis_value1, + float &axis_value2, + float &axis_value3) const; float axisValue(const TableAxis *axis, - float in_slew, - float load_cap) const; + float in_slew, + float load_cap) const; bool checkAxes(const TableModel *model); bool checkAxis(const TableAxis *axis); diff --git a/include/sta/Iterator.hh b/include/sta/Iterator.hh index 6c1ea621..eade8d31 100644 --- a/include/sta/Iterator.hh +++ b/include/sta/Iterator.hh @@ -40,4 +40,80 @@ public: virtual OBJ next() = 0; }; +template +class VectorIterator : public Iterator +{ +public: + VectorIterator(const VECTOR_TYPE *seq) : + seq_(seq) + { + if (seq_) + itr_ = seq_->begin(); + } + VectorIterator(const VECTOR_TYPE &seq) : + seq_(&seq), + itr_(seq.begin()) + { + } + + bool hasNext() { return seq_ && itr_ != seq_->end(); } + OBJ_TYPE next() { return *itr_++; } + +protected: + const VECTOR_TYPE *seq_; + VECTOR_TYPE::const_iterator itr_; +}; + +template +class MapIterator : public Iterator +{ +public: + MapIterator(const MAP_TYPE *map) : + map_(map) + { + if (map) + itr_ = map->begin(); + } + MapIterator(const MAP_TYPE &map) : + map_(&map), + itr_(map.begin()) + { + } + + bool hasNext() { return map_ && itr_ != map_->end(); } + OBJ_TYPE next() { + OBJ_TYPE next = itr_->second; + itr_++; + return next; + } + +protected: + const MAP_TYPE *map_; + MAP_TYPE::const_iterator itr_; +}; + +template +class SetIterator : public Iterator +{ +public: + SetIterator(const SET_TYPE *set) : + set_(set) + { + if (set) + itr_ = set->begin(); + } + SetIterator(const SET_TYPE &set) : + set_(&set), + itr_(set.begin()) + { + } + + bool hasNext() { return set_ && itr_ != set_->end(); } + OBJ_TYPE next() { return *itr_++; } + +protected: + const SET_TYPE *set_; + SET_TYPE::const_iterator itr_; +}; + } // namespace diff --git a/include/sta/LeakagePower.hh b/include/sta/LeakagePower.hh index a0dbd86d..0b542636 100644 --- a/include/sta/LeakagePower.hh +++ b/include/sta/LeakagePower.hh @@ -48,7 +48,7 @@ class LeakagePower { public: LeakagePower(LibertyCell *cell, - LeakagePowerAttrs *attrs); + LeakagePowerAttrs *attrs); ~LeakagePower(); LibertyCell *libertyCell() const { return cell_; } FuncExpr *when() const { return when_; } diff --git a/include/sta/Liberty.hh b/include/sta/Liberty.hh index 09b4579a..c89a5a66 100644 --- a/include/sta/Liberty.hh +++ b/include/sta/Liberty.hh @@ -27,7 +27,11 @@ #include #include #include +#include +#include +#include +#include "ContainerHelpers.hh" #include "MinMax.hh" #include "RiseFallMinMax.hh" #include "ConcreteLibrary.hh" @@ -56,40 +60,37 @@ class OcvDerate; class TimingArcAttrs; class InternalPowerAttrs; class StaState; -class Corner; -class Corners; -class DcalcAnalysisPt; +class Scene; class DriverWaveform; -typedef Map TableTemplateMap; -typedef Vector TableTemplateSeq; -typedef Map BusDclMap; -typedef Vector BusDclSeq; -typedef Map ScaleFactorsMap; -typedef Map WireloadMap; -typedef Map WireloadSelectionMap; -typedef Map OperatingConditionsMap; -typedef Map PortToSequentialMap; -typedef Vector TimingArcSetSeq; -typedef Set TimingArcSetMap; -typedef Map LibertyPortPairTimingArcMap; -typedef Vector InternalPowerSeq; -typedef Map PortInternalPowerSeq; -typedef Vector LeakagePowerSeq; -typedef Map LibertyPortTimingArcMap; -typedef Map ScaledCellMap; -typedef Map ScaledPortMap; -typedef Map ModeDefMap; -typedef Map ModeValueMap; -typedef Map LatchEnableMap; -typedef Vector LatchEnableSeq; -typedef Map OcvDerateMap; -typedef Vector InternalPowerAttrsSeq; -typedef Map SupplyVoltageMap; -typedef Map DriverWaveformMap; -typedef Vector DcalcAnalysisPtSeq; +using TableTemplateMap = std::map; +using TableTemplateSeq = std::vector; +using BusDclMap = std::map; +using BusDclSeq = std::vector; +using ScaleFactorsMap = std::map; +using WireloadMap = std::map; +using WireloadSelectionMap = std::map; +using OperatingConditionsMap = std::map; +using PortToSequentialMap = std::map; +using TimingArcSetSeq = std::vector; +using TimingArcSetSet = std::set; +using LibertyPortPairTimingArcMap = std::map; +using InternalPowerSeq = std::vector; +using PortInternalPowerMap = std::map; +using LeakagePowerSeq = std::vector; +using LibertyPortTimingArcMap = std::map; +using ScaledCellMap = std::map; +using ScaledPortMap = std::map; +using ModeDefMap = std::map; +using ModeValueMap = std::map; +using LatchEnableMap = std::map; +using LatchEnableSeq = std::vector; +using OcvDerateMap = std::map; +using InternalPowerAttrsSeq = std::vector; +using SupplyVoltageMap = std::map; +using DriverWaveformMap = std::map; +using SceneSeq = std::vector; enum class ClockGateType { none, latch_posedge, latch_negedge, other }; @@ -98,11 +99,11 @@ enum class DelayModelType { cmos_linear, cmos_pwl, cmos2, table, polynomial, dcm enum class ScanSignalType { enable, enable_inverted, clock, clock_a, clock_b, input, input_inverted, output, output_inverted, none }; enum class PwrGndType { none, - primary_power, primary_ground, - backup_power, backup_ground, - internal_power, internal_ground, - nwell, pwell, - deepnwell, deeppwell}; + primary_power, primary_ground, + backup_power, backup_ground, + internal_power, internal_ground, + nwell, pwell, + deepnwell, deeppwell}; enum class ScaleFactorPvt { process, volt, temp, unknown }; constexpr int scale_factor_pvt_count = int(ScaleFactorPvt::unknown) + 1; @@ -151,7 +152,7 @@ class LibertyLibrary : public ConcreteLibrary { public: LibertyLibrary(const char *name, - const char *filename); + const char *filename); virtual ~LibertyLibrary(); LibertyCell *findLibertyCell(const char *name) const; LibertyCellSeq findLibertyCellsMatching(PatternMatch *pattern); @@ -165,9 +166,9 @@ public: BusDcl *findBusDcl(const char *name) const; BusDclSeq busDcls() const; void addTableTemplate(TableTemplate *tbl_template, - TableTemplateType type); + TableTemplateType type); TableTemplate *findTableTemplate(const char *name, - TableTemplateType type); + TableTemplateType type); TableTemplateSeq tableTemplates() const; float nominalProcess() const { return nominal_process_; } void setNominalProcess(float process); @@ -182,21 +183,21 @@ public: ScaleFactors *findScaleFactors(const char *name); ScaleFactors *scaleFactors() const { return scale_factors_; } float scaleFactor(ScaleFactorType type, - const Pvt *pvt) const; + const Pvt *pvt) const; float scaleFactor(ScaleFactorType type, - const LibertyCell *cell, - const Pvt *pvt) const; + const LibertyCell *cell, + const Pvt *pvt) const; float scaleFactor(ScaleFactorType type, - int rf_index, - const LibertyCell *cell, - const Pvt *pvt) const; + int rf_index, + const LibertyCell *cell, + const Pvt *pvt) const; void setWireSlewDegradationTable(TableModel *model, - const RiseFall *rf); + const RiseFall *rf); TableModel *wireSlewDegradationTable(const RiseFall *rf) const; float degradeWireSlew(const RiseFall *rf, - float in_slew, - float wire_delay) const; + float in_slew, + float wire_delay) const; // Check for supported axis variables. // Return true if axes are supported. static bool checkSlewDegradationAxes(const TablePtr &table); @@ -215,58 +216,58 @@ public: float &intrisic, bool &exists) const; void setDefaultIntrinsic(const RiseFall *rf, - float value); + float value); // Uses defaultOutputPinRes or defaultBidirectPinRes based on dir. void defaultPinResistance(const RiseFall *rf, - const PortDirection *dir, - // Return values. - float &res, - bool &exists) const; + const PortDirection *dir, + // Return values. + float &res, + bool &exists) const; void defaultBidirectPinRes(const RiseFall *rf, - // Return values. - float &res, - bool &exists) const; + // Return values. + float &res, + bool &exists) const; void setDefaultBidirectPinRes(const RiseFall *rf, - float value); + float value); void defaultOutputPinRes(const RiseFall *rf, - // Return values. - float &res, - bool &exists) const; + // Return values. + float &res, + bool &exists) const; void setDefaultOutputPinRes(const RiseFall *rf, - float value); + float value); void defaultMaxSlew(float &slew, - bool &exists) const; + bool &exists) const; void setDefaultMaxSlew(float slew); void defaultMaxCapacitance(float &cap, - bool &exists) const; + bool &exists) const; void setDefaultMaxCapacitance(float cap); void defaultMaxFanout(float &fanout, - bool &exists) const; + bool &exists) const; void setDefaultMaxFanout(float fanout); void defaultFanoutLoad(// Return values. - float &fanout, - bool &exists) const; + float &fanout, + bool &exists) const; void setDefaultFanoutLoad(float load); // Logic thresholds. float inputThreshold(const RiseFall *rf) const; void setInputThreshold(const RiseFall *rf, - float th); + float th); float outputThreshold(const RiseFall *rf) const; void setOutputThreshold(const RiseFall *rf, - float th); + float th); // Slew thresholds (measured). float slewLowerThreshold(const RiseFall *rf) const; void setSlewLowerThreshold(const RiseFall *rf, - float th); + float th); float slewUpperThreshold(const RiseFall *rf) const; void setSlewUpperThreshold(const RiseFall *rf, - float th); + float th); // The library and delay calculator use the liberty slew upper/lower // (measured) thresholds for the table axes and value. These slews // are scaled by slew_derate_from_library to get slews reported to @@ -304,37 +305,37 @@ public: OcvDerate *findOcvDerate(const char *derate_name); void addOcvDerate(OcvDerate *derate); void addSupplyVoltage(const char *suppy_name, - float voltage); + float voltage); bool supplyExists(const char *suppy_name) const; void supplyVoltage(const char *supply_name, - // Return value. - float &voltage, - bool &exists) const; + // Return value. + float &voltage, + bool &exists) const; // Make scaled cell. Call LibertyCell::addScaledCell after it is complete. LibertyCell *makeScaledCell(const char *name, - const char *filename); + const char *filename); static void - makeCornerMap(LibertyLibrary *lib, - int ap_index, - Network *network, - Report *report); - static void - makeCornerMap(LibertyCell *link_cell, - LibertyCell *map_cell, - int ap_index, - Report *report); - static void - makeCornerMap(LibertyCell *cell1, - LibertyCell *cell2, - bool link, - int ap_index, - Report *report); - static void - checkCorners(LibertyCell *cell, - Corners *corners, + makeSceneMap(LibertyLibrary *lib, + int ap_index, + Network *network, Report *report); + static void + makeSceneMap(LibertyCell *link_cell, + LibertyCell *map_cell, + int ap_index, + Report *report); + static void + makeSceneMap(LibertyCell *cell1, + LibertyCell *cell2, + bool link, + int ap_index, + Report *report); + static void + checkScenes(LibertyCell *cell, + const SceneSeq &scenes, + Report *report); DriverWaveform *findDriverWaveform(const char *name); DriverWaveform *driverWaveformDefault() { return driver_waveform_default_; } @@ -342,8 +343,8 @@ public: protected: float degradeWireSlew(const TableModel *model, - float in_slew, - float wire_delay) const; + float in_slew, + float wire_delay) const; Units *units_; DelayModelType delay_model_type_; @@ -404,12 +405,12 @@ private: class LibertyCellIterator : public Iterator { public: - explicit LibertyCellIterator(const LibertyLibrary *library); + LibertyCellIterator(const LibertyLibrary *library); bool hasNext(); LibertyCell *next(); private: - ConcreteCellMap::ConstIterator iter_; + ConcreteLibraryCellIterator iter_; }; //////////////////////////////////////////////////////////////// @@ -418,8 +419,8 @@ class LibertyCell : public ConcreteCell { public: LibertyCell(LibertyLibrary *library, - const char *name, - const char *filename); + const char *name, + const char *filename); virtual ~LibertyCell(); LibertyLibrary *libertyLibrary() const { return liberty_library_; } LibertyLibrary *libertyLibrary() { return liberty_library_; } @@ -474,8 +475,8 @@ public: const InternalPowerSeq &internalPowers(const LibertyPort *port); LeakagePowerSeq *leakagePowers() { return &leakage_powers_; } void leakagePower(// Return values. - float &leakage, - bool &exists) const; + float &leakage, + bool &exists) const; bool leakagePowerExists() const { return leakage_power_exists_; } // Register, Latch or Statetable. @@ -492,16 +493,14 @@ public: bool hasInferedRegTimingArcs() const { return has_infered_reg_timing_arcs_; } TestCell *testCell() const { return test_cell_; } void latchEnable(const TimingArcSet *arc_set, - // Return values. - const LibertyPort *&enable_port, - const FuncExpr *&enable_func, - const RiseFall *&enable_rf) const; + // Return values. + const LibertyPort *&enable_port, + const FuncExpr *&enable_func, + const RiseFall *&enable_rf) const; const RiseFall *latchCheckEnableEdge(TimingArcSet *check_set); - bool isDisabledConstraint() const { return is_disabled_constraint_; } - LibertyCell *cornerCell(const Corner *corner, - const MinMax *min_max); - LibertyCell *cornerCell(const DcalcAnalysisPt *dcalc_ap); - LibertyCell *cornerCell(int ap_index); + LibertyCell *sceneCell(const Scene *scene, + const MinMax *min_max); + LibertyCell *sceneCell(int ap_index); // AOCV float ocvArcDepth() const; @@ -510,22 +509,22 @@ public: // Build helpers. void makeSequential(int size, - bool is_register, - FuncExpr *clk, - FuncExpr *data, - FuncExpr *clear, - FuncExpr *preset, - LogicValue clr_preset_out, - LogicValue clr_preset_out_inv, - LibertyPort *output, - LibertyPort *output_inv); + bool is_register, + FuncExpr *clk, + FuncExpr *data, + FuncExpr *clear, + FuncExpr *preset, + LogicValue clr_preset_out, + LogicValue clr_preset_out_inv, + LibertyPort *output, + LibertyPort *output_inv); void makeStatetable(LibertyPortSeq &input_ports, LibertyPortSeq &internal_ports, StatetableRows &table); void addBusDcl(BusDcl *bus_dcl); // Add scaled cell after it is complete. void addScaledCell(OperatingConditions *op_cond, - LibertyCell *scaled_cell); + LibertyCell *scaled_cell); unsigned addTimingArcSet(TimingArcSet *set); void addInternalPower(InternalPower *power); void addInternalPowerAttrs(InternalPowerAttrs *attrs); @@ -536,23 +535,22 @@ public: void addOcvDerate(OcvDerate *derate); void setTestCell(TestCell *test); void setHasInferedRegTimingArcs(bool infered); - void setIsDisabledConstraint(bool is_disabled); - void setCornerCell(LibertyCell *corner_cell, - int ap_index); + void setSceneCell(LibertyCell *scene_cell, + int ap_index); // Call after cell is finished being constructed. void finish(bool infer_latches, - Report *report, - Debug *debug); + Report *report, + Debug *debug); bool isBuffer() const; bool isInverter() const; // Only valid when isBuffer() returns true. void bufferPorts(// Return values. - LibertyPort *&input, - LibertyPort *&output) const; + LibertyPort *&input, + LibertyPort *&output) const; // Check all liberty cells to make sure they exist - // for all the defined corners. - static void checkLibertyCorners(); - void ensureVoltageWaveforms(const DcalcAnalysisPtSeq &dcalc_aps); + // for all the defined scenes. + static void checkLibertyScenes(); + void ensureVoltageWaveforms(const SceneSeq &scenes); const char *footprint() const; void setFootprint(const char *footprint); const char *userFunctionClass() const; @@ -563,18 +561,18 @@ protected: void setHasInternalPorts(bool has_internal); void setLibertyLibrary(LibertyLibrary *library); void makeLatchEnables(Report *report, - Debug *debug); + Debug *debug); FuncExpr *findLatchEnableFunc(const LibertyPort *d, const LibertyPort *en, const RiseFall *en_rf) const; LatchEnable *makeLatchEnable(LibertyPort *d, - LibertyPort *en, + LibertyPort *en, const RiseFall *en_rf, - LibertyPort *q, - TimingArcSet *d_to_q, - TimingArcSet *en_to_q, - TimingArcSet *setup_check, - Debug *debug); + LibertyPort *q, + TimingArcSet *d_to_q, + TimingArcSet *en_to_q, + TimingArcSet *setup_check, + Debug *debug); TimingArcSet *findLatchSetup(const LibertyPort *d, const LibertyPort *en, const RiseFall *en_rf, @@ -591,10 +589,10 @@ protected: void makeTimingArcMap(Report *report); void makeTimingArcPortMaps(); bool hasBufferFunc(const LibertyPort *input, - const LibertyPort *output) const; + const LibertyPort *output) const; bool hasInverterFunc(const LibertyPort *input, - const LibertyPort *output) const; - bool checkCornerCell(const Corner *corner, + const LibertyPort *output) const; + bool checkSceneCell(const Scene *scene, const MinMax *min_max) const; LibertyLibrary *liberty_library_; @@ -612,13 +610,13 @@ protected: bool interface_timing_; ClockGateType clock_gate_type_; TimingArcSetSeq timing_arc_sets_; - TimingArcSetMap timing_arc_set_map_; + TimingArcSetSet timing_arc_set_set_; LibertyPortPairTimingArcMap port_timing_arc_set_map_; LibertyPortTimingArcMap timing_arc_set_from_map_; LibertyPortTimingArcMap timing_arc_set_to_map_; bool has_infered_reg_timing_arcs_; InternalPowerSeq internal_powers_; - PortInternalPowerSeq port_internal_powers_; + PortInternalPowerMap port_internal_powers_; InternalPowerAttrsSeq internal_power_attrs_; LeakagePowerSeq leakage_powers_; SequentialSeq sequentials_; @@ -639,8 +637,7 @@ protected: float ocv_arc_depth_; OcvDerate *ocv_derate_; OcvDerateMap ocv_derate_map_; - bool is_disabled_constraint_; - Vector corner_cells_; + std::vector scene_cells_; float leakage_power_; bool leakage_power_exists_; bool has_internal_ports_; @@ -659,18 +656,18 @@ private: class LibertyCellPortIterator : public Iterator { public: - explicit LibertyCellPortIterator(const LibertyCell *cell); + LibertyCellPortIterator(const LibertyCell *cell); bool hasNext(); LibertyPort *next(); private: - ConcretePortSeq::ConstIterator iter_; + ConcreteCellPortIterator iter_; }; class LibertyCellPortBitIterator : public Iterator { public: - explicit LibertyCellPortBitIterator(const LibertyCell *cell); + LibertyCellPortBitIterator(const LibertyCell *cell); virtual ~LibertyCellPortBitIterator(); bool hasNext(); LibertyPort *next(); @@ -704,33 +701,33 @@ public: ScanSignalType scanSignalType() const { return scan_signal_type_; } void setScanSignalType(ScanSignalType type); void fanoutLoad(// Return values. - float &fanout_load, - bool &exists) const; + float &fanout_load, + bool &exists) const; void setFanoutLoad(float fanout_load); float capacitance() const; float capacitance(const MinMax *min_max) const; float capacitance(const RiseFall *rf, - const MinMax *min_max) const; + const MinMax *min_max) const; void capacitance(const RiseFall *rf, - const MinMax *min_max, - // Return values. - float &cap, - bool &exists) const; + const MinMax *min_max, + // Return values. + float &cap, + bool &exists) const; // Capacitance at op_cond derated by library/cell scale factors // using pvt. float capacitance(const RiseFall *rf, - const MinMax *min_max, - const OperatingConditions *op_cond, - const Pvt *pvt) const; + const MinMax *min_max, + const OperatingConditions *op_cond, + const Pvt *pvt) const; bool capacitanceIsOneValue() const; void setCapacitance(float cap); void setCapacitance(const RiseFall *rf, - const MinMax *min_max, - float cap); + const MinMax *min_max, + float cap); // Max of rise/fall. float driveResistance() const; float driveResistance(const RiseFall *rf, - const MinMax *min_max) const; + const MinMax *min_max) const; // Zero load delay. ArcDelay intrinsicDelay(const StaState *sta) const; ArcDelay intrinsicDelay(const RiseFall *rf, @@ -742,38 +739,38 @@ public: FuncExpr *tristateEnable() const { return tristate_enable_; } void setTristateEnable(FuncExpr *enable); void slewLimit(const MinMax *min_max, - // Return values. - float &limit, - bool &exists) const; + // Return values. + float &limit, + bool &exists) const; void setSlewLimit(float slew, - const MinMax *min_max); + const MinMax *min_max); void capacitanceLimit(const MinMax *min_max, - // Return values. - float &limit, - bool &exists) const; + // Return values. + float &limit, + bool &exists) const; void setCapacitanceLimit(float cap, - const MinMax *min_max); + const MinMax *min_max); void fanoutLimit(const MinMax *min_max, - // Return values. - float &limit, - bool &exists) const; + // Return values. + float &limit, + bool &exists) const; void setFanoutLimit(float fanout, - const MinMax *min_max); + const MinMax *min_max); void minPeriod(const OperatingConditions *op_cond, - const Pvt *pvt, - float &min_period, - bool &exists) const; + const Pvt *pvt, + float &min_period, + bool &exists) const; // Unscaled value. void minPeriod(float &min_period, - bool &exists) const; + bool &exists) const; void setMinPeriod(float min_period); // This corresponds to the min_pulse_width_high/low port attribute. // high = rise, low = fall void minPulseWidth(const RiseFall *hi_low, - float &min_width, - bool &exists) const; + float &min_width, + bool &exists) const; void setMinPulseWidth(const RiseFall *hi_low, - float min_width); + float min_width); bool isClock() const; void setIsClock(bool is_clk); bool isClockGateClock() const { return is_clk_gate_clk_; } @@ -813,19 +810,14 @@ public: // Rise for high, fall for low. const RiseFall *pulseClkSense() const { return pulse_clk_sense_; } void setPulseClk(const RiseFall *rfigger, - const RiseFall *sense); - bool isDisabledConstraint() const { return is_disabled_constraint_; } - void setIsDisabledConstraint(bool is_disabled); - LibertyPort *cornerPort(const Corner *corner, - const MinMax *min_max); - const LibertyPort *cornerPort(const Corner *corner, - const MinMax *min_max) const; - LibertyPort *cornerPort(const DcalcAnalysisPt *dcalc_ap); - const LibertyPort *cornerPort(const DcalcAnalysisPt *dcalc_ap) const; - LibertyPort *cornerPort(int ap_index); - const LibertyPort *cornerPort(int ap_index) const; - void setCornerPort(LibertyPort *corner_port, - int ap_index); + const RiseFall *sense); + LibertyPort *scenePort(const Scene *scene, + const MinMax *min_max); + const LibertyPort *scenePort(const Scene *scene, + const MinMax *min_max) const; + const LibertyPort *scenePort(int ap_index) const; + void setScenePort(LibertyPort *scene_port, + int ap_index); const char *relatedGroundPin() const; void setRelatedGroundPin(const char *related_ground_pin); const char *relatedPowerPin() const; @@ -852,35 +844,36 @@ public: RiseFallMinMax clockTreePathDelays() const __attribute__ ((deprecated)); static bool equiv(const LibertyPort *port1, - const LibertyPort *port2); + const LibertyPort *port2); static bool less(const LibertyPort *port1, - const LibertyPort *port2); + const LibertyPort *port2); protected: // Constructor is internal to LibertyBuilder. LibertyPort(LibertyCell *cell, - const char *name, - bool is_bus, - BusDcl *bus_dcl, + const char *name, + bool is_bus, + BusDcl *bus_dcl, int from_index, - int to_index, - bool is_bundle, - ConcretePortSeq *members); + int to_index, + bool is_bundle, + ConcretePortSeq *members); virtual ~LibertyPort(); void setMinPort(LibertyPort *min); void addScaledPort(OperatingConditions *op_cond, - LibertyPort *scaled_port); + LibertyPort *scaled_port); RiseFallMinMax clkTreeDelays1() const; void setMemberFlag(bool value, - const std::function &setter); + const std::function &setter); void setMemberFloat(float value, - const std::function &setter); + const std::function &setter); void setMemberMinMaxFloat(float value, - const MinMax *min_max, - const std::function &setter); + const MinMax *min_max, + const std::function &setter); + LibertyPort *scenePort(int ap_index); LibertyCell *liberty_cell_; BusDcl *bus_dcl_; @@ -902,7 +895,7 @@ protected: const RiseFall *pulse_clk_sense_; std::string related_ground_pin_; std::string related_power_pin_; - Vector corner_ports_; + std::vector scene_ports_; ReceiverModelPtr receiver_model_; DriverWaveform *driver_waveform_[RiseFall::index_count]; // Redundant with clock_tree_path_delay timing arcs but faster to access. @@ -923,7 +916,6 @@ protected: bool isolation_cell_enable_:1; bool level_shifter_data_:1; bool is_switch_:1; - bool is_disabled_constraint_:1; bool is_pad_:1; private: @@ -939,7 +931,7 @@ sortByName(const LibertyPortSet *set); class LibertyPortMemberIterator : public Iterator { public: - explicit LibertyPortMemberIterator(const LibertyPort *port); + LibertyPortMemberIterator(const LibertyPort *port); virtual ~LibertyPortMemberIterator(); virtual bool hasNext(); virtual LibertyPort *next(); @@ -974,10 +966,10 @@ class OperatingConditions : public Pvt public: OperatingConditions(const char *name); OperatingConditions(const char *name, - float process, - float voltage, - float temperature, - WireloadTree wire_load_tree); + float process, + float voltage, + float temperature, + WireloadTree wire_load_tree); const char *name() const { return name_.c_str(); } WireloadTree wireloadTree() const { return wire_load_tree_; } void setWireloadTree(WireloadTree tree); @@ -990,23 +982,23 @@ protected: class ScaleFactors { public: - explicit ScaleFactors(const char *name); + ScaleFactors(const char *name); const char *name() const { return name_.c_str(); } float scale(ScaleFactorType type, - ScaleFactorPvt pvt, - const RiseFall *rf); + ScaleFactorPvt pvt, + const RiseFall *rf); float scale(ScaleFactorType type, - ScaleFactorPvt pvt, - int rf_index); + ScaleFactorPvt pvt, + int rf_index); float scale(ScaleFactorType type, - ScaleFactorPvt pvt); + ScaleFactorPvt pvt); void setScale(ScaleFactorType type, - ScaleFactorPvt pvt, - const RiseFall *rf, - float scale); + ScaleFactorPvt pvt, + const RiseFall *rf, + float scale); void setScale(ScaleFactorType type, - ScaleFactorPvt pvt, - float scale); + ScaleFactorPvt pvt, + float scale); void print(); protected: @@ -1018,8 +1010,8 @@ class BusDcl { public: BusDcl(const char *name, - int from, - int to); + int from, + int to); const char *name() const { return name_.c_str(); } int from() const { return from_; } int to() const { return to_; } @@ -1037,8 +1029,8 @@ public: ~ModeDef(); const char *name() const { return name_.c_str(); } ModeValueDef *defineValue(const char *value, - FuncExpr *cond, - const char *sdf_cond); + FuncExpr *cond, + const char *sdf_cond); ModeValueDef *findValueDef(const char *value); ModeValueMap *values() { return &values_; } @@ -1067,8 +1059,8 @@ public: protected: // Private to ModeDef::defineValue. ModeValueDef(const char *value, - FuncExpr *cond, - const char *sdf_cond); + FuncExpr *cond, + const char *sdf_cond); std::string value_; FuncExpr *cond_; @@ -1083,9 +1075,9 @@ class TableTemplate public: TableTemplate(const char *name); TableTemplate(const char *name, - TableAxisPtr axis1, - TableAxisPtr axis2, - TableAxisPtr axis3); + TableAxisPtr axis1, + TableAxisPtr axis2, + TableAxisPtr axis3); const char *name() const { return name_.c_str(); } void setName(const char *name); const TableAxis *axis1() const { return axis1_.get(); } @@ -1125,9 +1117,9 @@ public: const EarlyLate *early_late, PathType path_type); void setDerateTable(const RiseFall *rf, - const EarlyLate *early_late, - PathType path_type, - TablePtr derate); + const EarlyLate *early_late, + PathType path_type, + TablePtr derate); private: const char *name_; diff --git a/include/sta/LibertyClass.hh b/include/sta/LibertyClass.hh index 06f2729f..1d200a76 100644 --- a/include/sta/LibertyClass.hh +++ b/include/sta/LibertyClass.hh @@ -25,10 +25,9 @@ #pragma once #include - -#include "Vector.hh" -#include "Map.hh" -#include "Set.hh" +#include +#include +#include namespace sta { @@ -67,19 +66,19 @@ class ReceiverModel; class Statetable; class StatetableRow; -typedef Vector LibertyLibrarySeq; -typedef Vector LibertyCellSeq; -typedef Vector SequentialSeq; -typedef Map LibertyCellEquivMap; -typedef Vector LibertyPortSeq; -typedef Set LibertyPortSet; -typedef std::pair LibertyPortPair; -typedef Set LibertyCellSet; -typedef std::shared_ptr TablePtr; -typedef std::shared_ptr TimingArcAttrsPtr; -typedef std::shared_ptr TableAxisPtr; -typedef std::shared_ptr ReceiverModelPtr; -typedef std::vector StatetableRows; +using LibertyLibrarySeq = std::vector; +using LibertyCellSeq = std::vector; +using SequentialSeq = std::vector; +using LibertyCellEquivMap = std::map; +using LibertyPortSeq = std::vector; +using LibertyPortSet = std::set; +using LibertyPortPair = std::pair; +using LibertyCellSet = std::set; +using TablePtr = std::shared_ptr
; +using TimingArcAttrsPtr = std::shared_ptr; +using TableAxisPtr = std::shared_ptr; +using ReceiverModelPtr = std::shared_ptr; +using StatetableRows = std::vector; enum class ScaleFactorType : unsigned { pin_cap, @@ -161,19 +160,19 @@ class LibertyPortPairLess { public: bool operator()(const LibertyPortPair &pair1, - const LibertyPortPair &pair2) const; + const LibertyPortPair &pair2) const; }; bool timingArcSetLess(const TimingArcSet *set1, - const TimingArcSet *set2); + const TimingArcSet *set2); class TimingArcSetLess { public: bool operator()(const TimingArcSet *set1, - const TimingArcSet *set2) const + const TimingArcSet *set2) const { return timingArcSetLess(set1, set2); } diff --git a/include/sta/LinearModel.hh b/include/sta/LinearModel.hh index f70cd737..a173ad6b 100644 --- a/include/sta/LinearModel.hh +++ b/include/sta/LinearModel.hh @@ -58,8 +58,8 @@ protected: class CheckLinearModel : public CheckTimingModel { public: - explicit CheckLinearModel(LibertyCell *cell, - float intrinsic); + CheckLinearModel(LibertyCell *cell, + float intrinsic); ArcDelay checkDelay(const Pvt *pvt, float from_slew, float to_slew, diff --git a/include/sta/Machine.hh b/include/sta/Machine.hh index c66b3ab9..68e95577 100644 --- a/include/sta/Machine.hh +++ b/include/sta/Machine.hh @@ -72,7 +72,7 @@ #define vsnprint vsnprintf #endif -#include // size_t +#include // size_t namespace sta { diff --git a/include/sta/Map.hh b/include/sta/Map.hh deleted file mode 100644 index bfcb6455..00000000 --- a/include/sta/Map.hh +++ /dev/null @@ -1,191 +0,0 @@ -// OpenSTA, Static Timing Analyzer -// Copyright (c) 2025, Parallax Software, Inc. -// -// This program is free software: you can redistribute it and/or modify -// it under the terms of the GNU General Public License as published by -// the Free Software Foundation, either version 3 of the License, or -// (at your option) any later version. -// -// This program is distributed in the hope that it will be useful, -// but WITHOUT ANY WARRANTY; without even the implied warranty of -// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -// GNU General Public License for more details. -// -// You should have received a copy of the GNU General Public License -// along with this program. If not, see . -// -// The origin of this software must not be misrepresented; you must not -// claim that you wrote the original software. -// -// Altered source versions must be plainly marked as such, and must not be -// misrepresented as being the original software. -// -// This notice may not be removed or altered from any source distribution. - -#pragma once - -#include -#include - -namespace sta { - -// Add convenience functions around STL container. -template > -class Map : public std::map -{ -public: - Map() : - std::map() - { - } - explicit Map(const CMP &cmp) : - std::map(cmp) - { - } - - // Find out if key is in the set. - bool - hasKey(const KEY key) const - { - return this->find(key) != this->end(); - } - - // Find the value corresponding to key. - VALUE - findKey(const KEY key) const - { - auto find_iter = this->find(key); - if (find_iter != this->end()) - return find_iter->second; - else - return nullptr; - } - void - findKey(const KEY key, - // Return Values. - VALUE &value, - bool &exists) const - { - auto find_iter = this->find(key); - if (find_iter != this->end()) { - value = find_iter->second; - exists = true; - } - else - exists = false; - } - void - findKey(const KEY &key, - // Return Values. - KEY &map_key, - VALUE &value, - bool &exists) const - { - auto find_iter = this->find(key); - if (find_iter != this->end()) { - map_key = find_iter->first; - value = find_iter->second; - exists = true; - } - else - exists = false; - } - - void - insert(const KEY &key, - VALUE value) - { - this->operator[](key) = value; - } - - void - deleteContents() - { - Iterator iter(this); - while (iter.hasNext()) - delete iter.next(); - } - - void - deleteKeysContents() - { - for (const auto [key, value] : this) { - delete key; - delete value; - } - } - - void - deleteArrayContents() - { - Iterator iter(this); - while (iter.hasNext()) - delete [] iter.next(); - } - - void - deleteContentsClear() - { - deleteContents(); - std::map::clear(); - } - - // Java style container itererator - // Map::Iterator iter(map); - // while (iter.hasNext()) { - // Value *v = iter.next(); - // } - class Iterator - { - public: - Iterator() : container_(nullptr) {} - explicit Iterator(std::map *container) : - container_(container) - { if (container_ != nullptr) iter_ = container_->begin(); } - explicit Iterator(std::map &container) : - container_(&container) - { if (container_ != nullptr) iter_ = container_->begin(); } - void init(std::map *container) - { container_ = container; if (container_ != nullptr) iter_=container_->begin();} - void init(std::map &container) - { container_ = &container; if (container_ != nullptr) iter_=container_->begin();} - bool hasNext() { return container_ != nullptr && iter_ != container_->end(); } - VALUE next() { return iter_++->second; } - void next(KEY &key, - VALUE &value) - { key = iter_->first; value = iter_->second; iter_++; } - std::map *container() { return container_; } - - private: - std::map *container_; - typename std::map::iterator iter_; - }; - - class ConstIterator - { - public: - ConstIterator() : container_(nullptr) {} - explicit ConstIterator(const std::map *container) : - container_(container) - { if (container_ != nullptr) iter_ = container_->begin(); } - explicit ConstIterator(const std::map &container) : - container_(&container) - { if (container_ != nullptr) iter_ = container_->begin(); } - void init(const std::map *container) - { container_ = container; if (container_ != nullptr) iter_=container_->begin();} - void init(const std::map &container) - { container_ = &container; if (container_ != nullptr) iter_=container_->begin();} - bool hasNext() { return container_ != nullptr && iter_ != container_->end(); } - VALUE next() { return iter_++->second; } - void next(KEY &key, - VALUE &value) - { key = iter_->first; value = iter_->second; iter_++; } - const std::map *container() { return container_; } - - private: - const std::map *container_; - typename std::map::const_iterator iter_; - }; -}; - -} // namespace diff --git a/include/sta/MinMax.hh b/include/sta/MinMax.hh index 15de0e72..4642c790 100644 --- a/include/sta/MinMax.hh +++ b/include/sta/MinMax.hh @@ -36,8 +36,8 @@ class MinMax; class MinMaxAll; // Use typedefs to make early/late functional equivalents to min/max. -typedef MinMax EarlyLate; -typedef MinMaxAll EarlyLateAll; +using EarlyLate = MinMax; +using EarlyLateAll = MinMaxAll; // Large value used for min/max initial values. extern const float INF; @@ -62,10 +62,10 @@ public: int initValueInt() const { return init_value_int_; } // Max value1 > value2, Min value1 < value2. bool compare(float value1, - float value2) const; + float value2) const; // min/max(value1, value2) float minMax(float value1, - float value2) const; + float value2) const; const MinMaxAll *asMinMaxAll() const; const MinMax *opposite() const; // for range support. @@ -83,18 +83,18 @@ public: private: MinMax(const char *name, - int index, - float init_value, + int index, + float init_value, int init_value_int, - bool (*compare)(float value1, - float value2)); + bool (*compare)(float value1, + float value2)); const std::string name_; int index_; float init_value_; int init_value_int_; bool (*compare_)(float value1, - float value2); + float value2); static const MinMax min_; static const MinMax max_; @@ -112,6 +112,7 @@ public: static const MinMaxAll *max() { return &max_; } static const MinMaxAll *late() { return &max_; } static const MinMaxAll *all() { return &all_; } + static const MinMaxAll *minMax() { return &all_; } const std::string &to_string() const { return name_; } int index() const { return index_; } const MinMax *asMinMax() const; @@ -125,9 +126,9 @@ public: private: MinMaxAll(const char *name, - int index, - std::vector range, - std::vector range_index); + int index, + std::vector range, + std::vector range_index); const std::string name_; int index_; diff --git a/include/sta/MinMaxValues.hh b/include/sta/MinMaxValues.hh index aa302071..6a96ee0b 100644 --- a/include/sta/MinMaxValues.hh +++ b/include/sta/MinMaxValues.hh @@ -82,7 +82,7 @@ public: void setValue(const MinMaxAll *min_max, - TYPE value) + TYPE value) { for (auto mm_index : min_max->rangeIndex()) { values_[mm_index] = value; @@ -92,7 +92,7 @@ public: void setValue(const MinMax *min_max, - TYPE value) + TYPE value) { int mm_index = min_max->index(); values_[mm_index] = value; @@ -101,11 +101,11 @@ public: void mergeValue(const MinMax *min_max, - TYPE value) + TYPE value) { int mm_index = min_max->index(); if (!exists_[mm_index] - || min_max->compare(value, values_[mm_index])) { + || min_max->compare(value, values_[mm_index])) { values_[mm_index] = value; exists_[mm_index] = true; } @@ -126,9 +126,9 @@ public: void value(const MinMax *min_max, - // Return values. - TYPE &value, - bool &exists) const + // Return values. + TYPE &value, + bool &exists) const { int mm_index = min_max->index(); exists = exists_[mm_index]; @@ -150,36 +150,36 @@ public: } static bool equal(const MinMaxValues *values1, - const MinMaxValues *values2) + const MinMaxValues *values2) { return ((!values1->exists_[MinMax::minIndex()] - && !values2->exists_[MinMax::minIndex()]) - || (values1->exists_[MinMax::minIndex()] - && values2->exists_[MinMax::minIndex()] - && values1->values_[MinMax::minIndex()] - == values2->values_[MinMax::minIndex()])) + && !values2->exists_[MinMax::minIndex()]) + || (values1->exists_[MinMax::minIndex()] + && values2->exists_[MinMax::minIndex()] + && values1->values_[MinMax::minIndex()] + == values2->values_[MinMax::minIndex()])) && ((!values1->exists_[MinMax::maxIndex()] - && !values2->exists_[MinMax::maxIndex()]) - || (values1->exists_[MinMax::maxIndex()] - && values2->exists_[MinMax::maxIndex()] - && values1->values_[MinMax::maxIndex()] - == values2->values_[MinMax::maxIndex()])); + && !values2->exists_[MinMax::maxIndex()]) + || (values1->exists_[MinMax::maxIndex()] + && values2->exists_[MinMax::maxIndex()] + && values1->values_[MinMax::maxIndex()] + == values2->values_[MinMax::maxIndex()])); } static int cmp(const MinMaxValues *values1, - const MinMaxValues *values2) + const MinMaxValues *values2) { if (!values1->exists_[MinMax::minIndex()] - && values2->exists_[MinMax::minIndex()]) + && values2->exists_[MinMax::minIndex()]) return -1; if (values1->exists_[MinMax::minIndex()] - && !values2->exists_[MinMax::minIndex()]) + && !values2->exists_[MinMax::minIndex()]) return 1; if (!values1->exists_[MinMax::maxIndex()] - && values2->exists_[MinMax::maxIndex()]) + && values2->exists_[MinMax::maxIndex()]) return -1; if (values1->exists_[MinMax::maxIndex()] - && !values2->exists_[MinMax::maxIndex()]) + && !values2->exists_[MinMax::maxIndex()]) return 1; if (values1->values_[MinMax::minIndex()] < values2->values_[MinMax::minIndex()]) return -1; @@ -197,7 +197,7 @@ private: bool exists_[MinMax::index_count]; }; -typedef MinMaxValues MinMaxFloatValues; -typedef MinMaxValues MinMaxIntValues; +using MinMaxFloatValues = MinMaxValues; +using MinMaxIntValues = MinMaxValues; } // namespace diff --git a/include/sta/Mode.hh b/include/sta/Mode.hh new file mode 100644 index 00000000..0c0827e1 --- /dev/null +++ b/include/sta/Mode.hh @@ -0,0 +1,95 @@ +// OpenSTA, Static Timing Analyzer +// Copyright (c) 2025, Parallax Software, Inc. +// +// This program is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see . +// +// The origin of this software must not be misrepresented; you must not +// claim that you wrote the original software. +// +// Altered source versions must be plainly marked as such, and must not be +// misrepresented as being the original software. +// +// This notice may not be removed or altered from any source distribution. + +#pragma once + +#include + +#include "StaState.hh" + +namespace sta { + +class Sdc; +class Sim; +class ClkNetwork; +class Genclks; +class PathGroups; + +using PathGroupSeq = std::vector; + +// Sdc and dependent state. +class Mode : public StaState +{ +public: + Mode(const std::string &name, + size_t mode_index, + StaState *sta); + virtual ~Mode(); + virtual void copyState(const StaState *sta); + void clear(); + const std::string &name() const { return name_; } + size_t modeIndex() const { return mode_index_; } + const SceneSeq &scenes() const { return scenes_; } + const SceneSet sceneSet() const; + void addScene(Scene *scene); + void removeScene(Scene *scene); + Sdc *sdc() { return sdc_; } + Sdc *sdc() const { return sdc_; } + Sim *sim() { return sim_; } + Sim *sim() const { return sim_; } + ClkNetwork *clkNetwork() { return clk_network_; } + ClkNetwork *clkNetwork() const { return clk_network_; } + Genclks *genclks() { return genclks_; } + Genclks *genclks() const { return genclks_; } + PathGroups *pathGroups() { return path_groups_; } + PathGroups *pathGroups() const { return path_groups_; } + PathGroupSeq pathGroups(const PathEnd *path_end) const; + PathGroups *makePathGroups(int group_path_count, + int endpoint_path_count, + bool unique_pins, + bool unique_edges, + float min_slack, + float max_slack, + StdStringSeq &group_names, + bool setup, + bool hold, + bool recovery, + bool removal, + bool clk_gating_setup, + bool clk_gating_hold, + bool unconstrained_paths); + void deletePathGroups(); + +private: + std::string name_; + size_t mode_index_; + SceneSeq scenes_; + Sdc *sdc_; + Sim *sim_; + ClkNetwork *clk_network_; + Genclks *genclks_; + PathGroups *path_groups_; +}; + +} // namespace diff --git a/include/sta/Mutex.hh b/include/sta/Mutex.hh index 9a96a6ad..943596ed 100644 --- a/include/sta/Mutex.hh +++ b/include/sta/Mutex.hh @@ -29,6 +29,6 @@ namespace sta { // Hide a bit of the std verbosity. -typedef std::lock_guard LockGuard; +using LockGuard = std::lock_guard; } // namespace diff --git a/include/sta/Network.hh b/include/sta/Network.hh index 00566c10..5e88b04c 100644 --- a/include/sta/Network.hh +++ b/include/sta/Network.hh @@ -25,8 +25,8 @@ #pragma once #include +#include -#include "Map.hh" #include "StringUtil.hh" #include "LibertyClass.hh" #include "VertexId.hh" @@ -39,12 +39,12 @@ class Report; class PatternMatch; class PinVisitor; -typedef Map LibertyLibraryMap; +using LibertyLibraryMap = std::map; // Link network function returns top level instance. // Return nullptr if link fails. -typedef std::function LinkNetworkFunc; -typedef Map NetDrvrPinsMap; +using LinkNetworkFunc = std::function; +using NetDrvrPinsMap = std::map; // The Network class defines the network API used by sta. // The interface to a network implementation is constructed by @@ -101,8 +101,8 @@ public: // linking is not necessary because the network has already been expanded. // Return true if successful. virtual bool linkNetwork(const char *top_cell_name, - bool make_black_boxes, - Report *report) = 0; + bool make_black_boxes, + Report *report) = 0; virtual bool isLinked() const; virtual bool isEditable() const { return false; } @@ -117,14 +117,14 @@ public: // Find liberty library by filename. virtual LibertyLibrary *findLibertyFilename(const char *filename); virtual Cell *findCell(const Library *library, - const char *name) const = 0; + const char *name) const = 0; // Search the design (non-liberty) libraries for cells matching pattern. virtual CellSeq findCellsMatching(const Library *library, const PatternMatch *pattern) const = 0; // Search liberty libraries for cell name. virtual LibertyCell *findLibertyCell(const char *name) const; virtual LibertyLibrary *makeLibertyLibrary(const char *name, - const char *filename) = 0; + const char *filename) = 0; // Hook for network after reading liberty library. virtual void readLibertyAfter(LibertyLibrary *library); // First liberty library read is used to look up defaults. @@ -132,10 +132,10 @@ public: virtual LibertyLibrary *defaultLibertyLibrary() const; void setDefaultLibertyLibrary(LibertyLibrary *library); // Check liberty cells used by the network to make sure they exist - // for all the defined corners. - void checkNetworkLibertyCorners(); - // Check liberty cells to make sure they exist for all the defined corners. - void checkLibertyCorners(); + // for all the defined scenes. + void checkNetworkLibertyScenes(); + // Check liberty cells to make sure they exist for all the defined scenes. + void checkLibertyScenes(); //////////////////////////////////////////////////////////////// // Cell functions. @@ -156,7 +156,7 @@ public: virtual const AttributeMap &attributeMap(const Cell *cell) const = 0; // Name can be a simple, bundle, bus, or bus bit name. virtual Port *findPort(const Cell *cell, - const char *name) const = 0; + const char *name) const = 0; virtual PortSeq findPortsMatching(const Cell *cell, const PatternMatch *pattern) const; virtual bool isLeaf(const Cell *cell) const = 0; @@ -182,17 +182,17 @@ public: virtual const char *busName(const Port *port) const = 0; // Bus member, bus[subscript]. virtual Port *findBusBit(const Port *port, - int index) const = 0; + int index) const = 0; virtual int fromIndex(const Port *port) const = 0; virtual int toIndex(const Port *port) const = 0; // Predicate to determine if index is within bus range. // (toIndex > fromIndex) && fromIndex <= index <= toIndex // || (fromIndex > toIndex) && fromIndex >= index >= toIndex bool busIndexInRange(const Port *port, - int index); + int index); // Find Bundle/bus member by index. virtual Port *findMember(const Port *port, - int index) const = 0; + int index) const = 0; // Iterate over the bits of a bus port or members of a bundle. // from_index -> to_index virtual PortMemberIterator *memberIterator(const Port *port) const = 0; @@ -222,13 +222,13 @@ public: // Hierarchical path name. virtual const char *pathName(const Instance *instance) const; bool pathNameLess(const Instance *inst1, - const Instance *inst2) const; + const Instance *inst2) const; int pathNameCmp(const Instance *inst1, - const Instance *inst2) const; + const Instance *inst2) const; // Path from instance up to top level (last in the sequence). void path(const Instance *inst, - // Return value. - InstanceSeq &path) const; + // Return value. + InstanceSeq &path) const; virtual Cell *cell(const Instance *instance) const = 0; virtual const char *cellName(const Instance *instance) const; virtual LibertyLibrary *libertyLibrary(const Instance *instance) const; @@ -237,14 +237,14 @@ public: virtual bool isLeaf(const Instance *instance) const = 0; virtual bool isHierarchical(const Instance *instance) const; virtual Instance *findChild(const Instance *parent, - const char *name) const = 0; + const char *name) const = 0; virtual void findChildrenMatching(const Instance *parent, - const PatternMatch *pattern, + const PatternMatch *pattern, // Return value. InstanceSeq &matches) const; // Is inst inside of hier_inst? bool isInside(const Instance *inst, - const Instance *hier_inst) const; + const Instance *hier_inst) const; // Iterate over all of the leaf instances in the hierarchy // This iterator is not virtual because it can be written in terms of @@ -274,14 +274,14 @@ public: virtual ObjectId id(const Pin *pin) const = 0; virtual Pin *findPin(const char *path_name) const; virtual Pin *findPin(const Instance *instance, - const char *port_name) const = 0; + const char *port_name) const = 0; virtual Pin *findPin(const Instance *instance, - const Port *port) const; + const Port *port) const; virtual Pin *findPin(const Instance *instance, - const LibertyPort *port) const; + const LibertyPort *port) const; // Find pin relative to hierarchical instance. Pin *findPinRelative(const Instance *inst, - const char *path_name) const; + const char *path_name) const; // Default implementation uses linear search. virtual PinSeq findPinsMatching(const Instance *instance, const PatternMatch *pattern) const; @@ -293,9 +293,9 @@ public: // Path name is instance_name/port_name. virtual const char *pathName(const Pin *pin) const; bool pathNameLess(const Pin *pin1, - const Pin *pin2) const; + const Pin *pin2) const; int pathNameCmp(const Pin *pin1, - const Pin *pin2) const; + const Pin *pin2) const; virtual Port *port(const Pin *pin) const = 0; virtual LibertyPort *libertyPort(const Pin *pin) const; virtual Instance *instance(const Pin *pin) const = 0; @@ -303,14 +303,14 @@ public: virtual Term *term(const Pin *pin) const = 0; virtual PortDirection *direction(const Pin *pin) const = 0; virtual bool isLeaf(const Pin *pin) const; - bool isHierarchical(const Pin *pin) const; - bool isTopLevelPort(const Pin *pin) const; + [[nodiscard]] bool isHierarchical(const Pin *pin) const; + [[nodiscard]] bool isTopLevelPort(const Pin *pin) const; // Is pin inside the instance hier_pin is attached to? bool isInside(const Pin *pin, - const Pin *hier_pin) const; + const Pin *hier_pin) const; // Is pin inside of hier_inst? bool isInside(const Pin *pin, - const Instance *hier_inst) const; + const Instance *hier_inst) const; bool isDriver(const Pin *pin) const; bool isLoad(const Pin *pin) const; // Has register/latch rise/fall edges from pin. @@ -324,23 +324,23 @@ public: // hierarchical pins). virtual PinConnectedPinIterator *connectedPinIterator(const Pin *pin) const; virtual void visitConnectedPins(const Pin *pin, - PinVisitor &visitor) const; + PinVisitor &visitor) const; // Find driver pins for the net connected to pin. // Return value is owned by the network. virtual PinSet *drivers(const Pin *pin); virtual bool pinLess(const Pin *pin1, - const Pin *pin2) const; + const Pin *pin2) const; // Return the id of the pin graph vertex. virtual VertexId vertexId(const Pin *pin) const = 0; virtual void setVertexId(Pin *pin, - VertexId id) = 0; + VertexId id) = 0; // Return the physical X/Y coordinates of the pin. virtual void location(const Pin *pin, - // Return values. - double &x, - double &y, - bool &exists) const; + // Return values. + double &x, + double &y, + bool &exists) const; int pinCount(); int pinCount(Instance *inst); @@ -369,7 +369,7 @@ public: virtual NetSeq findNetsMatching(const Instance *context, const PatternMatch *pattern) const; virtual Net *findNet(const Instance *instance, - const char *net_name) const = 0; + const char *net_name) const = 0; // Traverse the hierarchy from instance down and find nets matching // pattern of the form instance_name/net_name. virtual NetSeq findNetsHierMatching(const Instance *instance, @@ -380,25 +380,25 @@ public: NetSeq &matches) const = 0; virtual const char *pathName(const Net *net) const; bool pathNameLess(const Net *net1, - const Net *net2) const; + const Net *net2) const; int pathNameCmp(const Net *net1, - const Net *net2) const; + const Net *net2) const; virtual Instance *instance(const Net *net) const = 0; // Is net inside of hier_inst? virtual bool isInside(const Net *net, - const Instance *hier_inst) const; + const Instance *hier_inst) const; // Is pin connected to net anywhere in the hierarchy? virtual bool isConnected(const Net *net, - const Pin *pin) const; + const Pin *pin) const; // Is net1 connected to net2 anywhere in the hierarchy? virtual bool isConnected(const Net *net1, - const Net *net2) const; + const Net *net2) const; virtual Net *highestNetAbove(Net *net) const; virtual const Net *highestConnectedNet(Net *net) const; virtual void connectedNets(Net *net, - NetSet *nets) const; + NetSet *nets) const; virtual void connectedNets(const Pin *pin, - NetSet *nets) const; + NetSet *nets) const; virtual bool isPower(const Net *net) const = 0; virtual bool isGround(const Net *net) const = 0; @@ -411,7 +411,7 @@ public: // hierarchical pins). virtual NetConnectedPinIterator *connectedPinIterator(const Net *net) const; virtual void visitConnectedPins(const Net *net, - PinVisitor &visitor) const; + PinVisitor &visitor) const; // Find driver pins for net. // Return value is owned by the network. virtual PinSet *drivers(const Net *net); @@ -427,14 +427,14 @@ public: // first and tail are both null if there are no dividers in path. // Caller must delete first and tail. void pathNameFirst(const char *path_name, - char *&first, - char *&tail) const; + char *&first, + char *&tail) const; // Parse path into head/last (last hierarchy divider separated token). // head and last are both null if there are no dividers in path. // Caller must delete head and last. void pathNameLast(const char *path_name, - char *&head, - char *&last) const; + char *&head, + char *&last) const; // Divider between instance names in a hierarchical path name. virtual char pathDivider() const { return divider_; } @@ -445,11 +445,11 @@ public: protected: Pin *findPinLinear(const Instance *instance, - const char *port_name) const; + const char *port_name) const; void findInstancesMatching1(const Instance *context, - size_t context_name_length, - const PatternMatch *pattern, - InstanceSeq &insts) const; + size_t context_name_length, + const PatternMatch *pattern, + InstanceSeq &insts) const; void findInstancesHierMatching1(const Instance *instance, const PatternMatch *pattern, InstanceSeq &matches) const; @@ -464,15 +464,15 @@ protected: // Return value. PinSeq &matches) const; bool isConnected(const Net *net, - const Pin *pin, - NetSet &nets) const; + const Pin *pin, + NetSet &nets) const; bool isConnected(const Net *net1, - const Net *net2, - NetSet &nets) const; + const Net *net2, + NetSet &nets) const; int hierarchyLevel(const Net *net) const; virtual void visitConnectedPins(const Net *net, - PinVisitor &visitor, - NetSet &visited_nets) const; + PinVisitor &visitor, + NetSet &visited_nets) const; // Default implementation uses linear search. virtual void findInstPinsMatching(const Instance *instance, const PatternMatch *pattern, @@ -484,7 +484,7 @@ protected: PinSeq &matches) const; // findNet using linear search. Net *findNetLinear(const Instance *instance, - const char *net_name) const; + const char *net_name) const; // findNetsMatching using linear search. NetSeq findNetsMatchingLinear(const Instance *instance, const PatternMatch *pattern) const; @@ -506,33 +506,33 @@ public: NetworkEdit(); virtual bool isEditable() const { return true; } virtual Instance *makeInstance(LibertyCell *cell, - const char *name, - Instance *parent) = 0; + const char *name, + Instance *parent) = 0; virtual void makePins(Instance *inst) = 0; virtual void replaceCell(Instance *inst, - Cell *cell) = 0; + Cell *cell) = 0; // Deleting instance also deletes instance pins. virtual void deleteInstance(Instance *inst) = 0; // Connect the port on an instance to a net. virtual Pin *connect(Instance *inst, - Port *port, - Net *net) = 0; + Port *port, + Net *net) = 0; virtual Pin *connect(Instance *inst, - LibertyPort *port, - Net *net) = 0; + LibertyPort *port, + Net *net) = 0; // makePin/connectPin replaced by connect. // deprecated 2018-09-28 virtual void connectPin(Pin *pin, - Net *net) __attribute__ ((deprecated)); + Net *net) __attribute__ ((deprecated)); // Disconnect pin from net. virtual void disconnectPin(Pin *pin) = 0; virtual void deletePin(Pin *pin) = 0; virtual Net *makeNet(const char *name, - Instance *parent) = 0; + Instance *parent) = 0; // Deleting net disconnects (but does not delete) net pins. virtual void deleteNet(Net *net) = 0; virtual void mergeInto(Net *net, - Net *into_net) = 0; + Net *into_net) = 0; virtual Net *mergedInto(Net *net) = 0; }; @@ -545,19 +545,19 @@ public: virtual void readNetlistBefore() = 0; virtual void setLinkFunc(LinkNetworkFunc link) = 0; virtual Library *makeLibrary(const char *name, - const char *filename) = 0; + const char *filename) = 0; virtual void deleteLibrary(Library *library) = 0; // Search the libraries in read order for a cell by name. virtual Cell *findAnyCell(const char *name) = 0; virtual Cell *makeCell(Library *library, - const char *name, - bool is_leaf, - const char *filename) = 0; + const char *name, + bool is_leaf, + const char *filename) = 0; virtual void deleteCell(Cell *cell) = 0; virtual void setName(Cell *cell, - const char *name) = 0; + const char *name) = 0; virtual void setIsLeaf(Cell *cell, - bool is_leaf) = 0; + bool is_leaf) = 0; virtual void setAttribute(Cell *cell, const std::string &key, const std::string &value) = 0; @@ -565,42 +565,42 @@ public: const std::string &key, const std::string &value) = 0; virtual Port *makePort(Cell *cell, - const char *name) = 0; + const char *name) = 0; virtual Port *makeBusPort(Cell *cell, - const char *name, - int from_index, - int to_index) = 0; + const char *name, + int from_index, + int to_index) = 0; virtual void groupBusPorts(Cell *cell, std::function port_msb_first) = 0; virtual Port *makeBundlePort(Cell *cell, - const char *name, - PortSeq *members) = 0; + const char *name, + PortSeq *members) = 0; virtual Instance *makeInstance(Cell *cell, - const char *name, - Instance *parent) = 0; + const char *name, + Instance *parent) = 0; virtual Pin *makePin(Instance *inst, - Port *port, - Net *net) = 0; + Port *port, + Net *net) = 0; virtual Term *makeTerm(Pin *pin, - Net *net) = 0; + Net *net) = 0; virtual void setDirection(Port *port, - PortDirection *dir) = 0; + PortDirection *dir) = 0; // Instance is the network view for cell. virtual void setCellNetworkView(Cell *cell, - Instance *inst) = 0; + Instance *inst) = 0; virtual Instance *cellNetworkView(Cell *cell) = 0; virtual void deleteCellNetworkViews() = 0; virtual void addConstantNet(Net *net, - LogicValue const_value) = 0; + LogicValue const_value) = 0; using NetworkEdit::makeInstance; }; Instance * linkReaderNetwork(Cell *top_cell, - bool make_black_boxes, - Report *report, - NetworkReader *network); + bool make_black_boxes, + Report *report, + NetworkReader *network); // Abstract class for Network::constantPinIterator(). class ConstantPinIterator @@ -610,7 +610,7 @@ public: virtual ~ConstantPinIterator() {} virtual bool hasNext() = 0; virtual void next(const Pin *&pin, - LogicValue &value) = 0; + LogicValue &value) = 0; }; // Implementation class for Network::constantPinIterator(). @@ -618,20 +618,20 @@ class NetworkConstantPinIterator : public ConstantPinIterator { public: NetworkConstantPinIterator(const Network *network, - NetSet &zero_nets, - NetSet &one_nets); - ~NetworkConstantPinIterator(); + NetSet &zero_nets, + NetSet &one_nets); + virtual ~NetworkConstantPinIterator() {} virtual bool hasNext(); virtual void next(const Pin *&pin, LogicValue &value); private: void findConstantPins(NetSet &nets, - PinSet &pins); + PinSet &pins); const Network *network_; PinSet constant_pins_[2]; LogicValue value_; - PinSet::Iterator *pin_iter_; + PinSet::iterator pin_iter_; }; // Abstract base class for visitDrvrLoadsThruHierPin visitor. @@ -641,7 +641,7 @@ public: HierPinThruVisitor() {} virtual ~HierPinThruVisitor() {} virtual void visit(const Pin *drvr, - const Pin *load) = 0; + const Pin *load) = 0; }; class PinVisitor @@ -655,10 +655,10 @@ class FindNetDrvrLoads : public PinVisitor { public: FindNetDrvrLoads(const Pin *drvr_pin, - PinSet &visited_drvrs, - PinSeq &loads, - PinSeq &drvrs, - const Network *network); + PinSet &visited_drvrs, + PinSeq &loads, + PinSeq &drvrs, + const Network *network); virtual void operator()(const Pin *pin); protected: @@ -672,12 +672,12 @@ protected: // Visit driver/loads pins through a hierarcial pin. void visitDrvrLoadsThruHierPin(const Pin *hpin, - const Network *network, - HierPinThruVisitor *visitor); + const Network *network, + HierPinThruVisitor *visitor); void visitDrvrLoadsThruNet(const Net *net, - const Network *network, - HierPinThruVisitor *visitor); + const Network *network, + HierPinThruVisitor *visitor); char logicValueString(LogicValue value); diff --git a/include/sta/NetworkClass.hh b/include/sta/NetworkClass.hh index 8241481e..9e72fef6 100644 --- a/include/sta/NetworkClass.hh +++ b/include/sta/NetworkClass.hh @@ -26,10 +26,11 @@ #include #include +#include #include +#include +#include -#include "Set.hh" -#include "Vector.hh" #include "Iterator.hh" namespace sta { @@ -49,30 +50,31 @@ class ConstantPinIterator; class ViewType; class LibertyLibrary; -typedef Iterator LibraryIterator; -typedef Iterator LibertyLibraryIterator; -typedef Vector CellSeq; -typedef Vector PortSeq; -typedef Iterator CellPortIterator; -typedef Iterator CellPortBitIterator; -typedef Iterator PortMemberIterator; +using LibraryIterator = Iterator; +using LibertyLibraryIterator = Iterator; +using CellSeq = std::vector; +using PortSeq = std::vector; +using CellPortIterator = Iterator; +using CellPortBitIterator = Iterator; +using PortMemberIterator = Iterator; -typedef Vector PinSeq; -typedef Vector InstanceSeq; -typedef Vector NetSeq; -typedef std::vector ConstNetSeq; -typedef Iterator InstanceChildIterator; -typedef Iterator InstancePinIterator; -typedef Iterator InstanceNetIterator; -typedef Iterator LeafInstanceIterator; -typedef Iterator NetIterator; -typedef Iterator NetPinIterator; -typedef Iterator NetTermIterator; -typedef Iterator ConnectedPinIterator; -typedef ConnectedPinIterator NetConnectedPinIterator; -typedef ConnectedPinIterator PinConnectedPinIterator; -typedef uint32_t ObjectId; -typedef std::map AttributeMap; +using PinSeq = std::vector; +using PinUnorderedSet = std::unordered_set; +using InstanceSeq = std::vector; +using NetSeq = std::vector; +using ConstNetSeq = std::vector; +using InstanceChildIterator = Iterator; +using InstancePinIterator = Iterator; +using InstanceNetIterator = Iterator; +using LeafInstanceIterator = Iterator; +using NetIterator = Iterator; +using NetPinIterator = Iterator; +using NetTermIterator = Iterator; +using ConnectedPinIterator = Iterator; +using NetConnectedPinIterator = ConnectedPinIterator; +using PinConnectedPinIterator = ConnectedPinIterator; +using ObjectId = uint32_t; +using AttributeMap = std::map; enum class LogicValue : unsigned { zero, one, unknown, rise, fall }; @@ -138,55 +140,37 @@ private: //////////////////////////////////////////////////////////////// -class CellSet : public Set +class CellSet : public std::set { public: CellSet(const Network *network); }; -class PortSet : public Set +class PortSet : public std::set { public: PortSet(const Network *network); }; -class InstanceSet : public Set +class InstanceSet : public std::set { public: InstanceSet(); InstanceSet(const Network *network); - static int compare(const InstanceSet *set1, - const InstanceSet *set2, - const Network *network); - static bool intersects(const InstanceSet *set1, - const InstanceSet *set2, - const Network *network); }; -class PinSet : public Set +class PinSet : public std::set { public: PinSet(); PinSet(const Network *network); - static int compare(const PinSet *set1, - const PinSet *set2, - const Network *network); - static bool intersects(const PinSet *set1, - const PinSet *set2, - const Network *network); }; -class NetSet : public Set +class NetSet : public std::set { public: NetSet(); NetSet(const Network *network); - static int compare(const NetSet *set1, - const NetSet *set2, - const Network *network); - static bool intersects(const NetSet *set1, - const NetSet *set2, - const Network *network); }; } // namespace diff --git a/include/sta/NetworkCmp.hh b/include/sta/NetworkCmp.hh index c343ccab..dd7b871f 100644 --- a/include/sta/NetworkCmp.hh +++ b/include/sta/NetworkCmp.hh @@ -34,9 +34,9 @@ namespace sta { class PortNameLess { public: - explicit PortNameLess(const Network *network); + PortNameLess(const Network *network); bool operator()(const Port *port1, - const Port *port2) const; + const Port *port2) const; private: const Network *network_; @@ -45,9 +45,9 @@ private: class PinPathNameLess { public: - explicit PinPathNameLess(const Network *network); + PinPathNameLess(const Network *network); bool operator()(const Pin *pin1, - const Pin *pin2) const; + const Pin *pin2) const; private: const Network *network_; @@ -56,9 +56,9 @@ private: class InstancePathNameLess { public: - explicit InstancePathNameLess(const Network *network); + InstancePathNameLess(const Network *network); bool operator()(const Instance *inst1, - const Instance *inst2) const; + const Instance *inst2) const; private: const Network *network_; @@ -67,9 +67,9 @@ private: class NetPathNameLess { public: - explicit NetPathNameLess(const Network *network); + NetPathNameLess(const Network *network); bool operator()(const Net *net1, - const Net *net2) const; + const Net *net2) const; private: const Network *network_; @@ -78,6 +78,9 @@ private: PinSeq sortByPathName(const PinSet *set, const Network *network); +PinSeq +sortByPathName(const PinUnorderedSet *set, + const Network *network); PortSeq sortByName(const PortSet *set, const Network *network); diff --git a/include/sta/ObjectId.hh b/include/sta/ObjectId.hh index 6f3b7703..b4c04ef7 100644 --- a/include/sta/ObjectId.hh +++ b/include/sta/ObjectId.hh @@ -29,11 +29,11 @@ namespace sta { // ObjectId is block index and object index within the block. -typedef uint32_t ObjectId; +using ObjectId = uint32_t; // Block index. -typedef uint32_t BlockIdx; +using BlockIdx = uint32_t; // Object index within a block. -typedef uint32_t ObjectIdx; +using ObjectIdx = uint32_t; static constexpr int object_id_bits = sizeof(ObjectId) * 8; static constexpr BlockIdx block_idx_null = 0; diff --git a/include/sta/ObjectTable.hh b/include/sta/ObjectTable.hh index 3c752178..515d476a 100644 --- a/include/sta/ObjectTable.hh +++ b/include/sta/ObjectTable.hh @@ -24,7 +24,9 @@ #pragma once -#include "Vector.hh" +#include + +#include "ContainerHelpers.hh" #include "Error.hh" #include "ObjectId.hh" @@ -66,12 +68,12 @@ public: private: void makeBlock(); void freePush(TYPE *object, - ObjectId id); + ObjectId id); size_t size_; // Object ID of next free object. ObjectId free_; - Vector*> blocks_; + std::vector*> blocks_; static constexpr ObjectId idx_mask_ = block_object_count - 1; }; @@ -85,7 +87,7 @@ ObjectTable::ObjectTable() : template ObjectTable::~ObjectTable() { - blocks_.deleteContents(); + deleteContents(blocks_); } template @@ -106,7 +108,7 @@ ObjectTable::make() template void ObjectTable::freePush(TYPE *object, - ObjectId id) + ObjectId id) { // Link free objects into a list linked by Object ID. ObjectId *free_next = reinterpret_cast(object); @@ -181,7 +183,7 @@ template void ObjectTable::clear() { - blocks_.deleteContentsClear(); + deleteContents(blocks_);; size_ = 0; } @@ -192,7 +194,7 @@ class TableBlock { public: TableBlock(BlockIdx block_idx, - ObjectTable *table); + ObjectTable *table); BlockIdx index() const { return block_idx_; } TYPE &ref(ObjectIdx idx) { return objects_[idx]; } TYPE *pointer(ObjectIdx idx) { return &objects_[idx]; } @@ -205,7 +207,7 @@ private: template TableBlock::TableBlock(BlockIdx block_idx, - ObjectTable *table) : + ObjectTable *table) : block_idx_(block_idx), table_(table) { diff --git a/include/sta/Parasitics.hh b/include/sta/Parasitics.hh index 948843f2..bd2a0940 100644 --- a/include/sta/Parasitics.hh +++ b/include/sta/Parasitics.hh @@ -37,46 +37,42 @@ namespace sta { class Wireload; -class Corner; +class Scene; -typedef std::complex ComplexFloat; -typedef Vector ComplexFloatSeq; -typedef std::vector ParasiticNodeSeq; -typedef std::vector ParasiticResistorSeq; -typedef std::vector ParasiticCapacitorSeq; -typedef std::map ParasiticNodeResistorMap; -typedef std::map ParasiticNodeCapacitorMap; +using ComplexFloat = std::complex; +using ComplexFloatSeq = std::vector; +using ParasiticNodeSeq = std::vector; +using ParasiticResistorSeq = std::vector; +using ParasiticCapacitorSeq = std::vector; +using ParasiticNodeResistorMap = std::map; +using ParasiticNodeCapacitorMap = std::map; // Parasitics API. -// All parasitic parameters can have multiple values, each corresponding -// to an analysis point. -// Parasitic annotation for a pin or net may exist for one analysis point -// and not another. class Parasitics : public StaState { public: Parasitics(StaState *sta); virtual ~Parasitics() {} + virtual const std::string &name() const = 0; + virtual const std::string &filename() const = 0; virtual bool haveParasitics() = 0; + // Clear all state. virtual void clear() = 0; // Delete all parasitics. virtual void deleteParasitics() = 0; // Delete all parasitics on net at analysis point. - virtual void deleteParasitics(const Net *net, - const ParasiticAnalysisPt *ap) = 0; + virtual void deleteParasitics(const Net *net) = 0; // Delete all parasitics on pin at analysis point. - virtual void deleteParasitics(const Pin *pin, - const ParasiticAnalysisPt *ap) = 0; - virtual void deleteReducedParasitics(const Net *net, - const ParasiticAnalysisPt *ap) = 0; + virtual void deleteParasitics(const Pin *pin) = 0; + virtual void deleteReducedParasitics(const Net *net) = 0; virtual void deleteDrvrReducedParasitics(const Pin *drvr_pin) = 0; virtual bool isReducedParasiticNetwork(const Parasitic *parasitic) const = 0; // Flag this parasitic as reduced from a parasitic network. virtual void setIsReducedParasiticNetwork(Parasitic *parasitic, - bool is_reduced) = 0; + bool is_reduced) = 0; // Capacitance value of parasitic object. virtual float capacitance(const Parasitic *parasitic) const = 0; @@ -87,89 +83,83 @@ public: // capacitor on the driver pin. virtual bool isPiElmore(const Parasitic *parasitic) const = 0; virtual Parasitic *findPiElmore(const Pin *drvr_pin, - const RiseFall *rf, - const ParasiticAnalysisPt *ap) const = 0; + const RiseFall *rf, + const MinMax *min_max) const = 0; virtual Parasitic *makePiElmore(const Pin *drvr_pin, - const RiseFall *rf, - const ParasiticAnalysisPt *ap, - float c2, - float rpi, - float c1) = 0; + const RiseFall *rf, + const MinMax *min_max, + float c2, + float rpi, + float c1) = 0; //////////////////////////////////////////////////////////////// // Pi models are common to PiElmore and PiPoleResidue. virtual bool isPiModel(const Parasitic *parasitic) const = 0; virtual void piModel(const Parasitic *parasitic, - float &c2, - float &rpi, - float &c1) const = 0; + float &c2, + float &rpi, + float &c1) const = 0; // Set PI model parameters. virtual void setPiModel(Parasitic *parasitic, - float c2, - float rpi, - float c1) = 0; + float c2, + float rpi, + float c1) = 0; //////////////////////////////////////////////////////////////// // Elmore driver to load delay. // Common to LumpedElmore and PiElmore parasitics. virtual void findElmore(const Parasitic *parasitic, - const Pin *load_pin, - float &elmore, - bool &exists) const = 0; + const Pin *load_pin, + float &elmore, + bool &exists) const = 0; // Set load elmore delay. virtual void setElmore(Parasitic *parasitic, - const Pin *load_pin, - float elmore) = 0; + const Pin *load_pin, + float elmore) = 0; //////////////////////////////////////////////////////////////// // Pi model driver load with pole/residue interconnect model to load pins. virtual bool isPiPoleResidue(const Parasitic* parasitic) const = 0; virtual Parasitic *findPiPoleResidue(const Pin *drvr_pin, - const RiseFall *rf, - const ParasiticAnalysisPt *ap) const=0; + const RiseFall *rf, + const MinMax *min_max) const = 0; virtual Parasitic *makePiPoleResidue(const Pin *drvr_pin, - const RiseFall *rf, - const ParasiticAnalysisPt *ap, - float c2, - float rpi, - float c1) = 0; + const RiseFall *rf, + const MinMax *min_max, + float c2, + float rpi, + float c1) = 0; virtual Parasitic *findPoleResidue(const Parasitic *parasitic, - const Pin *load_pin) const = 0; + const Pin *load_pin) const = 0; // Make pole/residue model for load_pin. virtual void setPoleResidue(Parasitic *parasitic, - const Pin *load_pin, - ComplexFloatSeq *poles, - ComplexFloatSeq *residues) = 0; + const Pin *load_pin, + ComplexFloatSeq *poles, + ComplexFloatSeq *residues) = 0; virtual bool isPoleResidue(const Parasitic* parasitic) const = 0; // Return the number of poles and residues in a pole/residue parasitic. virtual size_t poleResidueCount(const Parasitic *parasitic) const = 0; // Find the pole_index'th pole/residue in a pole/residue parasitic. virtual void poleResidue(const Parasitic *parasitic, - int pole_index, - ComplexFloat &pole, - ComplexFloat &residue) const = 0; + int pole_index, + ComplexFloat &pole, + ComplexFloat &residue) const = 0; //////////////////////////////////////////////////////////////// // Parasitic Network (detailed parasitics). // This api assumes that parasitic networks are not rise/fall // dependent because they do not include pin capacitances. virtual bool isParasiticNetwork(const Parasitic *parasitic) const = 0; - virtual Parasitic *findParasiticNetwork(const Net *net, - const ParasiticAnalysisPt *ap) const = 0; - virtual Parasitic *findParasiticNetwork(const Pin *pin, - const ParasiticAnalysisPt *ap) const = 0; + virtual Parasitic *findParasiticNetwork(const Net *net) = 0; + virtual Parasitic *findParasiticNetwork(const Pin *pin) = 0; virtual Parasitic *makeParasiticNetwork(const Net *net, - bool includes_pin_caps, - const ParasiticAnalysisPt *ap) = 0; + bool includes_pin_caps) = 0; virtual ParasiticNodeSeq nodes(const Parasitic *parasitic) const = 0; virtual void report(const Parasitic *parasitic) const; virtual const Net *net(const Parasitic *parasitic) const = 0; virtual ParasiticResistorSeq resistors(const Parasitic *parasitic) const = 0; virtual ParasiticCapacitorSeq capacitors(const Parasitic *parasitic) const = 0; - // Delete parasitic network if it exists. - virtual void deleteParasiticNetwork(const Net *net, - const ParasiticAnalysisPt *ap) = 0; - virtual void deleteParasiticNetworks(const Net *net) = 0; + virtual void deleteParasiticNetwork(const Net *net) = 0; // True if the parasitic network caps include pin capacitances. virtual bool includesPinCaps(const Parasitic *parasitic) const = 0; // Parasitic network component builders. @@ -179,22 +169,22 @@ public: const Network *network) const = 0; // Make a subnode of the parasitic network net. virtual ParasiticNode *ensureParasiticNode(Parasitic *parasitic, - const Net *net, - int id, + const Net *net, + int id, const Network *network) = 0; // Find the parasitic node connected to pin. virtual ParasiticNode *findParasiticNode(const Parasitic *parasitic, const Pin *pin) const = 0; // deprecated 2024-02-27 virtual ParasiticNode *findNode(const Parasitic *parasitic, - const Pin *pin) const __attribute__ ((deprecated)); + const Pin *pin) const __attribute__ ((deprecated)); // Make a subnode of the parasitic network net connected to pin. virtual ParasiticNode *ensureParasiticNode(Parasitic *parasitic, - const Pin *pin, + const Pin *pin, const Network *network) = 0; // Increment the grounded capacitance on node. virtual void incrCap(ParasiticNode *node, - float cap) = 0; + float cap) = 0; virtual const char *name(const ParasiticNode *node) const = 0; virtual const Pin *pin(const ParasiticNode *node) const = 0; virtual const Net *net(const ParasiticNode *node, @@ -218,10 +208,10 @@ public: ParasiticNode *node) const; virtual void makeResistor(Parasitic *parasitic, - size_t id, - float res, + size_t id, + float res, ParasiticNode *node1, - ParasiticNode *node2) = 0; + ParasiticNode *node2) = 0; virtual size_t id(const ParasiticResistor *resistor) const = 0; virtual float value(const ParasiticResistor *resistor) const = 0; virtual ParasiticNode *node1(const ParasiticResistor *resistor) const = 0; @@ -248,17 +238,15 @@ public: Parasitic *reduceToPiElmore(const Parasitic *parasitic, const Pin *drvr_pin, const RiseFall *rf, - const Corner *corner, - const MinMax *cnst_min_max, - const ParasiticAnalysisPt *ap); + const Scene *scene, + const MinMax *min_max); // Reduce parasitic network to pi and 2nd order pole/residue models // for drvr_pin. Parasitic *reduceToPiPoleResidue2(const Parasitic *parasitic, const Pin *drvr_pin, const RiseFall *rf, - const Corner *corner, - const MinMax *cnst_min_max, - const ParasiticAnalysisPt *ap); + const Scene *scene, + const MinMax *min_max); // Estimate parasitic as pi elmore using wireload model. Parasitic *estimatePiElmore(const Pin *drvr_pin, @@ -266,67 +254,49 @@ public: const Wireload *wireload, float fanout, float net_pin_cap, - const Corner *corner, + const Scene *scene, const MinMax *min_max); Parasitic *makeWireloadNetwork(const Pin *drvr_pin, - const Wireload *wireload, - float fanout, - const MinMax *min_max, - const ParasiticAnalysisPt *ap); + const Wireload *wireload, + float fanout, + const Scene *scene, + const MinMax *min_max); // Network edit before/after methods. - virtual void disconnectPinBefore(const Pin *pin, - const Network *network) = 0; + virtual void disconnectPinBefore(const Pin *pin) = 0; virtual void deletePinBefore(const Pin *pin) = 0; virtual void loadPinCapacitanceChanged(const Pin *pin) = 0; - -protected: - void makeWireloadNetworkWorst(Parasitic *parasitic, - const Pin *drvr_pin, - const Net *net, - float wireload_cap, - float wireload_res, - float fanout); - void makeWireloadNetworkBest(Parasitic *parasitic, - const Pin *drvr_pin, - float wireload_cap, - float wireload_res, - float fanout); - void makeWireloadNetworkBalanced(Parasitic *parasitic, - const Pin *drvr_pin, - float wireload_cap, - float wireload_res, - float fanout); - - const Net *findParasiticNet(const Pin *pin) const; -}; - -// Managed by the Corner class. -class ParasiticAnalysisPt -{ -public: - ParasiticAnalysisPt(const char *name, - int index, - int index_max); - const char *name() const { return name_.c_str(); } - int index() const { return index_; } - int indexMax() const { return index_max_; } - // Coupling capacitor factor used by all reduction functions. float couplingCapFactor() const { return coupling_cap_factor_; } void setCouplingCapFactor(float factor); -private: - std::string name_; - int index_; - int index_max_; +protected: + void makeWireloadNetworkWorst(Parasitic *parasitic, + const Pin *drvr_pin, + const Net *net, + float wireload_cap, + float wireload_res, + float fanout); + void makeWireloadNetworkBest(Parasitic *parasitic, + const Pin *drvr_pin, + float wireload_cap, + float wireload_res, + float fanout); + void makeWireloadNetworkBalanced(Parasitic *parasitic, + const Pin *drvr_pin, + float wireload_cap, + float wireload_res, + float fanout); + + const Net *findParasiticNet(const Pin *pin) const; + float coupling_cap_factor_; }; class ParasiticNodeLess { public: + ParasiticNodeLess(); ParasiticNodeLess(const Parasitics *parasitics, const Network *network); - ParasiticNodeLess(const ParasiticNodeLess &less); bool operator()(const ParasiticNode *node1, const ParasiticNode *node2) const; private: diff --git a/include/sta/ParasiticsClass.hh b/include/sta/ParasiticsClass.hh index 2d35781d..02a7e2e4 100644 --- a/include/sta/ParasiticsClass.hh +++ b/include/sta/ParasiticsClass.hh @@ -29,7 +29,6 @@ namespace sta { class Parasitics; class Parasitic; class ParasiticNode; -class ParasiticAnalysisPt; class ParasiticResistor; class ParasiticCapacitor; diff --git a/include/sta/ParseBus.hh b/include/sta/ParseBus.hh index a7058efd..a33daf01 100644 --- a/include/sta/ParseBus.hh +++ b/include/sta/ParseBus.hh @@ -31,9 +31,9 @@ namespace sta { // Return true if name is a bus. bool isBusName(const char *name, - const char brkt_left, - const char brkt_right, - char escape); + const char brkt_left, + const char brkt_right, + char escape); // Parse name as a bus. // signal @@ -44,23 +44,23 @@ isBusName(const char *name, // Caller must delete returned bus_name string. void parseBusName(const char *name, - const char brkt_left, - const char brkt_right, - char escape, - // Return values. - bool &is_bus, + const char brkt_left, + const char brkt_right, + char escape, + // Return values. + bool &is_bus, std::string &bus_name, - int &index); + int &index); // Allow multiple different left/right bus brackets. void parseBusName(const char *name, - const char *brkts_left, - const char *brkts_right, - char escape, - // Return values. - bool &is_bus, - std::string &bus_name, - int &index); + const char *brkts_left, + const char *brkts_right, + char escape, + // Return values. + bool &is_bus, + std::string &bus_name, + int &index); // Parse a bus range, such as BUS[4:0]. // bus_name is set to null if name is not a range. @@ -96,8 +96,8 @@ parseBusName(const char *name, // Insert escapes before ch1 and ch2 in token. std::string escapeChars(const char *token, - const char ch1, - const char ch2, - const char escape); + const char ch1, + const char ch2, + const char escape); } // namespace diff --git a/include/sta/Path.hh b/include/sta/Path.hh index 09763f73..bf938249 100644 --- a/include/sta/Path.hh +++ b/include/sta/Path.hh @@ -35,8 +35,6 @@ namespace sta { -class DcalcAnalysisPt; - class Path { public: @@ -60,7 +58,6 @@ public: TimingArc *prev_arc, bool is_enum, const StaState *sta); - ~Path(); std::string to_string(const StaState *sta) const; bool isNull() const; // prev_path null @@ -86,6 +83,9 @@ public: VertexId vertexId(const StaState *sta) const; Pin *pin(const StaState *sta) const; Tag *tag(const StaState *sta) const; + Scene *scene(const StaState *sta) const; + Mode *mode(const StaState *sta) const; + Sdc *sdc(const StaState *sta) const; TagIndex tagIndex(const StaState *sta) const; void setTag(Tag *tag); size_t pathIndex(const StaState *sta) const; @@ -96,9 +96,8 @@ public: const RiseFall *transition(const StaState *sta) const; int rfIndex(const StaState *sta) const; const MinMax *minMax(const StaState *sta) const; - PathAnalysisPt *pathAnalysisPt(const StaState *sta) const; PathAPIndex pathAnalysisPtIndex(const StaState *sta) const; - DcalcAnalysisPt *dcalcAnalysisPt(const StaState *sta) const; + DcalcAPIndex dcalcAnalysisPtIndex(const StaState *sta) const; Arrival &arrival() { return arrival_; } const Arrival &arrival() const { return arrival_; } void setArrival(Arrival arrival); @@ -121,6 +120,8 @@ public: void setIsEnum(bool is_enum); void checkPrevPath(const StaState *sta) const; + const MinMax *tgtClkMinMax(const StaState *sta) const; + static Path *vertexPath(const Path *path, const StaState *sta); static Path *vertexPath(const Path &path, @@ -130,34 +131,34 @@ public: const StaState *sta); static bool less(const Path *path1, - const Path *path2, - const StaState *sta); + const Path *path2, + const StaState *sta); static int cmp(const Path *path1, - const Path *path2, - const StaState *sta); + const Path *path2, + const StaState *sta); // Compare all path attributes (vertex, transition, tag, analysis point). static bool equal(const Path *path1, - const Path *path2, - const StaState *sta); + const Path *path2, + const StaState *sta); // Compare pin name and transition and source clock edge. static int cmpPinTrClk(const Path *path1, - const Path *path2, - const StaState *sta); + const Path *path2, + const StaState *sta); // Compare source clock edge. static int cmpClk(const Path *path1, - const Path *path2, - const StaState *sta); + const Path *path2, + const StaState *sta); // Compare vertex, transition, path ap and tag without crpr clk pin. static int cmpNoCrpr(const Path *path1, - const Path *path2, - const StaState *sta); + const Path *path2, + const StaState *sta); // Search back on each path until finding a difference. static int cmpAll(const Path *path1, - const Path *path2, - const StaState *sta); + const Path *path2, + const StaState *sta); static bool lessAll(const Path *path1, - const Path *path2, - const StaState *sta); + const Path *path2, + const StaState *sta); protected: Path *prev_path_; @@ -176,9 +177,9 @@ protected: class PathLess { public: - explicit PathLess(const StaState *sta); + PathLess(const StaState *sta); bool operator()(const Path *path1, - const Path *path2) const; + const Path *path2) const; protected: const StaState *sta_; @@ -190,22 +191,16 @@ class VertexPathIterator : public Iterator public: // Iterate over all vertex paths. VertexPathIterator(Vertex *vertex, - const StaState *sta); - // Iterate over vertex paths with the same transition and - // analysis pt but different tags. + const StaState *sta); VertexPathIterator(Vertex *vertex, - const RiseFall *rf, - const PathAnalysisPt *path_ap, - const StaState *sta); + const Scene *scene, + const MinMax *min_max, + const RiseFall *rf, + const StaState *sta); // Iterate over vertex paths with the same transition and // analysis pt min/max but different tags. - VertexPathIterator(Vertex *vertex, - const RiseFall *rf, - const MinMax *min_max, - const StaState *sta); VertexPathIterator(Vertex *vertex, const RiseFall *rf, - const PathAnalysisPt *path_ap, const MinMax *min_max, const StaState *sta); virtual ~VertexPathIterator(); @@ -216,10 +211,10 @@ private: void findNext(); const Search *search_; - bool filtered_; - const RiseFall *rf_; - const PathAnalysisPt *path_ap_; + const Scene *scene_; const MinMax *min_max_; + const RiseFall *rf_; + bool filtered_; Path *paths_; size_t path_count_; size_t path_index_; diff --git a/include/sta/PathAnalysisPt.hh b/include/sta/PathAnalysisPt.hh deleted file mode 100644 index 6d6a7e94..00000000 --- a/include/sta/PathAnalysisPt.hh +++ /dev/null @@ -1,69 +0,0 @@ -// OpenSTA, Static Timing Analyzer -// Copyright (c) 2025, Parallax Software, Inc. -// -// This program is free software: you can redistribute it and/or modify -// it under the terms of the GNU General Public License as published by -// the Free Software Foundation, either version 3 of the License, or -// (at your option) any later version. -// -// This program is distributed in the hope that it will be useful, -// but WITHOUT ANY WARRANTY; without even the implied warranty of -// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -// GNU General Public License for more details. -// -// You should have received a copy of the GNU General Public License -// along with this program. If not, see . -// -// The origin of this software must not be misrepresented; you must not -// claim that you wrote the original software. -// -// Altered source versions must be plainly marked as such, and must not be -// misrepresented as being the original software. -// -// This notice may not be removed or altered from any source distribution. - -#pragma once - -#include - -#include "Iterator.hh" -#include "MinMax.hh" -#include "SdcClass.hh" -#include "SearchClass.hh" - -namespace sta { - -class MinMax; -class DcalcAnalysisPt; -class Corner; - -class PathAnalysisPt -{ -public: - PathAnalysisPt(Corner *corner, - PathAPIndex index, - const MinMax *path_min_max, - DcalcAnalysisPt *dcalc_ap); - std::string to_string() const; - Corner *corner() const { return corner_; } - PathAPIndex index() const { return index_; } - const MinMax *pathMinMax() const { return path_min_max_; } - // Converging path arrival merging. - const MinMax *mergeMinMax() const { return path_min_max_; } - // Path analysis point for timing check target clock arrivals. - PathAnalysisPt *tgtClkAnalysisPt() const { return tgt_clk_ap_; } - void setTgtClkAnalysisPt(PathAnalysisPt *path_ap); - DcalcAnalysisPt *dcalcAnalysisPt() const { return dcalc_ap_; } - PathAnalysisPt *insertionAnalysisPt(const EarlyLate *early_late) const; - void setInsertionAnalysisPt(const EarlyLate *early_late, PathAnalysisPt *ap); - -private: - Corner *corner_; - PathAPIndex index_; - const MinMax *path_min_max_; - PathAnalysisPt *tgt_clk_ap_; - PathAnalysisPt *insertion_aps_[EarlyLate::index_count]; - DcalcAnalysisPt *dcalc_ap_; -}; - -} // namespace diff --git a/include/sta/PathEnd.hh b/include/sta/PathEnd.hh index c61eb16a..4f974f3f 100644 --- a/include/sta/PathEnd.hh +++ b/include/sta/PathEnd.hh @@ -59,13 +59,13 @@ class ReportPath; class PathEnd { public: - enum Type { unconstrained, - check, - data_check, - latch_check, - output_delay, - gated_clk, - path_delay + enum class Type { unconstrained, + check, + data_check, + latch_check, + output_delay, + gated_clk, + path_delay }; virtual PathEnd *copy() const = 0; @@ -80,8 +80,6 @@ public: const EarlyLate *pathEarlyLate(const StaState *sta) const; virtual const EarlyLate *clkEarlyLate(const StaState *sta) const; const RiseFall *transition(const StaState *sta) const; - PathAnalysisPt *pathAnalysisPt(const StaState *sta) const; - PathAPIndex pathIndex(const StaState *sta) const; virtual void reportShort(const ReportPath *report) const = 0; virtual void reportFull(const ReportPath *report) const = 0; PathGroup *pathGroup() const { return path_group_; } @@ -89,17 +87,17 @@ public: // Predicates for PathEnd type. // Default methods overridden by respective types. - virtual bool isUnconstrained() const { return false; } - virtual bool isCheck() const { return false; } - virtual bool isDataCheck() const { return false; } - virtual bool isLatchCheck() const { return false; } - virtual bool isOutputDelay() const { return false; } - virtual bool isGatedClock() const { return false; } - virtual bool isPathDelay() const { return false; } + [[nodiscard]] virtual bool isUnconstrained() const { return false; } + [[nodiscard]] virtual bool isCheck() const { return false; } + [[nodiscard]] virtual bool isDataCheck() const { return false; } + [[nodiscard]] virtual bool isLatchCheck() const { return false; } + [[nodiscard]] virtual bool isOutputDelay() const { return false; } + [[nodiscard]] virtual bool isGatedClock() const { return false; } + [[nodiscard]] virtual bool isPathDelay() const { return false; } virtual Type type() const = 0; virtual const char *typeName() const = 0; virtual int exceptPathCmp(const PathEnd *path_end, - const StaState *sta) const; + const StaState *sta) const; virtual Arrival dataArrivalTime(const StaState *sta) const; // Arrival time with source clock offset. Arrival dataArrivalTimeOffset(const StaState *sta) const; @@ -154,20 +152,20 @@ public: virtual bool ignoreClkLatency(const StaState * /* sta */) const { return false; } static bool less(const PathEnd *path_end1, - const PathEnd *path_end2, - const StaState *sta); + const PathEnd *path_end2, + const StaState *sta); static int cmp(const PathEnd *path_end1, - const PathEnd *path_end2, - const StaState *sta); + const PathEnd *path_end2, + const StaState *sta); static int cmpSlack(const PathEnd *path_end1, - const PathEnd *path_end2, - const StaState *sta); + const PathEnd *path_end2, + const StaState *sta); static int cmpArrival(const PathEnd *path_end1, - const PathEnd *path_end2, - const StaState *sta); + const PathEnd *path_end2, + const StaState *sta); static int cmpNoCrpr(const PathEnd *path_end1, - const PathEnd *path_end2, - const StaState *sta); + const PathEnd *path_end2, + const StaState *sta); // Helper common to multiple PathEnd classes and used // externally. @@ -177,43 +175,43 @@ public: const TimingRole *check_role, const StaState *sta); static void checkTgtClkDelay(const Path *tgt_clk_path, - const ClockEdge *tgt_clk_edge, - const TimingRole *check_role, - const StaState *sta, - // Return values. - Delay &insertion, - Delay &latency); + const ClockEdge *tgt_clk_edge, + const TimingRole *check_role, + const StaState *sta, + // Return values. + Delay &insertion, + Delay &latency); static float checkClkUncertainty(const ClockEdge *src_clk_edge, - const ClockEdge *tgt_clk_edge, - const Path *tgt_clk_path, - const TimingRole *check_role, - const StaState *sta); + const ClockEdge *tgt_clk_edge, + const Path *tgt_clk_path, + const TimingRole *check_role, + const Sdc *sdc); // Non inter-clock uncertainty. static float checkTgtClkUncertainty(const Path *tgt_clk_path, const ClockEdge *tgt_clk_edge, const TimingRole *check_role, const StaState *sta); static float checkSetupMcpAdjustment(const ClockEdge *src_clk_edge, - const ClockEdge *tgt_clk_edge, - const MultiCyclePath *mcp, - int default_cycles, - Sdc *sdc); + const ClockEdge *tgt_clk_edge, + const MultiCyclePath *mcp, + int default_cycles, + Sdc *sdc); protected: PathEnd(Path *path); static void checkInterClkUncertainty(const ClockEdge *src_clk_edge, - const ClockEdge *tgt_clk_edge, - const TimingRole *check_role, - const StaState *sta, - float &uncertainty, - bool &exists); + const ClockEdge *tgt_clk_edge, + const TimingRole *check_role, + const Sdc *sdc, + float &uncertainty, + bool &exists); static float outputDelayMargin(OutputDelay *output_delay, - const Path *path, - const StaState *sta); + const Path *path, + const StaState *sta); static float pathDelaySrcClkOffset(const Path *path, - PathDelay *path_delay, - Arrival src_clk_arrival, - const StaState *sta); + PathDelay *path_delay, + Arrival src_clk_arrival, + const StaState *sta); static bool ignoreClkLatency(const Path *path, PathDelay *path_delay, const StaState *sta); @@ -224,7 +222,7 @@ protected: class PathEndUnconstrained : public PathEnd { public: - explicit PathEndUnconstrained(Path *path); + PathEndUnconstrained(Path *path); virtual Type type() const; virtual const char *typeName() const; virtual PathEnd *copy() const; @@ -262,21 +260,21 @@ public: virtual Slack slack(const StaState *sta) const; virtual Slack slackNoCrpr(const StaState *sta) const; virtual int exceptPathCmp(const PathEnd *path_end, - const StaState *sta) const; + const StaState *sta) const; virtual void setPath(Path *path); protected: PathEndClkConstrained(Path *path, - Path *clk_path); + Path *clk_path); PathEndClkConstrained(Path *path, - Path *clk_path, - Crpr crpr, - bool crpr_valid); + Path *clk_path, + Crpr crpr, + bool crpr_valid); float sourceClkOffset(const ClockEdge *src_clk_edge, - const ClockEdge *tgt_clk_edge, - const TimingRole *check_role, - const StaState *sta) const; + const ClockEdge *tgt_clk_edge, + const TimingRole *check_role, + const StaState *sta) const; // Internal to slackNoCrpr. virtual Arrival targetClkArrivalNoCrpr(const StaState *sta) const; virtual Required requiredTimeNoCrpr(const StaState *sta) const; @@ -292,24 +290,24 @@ public: virtual MultiCyclePath *multiCyclePath() const { return mcp_; } virtual float targetClkMcpAdjustment(const StaState *sta) const; virtual int exceptPathCmp(const PathEnd *path_end, - const StaState *sta) const; + const StaState *sta) const; protected: PathEndClkConstrainedMcp(Path *path, - Path *clk_path, - MultiCyclePath *mcp); + Path *clk_path, + MultiCyclePath *mcp); PathEndClkConstrainedMcp(Path *path, - Path *clk_path, - MultiCyclePath *mcp, - Crpr crpr, - bool crpr_valid); + Path *clk_path, + MultiCyclePath *mcp, + Crpr crpr, + bool crpr_valid); float checkMcpAdjustment(const Path *path, - const ClockEdge *tgt_clk_edge, - const StaState *sta) const; + const ClockEdge *tgt_clk_edge, + const StaState *sta) const; void findHoldMcps(const ClockEdge *tgt_clk_edge, - const MultiCyclePath *&setup_mcp, - const MultiCyclePath *&hold_mcp, - const StaState *sta) const; + const MultiCyclePath *&setup_mcp, + const MultiCyclePath *&hold_mcp, + const StaState *sta) const; MultiCyclePath *mcp_; }; @@ -319,11 +317,11 @@ class PathEndCheck : public PathEndClkConstrainedMcp { public: PathEndCheck(Path *path, - TimingArc *check_arc, - Edge *check_edge, - Path *clk_path, - MultiCyclePath *mcp, - const StaState *sta); + TimingArc *check_arc, + Edge *check_edge, + Path *clk_path, + MultiCyclePath *mcp, + const StaState *sta); virtual PathEnd *copy() const; virtual Type type() const; virtual const char *typeName() const; @@ -335,17 +333,17 @@ public: virtual const TimingRole *checkRole(const StaState *sta) const; virtual TimingArc *checkArc() const { return check_arc_; } virtual int exceptPathCmp(const PathEnd *path_end, - const StaState *sta) const; + const StaState *sta) const; virtual Delay clkSkew(const StaState *sta); protected: PathEndCheck(Path *path, - TimingArc *check_arc, - Edge *check_edge, - Path *clk_path, - MultiCyclePath *mcp, - Crpr crpr, - bool crpr_valid); + TimingArc *check_arc, + Edge *check_edge, + Path *clk_path, + MultiCyclePath *mcp, + Crpr crpr, + bool crpr_valid); Delay sourceClkDelay(const StaState *sta) const; virtual Required requiredTimeNoCrpr(const StaState *sta) const; @@ -358,12 +356,12 @@ class PathEndLatchCheck : public PathEndCheck { public: PathEndLatchCheck(Path *path, - TimingArc *check_arc, - Edge *check_edge, - Path *disable_path, - MultiCyclePath *mcp, - PathDelay *path_delay, - const StaState *sta); + TimingArc *check_arc, + Edge *check_edge, + Path *disable_path, + MultiCyclePath *mcp, + PathDelay *path_delay, + const StaState *sta); virtual Type type() const; virtual const char *typeName() const; virtual float sourceClkOffset(const StaState *sta) const; @@ -382,36 +380,36 @@ public: virtual float targetClkOffset(const StaState *sta) const; Arrival targetClkWidth(const StaState *sta) const; virtual int exceptPathCmp(const PathEnd *path_end, - const StaState *sta) const; + const StaState *sta) const; void latchRequired(const StaState *sta, - // Return values. - Required &required, - Delay &borrow, - Arrival &adjusted_data_arrival, - Delay &time_given_to_startpoint) const; + // Return values. + Required &required, + Delay &borrow, + Arrival &adjusted_data_arrival, + Delay &time_given_to_startpoint) const; void latchBorrowInfo(const StaState *sta, - // Return values. - float &nom_pulse_width, - Delay &open_latency, - Delay &latency_diff, - float &open_uncertainty, - Crpr &open_crpr, - Crpr &crpr_diff, - Delay &max_borrow, - bool &borrow_limit_exists) const; + // Return values. + float &nom_pulse_width, + Delay &open_latency, + Delay &latency_diff, + float &open_uncertainty, + Crpr &open_crpr, + Crpr &crpr_diff, + Delay &max_borrow, + bool &borrow_limit_exists) const; virtual bool ignoreClkLatency(const StaState *sta) const; protected: PathEndLatchCheck(Path *path, - TimingArc *check_arc, - Edge *check_edge, - Path *clk_path, - Path *disable, - MultiCyclePath *mcp, - PathDelay *path_delay, - Delay src_clk_arrival, - Crpr crpr, - bool crpr_valid); + TimingArc *check_arc, + Edge *check_edge, + Path *clk_path, + Path *disable, + MultiCyclePath *mcp, + PathDelay *path_delay, + Delay src_clk_arrival, + Crpr crpr, + bool crpr_valid); private: Path *disable_path_; @@ -427,10 +425,10 @@ class PathEndOutputDelay : public PathEndClkConstrainedMcp { public: PathEndOutputDelay(OutputDelay *output_delay, - Path *path, - Path *clk_path, - MultiCyclePath *mcp, - const StaState *sta); + Path *path, + Path *clk_path, + MultiCyclePath *mcp, + const StaState *sta); virtual PathEnd *copy() const; virtual Type type() const; virtual const char *typeName() const; @@ -445,24 +443,24 @@ public: virtual Delay targetClkInsertionDelay(const StaState *sta) const; virtual Crpr crpr(const StaState *sta) const; virtual int exceptPathCmp(const PathEnd *path_end, - const StaState *sta) const; + const StaState *sta) const; protected: PathEndOutputDelay(OutputDelay *output_delay, - Path *path, - Path *clk_path, - MultiCyclePath *mcp, - Crpr crpr, - bool crpr_valid); + Path *path, + Path *clk_path, + MultiCyclePath *mcp, + Crpr crpr, + bool crpr_valid); Arrival tgtClkDelay(const ClockEdge *tgt_clk_edge, - const TimingRole *check_role, - const StaState *sta) const; + const TimingRole *check_role, + const StaState *sta) const; void tgtClkDelay(const ClockEdge *tgt_clk_edge, - const TimingRole *check_role, - const StaState *sta, - // Return values. - Arrival &insertion, - Arrival &latency) const; + const TimingRole *check_role, + const StaState *sta, + // Return values. + Arrival &insertion, + Arrival &latency) const; OutputDelay *output_delay_; }; @@ -472,11 +470,11 @@ class PathEndGatedClock : public PathEndClkConstrainedMcp { public: PathEndGatedClock(Path *gating_ref, - Path *clk_path, - const TimingRole *check_role, - MultiCyclePath *mcp, - ArcDelay margin, - const StaState *sta); + Path *clk_path, + const TimingRole *check_role, + MultiCyclePath *mcp, + ArcDelay margin, + const StaState *sta); virtual PathEnd *copy() const; virtual Type type() const; virtual const char *typeName() const; @@ -486,16 +484,16 @@ public: virtual ArcDelay margin(const StaState *) const { return margin_; } virtual const TimingRole *checkRole(const StaState *sta) const; virtual int exceptPathCmp(const PathEnd *path_end, - const StaState *sta) const; + const StaState *sta) const; protected: PathEndGatedClock(Path *gating_ref, - Path *clk_path, - const TimingRole *check_role, - MultiCyclePath *mcp, - ArcDelay margin, - Crpr crpr, - bool crpr_valid); + Path *clk_path, + const TimingRole *check_role, + MultiCyclePath *mcp, + ArcDelay margin, + Crpr crpr, + bool crpr_valid); const TimingRole *check_role_; ArcDelay margin_; @@ -505,10 +503,10 @@ class PathEndDataCheck : public PathEndClkConstrainedMcp { public: PathEndDataCheck(DataCheck *check, - Path *data_path, - Path *data_clk_path, - MultiCyclePath *mcp, - const StaState *sta); + Path *data_path, + Path *data_clk_path, + MultiCyclePath *mcp, + const StaState *sta); virtual PathEnd *copy() const; virtual Type type() const; virtual const char *typeName() const; @@ -519,17 +517,17 @@ public: virtual const TimingRole *checkRole(const StaState *sta) const; virtual ArcDelay margin(const StaState *sta) const; virtual int exceptPathCmp(const PathEnd *path_end, - const StaState *sta) const; + const StaState *sta) const; virtual const Path *dataClkPath() const { return data_clk_path_; } protected: PathEndDataCheck(DataCheck *check, - Path *data_path, - Path *data_clk_path, - Path *clk_path, - MultiCyclePath *mcp, - Crpr crpr, - bool crpr_valid); + Path *data_path, + Path *data_clk_path, + Path *clk_path, + MultiCyclePath *mcp, + Crpr crpr, + bool crpr_valid); Path *clkPath(Path *path, const StaState *sta); Arrival requiredTimeNoCrpr(const StaState *sta) const; @@ -549,20 +547,20 @@ class PathEndPathDelay : public PathEndClkConstrained public: // Vanilla path delay. PathEndPathDelay(PathDelay *path_delay, - Path *path, - const StaState *sta); + Path *path, + const StaState *sta); // Path delay to timing check. PathEndPathDelay(PathDelay *path_delay, - Path *path, - Path *clk_path, - TimingArc *check_arc, - Edge *check_edge, - const StaState *sta); + Path *path, + Path *clk_path, + TimingArc *check_arc, + Edge *check_edge, + const StaState *sta); // Path delay to output with set_output_delay. PathEndPathDelay(PathDelay *path_delay, - Path *path, - OutputDelay *output_delay, - const StaState *sta); + Path *path, + OutputDelay *output_delay, + const StaState *sta); virtual PathEnd *copy() const; virtual Type type() const; virtual const char *typeName() const; @@ -581,20 +579,20 @@ public: virtual TimingArc *checkArc() const { return check_arc_; } virtual Required requiredTime(const StaState *sta) const; virtual int exceptPathCmp(const PathEnd *path_end, - const StaState *sta) const; - bool hasOutputDelay() const { return output_delay_ != nullptr; } + const StaState *sta) const; + [[nodiscard]] bool hasOutputDelay() const { return output_delay_ != nullptr; } virtual bool ignoreClkLatency(const StaState *sta) const; protected: PathEndPathDelay(PathDelay *path_delay, - Path *path, - Path *clk_path, - TimingArc *check_arc, - Edge *check_edge, - OutputDelay *output_delay, - Arrival src_clk_arrival, - Crpr crpr, - bool crpr_valid); + Path *path, + Path *clk_path, + TimingArc *check_arc, + Edge *check_edge, + OutputDelay *output_delay, + Arrival src_clk_arrival, + Crpr crpr, + bool crpr_valid); void findSrcClkArrival(const StaState *sta); PathDelay *path_delay_; @@ -613,9 +611,9 @@ protected: class PathEndLess { public: - explicit PathEndLess(const StaState *sta); + PathEndLess(const StaState *sta); bool operator()(const PathEnd *path_end1, - const PathEnd *path_end2) const; + const PathEnd *path_end2) const; protected: const StaState *sta_; @@ -625,9 +623,9 @@ protected: class PathEndSlackLess { public: - explicit PathEndSlackLess(const StaState *sta); + PathEndSlackLess(const StaState *sta); bool operator()(const PathEnd *path_end1, - const PathEnd *path_end2) const; + const PathEnd *path_end2) const; protected: const StaState *sta_; @@ -636,9 +634,9 @@ protected: class PathEndNoCrprLess { public: - explicit PathEndNoCrprLess(const StaState *sta); + PathEndNoCrprLess(const StaState *sta); bool operator()(const PathEnd *path_end1, - const PathEnd *path_end2) const; + const PathEnd *path_end2) const; protected: const StaState *sta_; diff --git a/include/sta/PathExpanded.hh b/include/sta/PathExpanded.hh index 784409bf..0269f685 100644 --- a/include/sta/PathExpanded.hh +++ b/include/sta/PathExpanded.hh @@ -38,13 +38,13 @@ public: PathExpanded(const StaState *sta); // Expand path for lookup by index. PathExpanded(const Path *path, - const StaState *sta); + const StaState *sta); PathExpanded(const Path *path, - // Expand generated clk source paths. - bool expand_genclks, - const StaState *sta); + // Expand generated clk source paths. + bool expand_genclks, + const StaState *sta); void expand(const Path *path, - bool expand_genclks); + bool expand_genclks); size_t size() const { return paths_.size(); } // path(0) is the startpoint. // path(size()-1) is the endpoint. @@ -59,9 +59,9 @@ public: size_t startIndex() const; const Path *clkPath() const; void latchPaths(// Return values. - const Path *&d_path, - const Path *&q_path, - Edge *&d_q_edge) const; + const Path *&d_path, + const Path *&q_path, + Edge *&d_q_edge) const; protected: void expandGenclk(const Path *clk_path); diff --git a/include/sta/PathGroup.hh b/include/sta/PathGroup.hh index cc84f9ea..a3bd6ee3 100644 --- a/include/sta/PathGroup.hh +++ b/include/sta/PathGroup.hh @@ -24,10 +24,11 @@ #pragma once +#include +#include +#include #include -#include "Map.hh" -#include "Vector.hh" #include "SdcClass.hh" #include "StaState.hh" #include "SearchClass.hh" @@ -37,11 +38,11 @@ namespace sta { class MinMax; class PathEndVisitor; -typedef PathEndSeq::Iterator PathGroupIterator; -typedef Map PathGroupClkMap; -typedef Map PathGroupNamedMap; -typedef std::vector PathGroupSeq; -typedef std::vector StdStringSeq; +using PathGroupIterator = PathEndSeq::iterator; +using PathGroupClkMap = std::map; +using PathGroupNamedMap = std::map; +using PathGroupSeq = std::vector; +using StdStringSeq = std::vector; // A collection of PathEnds grouped and sorted for reporting. class PathGroup @@ -50,22 +51,22 @@ public: ~PathGroup(); // Path group that compares compare slacks. static PathGroup *makePathGroupArrival(const char *name, - int group_path_count, - int endpoint_path_count, - bool unique_pins, - bool unique_edges, - const MinMax *min_max, - const StaState *sta); + int group_path_count, + int endpoint_path_count, + bool unique_pins, + bool unique_edges, + const MinMax *min_max, + const StaState *sta); // Path group that compares arrival time, sorted by min_max. static PathGroup *makePathGroupSlack(const char *name, - int group_path_count, - int endpoint_path_count, - bool unique_pins, - bool unique_edges, - float min_slack, - float max_slack, - const StaState *sta); - const char *name() const { return name_; } + int group_path_count, + int endpoint_path_count, + bool unique_pins, + bool unique_edges, + float min_slack, + float max_slack, + const StaState *sta); + const char *name() const { return name_.c_str(); } const MinMax *minMax() const { return min_max_;} const PathEndSeq &pathEnds() const { return path_ends_; } void insert(PathEnd *path_end); @@ -75,27 +76,27 @@ public: bool saveable(PathEnd *path_end); bool enumMinSlackUnderMin(PathEnd *path_end); int maxPaths() const { return group_path_count_; } - PathGroupIterator *iterator(); + PathEndSeq &pathEnds() { return path_ends_; } // This does NOT delete the path ends. void clear(); static size_t group_path_count_max; protected: PathGroup(const char *name, - size_t group_path_count, - size_t endpoint_path_count, - bool unique_pins, - bool unique_edges, - float min_slack, - float max_slack, - bool cmp_slack, - const MinMax *min_max, - const StaState *sta); + size_t group_path_count, + size_t endpoint_path_count, + bool unique_pins, + bool unique_edges, + float min_slack, + float max_slack, + bool cmp_slack, + const MinMax *min_max, + const StaState *sta); void ensureSortedMaxPaths(); void prune(); void sort(); - const char *name_; + std::string name_; size_t group_path_count_; size_t endpoint_path_count_; bool unique_pins_; @@ -114,35 +115,37 @@ class PathGroups : public StaState { public: PathGroups(int group_path_count, - int endpoint_path_count, - bool unique_pins, - bool unique_edges, - float slack_min, - float slack_max, - PathGroupNameSet *group_names, - bool setup, - bool hold, - bool recovery, - bool removal, - bool clk_gating_setup, - bool clk_gating_hold, - bool unconstrained, - const StaState *sta); + int endpoint_path_count, + bool unique_pins, + bool unique_edges, + float slack_min, + float slack_max, + StdStringSeq &group_names, + bool setup, + bool hold, + bool recovery, + bool removal, + bool clk_gating_setup, + bool clk_gating_hold, + bool unconstrained, + const Mode *mode); ~PathGroups(); - // Use corner nullptr to make PathEnds for all corners. + // Use scene nullptr to make PathEnds for all scenes. // The PathEnds in the vector are owned by the PathGroups. - PathEndSeq makePathEnds(ExceptionTo *to, - bool unconstrained_paths, - const Corner *corner, - const MinMaxAll *min_max, - bool sort_by_slack); + void makePathEnds(ExceptionTo *to, + const SceneSeq &scenes, + const MinMaxAll *min_max, + bool sort_by_slack, + bool unconstrained_paths, + // Return value. + PathEndSeq &path_ends); PathGroup *findPathGroup(const char *name, - const MinMax *min_max) const; + const MinMax *min_max) const; PathGroup *findPathGroup(const Clock *clock, - const MinMax *min_max) const; + const MinMax *min_max) const; PathGroupSeq pathGroups(const PathEnd *path_end) const; static StdStringSeq pathGroupNames(const PathEnd *path_end, - const StaState *sta); + const StaState *sta); static const char *asyncPathGroupName() { return async_group_name_; } static const char *pathDelayGroupName() { return path_delay_group_name_; } static const char *gatedClkGroupName() { return gated_clk_group_name_; } @@ -150,46 +153,50 @@ public: protected: void makeGroupPathEnds(ExceptionTo *to, - int group_path_count, - int endpoint_path_count, - bool unique_pins, - bool unique_edges, - const Corner *corner, - const MinMaxAll *min_max); + int group_path_count, + int endpoint_path_count, + bool unique_pins, + bool unique_edges, + const SceneSeq &scenes, + const MinMaxAll *min_max); void makeGroupPathEnds(ExceptionTo *to, - const Corner *corner, - const MinMaxAll *min_max, - PathEndVisitor *visitor); - void makeGroupPathEnds(VertexSet *endpoints, - const Corner *corner, - const MinMaxAll *min_max, - PathEndVisitor *visitor); + const SceneSeq &scenes, + const MinMaxAll *min_max, + PathEndVisitor *visitor); + void makeGroupPathEnds(VertexSet &endpoints, + const SceneSeq &scenes, + const MinMaxAll *min_max, + PathEndVisitor *visitor); void enumPathEnds(PathGroup *group, - int group_path_count, - int endpoint_path_count, - bool unique_pins, - bool unique_edges, - bool cmp_slack); + int group_path_count, + int endpoint_path_count, + bool unique_pins, + bool unique_edges, + bool cmp_slack); - void pushGroupPathEnds(PathEndSeq &path_ends); + void pushEnds(PathEndSeq &path_ends); void pushUnconstrainedPathEnds(PathEndSeq &path_ends, - const MinMaxAll *min_max); + const MinMaxAll *min_max); void makeGroups(int group_path_count, - int endpoint_path_count, - bool unique_pins, - bool unique_edges, - float slack_min, - float slack_max, - PathGroupNameSet *group_names, - bool setup_hold, - bool async, - bool gated_clk, - bool unconstrained, - const MinMax *min_max); + int endpoint_path_count, + bool unique_pins, + bool unique_edges, + float slack_min, + float slack_max, + StdStringSet &group_names, + bool setup_hold, + bool async, + bool gated_clk, + bool unconstrained, + const MinMax *min_max); bool reportGroup(const char *group_name, - PathGroupNameSet *group_names) const; + StdStringSet &group_names) const; + static GroupPath *groupPathTo(const PathEnd *path_end, + const StaState *sta); + StdStringSeq pathGroupNames(); + const Mode *mode_; int group_path_count_; int endpoint_path_count_; bool unique_pins_; diff --git a/include/sta/PatternMatch.hh b/include/sta/PatternMatch.hh index 3531b8a4..03c308aa 100644 --- a/include/sta/PatternMatch.hh +++ b/include/sta/PatternMatch.hh @@ -29,8 +29,8 @@ #include "Error.hh" // Don't require all of tcl.h. -typedef struct Tcl_RegExp_ *Tcl_RegExp; -typedef struct Tcl_Interp Tcl_Interp; +using Tcl_RegExp = struct Tcl_RegExp_ *; +using Tcl_Interp = struct Tcl_Interp; namespace sta { @@ -46,15 +46,15 @@ public: // If nocase is true, ignore case in the pattern. // Tcl_Interp is optional for reporting regexp compile errors. PatternMatch(const char *pattern, - bool is_regexp, - bool nocase, - Tcl_Interp *interp); + bool is_regexp, + bool nocase, + Tcl_Interp *interp); // Use unix glob style matching. PatternMatch(const char *pattern); PatternMatch(const char *pattern, - const PatternMatch *inherit_from); + const PatternMatch *inherit_from); PatternMatch(const std::string &pattern, - const PatternMatch *inherit_from); + const PatternMatch *inherit_from); bool match(const char *str) const; bool match(const std::string &str) const; bool matchNoCase(const char *str) const; @@ -78,7 +78,7 @@ private: class RegexpCompileError : public Exception { public: - explicit RegexpCompileError(const char *pattern); + RegexpCompileError(const char *pattern); virtual ~RegexpCompileError() noexcept {} virtual const char *what() const noexcept; @@ -91,11 +91,11 @@ private: // '?' matches any character bool patternMatch(const char *pattern, - const char *str); + const char *str); bool patternMatchNoCase(const char *pattern, - const char *str, - bool nocase); + const char *str, + bool nocase); // Predicate to find out if there are wildcard characters in the pattern. bool patternWildcards(const char *pattern); diff --git a/include/sta/PinPair.hh b/include/sta/PinPair.hh index 7d3f2711..bdc51135 100644 --- a/include/sta/PinPair.hh +++ b/include/sta/PinPair.hh @@ -24,27 +24,28 @@ #pragma once +#include + #include "Hash.hh" -#include "Set.hh" #include "NetworkClass.hh" namespace sta { -typedef std::pair PinPair; +using PinPair = std::pair; class PinPairLess { public: PinPairLess(const Network *network); bool operator()(const PinPair &pair1, - const PinPair &pair2) const; + const PinPair &pair2) const; private: const Network *network_; }; -class PinPairSet : public Set +class PinPairSet : public std::set { public: PinPairSet(const Network *network); @@ -64,7 +65,7 @@ class PinPairEqual { public: bool operator()(const PinPair &pair1, - const PinPair &pair2) const; + const PinPair &pair2) const; }; } // namespace diff --git a/include/sta/PortDelay.hh b/include/sta/PortDelay.hh index 4220bf7c..9f36e396 100644 --- a/include/sta/PortDelay.hh +++ b/include/sta/PortDelay.hh @@ -24,6 +24,8 @@ #pragma once +#include + #include "RiseFallMinMax.hh" #include "SdcClass.hh" @@ -31,7 +33,7 @@ namespace sta { class PortDelay; -typedef Vector PortDelaySeq; +using PortDelaySeq = std::vector; // set_input_delay arrival, set_output_delay departure class PortDelay @@ -52,7 +54,7 @@ public: protected: PortDelay(const Pin *pin, - const ClockEdge *clk_edge, + const ClockEdge *clk_edge, const Network *network); const Pin *pin_; @@ -71,9 +73,9 @@ public: protected: InputDelay(const Pin *pin, - const ClockEdge *clk_edge, - int index, - const Network *network); + const ClockEdge *clk_edge, + int index, + const Network *network); private: int index_; @@ -87,8 +89,8 @@ public: protected: OutputDelay(const Pin *pin, - const ClockEdge *clk_edge, - const Network *network); + const ClockEdge *clk_edge, + const Network *network); private: friend class Sdc; @@ -98,9 +100,9 @@ private: class PortDelayLess { public: - explicit PortDelayLess(const Network *network); + PortDelayLess(const Network *network); bool operator()(const PortDelay *delay1, - const PortDelay *delay2) const; + const PortDelay *delay2) const; private: const Network *network_; diff --git a/include/sta/PortDirection.hh b/include/sta/PortDirection.hh index 186914a9..b61f48f6 100644 --- a/include/sta/PortDirection.hh +++ b/include/sta/PortDirection.hh @@ -64,7 +64,7 @@ public: private: PortDirection(const char *name, - int index); + int index); const char *name_; int index_; diff --git a/include/sta/PortExtCap.hh b/include/sta/PortExtCap.hh index 2bad21c9..716dcbb9 100644 --- a/include/sta/PortExtCap.hh +++ b/include/sta/PortExtCap.hh @@ -32,39 +32,42 @@ namespace sta { -typedef MinMaxIntValues FanoutValues; +using FanoutValues = MinMaxIntValues; // Port external pin and wire capacitance (set_load -pin_load -wire_load). class PortExtCap { public: - PortExtCap(const Port *port); + PortExtCap(); const Port *port() { return port_; } void pinCap(const RiseFall *rf, - const MinMax *min_max, - // Return values. - float &cap, - bool &exists); - RiseFallMinMax *pinCap() { return &pin_cap_; } - void setPinCap(float cap, - const RiseFall *rf, - const MinMax *min_max); + const MinMax *min_max, + // Return values. + float &cap, + bool &exists) const; + const RiseFallMinMax *pinCap() const { return &pin_cap_; } + void setPinCap(const Port *port, + float cap, + const RiseFall *rf, + const MinMax *min_max); void wireCap(const RiseFall *rf, - const MinMax *min_max, - // Return values. - float &cap, - bool &exists); - RiseFallMinMax *wireCap() { return &wire_cap_; } - void setWireCap(float cap, - const RiseFall *rf, - const MinMax *min_max); - void setFanout(int fanout, - const MinMax *min_max); + const MinMax *min_max, + // Return values. + float &cap, + bool &exists) const; + const RiseFallMinMax *wireCap() const { return &wire_cap_; } + void setWireCap(const Port *port, + float cap, + const RiseFall *rf, + const MinMax *min_max); + void setFanout(const Port *port, + int fanout, + const MinMax *min_max); void fanout(const MinMax *min_max, - // Return values. - int &fanout, - bool &exists); - FanoutValues *fanout() { return &fanout_; } + // Return values. + int &fanout, + bool &exists) const; + const FanoutValues *fanout() const { return &fanout_; } private: const Port *port_; diff --git a/include/sta/PowerClass.hh b/include/sta/PowerClass.hh index ed4a4860..5b1d36be 100644 --- a/include/sta/PowerClass.hh +++ b/include/sta/PowerClass.hh @@ -24,6 +24,9 @@ #pragma once +#include +#include + namespace sta { class Power; @@ -47,8 +50,8 @@ class PwrActivity public: PwrActivity(); PwrActivity(float density, - float duty, - PwrActivityOrigin origin); + float duty, + PwrActivityOrigin origin); void init(); float density() const { return density_; } void setDensity(float density); @@ -58,8 +61,8 @@ public: void setOrigin(PwrActivityOrigin origin); const char *originName() const; void set(float density, - float duty, - PwrActivityOrigin origin); + float duty, + PwrActivityOrigin origin); bool isSet() const; private: @@ -92,4 +95,7 @@ private: float leakage_; }; +using InstPower = std::pair; +using InstPowers = std::vector; + } // namespace diff --git a/include/sta/Property.hh b/include/sta/Property.hh index 9ddafeac..4bfa86ca 100644 --- a/include/sta/Property.hh +++ b/include/sta/Property.hh @@ -26,6 +26,7 @@ #include #include +#include #include #include "LibertyClass.hh" @@ -47,7 +48,7 @@ class PropertyRegistry { public: typedef std::function PropertyHandler; - void defineProperty(const std::string &property, + void defineProperty(std::string_view property, PropertyHandler handler); PropertyValue getProperty(TYPE object, const std::string &property, @@ -65,84 +66,76 @@ public: virtual ~Properties() {} PropertyValue getProperty(const Library *lib, - const std::string property); + const std::string &property); PropertyValue getProperty(const LibertyLibrary *lib, - const std::string property); + const std::string &property); PropertyValue getProperty(const Cell *cell, - const std::string property); + const std::string &property); PropertyValue getProperty(const LibertyCell *cell, - const std::string property); + const std::string &property); PropertyValue getProperty(const Port *port, - const std::string property); + const std::string &property); PropertyValue getProperty(const LibertyPort *port, - const std::string property); + const std::string &property); PropertyValue getProperty(const Instance *inst, - const std::string property); + const std::string &property); PropertyValue getProperty(const Pin *pin, - const std::string property); + const std::string &property); PropertyValue getProperty(const Net *net, - const std::string property); + const std::string &property); PropertyValue getProperty(Edge *edge, - const std::string property); + const std::string &property); PropertyValue getProperty(const Clock *clk, - const std::string property); + const std::string &property); PropertyValue getProperty(PathEnd *end, - const std::string property); + const std::string &property); PropertyValue getProperty(Path *path, - const std::string property); + const std::string &property); PropertyValue getProperty(TimingArcSet *arc_set, - const std::string property); + const std::string &property); // Define handler for external property. // properties->defineProperty("foo", // [] (const Instance *, Sta *) -> PropertyValue { // return PropertyValue("bar"); // }); - void defineProperty(std::string &property, + void defineProperty(std::string_view property, PropertyRegistry::PropertyHandler handler); - void defineProperty(std::string &property, + void defineProperty(std::string_view property, PropertyRegistry::PropertyHandler handler); - void defineProperty(std::string &property, + void defineProperty(std::string_view property, PropertyRegistry::PropertyHandler handler); - void defineProperty(std::string &property, + void defineProperty(std::string_view property, PropertyRegistry::PropertyHandler handler); - void defineProperty(std::string &property, + void defineProperty(std::string_view property, PropertyRegistry::PropertyHandler handler); - void defineProperty(std::string &property, + void defineProperty(std::string_view property, PropertyRegistry::PropertyHandler handler); - void defineProperty(std::string &property, + void defineProperty(std::string_view property, PropertyRegistry::PropertyHandler handler); - void defineProperty(std::string &property, + void defineProperty(std::string_view property, PropertyRegistry::PropertyHandler handler); - void defineProperty(std::string &property, + void defineProperty(std::string_view property, PropertyRegistry::PropertyHandler handler); - void defineProperty(std::string &property, + void defineProperty(std::string_view property, PropertyRegistry::PropertyHandler handler); protected: PropertyValue portSlew(const Port *port, - const MinMax *min_max); - PropertyValue portSlew(const Port *port, - const RiseFall *rf, + const RiseFallBoth *rf, const MinMax *min_max); PropertyValue portSlack(const Port *port, - const MinMax *min_max); - PropertyValue portSlack(const Port *port, - const RiseFall *rf, + const RiseFallBoth *rf, const MinMax *min_max); PropertyValue pinArrival(const Pin *pin, - const RiseFall *rf, + const RiseFallBoth *rf, const MinMax *min_max); PropertyValue pinSlack(const Pin *pin, - const MinMax *min_max); - PropertyValue pinSlack(const Pin *pin, - const RiseFall *rf, + const RiseFallBoth *rf, const MinMax *min_max); PropertyValue pinSlew(const Pin *pin, - const MinMax *min_max); - PropertyValue pinSlew(const Pin *pin, - const RiseFall *rf, + const RiseFallBoth *rf, const MinMax *min_max); PropertyValue delayPropertyValue(Delay delay); @@ -179,11 +172,11 @@ protected: class PropertyValue { public: - enum Type { type_none, type_string, type_float, type_bool, - type_library, type_cell, type_port, - type_liberty_library, type_liberty_cell, type_liberty_port, - type_instance, type_pin, type_pins, type_net, - type_clk, type_clks, type_paths, type_pwr_activity }; + enum class Type { none, string, float_, bool_, + library, cell, port, + liberty_library, liberty_cell, liberty_port, + instance, pin, pins, net, + clk, clks, paths, pwr_activity }; PropertyValue(); PropertyValue(const char *value); PropertyValue(std::string &value); @@ -210,7 +203,7 @@ public: // Copy constructor. PropertyValue(const PropertyValue &props); // Move constructor. - PropertyValue(PropertyValue &&props); + PropertyValue(PropertyValue &&props) noexcept; ~PropertyValue(); Type type() const { return type_; } const Unit *unit() const { return unit_; } @@ -237,7 +230,7 @@ public: // Copy assignment. PropertyValue &operator=(const PropertyValue &); // Move assignment. - PropertyValue &operator=(PropertyValue &&); + PropertyValue &operator=(PropertyValue &&) noexcept; private: Type type_; diff --git a/include/sta/Report.hh b/include/sta/Report.hh index 7d2aebe9..9e8aed56 100644 --- a/include/sta/Report.hh +++ b/include/sta/Report.hh @@ -129,7 +129,7 @@ public: // Suppress message by id. void suppressMsgId(int id); void unsuppressMsgId(int id); - bool isSuppressed(int id); + [[nodiscard]] bool isSuppressed(int id); protected: // All sta print functions have an implicit return printed by this function. diff --git a/include/sta/ReportTcl.hh b/include/sta/ReportTcl.hh index 37ba416d..fe3391fc 100644 --- a/include/sta/ReportTcl.hh +++ b/include/sta/ReportTcl.hh @@ -62,8 +62,8 @@ protected: private: Tcl_ChannelType *makeEncapChannelType(Tcl_Channel channel, - char *channel_name, - Tcl_DriverOutputProc output_proc); + char *channel_name, + Tcl_DriverOutputProc output_proc); size_t printTcl(Tcl_Channel channel, const char *buffer, size_t length); diff --git a/include/sta/RiseFallMinMax.hh b/include/sta/RiseFallMinMax.hh index 1aacbdd4..81511ec5 100644 --- a/include/sta/RiseFallMinMax.hh +++ b/include/sta/RiseFallMinMax.hh @@ -35,41 +35,41 @@ class RiseFallMinMax public: RiseFallMinMax(); RiseFallMinMax(const RiseFallMinMax *rfmm); - explicit RiseFallMinMax(float init_value); + RiseFallMinMax(float init_value); float value(const RiseFall *rf, - const MinMax *min_max) const; + const MinMax *min_max) const; float value(const MinMax *min_max) const; void value(const RiseFall *rf, - const MinMax *min_max, - float &value, - bool &exists) const; + const MinMax *min_max, + float &value, + bool &exists) const; bool hasValue() const; void maxValue(// Return values - float &max_value, - bool &exists) const; - bool empty() const; + float &max_value, + bool &exists) const; + [[nodiscard]] bool empty() const; bool hasValue(const RiseFall *rf, - const MinMax *min_max) const; + const MinMax *min_max) const; void setValue(const RiseFallBoth *rf, - const MinMaxAll *min_max, - float value); + const MinMaxAll *min_max, + float value); void setValue(const RiseFallBoth *rf, - const MinMax *min_max, - float value); + const MinMax *min_max, + float value); void setValue(const RiseFall *rf, - const MinMax *min_max, float value); + const MinMax *min_max, float value); void setValue(float value); void mergeValue(const RiseFallBoth *rf, - const MinMaxAll *min_max, - float value); + const MinMaxAll *min_max, + float value); void mergeValue(const RiseFall *rf, - const MinMax *min_max, - float value); + const MinMax *min_max, + float value); void setValues(RiseFallMinMax *values); void removeValue(const RiseFallBoth *rf, - const MinMax *min_max); + const MinMax *min_max); void removeValue(const RiseFallBoth *rf, - const MinMaxAll *min_max); + const MinMaxAll *min_max); // Merge all values of rfmm. void mergeWith(RiseFallMinMax *rfmm); void clear(); @@ -77,8 +77,8 @@ public: bool isOneValue() const; bool isOneValue(float &value) const; bool isOneValue(const MinMax *min_max, - // Return values. - float &value) const; + // Return values. + float &value) const; private: float values_[RiseFall::index_count][MinMax::index_count]; diff --git a/include/sta/MakeConcreteParasitics.hh b/include/sta/RiseFallMinMaxDelay.hh similarity index 65% rename from include/sta/MakeConcreteParasitics.hh rename to include/sta/RiseFallMinMaxDelay.hh index 9bba835f..5d102fdb 100644 --- a/include/sta/MakeConcreteParasitics.hh +++ b/include/sta/RiseFallMinMaxDelay.hh @@ -24,9 +24,29 @@ #pragma once +#include "MinMax.hh" +#include "Transition.hh" +#include "Delay.hh" + namespace sta { -Parasitics * -makeConcreteParasitics(StaState *sta); +class RiseFallMinMaxDelay +{ +public: + RiseFallMinMaxDelay(); + [[nodiscard]] bool empty() const; + void value(const RiseFall *rf, + const MinMax *min_max, + Delay &value, + bool &exists) const; + void mergeValue(const RiseFall *rf, + const MinMax *min_max, + Delay &value, + const StaState *sta); + +private: + Delay values_[RiseFall::index_count][MinMax::index_count]; + bool exists_[RiseFall::index_count][MinMax::index_count]; +}; } // namespace diff --git a/include/sta/RiseFallValues.hh b/include/sta/RiseFallValues.hh index e3ba0ca7..a02c979e 100644 --- a/include/sta/RiseFallValues.hh +++ b/include/sta/RiseFallValues.hh @@ -33,10 +33,10 @@ class RiseFallValues { public: RiseFallValues(); - explicit RiseFallValues(float init_value); + RiseFallValues(float init_value); float value(const RiseFall *rf) const; void value(const RiseFall *rf, - float &value, bool &exists) const; + float &value, bool &exists) const; bool hasValue(const RiseFall *rf) const; void setValue(const RiseFallBoth *rf, float value); void setValue(const RiseFall *rf, float value); diff --git a/include/sta/Scene.hh b/include/sta/Scene.hh new file mode 100644 index 00000000..9b2e61a0 --- /dev/null +++ b/include/sta/Scene.hh @@ -0,0 +1,99 @@ +// OpenSTA, Static Timing Analyzer +// Copyright (c) 2025, Parallax Software, Inc. +// +// This program is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see . +// +// The origin of this software must not be misrepresented; you must not +// claim that you wrote the original software. +// +// Altered source versions must be plainly marked as such, and must not be +// misrepresented as being the original software. +// +// This notice may not be removed or altered from any source distribution. + +#pragma once + +#include +#include +#include + +#include "StringSeq.hh" +#include "GraphClass.hh" +#include "SearchClass.hh" + +namespace sta { + +class Mode; +class Sdc; +class MinMax; +class Scene; +class LibertyLibrary; +class Parasitics; + +using SceneSet = std::set; +using SceneSeq = std::vector; +using LibertySeq = std::vector; +using ModeSeq = std::vector; +using ModeSet = std::set; + +class Scene +{ +public: + Scene(const std::string &name, + size_t index, + Mode *mode, + Parasitics *parasitics); + Scene(const std::string &name, + size_t index, + Mode *mode, + Parasitics *parasitics_min, + Parasitics *parasitics_max); + const std::string &name() const { return name_; } + size_t index() const { return index_; } + Mode *mode() { return mode_; } + Mode *mode() const { return mode_; } + void setMode(Mode *mode); + Sdc *sdc(); + Sdc *sdc() const; + Parasitics *parasitics(const MinMax *min_max) const; + void setParasitics(Parasitics *parasitics, + const MinMaxAll *min_max); + size_t pathIndex(const MinMax *min_max) const; + + DcalcAPIndex dcalcAnalysisPtIndex(const MinMax *min_max) const; + const MinMax *checkClkSlewMinMax(const MinMax *min_max) const; + // Slew index of timing check clock. + DcalcAPIndex checkClkSlewIndex(const MinMax *min_max) const; + + const LibertySeq &libertyLibraries(const MinMax *min_max) const; + int libertyIndex(const MinMax *min_max) const; + void addLiberty(LibertyLibrary *lib, + const MinMax *min_max); + + static SceneSet sceneSet(const SceneSeq &scenes); + static ModeSeq modes(const SceneSeq &scenes); + static ModeSet modeSet(const SceneSeq &scenes); + static ModeSeq modesSorted(const SceneSeq &scenes); + +protected: + std::string name_; + size_t index_; + Mode *mode_; + LibertySeq liberty_[MinMax::index_count]; + std::array parasitics_; + + friend class Scenes; +}; + +} // namespace diff --git a/include/sta/Sdc.hh b/include/sta/Sdc.hh index b14e10cc..441db5d6 100644 --- a/include/sta/Sdc.hh +++ b/include/sta/Sdc.hh @@ -24,12 +24,13 @@ #pragma once +#include +#include +#include #include #include "StringUtil.hh" #include "StringSet.hh" -#include "Map.hh" -#include "UnorderedMap.hh" #include "MinMax.hh" #include "StaState.hh" #include "NetworkClass.hh" @@ -41,6 +42,7 @@ #include "DataCheck.hh" #include "CycleAccting.hh" #include "ExceptionPath.hh" +#include "PinPair.hh" namespace sta { @@ -58,18 +60,18 @@ class PatternMatch; class FindNetCaps; class ClkHpinDisable; class FindClkHpinDisables; -class Corner; +class Scene; class ClockPinIterator; class ClockIterator; -typedef std::pair PinClockPair; +using PinClockPair = std::pair; class ClockInsertionkLess { public: ClockInsertionkLess(const Network *network); bool operator()(const ClockInsertion *insert1, - const ClockInsertion *insert2) const; + const ClockInsertion *insert2) const; private: const Network *network_; @@ -80,7 +82,7 @@ class ClockLatencyLess public: ClockLatencyLess(const Network *network); bool operator()(const ClockLatency *latency1, - const ClockLatency *latency2) const; + const ClockLatency *latency2) const; private: const Network *network_; @@ -93,7 +95,7 @@ class ClockPairLess { public: bool operator()(const ClockPair &pair1, - const ClockPair &pair2) const; + const ClockPair &pair2) const; }; class PinClockPairLess @@ -101,7 +103,7 @@ class PinClockPairLess public: PinClockPairLess(const Network *network); bool operator()(const PinClockPair &pin_clk1, - const PinClockPair &pin_clk2) const; + const PinClockPair &pin_clk2) const; protected: const Network *network_; @@ -112,7 +114,7 @@ class ClkHpinDisableLess public: ClkHpinDisableLess(const Network *network); bool operator()(const ClkHpinDisable *disable1, - const ClkHpinDisable *disable2) const; + const ClkHpinDisable *disable2) const; private: const Network *network_; @@ -130,81 +132,81 @@ private: bool subtract_pin_cap_[MinMax::index_count]; }; -typedef Map ClockNameMap; -typedef UnorderedMap ClockPinMap; -typedef Set InputDelaySet; -typedef Map InputDelaysPinMap; -typedef Set OutputDelaySet; -typedef Map OutputDelaysPinMap; -typedef UnorderedMap PinExceptionsMap; -typedef UnorderedMap ClockExceptionsMap; -typedef UnorderedMap InstanceExceptionsMap; -typedef UnorderedMap NetExceptionsMap; -typedef UnorderedMap EdgeExceptionsMap; -typedef Vector ExceptionThruSeq; -typedef Map InputDriveMap; -typedef Map> ExceptionPathPtHash; -typedef Set ClockLatencies; -typedef Map PinClockUncertaintyMap; -typedef Set InterClockUncertaintySet; -typedef Map ClockGatingCheckMap; -typedef Map InstanceClockGatingCheckMap; -typedef Map PinClockGatingCheckMap; -typedef Set ClockInsertions; -typedef Map PinLatchBorrowLimitMap; -typedef Map InstLatchBorrowLimitMap; -typedef Map ClockLatchBorrowLimitMap; -typedef Set DataCheckSet; -typedef Map DataChecksMap; -typedef Map NetResistanceMap; -typedef Map PortSlewLimitMap; -typedef Map PinSlewLimitMap; -typedef Map CellSlewLimitMap; -typedef Map CellCapLimitMap; -typedef Map PortCapLimitMap; -typedef Map PinCapLimitMap; -typedef Map PortFanoutLimitMap; -typedef Map CellFanoutLimitMap; -typedef Map PortExtCapMap; -typedef Map NetWireCapMap; -typedef Map PinWireCapMap; -typedef Map InstancePvtMap; -typedef Map EdgeClockLatencyMap; -typedef Map PinMinPulseWidthMap; -typedef Map ClockMinPulseWidthMap; -typedef Map InstMinPulseWidthMap; -typedef Map NetDeratingFactorsMap; -typedef Map InstDeratingFactorsMap; -typedef Map CellDeratingFactorsMap; -typedef Set ClockGroupsSet; -typedef Map ClockGroupsClkMap; -typedef Map ClockGroupsNameMap; -typedef Map ClockSenseMap; -typedef Set ClkHpinDisables; -typedef Set GroupPathSet; -typedef Map GroupPathMap; -typedef Set ClockPairSet; -typedef Map NetVoltageMap; +using ClockNameMap = std::map; +using ClockPinMap = std::unordered_map; +using InputDelaySet = std::set; +using InputDelaysPinMap = std::map; +using OutputDelaySet = std::set; +using OutputDelaysPinMap = std::map; +using PinExceptionsMap = std::unordered_map; +using ClockExceptionsMap = std::unordered_map; +using InstanceExceptionsMap = std::unordered_map; +using NetExceptionsMap = std::unordered_map; +using EdgeExceptionsMap = std::unordered_map; +using InputDriveMap = std::map; +using ExceptionPathPtHash = std::map; +using ClockLatencies = std::set; +using EdgeClockLatencyMap = std::map; +using PinClockUncertaintyMap = std::map; +using InterClockUncertaintySet = std::set; +using ClockGatingCheckMap = std::map; +using InstanceClockGatingCheckMap = std::map; +using PinClockGatingCheckMap = std::map; +using ClockInsertions = std::set; +using PinLatchBorrowLimitMap = std::map; +using InstLatchBorrowLimitMap = std::map; +using ClockLatchBorrowLimitMap = std::map; +using DataCheckSet = std::set; +using DataChecksMap = std::map; +using NetResistanceMap = std::map; +using PortSlewLimitMap = std::map; +using PinSlewLimitMap = std::map; +using CellSlewLimitMap = std::map; +using CellCapLimitMap = std::map; +using PortCapLimitMap = std::map; +using PinCapLimitMap = std::map; +using PortFanoutLimitMap = std::map; +using CellFanoutLimitMap = std::map; +using PortExtCapMap = std::map; +using NetWireCapMap = std::map; +using PinWireCapMap = std::map; +using InstancePvtMap = std::map; +using PinMinPulseWidthMap = std::map; +using ClockMinPulseWidthMap = std::map; +using InstMinPulseWidthMap = std::map; +using NetDeratingFactorsMap = std::map; +using InstDeratingFactorsMap = std::map; +using CellDeratingFactorsMap = std::map; +using ClockGroupsSet = std::set; +using ClockGroupsClkMap = std::map; +using ClockGroupsNameMap = std::map; +using ClockSenseMap = std::map; +using ClkHpinDisables = std::set; +using GroupPathSet = std::set; +using GroupPathMap = std::map; +using ClockPairSet = std::set; +using NetVoltageMap = std::map; void findLeafLoadPins(const Pin *pin, - const Network *network, - PinSet *leaf_pins); + const Network *network, + PinSet *leaf_pins); void findLeafDriverPins(const Pin *pin, - const Network *network, - PinSet *leaf_pins); + const Network *network, + PinSet *leaf_pins); class Sdc : public StaState { public: - Sdc(StaState *sta); + Sdc(Mode *mode, + StaState *sta); ~Sdc(); + Mode *mode() const { return mode_; } // Note that Search may reference a Filter exception removed by clear(). void clear(); - void makeCornersBefore(); - void makeCornersAfter(Corners *corners); + void makeSceneBefore(); // Return true if pin is referenced by any constraint. bool isConstrained(const Pin *pin) const; // Return true if inst is referenced by any constraint. @@ -219,161 +221,161 @@ public: void deleteInstanceBefore(const Instance *inst); // SWIG sdc interface. - PortSeq allInputs(bool no_clks); - PortSeq allOutputs(); - AnalysisType analysisType() { return analysis_type_; } + PortSeq allInputs(bool no_clks) const; + PortSeq allOutputs() const; + AnalysisType analysisType() const { return analysis_type_; } void setAnalysisType(AnalysisType analysis_type); void setOperatingConditions(OperatingConditions *op_cond, - const MinMaxAll *min_max); + const MinMaxAll *min_max); void setOperatingConditions(OperatingConditions *op_cond, - const MinMax *min_max); + const MinMax *min_max); void setTimingDerate(TimingDerateType type, - PathClkOrData clk_data, - const RiseFallBoth *rf, - const EarlyLate *early_late, - float derate); + PathClkOrData clk_data, + const RiseFallBoth *rf, + const EarlyLate *early_late, + float derate); // Delay type is always net for net derating. void setTimingDerate(const Net *net, - PathClkOrData clk_data, - const RiseFallBoth *rf, - const EarlyLate *early_late, - float derate); + PathClkOrData clk_data, + const RiseFallBoth *rf, + const EarlyLate *early_late, + float derate); void setTimingDerate(const Instance *inst, - TimingDerateCellType type, - PathClkOrData clk_data, - const RiseFallBoth *rf, - const EarlyLate *early_late, - float derate); + TimingDerateCellType type, + PathClkOrData clk_data, + const RiseFallBoth *rf, + const EarlyLate *early_late, + float derate); void setTimingDerate(const LibertyCell *cell, - TimingDerateCellType type, - PathClkOrData clk_data, - const RiseFallBoth *rf, - const EarlyLate *early_late, - float derate); + TimingDerateCellType type, + PathClkOrData clk_data, + const RiseFallBoth *rf, + const EarlyLate *early_late, + float derate); float timingDerateInstance(const Pin *pin, - TimingDerateCellType type, - PathClkOrData clk_data, - const RiseFall *rf, - const EarlyLate *early_late) const; + TimingDerateCellType type, + PathClkOrData clk_data, + const RiseFall *rf, + const EarlyLate *early_late) const; float timingDerateNet(const Pin *pin, - PathClkOrData clk_data, - const RiseFall *rf, - const EarlyLate *early_late) const; + PathClkOrData clk_data, + const RiseFall *rf, + const EarlyLate *early_late) const; void unsetTimingDerate(); static void swapDeratingFactors(Sdc *sdc1, Sdc *sdc2); void setInputSlew(const Port *port, const RiseFallBoth *rf, - const MinMaxAll *min_max, + const MinMaxAll *min_max, float slew); // Set the rise/fall drive resistance on design port. void setDriveResistance(const Port *port, - const RiseFallBoth *rf, - const MinMaxAll *min_max, - float res); + const RiseFallBoth *rf, + const MinMaxAll *min_max, + float res); // Set the drive on design port using external cell timing arcs of // cell driven by from_slews between from_port and to_port. void setDriveCell(const LibertyLibrary *library, - const LibertyCell *cell, - const Port *port, - const LibertyPort *from_port, - float *from_slews, - const LibertyPort *to_port, - const RiseFallBoth *rf, - const MinMaxAll *min_max); + const LibertyCell *cell, + const Port *port, + const LibertyPort *from_port, + float *from_slews, + const LibertyPort *to_port, + const RiseFallBoth *rf, + const MinMaxAll *min_max); void setLatchBorrowLimit(const Pin *pin, - float limit); + float limit); void setLatchBorrowLimit(const Instance *inst, - float limit); + float limit); void setLatchBorrowLimit(const Clock *clk, - float limit); + float limit); // Return the latch borrow limit respecting precedence if multiple // limits apply. void latchBorrowLimit(const Pin *data_pin, - const Pin *enable_pin, - const Clock *clk, - // Return values. - float &limit, - bool &exists); + const Pin *enable_pin, + const Clock *clk, + // Return values. + float &limit, + bool &exists); void setMinPulseWidth(const RiseFallBoth *rf, - float min_width); + float min_width); void setMinPulseWidth(const Pin *pin, - const RiseFallBoth *rf, - float min_width); + const RiseFallBoth *rf, + float min_width); void setMinPulseWidth(const Instance *inst, - const RiseFallBoth *rf, - float min_width); + const RiseFallBoth *rf, + float min_width); void setMinPulseWidth(const Clock *clk, - const RiseFallBoth *rf, - float min_width); + const RiseFallBoth *rf, + float min_width); // Return min pulse with respecting precedence. void minPulseWidth(const Pin *pin, - const Clock *clk, - const RiseFall *hi_low, - float &min_width, - bool &exists) const; + const Clock *clk, + const RiseFall *hi_low, + float &min_width, + bool &exists) const; void setSlewLimit(Clock *clk, - const RiseFallBoth *rf, - const PathClkOrData clk_data, - const MinMax *min_max, - float slew); + const RiseFallBoth *rf, + const PathClkOrData clk_data, + const MinMax *min_max, + float slew); bool haveClkSlewLimits() const; - void slewLimit(Clock *clk, - const RiseFall *rf, - const PathClkOrData clk_data, - const MinMax *min_max, - float &slew, - bool &exists); + void slewLimit(const Clock *clk, + const RiseFall *rf, + const PathClkOrData clk_data, + const MinMax *min_max, + float &slew, + bool &exists) const; void slewLimit(Port *port, - const MinMax *min_max, - float &slew, - bool &exists); + const MinMax *min_max, + float &slew, + bool &exists) const; void setSlewLimit(Port *port, - const MinMax *min_max, - float slew); + const MinMax *min_max, + float slew); void slewLimit(Cell *cell, - const MinMax *min_max, - float &slew, - bool &exists); + const MinMax *min_max, + float &slew, + bool &exists) const; void setSlewLimit(Cell *cell, - const MinMax *min_max, - float slew); + const MinMax *min_max, + float slew); void capacitanceLimit(Port *port, - const MinMax *min_max, - float &cap, - bool &exists); + const MinMax *min_max, + float &cap, + bool &exists) const; void capacitanceLimit(Pin *pin, - const MinMax *min_max, - float &cap, - bool &exists); + const MinMax *min_max, + float &cap, + bool &exists) const; void capacitanceLimit(Cell *cell, - const MinMax *min_max, - float &cap, - bool &exists); + const MinMax *min_max, + float &cap, + bool &exists) const; void setCapacitanceLimit(Port *port, - const MinMax *min_max, - float cap); + const MinMax *min_max, + float cap); void setCapacitanceLimit(Pin *pin, - const MinMax *min_max, - float cap); + const MinMax *min_max, + float cap); void setCapacitanceLimit(Cell *cell, - const MinMax *min_max, - float cap); + const MinMax *min_max, + float cap); void fanoutLimit(Port *port, - const MinMax *min_max, - float &fanout, - bool &exists); + const MinMax *min_max, + float &fanout, + bool &exists) const; void setFanoutLimit(Port *port, - const MinMax *min_max, - float fanout); + const MinMax *min_max, + float fanout); void fanoutLimit(Cell *cell, - const MinMax *min_max, - float &fanout, - bool &exists); + const MinMax *min_max, + float &fanout, + bool &exists) const; void setFanoutLimit(Cell *cell, - const MinMax *min_max, - float fanout); + const MinMax *min_max, + float fanout); void setMaxArea(float area); float maxArea() const; Clock *makeClock(const char *name, @@ -407,79 +409,79 @@ public: void removePropagatedClock(Clock *clk); void setPropagatedClock(Pin *pin); void removePropagatedClock(Pin *pin); - bool isPropagatedClock(const Pin *pin); + bool isPropagatedClock(const Pin *pin) const; void setClockSlew(Clock *clk, - const RiseFallBoth *rf, - const MinMaxAll *min_max, - float slew); + const RiseFallBoth *rf, + const MinMaxAll *min_max, + float slew); void removeClockSlew(Clock *clk); // Latency can be on a clk, pin, or clk/pin combination. void setClockLatency(Clock *clk, - Pin *pin, - const RiseFallBoth *rf, - const MinMaxAll *min_max, - float delay); + Pin *pin, + const RiseFallBoth *rf, + const MinMaxAll *min_max, + float delay); void removeClockLatency(const Clock *clk, - const Pin *pin); + const Pin *pin); ClockLatency *clockLatency(Edge *edge) const; bool hasClockLatency(const Pin *pin) const; void clockLatency(Edge *edge, - const RiseFall *rf, - const MinMax *min_max, - // Return values. - float &latency, - bool &exists) const; + const RiseFall *rf, + const MinMax *min_max, + // Return values. + float &latency, + bool &exists) const; ClockLatencies *clockLatencies() { return &clk_latencies_; } const ClockLatencies *clockLatencies() const { return &clk_latencies_; } // Clock latency on pin with respect to clk. // This does NOT check for latency on clk (without pin). void clockLatency(const Clock *clk, - const Pin *pin, - const RiseFall *rf, - const MinMax *min_max, - // Return values. - float &latency, - bool &exists) const; + const Pin *pin, + const RiseFall *rf, + const MinMax *min_max, + // Return values. + float &latency, + bool &exists) const; void clockLatency(const Clock *clk, - const RiseFall *rf, - const MinMax *min_max, - // Return values. - float &latency, - bool &exists) const; + const RiseFall *rf, + const MinMax *min_max, + // Return values. + float &latency, + bool &exists) const; float clockLatency(const Clock *clk, - const RiseFall *rf, - const MinMax *min_max) const; + const RiseFall *rf, + const MinMax *min_max) const; // Clock insertion delay (set_clk_latency -source). // Insertion delay can be on a clk, pin, or clk/pin combination. void setClockInsertion(const Clock *clk, - const Pin *pin, - const RiseFallBoth *rf, - const MinMaxAll *min_max, - const EarlyLateAll *early_late, - float delay); + const Pin *pin, + const RiseFallBoth *rf, + const MinMaxAll *min_max, + const EarlyLateAll *early_late, + float delay); void setClockInsertion(const Clock *clk, const Pin *pin, - const RiseFall *rf, - const MinMax *min_max, - const EarlyLate *early_late, - float delay); + const RiseFall *rf, + const MinMax *min_max, + const EarlyLate *early_late, + float delay); void removeClockInsertion(const Clock *clk, - const Pin *pin); + const Pin *pin); static void swapClockInsertions(Sdc *sdc1, Sdc *sdc2); bool hasClockInsertion(const Pin *pin) const; float clockInsertion(const Clock *clk, - const RiseFall *rf, - const MinMax *min_max, - const EarlyLate *early_late) const; + const RiseFall *rf, + const MinMax *min_max, + const EarlyLate *early_late) const; // Respects precedence of pin/clk and set_input_delay on clk pin. void clockInsertion(const Clock *clk, - const Pin *pin, - const RiseFall *rf, - const MinMax *min_max, - const EarlyLate *early_late, - // Return values. - float &insertion, - bool &exists) const; + const Pin *pin, + const RiseFall *rf, + const MinMax *min_max, + const EarlyLate *early_late, + // Return values. + float &insertion, + bool &exists) const; const ClockInsertions &clockInsertions() const { return clk_insertions_; } // Clock uncertainty. void setClockUncertainty(Pin *pin, @@ -499,158 +501,151 @@ public: const RiseFallBoth *to_rf, const SetupHoldAll *setup_hold); ClockGroups *makeClockGroups(const char *name, - bool logically_exclusive, - bool physically_exclusive, - bool asynchronous, - bool allow_paths, - const char *comment); + bool logically_exclusive, + bool physically_exclusive, + bool asynchronous, + bool allow_paths, + const char *comment); void makeClockGroup(ClockGroups *clk_groups, - ClockSet *clks); + ClockSet *clks); void removeClockGroups(const char *name); // nullptr name removes all. void removeClockGroupsLogicallyExclusive(const char *name); void removeClockGroupsPhysicallyExclusive(const char *name); void removeClockGroupsAsynchronous(const char *name); bool sameClockGroup(const Clock *clk1, - const Clock *clk2); + const Clock *clk2) const; // Clocks explicitly excluded by set_clock_group. bool sameClockGroupExplicit(const Clock *clk1, - const Clock *clk2); + const Clock *clk2); void setClockSense(PinSet *pins, - ClockSet *clks, - ClockSense sense); + ClockSet *clks, + ClockSense sense); bool clkStopPropagation(const Pin *pin, - const Clock *clk) const; + const Clock *clk) const; bool clkStopPropagation(const Clock *clk, - const Pin *from_pin, - const RiseFall *from_rf, - const Pin *to_pin, - const RiseFall *to_rf) const; + const Pin *from_pin, + const RiseFall *from_rf, + const Pin *to_pin, + const RiseFall *to_rf) const; void setClockGatingCheck(const RiseFallBoth *rf, - const SetupHold *setup_hold, - float margin); + const SetupHold *setup_hold, + float margin); void setClockGatingCheck(Instance *inst, - const RiseFallBoth *rf, - const SetupHold *setup_hold, - float margin, - LogicValue active_value); + const RiseFallBoth *rf, + const SetupHold *setup_hold, + float margin, + LogicValue active_value); void setClockGatingCheck(Clock *clk, - const RiseFallBoth *rf, - const SetupHold *setup_hold, - float margin); + const RiseFallBoth *rf, + const SetupHold *setup_hold, + float margin); void setClockGatingCheck(const Pin *pin, - const RiseFallBoth *rf, - const SetupHold *setup_hold, - float margin, - LogicValue active_value); + const RiseFallBoth *rf, + const SetupHold *setup_hold, + float margin, + LogicValue active_value); void setDataCheck(Pin *from, - const RiseFallBoth *from_rf, - Pin *to, - const RiseFallBoth *to_rf, - Clock *clk, - const SetupHoldAll *setup_hold, - float margin); + const RiseFallBoth *from_rf, + Pin *to, + const RiseFallBoth *to_rf, + Clock *clk, + const SetupHoldAll *setup_hold, + float margin); void removeDataCheck(Pin *from, - const RiseFallBoth *from_rf, - Pin *to, - const RiseFallBoth *to_rf, - Clock *clk, - const SetupHoldAll *setup_hold); + const RiseFallBoth *from_rf, + Pin *to, + const RiseFallBoth *to_rf, + Clock *clk, + const SetupHoldAll *setup_hold); DataCheckSet *dataChecksFrom(const Pin *from) const; DataCheckSet *dataChecksTo(const Pin *to) const; void setInputDelay(const Pin *pin, - const RiseFallBoth *rf, - const Clock *clk, - const RiseFall *clk_rf, - const Pin *ref_pin, - bool source_latency_included, - bool network_latency_included, - const MinMaxAll *min_max, - bool add, + const RiseFallBoth *rf, + const Clock *clk, + const RiseFall *clk_rf, + const Pin *ref_pin, + bool source_latency_included, + bool network_latency_included, + const MinMaxAll *min_max, + bool add, float delay); void removeInputDelay(const Pin *pin, - const RiseFallBoth *rf, - const Clock *clk, - const RiseFall *clk_rf, - const MinMaxAll *min_max); + const RiseFallBoth *rf, + const Clock *clk, + const RiseFall *clk_rf, + const MinMaxAll *min_max); void setOutputDelay(const Pin *pin, - const RiseFallBoth *rf, - const Clock *clk, - const RiseFall *clk_tr, - const Pin *ref_pin, - bool source_latency_included, - bool network_latency_included, - const MinMaxAll *min_max, - bool add, + const RiseFallBoth *rf, + const Clock *clk, + const RiseFall *clk_tr, + const Pin *ref_pin, + bool source_latency_included, + bool network_latency_included, + const MinMaxAll *min_max, + bool add, float delay); void removeOutputDelay(const Pin *pin, - const RiseFallBoth *rf, - const Clock *clk, - const RiseFall *clk_rf, - const MinMaxAll *min_max); + const RiseFallBoth *rf, + const Clock *clk, + const RiseFall *clk_rf, + const MinMaxAll *min_max); static void swapPortDelays(Sdc *sdc1, Sdc *sdc2); // Set port external pin load (set_load -pin_load port). void setPortExtPinCap(const Port *port, - const RiseFall *rf, - const Corner *corner, - const MinMax *min_max, - float cap); + const RiseFall *rf, + const MinMax *min_max, + float cap); // Set port external wire load (set_load -wire port). void setPortExtWireCap(const Port *port, - bool subtract_pin_cap, - const RiseFall *rf, - const Corner *corner, - const MinMax *min_max, - float cap); + const RiseFall *rf, + const MinMax *min_max, + float cap); static void swapPortExtCaps(Sdc *sdc1, Sdc *sdc2); // Remove all "set_load net" annotations. void removeNetLoadCaps(); void setNetWireCap(const Net *net, - bool subtract_pin_cap, - const Corner *corner, - const MinMax *min_max, - float wire_cap); + bool subtract_pin_cap, + const MinMax *min_max, + float wire_cap); bool hasNetWireCap(const Net *net) const; // True if driver pin net has wire capacitance. - bool drvrPinHasWireCap(const Pin *pin, - const Corner *corner); + bool drvrPinHasWireCap(const Pin *pin) const; // Net wire capacitance (set_load -wire net). void drvrPinWireCap(const Pin *drvr_pin, - const Corner *corner, - const MinMax *min_max, - // Return values. - float &cap, - bool &exists, + const MinMax *min_max, + // Return values. + float &cap, + bool &exists, bool &subtract_pin_cap) const; // Pin capacitance derated by operating conditions and instance pvt. float pinCapacitance(const Pin *pin, - const RiseFall *rf, - const Corner *corner, - const MinMax *min_max); + const RiseFall *rf, + const Scene *scene, + const MinMax *min_max) const; void setResistance(const Net *net, - const MinMaxAll *min_max, - float res); + const MinMaxAll *min_max, + float res); void resistance(const Net *net, - const MinMax *min_max, - float &res, - bool &exists); - NetResistanceMap &netResistances() { return net_res_map_; } + const MinMax *min_max, + float &res, + bool &exists) const; + const NetResistanceMap &netResistances() const { return net_res_map_; } void setPortExtFanout(const Port *port, - const Corner *corner, - const MinMax *min_max, - int fanout); + const MinMax *min_max, + int fanout); // set_disable_timing cell [-from] [-to] // Disable all edges thru cell if from/to are null. // Bus and bundle ports are NOT supported. void disable(LibertyCell *cell, - LibertyPort *from, - LibertyPort *to); + LibertyPort *from, + LibertyPort *to); void removeDisable(LibertyCell *cell, - LibertyPort *from, - LibertyPort *to); + LibertyPort *from, + LibertyPort *to); // set_disable_timing liberty port. // Bus and bundle ports are NOT supported. void disable(LibertyPort *port); @@ -663,11 +658,11 @@ public: // Disable all edges thru instance if from/to are null. // Bus and bundle ports are NOT supported. void disable(Instance *inst, - LibertyPort *from, - LibertyPort *to); + LibertyPort *from, + LibertyPort *to); void removeDisable(Instance *inst, - LibertyPort *from, - LibertyPort *to); + LibertyPort *from, + LibertyPort *to); // set_disable_timing pin void disable(const Pin *pin); void removeDisable(Pin *pin); @@ -679,127 +674,140 @@ public: void removeDisable(TimingArcSet *arc_set); // Disable a wire edge. From/to pins musts be on the same net. // There is no SDC equivalent to this. - void disable(Pin *from, Pin *to); - void removeDisable(Pin *from, Pin *to); - bool isDisabled(const Pin *pin) const; + void disableWire(const Pin *from, + const Pin *to); + void removeDisableWire(Pin *from, + Pin *to); + [[nodiscard]] bool isDisabledWire(const Pin *from, + const Pin *to) const; + [[nodiscard]] bool isDisabledConstraint(const Pin *pin) const; // Edge disabled by hierarchical pin disable or instance/cell port pair. // Disables do NOT apply to timing checks. // inst can be either the from_pin or to_pin instance because it // is only referenced when they are the same (non-wire edge). - bool isDisabled(const Instance *inst, - const Pin *from_pin, - const Pin *to_pin, - const TimingRole *role) const; - bool isDisabled(Edge *edge); - bool isDisabled(TimingArcSet *arc_set) const; - DisabledCellPortsMap *disabledCellPorts(); + [[nodiscard]] bool isDisabled(const Instance *inst, + const Pin *from_pin, + const Pin *to_pin, + const TimingRole *role) const; + [[nodiscard]] bool isDisabled(const Edge *edge) const; + [[nodiscard]] bool isDisabled(TimingArcSet *arc_set) const; + const DisabledCellPortsMap *disabledCellPorts() const; const DisabledInstancePortsMap *disabledInstancePorts() const; const PinSet *disabledPins() const { return &disabled_pins_; } const PortSet *disabledPorts() const { return &disabled_ports_; } const LibertyPortSet *disabledLibPorts() const { return &disabled_lib_ports_; } const EdgeSet *disabledEdges() const { return &disabled_edges_; } + [[nodiscard]] bool isDisabledConstraint(const Edge *edge) const; + void disableClockGatingCheck(Instance *inst); void disableClockGatingCheck(Pin *pin); void removeDisableClockGatingCheck(Instance *inst); void removeDisableClockGatingCheck(Pin *pin); - bool isDisableClockGatingCheck(const Pin *pin); - bool isDisableClockGatingCheck(const Instance *inst); + bool isDisableClockGatingCheck(const Pin *pin) const; + bool isDisableClockGatingCheck(const Instance *inst) const; // set_LogicValue::zero, set_LogicValue::one, set_logic_dc void setLogicValue(const Pin *pin, - LogicValue value); + LogicValue value); // set_case_analysis void setCaseAnalysis(const Pin *pin, - LogicValue value); + LogicValue value); void removeCaseAnalysis(const Pin *pin); void logicValue(const Pin *pin, - LogicValue &value, - bool &exists); + LogicValue &value, + bool &exists) const; void caseLogicValue(const Pin *pin, LogicValue &value, - bool &exists); + bool &exists) const; // Pin has set_case_analysis or set_logic constant value. - bool hasLogicValue(const Pin *pin); + bool hasLogicValue(const Pin *pin) const; + // The from/thrus/to arguments passed into the following functions // that make exceptions are owned by the constraints once they are // passed in. The constraint internals may change or delete them do // to exception merging. void makeFalsePath(ExceptionFrom *from, - ExceptionThruSeq *thrus, - ExceptionTo *to, - const MinMaxAll *min_max, - const char *comment); + ExceptionThruSeq *thrus, + ExceptionTo *to, + const MinMaxAll *min_max, + const char *comment); // Loop paths are false paths used to disable paths around // combinational loops when dynamic loop breaking is enabled. void makeLoopExceptions(); void makeLoopExceptions(GraphLoop *loop); void deleteLoopExceptions(); void makeMulticyclePath(ExceptionFrom *from, - ExceptionThruSeq *thrus, - ExceptionTo *to, - const MinMaxAll *min_max, - bool use_end_clk, - int path_multiplier, - const char *comment); + ExceptionThruSeq *thrus, + ExceptionTo *to, + const MinMaxAll *min_max, + bool use_end_clk, + int path_multiplier, + const char *comment); void makePathDelay(ExceptionFrom *from, - ExceptionThruSeq *thrus, - ExceptionTo *to, - const MinMax *min_max, - bool ignore_clk_latency, + ExceptionThruSeq *thrus, + ExceptionTo *to, + const MinMax *min_max, + bool ignore_clk_latency, bool break_path, - float delay, - const char *comment); + float delay, + const char *comment); bool pathDelaysWithoutTo() const { return path_delays_without_to_; } // Delete matching false/multicycle/path_delay exceptions. // Caller owns from, thrus, to exception points (and must delete them). void resetPath(ExceptionFrom *from, - ExceptionThruSeq *thrus, - ExceptionTo *to, - const MinMaxAll *min_max); + ExceptionThruSeq *thrus, + ExceptionTo *to, + const MinMaxAll *min_max); void makeGroupPath(const char *name, - bool is_default, - ExceptionFrom *from, - ExceptionThruSeq *thrus, - ExceptionTo *to, - const char *comment); - bool isGroupPathName(const char *group_name); - GroupPathMap &groupPaths() { return group_path_map_; } + bool is_default, + ExceptionFrom *from, + ExceptionThruSeq *thrus, + ExceptionTo *to, + const char *comment); + bool isGroupPathName(const char *group_name) const; + const GroupPathMap &groupPaths() const { return group_path_map_; } void addException(ExceptionPath *exception); // The pin/clk/instance/net set arguments passed into the following // functions that make exception from/thru/to's are owned by the // constraints once they are passed in. ExceptionFrom *makeExceptionFrom(PinSet *from_pins, - ClockSet *from_clks, - InstanceSet *from_insts, - const RiseFallBoth *from_rf); + ClockSet *from_clks, + InstanceSet *from_insts, + const RiseFallBoth *from_rf) const; bool isExceptionStartpoint(const Pin *pin) const; // Make an exception -through specification. ExceptionThru *makeExceptionThru(PinSet *pins, - NetSet *nets, - InstanceSet *insts, - const RiseFallBoth *rf); - bool isExceptionEndpoint(const Pin *pin); + NetSet *nets, + InstanceSet *insts, + const RiseFallBoth *rf) const; + bool isExceptionEndpoint(const Pin *pin) const; // Make an exception -to specification. ExceptionTo *makeExceptionTo(PinSet *pins, - ClockSet *clks, - InstanceSet *insts, - const RiseFallBoth *rf, - const RiseFallBoth *end_rf); + ClockSet *clks, + InstanceSet *insts, + const RiseFallBoth *rf, + const RiseFallBoth *end_rf) const; + FilterPath *makeFilterPath(ExceptionFrom *from, - ExceptionThruSeq *thrus, - ExceptionTo *to); - Wireload *wireload(const MinMax *min_max); + ExceptionThruSeq *thrus, + ExceptionTo *to); + void makeFilter(ExceptionFrom *from, + ExceptionThruSeq *thrus); + FilterPath *filter() const { return filter_; } + void deleteFilter(); + + Wireload *wireload(const MinMax *min_max) const; void setWireload(Wireload *wireload, - const MinMaxAll *min_max); - WireloadMode wireloadMode(); + const MinMaxAll *min_max); + WireloadMode wireloadMode() const { return wireload_mode_; }; void setWireloadMode(WireloadMode mode); const WireloadSelection *wireloadSelection(const MinMax *min_max); void setWireloadSelection(WireloadSelection *selection, - const MinMaxAll *min_max); + const MinMaxAll *min_max); // STA interface. InputDelaySet *refPinInputDelays(const Pin *ref_pin) const; - LogicValueMap &logicValues() { return logic_value_map_; } - LogicValueMap &caseLogicValues() { return case_value_map_; } + const LogicValueMap &logicValues() const { return logic_value_map_; } + const LogicValueMap &caseLogicValues() const { return case_value_map_; } // Returns nullptr if set_operating_conditions has not been called. OperatingConditions *operatingConditions(const MinMax *min_max) const; // Instance specific process/voltage/temperature. @@ -807,23 +815,23 @@ public: const MinMax *min_max) const; // Pvt may be shared among multiple instances. void setPvt(const Instance *inst, - const MinMaxAll *min_max, - const Pvt &pvt); + const MinMaxAll *min_max, + const Pvt &pvt); void voltage(const MinMax *min_max, // Return values. float &voltage, - bool &exists); + bool &exists) const; void voltage(const Net *net, const MinMax *min_max, // Return values. float &voltage, - bool &exists); + bool &exists) const; void setVoltage(const MinMax *min_max, float voltage); void setVoltage(const Net *net, const MinMax *min_max, float voltage); - InputDrive *findInputDrive(Port *port); + InputDrive *findInputDrive(Port *port) const; Clock *findClock(const char *name) const; ClockSeq findClocksMatching(PatternMatch *pattern) const; // True if pin is defined as a clock source (pin may be hierarchical). @@ -835,51 +843,63 @@ public: // Find the clocks defined for pin. ClockSet *findClocks(const Pin *pin) const; ClockSet *findLeafPinClocks(const Pin *pin) const; - void sortedClocks(ClockSeq &clks); - ClockSeq *clocks() { return &clocks_; } - ClockSeq &clks() { return clocks_; } + const ClockSeq &clocks() const { return clocks_; } + ClockSeq sortedClocks() const; bool clkDisabledByHpinThru(const Clock *clk, - const Pin *from_pin, - const Pin *to_pin); + const Pin *from_pin, + const Pin *to_pin) const; void clkHpinDisablesInvalid(); - ClockUncertainties *clockUncertainties(const Pin *pin); + const ClockUncertainties *clockUncertainties(const Pin *pin) const; void clockUncertainty(const Pin *pin, - const SetupHold *setup_hold, - float &uncertainty, - bool &exists); + const SetupHold *setup_hold, + // Return values. + float &uncertainty, + bool &exists); // Inter-clock uncertainty. void clockUncertainty(const Clock *src_clk, - const RiseFall *src_rf, - const Clock *tgt_clk, - const RiseFall *tgt_rf, - const SetupHold *setup_hold, - float &uncertainty, bool &exists); + const RiseFall *src_rf, + const Clock *tgt_clk, + const RiseFall *tgt_rf, + const SetupHold *setup_hold, + // Return values. + float &uncertainty, + bool &exists) const; void clockGatingMarginEnablePin(const Pin *enable_pin, - const RiseFall *enable_rf, - const SetupHold *setup_hold, - bool &exists, float &margin); + const RiseFall *enable_rf, + const SetupHold *setup_hold, + // Return values. + bool &exists, + float &margin) const; void clockGatingMarginInstance(Instance *inst, - const RiseFall *enable_rf, - const SetupHold *setup_hold, - bool &exists, float &margin); + const RiseFall *enable_rf, + const SetupHold *setup_hold, + // Return values. + bool &exists, + float &margin) const; void clockGatingMarginClkPin(const Pin *clk_pin, - const RiseFall *enable_rf, - const SetupHold *setup_hold, - bool &exists, float &margin); + const RiseFall *enable_rf, + const SetupHold *setup_hold, + // Return values. + bool &exists, + float &margin) const; void clockGatingMarginClk(const Clock *clk, - const RiseFall *enable_rf, - const SetupHold *setup_hold, - bool &exists, float &margin); + const RiseFall *enable_rf, + const SetupHold *setup_hold, + // Return values. + bool &exists, + float &margin) const; void clockGatingMargin(const RiseFall *enable_rf, - const SetupHold *setup_hold, - bool &exists, float &margin); + const SetupHold *setup_hold, + // Return values. + bool &exists, + float &margin) const; // Gated clock active (non-controlling) logic value. LogicValue clockGatingActiveValue(const Pin *clk_pin, - const Pin *enable_pin); + const Pin *enable_pin) const; // Find the cycle accounting info for paths that start at src clock // edge and end at target clock edge. CycleAccting *cycleAccting(const ClockEdge *src, - const ClockEdge *tgt); + const ClockEdge *tgt); // Report clock to clock relationships that exceed max_cycle_count. void reportClkToClkMaxCycleWarnings(); @@ -887,7 +907,7 @@ public: // Pin -> input delays. const InputDelaysPinMap &inputDelayPinMap() const { return input_delay_pin_map_; } // Input delays on leaf_pin. - InputDelaySet *inputDelaysLeafPin(const Pin *leaf_pin); + InputDelaySet *inputDelaysLeafPin(const Pin *leaf_pin) const; bool hasInputDelay(const Pin *leaf_pin) const; // Pin is internal (not top level port) and has an input arrival. bool isInputDelayInternal(const Pin *pin) const; @@ -896,99 +916,94 @@ public: // Pin -> output delays. const OutputDelaysPinMap &outputDelaysPinMap() const { return output_delay_pin_map_; } // Output delays on leaf_pin. - OutputDelaySet *outputDelaysLeafPin(const Pin *leaf_pin); - bool hasOutputDelay(const Pin *leaf_pin) const; + OutputDelaySet *outputDelaysLeafPin(const Pin *leaf_pin) const; + [[nodiscard]] bool hasOutputDelay(const Pin *leaf_pin) const; - PortExtCap *portExtCap(const Port *port, - const Corner *corner) const; + const PortExtCap *portExtCap(const Port *port) const; bool hasPortExtCap(const Port *port) const; void portExtCap(const Port *port, - const RiseFall *rf, - const Corner *corner, - const MinMax *min_max, - // Return values. - float &pin_cap, - bool &has_pin_cap, - float &wire_cap, - bool &has_wire_cap, - int &fanout, - bool &has_fanout) const; + const RiseFall *rf, + const MinMax *min_max, + // Return values. + float &pin_cap, + bool &has_pin_cap, + float &wire_cap, + bool &has_wire_cap, + int &fanout, + bool &has_fanout) const; float portExtCap(const Port *port, - const RiseFall *rf, - const Corner *corner, - const MinMax *min_max) const; + const RiseFall *rf, + const MinMax *min_max) const; // Connected total capacitance. // pin_cap = pin capacitance + port external pin // wire_cap = port external wire capacitance + net wire capacitance void connectedCap(const Pin *pin, - const RiseFall *rf, - const Corner *corner, - const MinMax *min_max, - float &pin_cap, - float &wire_cap, - float &fanout, - bool &has_net_load) const; + const RiseFall *rf, + const Scene *scene, + const MinMax *min_max, + float &pin_cap, + float &wire_cap, + float &fanout, + bool &has_net_load) const; void pinCaps(const Pin *pin, - const RiseFall *rf, - const Corner *corner, - const MinMax *min_max, - float &pin_cap, - float &wire_cap, - float &fanout) const; + const RiseFall *rf, + const Scene *scene, + const MinMax *min_max, + float &pin_cap, + float &wire_cap, + float &fanout) const; void portExtFanout(const Port *port, - const Corner *corner, - const MinMax *min_max, - // Return values. - int &fanout, - bool &exists); + const MinMax *min_max, + // Return values. + int &fanout, + bool &exists) const; int portExtFanout(Port *port, - const Corner *corner, - const MinMax *min_max); + const MinMax *min_max) const; // Return true if search should proceed from pin/clk (no false paths // start at pin/clk). When thru is true, consider -thru exceptions // that start at pin/net/instance also). Transition tr applies to // pin, not clk. bool exceptionFromStates(const Pin *pin, - const RiseFall *rf, - const Clock *clk, - const RiseFall *clk_rf, - const MinMax *min_max, - ExceptionStateSet *&states) const; + const RiseFall *rf, + const Clock *clk, + const RiseFall *clk_rf, + const MinMax *min_max, + ExceptionStateSet *&states); bool exceptionFromStates(const Pin *pin, - const RiseFall *rf, - const Clock *clk, - const RiseFall *clk_rf, - const MinMax *min_max, - bool include_filter, - ExceptionStateSet *&states) const; + const RiseFall *rf, + const Clock *clk, + const RiseFall *clk_rf, + const MinMax *min_max, + bool include_filter, + ExceptionStateSet *&states); void exceptionFromClkStates(const Pin *pin, - const RiseFall *rf, - const Clock *clk, - const RiseFall *clk_rf, - const MinMax *min_max, - ExceptionStateSet *&states) const; + const RiseFall *rf, + const Clock *clk, + const RiseFall *clk_rf, + const MinMax *min_max, + ExceptionStateSet *&states); void filterRegQStates(const Pin *to_pin, - const RiseFall *to_rf, - const MinMax *min_max, - ExceptionStateSet *&states) const; + const RiseFall *to_rf, + const MinMax *min_max, + ExceptionStateSet *&states) const; // Return hierarchical -thru exceptions that start between // from_pin and to_pin. void exceptionThruStates(const Pin *from_pin, const Pin *to_pin, const RiseFall *to_rf, const MinMax *min_max, - ExceptionStateSet *&states) const; + ExceptionStateSet *&states); // Find the highest priority exception with first exception pt at // pin/clk end. void exceptionTo(ExceptionPathType type, - const Pin *pin, - const RiseFall *rf, - const ClockEdge *clk_edge, - const MinMax *min_max, - bool match_min_max_exactly, - // Return values. - ExceptionPath *&hi_priority_exception, - int &hi_priority) const; + const Pin *pin, + const RiseFall *rf, + const ClockEdge *clk_edge, + const MinMax *min_max, + bool match_min_max_exactly, + // Return values. + ExceptionPath *&hi_priority_exception, + int &hi_priority); bool exceptionMatchesTo(ExceptionPath *exception, const Pin *pin, const RiseFall *rf, @@ -997,18 +1012,18 @@ public: bool match_min_max_exactly, bool require_to_pin) const; void groupPathsTo(const Pin *pin, - const RiseFall *rf, - const ClockEdge *clk_edge, - const MinMax *min_max, - // Return value. - ExceptionPathSeq &group_paths) const; + const RiseFall *rf, + const ClockEdge *clk_edge, + const MinMax *min_max, + // Return value. + ExceptionPathSeq &group_paths); bool isCompleteTo(ExceptionState *state, - const Pin *pin, - const RiseFall *rf, - const ClockEdge *clk_edge, - const MinMax *min_max, - bool match_min_max_exactly, - bool require_to_pin) const; + const Pin *pin, + const RiseFall *rf, + const ClockEdge *clk_edge, + const MinMax *min_max, + bool match_min_max_exactly, + bool require_to_pin) const; bool isCompleteTo(ExceptionState *state, const Pin *pin, const RiseFall *rf, @@ -1018,29 +1033,39 @@ public: const PinSet &pathDelayInternalFrom() const; bool isPathDelayInternalTo(const Pin *pin) const; bool isPathDelayInternalToBreak(const Pin *pin) const; - ExceptionPathSet &exceptions() { return exceptions_; } + const ExceptionPathSet &exceptions() const { return exceptions_; } void deleteExceptions(); void deleteException(ExceptionPath *exception); void recordException(ExceptionPath *exception); void unrecordException(ExceptionPath *exception); - void annotateGraph(); - void removeGraphAnnotations(); // Network edit before/after methods. void deletePinBefore(const Pin *pin); void connectPinAfter(const Pin *pin); void clkHpinDisablesChanged(const Pin *pin); void makeClkHpinDisable(const Clock *clk, - const Pin *drvr, - const Pin *load); + const Pin *drvr, + const Pin *load); void ensureClkHpinDisables(); + //////////////////////////////////////////////////////////////// + // + // Sdc/Mode dependewnt state + // + //////////////////////////////////////////////////////////////// + + // Vertices are constrained if they have one or more of the + // following timing constraints: + // output delay constraints + // data check constraints + // path delay constraints + bool isConstrainedEnd(const Pin *pin) const; + protected: void portMembers(const Port *port, - PortSeq &ports); + PortSeq &ports) const; void initVariables(); void clearCycleAcctings(); - void removeLibertyAnnotations(); void deleteExceptionsReferencing(Clock *clk); void deleteClkPinMappings(Clock *clk); void makeClkPinMappings(Clock *clk); @@ -1048,8 +1073,6 @@ protected: PinSet *pins); void makeDefaultArrivalClock(); InputDrive *ensureInputDrive(const Port *port); - PortExtCap *ensurePortExtPinCap(const Port *port, - const Corner *corner); ExceptionPath *findMergeMatch(ExceptionPath *exception); void addException1(ExceptionPath *exception); void addException2(ExceptionPath *exception); @@ -1063,140 +1086,140 @@ protected: bool hasLibertyCheckTo(const Pin *pin); void deleteMatchingExceptions(ExceptionPath *exception); void findMatchingExceptions(ExceptionPath *exception, - ExceptionPathSet &matches); + ExceptionPathSet &matches); void checkForThruHpins(ExceptionPath *exception); void findMatchingExceptionsFirstFrom(ExceptionPath *exception, - ExceptionPathSet &matches); + ExceptionPathSet &matches); void findMatchingExceptionsFirstThru(ExceptionPath *exception, - ExceptionPathSet &matches); + ExceptionPathSet &matches); void findMatchingExceptionsFirstTo(ExceptionPath *exception, - ExceptionPathSet &matches); + ExceptionPathSet &matches); void findMatchingExceptionsClks(ExceptionPath *exception, - ClockSet *clks, - ClockExceptionsMap &exception_map, - ExceptionPathSet &matches); + ClockSet *clks, + ClockExceptionsMap &exception_map, + ExceptionPathSet &matches); void findMatchingExceptionsPins(ExceptionPath *exception, - PinSet *pins, - PinExceptionsMap &exception_map, - ExceptionPathSet &matches); + PinSet *pins, + PinExceptionsMap &exception_map, + ExceptionPathSet &matches); void findMatchingExceptionsInsts(ExceptionPath *exception, - InstanceSet *insts, - InstanceExceptionsMap &exception_map, - ExceptionPathSet &matches); + InstanceSet *insts, + InstanceExceptionsMap &exception_map, + ExceptionPathSet &matches); void findMatchingExceptions(ExceptionPath *exception, - ExceptionPathSet *potential_matches, - ExceptionPathSet &matches); + ExceptionPathSet *potential_matches, + ExceptionPathSet &matches); void expandExceptionExcluding(ExceptionPath *exception, - ExceptionPath *excluding, - ExceptionPathSet &expanded_matches); + ExceptionPath *excluding, + ExceptionPathSet &expanded_matches); void recordException1(ExceptionPath *exception); void recordExceptionFirstPts(ExceptionPath *exception); void recordExceptionFirstFrom(ExceptionPath *exception); void recordExceptionFirstThru(ExceptionPath *exception); void recordExceptionFirstTo(ExceptionPath *exception); void recordExceptionClks(ExceptionPath *exception, - ClockSet *clks, - ClockExceptionsMap &exception_map); + ClockSet *clks, + ClockExceptionsMap &exception_map); void recordExceptionInsts(ExceptionPath *exception, - InstanceSet *insts, - InstanceExceptionsMap &exception_map); + InstanceSet *insts, + InstanceExceptionsMap &exception_map); void recordExceptionPins(ExceptionPath *exception, - PinSet *pins, - PinExceptionsMap &exception_map); + PinSet *pins, + PinExceptionsMap &exception_map); void recordExceptionNets(ExceptionPath *exception, - NetSet *nets, - NetExceptionsMap &exception_map); + NetSet *nets, + NetExceptionsMap &exception_map); void recordExceptionHpin(ExceptionPath *exception, - Pin *pin, - PinExceptionsMap &exception_map); + Pin *pin, + PinExceptionsMap &exception_map); void recordExceptionEdges(ExceptionPath *exception, - EdgePinsSet *edges, - EdgeExceptionsMap &exception_map); + EdgePinsSet *edges, + EdgeExceptionsMap &exception_map); void recordMergeHash(ExceptionPath *exception, ExceptionPt *missing_pt); void recordMergeHashes(ExceptionPath *exception); void unrecordExceptionFirstPts(ExceptionPath *exception); void unrecordExceptionPins(ExceptionPath *exception); void unrecordExceptionClks(ExceptionPath *exception, - ClockSet *clks, - ClockExceptionsMap &exception_map); + ClockSet *clks, + ClockExceptionsMap &exception_map); void unrecordExceptionPins(ExceptionPath *exception, - PinSet *pins, - PinExceptionsMap &exception_map); + PinSet *pins, + PinExceptionsMap &exception_map); void unrecordExceptionInsts(ExceptionPath *exception, - InstanceSet *insts, - InstanceExceptionsMap &exception_map); + InstanceSet *insts, + InstanceExceptionsMap &exception_map); void unrecordExceptionEdges(ExceptionPath *exception, - EdgePinsSet *edges, - EdgeExceptionsMap &exception_map); + EdgePinsSet *edges, + EdgeExceptionsMap &exception_map); void unrecordExceptionNets(ExceptionPath *exception, - NetSet *nets, - NetExceptionsMap &exception_map); + NetSet *nets, + NetExceptionsMap &exception_map); void unrecordExceptionHpin(ExceptionPath *exception, - Pin *pin, - PinExceptionsMap &exception_map); + Pin *pin, + PinExceptionsMap &exception_map); void unrecordMergeHashes(ExceptionPath *exception); void unrecordMergeHash(ExceptionPath *exception, - ExceptionPt *missing_pt); + ExceptionPt *missing_pt); void mergeException(ExceptionPath *exception); void expandException(ExceptionPath *exception, - ExceptionPathSet &expansions); + ExceptionPathSet &expansions); bool exceptionFromStates(const ExceptionPathSet *exceptions, - const Pin *pin, - const RiseFall *rf, - const MinMax *min_max, - bool include_filter, - ExceptionStateSet *&states) const; + const Pin *pin, + const RiseFall *rf, + const MinMax *min_max, + bool include_filter, + ExceptionStateSet *&states) const; void exceptionThruStates(const ExceptionPathSet *exceptions, - const RiseFall *to_rf, - const MinMax *min_max, - // Return value. - ExceptionStateSet *&states) const; + const RiseFall *to_rf, + const MinMax *min_max, + // Return value. + ExceptionStateSet *&states) const; void exceptionTo(const ExceptionPathSet *to_exceptions, - ExceptionPathType type, - const Pin *pin, - const RiseFall *rf, - const ClockEdge *clk_edge, - const MinMax *min_max, - bool match_min_max_exactly, - // Return values. - ExceptionPath *&hi_priority_exception, - int &hi_priority) const; + ExceptionPathType type, + const Pin *pin, + const RiseFall *rf, + const ClockEdge *clk_edge, + const MinMax *min_max, + bool match_min_max_exactly, + // Return values. + ExceptionPath *&hi_priority_exception, + int &hi_priority) const; void exceptionTo(ExceptionPath *exception, - ExceptionPathType type, - const Pin *pin, - const RiseFall *rf, - const ClockEdge *clk_edge, - const MinMax *min_max, - bool match_min_max_exactly, - // Return values. - ExceptionPath *&hi_priority_exception, - int &hi_priority) const; + ExceptionPathType type, + const Pin *pin, + const RiseFall *rf, + const ClockEdge *clk_edge, + const MinMax *min_max, + bool match_min_max_exactly, + // Return values. + ExceptionPath *&hi_priority_exception, + int &hi_priority) const; void groupPathsTo(const ExceptionPathSet *to_exceptions, - const Pin *pin, - const RiseFall *rf, - const ClockEdge *clk_edge, - const MinMax *min_max, - // Return value. - ExceptionPathSeq &group_paths) const; + const Pin *pin, + const RiseFall *rf, + const ClockEdge *clk_edge, + const MinMax *min_max, + // Return value. + ExceptionPathSeq &group_paths) const; void makeLoopPath(ExceptionThruSeq *thrus); void makeLoopException(const Pin *loop_input_pin, - const Pin *loop_pin, - const Pin *loop_prev_pin); + const Pin *loop_pin, + const Pin *loop_prev_pin); void makeLoopExceptionThru(const Pin *pin, - ExceptionThruSeq *thrus); + ExceptionThruSeq *thrus); void deleteConstraints(); InputDelay *findInputDelay(const Pin *pin, - const ClockEdge *clk_edge); + const ClockEdge *clk_edge); InputDelay *makeInputDelay(const Pin *pin, - const ClockEdge *clk_edge); + const ClockEdge *clk_edge); void deleteInputDelays(const Pin *pin, - InputDelay *except); + InputDelay *except); void deleteInputDelaysReferencing(const Clock *clk); void deleteInputDelay(InputDelay *input_delay); OutputDelay *findOutputDelay(const Pin *pin, - const ClockEdge *clk_edge); + const ClockEdge *clk_edge); OutputDelay *makeOutputDelay(const Pin *pin, - const ClockEdge *clk_edge); + const ClockEdge *clk_edge); void deleteOutputDelays(const Pin *pin, OutputDelay *except); void deleteOutputDelaysReferencing(const Clock *clk); @@ -1211,44 +1234,32 @@ protected: // Liberty library to look for defaults. LibertyLibrary *defaultLibertyLibrary(); void annotateGraphConstrainOutputs(); - void annotateDisables(); - void annotateGraphDisabled(const Pin *pin); - void setEdgeDisabledInstPorts(DisabledInstancePorts *disabled_inst); - void setEdgeDisabledInstFrom(Pin *from_pin, - bool disable_checks); - void setEdgeDisabledInstPorts(DisabledPorts *disabled_port, - Instance *inst); void deleteClockLatenciesReferencing(Clock *clk); void deleteClockLatency(ClockLatency *latency); void deleteDeratingFactors(); - void annotateGraphOutputDelays(); - void annotateGraphDataChecks(); - void annotateGraphConstrained(const PinSet *pins); - void annotateGraphConstrained(const InstanceSet *insts); - void annotateGraphConstrained(const Instance *inst); - void annotateGraphConstrained(const Pin *pin); + void annotateHierClkLatency(); void annotateHierClkLatency(const Pin *hpin, - ClockLatency *latency); + ClockLatency *latency); void netCaps(const Pin *drvr_pin, - const RiseFall *rf, - const Corner *corner, - const MinMax *min_max, - // Return values. - float &pin_cap, - float &wire_cap, - float &fanout, + const RiseFall *rf, + const Scene *scene, + const MinMax *min_max, + // Return values. + float &pin_cap, + float &wire_cap, + float &fanout, bool &has_net_load) const; // connectedCap pin_cap. float connectedPinCap(const Pin *pin, - const RiseFall *rf, - const Corner *corner, - const MinMax *min_max); + const RiseFall *rf, + const Scene *scene, + const MinMax *min_max); float portCapacitance(Instance *inst, LibertyPort *port, - const RiseFall *rf, - const Corner *corner, - const MinMax *min_max) const; + const RiseFall *rf, + const Scene *scene, + const MinMax *min_max) const; void removeClockGroups(ClockGroups *groups); void ensureClkGroupExclusions(); void makeClkGroupExclusions(ClockGroups *clk_groups); @@ -1258,17 +1269,18 @@ protected: void clearClkGroupExclusions(); char *makeClockGroupsName(); void setClockSense(const Pin *pin, - const Clock *clk, - ClockSense sense); + const Clock *clk, + ClockSense sense); bool clkStopSense(const Pin *to_pin, - const Clock *clk, - const RiseFall *from_rf, - const RiseFall *to_rf) const; + const Clock *clk, + const RiseFall *from_rf, + const RiseFall *to_rf) const; void disconnectPinBefore(const Pin *pin, - ExceptionPathSet *exceptions); + ExceptionPathSet *exceptions); void clockGroupsDeleteClkRefs(Clock *clk); void clearGroupPathMap(); + Mode *mode_; AnalysisType analysis_type_; OperatingConditions *operating_conditions_[MinMax::index_count]; InstancePvtMap instance_pvt_maps_[MinMax::index_count]; @@ -1294,6 +1306,7 @@ protected: bool clk_hpin_disables_valid_; PinSet propagated_clk_pins_; ClockLatencies clk_latencies_; + EdgeClockLatencyMap edge_clk_latency_map_; ClockInsertions clk_insertions_; PinClockUncertaintyMap pin_clk_uncertainty_map_; InterClockUncertaintySet inter_clk_uncertainties_; @@ -1338,13 +1351,10 @@ protected: // External parasitics on top level ports. // set_load port // set_fanout_load port - // Indexed by corner_index. - std::vector port_ext_cap_maps_; + PortExtCapMap port_ext_cap_map_; // set_load net - // Indexed by corner_index. - std::vector net_wire_cap_maps_; - // Indexed by corner_index. - std::vector drvr_pin_wire_cap_maps_; + NetWireCapMap net_wire_cap_map_; + PinWireCapMap drvr_pin_wire_cap_map_; NetResistanceMap net_res_map_; PinSet disabled_pins_; PortSet disabled_ports_; @@ -1387,6 +1397,12 @@ protected: bool path_delays_without_to_; // Group path exception names. GroupPathMap group_path_map_; + + // Filter exception to tag arrivals for + // report_timing -from pin|inst -through. + // -to is always nullptr. + FilterPath *filter_; + InputDriveMap input_drive_map_; // set_LogicValue::one/zero/dc LogicValueMap logic_value_map_; @@ -1404,10 +1420,6 @@ protected: WireloadMode wireload_mode_; WireloadSelection *wireload_selection_[MinMax::index_count]; - // Annotations on graph objects that are stored in constraints - // rather on the graph itself. - EdgeClockLatencyMap edge_clk_latency_; - private: friend class WriteSdc; friend class FindNetCaps; diff --git a/include/sta/SdcClass.hh b/include/sta/SdcClass.hh index cb5e6712..adf15947 100644 --- a/include/sta/SdcClass.hh +++ b/include/sta/SdcClass.hh @@ -24,9 +24,10 @@ #pragma once -#include "Map.hh" -#include "Set.hh" -#include "Vector.hh" +#include +#include +#include + #include "LibertyClass.hh" #include "NetworkClass.hh" #include "MinMaxValues.hh" @@ -67,11 +68,11 @@ class PortDelay; enum class AnalysisType { single, bc_wc, ocv }; enum class ExceptionPathType { false_path, loop, multi_cycle, path_delay, - group_path, filter, any}; + group_path, filter, any}; enum class ClockSense { positive, negative, stop }; -typedef std::pair ClockPair; +using ClockPair = std::pair; class ClockIndexLess { @@ -80,25 +81,25 @@ public: const Clock *clk2) const; }; -typedef Vector FloatSeq; -typedef Vector IntSeq; -typedef Vector ClockSeq; -typedef std::vector ConstClockSeq; -typedef Set ClockSet; -typedef std::set ConstClockSet; -typedef ClockSet ClockGroup; -typedef Vector PinSetSeq; -typedef MinMax SetupHold; -typedef MinMaxAll SetupHoldAll; -typedef Vector ExceptionThruSeq; -typedef Set LibertyPortPairSet; -typedef Map DisabledInstancePortsMap; -typedef Map DisabledCellPortsMap; -typedef MinMaxValues ClockUncertainties; -typedef std::set ExceptionPathSet; -typedef PinPair EdgePins; -typedef PinPairSet EdgePinsSet; -typedef Map LogicValueMap; +using FloatSeq = std::vector; +using IntSeq = std::vector; +using ClockSeq = std::vector; +using ConstClockSeq = std::vector; +using ClockSet = std::set; +using ConstClockSet = std::set; +using ClockGroup = ClockSet; +using PinSetSeq = std::vector; +using SetupHold = MinMax; +using SetupHoldAll = MinMaxAll; +using ExceptionThruSeq = std::vector; +using LibertyPortPairSet = std::set; +using DisabledInstancePortsMap = std::map; +using DisabledCellPortsMap = std::map; +using ClockUncertainties = MinMaxValues; +using ExceptionPathSet = std::set; +using EdgePins = PinPair; +using EdgePinsSet = PinPairSet; +using LogicValueMap = std::map; class ClockSetLess { @@ -107,7 +108,7 @@ public: const ClockSet *set2) const; }; -typedef Set ClockGroupSet; +using ClockGroupSet = std::set; // For Search. class ExceptionState; @@ -120,7 +121,7 @@ public: }; class ExceptionPath; -typedef Set ExceptionStateSet; +using ExceptionStateSet = std::set; // Constraint applies to clock or data paths. enum class PathClkOrData { clk, data }; diff --git a/include/sta/SdcNetwork.hh b/include/sta/SdcNetwork.hh index a3473759..c20627f3 100644 --- a/include/sta/SdcNetwork.hh +++ b/include/sta/SdcNetwork.hh @@ -248,28 +248,28 @@ public: protected: void parsePath(const char *path, - // Return values. - Instance *&inst, - const char *&path_tail) const; + // Return values. + Instance *&inst, + const char *&path_tail) const; void scanPath(const char *path, - // Return values. - // Unescaped divider count. - int ÷r_count, - int &path_length) const; + // Return values. + // Unescaped divider count. + int ÷r_count, + int &path_length) const; void parsePath(const char *path, - int divider_count, - int path_length, - // Return values. - Instance *&inst, - const char *&path_tail) const; + int divider_count, + int path_length, + // Return values. + Instance *&inst, + const char *&path_tail) const; bool visitMatches(const Instance *parent, - const PatternMatch *pattern, - std::function - visit_tail) const; + const PatternMatch *pattern, + std::function + visit_tail) const; bool visitPinTail(const Instance *instance, - const PatternMatch *tail, - PinSeq &matches) const; + const PatternMatch *tail, + PinSeq &matches) const; void findInstancesMatching1(const Instance *context, const PatternMatch *pattern, InstanceSeq &matches) const; diff --git a/include/sta/Search.hh b/include/sta/Search.hh index b23ef5c4..9889be75 100644 --- a/include/sta/Search.hh +++ b/include/sta/Search.hh @@ -26,9 +26,9 @@ #include #include +#include #include "MinMax.hh" -#include "UnorderedSet.hh" #include "Transition.hh" #include "LibertyClass.hh" #include "NetworkClass.hh" @@ -47,6 +47,7 @@ class BfsFwdIterator; class BfsBkwdIterator; class SearchPred; class SearchThru; +class SearchAdj; class ClkInfoLess; class PathEndVisitor; class ArrivalVisitor; @@ -55,52 +56,49 @@ class ClkPathIterator; class EvalPred; class TagGroup; class TagGroupBldr; -class PathGroups; class WorstSlacks; -class DcalcAnalysisPt; class VisitPathEnds; class GatedClk; class CheckCrpr; -class Genclks; -class Corner; +class Scene; -typedef Set ClkInfoSet; -typedef UnorderedSet TagSet; -typedef UnorderedSet TagGroupSet; -typedef Map VertexSlackMap; -typedef Vector VertexSlackMapSeq; -typedef Vector WorstSlacksSeq; -typedef std::vector DelayDblSeq; -typedef Vector ExceptionPathSeq; -typedef std::vector PathGroupSeq; +using ClkInfoSet = std::set; +using TagSet = std::unordered_set; +using TagGroupSet = std::unordered_set; +using VertexSlackMap = std::map; +using VertexSlackMapSeq = std::vector; +using WorstSlacksSeq = std::vector; +using DelayDblSeq = std::vector; +using ExceptionPathSeq = std::vector; +using StdStringSeq = std::vector; class Search : public StaState { public: - explicit Search(StaState *sta); + Search(StaState *sta); virtual ~Search(); virtual void copyState(const StaState *sta); // Reset to virgin state. void clear(); // When enabled, non-critical path arrivals are pruned to improve // run time and reduce memory. - bool crprPathPruningEnabled() const; + [[nodiscard]] bool crprPathPruningEnabled() const; void setCrprpathPruningEnabled(bool enabled); // When path pruning is enabled required times for non-critical paths // that have been pruned require additional search. This option // disables additional search to returns approximate required times. - bool crprApproxMissingRequireds() const; + [[nodiscard]] bool crprApproxMissingRequireds() const; void setCrprApproxMissingRequireds(bool enabled); - bool unconstrainedPaths() const { return unconstrained_paths_; } + [[nodiscard]] bool unconstrainedPaths() const { return unconstrained_paths_; } // from/thrus/to are owned and deleted by Search. - // Use corner nullptr to report timing for all corners. - // PathEnds are owned by Search PathGroups and deleted on next call. + // Use scene nullptr to report timing for all scenes. + // PathEnds are owned by Mode PathGroups and deleted on next call. PathEndSeq findPathEnds(ExceptionFrom *from, ExceptionThruSeq *thrus, ExceptionTo *to, bool unconstrained, - const Corner *corner, + const SceneSeq &scenes, const MinMaxAll *min_max, size_t group_path_count, size_t endpoint_path_count, @@ -109,14 +107,14 @@ public: float slack_min, float slack_max, bool sort_by_slack, - PathGroupNameSet *group_names, + StdStringSeq &group_names, bool setup, bool hold, bool recovery, bool removal, bool clk_gating_setup, bool clk_gating_hold); - bool arrivalsValid(); + [[nodiscard]] bool arrivalsValid(); // Invalidate all arrival and required times. void arrivalsInvalid(); // Invalidate vertex arrival time. @@ -140,83 +138,60 @@ public: void findRequireds(); // Find required times down thru level. void findRequireds(Level level); - bool requiredsSeeded() const { return requireds_seeded_; } - bool requiredsExist() const { return requireds_exist_; } + [[nodiscard]] bool requiredsSeeded() const { return requireds_seeded_; } + [[nodiscard]] bool requiredsExist() const { return requireds_exist_; } // The sum of all negative endpoints slacks. // Incrementally updated. Slack totalNegativeSlack(const MinMax *min_max); - Slack totalNegativeSlack(const Corner *corner, - const MinMax *min_max); + Slack totalNegativeSlack(const Scene *scene, + const MinMax *min_max); // Worst endpoint slack and vertex. // Incrementally updated. void worstSlack(const MinMax *min_max, - // Return values. - Slack &worst_slack, - Vertex *&worst_vertex); - void worstSlack(const Corner *corner, - const MinMax *min_max, - // Return values. - Slack &worst_slack, - Vertex *&worst_vertex); + // Return values. + Slack &worst_slack, + Vertex *&worst_vertex); + void worstSlack(const Scene *scene, + const MinMax *min_max, + // Return values. + Slack &worst_slack, + Vertex *&worst_vertex); // Clock arrival respecting ideal clock insertion delay and latency. Arrival clkPathArrival(const Path *clk_path) const; Arrival clkPathArrival(const Path *clk_path, - const ClkInfo *clk_info, - const ClockEdge *clk_edge, - const MinMax *min_max, - const PathAnalysisPt *path_ap) const; + const ClkInfo *clk_info, + const ClockEdge *clk_edge, + const MinMax *min_max) const; // Clock arrival at the path source/launch point. Arrival pathClkPathArrival(const Path *path) const; - PathGroupSeq pathGroups(const PathEnd *path_end) const; void deletePathGroups(); - void makePathGroups(int group_path_count, - int endpoint_path_count, - bool unique_pins, - bool unique_edges, - float min_slack, - float max_slack, - PathGroupNameSet *group_names, - bool setup, - bool hold, - bool recovery, - bool removal, - bool clk_gating_setup, - bool clk_gating_hold); - virtual ExceptionPath *exceptionTo(ExceptionPathType type, - const Path *path, - const Pin *pin, - const RiseFall *rf, - const ClockEdge *clk_edge, - const MinMax *min_max, - bool match_min_max_exactly, - bool require_to_pin) const; + ExceptionPath *exceptionTo(ExceptionPathType type, + const Path *path, + const Pin *pin, + const RiseFall *rf, + const ClockEdge *clk_edge, + const MinMax *min_max, + bool match_min_max_exactly, + bool require_to_pin, + Sdc *sdc) const; ExceptionPathSeq groupPathsTo(const PathEnd *path_end) const; - FilterPath *filter() const { return filter_; } void deleteFilter(); void deleteFilteredArrivals(); - VertexSet *endpoints(); + VertexSet &endpoints(); void endpointsInvalid(); - // Clock tree vertices between the clock source pin and register clk pins. - // This does NOT include generated clock source paths. - bool isClock(const Vertex *vertex) const; - // Vertices on propagated generated clock source paths. - bool isGenClkSrc(const Vertex *vertex) const; // The set of clocks that arrive at vertex in the clock network. - ClockSet clocks(const Vertex *vertex) const; - ClockSet clocks(const Pin *pin) const; + ClockSet clocks(const Pin *pin, + const Mode *mode) const; + ClockSet clocks(const Vertex *vertex, + const Mode *mode) const; // Clock domains for a vertex. - ClockSet clockDomains(const Vertex *vertex) const; - ClockSet clockDomains(const Pin *pin) const; - void visitStartpoints(VertexVisitor *visitor); - void visitEndpoints(VertexVisitor *visitor); - bool havePathGroups() const; - PathGroup *findPathGroup(const char *name, - const MinMax *min_max) const; - PathGroup *findPathGroup(const Clock *clk, - const MinMax *min_max) const; + ClockSet clockDomains(const Vertex *vertex, + const Mode *mode) const; + ClockSet clockDomains(const Pin *pin, + const Mode *mode) const; //////////////////////////////////////////////////////////////// // @@ -226,39 +201,43 @@ public: // Find arrivals for the clock tree. void findClkArrivals(); - void seedArrival(Vertex *vertex); EvalPred *evalPred() const { return eval_pred_; } - SearchPred *searchAdj() const { return search_adj_; } + SearchPred *searchAdj() const { return search_thru_; } Tag *tag(TagIndex index) const; TagIndex tagCount() const; TagGroupIndex tagGroupCount() const; void reportTagGroups() const; void reportPathCountHistogram() const; - virtual int clkInfoCount() const; - virtual bool isEndpoint(Vertex *vertex) const; - virtual bool isEndpoint(Vertex *vertex, - SearchPred *pred) const; + int clkInfoCount() const; + // Endpoint for any mode. + [[nodiscard]] bool isEndpoint(Vertex *vertex) const; + // Endpoint for one mode. + [[nodiscard]] bool isEndpoint(Vertex *vertex, + const Mode *mode) const; + [[nodiscard]] bool isEndpoint(Vertex *vertex, + const ModeSeq &modes) const; + [[nodiscard]] bool isEndpoint(Vertex *vertex, + SearchPred *pred, + const Mode *mode) const; void endpointInvalid(Vertex *vertex); Tag *fromUnclkedInputTag(const Pin *pin, - const RiseFall *rf, - const MinMax *min_max, - const PathAnalysisPt *path_ap, - bool is_segment_start, - bool require_exception); + const RiseFall *rf, + const MinMax *min_max, + bool is_segment_start, + bool require_exception, + Scene *scene); Tag *fromRegClkTag(const Pin *from_pin, - const RiseFall *from_rf, - const Clock *clk, - const RiseFall *clk_rf, - const ClkInfo *clk_info, - const Pin *to_pin, - const RiseFall *to_rf, - const MinMax *min_max, - const PathAnalysisPt *path_ap); + const RiseFall *from_rf, + const Clock *clk, + const RiseFall *clk_rf, + const ClkInfo *clk_info, + const Pin *to_pin, + const RiseFall *to_rf, + const MinMax *min_max, + Scene *scene); Tag *thruTag(Tag *from_tag, Edge *edge, const RiseFall *to_rf, - const MinMax *min_max, - const PathAnalysisPt *path_ap, TagSet *tag_cache); Tag *thruClkTag(Path *from_path, Vertex *from_vertex, @@ -268,69 +247,73 @@ public: const RiseFall *to_rf, bool arc_delay_min_max_eq, const MinMax *min_max, - const PathAnalysisPt *path_ap); + Scene *scene); const ClkInfo *thruClkInfo(Path *from_path, - Vertex *from_vertex, - const ClkInfo *from_clk_info, - bool from_is_clk, - Edge *edge, - Vertex *to_vertex, - const Pin *to_pin, - bool to_is_clk, - bool arc_delay_min_max_eq, - const MinMax *min_max, - const PathAnalysisPt *path_ap); + Vertex *from_vertex, + const ClkInfo *from_clk_info, + bool from_is_clk, + Edge *edge, + Vertex *to_vertex, + const Pin *to_pin, + bool to_is_clk, + bool arc_delay_min_max_eq, + const MinMax *min_max, + Scene *scene); const ClkInfo *clkInfoWithCrprClkPath(const ClkInfo *from_clk_info, - Path *from_path, - const PathAnalysisPt *path_ap); + Path *from_path); void seedClkArrivals(const Pin *pin, - Vertex *vertex, - TagGroupBldr *tag_bldr); + const Mode *mode, + TagGroupBldr *tag_bldr); void setVertexArrivals(Vertex *vertex, - TagGroupBldr *group_bldr); + TagGroupBldr *group_bldr); void tnsInvalid(Vertex *vertex); - bool arrivalsChanged(Vertex *vertex, - TagGroupBldr *tag_bldr); + [[nodiscard]] bool arrivalsChanged(Vertex *vertex, + TagGroupBldr *tag_bldr); BfsFwdIterator *arrivalIterator() const { return arrival_iter_; } BfsBkwdIterator *requiredIterator() const { return required_iter_; } - bool arrivalsAtEndpointsExist()const{return arrivals_at_endpoints_exist_;} // Used by OpenROAD. bool makeUnclkedPaths(Vertex *vertex, - bool is_segment_start, + bool is_segment_start, bool require_exception, - TagGroupBldr *tag_bldr); + TagGroupBldr *tag_bldr, + const Mode *mode); bool makeUnclkedPaths2(Vertex *vertex, TagGroupBldr *tag_bldr); - bool isSegmentStart(const Pin *pin); - bool isInputArrivalSrchStart(Vertex *vertex); + [[nodiscard]] bool isInputArrivalSrchStart(Vertex *vertex); void seedInputSegmentArrival(const Pin *pin, - Vertex *vertex, - TagGroupBldr *tag_bldr); + Vertex *vertex, + const Mode *mode, + TagGroupBldr *tag_bldr); void enqueueLatchDataOutputs(Vertex *vertex); void enqueueLatchOutput(Vertex *vertex); - virtual void seedRequired(Vertex *vertex); - virtual void seedRequiredEnqueueFanin(Vertex *vertex); + void enqueuePendingClkFanouts(); + void postponeClkFanouts(Vertex *vertex); + void seedRequired(Vertex *vertex); + void seedRequiredEnqueueFanin(Vertex *vertex); void seedInputDelayArrival(const Pin *pin, - Vertex *vertex, - InputDelay *input_delay); + Vertex *vertex, + InputDelay *input_delay, + const Mode *mode); void seedInputDelayArrival(const Pin *pin, - Vertex *vertex, - InputDelay *input_delay, - bool is_segment_start, - TagGroupBldr *tag_bldr); + Vertex *vertex, + InputDelay *input_delay, + bool is_segment_start, + const Mode *mode, + TagGroupBldr *tag_bldr); // Insertion delay for regular or generated clock. Arrival clockInsertion(const Clock *clk, - const Pin *pin, - const RiseFall *rf, - const MinMax *min_max, - const EarlyLate *early_late, - const PathAnalysisPt *path_ap) const; - bool propagateClkSense(const Pin *from_pin, - Path *from_path, - const RiseFall *to_rf); + const Pin *pin, + const RiseFall *rf, + const MinMax *min_max, + const EarlyLate *early_late, + const Mode *mode) const; + [[nodiscard]] bool propagateClkSense(const Pin *from_pin, + Path *from_path, + const RiseFall *to_rf); - Tag *findTag(const RiseFall *rf, - const PathAnalysisPt *path_ap, + Tag *findTag(Scene *scene, + const RiseFall *rf, + const MinMax *min_max, const ClkInfo *tag_clk, bool is_clk, InputDelay *input_delay, @@ -340,47 +323,51 @@ public: TagSet *tag_cache); void reportTags() const; void reportClkInfos() const; - const ClkInfo *findClkInfo(const ClockEdge *clk_edge, - const Pin *clk_src, - bool is_propagated, - const Pin *gen_clk_src, - bool gen_clk_src_path, - const RiseFall *pulse_clk_sense, - Arrival insertion, - float latency, - ClockUncertainties *uncertainties, - const PathAnalysisPt *path_ap, - Path *crpr_clk_path); - const ClkInfo *findClkInfo(const ClockEdge *clk_edge, - const Pin *clk_src, - bool is_propagated, - Arrival insertion, - const PathAnalysisPt *path_ap); + const ClkInfo *findClkInfo(Scene *scene, + const ClockEdge *clk_edge, + const Pin *clk_src, + bool is_propagated, + const Pin *gen_clk_src, + bool gen_clk_src_path, + const RiseFall *pulse_clk_sense, + Arrival insertion, + float latency, + const ClockUncertainties *uncertainties, + const MinMax *min_max, + Path *crpr_clk_path); + const ClkInfo *findClkInfo(Scene *scene, + const ClockEdge *clk_edge, + const Pin *clk_src, + bool is_propagated, + Arrival insertion, + const MinMax *min_max); // Timing derated arc delay for a path analysis point. ArcDelay deratedDelay(const Vertex *from_vertex, - const TimingArc *arc, - const Edge *edge, - bool is_clk, - const PathAnalysisPt *path_ap); + const TimingArc *arc, + const Edge *edge, + bool is_clk, + const MinMax *min_max, + DcalcAPIndex dcalc_ap, + const Sdc *sdc); TagGroup *tagGroup(const Vertex *vertex) const; TagGroup *tagGroup(TagGroupIndex index) const; void reportArrivals(Vertex *vertex, - bool report_tag_index) const; + bool report_tag_index) const; Slack wnsSlack(Vertex *vertex, - PathAPIndex path_ap_index); + PathAPIndex path_ap_index); void levelsChangedBefore(); void levelChangedBefore(Vertex *vertex); void seedInputArrival(const Pin *pin, - Vertex *vertex, - TagGroupBldr *tag_bldr); + Vertex *vertex, + const Mode *mode, + TagGroupBldr *tag_bldr); void ensureDownstreamClkPins(); - bool matchesFilter(Path *path, - const ClockEdge *to_clk_edge); + [[nodiscard]] bool matchesFilter(Path *path, + const ClockEdge *to_clk_edge); CheckCrpr *checkCrpr() { return check_crpr_; } VisitPathEnds *visitPathEnds() { return visit_path_ends_; } GatedClk *gatedClk() { return gated_clk_; } - Genclks *genclks() { return genclks_; } void findClkVertexPins(PinSet &clk_pins); void findFilteredArrivals(ExceptionFrom *from, ExceptionThruSeq *thrus, @@ -391,10 +378,10 @@ public: Arrival *arrivals(const Vertex *vertex) const; Arrival *makeArrivals(const Vertex *vertex, - uint32_t count); + uint32_t count); void deleteArrivals(const Vertex *vertex); Required *requireds(const Vertex *vertex) const; - bool hasRequireds(const Vertex *vertex) const; + [[nodiscard]] bool hasRequireds(const Vertex *vertex) const; Required *makeRequireds(const Vertex *vertex, uint32_t count); void deleteRequireds(const Vertex *vertex); @@ -404,11 +391,11 @@ public: Path *makePrevPaths(const Vertex *vertex, uint32_t count); void deletePrevPaths(Vertex *vertex); - bool crprPathPruningDisabled(const Vertex *vertex) const; + [[nodiscard]] bool crprPathPruningDisabled(const Vertex *vertex) const; void setCrprPathPruningDisabled(const Vertex *vertex, bool disabled); - bool bfsInQueue(const Vertex *vertex, - BfsIndex index) const; + [[nodiscard]] bool bfsInQueue(const Vertex *vertex, + BfsIndex index) const; void setBfsInQueue(const Vertex *vertex, BfsIndex index, bool value); @@ -420,16 +407,11 @@ public: void deleteTagGroup(TagGroup *group); bool postponeLatchOutputs() const { return postpone_latch_outputs_; } void saveEnumPath(Path *path); + bool isSrchRoot(Vertex *vertex, + const Mode *mode) const; protected: - void init(StaState *sta); void initVars(); - void makeAnalysisPts(AnalysisType analysis_type); - void makeAnalysisPts(bool swap_clk_min_max, - bool report_min, - bool report_max, - DcalcAnalysisPt *dcalc_ap_min, - DcalcAnalysisPt *dcalc_ap_max); void deleteTags(); void deleteTagsPrev(); void deleteUnusedTagGroups(); @@ -437,90 +419,90 @@ protected: void seedArrivals(); void findClockVertices(VertexSet &vertices); void seedClkDataArrival(const Pin *pin, - const RiseFall *rf, - const Clock *clk, - const ClockEdge *clk_edge, - const MinMax *min_max, - const PathAnalysisPt *path_ap, - Arrival insertion, - TagGroupBldr *tag_bldr); + const RiseFall *rf, + const Clock *clk, + const ClockEdge *clk_edge, + const MinMax *min_max, + Arrival insertion, + Scene *scene, + TagGroupBldr *tag_bldr); void seedClkArrival(const Pin *pin, - const RiseFall *rf, - const Clock *clk, - const ClockEdge *clk_edge, - const MinMax *min_max, - const PathAnalysisPt *path_ap, - Arrival insertion, - TagGroupBldr *tag_bldr); + const RiseFall *rf, + const Clock *clk, + const ClockEdge *clk_edge, + const MinMax *min_max, + Arrival insertion, + Scene *scene, + TagGroupBldr *tag_bldr); Tag *clkDataTag(const Pin *pin, - const Clock *clk, - const RiseFall *rf, - const ClockEdge *clk_edge, - Arrival insertion, - const MinMax *min_max, - const PathAnalysisPt *path_ap); + const Clock *clk, + const RiseFall *rf, + const ClockEdge *clk_edge, + Arrival insertion, + const MinMax *min_max, + Scene *scene); void findInputArrivalVertices(VertexSet &vertices); - void seedInputArrivals(ClockSet *clks); void findRootVertices(VertexSet &vertices); void findInputDrvrVertices(VertexSet &vertices); void seedInputArrival1(const Pin *pin, - Vertex *vertex, - bool is_segment_start, - TagGroupBldr *tag_bldr); + Vertex *vertex, + bool is_segment_start, + const Mode *mode, + TagGroupBldr *tag_bldr); void seedInputArrival(const Pin *pin, - Vertex *vertex, - ClockSet *wrt_clks); + Vertex *vertex, + ClockSet *wrt_clks); void seedInputDelayArrival(const Pin *pin, - InputDelay *input_delay, - const ClockEdge *clk_edge, - float clk_arrival, - float clk_insertion, - float clk_latency, - bool is_segment_start, - const MinMax *min_max, - PathAnalysisPt *path_ap, - TagGroupBldr *tag_bldr); + InputDelay *input_delay, + const ClockEdge *clk_edge, + float clk_arrival, + float clk_insertion, + float clk_latency, + bool is_segment_start, + const MinMax *min_max, + Scene *scene, + TagGroupBldr *tag_bldr); void seedInputDelayArrival(const Pin *pin, - const RiseFall *rf, - float arrival, - InputDelay *input_delay, - const ClockEdge *clk_edge, - float clk_insertion, - float clk_latency, - bool is_segment_start, - const MinMax *min_max, - PathAnalysisPt *path_ap, - TagGroupBldr *tag_bldr); + const RiseFall *rf, + float arrival, + InputDelay *input_delay, + const ClockEdge *clk_edge, + float clk_insertion, + float clk_latency, + bool is_segment_start, + const MinMax *min_max, + Scene *scene, + TagGroupBldr *tag_bldr); void inputDelayClkArrival(InputDelay *input_delay, - const ClockEdge *clk_edge, - const MinMax *min_max, - const PathAnalysisPt *path_ap, - // Return values. - float &clk_arrival, - float &clk_insertion, - float &clk_latency); + const ClockEdge *clk_edge, + const MinMax *min_max, + const Mode *mode, + // Return values. + float &clk_arrival, + float &clk_insertion, + float &clk_latency); void inputDelayRefPinArrival(Path *ref_path, - const ClockEdge *clk_edge, - const MinMax *min_max, - // Return values. - float &ref_arrival, - float &ref_insertion, - float &ref_latency); + const ClockEdge *clk_edge, + const MinMax *min_max, + const Sdc *sdc, + // Return values. + float &ref_arrival, + float &ref_insertion, + float &ref_latency); Tag *inputDelayTag(const Pin *pin, - const RiseFall *rf, - const ClockEdge *clk_edge, - float clk_insertion, - float clk_latency, - InputDelay *input_delay, - bool is_segment_start, - const MinMax *min_max, - const PathAnalysisPt *path_ap); + const RiseFall *rf, + const ClockEdge *clk_edge, + float clk_insertion, + float clk_latency, + InputDelay *input_delay, + bool is_segment_start, + const MinMax *min_max, + Scene *scene); void seedClkVertexArrivals(); - void seedClkVertexArrivals(const Pin *pin, - Vertex *vertex); void findClkArrivals1(); - void findAllArrivals(bool thru_latches); + void findAllArrivals(bool thru_latches, + bool clks_only); void findArrivals1(Level level); Tag *mutateTag(Tag *from_tag, const Pin *from_pin, @@ -534,28 +516,28 @@ protected: bool to_is_segment_start, const ClkInfo *to_clk_info, InputDelay *to_input_delay, - const MinMax *min_max, - const PathAnalysisPt *path_ap, TagSet *tag_cache); ExceptionPath *exceptionTo(const Path *path, - const Pin *pin, - const RiseFall *rf, - const ClockEdge *clk_edge, - const MinMax *min_max) const; + const Pin *pin, + const RiseFall *rf, + const ClockEdge *clk_edge, + const MinMax *min_max) const; void seedRequireds(); void seedInvalidRequireds(); - bool havePendingLatchOutputs(); + [[nodiscard]] bool havePendingLatchOutputs(); void clearPendingLatchOutputs(); void enqueuePendingLatchOutputs(); void findFilteredArrivals(bool thru_latches); void findArrivalsSeed(); void seedFilterStarts(); - bool hasEnabledChecks(Vertex *vertex) const; - virtual float timingDerate(const Vertex *from_vertex, - const TimingArc *arc, - const Edge *edge, - bool is_clk, - const PathAnalysisPt *path_ap); + [[nodiscard]] bool hasEnabledChecks(Vertex *vertex, + const Mode *mode) const; + float timingDerate(const Vertex *from_vertex, + const TimingArc *arc, + const Edge *edge, + bool is_clk, + const Sdc *sdc, + const MinMax *min_max); void deletePaths(); // Delete with incremental tns/wns update. void deletePathsIncr(Vertex *vertex); @@ -569,29 +551,31 @@ protected: void updateInvalidTns(); void clearWorstSlack(); void wnsSlacks(Vertex *vertex, - // Return values. - SlackSeq &slacks); + // Return values. + SlackSeq &slacks); void wnsTnsPreamble(); void worstSlackPreamble(); void deleteWorstSlacks(); void updateWorstSlacks(Vertex *vertex, - Slack slacks); + Slack slacks); void updateTns(Vertex *vertex, - SlackSeq &slacks); + SlackSeq &slacks); void tnsIncr(Vertex *vertex, - Slack slack, - PathAPIndex path_ap_index); + Slack slack, + PathAPIndex path_ap_index); void tnsDecr(Vertex *vertex, - PathAPIndex path_ap_index); + PathAPIndex path_ap_index); void tnsNotifyBefore(Vertex *vertex); - bool matchesFilterTo(Path *path, - const ClockEdge *to_clk_edge) const; + [[nodiscard]] bool matchesFilterTo(Path *path, + const ClockEdge *to_clk_edge) const; const Path *pathClkPathArrival1(const Path *path) const; void deletePathsState(const Vertex *vertex) const; void clocks(const Vertex *vertex, + const Mode *mode, // Return value. ClockSet &clks) const; void clockDomains(const Vertex *vertex, + const Mode *mode, // Return value. ClockSet &clks) const; @@ -601,84 +585,90 @@ protected: bool unconstrained_paths_; bool crpr_path_pruning_enabled_; bool crpr_approx_missing_requireds_; + // Search predicates. - SearchPred *search_adj_; - SearchPred *search_clk_; + SearchPred *search_thru_; + SearchAdj *search_adj_; EvalPred *eval_pred_; - ArrivalVisitor *arrival_visitor_; - // Clock arrivals are known. - bool clk_arrivals_valid_; + // Some arrivals exist. bool arrivals_exist_; - // Arrivals at end points exist (but may be invalid). - bool arrivals_at_endpoints_exist_; // Arrivals at start points have been initialized. bool arrivals_seeded_; + // Vertices with invalid arrival times to update and search from. + VertexSet invalid_arrivals_; + std::mutex invalid_arrivals_lock_; + BfsFwdIterator *arrival_iter_; + ArrivalVisitor *arrival_visitor_; + // Some requireds exist. bool requireds_exist_; // Requireds have been seeded by searching arrivals to all endpoints. bool requireds_seeded_; - // Vertices with invalid arrival times to update and search from. - VertexSet *invalid_arrivals_; - std::mutex invalid_arrivals_lock_; - BfsFwdIterator *arrival_iter_; // Vertices with invalid required times to update and search from. - VertexSet *invalid_requireds_; + VertexSet invalid_requireds_; BfsBkwdIterator *required_iter_; + bool tns_exists_; // Endpoint vertices with slacks that have changed since tns was found. - VertexSet *invalid_tns_; + VertexSet invalid_tns_; // Indexed by path_ap->index(). DelayDblSeq tns_; // Indexed by path_ap->index(). VertexSlackMapSeq tns_slacks_; std::mutex tns_lock_; + // Indexed by path_ap->index(). WorstSlacks *worst_slacks_; + // Use pointer to clk_info set so Tag.hh does not need to be included. ClkInfoSet *clk_info_set_; std::mutex clk_info_lock_; - // Use pointer to tag set so Tag.hh does not need to be included. - TagSet *tag_set_; + // Entries in tags_ may be missing where previous filter tags were deleted. TagIndex tag_capacity_; std::atomic tags_; + // Use pointer to tag set so Tag.hh does not need to be included. + TagSet *tag_set_; std::vector tags_prev_; TagIndex tag_next_; - // Holes in tags_ left by deleting filter tags. - std::vector tag_free_indices_; std::mutex tag_lock_; - TagGroupSet *tag_group_set_; + + // Capacity of tag_groups_. + TagGroupIndex tag_group_capacity_; std::atomic tag_groups_; + TagGroupSet *tag_group_set_; std::vector tag_groups_prev_; TagGroupIndex tag_group_next_; // Holes in tag_groups_ left by deleting filter tag groups. std::vector tag_group_free_indices_; - // Capacity of tag_groups_. - TagGroupIndex tag_group_capacity_; std::mutex tag_group_lock_; + // Latches data outputs to queue on the next search pass. - VertexSet *pending_latch_outputs_; + VertexSet pending_latch_outputs_; std::mutex pending_latch_outputs_lock_; - VertexSet *endpoints_; - VertexSet *invalid_endpoints_; - // Filter exception to tag arrivals for - // report_timing -from pin|inst -through. - // -to is always nullptr. - FilterPath *filter_; - // filter_from_ is owned by filter_ if it exists. + // Clock network endpoints where arrival search was suppended by findClkArrivals(). + VertexSet pending_clk_endpoints_; + std::mutex pending_clk_endpoints_lock_; + + VertexSet endpoints_; + bool endpoints_initialized_; + VertexSet invalid_endpoints_; + + bool have_filter_; ExceptionFrom *filter_from_; + ExceptionThruSeq *filter_thrus_; ExceptionTo *filter_to_; - VertexSet *filtered_arrivals_; + VertexSet filtered_arrivals_; std::mutex filtered_arrivals_lock_; + bool found_downstream_clk_pins_; bool postpone_latch_outputs_; - PathGroups *path_groups_; - VisitPathEnds *visit_path_ends_; std::vector enum_paths_; + + VisitPathEnds *visit_path_ends_; GatedClk *gated_clk_; CheckCrpr *check_crpr_; - Genclks *genclks_; }; // Eval across latch D->Q edges. @@ -690,22 +680,21 @@ protected: class EvalPred : public SearchPred0 { public: - explicit EvalPred(const StaState *sta); - virtual bool searchThru(Edge *edge); + EvalPred(const StaState *sta); + bool searchThru(Edge *edge, + const Mode *mode) const override; void setSearchThruLatches(bool thru_latches); - virtual bool searchTo(const Vertex *to_vertex); + bool searchTo(const Vertex *to_vertex, + const Mode *mode) const override; + + using SearchPred::searchFrom; + using SearchPred::searchThru; + using SearchPred::searchTo; protected: bool search_thru_latches_; }; -class ClkArrivalSearchPred : public EvalPred -{ -public: - ClkArrivalSearchPred(const StaState *sta); - virtual bool searchThru(Edge *edge); -}; - // Class for visiting fanin/fanout paths of a vertex. // This used by forward/backward search to find arrival/required path times. class PathVisitor : public VertexVisitor, public StaState @@ -714,56 +703,58 @@ public: // Uses search->evalPred() for search predicate. PathVisitor(const StaState *sta); PathVisitor(SearchPred *pred, - bool make_tag_cache, - const StaState *sta); + bool make_tag_cache, + const StaState *sta); virtual ~PathVisitor(); virtual void visitFaninPaths(Vertex *to_vertex); virtual void visitFanoutPaths(Vertex *from_vertex); protected: // Return false to stop visiting. - virtual bool visitEdge(const Pin *from_pin, Vertex *from_vertex, - Edge *edge, const Pin *to_pin, Vertex *to_vertex); + virtual bool visitEdge(const Pin *from_pin, + Vertex *from_vertex, + Edge *edge, + const Pin *to_pin, + Vertex *to_vertex); // Return false to stop visiting. - bool visitArc(const Pin *from_pin, - Vertex *from_vertex, - const RiseFall *from_rf, - Path *from_path, - Edge *edge, - TimingArc *arc, - const Pin *to_pin, - Vertex *to_vertex, - const MinMax *min_max, - PathAnalysisPt *path_ap); + [[nodiscard]] bool visitArc(const Pin *from_pin, + Vertex *from_vertex, + const RiseFall *from_rf, + Path *from_path, + Edge *edge, + TimingArc *arc, + const Pin *to_pin, + Vertex *to_vertex, + const MinMax *min_max, + const Mode *mode); // This calls visit below with everything required to make to_path. // Return false to stop visiting. virtual bool visitFromPath(const Pin *from_pin, - Vertex *from_vertex, - const RiseFall *from_rf, - Path *from_path, - Edge *edge, - TimingArc *arc, - const Pin *to_pin, - Vertex *to_vertex, - const RiseFall *to_rf, - const MinMax *min_max, - const PathAnalysisPt *path_ap); + Vertex *from_vertex, + const RiseFall *from_rf, + Path *from_path, + Edge *edge, + TimingArc *arc, + const Pin *to_pin, + Vertex *to_vertex, + const RiseFall *to_rf, + const MinMax *min_max); // Return false to stop visiting. virtual bool visitFromToPath(const Pin *from_pin, - Vertex *from_vertex, - const RiseFall *from_rf, - Tag *from_tag, - Path *from_path, + Vertex *from_vertex, + const RiseFall *from_rf, + Tag *from_tag, + Path *from_path, const Arrival &from_arrival, - Edge *edge, - TimingArc *arc, - ArcDelay arc_delay, - Vertex *to_vertex, - const RiseFall *to_rf, - Tag *to_tag, - Arrival &to_arrival, - const MinMax *min_max, - const PathAnalysisPt *path_ap) = 0; + Edge *edge, + TimingArc *arc, + ArcDelay arc_delay, + Vertex *to_vertex, + const RiseFall *to_rf, + Tag *to_tag, + Arrival &to_arrival, + const MinMax *min_max) = 0; + SearchPred *pred_; TagSet *tag_cache_; }; @@ -776,45 +767,44 @@ public: ArrivalVisitor(const StaState *sta); virtual ~ArrivalVisitor(); // Initialize the visitor. - // Defaults pred to search->eval_pred_. - void init(bool always_to_endpoints); void init(bool always_to_endpoints, - SearchPred *pred); + bool clks_only, + SearchPred *pred); + void copyState(const StaState *sta); virtual void visit(Vertex *vertex); virtual VertexVisitor *copy() const; // Return false to stop visiting. virtual bool visitFromToPath(const Pin *from_pin, - Vertex *from_vertex, - const RiseFall *from_rf, - Tag *from_tag, - Path *from_path, + Vertex *from_vertex, + const RiseFall *from_rf, + Tag *from_tag, + Path *from_path, const Arrival &from_arrival, Edge *edge, - TimingArc *arc, - ArcDelay arc_delay, - Vertex *to_vertex, - const RiseFall *to_rf, - Tag *to_tag, - Arrival &to_arrival, - const MinMax *min_max, - const PathAnalysisPt *path_ap); + TimingArc *arc, + ArcDelay arc_delay, + Vertex *to_vertex, + const RiseFall *to_rf, + Tag *to_tag, + Arrival &to_arrival, + const MinMax *min_max); void setAlwaysToEndpoints(bool to_endpoints); TagGroupBldr *tagBldr() const { return tag_bldr_; } protected: ArrivalVisitor(bool always_to_endpoints, - SearchPred *pred, - const StaState *sta); + SearchPred *pred, + const StaState *sta); void init0(); - void enqueueRefPinInputDelays(const Pin *ref_pin); - void seedInputDelayArrival(const Pin *pin, - Vertex *vertex, - InputDelay *input_delay); + void enqueueRefPinInputDelays(const Pin *ref_pin, + const Sdc *sdc); + void seedArrivals(Vertex *vertex); void pruneCrprArrivals(); void constrainedRequiredsInvalid(Vertex *vertex, - bool is_clk); + bool is_clk); bool always_to_endpoints_; bool always_save_prev_paths_; + bool clks_only_; TagGroupBldr *tag_bldr_; TagGroupBldr *tag_bldr_no_crpr_; SearchPred *adj_pred_; @@ -827,14 +817,14 @@ class RequiredCmp public: RequiredCmp(); void requiredsInit(Vertex *vertex, - const StaState *sta); + const StaState *sta); void requiredSet(size_t path_index, - Required &required, - const MinMax *min_max, - const StaState *sta); + Required &required, + const MinMax *min_max, + const StaState *sta); // Return true if the requireds changed. bool requiredsSave(Vertex *vertex, - const StaState *sta); + const StaState *sta); Required required(size_t path_index); protected: @@ -854,46 +844,25 @@ public: protected: RequiredVisitor(bool make_tag_cache, - const StaState *sta); + const StaState *sta); // Return false to stop visiting. virtual bool visitFromToPath(const Pin *from_pin, - Vertex *from_vertex, - const RiseFall *from_rf, - Tag *from_tag, - Path *from_path, + Vertex *from_vertex, + const RiseFall *from_rf, + Tag *from_tag, + Path *from_path, const Arrival &from_arrival, - Edge *edge, - TimingArc *arc, - ArcDelay arc_delay, - Vertex *to_vertex, - const RiseFall *to_rf, - Tag *to_tag, - Arrival &to_arrival, - const MinMax *min_max, - const PathAnalysisPt *path_ap); + Edge *edge, + TimingArc *arc, + ArcDelay arc_delay, + Vertex *to_vertex, + const RiseFall *to_rf, + Tag *to_tag, + Arrival &to_arrival, + const MinMax *min_max); RequiredCmp *required_cmp_; VisitPathEnds *visit_path_ends_; }; -// This does not use SearchPred as a base class to avoid getting -// two sets of StaState variables when multiple inheritance is used -// to add the functions in this class to another. -class DynLoopSrchPred -{ -public: - DynLoopSrchPred(TagGroupBldr *tag_bldr); - -protected: - bool loopEnabled(Edge *edge, - bool dynamic_loop_breaking_enabled, - const Graph *graph, - Search *search); - bool hasPendingLoopPaths(Edge *edge, - const Graph *graph, - Search *search); - - TagGroupBldr *tag_bldr_; -}; - } // namespace diff --git a/include/sta/SearchClass.hh b/include/sta/SearchClass.hh index d9268b94..65683966 100644 --- a/include/sta/SearchClass.hh +++ b/include/sta/SearchClass.hh @@ -25,11 +25,10 @@ #pragma once #include +#include +#include -#include "Vector.hh" -#include "Set.hh" -#include "Map.hh" -#include "UnorderedMap.hh" +#include "VectorMap.hh" #include "StringSet.hh" #include "MinMaxValues.hh" #include "Delay.hh" @@ -39,7 +38,7 @@ namespace sta { class Search; -class Corner; +class Scene; class Path; class PathEnd; class PathGroup; @@ -56,8 +55,6 @@ class ClkInfo; class ClkInfoHash; class ClkInfoEqual; class VertexPathIterator; -class PathAnalysisPt; -class PathAnalysisPtIterator; class MinPulseWidthCheck; class MinPeriodCheck; class MaxSkewCheck; @@ -70,10 +67,10 @@ class ClkDelays; class TagMatchLess { public: - explicit TagMatchLess(bool match_crpr_clk_pin, - const StaState *sta); + TagMatchLess(bool match_crpr_clk_pin, + const StaState *sta); bool operator()(const Tag *tag1, - const Tag *tag2) const; + const Tag *tag2) const; protected: bool match_crpr_clk_pin_; @@ -84,7 +81,7 @@ class TagMatchHash { public: TagMatchHash(bool match_crpr_clk_pin, - const StaState *sta); + const StaState *sta); size_t operator()(const Tag *tag) const; protected: @@ -96,46 +93,42 @@ class TagMatchEqual { public: TagMatchEqual(bool match_crpr_clk_pin, - const StaState *sta); + const StaState *sta); bool operator()(const Tag *tag1, - const Tag *tag2) const; + const Tag *tag2) const; protected: bool match_crpr_clk_pin_; const StaState *sta_; }; -typedef int PathAPIndex; -typedef uint32_t TagIndex; -typedef Vector TagSeq; -typedef Vector MinPulseWidthCheckSeq; -typedef Vector MinPeriodCheckSeq; -typedef Vector MaxSkewCheckSeq; -typedef StringSet PathGroupNameSet; -typedef Vector PathEndSeq; -typedef Vector ArrivalSeq; -typedef Map VertexPathCountMap; -typedef Map PathIndexMap; -typedef Vector SlackSeq; -typedef Delay Crpr; -typedef Vector PathSeq; -typedef std::vector ConstPathSeq; +using PathAPIndex = int; +using TagIndex = uint32_t; +using TagSeq = std::vector; +using PathEndSeq = std::vector; +using ArrivalSeq = std::vector; +using VertexPathCountMap = std::map; +using PathIndexMap = VectorMap; +using SlackSeq = std::vector; +using Crpr = Delay; +using PathSeq = std::vector; +using ConstPathSeq = std::vector; enum class ReportPathFormat { full, - full_clock, - full_clock_expanded, - shorter, - endpoint, - summary, - slack_only, - json + full_clock, + full_clock_expanded, + shorter, + endpoint, + summary, + slack_only, + json }; static const TagIndex tag_index_bit_count = 28; static const TagIndex tag_index_max = (1 << tag_index_bit_count) - 1; static const TagIndex tag_index_null = tag_index_max; static const int path_ap_index_bit_count = 8; -// One path analysis point per corner min/max. -static const int corner_count_max = (1 << path_ap_index_bit_count) / 2; +// One path analysis point per scene min/max. +static const int scene_count_max = (1 << path_ap_index_bit_count) / 2; } // namespace diff --git a/include/sta/SearchPred.hh b/include/sta/SearchPred.hh index 618dd2ea..c1e4c21a 100644 --- a/include/sta/SearchPred.hh +++ b/include/sta/SearchPred.hh @@ -33,40 +33,49 @@ namespace sta { // Class hierarchy: // SearchPred +// SearchAdj (unless loop disabled, latch D->Q, timing check, dynamic loop) // SearchPred0 (unless disabled or constant) // EvalPred (unless timing check) -// SearchThru (unless latch D->Q, outside vertex subset) +// SearchThru (unless latch D->Q) // SearchPred1 (unless loop disabled) -// ClkTreeSearchPred (only wire or combinational) -// SearchPred2 (unless timing check) -// SearchPredNonLatch2 (unless latch D->Q) -// SearchPredNonReg2 (unless reg CLK->Q, latch D->Q) +// ClkTreeSearchPred (only wire or combinational) // Virtual base class for search predicates. class SearchPred { public: - SearchPred() {} + SearchPred(const StaState *sta); virtual ~SearchPred() {} // Search is allowed from from_vertex. - virtual bool searchFrom(const Vertex *from_vertex) = 0; + virtual bool searchFrom(const Vertex *from_vertex, + const Mode *mode) const = 0; + bool searchFrom(const Vertex *from_vertex) const; // Search is allowed through edge. // from/to pins are NOT checked. // inst can be either the from_pin or to_pin instance because it // is only referenced when they are the same (non-wire edge). - virtual bool searchThru(Edge *edge) = 0; + virtual bool searchThru(Edge *edge, + const Mode *mode) const = 0; + bool searchThru(Edge *edge) const; // Search is allowed to to_pin. - virtual bool searchTo(const Vertex *to_vertex) = 0; + virtual bool searchTo(const Vertex *to_vertex, + const Mode *mode) const = 0; + bool searchTo(const Vertex *to_vertex) const; + void copyState(const StaState *sta); + +protected: + const StaState *sta_; }; class SearchPred0 : public SearchPred { public: - explicit SearchPred0(const StaState *sta); + SearchPred0(const StaState *sta); // Search from a vertex unless // disabled by constraint // constant logic zero/one - virtual bool searchFrom(const Vertex *from_vertex); + bool searchFrom(const Vertex *from_vertex, + const Mode *mode) const override; // Search thru an edge unless // traverses disabled from/to pin pair // disabled by condition expression @@ -75,13 +84,12 @@ public: // cond expression is disabled // non-controlling constant values on other pins that disable the // edge (such as a mux select) - virtual bool searchThru(Edge *edge); + bool searchThru(Edge *edge, + const Mode *mode) const override; // Search to a vertex unless // constant logic zero/one - virtual bool searchTo(const Vertex *to_vertex); - -protected: - const StaState *sta_; + bool searchTo(const Vertex *to_vertex, + const Mode *mode) const override; }; // SearchPred0 unless @@ -89,75 +97,63 @@ protected: class SearchPred1 : public SearchPred0 { public: - explicit SearchPred1(const StaState *sta); - virtual bool searchThru(Edge *edge); -}; + SearchPred1(const StaState *sta); + bool searchThru(Edge *edge, + const Mode *mode) const override; -// SearchPred1 unless -// timing check edge -class SearchPred2 : public SearchPred1 -{ -public: - explicit SearchPred2(const StaState *sta); - virtual bool searchThru(Edge *edge); -}; - -// SearchPred2 unless -// latch D->Q edge -class SearchPredNonLatch2 : public SearchPred2 -{ -public: - explicit SearchPredNonLatch2(const StaState *sta); - virtual bool searchThru(Edge *edge); -}; - -// SearchPred2 unless -// register/latch CLK->Q edges. -class SearchPredNonReg2 : public SearchPred2 -{ -public: - explicit SearchPredNonReg2(const StaState *sta); - virtual bool searchThru(Edge *edge); + using SearchPred::searchFrom; + using SearchPred::searchThru; + using SearchPred::searchTo; }; // Predicate for BFS search to stop at the end of the clock tree. // Search only thru combinational gates and wires. -class ClkTreeSearchPred : public SearchPred1 +class ClkTreeSearchPred : public SearchPred { public: - explicit ClkTreeSearchPred(const StaState *sta); - virtual bool searchThru(Edge *edge); + ClkTreeSearchPred(const StaState *sta); + bool searchFrom(const Vertex *from_vertex, + const Mode *mode) const override; + bool searchThru(Edge *edge, + const Mode *mode) const override; + // The variable part of searchThru used by descendents. + virtual bool searchThruAllow(const TimingRole *role) const; + bool searchTo(const Vertex *to_vertex, + const Mode *mode) const override; }; bool -isClkEnd(Vertex *vertex, Graph *graph); +isClkEnd(Vertex *vertex, + const Mode *mode); // Predicate to see if arc/edge is disabled by constants on other pins // that effect the unateness of the edge. bool searchThru(const Edge *edge, - const TimingArc *arc, - const Graph *graph); + const TimingArc *arc, + const Mode *mode); bool searchThru(Vertex *from_vertex, - const RiseFall *from_rf, - const Edge *edge, - Vertex *to_vertex, - const RiseFall *to_rf); - + const RiseFall *from_rf, + const Edge *edge, + Vertex *to_vertex, + const RiseFall *to_rf, + const Mode *mode); //////////////////////////////////////////////////////////////// bool hasFanin(Vertex *vertex, - SearchPred *pred, - const Graph *graph); + SearchPred *pred, + const Graph *graph, + const Mode *mode); // Vertices with no fanout have at no enabled (non-disabled) edges // leaving them. bool hasFanout(Vertex *vertex, - SearchPred *pred, - const Graph *graph); + SearchPred *pred, + const Graph *graph, + const Mode *mode); } // namespace diff --git a/include/sta/Sequential.hh b/include/sta/Sequential.hh index cba09523..1923c270 100644 --- a/include/sta/Sequential.hh +++ b/include/sta/Sequential.hh @@ -55,8 +55,8 @@ enum class StateInternalValue { class StatetableRow; -typedef std::vector StateInputValues; -typedef std::vector StateInternalValues; +using StateInputValues = std::vector; +using StateInternalValues = std::vector; // Register/Latch class Sequential @@ -81,14 +81,14 @@ protected: // clocked_on/next_state for registers // enable/data for latches Sequential(bool is_register, - FuncExpr *clock, - FuncExpr *data, - FuncExpr *clear, - FuncExpr *preset, - LogicValue clr_preset_out, - LogicValue clr_preset_out_inv, - LibertyPort *output, - LibertyPort *output_inv); + FuncExpr *clock, + FuncExpr *data, + FuncExpr *clear, + FuncExpr *preset, + LogicValue clr_preset_out, + LogicValue clr_preset_out_inv, + LibertyPort *output, + LibertyPort *output_inv); bool is_register_; FuncExpr *clock_; diff --git a/include/sta/Set.hh b/include/sta/Set.hh deleted file mode 100644 index 7e08c3b1..00000000 --- a/include/sta/Set.hh +++ /dev/null @@ -1,220 +0,0 @@ -// OpenSTA, Static Timing Analyzer -// Copyright (c) 2025, Parallax Software, Inc. -// -// This program is free software: you can redistribute it and/or modify -// it under the terms of the GNU General Public License as published by -// the Free Software Foundation, either version 3 of the License, or -// (at your option) any later version. -// -// This program is distributed in the hope that it will be useful, -// but WITHOUT ANY WARRANTY; without even the implied warranty of -// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -// GNU General Public License for more details. -// -// You should have received a copy of the GNU General Public License -// along with this program. If not, see . -// -// The origin of this software must not be misrepresented; you must not -// claim that you wrote the original software. -// -// Altered source versions must be plainly marked as such, and must not be -// misrepresented as being the original software. -// -// This notice may not be removed or altered from any source distribution. - -#pragma once - -#include - -namespace sta { - -// Add convenience functions around STL container. -template > -class Set : public std::set -{ -public: - Set() : std::set() {} - explicit Set(const CMP &cmp) : std::set(cmp) {} - - // Find the entry corresponding to key. - KEY findKey(const KEY key) const - { - auto find_iter = this->find(key); - if (find_iter != this->end()) - return *find_iter; - else - return nullptr; - } - // Find out if key is in the set. - bool hasKey(const KEY key) const - { - auto find_iter = this->find(key); - return find_iter != this->end(); - } - - // Slowaris STL doesn't support operator== on sets. - static bool equal(const std::set *set1, - const std::set *set2); - - // True if set2 is a subset of this set. - bool isSubset(const std::set *set2); - - void insertSet(const std::set *set2); - - void - deleteContents() - { - Iterator iter(this); - while (iter.hasNext()) - delete iter.next(); - } - - void - deleteContentsClear() - { - deleteContents(); - this->clear(); - } - - static bool - intersects(const std::set *set1, - const std::set *set2, - CMP key_less); - - // Java style container itererator - // Set::Iterator iter(set); - // while (iter.hasNext()) { - // Key *v = iter.next(); - // } - class Iterator - { - public: - Iterator() : container_(nullptr) {} - explicit Iterator(std::set *container) : - container_(container) - { if (container_ != nullptr) iter_ = container_->begin(); } - explicit Iterator(std::set &container) : - container_(&container) - { if (container_ != nullptr) iter_ = container_->begin(); } - void init(std::set *container) - { container_ = container; if (container_ != nullptr) iter_=container_->begin();} - void init(std::set &container) - { container_ = &container; if (container_ != nullptr) iter_=container_->begin();} - bool hasNext() { return container_ != nullptr && iter_ != container_->end(); } - KEY next() { return *iter_++; } - std::set *container() { return container_; } - - private: - std::set *container_; - typename std::set::iterator iter_; - }; - - class ConstIterator - { - public: - ConstIterator() : container_(nullptr) {} - explicit ConstIterator(const std::set *container) : - container_(container) - { if (container_ != nullptr) iter_ = container_->begin(); } - explicit ConstIterator(const std::set &container) : - container_(&container) - { if (container_ != nullptr) iter_ = container_->begin(); } - void init(const std::set *container) - { container_ = container; if (container_ != nullptr) iter_=container_->begin();} - void init(const std::set &container) - { container_ = &container; if (container_ != nullptr) iter_=container_->begin();} - - bool hasNext() { return container_ != nullptr && iter_ != container_->end(); } - KEY next() { return *iter_++; } - const std::set *container() { return container_; } - - private: - const std::set *container_; - typename std::set::const_iterator iter_; - }; -}; - -template -bool -Set::equal(const std::set *set1, - const std::set *set2) -{ - if ((set1 == nullptr || set1->empty()) - && (set2 == nullptr || set2->empty())) - return true; - else if (set1 && set2) { - if (set1->size() == set2->size()) { - typename Set::ConstIterator iter1(set1); - typename Set::ConstIterator iter2(set2); - while (iter1.hasNext() && iter2.hasNext()) { - if (iter1.next() != iter2.next()) - return false; - } - return true; - } - else - return false; - } - else - return false; -} - -template -bool -Set::isSubset(const std::set *set2) -{ - if (this->empty() && set2->empty()) - return true; - else { - typename Set::ConstIterator iter2(set2); - while (iter2.hasNext()) { - const KEY key2 = iter2.next(); - if (!hasKey(key2)) - return false; - } - return true; - } -} - -template -bool -Set::intersects(const std::set *set1, - const std::set *set2, - CMP key_less) -{ - if (set1 && set2) { - auto iter1 = set1->begin(); - auto end1 = set1->end(); - auto iter2 = set2->begin(); - auto end2 = set2->end(); - while (iter1 != end1 && iter2 != end2) { - if (key_less(*iter1, *iter2)) - iter1++; - else if (key_less(*iter2, *iter1)) - iter2++; - else - return true; - } - } - return false; -} - -// A complicated way to call the base class operator<. -template -bool -operator<(const Set &set1, const Set &set2) -{ - const std::set &set1_base = set1; - const std::set &set2_base = set2; - return set1_base < set2_base; -} - -template -void -Set::insertSet(const std::set *set2) -{ - if (set2) - this->insert(set2->begin(), set2->end()); -} - -} // namespace diff --git a/include/sta/Sta.hh b/include/sta/Sta.hh index cdf67203..e0f30787 100644 --- a/include/sta/Sta.hh +++ b/include/sta/Sta.hh @@ -24,12 +24,16 @@ #pragma once +#include #include +#include +#include #include "StringSeq.hh" #include "LibertyClass.hh" #include "NetworkClass.hh" #include "SdcClass.hh" +#include "Scene.hh" #include "GraphClass.hh" #include "ParasiticsClass.hh" #include "StaState.hh" @@ -40,6 +44,7 @@ #include "CircuitSim.hh" #include "Variables.hh" #include "Property.hh" +#include "RiseFallMinMaxDelay.hh" struct Tcl_Interp; @@ -53,10 +58,9 @@ class RiseFall; class VerilogReader; class ReportPath; class CheckTiming; -class DcalcAnalysisPt; -class CheckSlewLimits; -class CheckFanoutLimits; -class CheckCapacitanceLimits; +class CheckSlews; +class CheckFanouts; +class CheckCapacitances; class CheckMinPulseWidths; class CheckMinPeriods; class CheckMaxSkews; @@ -64,18 +68,24 @@ class PatternMatch; class CheckPeriods; class LibertyReader; class SearchPred; -class Corner; +class Scene; class ClkSkews; class ReportField; class EquivCells; +class StaSimObserver; +class GraphLoop; -typedef InstanceSeq::Iterator SlowDrvrIterator; -typedef Vector CheckError; -typedef Vector CheckErrorSeq; -typedef Vector CornerSeq; -typedef std::vector StdStringSeq; - +using ModeNameMap = std::map; +using SceneNameMap = std::map; +using SlowDrvrIterator = Iterator; +using CheckError = StringSeq; +using CheckErrorSeq = std::vector; +using StdStringSeq = std::vector; enum class CmdNamespace { sta, sdc }; +using ParasiticsNameMap = std::map; +// Path::slack/arrival/required function. +using PathDelayFunc = std::function; +using GraphLoopSeq = std::vector; // Initialize sta functions that are not part of the Sta class. void initSta(); @@ -115,10 +125,34 @@ public: virtual int defaultThreadCount() const; void setThreadCount(int thread_count); + // define_corners compatibility. + void makeScenes(StringSeq *scene_names); + void makeScene(const std::string &name, + const std::string &mode_name, + const StdStringSeq &liberty_min_files, + const StdStringSeq &liberty_max_files, + const std::string &spef_min_file, + const std::string &spef_max_file); + Scene *findScene(const std::string &name) const; + // Pattern match name. + SceneSeq findScenes(const std::string &name) const; + SceneSeq findScenes(const std::string &name, + ModeSeq &modes) const; + Scene *cmdScene() const; + void setCmdScene(Scene *scene); + SceneSeq makeSceneSeq(Scene *scene) const; + + Mode *cmdMode() const { return cmd_scene_->mode(); } + const std::string &cmdModeName(); + void setCmdMode(const std::string &mode_name); + Mode *findMode(const std::string &mode_name) const; + ModeSeq findModes(const std::string &mode_name) const; + Sdc *cmdSdc() const; + virtual LibertyLibrary *readLiberty(const char *filename, - Corner *corner, - const MinMaxAll *min_max, - bool infer_latches); + Scene *scene, + const MinMaxAll *min_max, + bool infer_latches); bool readVerilog(const char *filename); // Network readers call this to notify the Sta to delete any previously // linked network. @@ -130,729 +164,818 @@ public: // SDC Swig API. Instance *currentInstance() const; void setCurrentInstance(Instance *inst); - virtual void setAnalysisType(AnalysisType analysis_type); + virtual void setAnalysisType(AnalysisType analysis_type, + Sdc *sdc); void setOperatingConditions(OperatingConditions *op_cond, - const MinMaxAll *min_max); + const MinMaxAll *min_max, + Sdc *sdc); void setTimingDerate(TimingDerateType type, - PathClkOrData clk_data, - const RiseFallBoth *rf, - const EarlyLate *early_late, - float derate); + PathClkOrData clk_data, + const RiseFallBoth *rf, + const EarlyLate *early_late, + float derate, + Sdc *sdc); // Delay type is always net for net derating. void setTimingDerate(const Net *net, - PathClkOrData clk_data, - const RiseFallBoth *rf, - const EarlyLate *early_late, - float derate); + PathClkOrData clk_data, + const RiseFallBoth *rf, + const EarlyLate *early_late, + float derate, + Sdc *sdc); void setTimingDerate(const Instance *inst, - TimingDerateCellType type, - PathClkOrData clk_data, - const RiseFallBoth *rf, - const EarlyLate *early_late, - float derate); + TimingDerateCellType type, + PathClkOrData clk_data, + const RiseFallBoth *rf, + const EarlyLate *early_late, + float derate, + Sdc *sdc); void setTimingDerate(const LibertyCell *cell, - TimingDerateCellType type, - PathClkOrData clk_data, - const RiseFallBoth *rf, - const EarlyLate *early_late, - float derate); - void unsetTimingDerate(); + TimingDerateCellType type, + PathClkOrData clk_data, + const RiseFallBoth *rf, + const EarlyLate *early_late, + float derate, + Sdc *sdc); + void unsetTimingDerate(Sdc *sdc); void setInputSlew(const Port *port, - const RiseFallBoth *rf, - const MinMaxAll *min_max, - float slew); + const RiseFallBoth *rf, + const MinMaxAll *min_max, + float slew, + Sdc *sdc); // Set port external pin load (set_load -pin port). void setPortExtPinCap(const Port *port, - const RiseFallBoth *rf, - const Corner *corner, - const MinMaxAll *min_max, - float cap); + const RiseFallBoth *rf, + const MinMaxAll *min_max, + float cap, + Sdc *sdc); void portExtCaps(const Port *port, - const Corner *corner, const MinMax *min_max, + const Sdc *sdc, float &pin_cap, float &wire_cap, int &fanout); // Set port external wire load (set_load -wire port). void setPortExtWireCap(const Port *port, - bool subtract_pin_cap, - const RiseFallBoth *rf, - const Corner *corner, - const MinMaxAll *min_max, - float cap); + const RiseFallBoth *rf, + const MinMaxAll *min_max, + float cap, + Sdc *sdc); // Set net wire capacitance (set_load -wire net). void setNetWireCap(const Net *net, - bool subtract_pin_load, - const Corner *corner, - const MinMaxAll *min_max, - float cap); + bool subtract_pin_load, + const MinMaxAll *min_max, + float cap, + Sdc *sdc); // Remove all "set_load net" annotations. - void removeNetLoadCaps() const; + void removeNetLoadCaps(Sdc *sdc) const; // Set port external fanout (used by wireload models). void setPortExtFanout(const Port *port, - int fanout, - const Corner *corner, - const MinMaxAll *min_max); + int fanout, + const MinMaxAll *min_max, + Sdc *sdc); // Liberty port capacitance. float capacitance(const LibertyPort *port, - Corner *corner, + Scene *scene, const MinMax *min_max); // pin_cap = net pin capacitances + port external pin capacitance, // wire_cap = annotated net capacitance + port external wire capacitance. void connectedCap(const Pin *drvr_pin, - const RiseFall *rf, - const Corner *corner, - const MinMax *min_max, - float &pin_cap, - float &wire_cap) const; + const RiseFall *rf, + const Scene *scene, + const MinMax *min_max, + float &pin_cap, + float &wire_cap) const; void connectedCap(const Net *net, - Corner *corner, - const MinMax *min_max, - float &pin_cap, - float &wire_cap) const; + Scene *scene, + const MinMax *min_max, + float &pin_cap, + float &wire_cap) const; void setResistance(const Net *net, - const MinMaxAll *min_max, - float res); + const MinMaxAll *min_max, + float res, + Sdc *sdc); void setDriveCell(const LibertyLibrary *library, - const LibertyCell *cell, - const Port *port, - const LibertyPort *from_port, - float *from_slews, - const LibertyPort *to_port, - const RiseFallBoth *rf, - const MinMaxAll *min_max); + const LibertyCell *cell, + const Port *port, + const LibertyPort *from_port, + float *from_slews, + const LibertyPort *to_port, + const RiseFallBoth *rf, + const MinMaxAll *min_max, + Sdc *sdc); void setDriveResistance(const Port *port, - const RiseFallBoth *rf, - const MinMaxAll *min_max, - float res); + const RiseFallBoth *rf, + const MinMaxAll *min_max, + float res, + Sdc *sdc); void setLatchBorrowLimit(const Pin *pin, - float limit); + float limit, + Sdc *sdc); void setLatchBorrowLimit(const Instance *inst, - float limit); + float limit, + Sdc *sdc); void setLatchBorrowLimit(const Clock *clk, - float limit); + float limit, + Sdc *sdc); void setMinPulseWidth(const RiseFallBoth *rf, - float min_width); + float min_width, + Sdc *sdc); void setMinPulseWidth(const Pin *pin, - const RiseFallBoth *rf, - float min_width); + const RiseFallBoth *rf, + float min_width, + Sdc *sdc); void setMinPulseWidth(const Instance *inst, - const RiseFallBoth *rf, - float min_width); + const RiseFallBoth *rf, + float min_width, + Sdc *sdc); void setMinPulseWidth(const Clock *clk, - const RiseFallBoth *rf, - float min_width); + const RiseFallBoth *rf, + float min_width, + Sdc *sdc); void setWireload(Wireload *wireload, - const MinMaxAll *min_max); - void setWireloadMode(WireloadMode mode); + const MinMaxAll *min_max, + Sdc *sdc); + void setWireloadMode(WireloadMode mode, + Sdc *sdc); void setWireloadSelection(WireloadSelection *selection, - const MinMaxAll *min_max); + const MinMaxAll *min_max, + Sdc *sdc); void setSlewLimit(Clock *clk, - const RiseFallBoth *rf, - const PathClkOrData clk_data, - const MinMax *min_max, - float slew); + const RiseFallBoth *rf, + const PathClkOrData clk_data, + const MinMax *min_max, + float slew, + Sdc *sdc); void setSlewLimit(Port *port, - const MinMax *min_max, - float slew); + const MinMax *min_max, + float slew, + Sdc *sdc); void setSlewLimit(Cell *cell, - const MinMax *min_max, - float slew); + const MinMax *min_max, + float slew, + Sdc *sdc); void setCapacitanceLimit(Cell *cell, - const MinMax *min_max, - float cap); + const MinMax *min_max, + float cap, + Sdc *sdc); void setCapacitanceLimit(Port *port, - const MinMax *min_max, - float cap); + const MinMax *min_max, + float cap, + Sdc *sdc); void setCapacitanceLimit(Pin *pin, - const MinMax *min_max, - float cap); + const MinMax *min_max, + float cap, + Sdc *sdc); void setFanoutLimit(Cell *cell, - const MinMax *min_max, - float fanout); + const MinMax *min_max, + float fanout, + Sdc *sdc); void setFanoutLimit(Port *port, - const MinMax *min_max, - float fanout); - void setMaxArea(float area); + const MinMax *min_max, + float fanout, + Sdc *sdc); + void setMaxArea(float area, + Sdc *sdc); void makeClock(const char *name, - PinSet *pins, - bool add_to_pins, - float period, - FloatSeq *waveform, - char *comment); + PinSet *pins, + bool add_to_pins, + float period, + FloatSeq *waveform, + char *comment, + const Mode *mode); // edges size must be 3. void makeGeneratedClock(const char *name, - PinSet *pins, - bool add_to_pins, - Pin *src_pin, - Clock *master_clk, - int divide_by, - int multiply_by, - float duty_cycle, - bool invert, - bool combinational, - IntSeq *edges, - FloatSeq *edge_shifts, - char *comment); - void removeClock(Clock *clk); + PinSet *pins, + bool add_to_pins, + Pin *src_pin, + Clock *master_clk, + int divide_by, + int multiply_by, + float duty_cycle, + bool invert, + bool combinational, + IntSeq *edges, + FloatSeq *edge_shifts, + char *comment, + const Mode *mode); + void removeClock(Clock *clk, + Sdc *sdc); // Update period/waveform for generated clocks from source pin clock. void updateGeneratedClks(); // True if pin is defined as a clock source (pin may be hierarchical). - bool isClockSrc(const Pin *pin) const; + bool isClockSrc(const Pin *pin, + const Sdc *sdc) const; // Propagated (non-ideal) clocks. - void setPropagatedClock(Clock *clk); - void removePropagatedClock(Clock *clk); - void setPropagatedClock(Pin *pin); - void removePropagatedClock(Pin *pin); + void setPropagatedClock(Clock *clk, + const Mode *mode); + void removePropagatedClock(Clock *clk, + const Mode *mode); + void setPropagatedClock(Pin *pin, + const Mode *mode); + void removePropagatedClock(Pin *pin, + const Mode *mode); void setClockSlew(Clock *clock, - const RiseFallBoth *rf, - const MinMaxAll *min_max, - float slew); - void removeClockSlew(Clock *clk); + const RiseFallBoth *rf, + const MinMaxAll *min_max, + float slew, + Sdc *sdc); + void removeClockSlew(Clock *clk, + Sdc *sdc); // Clock latency. // Latency can be on a clk, pin, or clk/pin combination. void setClockLatency(Clock *clk, - Pin *pin, - const RiseFallBoth *rf, - const MinMaxAll *min_max, - float delay); + Pin *pin, + const RiseFallBoth *rf, + const MinMaxAll *min_max, + float delay, + Sdc *sdc); void removeClockLatency(const Clock *clk, - const Pin *pin); + const Pin *pin, + Sdc *sdc); // Clock insertion delay (source latency). void setClockInsertion(const Clock *clk, - const Pin *pin, - const RiseFallBoth *rf, - const MinMaxAll *min_max, - const EarlyLateAll *early_late, - float delay); + const Pin *pin, + const RiseFallBoth *rf, + const MinMaxAll *min_max, + const EarlyLateAll *early_late, + float delay, + Sdc *sdc); void removeClockInsertion(const Clock *clk, - const Pin *pin); + const Pin *pin, + Sdc *sdc); // Clock uncertainty. - virtual void setClockUncertainty(Clock *clk, - const SetupHoldAll *setup_hold, - float uncertainty); - virtual void removeClockUncertainty(Clock *clk, - const SetupHoldAll *setup_hold); - virtual void setClockUncertainty(Pin *pin, - const SetupHoldAll *setup_hold, - float uncertainty); - virtual void removeClockUncertainty(Pin *pin, - const SetupHoldAll *setup_hold); + void setClockUncertainty(Clock *clk, + const SetupHoldAll *setup_hold, + float uncertainty); + void removeClockUncertainty(Clock *clk, + const SetupHoldAll *setup_hold); + void setClockUncertainty(Pin *pin, + const SetupHoldAll *setup_hold, + float uncertainty, + Sdc *sdc); + void removeClockUncertainty(Pin *pin, + const SetupHoldAll *setup_hold, + Sdc *sdc); // Inter-clock uncertainty. - virtual void setClockUncertainty(Clock *from_clk, - const RiseFallBoth *from_rf, - Clock *to_clk, - const RiseFallBoth *to_rf, - const SetupHoldAll *setup_hold, - float uncertainty); - virtual void removeClockUncertainty(Clock *from_clk, - const RiseFallBoth *from_rf, - Clock *to_clk, - const RiseFallBoth *to_rf, - const SetupHoldAll *setup_hold); + void setClockUncertainty(Clock *from_clk, + const RiseFallBoth *from_rf, + Clock *to_clk, + const RiseFallBoth *to_rf, + const SetupHoldAll *setup_hold, + float uncertainty, + Sdc *sdc); + void removeClockUncertainty(Clock *from_clk, + const RiseFallBoth *from_rf, + Clock *to_clk, + const RiseFallBoth *to_rf, + const SetupHoldAll *setup_hold, + Sdc *sdc); ClockGroups *makeClockGroups(const char *name, - bool logically_exclusive, - bool physically_exclusive, - bool asynchronous, - bool allow_paths, - const char *comment); + bool logically_exclusive, + bool physically_exclusive, + bool asynchronous, + bool allow_paths, + const char *comment, + Sdc *sdc); // nullptr name removes all. - void removeClockGroupsLogicallyExclusive(const char *name); - void removeClockGroupsPhysicallyExclusive(const char *name); - void removeClockGroupsAsynchronous(const char *name); + void removeClockGroupsLogicallyExclusive(const char *name, + Sdc *sdc); + void removeClockGroupsPhysicallyExclusive(const char *name, + Sdc *sdc); + void removeClockGroupsAsynchronous(const char *name, + Sdc *sdc); void makeClockGroup(ClockGroups *clk_groups, - ClockSet *clks); + ClockSet *clks, + Sdc *sdc); void setClockSense(PinSet *pins, - ClockSet *clks, - ClockSense sense); + ClockSet *clks, + ClockSense sense, + Sdc *sdc); void setClockGatingCheck(const RiseFallBoth *rf, - const SetupHold *setup_hold, - float margin); + const SetupHold *setup_hold, + float margin, + Sdc *sdc); void setClockGatingCheck(Clock *clk, - const RiseFallBoth *rf, - const SetupHold *setup_hold, - float margin); + const RiseFallBoth *rf, + const SetupHold *setup_hold, + float margin, + Sdc *sdc); void setClockGatingCheck(Instance *inst, - const RiseFallBoth *rf, - const SetupHold *setup_hold, - float margin, - LogicValue active_value); + const RiseFallBoth *rf, + const SetupHold *setup_hold, + float margin, + LogicValue active_value, + Sdc *sdc); void setClockGatingCheck(Pin *pin, - const RiseFallBoth *rf, - const SetupHold *setup_hold, - float margin, - LogicValue active_value); + const RiseFallBoth *rf, + const SetupHold *setup_hold, + float margin, + LogicValue active_value, + Sdc *sdc); void setDataCheck(Pin *from, - const RiseFallBoth *from_rf, - Pin *to, - const RiseFallBoth *to_rf, - Clock *clk, - const SetupHoldAll *setup_hold, - float margin); + const RiseFallBoth *from_rf, + Pin *to, + const RiseFallBoth *to_rf, + Clock *clk, + const SetupHoldAll *setup_hold, + float margin, + Sdc *sdc); void removeDataCheck(Pin *from, - const RiseFallBoth *from_rf, - Pin *to, - const RiseFallBoth *to_rf, - Clock *clk, - const SetupHoldAll *setup_hold); + const RiseFallBoth *from_rf, + Pin *to, + const RiseFallBoth *to_rf, + Clock *clk, + const SetupHoldAll *setup_hold, + Sdc *sdc); // set_disable_timing cell [-from] [-to] // Disable all edges thru cell if from/to are null. // Bus and bundle ports are NOT supported. void disable(LibertyCell *cell, - LibertyPort *from, - LibertyPort *to); + LibertyPort *from, + LibertyPort *to, + Sdc *sdc); void removeDisable(LibertyCell *cell, - LibertyPort *from, - LibertyPort *to); + LibertyPort *from, + LibertyPort *to, + Sdc *sdc); // set_disable_timing liberty port. // Bus and bundle ports are NOT supported. - void disable(LibertyPort *port); - void removeDisable(LibertyPort *port); + void disable(LibertyPort *port, + Sdc *sdc); + void removeDisable(LibertyPort *port, + Sdc *sdc); // set_disable_timing port (top level instance port). // Bus and bundle ports are NOT supported. - void disable(Port *port); - void removeDisable(Port *port); + void disable(Port *port, + Sdc *sdc); + void removeDisable(Port *port, + Sdc *sdc); // set_disable_timing instance [-from] [-to]. // Disable all edges thru instance if from/to are null. // Bus and bundle ports are NOT supported. // Hierarchical instances are NOT supported. void disable(Instance *inst, - LibertyPort *from, - LibertyPort *to); + LibertyPort *from, + LibertyPort *to, + Sdc *sdc); void removeDisable(Instance *inst, - LibertyPort *from, - LibertyPort *to); + LibertyPort *from, + LibertyPort *to, + Sdc *sdc); // set_disable_timing pin - void disable(Pin *pin); - void removeDisable(Pin *pin); + void disable(Pin *pin, + Sdc *sdc); + void removeDisable(Pin *pin, + Sdc *sdc); // set_disable_timing [get_timing_arc -of_objects instance]] - void disable(Edge *edge); - void removeDisable(Edge *edge); + void disable(Edge *edge, + Sdc *sdc); + void removeDisable(Edge *edge, + Sdc *sdc); // set_disable_timing [get_timing_arc -of_objects lib_cell]] - void disable(TimingArcSet *arc_set); - void removeDisable(TimingArcSet *arc_set); + void disable(TimingArcSet *arc_set, + Sdc *sdc); + void removeDisable(TimingArcSet *arc_set, + Sdc *sdc); // Edge is disabled by constant. - bool isDisabledConstant(Edge *edge); + [[nodiscard]] bool isDisabledConstant(Edge *edge, + const Mode *mode); // Return a set of constant pins that disabled edge. // Caller owns the returned set. - PinSet disabledConstantPins(Edge *edge); + PinSet disabledConstantPins(Edge *edge, + const Mode *mode); // Edge timing sense with propagated constants. - TimingSense simTimingSense(Edge *edge); + TimingSense simTimingSense(Edge *edge, + const Mode *mode); // Edge is disabled by set_disable_timing constraint. - bool isDisabledConstraint(Edge *edge); + [[nodiscard]] bool isDisabledConstraint(Edge *edge, + const Sdc *sdc); // Edge is disabled to break combinational loops. - bool isDisabledLoop(Edge *edge) const; + [[nodiscard]] bool isDisabledLoop(Edge *edge) const; // Edge is disabled internal bidirect output path. - bool isDisabledBidirectInstPath(Edge *edge) const; + [[nodiscard]] bool isDisabledBidirectInstPath(Edge *edge) const; // Edge is disabled bidirect net path. - bool isDisabledBidirectNetPath(Edge *edge) const; - bool isDisabledPresetClr(Edge *edge) const; + [[nodiscard]] bool isDisabledBidirectNetPath(Edge *edge) const; + [[nodiscard]] bool isDisabledPresetClr(Edge *edge) const; // Return a vector of graph edges that are disabled, sorted by // from/to vertex names. Caller owns the returned vector. - EdgeSeq disabledEdges(); - EdgeSeq disabledEdgesSorted(); - void disableClockGatingCheck(Instance *inst); - void disableClockGatingCheck(Pin *pin); - void removeDisableClockGatingCheck(Instance *inst); - void removeDisableClockGatingCheck(Pin *pin); + EdgeSeq disabledEdges(const Mode *mode); + EdgeSeq disabledEdgesSorted(const Mode *mode); + void disableClockGatingCheck(Instance *inst, + Sdc *sdc); + void disableClockGatingCheck(Pin *pin, + Sdc *sdc); + void removeDisableClockGatingCheck(Instance *inst, + Sdc *sdc); + void removeDisableClockGatingCheck(Pin *pin, + Sdc *sdc); void setLogicValue(Pin *pin, - LogicValue value); + LogicValue value, + Mode *mode); void setCaseAnalysis(Pin *pin, - LogicValue value); - void removeCaseAnalysis(Pin *pin); + LogicValue value, + Mode *mode); + void removeCaseAnalysis(Pin *pin, + Mode *mode); void setInputDelay(const Pin *pin, - const RiseFallBoth *rf, - const Clock *clk, - const RiseFall *clk_rf, - const Pin *ref_pin, - bool source_latency_included, - bool network_latency_included, - const MinMaxAll *min_max, - bool add, - float delay); + const RiseFallBoth *rf, + const Clock *clk, + const RiseFall *clk_rf, + const Pin *ref_pin, + bool source_latency_included, + bool network_latency_included, + const MinMaxAll *min_max, + bool add, + float delay, + Sdc *sdc); void removeInputDelay(const Pin *pin, - const RiseFallBoth *rf, - const Clock *clk, - const RiseFall *clk_rf, - const MinMaxAll *min_max); + const RiseFallBoth *rf, + const Clock *clk, + const RiseFall *clk_rf, + const MinMaxAll *min_max, + Sdc *sdc); void setOutputDelay(const Pin *pin, - const RiseFallBoth *rf, - const Clock *clk, - const RiseFall *clk_rf, - const Pin *ref_pin, - bool source_latency_included, - bool network_latency_included, - const MinMaxAll *min_max, - bool add, - float delay); + const RiseFallBoth *rf, + const Clock *clk, + const RiseFall *clk_rf, + const Pin *ref_pin, + bool source_latency_included, + bool network_latency_included, + const MinMaxAll *min_max, + bool add, + float delay, + Sdc *sdc); void removeOutputDelay(const Pin *pin, - const RiseFallBoth *rf, - const Clock *clk, - const RiseFall *clk_rf, - const MinMaxAll *min_max); + const RiseFallBoth *rf, + const Clock *clk, + const RiseFall *clk_rf, + const MinMaxAll *min_max, + Sdc *sdc); void makeFalsePath(ExceptionFrom *from, - ExceptionThruSeq *thrus, - ExceptionTo *to, - const MinMaxAll *min_max, - const char *comment); + ExceptionThruSeq *thrus, + ExceptionTo *to, + const MinMaxAll *min_max, + const char *comment, + Sdc *sdc); void makeMulticyclePath(ExceptionFrom *from, - ExceptionThruSeq *thrus, - ExceptionTo *to, - const MinMaxAll *min_max, - bool use_end_clk, - int path_multiplier, - const char *comment); + ExceptionThruSeq *thrus, + ExceptionTo *to, + const MinMaxAll *min_max, + bool use_end_clk, + int path_multiplier, + const char *comment, + Sdc *sdc); void makePathDelay(ExceptionFrom *from, - ExceptionThruSeq *thrus, - ExceptionTo *to, - const MinMax *min_max, - bool ignore_clk_latency, + ExceptionThruSeq *thrus, + ExceptionTo *to, + const MinMax *min_max, + bool ignore_clk_latency, bool break_path, - float delay, - const char *comment); + float delay, + const char *comment, + Sdc *sdc); void makeGroupPath(const char *name, - bool is_default, - ExceptionFrom *from, - ExceptionThruSeq *thrus, - ExceptionTo *to, - const char *comment); + bool is_default, + ExceptionFrom *from, + ExceptionThruSeq *thrus, + ExceptionTo *to, + const char *comment, + Sdc *sdc); // Deprecated 10/24/2025 - bool isGroupPathName(const char *group_name) __attribute__ ((deprecated)); - bool isPathGroupName(const char *group_name) const; - StdStringSeq pathGroupNames() const; + bool isGroupPathName(const char *group_name, + const Sdc *sdc) __attribute__ ((deprecated)); + bool isPathGroupName(const char *group_name, + const Sdc *sdc) const; + StdStringSeq pathGroupNames(const Sdc *sdc) const; void resetPath(ExceptionFrom *from, - ExceptionThruSeq *thrus, - ExceptionTo *to, - const MinMaxAll *min_max); + ExceptionThruSeq *thrus, + ExceptionTo *to, + const MinMaxAll *min_max, + Sdc *sdc); // Make an exception -from specification. ExceptionFrom *makeExceptionFrom(PinSet *from_pins, - ClockSet *from_clks, - InstanceSet *from_insts, - const RiseFallBoth *from_rf); + ClockSet *from_clks, + InstanceSet *from_insts, + const RiseFallBoth *from_rf, + const Sdc *sdc); void checkExceptionFromPins(ExceptionFrom *from, - const char *file, - int line) const; + const char *file, + int line, + const Sdc *sdc) const; void deleteExceptionFrom(ExceptionFrom *from); // Make an exception -through specification. ExceptionThru *makeExceptionThru(PinSet *pins, - NetSet *nets, - InstanceSet *insts, - const RiseFallBoth *rf); + NetSet *nets, + InstanceSet *insts, + const RiseFallBoth *rf, + const Sdc *sdc); void deleteExceptionThru(ExceptionThru *thru); // Make an exception -to specification. ExceptionTo *makeExceptionTo(PinSet *to_pins, - ClockSet *to_clks, - InstanceSet *to_insts, - const RiseFallBoth *rf, - const RiseFallBoth *end_rf); + ClockSet *to_clks, + InstanceSet *to_insts, + const RiseFallBoth *rf, + const RiseFallBoth *end_rf, + const Sdc *sdc); void checkExceptionToPins(ExceptionTo *to, - const char *file, int) const; + const char *file, + int line, + const Sdc *sdc) const; void deleteExceptionTo(ExceptionTo *to); + InstanceSet findRegisterInstances(ClockSet *clks, const RiseFallBoth *clk_rf, bool edge_triggered, - bool latches); + bool latches, + const Mode *mode); PinSet findRegisterDataPins(ClockSet *clks, const RiseFallBoth *clk_rf, bool registers, - bool latches); + bool latches, + const Mode *mode); PinSet findRegisterClkPins(ClockSet *clks, const RiseFallBoth *clk_rf, bool registers, - bool latches); + bool latches, + const Mode *mode); PinSet findRegisterAsyncPins(ClockSet *clks, const RiseFallBoth *clk_rf, bool registers, - bool latches); + bool latches, + const Mode *mode); PinSet findRegisterOutputPins(ClockSet *clks, const RiseFallBoth *clk_rf, bool registers, - bool latches); + bool latches, + const Mode *mode); PinSet findFaninPins(PinSeq *to, bool flat, bool startpoints_only, int inst_levels, int pin_levels, bool thru_disabled, - bool thru_constants); + bool thru_constants, + const Mode *mode); InstanceSet findFaninInstances(PinSeq *to, - bool flat, - bool startpoints_only, - int inst_levels, - int pin_levels, - bool thru_disabled, - bool thru_constants); + bool flat, + bool startpoints_only, + int inst_levels, + int pin_levels, + bool thru_disabled, + bool thru_constants, + const Mode *mode); PinSet findFanoutPins(PinSeq *from, - bool flat, - bool endpoints_only, - int inst_levels, - int pin_levels, - bool thru_disabled, - bool thru_constants); + bool flat, + bool endpoints_only, + int inst_levels, + int pin_levels, + bool thru_disabled, + bool thru_constants, + const Mode *mode); InstanceSet findFanoutInstances(PinSeq *from, - bool flat, - bool endpoints_only, - int inst_levels, - int pin_levels, - bool thru_disabled, - bool thru_constants); + bool flat, + bool endpoints_only, + int inst_levels, + int pin_levels, + bool thru_disabled, + bool thru_constants, + const Mode *mode); // The set of clocks that arrive at vertex in the clock network. - ClockSet clocks(const Pin *pin); + ClockSet clocks(const Pin *pin, + const Mode *mode); // Clock domains for a pin. - ClockSet clockDomains(const Pin *pin); + ClockSet clockDomains(const Pin *pin, + const Mode *mode); - void checkSlewLimitPreamble(); - // Return pins with the min/max slew limit slack. + //////////////////////////////////////////////////////////////// // net=null check all nets - // corner=nullptr checks all corners. - PinSeq checkSlewLimits(Net *net, - bool violators, - const Corner *corner, - const MinMax *min_max); - void reportSlewLimitShortHeader(); - void reportSlewLimitShort(Pin *pin, - const Corner *corner, - const MinMax *min_max); - void reportSlewLimitVerbose(Pin *pin, - const Corner *corner, - const MinMax *min_max); - // requires checkSlewLimitPreamble() + void reportSlewChecks(const Net *net, + size_t max_count, + bool violators, + bool verbose, + const SceneSeq &scenes, + const MinMax *min_max); + void checkSlewsPreamble(); + // requires checkSlewsPreamble() void checkSlew(const Pin *pin, - const Corner *corner, - const MinMax *min_max, - bool check_clks, - // Return values. - const Corner *&corner1, - const RiseFall *&tr, - Slew &slew, - float &limit, - float &slack); + const SceneSeq &scenes, + const MinMax *min_max, + bool check_clks, + // Return values. + Slew &slew, + float &limit, + float &slack, + const RiseFall *&rf, + const Scene *&Scene); void maxSlewCheck(// Return values. const Pin *&pin, Slew &slew, float &slack, float &limit); void findSlewLimit(const LibertyPort *port, - const Corner *corner, + const Scene *scene, const MinMax *min_max, // Return values. float &limit, bool &exists); + size_t maxSlewViolationCount(); - void checkFanoutLimitPreamble(); - // Return pins with the min/max fanout limit slack. - // net=null check all nets - // corner=nullptr checks all corners. - PinSeq checkFanoutLimits(Net *net, - bool violators, - const MinMax *min_max); - void reportFanoutLimitShortHeader(); - void reportFanoutLimitShort(Pin *pin, - const MinMax *min_max); - void reportFanoutLimitVerbose(Pin *pin, - const MinMax *min_max); - // requires checkFanoutLimitPreamble() + //////////////////////////////////////////////////////////////// + // net == nullptr to check all. + void reportFanoutChecks(const Net *net, + size_t max_count, + bool violators, + bool verbose, + const SceneSeq &scenes, + const MinMax *min_max); + void checkFanoutPreamble(); + // requires checkFanoutPreamble() void checkFanout(const Pin *pin, - const MinMax *min_max, - // Return values. - float &fanout, - float &limit, - float &slack); - void maxFanoutCheck(// Return values. - const Pin *&pin, - float &fanout, - float &slack, - float &limit); + const Mode *mode, + const MinMax *min_max, + // Return values. + float &fanout, + float &limit, + float &slack); + // Return the pin etc with max fanout check min slack. + void maxFanoutMinSlackPin(const ModeSeq &modes, + // Return values. + const Pin *&pin, + float &fanout, + float &limit, + float &slack, + const Mode *&mode); + size_t fanoutViolationCount(const MinMax *min_max, + const ModeSeq &modes); - void checkCapacitanceLimitPreamble(); - // Return pins with the min/max slew limit slack. + //////////////////////////////////////////////////////////////// // net=null check all nets - // corner=nullptr checks all corners. - PinSeq checkCapacitanceLimits(Net *net, - bool violators, - const Corner *corner, - const MinMax *min_max); - void reportCapacitanceLimitShortHeader(); - void reportCapacitanceLimitShort(Pin *pin, - const Corner *corner, - const MinMax *min_max); - void reportCapacitanceLimitVerbose(Pin *pin, - const Corner *corner, - const MinMax *min_max); + void reportCapacitanceChecks(const Net *net, + size_t max_count, + bool violators, + bool verbose, + const SceneSeq &scenes, + const MinMax *min_max); + size_t maxCapacitanceViolationCount(); + void checkCapacitancesPreamble(const SceneSeq &scenes); // requires checkCapacitanceLimitPreamble() void checkCapacitance(const Pin *pin, - const Corner *corner, - const MinMax *min_max, - // Return values. - const Corner *&corner1, - const RiseFall *&tr, - float &capacitance, - float &limit, - float &slack); + const SceneSeq &scenes, + const MinMax *min_max, + // Return values. + float &capacitance, + float &limit, + float &slack, + const RiseFall *&rf, + const Scene *&scene); void maxCapacitanceCheck(// Return values. const Pin *&pin, float &capacitance, float &slack, float &limit); - // Min pulse width check with the least slack. - // corner=nullptr checks all corners. - MinPulseWidthCheck *minPulseWidthSlack(const Corner *corner); - // All violating min pulse width checks. - // corner=nullptr checks all corners. - MinPulseWidthCheckSeq &minPulseWidthViolations(const Corner *corner); - // Min pulse width checks for pins. - // corner=nullptr checks all corners. - MinPulseWidthCheckSeq &minPulseWidthChecks(PinSeq *pins, - const Corner *corner); - // All min pulse width checks. - // corner=nullptr checks all corners. - MinPulseWidthCheckSeq &minPulseWidthChecks(const Corner *corner); - void reportMpwChecks(MinPulseWidthCheckSeq *checks, - bool verbose); - void reportMpwCheck(MinPulseWidthCheck *check, - bool verbose); + //////////////////////////////////////////////////////////////// + void reportMinPulseWidthChecks(const Net *net, + size_t max_count, + bool violators, + bool verbose, + const SceneSeq &scenes); - // Min period check with the least slack. - MinPeriodCheck *minPeriodSlack(); - // All violating min period checks. - MinPeriodCheckSeq &minPeriodViolations(); - void reportChecks(MinPeriodCheckSeq *checks, - bool verbose); - void reportCheck(MinPeriodCheck *check, - bool verbose); - - // Max skew check with the least slack. - MaxSkewCheck *maxSkewSlack(); - // All violating min period checks. - MaxSkewCheckSeq &maxSkewViolations(); - void reportChecks(MaxSkewCheckSeq *checks, - bool verbose); - void reportCheck(MaxSkewCheck *check, - bool verbose); + //////////////////////////////////////////////////////////////// + void reportMinPeriodChecks(const Net *net, + size_t max_count, + bool violators, + bool verbose, + const SceneSeq &scenes); + //////////////////////////////////////////////////////////////// + void reportMaxSkewChecks(const Net *net, + size_t max_count, + bool violators, + bool verbose, + const SceneSeq &scenes); //////////////////////////////////////////////////////////////// // User visible but non SDC commands. - // Instance specific process/voltage/temperature. - // Defaults to operating condition if instance is not annotated. - const Pvt *pvt(Instance *inst, - const MinMax *min_max); - void setPvt(Instance *inst, - const MinMaxAll *min_max, - float process, - float voltage, - float temperature); - // Pvt may be shared among multiple instances. - void setPvt(const Instance *inst, - const MinMaxAll *min_max, - const Pvt &pvt); - void setVoltage(const MinMax *min_max, - float voltage); - void setVoltage(const Net *net, - const MinMax *min_max, - float voltage); // Clear all state except network. virtual void clear(); - // Remove all constraints. - virtual void removeConstraints(); - // Notify the sta that the constraints have changed directly rather - // than thru this sta API. - virtual void constraintsChanged(); // Namespace used by command interpreter. CmdNamespace cmdNamespace(); void setCmdNamespace(CmdNamespace namespc); - OperatingConditions *operatingConditions(const MinMax *min_max) const; + OperatingConditions *operatingConditions(const MinMax *min_max, + const Sdc *sdc) const; // Set the delay on a timing arc. // Required/arrival times are incrementally updated. void setArcDelay(Edge *edge, - TimingArc *arc, - const Corner *corner, - const MinMaxAll *min_max, - ArcDelay delay); + TimingArc *arc, + const Scene *scene, + const MinMaxAll *min_max, + ArcDelay delay); // Set annotated slew on a vertex for delay calculation. void setAnnotatedSlew(Vertex *vertex, - const Corner *corner, - const MinMaxAll *min_max, - const RiseFallBoth *rf, - float slew); + const Scene *scene, + const MinMaxAll *min_max, + const RiseFallBoth *rf, + float slew); void writeSdf(const char *filename, - const Corner *corner, - char divider, + const Scene *scene, + char divider, bool include_typ, - int digits, - bool gzip, - bool no_timestamp, - bool no_version); + int digits, + bool gzip, + bool no_timestamp, + bool no_version); // Remove all delay and slew annotations. void removeDelaySlewAnnotations(); + // Instance specific process/voltage/temperature. + // Defaults to operating condition if instance is not annotated. + const Pvt *pvt(Instance *inst, + const MinMax *min_max, + Sdc *sdc); + void setPvt(Instance *inst, + const MinMaxAll *min_max, + float process, + float voltage, + float temperature, + Sdc *sdc); + // Pvt may be shared among multiple instances. + void setPvt(const Instance *inst, + const MinMaxAll *min_max, + const Pvt &pvt, + Sdc *sdc); + void setVoltage(const MinMax *min_max, + float voltage, + Sdc *sdc); + void setVoltage(const Net *net, + const MinMax *min_max, + float voltage, + Sdc *sdc); - virtual CheckErrorSeq &checkTiming(bool no_input_delay, - bool no_output_delay, - bool reg_multiple_clks, - bool reg_no_clks, - bool unconstrained_endpoints, - bool loops, - bool generated_clks); + CheckErrorSeq &checkTiming(const Mode *mode, + bool no_input_delay, + bool no_output_delay, + bool reg_multiple_clks, + bool reg_no_clks, + bool unconstrained_endpoints, + bool loops, + bool generated_clks); // Path from/thrus/to filter. // from/thrus/to are owned and deleted by Search. // PathEnds in the returned PathEndSeq are owned by Search PathGroups // and deleted on next call. - virtual PathEndSeq findPathEnds(ExceptionFrom *from, - ExceptionThruSeq *thrus, - ExceptionTo *to, - bool unconstrained, - // Use corner nullptr to report timing - // for all corners. - const Corner *corner, - // max for setup checks. - // min for hold checks. - // min_max for setup and hold checks. - const MinMaxAll *min_max, - // Number of path ends to report in - // each group. - int group_path_count, - // Number of paths to report for - // each endpoint. - int endpoint_path_count, - // endpoint_path_count paths report paths with - // unique pins. - bool unique_pins, - // endpoint_path_count paths report paths with - // unique pins and rise/fall edges. - bool unique_edges, - // Min/max bounds for slack of - // returned path ends. - float slack_min, - float slack_max, - // Sort path ends by slack ignoring path groups. - bool sort_by_slack, - // Path groups to report. - // Null or empty list reports all groups. - PathGroupNameSet *group_names, - // Predicates to filter the type of path - // ends returned. - bool setup, - bool hold, - bool recovery, - bool removal, - bool clk_gating_setup, - bool clk_gating_hold); + PathEndSeq findPathEnds(ExceptionFrom *from, + ExceptionThruSeq *thrus, + ExceptionTo *to, + bool unconstrained, + const SceneSeq &scenes, + // max for setup checks. + // min for hold checks. + // min_max for setup and hold checks. + const MinMaxAll *min_max, + // Number of path ends to report in + // each group. + int group_path_count, + // Number of paths to report for + // each endpoint. + int endpoint_path_count, + // endpoint_path_count paths report unique pins + // without rise/fall variations. + bool unique_pins, + // endpoint_path_count paths report paths with + // unique pins and rise/fall edges. + bool unique_edges, + // Min/max bounds for slack of + // returned path ends. + float slack_min, + float slack_max, + // Sort path ends by slack ignoring path groups. + bool sort_by_slack, + // Path groups to report. + // Empty list reports all groups. + StdStringSeq &group_names, + // Predicates to filter the type of path + // ends returned. + bool setup, + bool hold, + bool recovery, + bool removal, + bool clk_gating_setup, + bool clk_gating_hold); void setReportPathFormat(ReportPathFormat format); void setReportPathFieldOrder(StringSeq *field_names); void setReportPathFields(bool report_input_pin, bool report_hier_pins, - bool report_net, - bool report_cap, - bool report_slew, - bool report_fanout, - bool report_src_attr); + bool report_net, + bool report_cap, + bool report_slew, + bool report_fanout, + bool report_src_attr); ReportField *findReportPathField(const char *name); void setReportPathDigits(int digits); void setReportPathNoSplit(bool no_split); @@ -865,7 +988,7 @@ public: // Previous path end is used to detect path group changes // so headers are reported by group. void reportPathEnd(PathEnd *end, - PathEnd *prev_end, + PathEnd *prev_end, bool last); void reportPathEnd(PathEnd *end); void reportPathEnds(PathEndSeq *ends); @@ -874,19 +997,20 @@ public: // Report clk skews for clks. void reportClkSkew(ConstClockSeq &clks, - const Corner *corner, - const SetupHold *setup_hold, + const SceneSeq &scenes, + const SetupHold *setup_hold, bool include_internal_latency, - int digits); + int digits); float findWorstClkSkew(const SetupHold *setup_hold, bool include_internal_latency); void reportClkLatency(ConstClockSeq &clks, - const Corner *corner, + const SceneSeq &scenes, bool include_internal_latency, int digits); // Find min/max/rise/fall delays for clk. ClkDelays findClkDelays(const Clock *clk, + const Scene *scene, bool include_internal_latency); // Update arrival times for all pins. @@ -905,46 +1029,41 @@ public: void arrivalsInvalid(); PinSet startpointPins(); PinSet endpointPins(); - VertexSet *endpoints(); + VertexSet &endpoints(); int endpointViolationCount(const MinMax *min_max); // Find all required times after updateTiming(). void findRequireds(); std::string reportDelayCalc(Edge *edge, TimingArc *arc, - const Corner *corner, + const Scene *scene, const MinMax *min_max, int digits); - void writeSdc(const char *filename, - // Map hierarchical pins and instances to leaf pins and instances. - bool leaf, - // Replace non-sdc get functions with OpenSTA equivalents. - bool native, - int digits, + void writeSdc(const Sdc *sdc, + const char *filename, + // Map hierarchical pins and instances to leaf pins and instances. + bool leaf, + // Replace non-sdc get functions with OpenSTA equivalents. + bool native, + int digits, bool gzip, - bool no_timestamp); + bool no_timestamp); // The sum of all negative endpoints slacks. // Incrementally updated. Slack totalNegativeSlack(const MinMax *min_max); - Slack totalNegativeSlack(const Corner *corner, - const MinMax *min_max); + Slack totalNegativeSlack(const Scene *scene, + const MinMax *min_max); // Worst endpoint slack and vertex. // Incrementally updated. Slack worstSlack(const MinMax *min_max); void worstSlack(const MinMax *min_max, - // Return values. - Slack &worst_slack, - Vertex *&worst_vertex); - void worstSlack(const Corner *corner, - const MinMax *min_max, - // Return values. - Slack &worst_slack, - Vertex *&worst_vertex); - VertexPathIterator *vertexPathIterator(Vertex *vertex, - const RiseFall *rf, - const PathAnalysisPt *path_ap); - VertexPathIterator *vertexPathIterator(Vertex *vertex, - const RiseFall *rf, - const MinMax *min_max); + // Return values. + Slack &worst_slack, + Vertex *&worst_vertex); + void worstSlack(const Scene *scene, + const MinMax *min_max, + // Return values. + Slack &worst_slack, + Vertex *&worst_vertex); Path *vertexWorstArrivalPath(Vertex *vertex, const RiseFall *rf, const MinMax *min_max); @@ -971,93 +1090,75 @@ public: // update timing to the level of the vertex. They do NOT do multiple // passes required propagate arrivals around latch loops. // See Sta::updateTiming() to propagate arrivals around latch loops. - Arrival vertexArrival(Vertex *vertex, - const RiseFall *rf, - const ClockEdge *clk_edge, - const PathAnalysisPt *path_ap, - const MinMax *min_max); - // Min/max across all clock tags. - Arrival vertexArrival(Vertex *vertex, - const RiseFall *rf, - const PathAnalysisPt *path_ap); - Arrival vertexArrival(Vertex *vertex, - const MinMax *min_max); - Arrival pinArrival(const Pin *pin, - const RiseFall *rf, - const MinMax *min_max); - Required vertexRequired(Vertex *vertex, - const MinMax *min_max); - Required vertexRequired(Vertex *vertex, - const RiseFall *rf, - const MinMax *min_max); - // Min/max across all clock tags. - Required vertexRequired(Vertex *vertex, - const RiseFall *rf, - const PathAnalysisPt *path_ap); - Required vertexRequired(Vertex *vertex, - const RiseFall *rf, - const ClockEdge *clk_edge, - const PathAnalysisPt *path_ap); + Arrival arrival(const Pin *pin, + const RiseFallBoth *rf, + const MinMax *min_max); + Arrival arrival(Vertex *vertex, + const RiseFallBoth *rf, + const SceneSeq &scenes, + const MinMax *min_max); - Slack netSlack(const Net *net, - const MinMax *min_max); - Slack pinSlack(const Pin *pin, - const RiseFall *rf, - const MinMax *min_max); - Slack pinSlack(const Pin *pin, - const MinMax *min_max); + Required required(Vertex *vertex, + const RiseFallBoth *rf, + const SceneSeq &scenes, + const MinMax *min_max); + + Slack slack(const Net *net, + const MinMax *min_max); + Slack slack(const Pin *pin, + const RiseFallBoth *rf, + const SceneSeq &scenes, + const MinMax *min_max); + + Slack slack(Vertex *vertex, + const MinMax *min_max); + Slack slack(Vertex *vertex, + const RiseFall *rf, + const MinMax *min_max); + Slack slack(Vertex *vertex, + const RiseFallBoth *rf, + const SceneSeq &scenes, + const MinMax *min_max); + + void slacks(Vertex *vertex, + Slack (&slacks)[RiseFall::index_count][MinMax::index_count]); // Worst slack for an endpoint in a path group. Slack endpointSlack(const Pin *pin, - const std::string &path_group_name, - const MinMax *min_max); - Slack vertexSlack(Vertex *vertex, - const MinMax *min_max); - Slack vertexSlack(Vertex *vertex, - const RiseFall *rf, - const MinMax *min_max); - // Slack with respect to clk_edge. - Slack vertexSlack(Vertex *vertex, - const RiseFall *rf, - const ClockEdge *clk_edge, - const PathAnalysisPt *path_ap); - // Min slack across all clock tags. - Slack vertexSlack(Vertex *vertex, - const RiseFall *rf, - const PathAnalysisPt *path_ap); - void vertexSlacks(Vertex *vertex, - Slack (&slacks)[RiseFall::index_count][MinMax::index_count]); - // Slew for one corner. - Slew vertexSlew(Vertex *vertex, - const RiseFall *rf, - const Corner *corner, - const MinMax *min_max); - // Slew for one delay calc analysis pt (corner min/max). - Slew vertexSlew(Vertex *vertex, - const RiseFall *rf, - const DcalcAnalysisPt *dcalc_ap); - // Slew across all corners. - Slew vertexSlew(Vertex *vertex, - const RiseFall *rf, - const MinMax *min_max); - Slew vertexSlew(Vertex *vertex, - const MinMax *min_max); + const std::string &path_group_name, + const MinMax *min_max); + + void reportArrivalWrtClks(const Pin *pin, + const Scene *scene, + int digits); + void reportRequiredWrtClks(const Pin *pin, + const Scene *scene, + int digits); + void reportSlackWrtClks(const Pin *pin, + const Scene *scene, + int digits); + + Slew slew(Vertex *vertex, + const RiseFallBoth *rf, + const SceneSeq &scenes, + const MinMax *min_max); + ArcDelay arcDelay(Edge *edge, - TimingArc *arc, - const DcalcAnalysisPt *dcalc_ap); + TimingArc *arc, + DcalcAPIndex ap_index); // True if the timing arc has been back-annotated. bool arcDelayAnnotated(Edge *edge, - TimingArc *arc, - DcalcAnalysisPt *dcalc_ap); + TimingArc *arc, + const Scene *scene, + const MinMax *min_max); // Set/unset the back-annotation flag for a timing arc. void setArcDelayAnnotated(Edge *edge, - TimingArc *arc, - DcalcAnalysisPt *dcalc_ap, - bool annotated); + TimingArc *arc, + const Scene *scene, + const MinMax *min_max, + bool annotated); // Make sure levels are up to date and return vertex level. Level vertexLevel(Vertex *vertex); GraphLoopSeq &graphLoops(); - PathAnalysisPt *pathAnalysisPt(Path *path); - DcalcAnalysisPt *pathDcalcAnalysisPt(Path *path); TagIndex tagCount() const; TagGroupIndex tagGroupCount() const; int clkInfoCount() const; @@ -1065,90 +1166,91 @@ public: int vertexPathCount(Vertex *vertex) const; Vertex *maxPathCountVertex() const; - LogicValue simLogicValue(const Pin *pin); // Propagate liberty constant functions and pins tied high/low through - // combinational logic and registers. + // combinational logic and registers. This is mode/sdc independent. + // Used by OpenROAD/Restructure.cpp void findLogicConstants(); - // Clear the constants found by findLogicConstants so they do not interfere - // with normal constant propagate for timing. + LogicValue simLogicValue(const Pin *pin, + const Mode *mode); + // Clear propagated sim constants. void clearLogicConstants(); // Instances sorted by max driver pin slew. InstanceSeq slowDrivers(int count); - // Make parasitic analysis points. - // per_corner ap_count - // false 2 - // true corners*2 - void setParasiticAnalysisPts(bool per_corner); + Parasitics *makeConcreteParasitics(std::string name, + std::string filename); // Annotate hierarchical "instance" with parasitics. // The parasitic analysis point is ap_name. // The parasitic memory footprint is much smaller if parasitic // networks (dspf) are reduced and deleted after reading each net // with reduce_to and delete_after_reduce. // Return true if successful. - bool readSpef(const char *filename, - Instance *instance, - const Corner *corner, + bool readSpef(const std::string &name, + const std::string &filename, + Instance *instance, + Scene *scene, const MinMaxAll *min_max, - bool pin_cap_included, - bool keep_coupling_caps, - float coupling_cap_factor, - bool reduce); - void reportParasiticAnnotation(bool report_unannotated, - const Corner *corner); + bool pin_cap_included, + bool keep_coupling_caps, + float coupling_cap_factor, + bool reduce); + Parasitics *findParasitics(const std::string &name); + void reportParasiticAnnotation(const std::string &spef_name, + bool report_unannotated); // Parasitics. void findPiElmore(Pin *drvr_pin, - const RiseFall *rf, - const MinMax *min_max, - float &c2, - float &rpi, - float &c1, - bool &exists) const; + const RiseFall *rf, + const MinMax *min_max, + float &c2, + float &rpi, + float &c1, + bool &exists) const; void findElmore(Pin *drvr_pin, - Pin *load_pin, - const RiseFall *rf, - const MinMax *min_max, - float &elmore, - bool &exists) const; + Pin *load_pin, + const RiseFall *rf, + const MinMax *min_max, + float &elmore, + bool &exists) const; void makePiElmore(Pin *drvr_pin, - const RiseFall *rf, - const MinMaxAll *min_max, - float c2, - float rpi, - float c1); + const RiseFall *rf, + const MinMaxAll *min_max, + float c2, + float rpi, + float c1); void setElmore(Pin *drvr_pin, - Pin *load_pin, - const RiseFall *rf, - const MinMaxAll *min_max, - float elmore); + Pin *load_pin, + const RiseFall *rf, + const MinMaxAll *min_max, + float elmore); void deleteParasitics(); Parasitic *makeParasiticNetwork(const Net *net, bool includes_pin_caps, - const ParasiticAnalysisPt *ap); + const Scene *scene, + const MinMax *min_max); //////////////////////////////////////////////////////////////// // TCL network edit function support. virtual Instance *makeInstance(const char *name, - LibertyCell *cell, - Instance *parent); + LibertyCell *cell, + Instance *parent); virtual void deleteInstance(Instance *inst); // replace_cell virtual void replaceCell(Instance *inst, - Cell *to_cell); + Cell *to_cell); virtual void replaceCell(Instance *inst, - LibertyCell *to_lib_cell); + LibertyCell *to_lib_cell); virtual Net *makeNet(const char *name, - Instance *parent); + Instance *parent); virtual void deleteNet(Net *net); // connect_net virtual void connectPin(Instance *inst, - Port *port, - Net *net); + Port *port, + Net *net); virtual void connectPin(Instance *inst, - LibertyPort *port, - Net *net); + LibertyPort *port, + Net *net); // disconnect_net virtual void disconnectPin(Pin *pin); virtual void makePortPin(const char *port_name, @@ -1163,12 +1265,12 @@ public: // Replace the instance cell with to_cell. // equivCells(from_cell, to_cell) must be true. virtual void replaceEquivCellBefore(const Instance *inst, - const LibertyCell *to_cell); + const LibertyCell *to_cell); virtual void replaceEquivCellAfter(const Instance *inst); // Replace the instance cell with to_cell. // equivCellPorts(from_cell, to_cell) must be true. virtual void replaceCellBefore(const Instance *inst, - const LibertyCell *to_cell); + const LibertyCell *to_cell); virtual void replaceCellAfter(const Instance *inst); virtual void makePortPinAfter(Pin *pin); virtual void connectPinAfter(const Pin *pin); @@ -1179,14 +1281,19 @@ public: //////////////////////////////////////////////////////////////// - void ensureClkNetwork(); - void clkPinsInvalid(); + void ensureClkNetwork(const Mode *mode); + void clkPinsInvalid(const Mode *mode); // The following functions assume ensureClkNetwork() has been called. - bool isClock(const Pin *pin) const; - bool isClock(const Net *net) const; - bool isIdealClock(const Pin *pin) const; - bool isPropagatedClock(const Pin *pin) const; - const PinSet *pins(const Clock *clk); + bool isClock(const Pin *pin, + const Mode *mode) const; + bool isClock(const Net *net, + const Mode *mode) const; + bool isIdealClock(const Pin *pin, + const Mode *mode) const; + bool isPropagatedClock(const Pin *pin, + const Mode *mode) const; + const PinSet *pins(const Clock *clk, + const Mode *mode); //////////////////////////////////////////////////////////////// @@ -1200,11 +1307,7 @@ public: // Ensure that the timing graph has been built. Graph *ensureGraph(); void ensureClkArrivals(); - Corner *cmdCorner() const; - void setCmdCorner(Corner *corner); - Corner *findCorner(const char *corner_name); - bool multiCorner(); - virtual void makeCorners(StringSet *corner_names); + // Find all arc delays and vertex slews with delay calculator. virtual void findDelays(); // Find arc delays and vertex slews thru to level of to_vertex. @@ -1222,7 +1325,7 @@ public: void setArcDelayCalc(const char *delay_calc_name); void setDebugLevel(const char *what, - int level); + int level); // Delays and arrivals downsteam from inst are invalid. void delaysInvalidFrom(const Instance *inst); @@ -1235,33 +1338,47 @@ public: void delaysInvalidFromFanin(const Pin *pin); void delaysInvalidFromFanin(Vertex *vertex); void replaceCellPinInvalidate(const LibertyPort *from_port, - Vertex *vertex, - const LibertyCell *to_cell); + Vertex *vertex, + const LibertyCell *to_cell); // Power API. + void reportPowerDesign(const Scene *scene, + int digits); + void reportPowerInsts(const InstanceSeq &insts, + const Scene *scene, + int digits); + void reportPowerHighestInsts(size_t count, + const Scene *scene, + int digits); + void reportPowerDesignJson(const Scene *scene, + int digits); + void reportPowerInstsJson(const InstanceSeq &insts, + const Scene *scene, + int digits); Power *power() { return power_; } const Power *power() const { return power_; } - void power(const Corner *corner, - // Return values. - PowerResult &total, - PowerResult &sequential, - PowerResult &combinational, - PowerResult &clock, - PowerResult ¯o, - PowerResult &pad); + void power(const Scene *scene, + // Return values. + PowerResult &total, + PowerResult &sequential, + PowerResult &combinational, + PowerResult &clock, + PowerResult ¯o, + PowerResult &pad); PowerResult power(const Instance *inst, - const Corner *corner); - PwrActivity activity(const Pin *pin); + const Scene *scene); + PwrActivity activity(const Pin *pin, + const Scene *scene); void writeTimingModel(const char *lib_name, const char *cell_name, const char *filename, - const Corner *corner); + const Scene *scene); // Find equivalent cells in equiv_libs. // Optionally add mappings for cells in map_libs. void makeEquivCells(LibertyLibrarySeq *equiv_libs, - LibertyLibrarySeq *map_libs); + LibertyLibrarySeq *map_libs); LibertyCellSeq *equivCells(LibertyCell *cell); void writePathSpice(Path *path, @@ -1307,10 +1424,6 @@ public: // Enable/disable timing from bidirect pins back into the instance. bool bidirectInstPathsEnabled() const; void setBidirectInstPathsEnabled(bool enabled); - // TCL variable sta_bidirect_net_paths_enabled. - // Enable/disable timing from bidirect driver pins to their own loads. - bool bidirectNetPathsEnabled() const; - void setBidirectNetPathsEnabled(bool enabled); // TCL variable sta_recovery_removal_checks_enabled. bool recoveryRemovalChecksEnabled() const; void setRecoveryRemovalChecksEnabled(bool enabled); @@ -1345,21 +1458,17 @@ protected: virtual void makeUnits(); virtual void makeNetwork(); virtual void makeSdcNetwork(); - virtual void makeSdc(); virtual void makeGraph(); - virtual void makeCorners(); + virtual void makeDefaultScene(); virtual void makeLevelize(); - virtual void makeParasitics(); virtual void makeArcDelayCalc(); virtual void makeGraphDelayCalc(); - virtual void makeSim(); virtual void makeSearch(); virtual void makeLatches(); - virtual void makeClkNetwork(); virtual void makeCheckTiming(); - virtual void makeCheckSlewLimits(); - virtual void makeCheckFanoutLimits(); - virtual void makeCheckCapacitanceLimits(); + virtual void makeCheckSlews(); + virtual void makeCheckFanouts(); + virtual void makeCheckCapacitances(); virtual void makeCheckMinPulseWidths(); virtual void makeCheckMinPeriods(); virtual void makeCheckMaxSkews(); @@ -1370,101 +1479,133 @@ protected: NetworkEdit *networkCmdEdit(); LibertyLibrary *readLibertyFile(const char *filename, - Corner *corner, - const MinMaxAll *min_max, - bool infer_latches); + Scene *scene, + const MinMaxAll *min_max, + bool infer_latches); // Allow external Liberty reader to parse forms not used by Sta. virtual LibertyLibrary *readLibertyFile(const char *filename, - bool infer_latches); + bool infer_latches); void delayCalcPreamble(); void delaysInvalidFrom(const Port *port); void delaysInvalidFromFanin(const Port *port); void deleteEdge(Edge *edge); void netParasiticCaps(Net *net, - const RiseFall *rf, - const MinMax *min_max, - float &pin_cap, - float &wire_cap) const; + const RiseFall *rf, + const MinMax *min_max, + float &pin_cap, + float &wire_cap) const; const Pin *findNetParasiticDrvrPin(const Net *net) const; void exprConstantPins(FuncExpr *expr, - const Instance *inst, - PinSet &pins); - Slack vertexSlack1(Vertex *vertex, - const RiseFall *rf, - const ClockEdge *clk_edge, - const PathAnalysisPt *path_ap); + const Instance *inst, + const Mode *mode, + // Return value. + PinSet &pins); void findRequired(Vertex *vertex); - Required vertexRequired(Vertex *vertex, - const RiseFall *rf, - const ClockEdge *clk_edge, - const PathAnalysisPt *path_ap, - const MinMax *min_max); + + void reportDelaysWrtClks(const Pin *pin, + const Scene *scene, + int digits, + PathDelayFunc get_path_delay); + void reportDelaysWrtClks(Vertex *vertex, + const Scene *scene, + int digits, + PathDelayFunc get_path_delay); + void reportDelaysWrtClks(Vertex *vertex, + const ClockEdge *clk_edge, + const Scene *scene, + int digits, + PathDelayFunc get_path_delay); + RiseFallMinMaxDelay findDelaysWrtClks(Vertex *vertex, + const ClockEdge *clk_edge, + const Scene *scene, + PathDelayFunc get_path_delay); + std::string formatDelay(const RiseFall *rf, + const MinMax *min_max, + const RiseFallMinMaxDelay &delays, + int digits); + void connectDrvrPinAfter(Vertex *vertex); void connectLoadPinAfter(Vertex *vertex); Path *latchEnablePath(Path *q_path, - Edge *d_q_edge, - const ClockEdge *en_clk_edge); + Edge *d_q_edge, + const ClockEdge *en_clk_edge); void clockSlewChanged(Clock *clk); - void minPulseWidthPreamble(); - void minPeriodPreamble(); void maxSkewPreamble(); bool idealClockMode(); void disableAfter(); void findFaninPins(Vertex *vertex, - bool flat, - bool startpoints_only, - int inst_levels, - int pin_levels, - PinSet &fanin, - SearchPred &pred); + bool flat, + bool startpoints_only, + int inst_levels, + int pin_levels, + PinSet &fanin, + SearchPred &pred, + const Mode *mode); void findFaninPins(Vertex *to, - bool flat, - int inst_levels, - int pin_levels, - VertexSet &visited, - SearchPred *pred, - int inst_level, - int pin_level); + bool flat, + int inst_levels, + int pin_levels, + VertexSet &visited, + SearchPred *pred, + int inst_level, + int pin_level, + const Mode *mode); void findFanoutPins(Vertex *vertex, - bool flat, - bool endpoints_only, - int inst_levels, - int pin_levels, - PinSet &fanout, - SearchPred &pred); + bool flat, + bool endpoints_only, + int inst_levels, + int pin_levels, + PinSet &fanout, + SearchPred &pred, + const Mode *mode); void findFanoutPins(Vertex *from, - bool flat, - int inst_levels, - int pin_levels, - VertexSet &visited, - SearchPred *pred, - int inst_level, - int pin_level); - void findRegisterPreamble(); + bool flat, + int inst_levels, + int pin_levels, + VertexSet &visited, + SearchPred *pred, + int inst_level, + int pin_level, + const Mode *mode); + void findRegisterPreamble(const Mode *mode); bool crossesHierarchy(Edge *edge) const; void readLibertyAfter(LibertyLibrary *liberty, - Corner *corner, - const MinMax *min_max); + Scene *scene, + const MinMax *min_max); void powerPreamble(); + void powerPreamble(const Scene *scene); virtual void replaceCell(Instance *inst, Cell *to_cell, LibertyCell *to_lib_cell); - void sdcChangedGraph(); - void ensureGraphSdcAnnotated(); - CornerSeq makeCornerSeq(Corner *corner) const; - void makeParasiticAnalysisPts(); void clkSkewPreamble(); void setCmdNamespace1(CmdNamespace namespc); void setThreadCount1(int thread_count); + void updateLibertyScenes(); + void updateSceneLiberty(Scene *scene, + const StdStringSeq &liberty_files, + const MinMax *min_max); + LibertyLibrary *findLibertyFileBasename(const std::string &filename) const; + Scene *makeScene(const std::string &name, + Mode *mode, + Parasitics *parasitics_min, + Parasitics *parasitics_max); + Scene *makeScene(const std::string &name, + Mode *mode, + Parasitics *parasitics); + void deleteScenes(); + + Scene *cmd_scene_; CmdNamespace cmd_namespace_; Instance *current_instance_; - Corner *cmd_corner_; + SceneNameMap scene_name_map_; + ModeNameMap mode_name_map_; + ParasiticsNameMap parasitics_name_map_; VerilogReader *verilog_reader_; CheckTiming *check_timing_; - CheckSlewLimits *check_slew_limits_; - CheckFanoutLimits *check_fanout_limits_; - CheckCapacitanceLimits *check_capacitance_limits_; + CheckSlews *check_slews_; + CheckFanouts *check_fanouts_; + CheckCapacitances *check_capacitances_; CheckMinPulseWidths *check_min_pulse_widths_; CheckMinPeriods *check_min_periods_; CheckMaxSkews *check_max_skews_; @@ -1474,9 +1615,6 @@ protected: Tcl_Interp *tcl_interp_; bool update_genclks_; EquivCells *equiv_cells_; - bool graph_sdc_annotated_; - bool parasitics_per_corner_; - bool parasitics_per_min_max_; Properties properties_; // Singleton sta used by tcl command interpreter. diff --git a/include/sta/StaMain.hh b/include/sta/StaMain.hh index 92a9bbe4..0d34ff07 100644 --- a/include/sta/StaMain.hh +++ b/include/sta/StaMain.hh @@ -33,16 +33,16 @@ class Sta; // Parse command line argument int staTclAppInit(int argc, - char *argv[], - const char *init_filename, - Tcl_Interp *interp); + char *argv[], + const char *init_filename, + Tcl_Interp *interp); // Sta initialization. // Makes the Sta object and registers TCL commands. void initSta(int argc, - char *argv[], - Tcl_Interp *interp); + char *argv[], + Tcl_Interp *interp); // TCL init files are encoded into the string init using the three // digit decimal equivalent for each ascii character. This function @@ -51,28 +51,26 @@ initSta(int argc, // separate files that have to be located and loaded at run time. void evalTclInit(Tcl_Interp *interp, - const char *inits[]); + const char *inits[]); char * unencode(const char *inits[]); bool findCmdLineFlag(int &argc, - char *argv[], - const char *flag); + char *argv[], + const char *flag); char * findCmdLineKey(int &argc, - char *argv[], - const char *key); + char *argv[], + const char *key); int parseThreadsArg(int &argc, - char *argv[]); + char *argv[]); int sourceTclFile(const char *filename, - bool echo, - bool verbose, - Tcl_Interp *interp); -bool -is_regular_file(const char *filename); + bool echo, + bool verbose, + Tcl_Interp *interp); } // namespace diff --git a/include/sta/StaState.hh b/include/sta/StaState.hh index cce271be..7d6ce5a7 100644 --- a/include/sta/StaState.hh +++ b/include/sta/StaState.hh @@ -24,6 +24,10 @@ #pragma once +#include + +#include "Scene.hh" + namespace sta { class Report; @@ -32,8 +36,6 @@ class Units; class Network; class NetworkEdit; class NetworkReader; -class Sdc; -class Corners; class Graph; class Edge; class Levelize; @@ -43,10 +45,12 @@ class Parasitics; class ArcDelayCalc; class GraphDelayCalc; class Latches; -class ClkNetwork; class DispatchQueue; class Variables; +using ModeSeq = std::vector; +using ModeSet = std::set; + // Most STA components use functionality in other components. // This class simplifies the process of copying pointers to the // components. It is deliberately simple to minimize circular @@ -81,35 +85,38 @@ public: // Command network uses the SDC namespace. Network *cmdNetwork() { return cmd_network_; } Network *cmdNetwork() const { return cmd_network_; } - Sdc *sdc() { return sdc_; } - Sdc *sdc() const { return sdc_; } - Corners *corners() { return corners_; } - Corners *corners() const { return corners_; } Graph *graph() { return graph_; } Graph *graph() const { return graph_; } + Graph *&graphRef() { return graph_; } Levelize *levelize() { return levelize_; } Levelize *levelize() const { return levelize_; } - Parasitics *parasitics() { return parasitics_; } - Parasitics *parasitics() const { return parasitics_; } ArcDelayCalc *arcDelayCalc() { return arc_delay_calc_; } ArcDelayCalc *arcDelayCalc() const { return arc_delay_calc_; } GraphDelayCalc *graphDelayCalc() { return graph_delay_calc_; } GraphDelayCalc *graphDelayCalc() const { return graph_delay_calc_; } - Sim *sim() { return sim_; } - Sim *sim() const { return sim_; } Search *search() { return search_; } Search *search() const { return search_; } Latches *latches() { return latches_; } Latches *latches() const { return latches_; } - ClkNetwork *clkNetwork() { return clk_network_; } - ClkNetwork *clkNetwork() const { return clk_network_; } unsigned threadCount() const { return thread_count_; } float sigmaFactor() const { return sigma_factor_; } - bool crprActive() const; + bool crprActive(const Mode *mode) const; Variables *variables() { return variables_; } const Variables *variables() const { return variables_; } // Edge is default cond disabled by timing_disable_cond_default_arcs var. - bool isDisabledCondDefault(Edge *edge) const; + [[nodiscard]] bool isDisabledCondDefault(const Edge *edge) const; + + const SceneSeq &scenes() { return scenes_; } + const SceneSeq &scenes() const { return scenes_; } + bool multiScene() const { return scenes_.size() > 1; } + size_t scenePathCount() const; + DcalcAPIndex dcalcAnalysisPtCount() const; + + const SceneSet scenesSet(); + + ModeSeq &modes() { return modes_; } + const ModeSeq &modes() const { return modes_; } + bool multiMode() const { return modes_.size() > 1; } protected: Report *report_; @@ -119,17 +126,14 @@ protected: Network *sdc_network_; // Network used by command interpreter (SdcNetwork). Network *cmd_network_; - Sdc *sdc_; - Corners *corners_; + SceneSeq scenes_; + ModeSeq modes_; Graph *graph_; Levelize *levelize_; - Parasitics *parasitics_; ArcDelayCalc *arc_delay_calc_; GraphDelayCalc *graph_delay_calc_; - Sim *sim_; Search *search_; Latches *latches_; - ClkNetwork *clk_network_; Variables *variables_; int thread_count_; DispatchQueue *dispatch_queue_; diff --git a/include/sta/Stats.hh b/include/sta/Stats.hh index 7f10effe..4d40594b 100644 --- a/include/sta/Stats.hh +++ b/include/sta/Stats.hh @@ -35,8 +35,8 @@ class Report; class Stats { public: - explicit Stats(Debug *debug, - Report *report); + Stats(Debug *debug, + Report *report); void report(const char *step); private: diff --git a/include/sta/StringSeq.hh b/include/sta/StringSeq.hh index 453af7ef..ca7c304f 100644 --- a/include/sta/StringSeq.hh +++ b/include/sta/StringSeq.hh @@ -24,12 +24,14 @@ #pragma once +#include + #include "StringUtil.hh" -#include "Vector.hh" namespace sta { -typedef Vector StringSeq; +using StringSeq = std::vector; +using StdStringSeq = std::vector; void deleteContents(StringSeq *strings); diff --git a/include/sta/StringSet.hh b/include/sta/StringSet.hh index ae643e35..36fa7e67 100644 --- a/include/sta/StringSet.hh +++ b/include/sta/StringSet.hh @@ -26,12 +26,12 @@ #include #include "StringUtil.hh" -#include "Set.hh" namespace sta { -typedef Set StringSet; -typedef std::set StdStringSet; +using StringSet = std::set; +using StdStringSet = std::set; +using StdStringSeq = std::vector; void deleteContents(StringSet *strings); diff --git a/include/sta/StringUtil.hh b/include/sta/StringUtil.hh index c858df5f..9523670b 100644 --- a/include/sta/StringUtil.hh +++ b/include/sta/StringUtil.hh @@ -27,15 +27,15 @@ #include #include #include +#include #include "Machine.hh" // __attribute__ -#include "Vector.hh" namespace sta { inline bool stringEq(const char *str1, - const char *str2) + const char *str2) { return strcmp(str1, str2) == 0; } @@ -43,15 +43,15 @@ stringEq(const char *str1, // Compare the first length characters. inline bool stringEq(const char *str1, - const char *str2, - size_t length) + const char *str2, + size_t length) { return strncmp(str1, str2, length) == 0; } inline bool stringEqIf(const char *str1, - const char *str2) + const char *str2) { return (str1 == nullptr && str2 == nullptr) || (str1 && str2 && strcmp(str1, str2) == 0); @@ -60,7 +60,7 @@ stringEqIf(const char *str1, // Case sensitive compare the beginning of str1 to str2. inline bool stringBeginEq(const char *str1, - const char *str2) + const char *str2) { return strncmp(str1, str2, strlen(str2)) == 0; } @@ -68,7 +68,7 @@ stringBeginEq(const char *str1, // Case insensitive compare the beginning of str1 to str2. inline bool stringBeginEqual(const char *str1, - const char *str2) + const char *str2) { return strncasecmp(str1, str2, strlen(str2)) == 0; } @@ -76,14 +76,14 @@ stringBeginEqual(const char *str1, // Case insensitive compare. inline bool stringEqual(const char *str1, - const char *str2) + const char *str2) { return strcasecmp(str1, str2) == 0; } inline bool stringEqualIf(const char *str1, - const char *str2) + const char *str2) { return (str1 == nullptr && str2 == nullptr) || (str1 && str2 && strcasecmp(str1, str2) == 0); @@ -91,14 +91,14 @@ stringEqualIf(const char *str1, inline bool stringLess(const char *str1, - const char *str2) + const char *str2) { return strcmp(str1, str2) < 0; } inline bool stringLessIf(const char *str1, - const char *str2) + const char *str2) { return (str1 == nullptr && str2 != nullptr) || (str1 != nullptr && str2 != nullptr && strcmp(str1, str2) < 0); @@ -108,7 +108,7 @@ class CharPtrLess { public: bool operator()(const char *string1, - const char *string2) const + const char *string2) const { return stringLess(string1, string2); } @@ -119,7 +119,7 @@ class CharPtrCaseLess { public: bool operator()(const char *string1, - const char *string2) const + const char *string2) const { return strcasecmp(string1, string2) < 0; } @@ -129,7 +129,7 @@ class StringLessIf { public: bool operator()(const char *string1, - const char *string2) const + const char *string2) const { return stringLessIf(string1, string2); } @@ -141,7 +141,7 @@ stringCopy(const char *str); inline void stringAppend(char *&str1, - const char *str2) + const char *str2) { strcpy(str1, str2); str1 += strlen(str2); @@ -164,17 +164,17 @@ isDigits(const char *str); // Caller owns returned string. char * stringPrint(const char *fmt, - ...) __attribute__((format (printf, 1, 2))); + ...) __attribute__((format (printf, 1, 2))); std::string stdstrPrint(const char *fmt, - ...) __attribute__((format (printf, 1, 2))); + ...) __attribute__((format (printf, 1, 2))); char * stringPrintArgs(const char *fmt, - va_list args); + va_list args); void stringPrint(std::string &str, - const char *fmt, - ...) __attribute__((format (printf, 2, 3))); + const char *fmt, + ...) __attribute__((format (printf, 2, 3))); // Formated append to std::string. void stringAppend(std::string &str, @@ -184,7 +184,7 @@ stringAppend(std::string &str, // Print to a temporary string. char * stringPrintTmp(const char *fmt, - ...) __attribute__((format (printf, 1, 2))); + ...) __attribute__((format (printf, 1, 2))); char * makeTmpString(size_t length); @@ -199,7 +199,7 @@ isTmpString(const char *str); void trimRight(std::string &str); -typedef Vector StringVector; +using StringVector = std::vector; void split(const std::string &text, diff --git a/include/sta/TableModel.hh b/include/sta/TableModel.hh index 40dd60c6..a392e7d6 100644 --- a/include/sta/TableModel.hh +++ b/include/sta/TableModel.hh @@ -26,9 +26,9 @@ #include #include +#include #include "MinMax.hh" -#include "Vector.hh" #include "Transition.hh" #include "LibertyClass.hh" #include "TimingModel.hh" @@ -42,10 +42,10 @@ class Table; class OutputWaveforms; class Table1; -typedef Vector FloatSeq; -typedef Vector FloatTable; -typedef Vector Table1Seq; -typedef Table1 Waveform; +using FloatSeq = std::vector; +using FloatTable = std::vector; +using Table1Seq = std::vector; +using Waveform = Table1; TableAxisVariable stringTableAxisVariable(const char *variable); @@ -53,16 +53,16 @@ const char * tableVariableString(TableAxisVariable variable); const Unit * tableVariableUnit(TableAxisVariable variable, - const Units *units); + const Units *units); class GateTableModel : public GateTimingModel { public: GateTableModel(LibertyCell *cell, TableModel *delay_model, - TableModel *delay_sigma_models[EarlyLate::index_count], - TableModel *slew_model, - TableModel *slew_sigma_models[EarlyLate::index_count], + TableModel *delay_sigma_models[EarlyLate::index_count], + TableModel *slew_model, + TableModel *slew_sigma_models[EarlyLate::index_count], ReceiverModelPtr receiver_model, OutputWaveforms *output_waveforms); virtual ~GateTableModel(); @@ -99,19 +99,19 @@ public: protected: void maxCapSlew(float in_slew, - const Pvt *pvt, - float &slew, - float &cap) const; + const Pvt *pvt, + float &slew, + float &cap) const; void setIsScaled(bool is_scaled) override; float axisValue(const TableAxis *axis, - float load_cap, - float in_slew, - float related_out_cap) const; + float load_cap, + float in_slew, + float related_out_cap) const; float findValue(const Pvt *pvt, - const TableModel *model, - float in_slew, - float load_cap, - float related_out_cap) const; + const TableModel *model, + float in_slew, + float load_cap, + float related_out_cap) const; std::string reportTableLookup(const char *result_name, const Pvt *pvt, const TableModel *model, @@ -120,13 +120,13 @@ protected: float related_out_cap, int digits) const; void findAxisValues(const TableModel *model, - float in_slew, - float load_cap, - float related_out_cap, - // Return values. - float &axis_value1, - float &axis_value2, - float &axis_value3) const; + float in_slew, + float load_cap, + float related_out_cap, + // Return values. + float &axis_value1, + float &axis_value2, + float &axis_value3) const; static bool checkAxis(const TableAxis *axis); TableModel *delay_model_; @@ -140,9 +140,9 @@ protected: class CheckTableModel : public CheckTimingModel { public: - explicit CheckTableModel(LibertyCell *cell, - TableModel *model, - TableModel *sigma_models[EarlyLate::index_count]); + CheckTableModel(LibertyCell *cell, + TableModel *model, + TableModel *sigma_models[EarlyLate::index_count]); virtual ~CheckTableModel(); ArcDelay checkDelay(const Pvt *pvt, float from_slew, @@ -165,21 +165,21 @@ public: protected: void setIsScaled(bool is_scaled) override; float findValue(const Pvt *pvt, - const TableModel *model, - float from_slew, - float to_slew, - float related_out_cap) const; + const TableModel *model, + float from_slew, + float to_slew, + float related_out_cap) const; void findAxisValues(float from_slew, - float to_slew, - float related_out_cap, - // Return values. - float &axis_value1, - float &axis_value2, - float &axis_value3) const; + float to_slew, + float related_out_cap, + // Return values. + float &axis_value1, + float &axis_value2, + float &axis_value3) const; float axisValue(const TableAxis *axis, - float load_cap, - float in_slew, - float related_out_cap) const; + float load_cap, + float in_slew, + float related_out_cap) const; std::string reportTableDelay(const char *result_name, const Pvt *pvt, const TableModel *model, @@ -200,8 +200,8 @@ class TableModel public: TableModel(TablePtr table, TableTemplate *tbl_template, - ScaleFactorType scale_factor_type, - const RiseFall *rf); + ScaleFactorType scale_factor_type, + const RiseFall *rf); void setScaleFactorType(ScaleFactorType type); int order() const; TableTemplate *tblTemplate() const { return tbl_template_; } @@ -214,14 +214,14 @@ public: size_t index3) const; // Table interpolated lookup. float findValue(float value1, - float value2, - float value3) const; + float value2, + float value3) const; // Table interpolated lookup with scale factor. float findValue(const LibertyCell *cell, - const Pvt *pvt, - float value1, - float value2, - float value3) const; + const Pvt *pvt, + float value1, + float value2, + float value3) const; std::string reportValue(const char *result_name, const LibertyCell *cell, const Pvt *pvt, @@ -236,7 +236,7 @@ public: protected: float scaleFactor(const LibertyCell *cell, - const Pvt *pvt) const; + const Pvt *pvt) const; std::string reportPvtScaleFactor(const LibertyCell *cell, const Pvt *pvt, int digits) const; @@ -266,15 +266,15 @@ public: size_t axis_idx3) const = 0; // Table interpolated lookup. virtual float findValue(float axis_value1, - float axis_value2, - float axis_value3) const = 0; + float axis_value2, + float axis_value3) const = 0; // Table interpolated lookup with scale factor. float findValue(const LibertyLibrary *library, - const LibertyCell *cell, - const Pvt *pvt, - float axis_value1, - float axis_value2, - float axis_value3) const; + const LibertyCell *cell, + const Pvt *pvt, + float axis_value1, + float axis_value2, + float axis_value3) const; virtual std::string reportValue(const char *result_name, const LibertyCell *cell, const Pvt *pvt, @@ -285,7 +285,7 @@ public: const Unit *table_unit, int digits) const = 0; virtual void report(const Units *units, - Report *report) const = 0; + Report *report) const = 0; }; // Zero dimension (scalar) table. @@ -323,7 +323,7 @@ class Table1 : public Table public: Table1(); Table1(FloatSeq *values, - TableAxisPtr axis1); + TableAxisPtr axis1); virtual ~Table1(); Table1(Table1 &&table); Table1(const Table1 &table); @@ -370,8 +370,8 @@ class Table2 : public Table { public: Table2(FloatTable *values, - TableAxisPtr axis1, - TableAxisPtr axis2); + TableAxisPtr axis1, + TableAxisPtr axis2); virtual ~Table2(); int order() const override { return 2; } const TableAxis *axis1() const override { return axis1_.get(); } @@ -414,9 +414,9 @@ class Table3 : public Table2 { public: Table3(FloatTable *values, - TableAxisPtr axis1, - TableAxisPtr axis2, - TableAxisPtr axis3); + TableAxisPtr axis1, + TableAxisPtr axis2, + TableAxisPtr axis3); virtual ~Table3() {} int order() const override { return 3; } const TableAxis *axis1() const override { return axis1_.get(); } @@ -449,7 +449,7 @@ class TableAxis { public: TableAxis(TableAxisVariable variable, - FloatSeq *values); + FloatSeq *values); ~TableAxis(); TableAxisVariable variable() const { return variable_; } const char *variableString() const; diff --git a/include/sta/TclTypeHelpers.hh b/include/sta/TclTypeHelpers.hh index a70f8400..e521c4a9 100644 --- a/include/sta/TclTypeHelpers.hh +++ b/include/sta/TclTypeHelpers.hh @@ -36,15 +36,21 @@ namespace sta { StringSet * tclListSetConstChar(Tcl_Obj *const source, - Tcl_Interp *interp); + Tcl_Interp *interp); StringSeq * tclListSeqConstChar(Tcl_Obj *const source, - Tcl_Interp *interp); + Tcl_Interp *interp); +StdStringSeq +tclListSeqStdString(Tcl_Obj *const source, + Tcl_Interp *interp); +StdStringSeq * +tclListSeqStdStringPtr(Tcl_Obj *const source, + Tcl_Interp *interp); StdStringSet * tclListSetStdString(Tcl_Obj *const source, - Tcl_Interp *interp); + Tcl_Interp *interp); void tclArgError(Tcl_Interp *interp, @@ -54,10 +60,10 @@ tclArgError(Tcl_Interp *interp, void objectListNext(const char *list, - const char *type, - // Return values. - bool &type_match, - const char *&next); + const char *type, + // Return values. + bool &type_match, + const char *&next); Tcl_Obj * tclArcDcalcArg(ArcDcalcArg &gate, diff --git a/include/sta/TimingArc.hh b/include/sta/TimingArc.hh index 3884cbd3..080cf84d 100644 --- a/include/sta/TimingArc.hh +++ b/include/sta/TimingArc.hh @@ -25,8 +25,9 @@ #pragma once #include +#include +#include -#include "Vector.hh" #include "Transition.hh" #include "Delay.hh" #include "LibertyClass.hh" @@ -36,11 +37,11 @@ namespace sta { class TimingArcAttrs; class WireTimingArc; class GateTableModel; -class DcalcAnalysisPt; +class Scene; -typedef int TimingArcIndex; -typedef Vector TimingArcSeq; -typedef Map ScaledTimingModelMap; +using TimingArcIndex = int; +using TimingArcSeq = std::vector; +using ScaledTimingModelMap = std::map; enum class TimingType { clear, @@ -117,7 +118,7 @@ public: void setModeValue(const char *value); TimingModel *model(const RiseFall *rf) const; void setModel(const RiseFall *rf, - TimingModel *model); + TimingModel *model); float ocvArcDepth() const { return ocv_arc_depth_; } void setOcvArcDepth(float depth); @@ -143,11 +144,11 @@ class TimingArcSet { public: TimingArcSet(LibertyCell *cell, - LibertyPort *from, - LibertyPort *to, - LibertyPort *related_out, - const TimingRole *role, - TimingArcAttrsPtr attrs); + LibertyPort *from, + LibertyPort *to, + LibertyPort *related_out, + const TimingRole *role, + TimingArcAttrsPtr attrs); virtual ~TimingArcSet(); LibertyCell *libertyCell() const; LibertyPort *from() const { return from_; } @@ -162,9 +163,9 @@ public: TimingArcSeq &arcs() { return arcs_; } // Return 1 or 2 arcs matching from transition. void arcsFrom(const RiseFall *from_rf, - // Return values. - TimingArc *&arc1, - TimingArc *&arc2) const; + // Return values. + TimingArc *&arc1, + TimingArc *&arc2) const; TimingArc *arcTo(const RiseFall *to_rf) const; const TimingArcSeq &arcs() const { return arcs_; } TimingArcIndex addTimingArc(TimingArc *arc); @@ -186,15 +187,13 @@ public: const char *modeValue() const { return attrs_->modeValue(); } // Timing arc set index in cell. TimingArcIndex index() const { return index_; } - bool isDisabledConstraint() const { return is_disabled_constraint_; } - void setIsDisabledConstraint(bool is_disabled); // OCV arc depth from timing/cell/library. float ocvArcDepth() const; static bool equiv(const TimingArcSet *set1, - const TimingArcSet *set2); + const TimingArcSet *set2); static bool less(const TimingArcSet *set1, - const TimingArcSet *set2); + const TimingArcSet *set2); static void init(); static void destroy(); @@ -217,7 +216,6 @@ protected: TimingArcSeq arcs_; bool is_cond_default_; unsigned index_; - bool is_disabled_constraint_; TimingArc *from_arc1_[RiseFall::index_count]; TimingArc *from_arc2_[RiseFall::index_count]; TimingArc *to_arc_[RiseFall::index_count]; @@ -232,9 +230,9 @@ class TimingArc { public: TimingArc(TimingArcSet *set, - const Transition *from_rf, - const Transition *to_rf, - TimingModel *model); + const Transition *from_rf, + const Transition *to_rf, + TimingModel *model); ~TimingArc(); std::string to_string() const; LibertyPort *from() const { return set_->from(); } @@ -247,24 +245,28 @@ public: // Index in TimingArcSet. unsigned index() const { return index_; } TimingModel *model() const { return model_; } - GateTimingModel *gateModel(const DcalcAnalysisPt *dcalc_ap) const; - CheckTimingModel *checkModel(const DcalcAnalysisPt *dcalc_ap) const; + GateTimingModel *gateModel(const Scene *scene, + const MinMax *min_max) const; + CheckTimingModel *checkModel(const Scene *scene, + const MinMax *min_max) const; GateTableModel *gateTableModel() const; - GateTableModel *gateTableModel(const DcalcAnalysisPt *dcalc_ap) const; - const TimingArc *cornerArc(int ap_index) const; - void setCornerArc(TimingArc *corner_arc, - int ap_index); + GateTableModel *gateTableModel(const Scene *scene, + const MinMax *min_max) const; + const TimingArc *sceneArc(int ap_index) const; + void setSceneArc(TimingArc *scene_arc, + int ap_index); float driveResistance() const; ArcDelay intrinsicDelay() const; static bool equiv(const TimingArc *arc1, - const TimingArc *arc2); + const TimingArc *arc2); protected: - TimingModel *model(const DcalcAnalysisPt *dcalc_ap) const; + TimingModel *model(const Scene *scene, + const MinMax *min_max) const; void setIndex(unsigned index); void addScaledModel(const OperatingConditions *op_cond, - TimingModel *scaled_model); + TimingModel *scaled_model); TimingArcSet *set_; const Transition *from_rf_; @@ -272,7 +274,7 @@ protected: unsigned index_; TimingModel *model_; ScaledTimingModelMap *scaled_models_; - Vector corner_arcs_; + std::vector scene_arcs_; private: friend class LibertyLibrary; diff --git a/include/sta/TimingModel.hh b/include/sta/TimingModel.hh index 3ee8cab8..c9f5ee8a 100644 --- a/include/sta/TimingModel.hh +++ b/include/sta/TimingModel.hh @@ -50,12 +50,12 @@ public: GateTimingModel(LibertyCell *cell); // Gate delay calculation. virtual void gateDelay(const Pvt *pvt, - float in_slew, - float load_cap, - bool pocv_enabled, - // Return values. - ArcDelay &gate_delay, - Slew &drvr_slew) const = 0; + float in_slew, + float load_cap, + bool pocv_enabled, + // Return values. + ArcDelay &gate_delay, + Slew &drvr_slew) const = 0; virtual std::string reportGateDelay(const Pvt *pvt, float in_slew, float load_cap, diff --git a/include/sta/TimingRole.hh b/include/sta/TimingRole.hh index b9456cc1..3621f63c 100644 --- a/include/sta/TimingRole.hh +++ b/include/sta/TimingRole.hh @@ -33,7 +33,7 @@ namespace sta { class TimingRole; -typedef std::map TimingRoleMap; +using TimingRoleMap = std::map; class TimingRole { @@ -74,10 +74,10 @@ public: bool isTimingCheck() const { return is_timing_check_; } // TIming check but not width or period. bool isTimingCheckBetween() const; - bool isAsyncTimingCheck() const; - bool isNonSeqTimingCheck() const { return is_non_seq_check_; } - bool isDataCheck() const; - bool isLatchDtoQ() const; + [[nodiscard]] bool isAsyncTimingCheck() const; + [[nodiscard]] bool isNonSeqTimingCheck() const { return is_non_seq_check_; } + [[nodiscard]] bool isDataCheck() const; + [[nodiscard]] bool isLatchDtoQ() const; const TimingRole *genericRole() const; const TimingRole *sdfRole() const; // Timing check data path min/max. @@ -88,18 +88,18 @@ public: // Pseudo role to match sdf IOPATH. static const TimingRole *sdfIopath() { return &sdf_iopath_; } static bool less(const TimingRole *role1, - const TimingRole *role2); + const TimingRole *role2); static const int index_max = 26; private: TimingRole(const char *name, - bool is_sdf_iopath, - bool is_timing_check, - bool is_non_seq_check, - const MinMax *path_min_max, - // generic_type = nullptr means type is the same as this. - const TimingRole *generic_role, - int index); + bool is_sdf_iopath, + bool is_timing_check, + bool is_non_seq_check, + const MinMax *path_min_max, + // generic_type = nullptr means type is the same as this. + const TimingRole *generic_role, + int index); const std::string name_; bool is_timing_check_; diff --git a/include/sta/TokenParser.hh b/include/sta/TokenParser.hh index f5f1bb20..a339a6a8 100644 --- a/include/sta/TokenParser.hh +++ b/include/sta/TokenParser.hh @@ -37,7 +37,7 @@ class TokenParser { public: TokenParser(const char *str, - const char *delimiters); + const char *delimiters); bool hasNext(); char *next(); diff --git a/include/sta/Transition.hh b/include/sta/Transition.hh index c7a490a8..39190c6c 100644 --- a/include/sta/Transition.hh +++ b/include/sta/Transition.hh @@ -26,9 +26,9 @@ #include #include +#include #include "Iterator.hh" -#include "Map.hh" #include "StringUtil.hh" namespace sta { @@ -37,7 +37,7 @@ class Transition; class RiseFall; class RiseFallBoth; -typedef Map TransitionMap; +using TransitionMap = std::map; // Rise/fall transition. class RiseFall @@ -164,9 +164,9 @@ public: private: Transition(const char *name, - const char *init_final, - const RiseFall *as_rise_fall, - int sdf_triple_index); + const char *init_final, + const RiseFall *as_rise_fall, + int sdf_triple_index); const std::string name_; const std::string init_final_; diff --git a/include/sta/Units.hh b/include/sta/Units.hh index 8b54be5f..79bf472a 100644 --- a/include/sta/Units.hh +++ b/include/sta/Units.hh @@ -59,7 +59,7 @@ public: const char *asString(float value) const; const char *asString(double value) const; const char *asString(float value, - int digits) const; + int digits) const; private: void setScaleAbbrevSuffix(); diff --git a/include/sta/UnorderedMap.hh b/include/sta/UnorderedMap.hh deleted file mode 100644 index 316a254f..00000000 --- a/include/sta/UnorderedMap.hh +++ /dev/null @@ -1,203 +0,0 @@ -// OpenSTA, Static Timing Analyzer -// Copyright (c) 2025, Parallax Software, Inc. -// -// This program is free software: you can redistribute it and/or modify -// it under the terms of the GNU General Public License as published by -// the Free Software Foundation, either version 3 of the License, or -// (at your option) any later version. -// -// This program is distributed in the hope that it will be useful, -// but WITHOUT ANY WARRANTY; without even the implied warranty of -// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -// GNU General Public License for more details. -// -// You should have received a copy of the GNU General Public License -// along with this program. If not, see . -// -// The origin of this software must not be misrepresented; you must not -// claim that you wrote the original software. -// -// Altered source versions must be plainly marked as such, and must not be -// misrepresented as being the original software. -// -// This notice may not be removed or altered from any source distribution. - -#pragma once - -#include -#include - -namespace sta { - -// Add convenience functions around STL container. -template , class EQUAL = std::equal_to> -class UnorderedMap : public std::unordered_map -{ -public: - UnorderedMap() : - std::unordered_map() - { - } - - explicit UnorderedMap(const HASH &hash) : - std::unordered_map(0, hash, std::equal_to()) - { - } - - explicit UnorderedMap(size_t size, - const HASH &hash, - const EQUAL &equal) : - std::unordered_map(size, hash, equal) - { - } - - // Find out if key is in the set. - bool - hasKey(const KEY key) const - { - return this->find(key) != this->end(); - } - - // Find the value corresponding to key. - VALUE - findKey(const KEY key) const - { - auto find_iter = this->find(key); - if (find_iter != this->end()) - return find_iter->second; - else - return nullptr; - } - void - findKey(const KEY key, - // Return Values. - VALUE &value, - bool &exists) const - { - auto find_iter = this->find(key); - if (find_iter != this->end()) { - value = find_iter->second; - exists = true; - } - else - exists = false; - } - void - findKey(const KEY &key, - // Return Values. - KEY &map_key, - VALUE &value, - bool &exists) const - { - auto find_iter = this->find(key); - if (find_iter != this->end()) { - map_key = find_iter->first; - value = find_iter->second; - exists = true; - } - else - exists = false; - } - - void - insert(const KEY &key, - VALUE value) - { - this->operator[](key) = value; - } - - void - deleteContents() - { - Iterator iter(this); - while (iter.hasNext()) - delete iter.next(); - } - - void - deleteKeysContents() - { - Iterator iter(this); - while (iter.hasNext()) { - KEY key; - VALUE value; - iter.next(key, value); - delete key; - delete value; - } - } - - void - deleteArrayContents() - { - Iterator iter(this); - while (iter.hasNext()) - delete [] iter.next(); - } - - void - deleteContentsClear() - { - deleteContents(); - std::unordered_map::clear(); - } - - // Java style container itererator - // Map::Iterator iter(map); - // while (iter.hasNext()) { - // Value *v = iter.next(); - // } - class Iterator - { - public: - Iterator() : container_(nullptr) {} - explicit Iterator(std::unordered_map *container) : - container_(container) - { if (container_ != nullptr) iter_ = container_->begin(); } - explicit Iterator(std::unordered_map &container) : - container_(&container) - { if (container_ != nullptr) iter_ = container_->begin(); } - void init(std::unordered_map *container) - { container_ = container; if (container_ != nullptr) iter_=container_->begin();} - void init(std::unordered_map &container) - { container_ = &container; if (container_ != nullptr) iter_=container_->begin();} - bool hasNext() { return container_ != nullptr && iter_ != container_->end(); } - VALUE next() { return iter_++->second; } - void next(KEY &key, - VALUE &value) - { key = iter_->first; value = iter_->second; iter_++; } - std::unordered_map *container() { return container_; } - - private: - std::unordered_map *container_; - typename std::unordered_map::iterator iter_; - }; - - class ConstIterator - { - public: - ConstIterator() : container_(nullptr) {} - explicit ConstIterator(const std::unordered_map *container) : - container_(container) - { if (container_ != nullptr) iter_ = container_->begin(); } - explicit ConstIterator(const std::unordered_map &container) : - container_(&container) - { if (container_ != nullptr) iter_ = container_->begin(); } - void init(const std::unordered_map *container) - { container_ = container; if (container_ != nullptr) iter_=container_->begin();} - void init(const std::unordered_map &container) - { container_ = &container; if (container_ != nullptr) iter_=container_->begin();} - bool hasNext() { return container_ != nullptr && iter_ != container_->end(); } - VALUE next() { return iter_++->second; } - void next(KEY &key, - VALUE &value) - { key = iter_->first; value = iter_->second; iter_++; } - const std::unordered_map *container() { return container_; } - - private: - const std::unordered_map *container_; - typename std::unordered_map::const_iterator iter_; - }; -}; - -} // namespace diff --git a/include/sta/UnorderedSet.hh b/include/sta/UnorderedSet.hh deleted file mode 100644 index 2d859815..00000000 --- a/include/sta/UnorderedSet.hh +++ /dev/null @@ -1,139 +0,0 @@ -// OpenSTA, Static Timing Analyzer -// Copyright (c) 2025, Parallax Software, Inc. -// -// This program is free software: you can redistribute it and/or modify -// it under the terms of the GNU General Public License as published by -// the Free Software Foundation, either version 3 of the License, or -// (at your option) any later version. -// -// This program is distributed in the hope that it will be useful, -// but WITHOUT ANY WARRANTY; without even the implied warranty of -// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -// GNU General Public License for more details. -// -// You should have received a copy of the GNU General Public License -// along with this program. If not, see . -// -// The origin of this software must not be misrepresented; you must not -// claim that you wrote the original software. -// -// Altered source versions must be plainly marked as such, and must not be -// misrepresented as being the original software. -// -// This notice may not be removed or altered from any source distribution. - -#pragma once - -#include -#include - -namespace sta { - -// Add convenience functions around STL container. -template , class EQUAL = std::equal_to > -class UnorderedSet : public std::unordered_set -{ -public: - UnorderedSet() : - std::unordered_set() - { - } - - explicit UnorderedSet(size_t size) : - std::unordered_set(size) - { - } - - explicit UnorderedSet(size_t size, - const HASH &hash, - const EQUAL &equal) : - std::unordered_set(size, hash, equal) - { - } - - // Find out if key is in the set. - bool - hasKey(const KEY key) const - { - return this->find(key) != this->end(); - } - - // Find the value corresponding to key. - KEY - findKey(const KEY key) const - { - auto find_iter = this->find(key); - if (find_iter != this->end()) - return *find_iter; - else - return nullptr; - } - - void - deleteContents() - { - Iterator iter(this); - while (iter.hasNext()) - delete iter.next(); - } - - void - deleteContentsClear() - { - deleteContents(); - std::unordered_set::clear(); - } - - // Java style container itererator - // Set::Iterator iter(set); - // while (iter.hasNext()) { - // Value *v = iter.next(); - // } - class Iterator - { - public: - Iterator() : container_(nullptr) {} - explicit Iterator(std::unordered_set *container) : - container_(container) - { if (container_ != nullptr) iter_ = container_->begin(); } - explicit Iterator(std::unordered_set &container) : - container_(&container) - { if (container_ != nullptr) iter_ = container_->begin(); } - void init(std::unordered_set *container) - { container_ = container; if (container_ != nullptr) iter_=container_->begin();} - void init(std::unordered_set &container) - { container_ = &container; if (container_ != nullptr) iter_=container_->begin();} - bool hasNext() { return container_ != nullptr && iter_ != container_->end(); } - KEY next() { return *iter_++; } - std::unordered_set *container() { return container_; } - - private: - std::unordered_set *container_; - typename std::unordered_set::iterator iter_; - }; - - class ConstIterator - { - public: - ConstIterator() : container_(nullptr) {} - explicit ConstIterator(const std::unordered_set *container) : - container_(container) - { if (container_ != nullptr) iter_ = container_->begin(); } - explicit ConstIterator(const std::unordered_set &container) : - container_(&container) - { if (container_ != nullptr) iter_ = container_->begin(); } - void init(const std::unordered_set *container) - { container_ = container; if (container_ != nullptr) iter_=container_->begin();} - void init(const std::unordered_set &container) - { container_ = &container; if (container_ != nullptr) iter_=container_->begin();} - bool hasNext() { return container_ != nullptr && iter_ != container_->end(); } - KEY next() { return iter_++->second; } - const std::unordered_set *container() { return container_; } - - private: - const std::unordered_set *container_; - typename std::unordered_set::const_iterator iter_; - }; -}; - -} // namespace diff --git a/include/sta/Variables.hh b/include/sta/Variables.hh index 1d60408e..2bd99990 100644 --- a/include/sta/Variables.hh +++ b/include/sta/Variables.hh @@ -54,10 +54,6 @@ public: // Enable/disable timing from bidirect pins back into the instance. bool bidirectInstPathsEnabled() const { return bidirect_inst_paths_enabled_; } void setBidirectInstPathsEnabled(bool enabled); - // TCL variable sta_bidirect_net_paths_enabled. - // Enable/disable timing from bidirect driver pins to their own loads. - bool bidirectNetPathsEnabled() const { return bidirect_net_paths_enabled_; } - void setBidirectNetPathsEnabled(bool enabled); // TCL variable sta_recovery_removal_checks_enabled. bool recoveryRemovalChecksEnabled() const { return recovery_removal_checks_enabled_; } void setRecoveryRemovalChecksEnabled(bool enabled); @@ -85,7 +81,6 @@ private: bool propagate_gated_clock_enable_; bool preset_clr_arcs_enabled_; bool cond_default_arcs_enabled_; - bool bidirect_net_paths_enabled_; bool bidirect_inst_paths_enabled_; bool recovery_removal_checks_enabled_; bool gated_clk_checks_enabled_; diff --git a/include/sta/Vector.hh b/include/sta/Vector.hh deleted file mode 100644 index 001b3713..00000000 --- a/include/sta/Vector.hh +++ /dev/null @@ -1,146 +0,0 @@ -// OpenSTA, Static Timing Analyzer -// Copyright (c) 2025, Parallax Software, Inc. -// -// This program is free software: you can redistribute it and/or modify -// it under the terms of the GNU General Public License as published by -// the Free Software Foundation, either version 3 of the License, or -// (at your option) any later version. -// -// This program is distributed in the hope that it will be useful, -// but WITHOUT ANY WARRANTY; without even the implied warranty of -// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -// GNU General Public License for more details. -// -// You should have received a copy of the GNU General Public License -// along with this program. If not, see . -// -// The origin of this software must not be misrepresented; you must not -// claim that you wrote the original software. -// -// Altered source versions must be plainly marked as such, and must not be -// misrepresented as being the original software. -// -// This notice may not be removed or altered from any source distribution. - -#pragma once - -#include -#include - -namespace sta { - -// Add convenience functions around STL container. -template -class Vector : public std::vector -{ -public: - Vector() : std::vector() {} - Vector(size_t n) : std::vector(n) {} - Vector(size_t n, const OBJ &obj) : std::vector(n, obj) {} - - // Erase an object from the vector (slow). - void - eraseObject(OBJ obj) - { - auto find_iter = std::find(this->begin(), this->end(), obj); - if (find_iter != this->end()) - this->erase(find_iter); - } - - void - deleteContents() - { - Iterator iter(this); - while (iter.hasNext()) - delete iter.next(); - } - - void - deleteContentsClear() - { - deleteContents(); - this->clear(); - } - - void - deleteArrayContentsClear() - { - Iterator iter(this); - while (iter.hasNext()) - delete [] iter.next(); - this->clear(); - } - - // Java style container itererator - // Vector::Iterator iter(vector); - // while (iter.hasNext()) { - // Object *v = iter.next(); - // } - class Iterator - { - public: - Iterator() : container_(nullptr) {} - Iterator(std::vector *container) : - container_(container) - { if (container) iter_ = container->begin(); } - Iterator(std::vector &container) : - container_(&container) - { if (container_) iter_ = container_->begin(); } - void init() { iter_ = container_->begin(); } - void init(std::vector *container) - { container_ = container; if (container_) iter_=container_->begin(); } - void init(std::vector &container) - { container_ = &container; iter_ = container_->begin(); } - bool hasNext() { return container_ && iter_ != container_->end(); } - OBJ& next() { return *iter_++; } - std::vector *container() { return container_; } - - private: - std::vector *container_; - typename std::vector::iterator iter_; - }; - - class ConstIterator - { - public: - ConstIterator() : container_(nullptr) {} - ConstIterator(const std::vector *container) : - container_(container) - { if (container_) iter_ = container_->begin(); } - ConstIterator(const std::vector &container) : - container_(&container) - { iter_ = container_->begin(); } - void init() { iter_ = container_->begin(); } - void init(const std::vector *container) - { container_ = container; if (container_) iter_=container_->begin();} - void init(const std::vector &container) - { container_ = &container; if (container_) iter_=container_->begin();} - bool hasNext() { return container_ && iter_ != container_->end(); } - const OBJ& next() { return *iter_++; } - const std::vector *container() { return container_; } - - private: - const std::vector *container_; - typename std::vector::const_iterator iter_; - }; -}; - -template -void -sort(Vector &seq, SortCmp cmp) -{ - // For some strange reason std::sort goes off into never never land - // when optimization is turned on in gcc. - std::stable_sort(seq.begin(), seq.end(), cmp); -} - -template -void -sort(Vector *seq, SortCmp cmp) -{ - // For some strange reason std::sort goes off into never never land - // when optimization is turned on in gcc. - std::stable_sort(seq->begin(), seq->end(), cmp); -} - -} // namespace sta diff --git a/include/sta/VectorMap.hh b/include/sta/VectorMap.hh new file mode 100644 index 00000000..33cc5080 --- /dev/null +++ b/include/sta/VectorMap.hh @@ -0,0 +1,494 @@ +// OpenSTA, Static Timing Analyzer +// Copyright (c) 2025, Parallax Software, Inc. +// +// This program is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see . +// +// The origin of this software must not be misrepresented; you must not +// claim that you wrote the original software. +// +// Altered source versions must be plainly marked as such, and must not be +// misrepresented as being the original software. +// +// This notice may not be removed or altered from any source distribution. + +#pragma once + +#include +#include +#include +#include +#include +#include + +namespace sta { + +// Proxy reference type that mimics std::pair +// and supports structured bindings via tuple interface +template +class VectorMapReferenceProxy { +public: + // Constructor that stores pointer to underlying pair (non-const) + VectorMapReferenceProxy(std::pair* ptr) : pair_ptr_(ptr) {} + + // Constructor that stores pointer to underlying pair (const) + VectorMapReferenceProxy(const std::pair* ptr) + : pair_ptr_(const_cast*>(ptr)) {} + + // Access members like std::pair (for compatibility) + const Key& first() const { return pair_ptr_->first; } + Value& second() { return pair_ptr_->second; } + const Value& second() const { return pair_ptr_->second; } + + // Tuple-like access for structured bindings + template + auto get() const { + if constexpr (I == 0) return pair_ptr_->first; + if constexpr (I == 1) return pair_ptr_->second; + } + + template + auto get() { + if constexpr (I == 0) return pair_ptr_->first; + if constexpr (I == 1) return pair_ptr_->second; + } + + // Assignment (only second can be assigned) + VectorMapReferenceProxy& operator=(const std::pair& other) { + pair_ptr_->second = other.second; + return *this; + } + +private: + std::pair* pair_ptr_; +}; + +// VectorMap: A map implementation using a sorted vector with binary search. +// This provides O(log n) lookup, O(n) insertion/deletion, but better cache +// locality than std::map for small to medium-sized maps. +template > +class VectorMap { +public: + using key_type = Key; + using mapped_type = Value; + using value_type = std::pair; + using key_compare = Compare; + using size_type = size_t; + using difference_type = ptrdiff_t; + using reference = value_type&; + using const_reference = const value_type&; + using pointer = value_type*; + using const_pointer = const value_type*; + +private: + // Internal storage: vector of pairs + // We use std::pair internally, but expose it as + // std::pair through iterators + using storage_type = std::vector>; + storage_type data_; + Compare comp_; + + // Helper to find insertion point using binary search + typename storage_type::iterator findInsertPos(const Key& key) { + return std::lower_bound(data_.begin(), data_.end(), key, + [this](const auto& pair, const Key& k) { + return comp_(pair.first, k); + }); + } + + typename storage_type::const_iterator findInsertPos(const Key& key) const { + return std::lower_bound(data_.begin(), data_.end(), key, + [this](const auto& pair, const Key& k) { + return comp_(pair.first, k); + }); + } + + // Iterator adapter to expose const Key in pair + // Uses a proxy reference to safely expose std::pair + template + class IteratorAdapter { + public: + using iterator_category = std::random_access_iterator_tag; + using value_type = std::pair; + using difference_type = ptrdiff_t; + using proxy_type = VectorMapReferenceProxy; + + using reference = proxy_type; + using pointer = proxy_type*; + + IteratorAdapter() = default; + explicit IteratorAdapter(BaseIter it) : it_(it) {} + + // Conversion constructor: allow conversion from non-const to const iterator + template + IteratorAdapter(const IteratorAdapter& other, + typename std::enable_if< + std::is_convertible_v + >::type* = nullptr) + : it_(other.base()) {} + + reference operator*() { + return proxy_type(&*it_); + } + + reference operator*() const { + return proxy_type(&*it_); + } + + // For operator->, we return a pointer to a temporary + // This is not ideal but necessary for compatibility + class arrow_proxy { + public: + explicit arrow_proxy(const proxy_type& ref) + : value_(ref.first(), ref.second()) {} + value_type* operator->() { return &value_; } + private: + value_type value_; + }; + + arrow_proxy operator->() { + return arrow_proxy(operator*()); + } + + arrow_proxy operator->() const { + return arrow_proxy(operator*()); + } + + // Assignment operator: allow assignment from non-const to const iterator + template + typename std::enable_if< + std::is_convertible_v, + IteratorAdapter& + >::type + operator=(const IteratorAdapter& other) { + it_ = other.base(); + return *this; + } + + IteratorAdapter& operator++() { + ++it_; + return *this; + } + + IteratorAdapter operator++(int) { + IteratorAdapter tmp = *this; + ++it_; + return tmp; + } + + IteratorAdapter& operator--() { + --it_; + return *this; + } + + IteratorAdapter operator--(int) { + IteratorAdapter tmp = *this; + --it_; + return tmp; + } + + IteratorAdapter& operator+=(difference_type n) { + it_ += n; + return *this; + } + + IteratorAdapter& operator-=(difference_type n) { + it_ -= n; + return *this; + } + + IteratorAdapter operator+(difference_type n) const { + return IteratorAdapter(it_ + n); + } + + IteratorAdapter operator-(difference_type n) const { + return IteratorAdapter(it_ - n); + } + + difference_type operator-(const IteratorAdapter& other) const { + return it_ - other.it_; + } + + reference operator[](difference_type n) { + return proxy_type(&it_[n]); + } + + reference operator[](difference_type n) const { + return proxy_type(&it_[n]); + } + + bool operator==(const IteratorAdapter& other) const { + return it_ == other.it_; + } + + bool operator!=(const IteratorAdapter& other) const { + return it_ != other.it_; + } + + bool operator<(const IteratorAdapter& other) const { + return it_ < other.it_; + } + + bool operator<=(const IteratorAdapter& other) const { + return it_ <= other.it_; + } + + bool operator>(const IteratorAdapter& other) const { + return it_ > other.it_; + } + + bool operator>=(const IteratorAdapter& other) const { + return it_ >= other.it_; + } + + BaseIter base() const { return it_; } + + private: + BaseIter it_; + }; + +public: + using iterator = IteratorAdapter; + using const_iterator = IteratorAdapter; + using reverse_iterator = std::reverse_iterator; + using const_reverse_iterator = std::reverse_iterator; + + VectorMap() = default; + explicit VectorMap(const Compare& comp) : comp_(comp) {} + + template + VectorMap(InputIt first, InputIt last, const Compare& comp = Compare()) + : comp_(comp) { + for (; first != last; ++first) { + insert(*first); + } + } + + VectorMap(std::initializer_list init, + const Compare& comp = Compare()) + : comp_(comp) { + for (const auto& pair : init) { + insert(pair); + } + } + + // Element access + Value& operator[](const Key& key) { + auto it = findInsertPos(key); + if (it != data_.end() && !comp_(key, it->first)) { + // Key exists + return it->second; + } else { + // Key doesn't exist, insert it + return data_.insert(it, std::make_pair(key, Value{}))->second; + } + } + + Value& at(const Key& key) { + auto it = findInsertPos(key); + if (it != data_.end() && !comp_(key, it->first)) { + return it->second; + } + throw std::out_of_range("VectorMap::at"); + } + + const Value& at(const Key& key) const { + auto it = findInsertPos(key); + if (it != data_.end() && !comp_(key, it->first)) { + return it->second; + } + throw std::out_of_range("VectorMap::at"); + } + + // Lookup + bool contains(const Key& key) const { + auto it = findInsertPos(key); + return it != data_.end() && !comp_(key, it->first); + } + + iterator find(const Key& key) { + auto it = findInsertPos(key); + if (it != data_.end() && !comp_(key, it->first)) { + return iterator(it); + } + return end(); + } + + const_iterator find(const Key& key) const { + auto it = findInsertPos(key); + if (it != data_.end() && !comp_(key, it->first)) { + return const_iterator(it); + } + return end(); + } + + size_type count(const Key& key) const { + return contains(key) ? 1 : 0; + } + + // Modifiers + std::pair insert(const value_type& value) { + auto it = findInsertPos(value.first); + if (it != data_.end() && !comp_(value.first, it->first)) { + // Key already exists + return std::make_pair(iterator(it), false); + } else { + // Insert new key-value pair + it = data_.insert(it, std::make_pair(value.first, value.second)); + return std::make_pair(iterator(it), true); + } + } + + std::pair insert(value_type&& value) { + auto it = findInsertPos(value.first); + if (it != data_.end() && !comp_(value.first, it->first)) { + // Key already exists + return std::make_pair(iterator(it), false); + } else { + // Insert new key-value pair + it = data_.insert(it, std::make_pair(std::move(value.first), + std::move(value.second))); + return std::make_pair(iterator(it), true); + } + } + + template + std::pair insert(P&& value) { + return insert(value_type(std::forward

(value))); + } + + template + void insert(InputIt first, InputIt last) { + for (; first != last; ++first) { + insert(*first); + } + } + + void insert(std::initializer_list ilist) { + for (const auto& pair : ilist) { + insert(pair); + } + } + + iterator erase(const_iterator pos) { + return iterator(data_.erase(pos.base())); + } + + iterator erase(const_iterator first, const_iterator last) { + return iterator(data_.erase(first.base(), last.base())); + } + + size_type erase(const Key& key) { + auto it = findInsertPos(key); + if (it != data_.end() && !comp_(key, it->first)) { + data_.erase(it); + return 1; + } + return 0; + } + + void clear() { + data_.clear(); + } + + // Capacity + bool empty() const { + return data_.empty(); + } + + size_type size() const { + return data_.size(); + } + + size_type max_size() const { + return data_.max_size(); + } + + // Iterators + iterator begin() { + return iterator(data_.begin()); + } + + const_iterator begin() const { + return const_iterator(data_.begin()); + } + + const_iterator cbegin() const { + return const_iterator(data_.begin()); + } + + iterator end() { + return iterator(data_.end()); + } + + const_iterator end() const { + return const_iterator(data_.end()); + } + + const_iterator cend() const { + return const_iterator(data_.end()); + } + + reverse_iterator rbegin() { + return reverse_iterator(end()); + } + + const_reverse_iterator rbegin() const { + return const_reverse_iterator(end()); + } + + const_reverse_iterator crbegin() const { + return const_reverse_iterator(end()); + } + + reverse_iterator rend() { + return reverse_iterator(begin()); + } + + const_reverse_iterator rend() const { + return const_reverse_iterator(begin()); + } + + const_reverse_iterator crend() const { + return const_reverse_iterator(begin()); + } + + // Observers + key_compare key_comp() const { + return comp_; + } +}; + +} // namespace sta + +// Specializations for structured bindings support +namespace std { + +template +struct tuple_size> + : std::integral_constant {}; + +template +struct tuple_element> { + static_assert(I < 2, "Index out of bounds for pair"); + using type = std::conditional_t; +}; + +template +struct tuple_element> { + static_assert(I < 2, "Index out of bounds for pair"); + using type = std::conditional_t; +}; + +} // namespace std + diff --git a/include/sta/VerilogReader.hh b/include/sta/VerilogReader.hh index dc76ccc6..2b244d0c 100644 --- a/include/sta/VerilogReader.hh +++ b/include/sta/VerilogReader.hh @@ -25,10 +25,10 @@ #pragma once #include +#include +#include #include "StringSet.hh" -#include "Vector.hh" -#include "Map.hh" #include "NetworkClass.hh" namespace sta { @@ -62,13 +62,13 @@ class VerilogNetPortRef; class VerilogError; class LibertyCell; -typedef Map VerilogModuleMap; -typedef Vector VerilogStmtSeq; -typedef Vector VerilogNetSeq; -typedef Vector VerilogDclArgSeq; -typedef Vector VerilogAttrStmtSeq; -typedef Vector VerilogAttrEntrySeq; -typedef Vector VerilogErrorSeq; +using VerilogModuleMap = std::map; +using VerilogStmtSeq = std::vector; +using VerilogNetSeq = std::vector; +using VerilogDclArgSeq = std::vector; +using VerilogAttrStmtSeq = std::vector; +using VerilogAttrEntrySeq = std::vector; +using VerilogErrorSeq = std::vector; class VerilogReader { @@ -115,47 +115,47 @@ public: VerilogAttrStmtSeq *attr_stmts, const int line); VerilogAssign *makeAssign(VerilogNet *lhs, - VerilogNet *rhs, - int line); + VerilogNet *rhs, + int line); VerilogNetScalar *makeNetScalar(const std::string *name); VerilogNetPortRef *makeNetNamedPortRefScalarNet(const std::string *port_vname); VerilogNetPortRef *makeNetNamedPortRefScalarNet(const std::string *port_name, - const std::string *net_name); + const std::string *net_name); VerilogNetPortRef *makeNetNamedPortRefBitSelect(const std::string *port_name, - const std::string *bus_name, - int index); + const std::string *bus_name, + int index); VerilogNetPortRef *makeNetNamedPortRefScalar(const std::string *port_name, - VerilogNet *net); + VerilogNet *net); VerilogNetPortRef *makeNetNamedPortRefBit(const std::string *port_name, - int index, - VerilogNet *net); + int index, + VerilogNet *net); VerilogNetPortRef *makeNetNamedPortRefPart(const std::string *port_name, - int from_index, - int to_index, - VerilogNet *net); + int from_index, + int to_index, + VerilogNet *net); VerilogNetConcat *makeNetConcat(VerilogNetSeq *nets); VerilogNetConstant *makeNetConstant(const std::string *constant, int line); VerilogNetBitSelect *makeNetBitSelect(const std::string *name, - int index); + int index); VerilogNetPartSelect *makeNetPartSelect(const std::string *name, - int from_index, - int to_index); + int from_index, + int to_index); VerilogModule *module(Cell *cell); Instance *linkNetwork(const char *top_cell_name, - bool make_black_boxes, + bool make_black_boxes, bool delete_modules); const char *filename() const { return filename_.c_str(); } void incrLine(); Report *report() const { return report_; } void error(int id, const char *filename, - int line, - const char *fmt, ...); + int line, + const char *fmt, ...); void warn(int id, const char *filename, - int line, - const char *fmt, ...); + int line, + const char *fmt, ...); const std::string &zeroNetName() const { return zero_net_name_; } const std::string &oneNetName() const { return one_net_name_; } void deleteModules(); @@ -165,95 +165,95 @@ public: protected: void init(const char *filename); void makeCellPorts(Cell *cell, - VerilogModule *module, - VerilogNetSeq *ports); + VerilogModule *module, + VerilogNetSeq *ports); Port *makeCellPort(Cell *cell, - VerilogModule *module, - const std::string &port_name); + VerilogModule *module, + const std::string &port_name); void makeNamedPortRefCellPorts(Cell *cell, - VerilogModule *module, - VerilogNet *mod_port, - StdStringSet &port_names); + VerilogModule *module, + VerilogNet *mod_port, + StdStringSet &port_names); void checkModuleDcls(VerilogModule *module, - std::set &port_names); + std::set &port_names); void makeModuleInstBody(VerilogModule *module, - Instance *inst, - VerilogBindingTbl *bindings, - bool make_black_boxes); + Instance *inst, + VerilogBindingTbl *bindings, + bool make_black_boxes); void makeModuleInstNetwork(VerilogModuleInst *mod_inst, - Instance *parent, - VerilogModule *parent_module, - VerilogBindingTbl *parent_bindings, - bool make_black_boxes); + Instance *parent, + VerilogModule *parent_module, + VerilogBindingTbl *parent_bindings, + bool make_black_boxes); void makeLibertyInst(VerilogLibertyInst *lib_inst, - Instance *parent, - VerilogModule *parent_module, - VerilogBindingTbl *parent_bindings); + Instance *parent, + VerilogModule *parent_module, + VerilogBindingTbl *parent_bindings); void bindGlobalNets(VerilogBindingTbl *bindings); void makeNamedInstPins1(Cell *cell, - Instance *inst, - VerilogModuleInst *mod_inst, - VerilogBindingTbl *bindings, - Instance *parent, - VerilogBindingTbl *parent_bindings, - bool is_leaf); + Instance *inst, + VerilogModuleInst *mod_inst, + VerilogBindingTbl *bindings, + Instance *parent, + VerilogBindingTbl *parent_bindings, + bool is_leaf); void makeNamedInstPins(Cell *cell, - Instance *inst, - VerilogModuleInst *mod_inst, - VerilogBindingTbl *bindings, - Instance *parent, - VerilogModule *parent_module, - VerilogBindingTbl *parent_bindings, - bool is_leaf); + Instance *inst, + VerilogModuleInst *mod_inst, + VerilogBindingTbl *bindings, + Instance *parent, + VerilogModule *parent_module, + VerilogBindingTbl *parent_bindings, + bool is_leaf); void makeOrderedInstPins(Cell *cell, - Instance *inst, - VerilogModuleInst *mod_inst, - VerilogBindingTbl *bindings, - Instance *parent, - VerilogModule *parent_module, - VerilogBindingTbl *parent_bindings, - bool is_leaf); + Instance *inst, + VerilogModuleInst *mod_inst, + VerilogBindingTbl *bindings, + Instance *parent, + VerilogModule *parent_module, + VerilogBindingTbl *parent_bindings, + bool is_leaf); void mergeAssignNet(VerilogAssign *assign, - VerilogModule *module, - Instance *inst, - VerilogBindingTbl *bindings); + VerilogModule *module, + Instance *inst, + VerilogBindingTbl *bindings); void makeInstPin(Instance *inst, - Port *port, - VerilogNetNameIterator *net_name_iter, - VerilogBindingTbl *bindings, - Instance *parent, - VerilogBindingTbl *parent_bindings, - bool is_leaf); + Port *port, + VerilogNetNameIterator *net_name_iter, + VerilogBindingTbl *bindings, + Instance *parent, + VerilogBindingTbl *parent_bindings, + bool is_leaf); void makeInstPin(Instance *inst, - Port *port, - const std::string &net_name, - VerilogBindingTbl *bindings, - Instance *parent, - VerilogBindingTbl *parent_bindings, - bool is_leaf); + Port *port, + const std::string &net_name, + VerilogBindingTbl *bindings, + Instance *parent, + VerilogBindingTbl *parent_bindings, + bool is_leaf); void linkWarn(int id, const char *filename, - int line, - const char *msg, ...) + int line, + const char *msg, ...) __attribute__((format (printf, 5, 6))); void linkError(int id, const char *filename, - int line, - const char *msg, ...) + int line, + const char *msg, ...) __attribute__((format (printf, 5, 6))); bool reportLinkErrors(); bool haveLinkErrors(); Cell *makeBlackBox(VerilogModuleInst *mod_inst, - VerilogModule *parent_module); + VerilogModule *parent_module); void makeBlackBoxNamedPorts(Cell *cell, - VerilogModuleInst *mod_inst, - VerilogModule *parent_module); + VerilogModuleInst *mod_inst, + VerilogModule *parent_module); void makeBlackBoxOrderedPorts(Cell *cell, - VerilogModuleInst *mod_inst, - VerilogModule *parent_module); + VerilogModuleInst *mod_inst, + VerilogModule *parent_module); bool isBlackBox(Cell *cell); bool hasScalarNamedPortRefs(LibertyCell *liberty_cell, - VerilogNetSeq *pins); + VerilogNetSeq *pins); std::string filename_; Report *report_; @@ -294,4 +294,3 @@ protected: }; } // namespace sta - diff --git a/include/sta/VerilogWriter.hh b/include/sta/VerilogWriter.hh index b4a08e8c..a0ba6346 100644 --- a/include/sta/VerilogWriter.hh +++ b/include/sta/VerilogWriter.hh @@ -30,8 +30,8 @@ namespace sta { void writeVerilog(const char *filename, - bool include_pwr_gnd, - CellSeq *remove_cells, - Network *network); + bool include_pwr_gnd, + CellSeq *remove_cells, + Network *network); } // namespace diff --git a/include/sta/VertexId.hh b/include/sta/VertexId.hh index b56b8b7c..c2dbcfbc 100644 --- a/include/sta/VertexId.hh +++ b/include/sta/VertexId.hh @@ -30,7 +30,7 @@ namespace sta { -typedef ObjectId VertexId; +using VertexId = ObjectId; static constexpr VertexId vertex_id_null = object_id_null; diff --git a/include/sta/VisitPathEnds.hh b/include/sta/VisitPathEnds.hh index f6114b3f..e07fb2d0 100644 --- a/include/sta/VisitPathEnds.hh +++ b/include/sta/VisitPathEnds.hh @@ -38,109 +38,104 @@ class VisitPathEnds : public StaState { public: VisitPathEnds(const StaState *sta); - // All corners, unfiltered. + // All scenes, unfiltered. void visitPathEnds(Vertex *vertex, - PathEndVisitor *visitor); - // Use corner nullptr to visit PathEnds for all corners. + PathEndVisitor *visitor); void visitPathEnds(Vertex *vertex, - const Corner *corner, - const MinMaxAll *min_max, - bool filtered, - PathEndVisitor *visitor); - bool checkEdgeEnabled(Edge *edge) const; + const SceneSet &scenes, + const MinMaxAll *min_max, + bool filtered, + PathEndVisitor *visitor); + bool checkEdgeEnabled(const Edge *edge, + const Mode *mode) const; protected: void visitClkedPathEnds(const Pin *pin, - Vertex *vertex, - const Corner *corner, - const MinMaxAll *min_max, - bool filtered, - PathEndVisitor *visitor, - bool &is_constrained); + Vertex *vertex, + const SceneSet &scenes, + const MinMaxAll *min_max, + bool filtered, + PathEndVisitor *visitor, + bool &is_constrained); virtual void visitCheckEnd(const Pin *pin, - Vertex *vertex, - Path *path, - const RiseFall *end_rf, - const PathAnalysisPt *path_ap, - bool filtered, - PathEndVisitor *visitor, - bool &is_constrained); + Vertex *vertex, + Path *path, + const RiseFall *end_rf, + bool filtered, + PathEndVisitor *visitor, + bool &is_constrained); void visitCheckEndUnclked(const Pin *pin, - Vertex *vertex, - Path *path, - const RiseFall *end_rf, - const PathAnalysisPt *path_ap, - bool filtered, - PathEndVisitor *visitor, - bool &is_constrained); + Vertex *vertex, + Path *path, + const RiseFall *end_rf, + bool filtered, + PathEndVisitor *visitor, + bool &is_constrained); void visitOutputDelayEnd(const Pin *pin, - Path *path, - const RiseFall *end_rf, - const PathAnalysisPt *path_ap, - bool filtered, - PathEndVisitor *visitor, - bool &is_constrained); + Path *path, + const RiseFall *end_rf, + bool filtered, + PathEndVisitor *visitor, + bool &is_constrained); virtual void visitOutputDelayEnd1(OutputDelay *output_delay, - const Pin *pin, - Path *path, - const RiseFall *end_rf, - const ClockEdge *tgt_clk_edge, - Path *ref_path, - const MinMax *min_max, - PathEndVisitor *visitor, - bool &is_constrained); + const Pin *pin, + Path *path, + const RiseFall *end_rf, + const ClockEdge *tgt_clk_edge, + Path *ref_path, + const MinMax *min_max, + PathEndVisitor *visitor, + bool &is_constrained); virtual void visitGatedClkEnd(const Pin *pin, - Vertex *vertex, - Path *path, - const RiseFall *end_rf, - const PathAnalysisPt *path_ap, - bool filtered, - PathEndVisitor *visitor, - bool &is_constrained); + Vertex *vertex, + Path *path, + const RiseFall *end_rf, + bool filtered, + PathEndVisitor *visitor, + bool &is_constrained); float clockGatingMargin(const Clock *clk, - const Pin *clk_pin, - const Pin *enable_pin, - const RiseFall *enable_rf, - const SetupHold *setup_hold); + const Pin *clk_pin, + const Pin *enable_pin, + const RiseFall *enable_rf, + const SetupHold *setup_hold, + const Sdc *sdc); void visitDataCheckEnd(const Pin *pin, - Path *path, - const RiseFall *end_rf, - const PathAnalysisPt *path_ap, - bool filtered, - PathEndVisitor *visitor, - bool &is_constrained); + Path *path, + const RiseFall *end_rf, + bool filtered, + PathEndVisitor *visitor, + bool &is_constrained); bool visitDataCheckEnd1(DataCheck *check, - const Pin *pin, - Path *path, - const Clock *src_clk, - const RiseFall *end_rf, - const MinMax *min_max, - const PathAnalysisPt *clk_ap, - const Pin *from_pin, - Vertex *from_vertex, - const RiseFall *from_rf, - bool filtered, - PathEndVisitor *visitor, - bool &is_constrained); + const Pin *pin, + Path *path, + const Clock *src_clk, + const RiseFall *end_rf, + const MinMax *min_max, + const Pin *from_pin, + Vertex *from_vertex, + const RiseFall *from_rf, + bool filtered, + PathEndVisitor *visitor, + bool &is_constrained); virtual void visitUnconstrainedPathEnds(const Pin *pin, - Vertex *vertex, - const Corner *corner, - const MinMaxAll *min_max, - bool filtered, - PathEndVisitor *visitor); + Vertex *vertex, + const SceneSet &scenes, + const MinMaxAll *min_max, + bool filtered, + PathEndVisitor *visitor); bool falsePathTo(Path *path, - const Pin *pin, - const RiseFall *rf, - const MinMax *min_max); + const Pin *pin, + const RiseFall *rf, + const MinMax *min_max); PathDelay *pathDelayTo(Path *path, - const Pin *pin, - const RiseFall *rf, - const MinMax *min_max); + const Pin *pin, + const RiseFall *rf, + const MinMax *min_max); ExceptionPath *exceptionTo(const Path *path, - const Pin *pin, - const RiseFall *rf, - const ClockEdge *clk_edge, - const MinMax *min_max) const; + const Pin *pin, + const RiseFall *rf, + const ClockEdge *clk_edge, + const MinMax *min_max) const; }; // Abstract base class used by visitPathEnds to visit vertex path ends. diff --git a/include/sta/Wireload.hh b/include/sta/Wireload.hh index d0ea001c..42621171 100644 --- a/include/sta/Wireload.hh +++ b/include/sta/Wireload.hh @@ -24,16 +24,18 @@ #pragma once -#include "Vector.hh" +#include +#include + #include "LibertyClass.hh" namespace sta { class WireloadForArea; -typedef std::pair FanoutLength; -typedef Vector FanoutLengthSeq; -typedef Vector WireloadForAreaSeq; +using FanoutLength = std::pair; +using FanoutLengthSeq = std::vector; +using WireloadForAreaSeq = std::vector; const char * wireloadTreeString(WireloadTree tree); @@ -49,13 +51,13 @@ class Wireload { public: Wireload(const char *name, - LibertyLibrary *library); + LibertyLibrary *library); Wireload(const char *name, - LibertyLibrary *library, - float area, - float resistance, - float capacitance, - float slope); + LibertyLibrary *library, + float area, + float resistance, + float capacitance, + float slope); virtual ~Wireload(); const char *name() const { return name_; } void setArea(float area); @@ -63,12 +65,12 @@ public: void setCapacitance(float cap); void setSlope(float slope); void addFanoutLength(float fanout, - float length); + float length); // Find wireload resistance/capacitance for fanout. virtual void findWireload(float fanout, - const OperatingConditions *op_cond, - float &cap, - float &res) const; + const OperatingConditions *op_cond, + float &cap, + float &res) const; protected: const char *name_; @@ -84,12 +86,12 @@ protected: class WireloadSelection { public: - explicit WireloadSelection(const char *name); + WireloadSelection(const char *name); ~WireloadSelection(); const char *name() const { return name_; } void addWireloadFromArea(float min_area, - float max_area, - const Wireload *wireload); + float max_area, + const Wireload *wireload); const Wireload *findWireload(float area) const; private: diff --git a/include/sta/WriteSdc.hh b/include/sta/WriteSdc.hh index 3aa51768..02abd693 100644 --- a/include/sta/WriteSdc.hh +++ b/include/sta/WriteSdc.hh @@ -32,16 +32,16 @@ namespace sta { // Write SDC to a file. // Allow SDC to apply to an instance to support write_context. void -writeSdc(Instance *instance, - const char *filename, - const char *creator, - // Map hierarchical pins and instances to leaf pins and instances. - bool map_hpins, - // Replace non-sdc get functions with OpenSTA equivalents. - bool native, - int digits, +writeSdc(const Sdc *sdc, + Instance *instance, + const char *filename, + const char *creator, + // Map hierarchical pins and instances to leaf pins and instances. + bool map_hpins, + // Replace non-sdc get functions with OpenSTA equivalents. + bool native, + int digits, bool gzip, - bool no_timestamp, - Sdc *sdc); + bool no_timestamp); } // namespace diff --git a/include/sta/Zlib.hh b/include/sta/Zlib.hh index 7a9399de..c1e14344 100644 --- a/include/sta/Zlib.hh +++ b/include/sta/Zlib.hh @@ -47,7 +47,7 @@ #define Z_NULL nullptr namespace gzstream { -typedef std::ifstream igzstream; +using igzstream = std::ifstream; } #endif // ZLIB_FOUND diff --git a/liberty/EquivCells.cc b/liberty/EquivCells.cc index f8910791..c39553ec 100644 --- a/liberty/EquivCells.cc +++ b/liberty/EquivCells.cc @@ -24,6 +24,7 @@ #include "EquivCells.hh" +#include "ContainerHelpers.hh" #include "Hash.hh" #include "MinMax.hh" #include "PortDirection.hh" @@ -49,7 +50,7 @@ static unsigned hashSequential(const Sequential *seq); bool equivCellStatetables(const LibertyCell *cell1, - const LibertyCell *cell2); + const LibertyCell *cell2); static bool equivCellPortSeq(const LibertyPortSeq &ports1, const LibertyPortSeq &ports2); @@ -86,77 +87,75 @@ class CellDriveResistanceGreater { public: bool operator()(const LibertyCell *cell1, - const LibertyCell *cell2) const + const LibertyCell *cell2) const { return cellDriveResistance(cell1) > cellDriveResistance(cell2); } }; EquivCells::EquivCells(LibertyLibrarySeq *equiv_libs, - LibertyLibrarySeq *map_libs) + LibertyLibrarySeq *map_libs) { LibertyCellHashMap hash_matches; for (auto lib : *equiv_libs) findEquivCells(lib, hash_matches); // Sort the equiv sets by drive resistance. for (auto cell : unique_equiv_cells_) { - auto equivs = equiv_cells_.findKey(cell); + auto equivs = findKey(equiv_cells_, cell); sort(equivs, CellDriveResistanceGreater()); } if (map_libs) { for (auto lib : *map_libs) mapEquivCells(lib, hash_matches); } - hash_matches.deleteContents(); + deleteContents(hash_matches); } EquivCells::~EquivCells() { for (auto cell : unique_equiv_cells_) - delete equiv_cells_.findKey(cell); + delete findKey(equiv_cells_, cell); } LibertyCellSeq * EquivCells::equivs(LibertyCell *cell) { - return equiv_cells_.findKey(cell); + return findKey(equiv_cells_, cell); } // Use a comprehensive hash on cell properties to segregate // cells into groups of potential matches. void EquivCells::findEquivCells(const LibertyLibrary *library, - LibertyCellHashMap &hash_matches) + LibertyCellHashMap &hash_matches) { LibertyCellIterator cell_iter(library); while (cell_iter.hasNext()) { LibertyCell *cell = cell_iter.next(); if (!cell->dontUse()) { unsigned hash = hashCell(cell); - LibertyCellSeq *matches = hash_matches.findKey(hash); + LibertyCellSeq *matches = findKey(hash_matches, hash); if (matches) { - LibertyCellSeq::Iterator match_iter(matches); - while (match_iter.hasNext()) { - LibertyCell *match = match_iter.next(); - if (equivCells(match, cell)) { - LibertyCellSeq *equivs = equiv_cells_.findKey(match); - if (equivs == nullptr) { - equivs = new LibertyCellSeq; - equivs->push_back(match); - unique_equiv_cells_.push_back(match); - equiv_cells_[match] = equivs; - } - equivs->push_back(cell); - equiv_cells_[cell] = equivs; - break; - } - } - matches->push_back(cell); + for (LibertyCell *match : *matches) { + if (equivCells(match, cell)) { + LibertyCellSeq *equivs = findKey(equiv_cells_, match); + if (equivs == nullptr) { + equivs = new LibertyCellSeq; + equivs->push_back(match); + unique_equiv_cells_.push_back(match); + equiv_cells_[match] = equivs; + } + equivs->push_back(cell); + equiv_cells_[cell] = equivs; + break; + } + } + matches->push_back(cell); } else { - matches = new LibertyCellSeq; - hash_matches[hash] = matches; - matches->push_back(cell); + matches = new LibertyCellSeq; + hash_matches[hash] = matches; + matches->push_back(cell); } } } @@ -165,7 +164,7 @@ EquivCells::findEquivCells(const LibertyLibrary *library, // Map library cells to equiv cells. void EquivCells::mapEquivCells(const LibertyLibrary *library, - LibertyCellHashMap &hash_matches) + LibertyCellHashMap &hash_matches) { LibertyCellIterator cell_iter(library); @@ -173,17 +172,15 @@ EquivCells::mapEquivCells(const LibertyLibrary *library, LibertyCell *cell = cell_iter.next(); if (!cell->dontUse()) { unsigned hash = hashCell(cell); - LibertyCellSeq *matches = hash_matches.findKey(hash); + LibertyCellSeq *matches = findKey(hash_matches, hash); if (matches) { - LibertyCellSeq::Iterator match_iter(matches); - while (match_iter.hasNext()) { - LibertyCell *match = match_iter.next(); - if (equivCells(match, cell)) { - LibertyCellSeq *equivs = equiv_cells_.findKey(match); - equiv_cells_[cell] = equivs; - break; - } - } + for (LibertyCell *match : *matches) { + if (equivCells(match, cell)) { + LibertyCellSeq *equivs = findKey(equiv_cells_, match); + equiv_cells_[cell] = equivs; + break; + } + } } } } @@ -286,22 +283,22 @@ hashFuncExpr(const FuncExpr *expr) return 0; else { switch (expr->op()) { - case FuncExpr::op_port: + case FuncExpr::Op::port: return hashPort(expr->port()) * 17; break; - case FuncExpr::op_not: + case FuncExpr::Op::not_: return hashFuncExpr(expr->left()) * 31; break; default: return (hashFuncExpr(expr->left()) + hashFuncExpr(expr->right())) - * ((1 << expr->op()) - 1); + * ((1 << static_cast(expr->op())) - 1); } } } bool equivCells(const LibertyCell *cell1, - const LibertyCell *cell2) + const LibertyCell *cell2) { return equivCellPorts(cell1, cell2) && equivCellFuncs(cell1, cell2) @@ -356,7 +353,7 @@ equivCellFuncs(const LibertyCell *cell1, bool equivCellPorts(const LibertyCell *cell1, - const LibertyCell *cell2) + const LibertyCell *cell2) { if (cell1->portCount() != cell2->portCount()) return false; @@ -375,7 +372,7 @@ equivCellPorts(const LibertyCell *cell1, bool equivCellSequentials(const LibertyCell *cell1, - const LibertyCell *cell2) + const LibertyCell *cell2) { const SequentialSeq &seqs1 = cell1->sequentials(); const SequentialSeq &seqs2 = cell2->sequentials(); @@ -386,11 +383,11 @@ equivCellSequentials(const LibertyCell *cell1, const Sequential *seq1 = *seq_itr1; const Sequential *seq2 = *seq_itr2; if (!(FuncExpr::equiv(seq1->clock(), seq2->clock()) - && FuncExpr::equiv(seq1->data(), seq2->data()) - && LibertyPort::equiv(seq1->output(), seq2->output()) - && LibertyPort::equiv(seq1->outputInv(), seq2->outputInv()) - && FuncExpr::equiv(seq1->clear(), seq2->clear()) - && FuncExpr::equiv(seq1->preset(), seq2->preset()))) + && FuncExpr::equiv(seq1->data(), seq2->data()) + && LibertyPort::equiv(seq1->output(), seq2->output()) + && LibertyPort::equiv(seq1->outputInv(), seq2->outputInv()) + && FuncExpr::equiv(seq1->clear(), seq2->clear()) + && FuncExpr::equiv(seq1->preset(), seq2->preset()))) return false; } return seq_itr1 == seqs1.end() && seq_itr2 == seqs2.end(); @@ -398,7 +395,7 @@ equivCellSequentials(const LibertyCell *cell1, bool equivCellStatetables(const LibertyCell *cell1, - const LibertyCell *cell2) + const LibertyCell *cell2) { const Statetable *statetable1 = cell1->statetable(); @@ -494,7 +491,7 @@ equivStatetableRow(const StatetableRow &row1, bool equivCellTimingArcSets(const LibertyCell *cell1, - const LibertyCell *cell2) + const LibertyCell *cell2) { if (cell1->timingArcSetCount() != cell2->timingArcSetCount()) return false; @@ -502,7 +499,7 @@ equivCellTimingArcSets(const LibertyCell *cell1, for (TimingArcSet *arc_set1 : cell1->timingArcSets()) { TimingArcSet *arc_set2 = cell2->findTimingArcSet(arc_set1); if (!(arc_set2 && TimingArcSet::equiv(arc_set1, arc_set2))) - return false; + return false; } return true; } diff --git a/liberty/FuncExpr.cc b/liberty/FuncExpr.cc index 67de253c..41faa2f6 100644 --- a/liberty/FuncExpr.cc +++ b/liberty/FuncExpr.cc @@ -35,53 +35,53 @@ using std::string; FuncExpr * FuncExpr::makePort(LibertyPort *port) { - return new FuncExpr(op_port, nullptr, nullptr, port); + return new FuncExpr(Op::port, nullptr, nullptr, port); } FuncExpr * FuncExpr::makeNot(FuncExpr *expr) { - return new FuncExpr(op_not, expr, nullptr, nullptr); + return new FuncExpr(Op::not_, expr, nullptr, nullptr); } FuncExpr * FuncExpr::makeAnd(FuncExpr *left, - FuncExpr *right) + FuncExpr *right) { - return new FuncExpr(op_and, left, right, nullptr); + return new FuncExpr(Op::and_, left, right, nullptr); } FuncExpr * FuncExpr::makeOr(FuncExpr *left, - FuncExpr *right) + FuncExpr *right) { - return new FuncExpr(op_or, left, right, nullptr); + return new FuncExpr(Op::or_, left, right, nullptr); } FuncExpr * FuncExpr::makeXor(FuncExpr *left, - FuncExpr *right) + FuncExpr *right) { - return new FuncExpr(op_xor, left, right, nullptr); + return new FuncExpr(Op::xor_, left, right, nullptr); } FuncExpr * FuncExpr::makeZero() { - return new FuncExpr(op_zero, nullptr, nullptr, nullptr); + return new FuncExpr(Op::zero, nullptr, nullptr, nullptr); } FuncExpr * FuncExpr::makeOne() { - return new FuncExpr(op_one, nullptr, nullptr, nullptr); + return new FuncExpr(Op::one, nullptr, nullptr, nullptr); } -FuncExpr::FuncExpr(Operator op, - FuncExpr *left, - FuncExpr *right, - LibertyPort *port) : +FuncExpr::FuncExpr(Op op, + FuncExpr *left, + FuncExpr *right, + LibertyPort *port) : op_(op), left_(left), right_(right), @@ -110,7 +110,7 @@ FuncExpr::copy() LibertyPort * FuncExpr::port() const { - if (op_ == op_port) + if (op_ == Op::port) return port_; else return nullptr; @@ -123,29 +123,29 @@ FuncExpr::portTimingSense(const LibertyPort *port) const TimingSense left_sense, right_sense; switch (op_) { - case op_port: + case Op::port: if (port == port_) return TimingSense::positive_unate; else return TimingSense::none; - case op_not: + case Op::not_: if (left_) { switch (left_->portTimingSense(port)) { case TimingSense::positive_unate: - return TimingSense::negative_unate; + return TimingSense::negative_unate; case TimingSense::negative_unate: - return TimingSense::positive_unate; + return TimingSense::positive_unate; case TimingSense::non_unate: - return TimingSense::non_unate; + return TimingSense::non_unate; case TimingSense::none: - return TimingSense::none; + return TimingSense::none; case TimingSense::unknown: - return TimingSense::unknown; + return TimingSense::unknown; } } return TimingSense::unknown; - case op_or: - case op_and: + case Op::or_: + case Op::and_: left_sense = TimingSense::unknown; right_sense = TimingSense::unknown; if (left_) @@ -156,21 +156,21 @@ FuncExpr::portTimingSense(const LibertyPort *port) const if (left_sense == right_sense) return left_sense; else if (left_sense == TimingSense::non_unate - || right_sense == TimingSense::non_unate - || (left_sense == TimingSense::positive_unate - && right_sense == TimingSense::negative_unate) - || (left_sense == TimingSense::negative_unate - && right_sense == TimingSense::positive_unate)) + || right_sense == TimingSense::non_unate + || (left_sense == TimingSense::positive_unate + && right_sense == TimingSense::negative_unate) + || (left_sense == TimingSense::negative_unate + && right_sense == TimingSense::positive_unate)) return TimingSense::non_unate; else if (left_sense == TimingSense::none - || left_sense == TimingSense::unknown) + || left_sense == TimingSense::unknown) return right_sense; else if (right_sense == TimingSense::none - || right_sense == TimingSense::unknown) + || right_sense == TimingSense::unknown) return left_sense; else return TimingSense::unknown; - case op_xor: + case Op::xor_: left_sense = TimingSense::unknown; right_sense = TimingSense::unknown; if (left_) @@ -178,17 +178,17 @@ FuncExpr::portTimingSense(const LibertyPort *port) const if (right_) right_sense = right_->portTimingSense(port); if (left_sense == TimingSense::positive_unate - || left_sense == TimingSense::negative_unate - || left_sense == TimingSense::non_unate - || right_sense == TimingSense::positive_unate - || right_sense == TimingSense::negative_unate - || right_sense == TimingSense::non_unate) + || left_sense == TimingSense::negative_unate + || left_sense == TimingSense::non_unate + || right_sense == TimingSense::positive_unate + || right_sense == TimingSense::negative_unate + || right_sense == TimingSense::non_unate) return TimingSense::non_unate; else return TimingSense::unknown; - case op_one: + case Op::one: return TimingSense::none; - case op_zero: + case Op::zero: return TimingSense::none; } // Prevent warnings from lame compilers. @@ -205,22 +205,22 @@ string FuncExpr::to_string(bool with_parens) const { switch (op_) { - case op_port: + case Op::port: return port_->name(); - case op_not: { + case Op::not_: { string result = "!"; result += left_->to_string(true); return result; } - case op_or: + case Op::or_: return to_string(with_parens, '+'); - case op_and: + case Op::and_: return to_string(with_parens, '*'); - case op_xor: + case Op::xor_: return to_string(with_parens, '^'); - case op_one: + case Op::one: return "1"; - case op_zero: + case Op::zero: return "0"; default: return "?"; @@ -247,11 +247,11 @@ FuncExpr * FuncExpr::bitSubExpr(int bit_offset) { switch (op_) { - case op_port: + case Op::port: if (port_->hasMembers()) { if (port_->size() == 1) { - LibertyPort *port = port_->findLibertyMember(0); - return makePort(port); + LibertyPort *port = port_->findLibertyMember(0); + return makePort(port); } else { if (bit_offset < port_->size()) { @@ -265,19 +265,19 @@ FuncExpr::bitSubExpr(int bit_offset) else // Always copy so the subexpr doesn't share memory. return makePort(port_); - case op_not: + case Op::not_: return makeNot(left_->bitSubExpr(bit_offset)); - case op_or: + case Op::or_: return makeOr(left_->bitSubExpr(bit_offset), - right_->bitSubExpr(bit_offset)); - case op_and: + right_->bitSubExpr(bit_offset)); + case Op::and_: return makeAnd(left_->bitSubExpr(bit_offset), - right_->bitSubExpr(bit_offset)); - case op_xor: + right_->bitSubExpr(bit_offset)); + case Op::xor_: return makeXor(left_->bitSubExpr(bit_offset), - right_->bitSubExpr(bit_offset)); - case op_one: - case op_zero: + right_->bitSubExpr(bit_offset)); + case Op::one: + case Op::zero: return this; } // Prevent warnings from lame compilers. @@ -288,17 +288,17 @@ bool FuncExpr::hasPort(const LibertyPort *port) const { switch (op_) { - case op_port: + case Op::port: return (port_ == port); - case op_not: + case Op::not_: return left_ && left_->hasPort(port); - case op_or: - case op_and: - case op_xor: + case Op::or_: + case Op::and_: + case Op::xor_: return (left_ && left_->hasPort(port)) || (right_ && right_->hasPort(port)); - case op_one: - case op_zero: + case Op::one: + case Op::zero: return false; } // Prevent warnings from lame compilers. @@ -316,18 +316,18 @@ FuncExpr::checkSize(size_t size) { size_t port_size; switch (op_) { - case op_port: + case Op::port: port_size = port_->size(); return !(port_size == size - || port_size == 1); - case op_not: + || port_size == 1); + case Op::not_: return left_->checkSize(size); - case op_or: - case op_and: - case op_xor: + case Op::or_: + case Op::and_: + case Op::xor_: return left_->checkSize(size) || right_->checkSize(size); - case op_one: - case op_zero: + case Op::one: + case Op::zero: return false; } // Prevent warnings from lame compilers. @@ -337,7 +337,7 @@ FuncExpr::checkSize(size_t size) FuncExpr * funcExprNot(FuncExpr *expr) { - if (expr->op() == FuncExpr::op_not) { + if (expr->op() == FuncExpr::Op::not_) { FuncExpr *not_expr = expr->left(); delete expr; return not_expr; @@ -346,43 +346,44 @@ funcExprNot(FuncExpr *expr) return FuncExpr::makeNot(expr); } -//////////////////////////////////////////////////////////////// - -FuncExprPortIterator::FuncExprPortIterator(const FuncExpr *expr) +LibertyPortSet +FuncExpr::ports() const { - findPorts(expr); - iter_.init(ports_); + LibertyPortSet ports; + findPorts(this, ports); + return ports; } void -FuncExprPortIterator::findPorts(const FuncExpr *expr) +FuncExpr::findPorts(const FuncExpr *expr, + LibertyPortSet &ports) const { if (expr) { - if (expr->op() == FuncExpr::op_port) - ports_.insert(expr->port()); + if (expr->op() == FuncExpr::Op::port) + ports.insert(expr->port()); else { - findPorts(expr->left()); - findPorts(expr->right()); + findPorts(expr->left(), ports); + findPorts(expr->right(), ports); } } } bool FuncExpr::equiv(const FuncExpr *expr1, - const FuncExpr *expr2) + const FuncExpr *expr2) { if (expr1 == nullptr && expr2 == nullptr) return true; else if (expr1 != nullptr && expr2 != nullptr - && expr1->op() == expr2->op()) { + && expr1->op() == expr2->op()) { switch (expr1->op()) { - case FuncExpr::op_port: + case FuncExpr::Op::port: return LibertyPort::equiv(expr1->port(), expr2->port()); - case FuncExpr::op_not: + case FuncExpr::Op::not_: return equiv(expr1->left(), expr2->left()); default: return equiv(expr1->left(), expr2->left()) - && equiv(expr1->right(), expr2->right()); + && equiv(expr1->right(), expr2->right()); } } else @@ -391,22 +392,22 @@ FuncExpr::equiv(const FuncExpr *expr1, bool FuncExpr::less(const FuncExpr *expr1, - const FuncExpr *expr2) + const FuncExpr *expr2) { if (expr1 != nullptr && expr2 != nullptr) { - Operator op1 = expr1->op(); - Operator op2 = expr2->op(); + Op op1 = expr1->op(); + Op op2 = expr2->op(); if (op1 == op2) { switch (expr1->op()) { - case FuncExpr::op_port: - return LibertyPort::less(expr1->port(), expr2->port()); - case FuncExpr::op_not: - return less(expr1->left(), expr2->left()); + case FuncExpr::Op::port: + return LibertyPort::less(expr1->port(), expr2->port()); + case FuncExpr::Op::not_: + return less(expr1->left(), expr2->left()); default: - if (equiv(expr1->left(), expr2->left())) - return less(expr1->right(), expr2->right()); - else - return less(expr1->left(), expr2->left()); + if (equiv(expr1->left(), expr2->left())) + return less(expr1->right(), expr2->right()); + else + return less(expr1->left(), expr2->left()); } } else diff --git a/liberty/InternalPower.cc b/liberty/InternalPower.cc index a68dd196..407b152e 100644 --- a/liberty/InternalPower.cc +++ b/liberty/InternalPower.cc @@ -71,7 +71,7 @@ InternalPowerAttrs::setWhen(FuncExpr *when) void InternalPowerAttrs::setModel(const RiseFall *rf, - InternalPowerModel *model) + InternalPowerModel *model) { models_[rf->index()] = model; } @@ -86,9 +86,9 @@ InternalPowerAttrs::setRelatedPgPin(const char *related_pg_pin) //////////////////////////////////////////////////////////////// InternalPower::InternalPower(LibertyCell *cell, - LibertyPort *port, - LibertyPort *related_port, - InternalPowerAttrs *attrs) : + LibertyPort *port, + LibertyPort *related_port, + InternalPowerAttrs *attrs) : port_(port), related_port_(related_port), when_(attrs->when()), @@ -114,9 +114,9 @@ InternalPower::libertyCell() const float InternalPower::power(const RiseFall *rf, - const Pvt *pvt, - float in_slew, - float load_cap) + const Pvt *pvt, + float in_slew, + float load_cap) { InternalPowerModel *model = models_[rf->index()]; if (model) @@ -139,14 +139,14 @@ InternalPowerModel::~InternalPowerModel() float InternalPowerModel::power(const LibertyCell *cell, - const Pvt *pvt, - float in_slew, - float load_cap) const + const Pvt *pvt, + float in_slew, + float load_cap) const { if (model_) { float axis_value1, axis_value2, axis_value3; findAxisValues(in_slew, load_cap, - axis_value1, axis_value2, axis_value3); + axis_value1, axis_value2, axis_value3); return model_->findValue(cell, pvt, axis_value1, axis_value2, axis_value3); } else @@ -155,15 +155,15 @@ InternalPowerModel::power(const LibertyCell *cell, string InternalPowerModel::reportPower(const LibertyCell *cell, - const Pvt *pvt, - float in_slew, - float load_cap, - int digits) const + const Pvt *pvt, + float in_slew, + float load_cap, + int digits) const { if (model_) { float axis_value1, axis_value2, axis_value3; findAxisValues(in_slew, load_cap, - axis_value1, axis_value2, axis_value3); + axis_value1, axis_value2, axis_value3); const LibertyLibrary *library = cell->libertyLibrary(); return model_->reportValue("Power", cell, pvt, axis_value1, nullptr, axis_value2, axis_value3, @@ -174,11 +174,11 @@ InternalPowerModel::reportPower(const LibertyCell *cell, void InternalPowerModel::findAxisValues(float in_slew, - float load_cap, - // Return values. - float &axis_value1, - float &axis_value2, - float &axis_value3) const + float load_cap, + // Return values. + float &axis_value1, + float &axis_value2, + float &axis_value3) const { switch (model_->order()) { case 0: @@ -211,8 +211,8 @@ InternalPowerModel::findAxisValues(float in_slew, float InternalPowerModel::axisValue(const TableAxis *axis, - float in_slew, - float load_cap) const + float in_slew, + float load_cap) const { TableAxisVariable var = axis->variable(); if (var == TableAxisVariable::input_transition_time) diff --git a/liberty/LeakagePower.cc b/liberty/LeakagePower.cc index 73e4a618..4219cd96 100644 --- a/liberty/LeakagePower.cc +++ b/liberty/LeakagePower.cc @@ -51,7 +51,7 @@ LeakagePowerAttrs::setPower(float power) //////////////////////////////////////////////////////////////// LeakagePower::LeakagePower(LibertyCell *cell, - LeakagePowerAttrs *attrs) : + LeakagePowerAttrs *attrs) : cell_(cell), when_(attrs->when()), power_(attrs->power()) diff --git a/liberty/LibExprReader.cc b/liberty/LibExprReader.cc index f4b873c2..c9bc84bc 100644 --- a/liberty/LibExprReader.cc +++ b/liberty/LibExprReader.cc @@ -37,9 +37,9 @@ namespace sta { FuncExpr * parseFuncExpr(const char *func, - LibertyCell *cell, - const char *error_msg, - Report *report) + LibertyCell *cell, + const char *error_msg, + Report *report) { if (func != nullptr && func[0] != '\0') { std::string func1(func); @@ -56,9 +56,9 @@ parseFuncExpr(const char *func, } LibExprReader::LibExprReader(const char *func, - LibertyCell *cell, - const char *error_msg, - Report *report) : + LibertyCell *cell, + const char *error_msg, + Report *report) : func_(func), cell_(cell), error_msg_(error_msg), @@ -97,7 +97,7 @@ LibExprReader::makeFuncExprNot(FuncExpr *arg) FuncExpr * LibExprReader::makeFuncExprXor(FuncExpr *arg1, - FuncExpr *arg2) + FuncExpr *arg2) { if (arg1 && arg2) return FuncExpr::makeXor(arg1, arg2); @@ -107,7 +107,7 @@ LibExprReader::makeFuncExprXor(FuncExpr *arg1, FuncExpr * LibExprReader::makeFuncExprAnd(FuncExpr *arg1, - FuncExpr *arg2) + FuncExpr *arg2) { if (arg1 && arg2) return FuncExpr::makeAnd(arg1, arg2); @@ -117,7 +117,7 @@ LibExprReader::makeFuncExprAnd(FuncExpr *arg1, FuncExpr * LibExprReader::makeFuncExprOr(FuncExpr *arg1, - FuncExpr *arg2) + FuncExpr *arg2) { if (arg1 && arg2) return FuncExpr::makeOr(arg1, arg2); diff --git a/liberty/LibExprReader.hh b/liberty/LibExprReader.hh index 3e15ac35..79d6d35f 100644 --- a/liberty/LibExprReader.hh +++ b/liberty/LibExprReader.hh @@ -32,8 +32,8 @@ class LibertyCell; FuncExpr * parseFuncExpr(const char *func, - LibertyCell *cell, - const char *error_msg, - Report *report); + LibertyCell *cell, + const char *error_msg, + Report *report); } // namespace diff --git a/liberty/LibExprReaderPvt.hh b/liberty/LibExprReaderPvt.hh index 78cf21b6..4532b2e8 100644 --- a/liberty/LibExprReaderPvt.hh +++ b/liberty/LibExprReaderPvt.hh @@ -35,22 +35,22 @@ class LibExprReader { public: LibExprReader(const char *func, - LibertyCell *cell, - const char *error_msg, - Report *report); + LibertyCell *cell, + const char *error_msg, + Report *report); FuncExpr *makeFuncExprPort(const char *port_name); FuncExpr *makeFuncExprOr(FuncExpr *arg1, - FuncExpr *arg2); + FuncExpr *arg2); FuncExpr *makeFuncExprAnd(FuncExpr *arg1, - FuncExpr *arg2); + FuncExpr *arg2); FuncExpr *makeFuncExprXor(FuncExpr *arg1, - FuncExpr *arg2); + FuncExpr *arg2); FuncExpr *makeFuncExprNot(FuncExpr *arg); void setResult(FuncExpr *result); FuncExpr *result() { return result_; } void parseError(const char *msg); size_t copyInput(char *buf, - size_t max_size); + size_t max_size); Report *report() const { return report_; } private: diff --git a/liberty/Liberty.cc b/liberty/Liberty.cc index 3cf867f2..cb986a59 100644 --- a/liberty/Liberty.cc +++ b/liberty/Liberty.cc @@ -24,6 +24,7 @@ #include "Liberty.hh" +#include "ContainerHelpers.hh" #include "Mutex.hh" #include "EnumNameMap.hh" #include "Report.hh" @@ -45,15 +46,12 @@ #include "EquivCells.hh" #include "Network.hh" #include "PortDirection.hh" -#include "Corner.hh" -#include "DcalcAnalysisPt.hh" +#include "Scene.hh" namespace sta { using std::string; -typedef Set LatchEnableSet; - void initLiberty() { @@ -67,7 +65,7 @@ deleteLiberty() } LibertyLibrary::LibertyLibrary(const char *name, - const char *filename) : + const char *filename) : ConcreteLibrary(name, filename, true), units_(new Units()), delay_model_type_(DelayModelType::table), // default @@ -101,7 +99,7 @@ LibertyLibrary::LibertyLibrary(const char *name, for (int i = 0; i != table_template_type_count; i++) { TableTemplateType type = static_cast(i); TableTemplate *scalar_template = new TableTemplate("scalar", nullptr, - nullptr, nullptr); + nullptr, nullptr); addTableTemplate(scalar_template, type); } @@ -116,26 +114,26 @@ LibertyLibrary::LibertyLibrary(const char *name, LibertyLibrary::~LibertyLibrary() { - bus_dcls_.deleteContents(); + deleteContents(bus_dcls_); for (int i = 0; i < table_template_type_count; i++) - template_maps_[i].deleteContents(); - scale_factors_map_.deleteContents(); + deleteContents(template_maps_[i]); + deleteContents(scale_factors_map_); delete scale_factors_; for (auto rf_index : RiseFall::rangeIndex()) { TableModel *model = wire_slew_degradation_tbls_[rf_index]; delete model; } - operating_conditions_.deleteContents(); - wireloads_.deleteContents(); - wire_load_selections_.deleteContents(); + deleteContents(operating_conditions_); + deleteContents(wireloads_); + deleteContents(wire_load_selections_); delete units_; // Also deletes default_ocv_derate_ - ocv_derate_map_.deleteContents(); + deleteContents(ocv_derate_map_); delete buffers_; delete inverters_; - driver_waveform_map_.deleteContents(); + deleteContents(driver_waveform_map_); delete driver_waveform_default_; } @@ -183,8 +181,8 @@ LibertyLibrary::buffers() while (cell_iter.hasNext()) { LibertyCell *cell = cell_iter.next(); if (!cell->dontUse() - && cell->isBuffer()) - buffers_->push_back(cell); + && cell->isBuffer()) + buffers_->push_back(cell); } } return buffers_; @@ -205,7 +203,7 @@ LibertyLibrary::addBusDcl(BusDcl *bus_dcl) BusDcl * LibertyLibrary::findBusDcl(const char *name) const { - return bus_dcls_.findKey(name); + return findKey(bus_dcls_, name); } BusDclSeq @@ -219,16 +217,16 @@ LibertyLibrary::busDcls() const void LibertyLibrary::addTableTemplate(TableTemplate *tbl_template, - TableTemplateType type) + TableTemplateType type) { template_maps_[int(type)][tbl_template->name()] = tbl_template; } TableTemplate * LibertyLibrary::findTableTemplate(const char *name, - TableTemplateType type) + TableTemplateType type) { - return template_maps_[int(type)].findKey(name); + return findKey(template_maps_[int(type)], name); } TableTemplateSeq @@ -280,24 +278,24 @@ LibertyLibrary::findScaleFactors(const char *name) float LibertyLibrary::scaleFactor(ScaleFactorType type, - const Pvt *pvt) const + const Pvt *pvt) const { return scaleFactor(type, 0, nullptr, pvt); } float LibertyLibrary::scaleFactor(ScaleFactorType type, - const LibertyCell *cell, - const Pvt *pvt) const + const LibertyCell *cell, + const Pvt *pvt) const { return scaleFactor(type, 0, cell, pvt); } float LibertyLibrary::scaleFactor(ScaleFactorType type, - int rf_index, - const LibertyCell *cell, - const Pvt *pvt) const + int rf_index, + const LibertyCell *cell, + const Pvt *pvt) const { if (pvt == nullptr) pvt = default_operating_conditions_; @@ -312,11 +310,11 @@ LibertyLibrary::scaleFactor(ScaleFactorType type, scale_factors = scale_factors_; if (scale_factors) { float process_scale = 1.0F + (pvt->process() - nominal_process_) - * scale_factors->scale(type, ScaleFactorPvt::process, rf_index); + * scale_factors->scale(type, ScaleFactorPvt::process, rf_index); float temp_scale = 1.0F + (pvt->temperature() - nominal_temperature_) - * scale_factors->scale(type, ScaleFactorPvt::temp, rf_index); + * scale_factors->scale(type, ScaleFactorPvt::temp, rf_index); float volt_scale = 1.0F + (pvt->voltage() - nominal_voltage_) - * scale_factors->scale(type, ScaleFactorPvt::volt, rf_index); + * scale_factors->scale(type, ScaleFactorPvt::volt, rf_index); float scale = process_scale * temp_scale * volt_scale; return scale; } @@ -326,7 +324,7 @@ LibertyLibrary::scaleFactor(ScaleFactorType type, void LibertyLibrary::setWireSlewDegradationTable(TableModel *model, - const RiseFall *rf) + const RiseFall *rf) { int rf_index = rf->index(); if (wire_slew_degradation_tbls_[rf_index]) @@ -342,8 +340,8 @@ LibertyLibrary::wireSlewDegradationTable(const RiseFall *rf) const float LibertyLibrary::degradeWireSlew(const RiseFall *rf, - float in_slew, - float wire_delay) const + float in_slew, + float wire_delay) const { const TableModel *model = wireSlewDegradationTable(rf); if (model) @@ -354,8 +352,8 @@ LibertyLibrary::degradeWireSlew(const RiseFall *rf, float LibertyLibrary::degradeWireSlew(const TableModel *model, - float in_slew, - float wire_delay) const + float in_slew, + float wire_delay) const { switch (model->order()) { case 0: @@ -378,10 +376,10 @@ LibertyLibrary::degradeWireSlew(const TableModel *model, TableAxisVariable var1 = axis1->variable(); TableAxisVariable var2 = axis2->variable(); if (var1 == TableAxisVariable::output_pin_transition - && var2 == TableAxisVariable::connect_delay) + && var2 == TableAxisVariable::connect_delay) return model->findValue(in_slew, wire_delay, 0.0); else if (var1 == TableAxisVariable::connect_delay - && var2 == TableAxisVariable::output_pin_transition) + && var2 == TableAxisVariable::output_pin_transition) return model->findValue(wire_delay, in_slew, 0.0); else { criticalError(1117, "unsupported slew degradation table axes"); @@ -414,9 +412,9 @@ LibertyLibrary::checkSlewDegradationAxes(const TablePtr &table) TableAxisVariable var1 = axis1->variable(); TableAxisVariable var2 = axis2->variable(); return (var1 == TableAxisVariable::output_pin_transition - && var2 == TableAxisVariable::connect_delay) + && var2 == TableAxisVariable::connect_delay) || (var1 == TableAxisVariable::connect_delay - && var2 == TableAxisVariable::output_pin_transition); + && var2 == TableAxisVariable::output_pin_transition); } default: criticalError(1119, "unsupported slew degradation table axes"); @@ -426,7 +424,7 @@ LibertyLibrary::checkSlewDegradationAxes(const TablePtr &table) void LibertyLibrary::defaultMaxFanout(float &fanout, - bool &exists) const + bool &exists) const { fanout = default_max_fanout_; exists = default_max_fanout_exists_; @@ -441,7 +439,7 @@ LibertyLibrary::setDefaultMaxFanout(float fanout) void LibertyLibrary::defaultMaxSlew(float &slew, - bool &exists) const + bool &exists) const { slew = default_max_slew_; exists = default_max_slew_exists_; @@ -456,7 +454,7 @@ LibertyLibrary::setDefaultMaxSlew(float slew) void LibertyLibrary::defaultMaxCapacitance(float &cap, - bool &exists) const + bool &exists) const { cap = default_max_cap_; exists = default_max_cap_exists_; @@ -471,8 +469,8 @@ LibertyLibrary::setDefaultMaxCapacitance(float cap) void LibertyLibrary::defaultFanoutLoad(// Return values. - float &fanout, - bool &exists) const + float &fanout, + bool &exists) const { fanout = default_fanout_load_; exists = default_fanout_load_exists_; @@ -505,26 +503,26 @@ LibertyLibrary::setDefaultOutputPinCap(float cap) void LibertyLibrary::defaultIntrinsic(const RiseFall *rf, - // Return values. - float &intrinsic, - bool &exists) const + // Return values. + float &intrinsic, + bool &exists) const { default_intrinsic_.value(rf, intrinsic, exists); } void LibertyLibrary::setDefaultIntrinsic(const RiseFall *rf, - float value) + float value) { default_intrinsic_.setValue(rf, value); } void LibertyLibrary::defaultPinResistance(const RiseFall *rf, - const PortDirection *dir, - // Return values. - float &res, - bool &exists) const + const PortDirection *dir, + // Return values. + float &res, + bool &exists) const { if (dir->isAnyTristate()) defaultBidirectPinRes(rf, res, exists); @@ -534,32 +532,32 @@ LibertyLibrary::defaultPinResistance(const RiseFall *rf, void LibertyLibrary::defaultBidirectPinRes(const RiseFall *rf, - // Return values. - float &res, - bool &exists) const + // Return values. + float &res, + bool &exists) const { return default_inout_pin_res_.value(rf, res, exists); } void LibertyLibrary::setDefaultBidirectPinRes(const RiseFall *rf, - float value) + float value) { default_inout_pin_res_.setValue(rf, value); } void LibertyLibrary::defaultOutputPinRes(const RiseFall *rf, - // Return values. - float &res, - bool &exists) const + // Return values. + float &res, + bool &exists) const { default_output_pin_res_.value(rf, res, exists); } void LibertyLibrary::setDefaultOutputPinRes(const RiseFall *rf, - float value) + float value) { default_output_pin_res_.setValue(rf, value); } @@ -573,7 +571,7 @@ LibertyLibrary::addWireload(Wireload *wireload) Wireload * LibertyLibrary::findWireload(const char *name) const { - return wireloads_.findKey(name); + return findKey(wireloads_, name); } void @@ -597,7 +595,7 @@ LibertyLibrary::addWireloadSelection(WireloadSelection *selection) WireloadSelection * LibertyLibrary::findWireloadSelection(const char *name) const { - return wire_load_selections_.findKey(name); + return findKey(wire_load_selections_, name); } WireloadSelection * @@ -633,7 +631,7 @@ LibertyLibrary::addOperatingConditions(OperatingConditions *op_cond) OperatingConditions * LibertyLibrary::findOperatingConditions(const char *name) { - return operating_conditions_.findKey(name); + return findKey(operating_conditions_, name); } OperatingConditions * @@ -656,7 +654,7 @@ LibertyLibrary::inputThreshold(const RiseFall *rf) const void LibertyLibrary::setInputThreshold(const RiseFall *rf, - float th) + float th) { input_threshold_[rf->index()] = th; } @@ -669,7 +667,7 @@ LibertyLibrary::outputThreshold(const RiseFall *rf) const void LibertyLibrary::setOutputThreshold(const RiseFall *rf, - float th) + float th) { output_threshold_[rf->index()] = th; } @@ -682,7 +680,7 @@ LibertyLibrary::slewLowerThreshold(const RiseFall *rf) const void LibertyLibrary::setSlewLowerThreshold(const RiseFall *rf, - float th) + float th) { slew_lower_threshold_[rf->index()] = th; } @@ -695,7 +693,7 @@ LibertyLibrary::slewUpperThreshold(const RiseFall *rf) const void LibertyLibrary::setSlewUpperThreshold(const RiseFall *rf, - float th) + float th) { slew_upper_threshold_[rf->index()] = th; } @@ -714,7 +712,7 @@ LibertyLibrary::setSlewDerateFromLibrary(float derate) LibertyCell * LibertyLibrary::makeScaledCell(const char *name, - const char *filename) + const char *filename) { LibertyCell *cell = new LibertyCell(this, name, filename); return cell; @@ -723,10 +721,10 @@ LibertyLibrary::makeScaledCell(const char *name, //////////////////////////////////////////////////////////////// void -LibertyLibrary::makeCornerMap(LibertyLibrary *lib, - int ap_index, - Network *network, - Report *report) +LibertyLibrary::makeSceneMap(LibertyLibrary *lib, + int ap_index, + Network *network, + Report *report) { LibertyCellIterator cell_iter(lib); while (cell_iter.hasNext()) { @@ -734,30 +732,30 @@ LibertyLibrary::makeCornerMap(LibertyLibrary *lib, const char *name = cell->name(); LibertyCell *link_cell = network->findLibertyCell(name); if (link_cell) - makeCornerMap(link_cell, cell, ap_index, report); + makeSceneMap(link_cell, cell, ap_index, report); } } // Map a cell linked in the network to the corresponding liberty cell -// to use for delay calculation at a corner. +// to use for delay calculation at a scene. void -LibertyLibrary::makeCornerMap(LibertyCell *link_cell, - LibertyCell *corner_cell, - int ap_index, - Report *report) +LibertyLibrary::makeSceneMap(LibertyCell *link_cell, + LibertyCell *scene_cell, + int ap_index, + Report *report) { - link_cell->setCornerCell(corner_cell, ap_index); - makeCornerMap(link_cell, corner_cell, true, ap_index, report); + link_cell->setSceneCell(scene_cell, ap_index); + makeSceneMap(link_cell, scene_cell, true, ap_index, report); // Check for brain damage in the other direction. - makeCornerMap(corner_cell, link_cell, false, ap_index, report); + makeSceneMap(scene_cell, link_cell, false, ap_index, report); } void -LibertyLibrary::makeCornerMap(LibertyCell *cell1, - LibertyCell *cell2, - bool link, - int ap_index, - Report *report) +LibertyLibrary::makeSceneMap(LibertyCell *cell1, + LibertyCell *cell2, + bool link, + int ap_index, + Report *report) { LibertyCellPortBitIterator port_iter1(cell1); while (port_iter1.hasNext()) { @@ -766,15 +764,15 @@ LibertyLibrary::makeCornerMap(LibertyCell *cell1, LibertyPort *port2 = cell2->findLibertyPort(port_name); if (port2) { if (link) - port1->setCornerPort(port2, ap_index); + port1->setScenePort(port2, ap_index); } else report->warn(1110, "cell %s/%s port %s not found in cell %s/%s.", - cell1->library()->name(), - cell1->name(), - port_name, - cell2->library()->name(), - cell2->name()); + cell1->library()->name(), + cell1->name(), + port_name, + cell2->library()->name(), + cell2->name()); } for (TimingArcSet *arc_set1 : cell1->timing_arc_sets_) { @@ -789,35 +787,35 @@ LibertyLibrary::makeCornerMap(LibertyCell *cell1, arc_itr1++, arc_itr2++) { TimingArc *arc1 = *arc_itr1; TimingArc *arc2 = *arc_itr2; - if (TimingArc::equiv(arc1, arc2)) - arc1->setCornerArc(arc2, ap_index); - } + if (TimingArc::equiv(arc1, arc2)) + arc1->setSceneArc(arc2, ap_index); + } } } else report->warn(1111, "cell %s/%s %s -> %s timing group %s not found in cell %s/%s.", - cell1->library()->name(), - cell1->name(), - arc_set1->from() ? arc_set1->from()->name() : "", - arc_set1->to()->name(), - arc_set1->role()->to_string().c_str(), - cell2->library()->name(), - cell2->name()); + cell1->library()->name(), + cell1->name(), + arc_set1->from() ? arc_set1->from()->name() : "", + arc_set1->to()->name(), + arc_set1->role()->to_string().c_str(), + cell2->library()->name(), + cell2->name()); } } void -LibertyLibrary::checkCorners(LibertyCell *cell, - Corners *corners, +LibertyLibrary::checkScenes(LibertyCell *cell, + const SceneSeq &scenes, Report *report) { - for (const Corner *corner : *corners) { + for (const Scene *scene : scenes) { for (auto min_max : MinMax::range()) { - if (!cell->checkCornerCell(corner, min_max)) + if (!cell->checkSceneCell(scene, min_max)) report->error(1112, "Liberty cell %s/%s for corner %s/%s not found.", cell->libertyLibrary()->name(), cell->name(), - corner->name(), + scene->name().c_str(), min_max->to_string().c_str()); } } @@ -852,7 +850,7 @@ LibertyLibrary::setDefaultOcvDerate(OcvDerate *derate) OcvDerate * LibertyLibrary::findOcvDerate(const char *derate_name) { - return ocv_derate_map_.findKey(derate_name); + return findKey(ocv_derate_map_, derate_name); } void @@ -863,24 +861,32 @@ LibertyLibrary::addOcvDerate(OcvDerate *derate) void LibertyLibrary::addSupplyVoltage(const char *supply_name, - float voltage) + float voltage) { supply_voltage_map_[supply_name] = voltage; } void LibertyLibrary::supplyVoltage(const char *supply_name, - // Return value. - float &voltage, - bool &exists) const + // Return value. + float &voltage, + bool &exists) const { - supply_voltage_map_.findKey(supply_name, voltage, exists); + auto itr = supply_voltage_map_.find(supply_name); + if (itr != supply_voltage_map_.end()) { + voltage = itr->second; + exists = true; + } + else { + voltage = 0.0; + exists = false; + } } bool LibertyLibrary::supplyExists(const char *supply_name) const { - return supply_voltage_map_.hasKey(supply_name); + return supply_voltage_map_.contains(supply_name); } DriverWaveform * @@ -922,8 +928,8 @@ LibertyCellIterator::next() //////////////////////////////////////////////////////////////// LibertyCell::LibertyCell(LibertyLibrary *library, - const char *name, - const char *filename) : + const char *name, + const char *filename) : ConcreteCell(name, filename, true, library), liberty_library_(library), area_(0.0), @@ -945,7 +951,6 @@ LibertyCell::LibertyCell(LibertyLibrary *library, test_cell_(nullptr), ocv_arc_depth_(0.0), ocv_derate_(nullptr), - is_disabled_constraint_(false), leakage_power_(0.0), leakage_power_exists_(false), has_internal_ports_(false), @@ -956,25 +961,25 @@ LibertyCell::LibertyCell(LibertyLibrary *library, LibertyCell::~LibertyCell() { - mode_defs_.deleteContents(); - latch_enables_.deleteContents(); + deleteContents(mode_defs_); + deleteContents(latch_enables_); - timing_arc_sets_.deleteContents(); - port_timing_arc_set_map_.deleteContents(); - timing_arc_set_from_map_.deleteContents(); - timing_arc_set_to_map_.deleteContents(); + deleteContents(timing_arc_sets_); + deleteContents(port_timing_arc_set_map_); + deleteContents(timing_arc_set_from_map_); + deleteContents(timing_arc_set_to_map_); deleteInternalPowerAttrs(); - internal_powers_.deleteContents(); - leakage_powers_.deleteContents(); + deleteContents(internal_powers_); + deleteContents(leakage_powers_); - sequentials_.deleteContents(); + deleteContents(sequentials_); delete statetable_; - bus_dcls_.deleteContents(); - scaled_cells_.deleteContents(); + deleteContents(bus_dcls_); + deleteContents(scaled_cells_); + deleteContents(ocv_derate_map_); delete test_cell_; - ocv_derate_map_.deleteContents(); } LibertyPort * @@ -995,9 +1000,9 @@ LibertyCell::findLibertyPortsMatching(PatternMatch *pattern) const if (port->hasMembers()) { LibertyPortMemberIterator port_iter2(port); while (port_iter2.hasNext()) { - LibertyPort *port2 = port_iter2.next(); - if (pattern->match(port2->name())) - matches.push_back(port2); + LibertyPort *port2 = port_iter2.next(); + if (pattern->match(port2->name())) + matches.push_back(port2); } } } @@ -1030,7 +1035,7 @@ LibertyCell::makeModeDef(const char *name) ModeDef * LibertyCell::findModeDef(const char *name) { - return mode_defs_.findKey(name); + return findKey(mode_defs_, name); } void @@ -1048,7 +1053,7 @@ LibertyCell::addBusDcl(BusDcl *bus_dcl) BusDcl * LibertyCell::findBusDcl(const char *name) const { - return bus_dcls_.findKey(name); + return findKey(bus_dcls_, name); } void @@ -1167,11 +1172,11 @@ LibertyCell::isBuffer() const bool LibertyCell::hasBufferFunc(const LibertyPort *input, - const LibertyPort *output) const + const LibertyPort *output) const { FuncExpr *func = output->function(); return func - && func->op() == FuncExpr::op_port + && func->op() == FuncExpr::Op::port && func->port() == input; } @@ -1189,19 +1194,19 @@ LibertyCell::isInverter() const bool LibertyCell::hasInverterFunc(const LibertyPort *input, - const LibertyPort *output) const + const LibertyPort *output) const { FuncExpr *func = output->function(); return func - && func->op() == FuncExpr::op_not - && func->left()->op() == FuncExpr::op_port + && func->op() == FuncExpr::Op::not_ + && func->left()->op() == FuncExpr::Op::port && func->left()->port() == input; } void LibertyCell::bufferPorts(// Return values. - LibertyPort *&input, - LibertyPort *&output) const + LibertyPort *&input, + LibertyPort *&output) const { input = nullptr; output = nullptr; @@ -1210,19 +1215,19 @@ LibertyCell::bufferPorts(// Return values. PortDirection *dir = port->direction(); if (dir->isInput()) { if (input) { - // More than one input. - input = nullptr; - output = nullptr; - break; + // More than one input. + input = nullptr; + output = nullptr; + break; } input = port; } else if (dir->isOutput()) { if (output) { - // More than one output. - input = nullptr; - output = nullptr; - break; + // More than one output. + input = nullptr; + output = nullptr; + break; } output = port; } @@ -1276,7 +1281,7 @@ LibertyCell::addInternalPowerAttrs(InternalPowerAttrs *attrs) void LibertyCell::deleteInternalPowerAttrs() { - for (auto attrs : internal_power_attrs_) { + for (InternalPowerAttrs *attrs : internal_power_attrs_) { attrs->deleteContents(); delete attrs; } @@ -1297,8 +1302,8 @@ LibertyCell::setLeakagePower(float leakage) void LibertyCell::leakagePower(// Return values. - float &leakage, - bool &exists) const + float &leakage, + bool &exists) const { leakage = leakage_power_; exists = leakage_power_exists_; @@ -1306,8 +1311,8 @@ LibertyCell::leakagePower(// Return values. void LibertyCell::finish(bool infer_latches, - Report *report, - Debug *debug) + Report *report, + Debug *debug) { translatePresetClrCheckRoles(); makeTimingArcMap(report); @@ -1325,14 +1330,14 @@ LibertyCell::findDefaultCondArcs() bool has_cond_arcs = false; for (auto set : *sets) { if (set->cond()) { - has_cond_arcs = true; - break; + has_cond_arcs = true; + break; } } if (has_cond_arcs) { for (auto set : *sets) { - if (!set->cond()) - set->setIsCondDefault(true); + if (!set->cond()) + set->setIsCondDefault(true); } } } @@ -1352,11 +1357,11 @@ LibertyCell::translatePresetClrCheckRoles() if (!pre_clr_ports.empty()) { for (auto arc_set : timing_arc_sets_) { - if (pre_clr_ports.findKey(arc_set->to())) { - if (arc_set->role() == TimingRole::setup()) - arc_set->setRole(TimingRole::recovery()); - else if (arc_set->role() == TimingRole::hold()) - arc_set->setRole(TimingRole::removal()); + if (findKey(pre_clr_ports, arc_set->to())) { + if (arc_set->role() == TimingRole::setup()) + arc_set->setRole(TimingRole::recovery()); + else if (arc_set->role() == TimingRole::hold()) + arc_set->setRole(TimingRole::removal()); } } } @@ -1368,22 +1373,22 @@ LibertyCell::makeTimingArcMap(Report *) // Filter duplicate timing arcs, keeping the later definition. for (auto arc_set : timing_arc_sets_) // The last definition will be left in the set. - timing_arc_set_map_.insert(arc_set); + timing_arc_set_set_.insert(arc_set); // Prune the arc sets not in the map. int j = 0; for (size_t i = 0; i < timing_arc_sets_.size(); i++) { TimingArcSet *arc_set = timing_arc_sets_[i]; - TimingArcSet *match = timing_arc_set_map_.findKey(arc_set); + TimingArcSet *match = findKey(timing_arc_set_set_, arc_set); if (match != arc_set) { // Unfortunately these errors are common in some brain damaged // libraries. // report->warn("cell %s/%s has duplicate %s -> %s %s timing groups.", - // library_->name(), - // name_, - // match->from()->name(), - // match->to()->name(), - // match->role()->asString()); + // library_->name(), + // name_, + // match->from()->name(), + // match->to()->name(), + // match->role()->asString()); delete arc_set; } else @@ -1392,7 +1397,7 @@ LibertyCell::makeTimingArcMap(Report *) } timing_arc_sets_.resize(j); - if (timing_arc_set_map_.size() != timing_arc_sets_.size()) + if (timing_arc_sets_.size() != timing_arc_sets_.size()) criticalError(1121, "timing arc count mismatch"); } @@ -1403,7 +1408,8 @@ LibertyCell::makeTimingArcPortMaps() LibertyPort *from = arc_set->from(); LibertyPort *to = arc_set->to(); LibertyPortPair port_pair(from, to); - TimingArcSetSeq *sets = port_timing_arc_set_map_.findKey(port_pair); + TimingArcSetSeq *sets = + findKey(port_timing_arc_set_map_, port_pair); if (sets == nullptr) { // First arc set for from/to ports. sets = new TimingArcSetSeq; @@ -1411,14 +1417,14 @@ LibertyCell::makeTimingArcPortMaps() } sets->push_back(arc_set); - sets = timing_arc_set_from_map_.findKey(from); + sets = findKey(timing_arc_set_from_map_, from); if (sets == nullptr) { sets = new TimingArcSetSeq; timing_arc_set_from_map_[from] = sets; } sets->push_back(arc_set); - sets = timing_arc_set_to_map_.findKey(to); + sets = findKey(timing_arc_set_to_map_, to); if (sets == nullptr) { sets = new TimingArcSetSeq; timing_arc_set_to_map_[to] = sets; @@ -1429,17 +1435,17 @@ LibertyCell::makeTimingArcPortMaps() const TimingArcSetSeq & LibertyCell::timingArcSets(const LibertyPort *from, - const LibertyPort *to) const + const LibertyPort *to) const { TimingArcSetSeq *arc_sets = nullptr; if (from && to) { LibertyPortPair port_pair(from, to); - arc_sets = port_timing_arc_set_map_.findKey(port_pair); + arc_sets = findKey(port_timing_arc_set_map_, port_pair); } else if (from) - arc_sets = timing_arc_set_from_map_.findKey(from); + arc_sets = findKey(timing_arc_set_from_map_, from); else if (to) - arc_sets = timing_arc_set_to_map_.findKey(to); + arc_sets = findKey(timing_arc_set_to_map_, to); if (arc_sets) return *arc_sets; @@ -1450,9 +1456,9 @@ LibertyCell::timingArcSets(const LibertyPort *from, } TimingArcSet * -LibertyCell::findTimingArcSet(TimingArcSet *key) const +LibertyCell::findTimingArcSet(TimingArcSet *arc_set) const { - return timing_arc_set_map_.findKey(key); + return findKey(timing_arc_set_set_, arc_set); } TimingArcSet * @@ -1470,21 +1476,21 @@ LibertyCell::timingArcSetCount() const bool LibertyCell::hasTimingArcs(LibertyPort *port) const { - return timing_arc_set_from_map_.findKey(port) - || timing_arc_set_to_map_.findKey(port); + return findKey(timing_arc_set_from_map_, port) + || findKey(timing_arc_set_to_map_, port); } void LibertyCell::makeSequential(int size, - bool is_register, - FuncExpr *clk, - FuncExpr *data, - FuncExpr *clear, - FuncExpr *preset, - LogicValue clr_preset_out, - LogicValue clr_preset_out_inv, - LibertyPort *output, - LibertyPort *output_inv) + bool is_register, + FuncExpr *clk, + FuncExpr *data, + FuncExpr *clear, + FuncExpr *preset, + LogicValue clr_preset_out, + LogicValue clr_preset_out_inv, + LibertyPort *output, + LibertyPort *output_inv) { for (int bit = 0; bit < size; bit++) { FuncExpr *clk_bit = nullptr; @@ -1506,9 +1512,9 @@ LibertyCell::makeSequential(int size, if (output_inv && output_inv->hasMembers()) out_inv_bit = output_inv->findLibertyMember(bit); Sequential *seq = new Sequential(is_register, clk_bit, data_bit, - clear_bit,preset_bit, - clr_preset_out, clr_preset_out_inv, - out_bit, out_inv_bit); + clear_bit,preset_bit, + clr_preset_out, clr_preset_out_inv, + out_bit, out_inv_bit); sequentials_.push_back(seq); port_to_seq_map_[seq->output()] = seq; port_to_seq_map_[seq->outputInv()] = seq; @@ -1518,7 +1524,7 @@ LibertyCell::makeSequential(int size, Sequential * LibertyCell::outputPortSequential(LibertyPort *port) { - return port_to_seq_map_.findKey(port); + return findKey(port_to_seq_map_, port); } bool @@ -1538,7 +1544,7 @@ LibertyCell::makeStatetable(LibertyPortSeq &input_ports, void LibertyCell::addScaledCell(OperatingConditions *op_cond, - LibertyCell *scaled_cell) + LibertyCell *scaled_cell) { scaled_cells_[op_cond] = scaled_cell; @@ -1567,9 +1573,9 @@ LibertyCell::addScaledCell(OperatingConditions *op_cond, const TimingArc *scaled_arc = *arc_itr2; if (TimingArc::equiv(arc, scaled_arc)) { - TimingModel *model = scaled_arc->model(); - model->setIsScaled(true); - arc->addScaledModel(op_cond, model); + TimingModel *model = scaled_arc->model(); + model->setIsScaled(true); + arc->addScaledModel(op_cond, model); } } } @@ -1594,53 +1600,41 @@ LibertyCell::setTestCell(TestCell *test) test_cell_ = test; } -void -LibertyCell::setIsDisabledConstraint(bool is_disabled) +LibertyCell * +LibertyCell::sceneCell(const Scene *scene, + const MinMax *min_max) { - is_disabled_constraint_ = is_disabled; + return sceneCell(scene->libertyIndex(min_max)); } LibertyCell * -LibertyCell::cornerCell(const Corner *corner, - const MinMax *min_max) +LibertyCell::sceneCell(int ap_index) { - return cornerCell(corner->libertyIndex(min_max)); -} - -LibertyCell * -LibertyCell::cornerCell(const DcalcAnalysisPt *dcalc_ap) -{ - return cornerCell(dcalc_ap->libertyIndex()); -} - -LibertyCell * -LibertyCell::cornerCell(int ap_index) -{ - if (corner_cells_.empty()) + if (scene_cells_.empty()) return this; - else if (ap_index < static_cast(corner_cells_.size())) - return corner_cells_[ap_index]; + else if (ap_index < static_cast(scene_cells_.size())) + return scene_cells_[ap_index]; else return nullptr; } bool -LibertyCell::checkCornerCell(const Corner *corner, +LibertyCell::checkSceneCell(const Scene *scene, const MinMax *min_max) const { - unsigned lib_index = corner->libertyIndex(min_max); - return corner_cells_.empty() - || (lib_index < corner_cells_.size() - && corner_cells_[lib_index]); + unsigned lib_index = scene->libertyIndex(min_max); + return scene_cells_.empty() + || (lib_index < scene_cells_.size() + && scene_cells_[lib_index]); } void -LibertyCell::setCornerCell(LibertyCell *corner_cell, - int ap_index) +LibertyCell::setSceneCell(LibertyCell *scene_cell, + int ap_index) { - if (ap_index >= static_cast(corner_cells_.size())) - corner_cells_.resize(ap_index + 1); - corner_cells_[ap_index] = corner_cell; + if (ap_index >= static_cast(scene_cells_.size())) + scene_cells_.resize(ap_index + 1); + scene_cells_[ap_index] = scene_cell; } //////////////////////////////////////////////////////////////// @@ -1675,7 +1669,7 @@ LibertyCell::setOcvDerate(OcvDerate *derate) OcvDerate * LibertyCell::findOcvDerate(const char *derate_name) { - return ocv_derate_map_.findKey(derate_name); + return findKey(ocv_derate_map_, derate_name); } void @@ -1691,13 +1685,13 @@ class LatchEnable { public: LatchEnable(LibertyPort *data, - LibertyPort *enable, - const RiseFall *enable_edge, - FuncExpr *enable_func, - LibertyPort *output, - TimingArcSet *d_to_q, - TimingArcSet *en_to_q, - TimingArcSet *setup_check); + LibertyPort *enable, + const RiseFall *enable_edge, + FuncExpr *enable_func, + LibertyPort *output, + TimingArcSet *d_to_q, + TimingArcSet *en_to_q, + TimingArcSet *setup_check); LibertyPort *data() const { return data_; } LibertyPort *output() const { return output_; } LibertyPort *enable() const { return enable_; } @@ -1719,13 +1713,13 @@ private: }; LatchEnable::LatchEnable(LibertyPort *data, - LibertyPort *enable, - const RiseFall *enable_edge, - FuncExpr *enable_func, - LibertyPort *output, - TimingArcSet *d_to_q, - TimingArcSet *en_to_q, - TimingArcSet *setup_check) : + LibertyPort *enable, + const RiseFall *enable_edge, + FuncExpr *enable_func, + LibertyPort *output, + TimingArcSet *d_to_q, + TimingArcSet *en_to_q, + TimingArcSet *setup_check) : data_(data), enable_(enable), enable_edge_(enable_edge), @@ -1742,20 +1736,20 @@ LatchEnable::LatchEnable(LibertyPort *data, // Use timing arcs rather than sequentials (because they are optional). void LibertyCell::makeLatchEnables(Report *report, - Debug *debug) + Debug *debug) { if (hasSequentials() || hasInferedRegTimingArcs()) { for (auto en_to_q : timing_arc_sets_) { if (en_to_q->role() == TimingRole::latchEnToQ()) { - LibertyPort *en = en_to_q->from(); - LibertyPort *q = en_to_q->to(); + LibertyPort *en = en_to_q->from(); + LibertyPort *q = en_to_q->to(); for (TimingArcSet *d_to_q : timingArcSets(nullptr, q)) { - if (d_to_q->role() == TimingRole::latchDtoQ() + if (d_to_q->role() == TimingRole::latchDtoQ() && condMatch(en_to_q, d_to_q)) { - LibertyPort *d = d_to_q->from(); + LibertyPort *d = d_to_q->from(); const RiseFall *en_rf = en_to_q->isRisingFallingEdge(); - if (en_rf) { + if (en_rf) { TimingArcSet *setup_check = findLatchSetup(d, en, en_rf, q, d_to_q, report); LatchEnable *latch_enable = makeLatchEnable(d, en, en_rf, q, d_to_q, @@ -1784,7 +1778,7 @@ LibertyCell::makeLatchEnables(Report *report, } } } - } + } } } } @@ -1845,15 +1839,15 @@ LibertyCell::findLatchSetup(const LibertyPort *d, FuncExpr * LibertyCell::findLatchEnableFunc(const LibertyPort *d, - const LibertyPort *en, + const LibertyPort *en, const RiseFall *en_rf) const { for (auto seq : sequentials_) { if (seq->isLatch() - && seq->data() - && seq->data()->hasPort(d) - && seq->clock() - && seq->clock()->hasPort(en)) { + && seq->data() + && seq->data()->hasPort(d) + && seq->clock() + && seq->clock()->hasPort(en)) { FuncExpr *en_func = seq->clock(); TimingSense en_sense = en_func->portTimingSense(en); if ((en_sense == TimingSense::positive_unate @@ -1868,17 +1862,17 @@ LibertyCell::findLatchEnableFunc(const LibertyPort *d, LatchEnable * LibertyCell::makeLatchEnable(LibertyPort *d, - LibertyPort *en, + LibertyPort *en, const RiseFall *en_rf, - LibertyPort *q, - TimingArcSet *d_to_q, - TimingArcSet *en_to_q, - TimingArcSet *setup_check, - Debug *debug) + LibertyPort *q, + TimingArcSet *d_to_q, + TimingArcSet *en_to_q, + TimingArcSet *setup_check, + Debug *debug) { FuncExpr *en_func = findLatchEnableFunc(d, en, en_rf); LatchEnable *latch_enable = new LatchEnable(d, en, en_rf, en_func, q, - d_to_q, en_to_q, setup_check); + d_to_q, en_to_q, setup_check); latch_enables_.push_back(latch_enable); latch_d_to_q_map_[d_to_q] = latch_enable; latch_check_map_[setup_check] = latch_enable; @@ -1902,25 +1896,25 @@ LibertyCell::inferLatchRoles(Report *report, { if (hasInferedRegTimingArcs()) { // Hunt down potential latch D/EN/Q triples. - LatchEnableSet latch_enables; + std::set latch_enables; for (TimingArcSet *en_to_q : timingArcSets()) { // Locate potential d->q arcs from reg clk->q arcs. if (en_to_q->role() == TimingRole::regClkToQ()) { - LibertyPort *en = en_to_q->from(); - LibertyPort *q = en_to_q->to(); + LibertyPort *en = en_to_q->from(); + LibertyPort *q = en_to_q->to(); for (TimingArcSet *d_to_q : timingArcSets(nullptr, q)) { - // Look for combinational d->q arcs. - const TimingRole *d_to_q_role = d_to_q->role(); - if (((d_to_q_role == TimingRole::combinational() + // Look for combinational d->q arcs. + const TimingRole *d_to_q_role = d_to_q->role(); + if (((d_to_q_role == TimingRole::combinational() && d_to_q->arcCount() == 2 && (d_to_q->sense() == TimingSense::positive_unate || d_to_q->sense() == TimingSense::negative_unate)) // Previously identified as D->Q arc. || d_to_q_role == TimingRole::latchDtoQ()) && condMatch(en_to_q, d_to_q)) { - LibertyPort *d = d_to_q->from(); + LibertyPort *d = d_to_q->from(); const RiseFall *en_rf = en_to_q->isRisingFallingEdge(); - if (en_rf) { + if (en_rf) { TimingArcSet *setup_check = findLatchSetup(d, en, en_rf, q, en_to_q, report); makeLatchEnable(d, en, en_rf, q, d_to_q, en_to_q, setup_check, debug); @@ -1928,7 +1922,7 @@ LibertyCell::inferLatchRoles(Report *report, en_to_q->setRole(TimingRole::latchEnToQ()); } } - } + } } } } @@ -1936,12 +1930,12 @@ LibertyCell::inferLatchRoles(Report *report, void LibertyCell::latchEnable(const TimingArcSet *d_to_q_set, - // Return values. - const LibertyPort *&enable_port, - const FuncExpr *&enable_func, - const RiseFall *&enable_edge) const + // Return values. + const LibertyPort *&enable_port, + const FuncExpr *&enable_func, + const RiseFall *&enable_edge) const { - LatchEnable *latch_enable = latch_d_to_q_map_.findKey(d_to_q_set); + LatchEnable *latch_enable = findKey(latch_d_to_q_map_, d_to_q_set); if (latch_enable) { enable_port = latch_enable->enable(); enable_func = latch_enable->enableFunc(); @@ -1957,7 +1951,7 @@ LibertyCell::latchEnable(const TimingArcSet *d_to_q_set, const RiseFall * LibertyCell::latchCheckEnableEdge(TimingArcSet *check_set) { - LatchEnable *latch_enable = latch_check_map_.findKey(check_set); + LatchEnable *latch_enable = findKey(latch_check_map_, check_set); if (latch_enable) return latch_enable->enableEdge(); else @@ -1965,7 +1959,7 @@ LibertyCell::latchCheckEnableEdge(TimingArcSet *check_set) } void -LibertyCell::ensureVoltageWaveforms(const DcalcAnalysisPtSeq &dcalc_aps) +LibertyCell::ensureVoltageWaveforms(const SceneSeq &scenes) { if (!have_voltage_waveforms_) { LockGuard lock(waveform_lock_); @@ -1978,12 +1972,14 @@ LibertyCell::ensureVoltageWaveforms(const DcalcAnalysisPtSeq &dcalc_aps) criticalError(1120, "library missing vdd"); for (TimingArcSet *arc_set : timingArcSets()) { for (TimingArc *arc : arc_set->arcs()) { - for (const DcalcAnalysisPt *dcalc_ap : dcalc_aps) { - GateTableModel *model = arc->gateTableModel(dcalc_ap); - if (model) { - OutputWaveforms *output_waveforms = model->outputWaveforms(); - if (output_waveforms) - output_waveforms->ensureVoltageWaveforms(vdd); + for (const Scene *scene : scenes) { + for (const MinMax *min_max : MinMax::range()) { + GateTableModel *model = arc->gateTableModel(scene, min_max); + if (model) { + OutputWaveforms *output_waveforms = model->outputWaveforms(); + if (output_waveforms) + output_waveforms->ensureVoltageWaveforms(vdd); + } } } } @@ -2070,13 +2066,13 @@ LibertyCellPortBitIterator::next() //////////////////////////////////////////////////////////////// LibertyPort::LibertyPort(LibertyCell *cell, - const char *name, - bool is_bus, - BusDcl *bus_dcl, + const char *name, + bool is_bus, + BusDcl *bus_dcl, int from_index, - int to_index, - bool is_bundle, - ConcretePortSeq *members) : + int to_index, + bool is_bundle, + ConcretePortSeq *members) : ConcretePort(name, is_bus, from_index, to_index, is_bundle, members, cell), liberty_cell_(cell), bus_dcl_(bus_dcl), @@ -2107,7 +2103,6 @@ LibertyPort::LibertyPort(LibertyCell *cell, isolation_cell_enable_(false), level_shifter_data_(false), is_switch_(false), - is_disabled_constraint_(false), is_pad_(false) { liberty_port_ = this; @@ -2236,8 +2231,8 @@ LibertyPort::setCapacitance(float cap) void LibertyPort::setCapacitance(const RiseFall *rf, - const MinMax *min_max, - float cap) + const MinMax *min_max, + float cap) { capacitance_.setValue(rf, min_max, cap); if (hasMembers()) { @@ -2269,7 +2264,7 @@ LibertyPort::capacitance(const MinMax *min_max) const float LibertyPort::capacitance(const RiseFall *rf, - const MinMax *min_max) const + const MinMax *min_max) const { float cap; bool exists; @@ -2282,19 +2277,19 @@ LibertyPort::capacitance(const RiseFall *rf, void LibertyPort::capacitance(const RiseFall *rf, - const MinMax *min_max, - // Return values. - float &cap, - bool &exists) const + const MinMax *min_max, + // Return values. + float &cap, + bool &exists) const { capacitance_.value(rf, min_max, cap, exists); } float LibertyPort::capacitance(const RiseFall *rf, - const MinMax *min_max, - const OperatingConditions *op_cond, - const Pvt *pvt) const + const MinMax *min_max, + const OperatingConditions *op_cond, + const Pvt *pvt) const { if (scaled_ports_) { LibertyPort *scaled_port = (*scaled_ports_)[op_cond]; @@ -2325,22 +2320,22 @@ LibertyPort::driveResistance() const // Min/max "drive" for all cell timing arcs. float LibertyPort::driveResistance(const RiseFall *rf, - const MinMax *min_max) const + const MinMax *min_max) const { float max_drive = min_max->initValue(); bool found_drive = false; for (TimingArcSet *arc_set : liberty_cell_->timingArcSets(nullptr, this)) { if (!arc_set->role()->isTimingCheck()) { for (TimingArc *arc : arc_set->arcs()) { - if (rf == nullptr - || arc->toEdge()->asRiseFall() == rf) { + if (rf == nullptr + || arc->toEdge()->asRiseFall() == rf) { float drive = arc->driveResistance(); if (drive > 0.0) { if (min_max->compare(drive, max_drive)) max_drive = drive; - found_drive = true; - } - } + found_drive = true; + } + } } } } @@ -2358,7 +2353,7 @@ LibertyPort::intrinsicDelay(const StaState *sta) const ArcDelay LibertyPort::intrinsicDelay(const RiseFall *rf, - const MinMax *min_max, + const MinMax *min_max, const StaState *sta) const { ArcDelay max_delay = min_max->initValue(); @@ -2366,14 +2361,14 @@ LibertyPort::intrinsicDelay(const RiseFall *rf, for (TimingArcSet *arc_set : liberty_cell_->timingArcSets(nullptr, this)) { if (!arc_set->role()->isTimingCheck()) { for (TimingArc *arc : arc_set->arcs()) { - if (rf == nullptr - || arc->toEdge()->asRiseFall() == rf) { + if (rf == nullptr + || arc->toEdge()->asRiseFall() == rf) { ArcDelay delay = arc->intrinsicDelay(); if (delayGreater(delay, 0.0, sta)) { - if (delayGreater(delay, max_delay, min_max, sta)) - max_delay = delay; - found_delay = true; - } + if (delayGreater(delay, max_delay, min_max, sta)) + max_delay = delay; + found_delay = true; + } } } } @@ -2411,7 +2406,7 @@ LibertyPort::setTristateEnable(FuncExpr *enable) while (member_iter.hasNext()) { LibertyPort *port_bit = member_iter.next(); FuncExpr *sub_expr = - (enable) ? enable->bitSubExpr(port_bit->busBitIndex()) : nullptr; + (enable) ? enable->bitSubExpr(port_bit->busBitIndex()) : nullptr; port_bit->setTristateEnable(sub_expr); } } @@ -2419,16 +2414,16 @@ LibertyPort::setTristateEnable(FuncExpr *enable) void LibertyPort::slewLimit(const MinMax *min_max, - // Return values. - float &limit, - bool &exists) const + // Return values. + float &limit, + bool &exists) const { slew_limit_.value(min_max, limit, exists); } void LibertyPort::setSlewLimit(float slew, - const MinMax *min_max) + const MinMax *min_max) { slew_limit_.setValue(min_max, slew); setMemberMinMaxFloat(slew, min_max, &LibertyPort::setSlewLimit); @@ -2436,16 +2431,16 @@ LibertyPort::setSlewLimit(float slew, void LibertyPort::capacitanceLimit(const MinMax *min_max, - // Return values. - float &limit, - bool &exists) const + // Return values. + float &limit, + bool &exists) const { return cap_limit_.value(min_max, limit, exists); } void LibertyPort::setCapacitanceLimit(float cap, - const MinMax *min_max) + const MinMax *min_max) { cap_limit_.setValue(min_max, cap); setMemberMinMaxFloat(cap, min_max, &LibertyPort::setCapacitanceLimit); @@ -2453,8 +2448,8 @@ LibertyPort::setCapacitanceLimit(float cap, void LibertyPort::fanoutLoad(// Return values. - float &fanout_load, - bool &exists) const + float &fanout_load, + bool &exists) const { fanout_load = fanout_load_; exists = fanout_load_exists_; @@ -2470,25 +2465,25 @@ LibertyPort::setFanoutLoad(float fanout_load) void LibertyPort::fanoutLimit(const MinMax *min_max, - // Return values. - float &limit, - bool &exists) const + // Return values. + float &limit, + bool &exists) const { return fanout_limit_.value(min_max, limit, exists); } void LibertyPort::setFanoutLimit(float fanout, - const MinMax *min_max) + const MinMax *min_max) { fanout_limit_.setValue(min_max, fanout); } void LibertyPort::minPeriod(const OperatingConditions *op_cond, - const Pvt *pvt, - float &min_period, - bool &exists) const + const Pvt *pvt, + float &min_period, + bool &exists) const { if (scaled_ports_) { LibertyPort *scaled_port = (*scaled_ports_)[op_cond]; @@ -2499,13 +2494,13 @@ LibertyPort::minPeriod(const OperatingConditions *op_cond, } LibertyLibrary *lib = liberty_cell_->libertyLibrary(); min_period = min_period_ * lib->scaleFactor(ScaleFactorType::min_period, - liberty_cell_, pvt); + liberty_cell_, pvt); exists = min_period_exists_; } void LibertyPort::minPeriod(float &min_period, - bool &exists) const + bool &exists) const { min_period = min_period_; exists = min_period_exists_; @@ -2527,8 +2522,8 @@ LibertyPort::setMinPeriod(float min_period) void LibertyPort::minPulseWidth(const RiseFall *hi_low, - float &min_width, - bool &exists) const + float &min_width, + bool &exists) const { int hi_low_index = hi_low->index(); min_width = min_pulse_width_[hi_low_index]; @@ -2537,7 +2532,7 @@ LibertyPort::minPulseWidth(const RiseFall *hi_low, void LibertyPort::setMinPulseWidth(const RiseFall *hi_low, - float min_width) + float min_width) { int hi_low_index = hi_low->index(); min_pulse_width_[hi_low_index] = min_width; @@ -2553,18 +2548,18 @@ LibertyPort::setMinPulseWidth(const RiseFall *hi_low, bool LibertyPort::equiv(const LibertyPort *port1, - const LibertyPort *port2) + const LibertyPort *port2) { return (port1 == nullptr && port2 == nullptr) || (port1 != nullptr && port2 != nullptr - && stringEq(port1->name(), port2->name()) - && port1->direction() == port2->direction() - && port1->pwr_gnd_type_ == port2->pwr_gnd_type_); + && stringEq(port1->name(), port2->name()) + && port1->direction() == port2->direction() + && port1->pwr_gnd_type_ == port2->pwr_gnd_type_); } bool LibertyPort::less(const LibertyPort *port1, - const LibertyPort *port2) + const LibertyPort *port2) { if (port1 == nullptr && port2 != nullptr) return true; @@ -2582,7 +2577,7 @@ LibertyPort::less(const LibertyPort *port1, void LibertyPort::addScaledPort(OperatingConditions *op_cond, - LibertyPort *scaled_port) + LibertyPort *scaled_port) { if (scaled_ports_ == nullptr) scaled_ports_ = new ScaledPortMap; @@ -2683,18 +2678,12 @@ LibertyPort::setIsSwitch(bool is_switch) void LibertyPort::setPulseClk(const RiseFall *trigger, - const RiseFall *sense) + const RiseFall *sense) { pulse_clk_trigger_ = trigger; pulse_clk_sense_ = sense; } -void -LibertyPort::setIsDisabledConstraint(bool is_disabled) -{ - is_disabled_constraint_ = is_disabled; -} - void LibertyPort::setIsPad(bool is_pad) { @@ -2702,60 +2691,48 @@ LibertyPort::setIsPad(bool is_pad) } LibertyPort * -LibertyPort::cornerPort(const Corner *corner, - const MinMax *min_max) +LibertyPort::scenePort(const Scene *scene, + const MinMax *min_max) { - return cornerPort(corner->libertyIndex(min_max)); + return scenePort(scene->libertyIndex(min_max)); } const LibertyPort * -LibertyPort::cornerPort(const Corner *corner, - const MinMax *min_max) const +LibertyPort::scenePort(const Scene *scene, + const MinMax *min_max) const { - return cornerPort(corner->libertyIndex(min_max)); + return scenePort(scene->libertyIndex(min_max)); } LibertyPort * -LibertyPort::cornerPort(const DcalcAnalysisPt *dcalc_ap) +LibertyPort::scenePort(int ap_index) { - return cornerPort(dcalc_ap->libertyIndex()); -} - -const LibertyPort * -LibertyPort::cornerPort(const DcalcAnalysisPt *dcalc_ap) const -{ - return cornerPort(dcalc_ap->libertyIndex()); -} - -LibertyPort * -LibertyPort::cornerPort(int ap_index) -{ - if (corner_ports_.empty()) + if (scene_ports_.empty()) return this; - else if (ap_index < static_cast(corner_ports_.size())) - return corner_ports_[ap_index]; + else if (ap_index < static_cast(scene_ports_.size())) + return scene_ports_[ap_index]; else return nullptr; } const LibertyPort * -LibertyPort::cornerPort(int ap_index) const +LibertyPort::scenePort(int ap_index) const { - if (corner_ports_.empty()) + if (scene_ports_.empty()) return this; - else if (ap_index < static_cast(corner_ports_.size())) - return corner_ports_[ap_index]; + else if (ap_index < static_cast(scene_ports_.size())) + return scene_ports_[ap_index]; else return nullptr; } void -LibertyPort::setCornerPort(LibertyPort *corner_port, - int ap_index) +LibertyPort::setScenePort(LibertyPort *scene_port, + int ap_index) { - if (ap_index >= static_cast(corner_ports_.size())) - corner_ports_.resize(ap_index + 1); - corner_ports_[ap_index] = corner_port; + if (ap_index >= static_cast(scene_ports_.size())) + scene_ports_.resize(ap_index + 1); + scene_ports_[ap_index] = scene_port; } const char * @@ -2892,8 +2869,8 @@ LibertyPort::setClkTreeDelay(const TableModel *model, void LibertyPort::setMemberFlag(bool value, - const std::function &setter) + const std::function &setter) { if (hasMembers()) { LibertyPortMemberIterator member_iter(this); @@ -2906,8 +2883,8 @@ LibertyPort::setMemberFlag(bool value, void LibertyPort::setMemberFloat(float value, - const std::function &setter) + const std::function &setter) { if (hasMembers()) { LibertyPortMemberIterator member_iter(this); @@ -2920,10 +2897,10 @@ LibertyPort::setMemberFloat(float value, void LibertyPort::setMemberMinMaxFloat(float value, - const MinMax *min_max, - const std::function &setter) + const MinMax *min_max, + const std::function &setter) { if (hasMembers()) { LibertyPortMemberIterator member_iter(this); @@ -2955,20 +2932,20 @@ LibertyPortLess::operator()(const LibertyPort *port1, bool LibertyPortNameLess::operator()(const LibertyPort *port1, - const LibertyPort *port2) const + const LibertyPort *port2) const { return stringLess(port1->name(), port2->name()); } bool LibertyPortPairLess::operator()(const LibertyPortPair &pair1, - const LibertyPortPair &pair2) const + const LibertyPortPair &pair2) const { ObjectId id1 = pair1.first ? pair1.first->id() : 0; ObjectId id2 = pair2.first ? pair2.first->id() : 0; return id1 < id2 || (id1 == id2 - && pair1.second->id() < pair2.second->id()); + && pair1.second->id() < pair2.second->id()); } //////////////////////////////////////////////////////////////// @@ -2998,8 +2975,8 @@ LibertyPortMemberIterator::next() //////////////////////////////////////////////////////////////// BusDcl::BusDcl(const char *name, - int from, - int to) : + int from, + int to) : name_(name), from_(from), to_(to) @@ -3015,13 +2992,13 @@ ModeDef::ModeDef(const char *name) : ModeDef::~ModeDef() { - values_.deleteContents(); + deleteContents(values_); } ModeValueDef * ModeDef::defineValue(const char *value, - FuncExpr *cond, - const char *sdf_cond) + FuncExpr *cond, + const char *sdf_cond) { ModeValueDef *val_def = new ModeValueDef(value, cond, sdf_cond); values_[val_def->value()] = val_def; @@ -3037,8 +3014,8 @@ ModeDef::findValueDef(const char *value) //////////////////////////////////////////////////////////////// ModeValueDef::ModeValueDef(const char *value, - FuncExpr *cond, - const char *sdf_cond) : + FuncExpr *cond, + const char *sdf_cond) : value_(value), cond_(cond), sdf_cond_(sdf_cond ? sdf_cond : "") @@ -3111,8 +3088,8 @@ TableTemplate::setAxis3(TableAxisPtr axis) //////////////////////////////////////////////////////////////// Pvt::Pvt(float process, - float voltage, - float temperature) : + float voltage, + float temperature) : process_(process), voltage_(voltage), temperature_(temperature) @@ -3146,10 +3123,10 @@ OperatingConditions::OperatingConditions(const char *name) : } OperatingConditions::OperatingConditions(const char *name, - float process, - float voltage, - float temperature, - WireloadTree wire_load_tree) : + float process, + float voltage, + float temperature, + WireloadTree wire_load_tree) : Pvt(process, voltage, temperature), name_(name), wire_load_tree_(wire_load_tree) @@ -3246,7 +3223,7 @@ ScaleFactors::ScaleFactors(const char *name) : for (int type = 0; type < scale_factor_type_count; type++) { for (int pvt = 0; pvt < scale_factor_pvt_count; pvt++) { for (auto rf_index : RiseFall::rangeIndex()) { - scales_[type][pvt][rf_index] = 0.0; + scales_[type][pvt][rf_index] = 0.0; } } } @@ -3254,40 +3231,40 @@ ScaleFactors::ScaleFactors(const char *name) : void ScaleFactors::setScale(ScaleFactorType type, - ScaleFactorPvt pvt, - const RiseFall *rf, - float scale) + ScaleFactorPvt pvt, + const RiseFall *rf, + float scale) { scales_[int(type)][int(pvt)][rf->index()] = scale; } void ScaleFactors::setScale(ScaleFactorType type, - ScaleFactorPvt pvt, - float scale) + ScaleFactorPvt pvt, + float scale) { scales_[int(type)][int(pvt)][0] = scale; } float ScaleFactors::scale(ScaleFactorType type, - ScaleFactorPvt pvt, - const RiseFall *rf) + ScaleFactorPvt pvt, + const RiseFall *rf) { return scales_[int(type)][int(pvt)][rf->index()]; } float ScaleFactors::scale(ScaleFactorType type, - ScaleFactorPvt pvt, - int rf_index) + ScaleFactorPvt pvt, + int rf_index) { return scales_[int(type)][int(pvt)][rf_index]; } float ScaleFactors::scale(ScaleFactorType type, - ScaleFactorPvt pvt) + ScaleFactorPvt pvt) { return scales_[int(type)][int(pvt)][0]; } @@ -3306,15 +3283,15 @@ ScaleFactors::print() printf("%10s ", scaleFactorTypeName(type)); for (int pvt_index = 0; pvt_index < scale_factor_pvt_count; pvt_index++) { if (scaleFactorTypeRiseFallSuffix(type) - || scaleFactorTypeRiseFallPrefix(type) - || scaleFactorTypeLowHighSuffix(type)) { - printf(" %.3f,%.3f", - scales_[type_index][pvt_index][RiseFall::riseIndex()], - scales_[type_index][pvt_index][RiseFall::fallIndex()]); + || scaleFactorTypeRiseFallPrefix(type) + || scaleFactorTypeLowHighSuffix(type)) { + printf(" %.3f,%.3f", + scales_[type_index][pvt_index][RiseFall::riseIndex()], + scales_[type_index][pvt_index][RiseFall::fallIndex()]); } else { - printf(" %.3f", - scales_[type_index][pvt_index][0]); + printf(" %.3f", + scales_[type_index][pvt_index][0]); } } printf("\n"); @@ -3348,17 +3325,17 @@ OcvDerate::~OcvDerate() const Table * OcvDerate::derateTable(const RiseFall *rf, - const EarlyLate *early_late, - PathType path_type) + const EarlyLate *early_late, + PathType path_type) { return derate_[rf->index()][early_late->index()][int(path_type)].get(); } void OcvDerate::setDerateTable(const RiseFall *rf, - const EarlyLate *early_late, - const PathType path_type, - TablePtr derate) + const EarlyLate *early_late, + const PathType path_type, + TablePtr derate) { derate_[rf->index()][early_late->index()][int(path_type)] = derate; } diff --git a/liberty/Liberty.i b/liberty/Liberty.i index e56891e2..10bb9963 100644 --- a/liberty/Liberty.i +++ b/liberty/Liberty.i @@ -116,12 +116,12 @@ private: bool read_liberty_cmd(char *filename, - Corner *corner, - const MinMaxAll *min_max, - bool infer_latches) + Scene *scene, + const MinMaxAll *min_max, + bool infer_latches) { Sta *sta = Sta::sta(); - LibertyLibrary *lib = sta->readLiberty(filename, corner, min_max, infer_latches); + LibertyLibrary *lib = sta->readLiberty(filename, scene, min_max, infer_latches); return (lib != nullptr); } @@ -148,21 +148,21 @@ find_equiv_cells(LibertyCell *cell) bool equiv_cells(LibertyCell *cell1, - LibertyCell *cell2) + LibertyCell *cell2) { return sta::equivCells(cell1, cell2); } bool equiv_cell_ports(LibertyCell *cell1, - LibertyCell *cell2) + LibertyCell *cell2) { return equivCellPorts(cell1, cell2); } bool equiv_cell_timing_arcs(LibertyCell *cell1, - LibertyCell *cell2) + LibertyCell *cell2) { return equivCellTimingArcSets(cell1, cell2); } @@ -178,7 +178,7 @@ liberty_port_direction(const LibertyPort *port) { return port->direction()->name(); } - + bool liberty_supply_exists(const char *supply_name) { @@ -230,8 +230,8 @@ find_liberty_cell(const char *name) LibertyCellSeq find_liberty_cells_matching(const char *pattern, - bool regexp, - bool nocase) + bool regexp, + bool nocase) { PatternMatch matcher(pattern, regexp, nocase, Sta::sta()->tclInterp()); return self->findLibertyCellsMatching(&matcher); @@ -278,8 +278,8 @@ find_liberty_port(const char *name) LibertyPortSeq find_liberty_ports_matching(const char *pattern, - bool regexp, - bool nocase) + bool regexp, + bool nocase) { PatternMatch matcher(pattern, regexp, nocase, Sta::sta()->tclInterp()); return self->findLibertyPortsMatching(&matcher); @@ -297,9 +297,8 @@ timing_arc_sets() void ensure_voltage_waveforms() { - Corners *corners = Sta::sta()->corners(); - const DcalcAnalysisPtSeq &dcalc_aps = corners->dcalcAnalysisPts(); - self->ensureVoltageWaveforms(dcalc_aps); + const SceneSeq &scenes = Sta::sta()->scenes(); + self->ensureVoltageWaveforms(scenes); } LibertyCell *test_cell() { return self->testCell(); } @@ -319,7 +318,7 @@ member_iterator() { return new LibertyPortMemberIterator(self); } LibertyPort *bundle_port() { return self->bundlePort(); } bool is_pwr_gnd() { return self->isPwrGnd(); } -string +std::string function() { FuncExpr *func = self->function(); @@ -329,7 +328,7 @@ function() return ""; } -string +std::string tristate_enable() { FuncExpr *enable = self->tristateEnable(); @@ -340,11 +339,11 @@ tristate_enable() } float -capacitance(Corner *corner, - const MinMax *min_max) +capacitance(Scene *scene, + const MinMax *min_max) { Sta *sta = Sta::sta(); - return sta->capacitance(self, corner, min_max); + return sta->capacitance(self, scene, min_max); } void @@ -374,9 +373,9 @@ full_name() const char *to = self->to()->name(); const char *cell_name = self->libertyCell()->name(); return stringPrintTmp("%s %s -> %s", - cell_name, - from, - to); + cell_name, + from, + to); } TimingArcSeq & diff --git a/liberty/Liberty.tcl b/liberty/Liberty.tcl index d4ac84a1..672e876f 100644 --- a/liberty/Liberty.tcl +++ b/liberty/Liberty.tcl @@ -35,7 +35,7 @@ proc_redirect read_liberty { check_argc_eq1 "read_liberty" $args set filename [file nativename [lindex $args 0]] - set corner [parse_corner keys] + set corner [parse_scene keys] set min_max [parse_min_max_all_flags flags] set infer_latches [info exists flags(-infer_latches)] read_liberty_cmd $filename $corner $min_max $infer_latches @@ -58,13 +58,13 @@ proc_redirect report_lib_cell { check_argc_eq1 "report_lib_cell" $args set arg [lindex $args 0] set cell [get_lib_cell_warn "lib_cell" $arg] - set corner [cmd_corner] + set scene [cmd_scene] if { $cell != "NULL" } { - report_lib_cell_ $cell $corner + report_lib_cell_ $cell $scene } } -proc report_lib_cell_ { cell corner } { +proc report_lib_cell_ { cell scene } { global sta_report_default_digits set lib [$cell liberty_library] @@ -78,21 +78,21 @@ proc report_lib_cell_ { cell corner } { while {[$iter has_next]} { set port [$iter next] if { [$port is_bus] || [$port is_bundle] } { - report_lib_port $port $corner + report_lib_port $port $scene set member_iter [$port member_iterator] while { [$member_iter has_next] } { set port [$member_iter next] - report_lib_port $port $corner + report_lib_port $port $scene } $member_iter finish } elseif { ![$port is_bundle_member] && ![$port is_bus_bit] } { - report_lib_port $port $corner + report_lib_port $port $scene } } $iter finish } -proc report_lib_port { port corner } { +proc report_lib_port { port scene } { global sta_report_default_digits if { [$port is_bus] } { @@ -112,7 +112,7 @@ proc report_lib_port { port corner } { if { $func != "" } { set func " function=$func" } - report_line " ${indent}$port_name [liberty_port_direction $port]$enable$func[port_capacitance_str $port $corner $sta_report_default_digits]" + report_line " ${indent}$port_name [liberty_port_direction $port]$enable$func[port_capacitance_str $port $scene $sta_report_default_digits]" } # sta namespace end diff --git a/liberty/LibertyBuilder.cc b/liberty/LibertyBuilder.cc index 46bde91a..fa29f5ec 100644 --- a/liberty/LibertyBuilder.cc +++ b/liberty/LibertyBuilder.cc @@ -49,8 +49,8 @@ LibertyBuilder::init(Debug *debug, LibertyCell * LibertyBuilder::makeCell(LibertyLibrary *library, - const char *name, - const char *filename) + const char *name, + const char *filename) { LibertyCell *cell = new LibertyCell(library, name, filename); library->addCell(cell); @@ -59,7 +59,7 @@ LibertyBuilder::makeCell(LibertyLibrary *library, LibertyPort * LibertyBuilder::makePort(LibertyCell *cell, - const char *port_name) + const char *port_name) { LibertyPort *port = new LibertyPort(cell, port_name, false, nullptr, -1, -1, false, nullptr); @@ -69,14 +69,14 @@ LibertyBuilder::makePort(LibertyCell *cell, LibertyPort * LibertyBuilder::makeBusPort(LibertyCell *cell, - const char *bus_name, + const char *bus_name, int from_index, - int to_index, - BusDcl *bus_dcl) + int to_index, + BusDcl *bus_dcl) { LibertyPort *port = new LibertyPort(cell, bus_name, true, bus_dcl, from_index, to_index, - false, new ConcretePortSeq); + false, new ConcretePortSeq); cell->addPort(port); makeBusPortBits(cell->library(), cell, port, bus_name, from_index, to_index); return port; @@ -84,11 +84,11 @@ LibertyBuilder::makeBusPort(LibertyCell *cell, void LibertyBuilder::makeBusPortBits(ConcreteLibrary *library, - LibertyCell *cell, - ConcretePort *bus_port, - const char *bus_name, - int from_index, - int to_index) + LibertyCell *cell, + ConcretePort *bus_port, + const char *bus_name, + int from_index, + int to_index) { if (from_index < to_index) { for (int index = from_index; index <= to_index; index++) @@ -102,10 +102,10 @@ LibertyBuilder::makeBusPortBits(ConcreteLibrary *library, void LibertyBuilder::makeBusPortBit(ConcreteLibrary *library, - LibertyCell *cell, - ConcretePort *bus_port, - const char *bus_name, - int bit_index) + LibertyCell *cell, + ConcretePort *bus_port, + const char *bus_name, + int bit_index) { string bit_name; stringPrint(bit_name, "%s%c%d%c", @@ -120,18 +120,18 @@ LibertyBuilder::makeBusPortBit(ConcreteLibrary *library, LibertyPort * LibertyBuilder::makePort(LibertyCell *cell, - const char *bit_name, - int bit_index) + const char *bit_name, + int bit_index) { LibertyPort *port = new LibertyPort(cell, bit_name, false, nullptr, - bit_index, bit_index, false, nullptr); + bit_index, bit_index, false, nullptr); return port; } LibertyPort * LibertyBuilder::makeBundlePort(LibertyCell *cell, - const char *name, - ConcretePortSeq *members) + const char *name, + ConcretePortSeq *members) { LibertyPort *port = new LibertyPort(cell, name, false, nullptr, -1, -1, true, members); cell->addPort(port); @@ -144,10 +144,10 @@ LibertyBuilder::makeBundlePort(LibertyCell *cell, TimingArcSet * LibertyBuilder::makeTimingArcs(LibertyCell *cell, - LibertyPort *from_port, - LibertyPort *to_port, - LibertyPort *related_out, - TimingArcAttrsPtr attrs, + LibertyPort *from_port, + LibertyPort *to_port, + LibertyPort *related_out, + TimingArcAttrsPtr attrs, int /* line */) { FuncExpr *to_func = to_port->function(); @@ -203,20 +203,20 @@ LibertyBuilder::makeTimingArcs(LibertyCell *cell, return makeCombinationalArcs(cell, from_port, to_port, true, false, attrs); case TimingType::setup_rising: return makeFromTransitionArcs(cell, from_port, to_port, related_out, - RiseFall::rise(), TimingRole::setup(), - attrs); + RiseFall::rise(), TimingRole::setup(), + attrs); case TimingType::setup_falling: return makeFromTransitionArcs(cell, from_port, to_port, related_out, - RiseFall::fall(), TimingRole::setup(), - attrs); + RiseFall::fall(), TimingRole::setup(), + attrs); case TimingType::hold_rising: return makeFromTransitionArcs(cell, from_port, to_port, related_out, - RiseFall::rise(), TimingRole::hold(), - attrs); + RiseFall::rise(), TimingRole::hold(), + attrs); case TimingType::hold_falling: return makeFromTransitionArcs(cell, from_port, to_port, related_out, - RiseFall::fall(), TimingRole::hold(), - attrs); + RiseFall::fall(), TimingRole::hold(), + attrs); case TimingType::rising_edge: return makeRegLatchArcs(cell, from_port, to_port, RiseFall::rise(), attrs); case TimingType::falling_edge: @@ -227,20 +227,20 @@ LibertyBuilder::makeTimingArcs(LibertyCell *cell, return makePresetClrArcs(cell, from_port, to_port, RiseFall::fall(), attrs); case TimingType::recovery_rising: return makeFromTransitionArcs(cell, from_port, to_port, related_out, - RiseFall::rise(),TimingRole::recovery(), - attrs); + RiseFall::rise(),TimingRole::recovery(), + attrs); case TimingType::recovery_falling: return makeFromTransitionArcs(cell, from_port, to_port, related_out, - RiseFall::fall(),TimingRole::recovery(), - attrs); + RiseFall::fall(),TimingRole::recovery(), + attrs); case TimingType::removal_rising: return makeFromTransitionArcs(cell, from_port, to_port, related_out, - RiseFall::rise(), TimingRole::removal(), - attrs); + RiseFall::rise(), TimingRole::removal(), + attrs); case TimingType::removal_falling: return makeFromTransitionArcs(cell, from_port, to_port, related_out, - RiseFall::fall(), TimingRole::removal(), - attrs); + RiseFall::fall(), TimingRole::removal(), + attrs); case TimingType::three_state_disable: return makeTristateDisableArcs(cell, from_port, to_port, true, true, attrs); case TimingType::three_state_disable_fall: @@ -255,30 +255,30 @@ LibertyBuilder::makeTimingArcs(LibertyCell *cell, return makeTristateEnableArcs(cell, from_port, to_port, true, false, attrs); case TimingType::skew_falling: return makeFromTransitionArcs(cell, from_port, to_port, related_out, - RiseFall::fall(), TimingRole::skew(), - attrs); + RiseFall::fall(), TimingRole::skew(), + attrs); case TimingType::skew_rising: return makeFromTransitionArcs(cell, from_port, to_port, related_out, - RiseFall::rise(), TimingRole::skew(), - attrs); + RiseFall::rise(), TimingRole::skew(), + attrs); case TimingType::non_seq_setup_rising: return makeFromTransitionArcs(cell, from_port, to_port, related_out, - RiseFall::rise(), - TimingRole::nonSeqSetup(), attrs); + RiseFall::rise(), + TimingRole::nonSeqSetup(), attrs); case TimingType::non_seq_setup_falling: return makeFromTransitionArcs(cell, from_port, to_port, related_out, - RiseFall::fall(), - TimingRole::nonSeqSetup(), attrs); + RiseFall::fall(), + TimingRole::nonSeqSetup(), attrs); case TimingType::non_seq_hold_rising: return makeFromTransitionArcs(cell, from_port, to_port, related_out, - RiseFall::rise(), - TimingRole::nonSeqHold(), - attrs); + RiseFall::rise(), + TimingRole::nonSeqHold(), + attrs); case TimingType::non_seq_hold_falling: return makeFromTransitionArcs(cell, from_port, to_port, related_out, - RiseFall::fall(), - TimingRole::nonSeqHold(), - attrs); + RiseFall::fall(), + TimingRole::nonSeqHold(), + attrs); case TimingType::min_clock_tree_path: return makeClockTreePathArcs(cell, to_port, TimingRole::clockTreePathMin(), MinMax::min(), attrs); @@ -305,16 +305,16 @@ LibertyBuilder::makeTimingArcs(LibertyCell *cell, TimingArcSet * LibertyBuilder::makeCombinationalArcs(LibertyCell *cell, - LibertyPort *from_port, - LibertyPort *to_port, - bool to_rise, - bool to_fall, - TimingArcAttrsPtr attrs) + LibertyPort *from_port, + LibertyPort *to_port, + bool to_rise, + bool to_fall, + TimingArcAttrsPtr attrs) { FuncExpr *func = to_port->function(); FuncExpr *enable = to_port->tristateEnable(); TimingArcSet *arc_set = makeTimingArcSet(cell, from_port, to_port, - TimingRole::combinational(), attrs); + TimingRole::combinational(), attrs); TimingSense sense = attrs->timingSense(); if (sense == TimingSense::unknown) { // Timing sense not specified - find it from function. @@ -340,13 +340,13 @@ LibertyBuilder::makeCombinationalArcs(LibertyCell *cell, to_rf = RiseFall::rise(); model = attrs->model(to_rf); if (model) - makeTimingArc(arc_set, RiseFall::rise(), to_rf, model); + makeTimingArc(arc_set, RiseFall::rise(), to_rf, model); } if (to_fall) { to_rf = RiseFall::fall(); model = attrs->model(to_rf); if (model) - makeTimingArc(arc_set, RiseFall::fall(), to_rf, model); + makeTimingArc(arc_set, RiseFall::fall(), to_rf, model); } break; case TimingSense::negative_unate: @@ -354,13 +354,13 @@ LibertyBuilder::makeCombinationalArcs(LibertyCell *cell, to_rf = RiseFall::fall(); model = attrs->model(to_rf); if (model) - makeTimingArc(arc_set, RiseFall::rise(), to_rf, model); + makeTimingArc(arc_set, RiseFall::rise(), to_rf, model); } if (to_rise) { to_rf = RiseFall::rise(); model = attrs->model(to_rf); if (model) - makeTimingArc(arc_set, RiseFall::fall(), to_rf, model); + makeTimingArc(arc_set, RiseFall::fall(), to_rf, model); } break; case TimingSense::non_unate: @@ -370,16 +370,16 @@ LibertyBuilder::makeCombinationalArcs(LibertyCell *cell, to_rf = RiseFall::fall(); model = attrs->model(to_rf); if (model) { - makeTimingArc(arc_set, RiseFall::fall(), to_rf, model); - makeTimingArc(arc_set, RiseFall::rise(), to_rf, model); + makeTimingArc(arc_set, RiseFall::fall(), to_rf, model); + makeTimingArc(arc_set, RiseFall::rise(), to_rf, model); } } if (to_rise) { to_rf = RiseFall::rise(); model = attrs->model(to_rf); if (model) { - makeTimingArc(arc_set, RiseFall::rise(), to_rf, model); - makeTimingArc(arc_set, RiseFall::fall(), to_rf, model); + makeTimingArc(arc_set, RiseFall::rise(), to_rf, model); + makeTimingArc(arc_set, RiseFall::fall(), to_rf, model); } } break; @@ -389,13 +389,13 @@ LibertyBuilder::makeCombinationalArcs(LibertyCell *cell, TimingArcSet * LibertyBuilder::makeLatchDtoQArcs(LibertyCell *cell, - LibertyPort *from_port, - LibertyPort *to_port, + LibertyPort *from_port, + LibertyPort *to_port, TimingSense sense, - TimingArcAttrsPtr attrs) + TimingArcAttrsPtr attrs) { TimingArcSet *arc_set = makeTimingArcSet(cell, from_port, to_port, - TimingRole::latchDtoQ(), attrs); + TimingRole::latchDtoQ(), attrs); TimingModel *model; const RiseFall *to_rf = RiseFall::rise(); model = attrs->model(to_rf); @@ -418,31 +418,30 @@ LibertyBuilder::makeLatchDtoQArcs(LibertyCell *cell, TimingArcSet * LibertyBuilder::makeRegLatchArcs(LibertyCell *cell, - LibertyPort *from_port, - LibertyPort *to_port, - const RiseFall *from_rf, - TimingArcAttrsPtr attrs) + LibertyPort *from_port, + LibertyPort *to_port, + const RiseFall *from_rf, + TimingArcAttrsPtr attrs) { FuncExpr *to_func = to_port->function(); - FuncExprPortIterator port_iter(to_func); - while (port_iter.hasNext()) { - LibertyPort *func_port = port_iter.next(); + LibertyPortSet to_ports = to_func->ports(); + for (LibertyPort *func_port : to_ports) { Sequential *seq = cell->outputPortSequential(func_port); if (seq) { if (seq->clock() && seq->clock()->hasPort(from_port)) { - const TimingRole *role = seq->isRegister() ? - TimingRole::regClkToQ() : TimingRole::latchEnToQ(); - return makeFromTransitionArcs(cell, from_port, to_port, nullptr, + const TimingRole *role = seq->isRegister() ? + TimingRole::regClkToQ() : TimingRole::latchEnToQ(); + return makeFromTransitionArcs(cell, from_port, to_port, nullptr, from_rf, role, attrs); } else if (seq->isLatch() - && seq->data() - && seq->data()->hasPort(from_port)) - return makeFromTransitionArcs(cell, from_port, to_port, nullptr, + && seq->data() + && seq->data()->hasPort(from_port)) + return makeFromTransitionArcs(cell, from_port, to_port, nullptr, from_rf, TimingRole::latchDtoQ(), attrs); else if ((seq->clear() && seq->clear()->hasPort(from_port)) - || (seq->preset() && seq->preset()->hasPort(from_port))) - return makeFromTransitionArcs(cell, from_port, to_port, nullptr, + || (seq->preset() && seq->preset()->hasPort(from_port))) + return makeFromTransitionArcs(cell, from_port, to_port, nullptr, from_rf, TimingRole::regSetClr(), attrs); } } @@ -454,15 +453,15 @@ LibertyBuilder::makeRegLatchArcs(LibertyCell *cell, TimingArcSet * LibertyBuilder::makeFromTransitionArcs(LibertyCell *cell, - LibertyPort *from_port, - LibertyPort *to_port, - LibertyPort *related_out, - const RiseFall *from_rf, - const TimingRole *role, - TimingArcAttrsPtr attrs) + LibertyPort *from_port, + LibertyPort *to_port, + LibertyPort *related_out, + const RiseFall *from_rf, + const TimingRole *role, + TimingArcAttrsPtr attrs) { TimingArcSet *arc_set = makeTimingArcSet(cell, from_port, to_port, - related_out, role, attrs); + related_out, role, attrs); for (auto to_rf : RiseFall::range()) { TimingModel *model = attrs->model(to_rf); if (model) @@ -473,16 +472,16 @@ LibertyBuilder::makeFromTransitionArcs(LibertyCell *cell, TimingArcSet * LibertyBuilder::makePresetClrArcs(LibertyCell *cell, - LibertyPort *from_port, - LibertyPort *to_port, - const RiseFall *to_rf, - TimingArcAttrsPtr attrs) + LibertyPort *from_port, + LibertyPort *to_port, + const RiseFall *to_rf, + TimingArcAttrsPtr attrs) { TimingArcSet *arc_set = nullptr; TimingModel *model = attrs->model(to_rf); if (model) { arc_set = makeTimingArcSet(cell, from_port, to_port, - TimingRole::regSetClr(), attrs); + TimingRole::regSetClr(), attrs); const RiseFall *opp_rf = to_rf->opposite(); switch (attrs->timingSense()) { case TimingSense::positive_unate: @@ -508,14 +507,14 @@ LibertyBuilder::makePresetClrArcs(LibertyCell *cell, // 1Z, Z0 fall TimingArcSet * LibertyBuilder::makeTristateEnableArcs(LibertyCell *cell, - LibertyPort *from_port, - LibertyPort *to_port, - bool to_rise, - bool to_fall, - TimingArcAttrsPtr attrs) + LibertyPort *from_port, + LibertyPort *to_port, + bool to_rise, + bool to_fall, + TimingArcAttrsPtr attrs) { TimingArcSet *arc_set = makeTimingArcSet(cell, from_port, to_port, - TimingRole::tristateEnable(), attrs); + TimingRole::tristateEnable(), attrs); FuncExpr *tristate_enable = to_port->tristateEnable(); TimingSense sense = attrs->timingSense(); if (sense == TimingSense::unknown && tristate_enable) @@ -528,13 +527,13 @@ LibertyBuilder::makeTristateEnableArcs(LibertyCell *cell, to_rf = RiseFall::rise(); model = attrs->model(to_rf); if (model) - makeTimingArc(arc_set, Transition::rise(), Transition::trZ1(), model); + makeTimingArc(arc_set, Transition::rise(), Transition::trZ1(), model); } if (to_fall) { to_rf = RiseFall::fall(); model = attrs->model(to_rf); if (model) - makeTimingArc(arc_set, Transition::rise(), Transition::trZ0(), model); + makeTimingArc(arc_set, Transition::rise(), Transition::trZ0(), model); } break; case TimingSense::negative_unate: @@ -542,13 +541,13 @@ LibertyBuilder::makeTristateEnableArcs(LibertyCell *cell, to_rf = RiseFall::rise(); model = attrs->model(to_rf); if (model) - makeTimingArc(arc_set, Transition::fall(), Transition::trZ1(), model); + makeTimingArc(arc_set, Transition::fall(), Transition::trZ1(), model); } if (to_fall) { to_rf = RiseFall::fall(); model = attrs->model(to_rf); if (model) - makeTimingArc(arc_set, Transition::fall(), Transition::trZ0(), model); + makeTimingArc(arc_set, Transition::fall(), Transition::trZ0(), model); } break; case TimingSense::non_unate: @@ -557,16 +556,16 @@ LibertyBuilder::makeTristateEnableArcs(LibertyCell *cell, to_rf = RiseFall::rise(); model = attrs->model(to_rf); if (model) { - makeTimingArc(arc_set, Transition::rise(), Transition::trZ1(), model); - makeTimingArc(arc_set, Transition::fall(), Transition::trZ1(), model); + makeTimingArc(arc_set, Transition::rise(), Transition::trZ1(), model); + makeTimingArc(arc_set, Transition::fall(), Transition::trZ1(), model); } } if (to_fall) { to_rf = RiseFall::fall(); model = attrs->model(to_rf); if (model) { - makeTimingArc(arc_set, Transition::rise(), Transition::trZ0(), model); - makeTimingArc(arc_set, Transition::fall(), Transition::trZ0(), model); + makeTimingArc(arc_set, Transition::rise(), Transition::trZ0(), model); + makeTimingArc(arc_set, Transition::fall(), Transition::trZ0(), model); } } break; @@ -578,15 +577,15 @@ LibertyBuilder::makeTristateEnableArcs(LibertyCell *cell, TimingArcSet * LibertyBuilder::makeTristateDisableArcs(LibertyCell *cell, - LibertyPort *from_port, - LibertyPort *to_port, - bool to_rise, - bool to_fall, - TimingArcAttrsPtr attrs) + LibertyPort *from_port, + LibertyPort *to_port, + bool to_rise, + bool to_fall, + TimingArcAttrsPtr attrs) { TimingArcSet *arc_set = makeTimingArcSet(cell, from_port, to_port, - TimingRole::tristateDisable(), - attrs); + TimingRole::tristateDisable(), + attrs); TimingSense sense = attrs->timingSense(); FuncExpr *tristate_enable = to_port->tristateEnable(); if (sense == TimingSense::unknown && tristate_enable) @@ -599,13 +598,13 @@ LibertyBuilder::makeTristateDisableArcs(LibertyCell *cell, to_rf = RiseFall::rise(); model = attrs->model(to_rf); if (model) - makeTimingArc(arc_set, Transition::rise(), Transition::tr0Z(), model); + makeTimingArc(arc_set, Transition::rise(), Transition::tr0Z(), model); } if (to_fall) { to_rf = RiseFall::fall(); model = attrs->model(to_rf); if (model) - makeTimingArc(arc_set, Transition::rise(), Transition::tr1Z(), model); + makeTimingArc(arc_set, Transition::rise(), Transition::tr1Z(), model); } break; case TimingSense::negative_unate: @@ -613,13 +612,13 @@ LibertyBuilder::makeTristateDisableArcs(LibertyCell *cell, to_rf = RiseFall::rise(); model = attrs->model(to_rf); if (model) - makeTimingArc(arc_set, Transition::fall(), Transition::tr0Z(), model); + makeTimingArc(arc_set, Transition::fall(), Transition::tr0Z(), model); } if (to_fall) { to_rf = RiseFall::fall(); model = attrs->model(to_rf); if (model) - makeTimingArc(arc_set, Transition::fall(), Transition::tr1Z(), model); + makeTimingArc(arc_set, Transition::fall(), Transition::tr1Z(), model); } break; case TimingSense::non_unate: @@ -628,16 +627,16 @@ LibertyBuilder::makeTristateDisableArcs(LibertyCell *cell, to_rf = RiseFall::rise(); model = attrs->model(to_rf); if (model) { - makeTimingArc(arc_set, Transition::fall(), Transition::tr0Z(), model); - makeTimingArc(arc_set, Transition::rise(), Transition::tr0Z(), model); + makeTimingArc(arc_set, Transition::fall(), Transition::tr0Z(), model); + makeTimingArc(arc_set, Transition::rise(), Transition::tr0Z(), model); } } if (to_fall) { to_rf = RiseFall::fall(); model = attrs->model(to_rf); if (model) { - makeTimingArc(arc_set, Transition::fall(), Transition::tr1Z(), model); - makeTimingArc(arc_set, Transition::rise(), Transition::tr1Z(), model); + makeTimingArc(arc_set, Transition::fall(), Transition::tr1Z(), model); + makeTimingArc(arc_set, Transition::rise(), Transition::tr1Z(), model); } } break; @@ -708,40 +707,40 @@ LibertyBuilder::makeMinPulseWidthArcs(LibertyCell *cell, TimingArcSet * LibertyBuilder::makeTimingArcSet(LibertyCell *cell, - LibertyPort *from, - LibertyPort *to, - const TimingRole *role, - TimingArcAttrsPtr attrs) + LibertyPort *from, + LibertyPort *to, + const TimingRole *role, + TimingArcAttrsPtr attrs) { return new TimingArcSet(cell, from, to, nullptr, role, attrs); } TimingArcSet * LibertyBuilder::makeTimingArcSet(LibertyCell *cell, - LibertyPort *from, - LibertyPort *to, - LibertyPort *related_out, - const TimingRole *role, - TimingArcAttrsPtr attrs) + LibertyPort *from, + LibertyPort *to, + LibertyPort *related_out, + const TimingRole *role, + TimingArcAttrsPtr attrs) { return new TimingArcSet(cell, from, to, related_out, role, attrs); } TimingArc * LibertyBuilder::makeTimingArc(TimingArcSet *set, - const RiseFall *from_rf, - const RiseFall *to_rf, - TimingModel *model) + const RiseFall *from_rf, + const RiseFall *to_rf, + TimingModel *model) { return new TimingArc(set, from_rf->asTransition(), - to_rf->asTransition(), model); + to_rf->asTransition(), model); } TimingArc * LibertyBuilder::makeTimingArc(TimingArcSet *set, - const Transition *from_rf, - const Transition *to_rf, - TimingModel *model) + const Transition *from_rf, + const Transition *to_rf, + TimingModel *model) { return new TimingArc(set, from_rf, to_rf, model); } @@ -750,16 +749,16 @@ LibertyBuilder::makeTimingArc(TimingArcSet *set, InternalPower * LibertyBuilder::makeInternalPower(LibertyCell *cell, - LibertyPort *port, - LibertyPort *related_port, - InternalPowerAttrs *attrs) + LibertyPort *port, + LibertyPort *related_port, + InternalPowerAttrs *attrs) { return new InternalPower(cell, port, related_port, attrs); } LeakagePower * LibertyBuilder::makeLeakagePower(LibertyCell *cell, - LeakagePowerAttrs *attrs) + LeakagePowerAttrs *attrs) { return new LeakagePower(cell, attrs); } diff --git a/liberty/LibertyBuilder.hh b/liberty/LibertyBuilder.hh index 9ce87931..27b60b69 100644 --- a/liberty/LibertyBuilder.hh +++ b/liberty/LibertyBuilder.hh @@ -25,7 +25,6 @@ #pragma once #include "MinMax.hh" -#include "Vector.hh" #include "Transition.hh" #include "LibertyClass.hh" #include "ConcreteLibrary.hh" @@ -46,47 +45,47 @@ public: void init(Debug *debug, Report *report); virtual LibertyCell *makeCell(LibertyLibrary *library, - const char *name, - const char *filename); + const char *name, + const char *filename); virtual LibertyPort *makePort(LibertyCell *cell, - const char *name); + const char *name); virtual LibertyPort *makeBusPort(LibertyCell *cell, - const char *bus_name, - int from_index, - int to_index, + const char *bus_name, + int from_index, + int to_index, BusDcl *bus_dcl); virtual LibertyPort *makeBundlePort(LibertyCell *cell, - const char *name, - ConcretePortSeq *members); + const char *name, + ConcretePortSeq *members); // Build timing arc sets and their arcs given a type and sense. // Port functions and cell latches are also used by this builder // to get the correct roles. TimingArcSet *makeTimingArcs(LibertyCell *cell, - LibertyPort *from_port, - LibertyPort *to_port, - LibertyPort *related_out, - TimingArcAttrsPtr attrs, + LibertyPort *from_port, + LibertyPort *to_port, + LibertyPort *related_out, + TimingArcAttrsPtr attrs, int line); InternalPower *makeInternalPower(LibertyCell *cell, - LibertyPort *port, - LibertyPort *related_port, - InternalPowerAttrs *attrs); + LibertyPort *port, + LibertyPort *related_port, + InternalPowerAttrs *attrs); LeakagePower *makeLeakagePower(LibertyCell *cell, - LeakagePowerAttrs *attrs); + LeakagePowerAttrs *attrs); TimingArcSet *makeFromTransitionArcs(LibertyCell *cell, - LibertyPort *from_port, - LibertyPort *to_port, - LibertyPort *related_out, - const RiseFall *from_rf, - const TimingRole *role, - TimingArcAttrsPtr attrs); + LibertyPort *from_port, + LibertyPort *to_port, + LibertyPort *related_out, + const RiseFall *from_rf, + const TimingRole *role, + TimingArcAttrsPtr attrs); TimingArcSet *makeCombinationalArcs(LibertyCell *cell, - LibertyPort *from_port, - LibertyPort *to_port, - bool to_rise, - bool to_fall, - TimingArcAttrsPtr attrs); + LibertyPort *from_port, + LibertyPort *to_port, + bool to_rise, + bool to_fall, + TimingArcAttrsPtr attrs); TimingArcSet *makeClockTreePathArcs(LibertyCell *cell, LibertyPort *to_port, const TimingRole *role, @@ -101,70 +100,70 @@ public: protected: ConcretePort *makeBusPort(const char *name, - int from_index, - int to_index, - ConcretePortSeq *members); + int from_index, + int to_index, + ConcretePortSeq *members); void makeBusPortBits(ConcreteLibrary *library, - LibertyCell *cell, - ConcretePort *bus_port, - const char *bus_name, - int from_index, - int to_index); + LibertyCell *cell, + ConcretePort *bus_port, + const char *bus_name, + int from_index, + int to_index); // Bus port bit (internal to makeBusPortBits). virtual LibertyPort *makePort(LibertyCell *cell, const char *bit_name, int bit_index); void makeBusPortBit(ConcreteLibrary *library, - LibertyCell *cell, - ConcretePort *bus_port, - const char *bus_name, - int index); + LibertyCell *cell, + ConcretePort *bus_port, + const char *bus_name, + int index); virtual TimingArcSet *makeTimingArcSet(LibertyCell *cell, - LibertyPort *from, - LibertyPort *to, - const TimingRole *role, - TimingArcAttrsPtr attrs); + LibertyPort *from, + LibertyPort *to, + const TimingRole *role, + TimingArcAttrsPtr attrs); virtual TimingArcSet *makeTimingArcSet(LibertyCell *cell, - LibertyPort *from, - LibertyPort *to, - LibertyPort *related_out, - const TimingRole *role, - TimingArcAttrsPtr attrs); + LibertyPort *from, + LibertyPort *to, + LibertyPort *related_out, + const TimingRole *role, + TimingArcAttrsPtr attrs); virtual TimingArc *makeTimingArc(TimingArcSet *set, - const Transition *from_rf, - const Transition *to_rf, - TimingModel *model); + const Transition *from_rf, + const Transition *to_rf, + TimingModel *model); TimingArc *makeTimingArc(TimingArcSet *set, - const RiseFall *from_rf, - const RiseFall *to_rf, - TimingModel *model); + const RiseFall *from_rf, + const RiseFall *to_rf, + TimingModel *model); TimingArcSet *makeLatchDtoQArcs(LibertyCell *cell, - LibertyPort *from_port, - LibertyPort *to_port, + LibertyPort *from_port, + LibertyPort *to_port, TimingSense sense, - TimingArcAttrsPtr attrs); + TimingArcAttrsPtr attrs); TimingArcSet *makeRegLatchArcs(LibertyCell *cell, - LibertyPort *from_port, - LibertyPort *to_port, - const RiseFall *from_rf, - TimingArcAttrsPtr attrs); + LibertyPort *from_port, + LibertyPort *to_port, + const RiseFall *from_rf, + TimingArcAttrsPtr attrs); TimingArcSet *makePresetClrArcs(LibertyCell *cell, - LibertyPort *from_port, - LibertyPort *to_port, - const RiseFall *to_rf, - TimingArcAttrsPtr attrs); + LibertyPort *from_port, + LibertyPort *to_port, + const RiseFall *to_rf, + TimingArcAttrsPtr attrs); TimingArcSet *makeTristateEnableArcs(LibertyCell *cell, - LibertyPort *from_port, - LibertyPort *to_port, - bool to_rise, - bool to_fall, - TimingArcAttrsPtr attrs); + LibertyPort *from_port, + LibertyPort *to_port, + bool to_rise, + bool to_fall, + TimingArcAttrsPtr attrs); TimingArcSet *makeTristateDisableArcs(LibertyCell *cell, - LibertyPort *from_port, - LibertyPort *to_port, - bool to_rise, - bool to_fall, - TimingArcAttrsPtr attrs); + LibertyPort *from_port, + LibertyPort *to_port, + bool to_rise, + bool to_fall, + TimingArcAttrsPtr attrs); Debug *debug_; Report *report_; diff --git a/liberty/LibertyExt.cc b/liberty/LibertyExt.cc index aa2850e8..10a214b1 100644 --- a/liberty/LibertyExt.cc +++ b/liberty/LibertyExt.cc @@ -67,7 +67,7 @@ protected: }; BigcoCell::BigcoCell(LibertyLibrary *library, const char *name, - const char *filename) : + const char *filename) : LibertyCell(library, name, filename), thingy_(0) { @@ -110,17 +110,17 @@ class BigcoTimingArcSet : public TimingArcSet { public: BigcoTimingArcSet(LibertyCell *cell, LibertyPort *from, LibertyPort *to, - LibertyPort *related_out, TimingRole *role, - TimingArcAttrs *attrs); + LibertyPort *related_out, TimingRole *role, + TimingArcAttrs *attrs); protected: const char *frob_; }; BigcoTimingArcSet::BigcoTimingArcSet(LibertyCell *cell, LibertyPort *from, - LibertyPort *to, - LibertyPort *related_out, TimingRole *role, - TimingArcAttrs *attrs) : + LibertyPort *to, + LibertyPort *related_out, TimingRole *role, + TimingArcAttrs *attrs) : TimingArcSet(cell, from, to, related_out, role, attrs) { const char *frob = static_cast(attrs)->frob(); @@ -135,19 +135,19 @@ class BigcoLibertyBuilder : public LibertyBuilder { public: virtual LibertyCell *makeCell(LibertyLibrary *library, const char *name, - const char *filename); + const char *filename); protected: virtual TimingArcSet *makeTimingArcSet(LibertyCell *cell, LibertyPort *from, - LibertyPort *to, - LibertyPort *related_out, - TimingRole *role, - TimingArcAttrs *attrs); + LibertyPort *to, + LibertyPort *related_out, + TimingRole *role, + TimingArcAttrs *attrs); }; LibertyCell * BigcoLibertyBuilder::makeCell(LibertyLibrary *library, const char *name, - const char *filename) + const char *filename) { LibertyCell *cell = new BigcoCell(library, name, filename); library->addCell(cell); @@ -156,10 +156,10 @@ BigcoLibertyBuilder::makeCell(LibertyLibrary *library, const char *name, TimingArcSet * BigcoLibertyBuilder::makeTimingArcSet(LibertyCell *cell, LibertyPort *from, - LibertyPort *to, - LibertyPort *related_out, - TimingRole *role, - TimingArcAttrs *attrs) + LibertyPort *to, + LibertyPort *related_out, + TimingRole *role, + TimingArcAttrs *attrs) { return new BigcoTimingArcSet(cell, from, to, related_out, role, attrs); } @@ -255,8 +255,8 @@ public: protected: virtual LibertyLibrary *readLibertyFile(const char *filename, - bool infer_latches, - Network *network); + bool infer_latches, + Network *network); }; BigcoSta::BigcoSta() : @@ -267,8 +267,8 @@ BigcoSta::BigcoSta() : // Replace Sta liberty file reader with Bigco's very own. LibertyLibrary * Sta::readLibertyFile(const char *filename, - bool infer_latches, - Network *network) + bool infer_latches, + Network *network) { BigcoLibertyBuilder builder; BigcoLibertyReader reader(&builder); diff --git a/liberty/LibertyParser.cc b/liberty/LibertyParser.cc index f1eddb1b..4dff3a40 100644 --- a/liberty/LibertyParser.cc +++ b/liberty/LibertyParser.cc @@ -28,6 +28,7 @@ #include #include +#include "ContainerHelpers.hh" #include "Zlib.hh" #include "Report.hh" #include "Error.hh" @@ -40,8 +41,8 @@ using std::string; void parseLibertyFile(const char *filename, - LibertyGroupVisitor *library_visitor, - Report *report) + LibertyGroupVisitor *library_visitor, + Report *report) { gzstream::igzstream stream(filename); if (stream.is_open()) { @@ -81,7 +82,7 @@ LibertyParser::makeDefine(LibertyAttrValueSeq *values, LibertyAttrType value_type = attrValueType(value_type_name); LibertyGroupType group_type = groupType(group_type_name); define = new LibertyDefine(define_name, group_type, - value_type, line); + value_type, line); LibertyGroup *group = this->group(); group->addDefine(define); } @@ -162,7 +163,7 @@ LibertyParser::group() void LibertyParser::deleteGroups() { - group_stack_.deleteContentsClear(); + deleteContents(group_stack_); } LibertyStmt * @@ -194,9 +195,7 @@ LibertyParser::makeComplexAttr(const char *name, if (stringEq(name, "define")) { LibertyStmt *define = makeDefine(values, line); stringDelete(name); - LibertyAttrValueSeq::Iterator attr_iter(values); - while (attr_iter.hasNext()) - delete attr_iter.next(); + deleteContents(values); delete values; return define; } @@ -252,8 +251,8 @@ LibertyStmt::LibertyStmt(int line) : } LibertyGroup::LibertyGroup(const char *type, - LibertyAttrValueSeq *params, - int line) : + LibertyAttrValueSeq *params, + int line) : LibertyStmt(line), type_(type), params_(params), @@ -278,7 +277,7 @@ LibertyGroup::addDefine(LibertyDefine *define) if (define_map_ == nullptr) define_map_ = new LibertyDefineMap; const char *define_name = define->name(); - LibertyDefine *prev_define = define_map_->findKey(define_name); + LibertyDefine *prev_define = findKey(define_map_, define_name); if (prev_define) { define_map_->erase(define_name); delete prev_define; @@ -299,21 +298,20 @@ LibertyGroup::addAttribute(LibertyAttr *attr) LibertyGroup::~LibertyGroup() { if (params_) { - params_->deleteContents(); + deleteContents(params_); delete params_; } if (attrs_) { - LibertyAttrSeq::Iterator iter(attrs_); - attrs_->deleteContents(); + deleteContents(attrs_); delete attrs_; delete attr_map_; } if (subgroups_) { - subgroups_->deleteContents(); + deleteContents(subgroups_); delete subgroups_; } if (define_map_) { - define_map_->deleteContents(); + deleteContents(define_map_); delete define_map_; } } @@ -346,40 +344,27 @@ LibertyGroup::findAttr(const char *name) if (attrs_) { if (attr_map_ == nullptr) { // Build attribute name map on demand. - LibertyAttrSeq::Iterator attr_iter(attrs_); - while (attr_iter.hasNext()) { - LibertyAttr *attr = attr_iter.next(); - (*attr_map_)[attr->name()] = attr; - } + for (LibertyAttr *attr : *attrs_) + (*attr_map_)[attr->name()] = attr; } - return attr_map_->findKey(name); + return findKey(attr_map_, name); } else return nullptr; } -LibertySubgroupIterator::LibertySubgroupIterator(LibertyGroup *group) : - LibertyGroupSeq::Iterator(group->subgroups()) -{ -} - -LibertyAttrIterator::LibertyAttrIterator(LibertyGroup *group) : - LibertyAttrSeq::Iterator(group->attrs()) -{ -} - //////////////////////////////////////////////////////////////// LibertyAttr::LibertyAttr(const char *name, - int line) : + int line) : LibertyStmt(line), name_(name) { } LibertySimpleAttr::LibertySimpleAttr(const char *name, - LibertyAttrValue *value, - int line) : + LibertyAttrValue *value, + int line) : LibertyAttr(name, line), value_(value) { @@ -398,8 +383,8 @@ LibertySimpleAttr::values() const } LibertyComplexAttr::LibertyComplexAttr(const char *name, - LibertyAttrValueSeq *values, - int line) : + LibertyAttrValueSeq *values, + int line) : LibertyAttr(name, line), values_(values) { @@ -408,7 +393,7 @@ LibertyComplexAttr::LibertyComplexAttr(const char *name, LibertyComplexAttr::~LibertyComplexAttr() { if (values_) { - values_->deleteContents(); + deleteContents(values_); delete values_; } } @@ -429,14 +414,14 @@ LibertyStringAttrValue::LibertyStringAttrValue(const char *value) : } float -LibertyStringAttrValue::floatValue() +LibertyStringAttrValue::floatValue() const { criticalError(1126, "LibertyStringAttrValue called for float value"); return 0.0; } const char * -LibertyStringAttrValue::stringValue() +LibertyStringAttrValue::stringValue() const { return value_.c_str(); } @@ -447,13 +432,13 @@ LibertyFloatAttrValue::LibertyFloatAttrValue(float value) : } float -LibertyFloatAttrValue::floatValue() +LibertyFloatAttrValue::floatValue() const { return value_; } const char * -LibertyFloatAttrValue::stringValue() +LibertyFloatAttrValue::stringValue() const { criticalError(1127, "LibertyStringAttrValue called for float value"); return nullptr; @@ -462,9 +447,9 @@ LibertyFloatAttrValue::stringValue() //////////////////////////////////////////////////////////////// LibertyDefine::LibertyDefine(const char *name, - LibertyGroupType group_type, - LibertyAttrType value_type, - int line) : + LibertyGroupType group_type, + LibertyAttrType value_type, + int line) : LibertyStmt(line), name_(name), group_type_(group_type), @@ -475,8 +460,8 @@ LibertyDefine::LibertyDefine(const char *name, //////////////////////////////////////////////////////////////// LibertyVariable::LibertyVariable(const char *var, - float value, - int line) : + float value, + int line) : LibertyStmt(line), var_(var), value_(value) diff --git a/liberty/LibertyParser.hh b/liberty/LibertyParser.hh index c1a9ec46..9b1fce2c 100644 --- a/liberty/LibertyParser.hh +++ b/liberty/LibertyParser.hh @@ -24,10 +24,10 @@ #pragma once +#include +#include + #include "Zlib.hh" -#include "Vector.hh" -#include "Map.hh" -#include "Set.hh" #include "StringUtil.hh" namespace sta { @@ -45,19 +45,17 @@ class LibertySubgroupIterator; class LibertyAttrIterator; class LibertyScanner; -typedef Vector LibertyStmtSeq; -typedef Vector LibertyGroupSeq; -typedef Vector LibertyAttrSeq; -typedef Map LibertyAttrMap; -typedef Map LibertyDefineMap; -typedef Vector LibertyAttrValueSeq; -typedef Map LibertyVariableMap; -typedef MapLibertyGroupVisitorMap; -typedef LibertyAttrValueSeq::Iterator LibertyAttrValueIterator; -typedef Vector LibertyGroupSeq; +using LibertyStmtSeq = std::vector; +using LibertyGroupSeq = std::vector; +using LibertyAttrSeq = std::vector; +using LibertyAttrMap = std::map; +using LibertyDefineMap = std::map; +using LibertyAttrValueSeq = std::vector; +using LibertyVariableMap = std::map; +using LibertyGroupVisitorMap = std::map; enum class LibertyAttrType { attr_string, attr_int, attr_double, - attr_boolean, attr_unknown }; + attr_boolean, attr_unknown }; enum class LibertyGroupType { library, cell, pin, timing, unknown }; @@ -122,8 +120,8 @@ class LibertyGroup : public LibertyStmt { public: LibertyGroup(const char *type, - LibertyAttrValueSeq *params, - int line); + LibertyAttrValueSeq *params, + int line); virtual ~LibertyGroup(); virtual bool isGroup() const { return true; } const char *type() const { return type_.c_str(); } @@ -151,24 +149,12 @@ protected: LibertyDefineMap *define_map_; }; -class LibertySubgroupIterator : public LibertyGroupSeq::Iterator -{ -public: - LibertySubgroupIterator(LibertyGroup *group); -}; - -class LibertyAttrIterator : public LibertyAttrSeq::Iterator -{ -public: - LibertyAttrIterator(LibertyGroup *group); -}; - // Abstract base class for attributes. class LibertyAttr : public LibertyStmt { public: LibertyAttr(const char *name, - int line); + int line); const char *name() const { return name_.c_str(); } virtual bool isAttribute() const { return true; } virtual bool isSimple() const = 0; @@ -186,13 +172,13 @@ class LibertySimpleAttr : public LibertyAttr { public: LibertySimpleAttr(const char *name, - LibertyAttrValue *value, - int line); + LibertyAttrValue *value, + int line); virtual ~LibertySimpleAttr(); - virtual bool isSimple() const { return true; } - virtual bool isComplex() const { return false; } - virtual LibertyAttrValue *firstValue() { return value_; } - virtual LibertyAttrValueSeq *values() const; + bool isSimple() const override { return true; }; + bool isComplex() const override { return false; }; + LibertyAttrValue *firstValue() override { return value_; }; + LibertyAttrValueSeq *values() const override; private: LibertyAttrValue *value_; @@ -204,13 +190,13 @@ class LibertyComplexAttr : public LibertyAttr { public: LibertyComplexAttr(const char *name, - LibertyAttrValueSeq *values, - int line); + LibertyAttrValueSeq *values, + int line); virtual ~LibertyComplexAttr(); - virtual bool isSimple() const { return false; } - virtual bool isComplex() const { return true; } - virtual LibertyAttrValue *firstValue(); - virtual LibertyAttrValueSeq *values() const { return values_; } + bool isSimple() const override { return false; } + bool isComplex() const override { return true; } + LibertyAttrValue *firstValue() override ; + LibertyAttrValueSeq *values() const override { return values_; } private: LibertyAttrValueSeq *values_; @@ -222,10 +208,10 @@ class LibertyAttrValue public: LibertyAttrValue() {} virtual ~LibertyAttrValue() {} - virtual bool isString() = 0; - virtual bool isFloat() = 0; - virtual float floatValue() = 0; - virtual const char *stringValue() = 0; + virtual bool isString() const = 0; + virtual bool isFloat() const = 0; + virtual float floatValue() const = 0; + virtual const char *stringValue() const = 0; }; class LibertyStringAttrValue : public LibertyAttrValue @@ -233,10 +219,10 @@ class LibertyStringAttrValue : public LibertyAttrValue public: LibertyStringAttrValue(const char *value); virtual ~LibertyStringAttrValue() {} - virtual bool isFloat() { return false; } - virtual bool isString() { return true; } - virtual float floatValue(); - virtual const char *stringValue(); + bool isFloat() const override { return false; } + bool isString() const override { return true; } + float floatValue() const override ; + const char *stringValue() const override; private: std::string value_; @@ -247,10 +233,10 @@ class LibertyFloatAttrValue : public LibertyAttrValue public: LibertyFloatAttrValue(float value); virtual ~LibertyFloatAttrValue() {} - virtual bool isString() { return false; } - virtual bool isFloat() { return true; } - virtual float floatValue(); - virtual const char *stringValue(); + bool isString() const override { return false; } + bool isFloat() const override { return true; } + float floatValue() const override; + const char *stringValue() const override; private: float value_; @@ -263,9 +249,9 @@ class LibertyDefine : public LibertyStmt { public: LibertyDefine(const char *name, - LibertyGroupType group_type, - LibertyAttrType value_type, - int line); + LibertyGroupType group_type, + LibertyAttrType value_type, + int line); virtual bool isDefine() const { return true; } const char *name() const { return name_.c_str(); } LibertyGroupType groupType() const { return group_type_; } @@ -285,9 +271,9 @@ class LibertyVariable : public LibertyStmt { public: LibertyVariable(const char *var, - float value, - int line); - virtual bool isVariable() const { return true; } + float value, + int line); + bool isVariable() const override { return true; } const char *variable() const { return var_.c_str(); } float value() const { return value_; } @@ -313,6 +299,6 @@ public: void parseLibertyFile(const char *filename, - LibertyGroupVisitor *library_visitor, - Report *report); + LibertyGroupVisitor *library_visitor, + Report *report); } // namespace diff --git a/liberty/LibertyReader.cc b/liberty/LibertyReader.cc index bb24b5fe..5479093e 100644 --- a/liberty/LibertyReader.cc +++ b/liberty/LibertyReader.cc @@ -28,6 +28,7 @@ #include #include +#include "ContainerHelpers.hh" #include "EnumNameMap.hh" #include "Report.hh" #include "Debug.hh" @@ -59,12 +60,12 @@ using std::string; static void scaleFloats(FloatSeq *floats, - float scale); + float scale); LibertyLibrary * readLibertyFile(const char *filename, - bool infer_latches, - Network *network) + bool infer_latches, + Network *network) { LibertyReader reader(filename, infer_latches, network); return reader.readLibertyFile(filename); @@ -153,8 +154,8 @@ LibertyReader::readLibertyFile(const char *filename) void LibertyReader::defineGroupVisitor(const char *type, - LibraryGroupVisitor begin_visitor, - LibraryGroupVisitor end_visitor) + LibraryGroupVisitor begin_visitor, + LibraryGroupVisitor end_visitor) { group_begin_map_[type] = begin_visitor; group_end_map_[type] = end_visitor; @@ -162,7 +163,7 @@ LibertyReader::defineGroupVisitor(const char *type, void LibertyReader::defineAttrVisitor(const char *attr_name, - LibraryAttrVisitor visitor) + LibraryAttrVisitor visitor) { attr_visitor_map_[attr_name] = visitor; } @@ -172,13 +173,13 @@ LibertyReader::defineVisitors() { // Library defineGroupVisitor("library", &LibertyReader::beginLibrary, - &LibertyReader::endLibrary); + &LibertyReader::endLibrary); defineAttrVisitor("time_unit", &LibertyReader::visitTimeUnit); defineAttrVisitor("pulling_resistance_unit", - &LibertyReader::visitPullingResistanceUnit); + &LibertyReader::visitPullingResistanceUnit); defineAttrVisitor("resistance_unit", &LibertyReader::visitResistanceUnit); defineAttrVisitor("capacitive_load_unit", - &LibertyReader::visitCapacitiveLoadUnit); + &LibertyReader::visitCapacitiveLoadUnit); defineAttrVisitor("voltage_unit", &LibertyReader::visitVoltageUnit); defineAttrVisitor("current_unit", &LibertyReader::visitCurrentUnit); defineAttrVisitor("leakage_power_unit", &LibertyReader::visitPowerUnit); @@ -190,62 +191,62 @@ LibertyReader::defineVisitors() defineAttrVisitor("nom_voltage", &LibertyReader::visitNomVolt); defineAttrVisitor("nom_process", &LibertyReader::visitNomProc); defineAttrVisitor("default_inout_pin_cap", - &LibertyReader::visitDefaultInoutPinCap); + &LibertyReader::visitDefaultInoutPinCap); defineAttrVisitor("default_input_pin_cap", - &LibertyReader::visitDefaultInputPinCap); + &LibertyReader::visitDefaultInputPinCap); defineAttrVisitor("default_output_pin_cap", - &LibertyReader::visitDefaultOutputPinCap); + &LibertyReader::visitDefaultOutputPinCap); defineAttrVisitor("default_max_transition", - &LibertyReader::visitDefaultMaxTransition); + &LibertyReader::visitDefaultMaxTransition); defineAttrVisitor("default_max_fanout", - &LibertyReader::visitDefaultMaxFanout); + &LibertyReader::visitDefaultMaxFanout); defineAttrVisitor("default_intrinsic_rise", - &LibertyReader::visitDefaultIntrinsicRise); + &LibertyReader::visitDefaultIntrinsicRise); defineAttrVisitor("default_intrinsic_fall", - &LibertyReader::visitDefaultIntrinsicFall); + &LibertyReader::visitDefaultIntrinsicFall); defineAttrVisitor("default_inout_pin_rise_res", - &LibertyReader::visitDefaultInoutPinRiseRes); + &LibertyReader::visitDefaultInoutPinRiseRes); defineAttrVisitor("default_inout_pin_fall_res", - &LibertyReader::visitDefaultInoutPinFallRes); + &LibertyReader::visitDefaultInoutPinFallRes); defineAttrVisitor("default_output_pin_rise_res", - &LibertyReader::visitDefaultOutputPinRiseRes); + &LibertyReader::visitDefaultOutputPinRiseRes); defineAttrVisitor("default_output_pin_fall_res", - &LibertyReader::visitDefaultOutputPinFallRes); + &LibertyReader::visitDefaultOutputPinFallRes); defineAttrVisitor("default_fanout_load", - &LibertyReader::visitDefaultFanoutLoad); + &LibertyReader::visitDefaultFanoutLoad); defineAttrVisitor("default_wire_load", - &LibertyReader::visitDefaultWireLoad); + &LibertyReader::visitDefaultWireLoad); defineAttrVisitor("default_wire_load_mode", - &LibertyReader::visitDefaultWireLoadMode); + &LibertyReader::visitDefaultWireLoadMode); defineAttrVisitor("default_wire_load_selection", - &LibertyReader::visitDefaultWireLoadSelection); + &LibertyReader::visitDefaultWireLoadSelection); defineAttrVisitor("default_operating_conditions", - &LibertyReader::visitDefaultOperatingConditions); + &LibertyReader::visitDefaultOperatingConditions); defineAttrVisitor("input_threshold_pct_fall", - &LibertyReader::visitInputThresholdPctFall); + &LibertyReader::visitInputThresholdPctFall); defineAttrVisitor("input_threshold_pct_rise", - &LibertyReader::visitInputThresholdPctRise); + &LibertyReader::visitInputThresholdPctRise); defineAttrVisitor("output_threshold_pct_fall", - &LibertyReader::visitOutputThresholdPctFall); + &LibertyReader::visitOutputThresholdPctFall); defineAttrVisitor("output_threshold_pct_rise", - &LibertyReader::visitOutputThresholdPctRise); + &LibertyReader::visitOutputThresholdPctRise); defineAttrVisitor("slew_lower_threshold_pct_fall", - &LibertyReader::visitSlewLowerThresholdPctFall); + &LibertyReader::visitSlewLowerThresholdPctFall); defineAttrVisitor("slew_lower_threshold_pct_rise", - &LibertyReader::visitSlewLowerThresholdPctRise); + &LibertyReader::visitSlewLowerThresholdPctRise); defineAttrVisitor("slew_upper_threshold_pct_fall", - &LibertyReader::visitSlewUpperThresholdPctFall); + &LibertyReader::visitSlewUpperThresholdPctFall); defineAttrVisitor("slew_upper_threshold_pct_rise", - &LibertyReader::visitSlewUpperThresholdPctRise); + &LibertyReader::visitSlewUpperThresholdPctRise); defineAttrVisitor("slew_derate_from_library", - &LibertyReader::visitSlewDerateFromLibrary); + &LibertyReader::visitSlewDerateFromLibrary); defineGroupVisitor("lu_table_template", - &LibertyReader::beginTableTemplateDelay, - &LibertyReader::endTableTemplate); + &LibertyReader::beginTableTemplateDelay, + &LibertyReader::endTableTemplate); defineGroupVisitor("output_current_template", - &LibertyReader::beginTableTemplateOutputCurrent, - &LibertyReader::endTableTemplate); + &LibertyReader::beginTableTemplateOutputCurrent, + &LibertyReader::endTableTemplate); defineAttrVisitor("variable_1", &LibertyReader::visitVariable1); defineAttrVisitor("variable_2", &LibertyReader::visitVariable2); defineAttrVisitor("variable_3", &LibertyReader::visitVariable3); @@ -257,47 +258,47 @@ LibertyReader::defineVisitors() &LibertyReader::beginTechnology, &LibertyReader::endTechnology); defineGroupVisitor("rise_transition_degradation", - &LibertyReader::beginRiseTransitionDegredation, - &LibertyReader::endRiseFallTransitionDegredation); + &LibertyReader::beginRiseTransitionDegredation, + &LibertyReader::endRiseFallTransitionDegredation); defineGroupVisitor("fall_transition_degradation", - &LibertyReader::beginFallTransitionDegredation, - &LibertyReader::endRiseFallTransitionDegredation); + &LibertyReader::beginFallTransitionDegredation, + &LibertyReader::endRiseFallTransitionDegredation); defineGroupVisitor("type", &LibertyReader::beginType, - &LibertyReader::endType); + &LibertyReader::endType); defineAttrVisitor("bit_from", &LibertyReader::visitBitFrom); defineAttrVisitor("bit_to", &LibertyReader::visitBitTo); defineGroupVisitor("scaling_factors", &LibertyReader::beginScalingFactors, - &LibertyReader::endScalingFactors); + &LibertyReader::endScalingFactors); defineScalingFactorVisitors(); defineGroupVisitor("operating_conditions", &LibertyReader::beginOpCond, - &LibertyReader::endOpCond); + &LibertyReader::endOpCond); defineAttrVisitor("process", &LibertyReader::visitProc); defineAttrVisitor("voltage", &LibertyReader::visitVolt); defineAttrVisitor("temperature", &LibertyReader::visitTemp); defineAttrVisitor("tree_type", &LibertyReader::visitTreeType); defineGroupVisitor("wire_load", &LibertyReader::beginWireload, - &LibertyReader::endWireload); + &LibertyReader::endWireload); defineAttrVisitor("resistance", &LibertyReader::visitResistance); defineAttrVisitor("slope", &LibertyReader::visitSlope); defineAttrVisitor("fanout_length", &LibertyReader::visitFanoutLength); defineGroupVisitor("wire_load_selection", - &LibertyReader::beginWireloadSelection, - &LibertyReader::endWireloadSelection); + &LibertyReader::beginWireloadSelection, + &LibertyReader::endWireloadSelection); defineAttrVisitor("wire_load_from_area", - &LibertyReader::visitWireloadFromArea); + &LibertyReader::visitWireloadFromArea); // Cells defineGroupVisitor("cell", &LibertyReader::beginCell, - &LibertyReader::endCell); + &LibertyReader::endCell); defineGroupVisitor("scaled_cell", &LibertyReader::beginScaledCell, - &LibertyReader::endScaledCell); + &LibertyReader::endScaledCell); defineAttrVisitor("clock_gating_integrated_cell", - &LibertyReader::visitClockGatingIntegratedCell); + &LibertyReader::visitClockGatingIntegratedCell); defineAttrVisitor("area", &LibertyReader::visitArea); defineAttrVisitor("dont_use", &LibertyReader::visitDontUse); defineAttrVisitor("is_macro_cell", &LibertyReader::visitIsMacro); @@ -320,7 +321,7 @@ LibertyReader::defineVisitors() defineGroupVisitor("pin", &LibertyReader::beginPin,&LibertyReader::endPin); defineGroupVisitor("bus", &LibertyReader::beginBus,&LibertyReader::endBus); defineGroupVisitor("bundle", &LibertyReader::beginBundle, - &LibertyReader::endBundle); + &LibertyReader::endBundle); defineAttrVisitor("direction", &LibertyReader::visitDirection); defineAttrVisitor("clock", &LibertyReader::visitClock); defineAttrVisitor("bus_type", &LibertyReader::visitBusType); @@ -331,9 +332,9 @@ LibertyReader::defineVisitors() defineAttrVisitor("rise_capacitance", &LibertyReader::visitRiseCap); defineAttrVisitor("fall_capacitance", &LibertyReader::visitFallCap); defineAttrVisitor("rise_capacitance_range", - &LibertyReader::visitRiseCapRange); + &LibertyReader::visitRiseCapRange); defineAttrVisitor("fall_capacitance_range", - &LibertyReader::visitFallCapRange); + &LibertyReader::visitFallCapRange); defineAttrVisitor("fanout_load", &LibertyReader::visitFanoutLoad); defineAttrVisitor("max_fanout", &LibertyReader::visitMaxFanout); defineAttrVisitor("min_fanout", &LibertyReader::visitMinFanout); @@ -343,19 +344,19 @@ LibertyReader::defineVisitors() defineAttrVisitor("min_capacitance", &LibertyReader::visitMinCapacitance); defineAttrVisitor("min_period", &LibertyReader::visitMinPeriod); defineAttrVisitor("min_pulse_width_low", - &LibertyReader::visitMinPulseWidthLow); + &LibertyReader::visitMinPulseWidthLow); defineAttrVisitor("min_pulse_width_high", - &LibertyReader::visitMinPulseWidthHigh); + &LibertyReader::visitMinPulseWidthHigh); defineAttrVisitor("pulse_clock", - &LibertyReader::visitPulseClock); + &LibertyReader::visitPulseClock); defineAttrVisitor("clock_gate_clock_pin", - &LibertyReader::visitClockGateClockPin); + &LibertyReader::visitClockGateClockPin); defineAttrVisitor("clock_gate_enable_pin", - &LibertyReader::visitClockGateEnablePin); + &LibertyReader::visitClockGateEnablePin); defineAttrVisitor("clock_gate_out_pin", - &LibertyReader::visitClockGateOutPin); + &LibertyReader::visitClockGateOutPin); defineAttrVisitor("is_pll_feedback_pin", - &LibertyReader::visitIsPllFeedbackPin); + &LibertyReader::visitIsPllFeedbackPin); defineAttrVisitor("signal_type", &LibertyReader::visitSignalType); defineAttrVisitor("isolation_cell_data_pin", @@ -368,16 +369,16 @@ LibertyReader::defineVisitors() // Memory defineGroupVisitor("memory", &LibertyReader::beginMemory, - &LibertyReader::endMemory); + &LibertyReader::endMemory); // Register/latch defineGroupVisitor("ff", &LibertyReader::beginFF, &LibertyReader::endFF); defineGroupVisitor("ff_bank", &LibertyReader::beginFFBank, - &LibertyReader::endFFBank); + &LibertyReader::endFFBank); defineGroupVisitor("latch", &LibertyReader::beginLatch, - &LibertyReader::endLatch); + &LibertyReader::endLatch); defineGroupVisitor("latch_bank", &LibertyReader::beginLatchBank, - &LibertyReader::endLatchBank); + &LibertyReader::endLatchBank); defineAttrVisitor("clocked_on", &LibertyReader::visitClockedOn); defineAttrVisitor("enable", &LibertyReader::visitClockedOn); defineAttrVisitor("data_in", &LibertyReader::visitDataIn); @@ -393,11 +394,11 @@ LibertyReader::defineVisitors() defineAttrVisitor("table", &LibertyReader::visitTable); defineGroupVisitor("timing", &LibertyReader::beginTiming, - &LibertyReader::endTiming); + &LibertyReader::endTiming); defineAttrVisitor("related_pin", &LibertyReader::visitRelatedPin); defineAttrVisitor("related_bus_pins", &LibertyReader::visitRelatedBusPins); defineAttrVisitor("related_output_pin", - &LibertyReader::visitRelatedOutputPin); + &LibertyReader::visitRelatedOutputPin); defineAttrVisitor("timing_type", &LibertyReader::visitTimingType); defineAttrVisitor("timing_sense", &LibertyReader::visitTimingSense); defineAttrVisitor("sdf_cond_start", &LibertyReader::visitSdfCondStart); @@ -408,47 +409,47 @@ LibertyReader::defineVisitors() defineAttrVisitor("rise_resistance", &LibertyReader::visitRiseResistance); defineAttrVisitor("fall_resistance", &LibertyReader::visitFallResistance); defineGroupVisitor("cell_rise", &LibertyReader::beginCellRise, - &LibertyReader::endCellRiseFall); + &LibertyReader::endCellRiseFall); defineGroupVisitor("cell_fall", &LibertyReader::beginCellFall, - &LibertyReader::endCellRiseFall); + &LibertyReader::endCellRiseFall); defineGroupVisitor("rise_transition", &LibertyReader::beginRiseTransition, - &LibertyReader::endRiseFallTransition); + &LibertyReader::endRiseFallTransition); defineGroupVisitor("fall_transition", &LibertyReader::beginFallTransition, - &LibertyReader::endRiseFallTransition); + &LibertyReader::endRiseFallTransition); defineGroupVisitor("rise_constraint", &LibertyReader::beginRiseConstraint, - &LibertyReader::endRiseFallConstraint); + &LibertyReader::endRiseFallConstraint); defineGroupVisitor("fall_constraint", &LibertyReader::beginFallConstraint, - &LibertyReader::endRiseFallConstraint); + &LibertyReader::endRiseFallConstraint); defineAttrVisitor("value", &LibertyReader::visitValue); defineAttrVisitor("values", &LibertyReader::visitValues); defineGroupVisitor("lut", &LibertyReader::beginLut,&LibertyReader::endLut); defineGroupVisitor("test_cell", &LibertyReader::beginTestCell, - &LibertyReader::endTestCell); + &LibertyReader::endTestCell); defineGroupVisitor("mode_definition", &LibertyReader::beginModeDef, - &LibertyReader::endModeDef); + &LibertyReader::endModeDef); defineGroupVisitor("mode_value", &LibertyReader::beginModeValue, - &LibertyReader::endModeValue); + &LibertyReader::endModeValue); defineAttrVisitor("when", &LibertyReader::visitWhen); defineAttrVisitor("sdf_cond", &LibertyReader::visitSdfCond); // Power attributes. defineGroupVisitor("power_lut_template", - &LibertyReader::beginTableTemplatePower, - &LibertyReader::endTableTemplate); + &LibertyReader::beginTableTemplatePower, + &LibertyReader::endTableTemplate); defineGroupVisitor("leakage_power", &LibertyReader::beginLeakagePower, - &LibertyReader::endLeakagePower); + &LibertyReader::endLeakagePower); defineGroupVisitor("internal_power", &LibertyReader::beginInternalPower, - &LibertyReader::endInternalPower); + &LibertyReader::endInternalPower); // power group for both rise/fall defineGroupVisitor("power", &LibertyReader::beginRisePower, - &LibertyReader::endPower); + &LibertyReader::endPower); defineGroupVisitor("fall_power", &LibertyReader::beginFallPower, - &LibertyReader::endRiseFallPower); + &LibertyReader::endRiseFallPower); defineGroupVisitor("rise_power", &LibertyReader::beginRisePower, - &LibertyReader::endRiseFallPower); + &LibertyReader::endRiseFallPower); defineAttrVisitor("related_ground_pin",&LibertyReader::visitRelatedGroundPin); defineAttrVisitor("related_power_pin", &LibertyReader::visitRelatedPowerPin); defineAttrVisitor("related_pg_pin", &LibertyReader::visitRelatedPgPin); @@ -456,43 +457,43 @@ LibertyReader::defineVisitors() // AOCV attributes. defineAttrVisitor("ocv_arc_depth", &LibertyReader::visitOcvArcDepth); defineAttrVisitor("default_ocv_derate_group", - &LibertyReader::visitDefaultOcvDerateGroup); + &LibertyReader::visitDefaultOcvDerateGroup); defineAttrVisitor("ocv_derate_group", &LibertyReader::visitOcvDerateGroup); defineGroupVisitor("ocv_table_template", - &LibertyReader::beginTableTemplateOcv, - &LibertyReader::endTableTemplate); + &LibertyReader::beginTableTemplateOcv, + &LibertyReader::endTableTemplate); defineGroupVisitor("ocv_derate", - &LibertyReader::beginOcvDerate, - &LibertyReader::endOcvDerate); + &LibertyReader::beginOcvDerate, + &LibertyReader::endOcvDerate); defineGroupVisitor("ocv_derate_factors", - &LibertyReader::beginOcvDerateFactors, - &LibertyReader::endOcvDerateFactors); + &LibertyReader::beginOcvDerateFactors, + &LibertyReader::endOcvDerateFactors); defineAttrVisitor("rf_type", &LibertyReader::visitRfType); defineAttrVisitor("derate_type", &LibertyReader::visitDerateType); defineAttrVisitor("path_type", &LibertyReader::visitPathType); // POCV attributes. defineGroupVisitor("ocv_sigma_cell_rise", &LibertyReader::beginOcvSigmaCellRise, - &LibertyReader::endOcvSigmaCell); + &LibertyReader::endOcvSigmaCell); defineGroupVisitor("ocv_sigma_cell_fall", &LibertyReader::beginOcvSigmaCellFall, - &LibertyReader::endOcvSigmaCell); + &LibertyReader::endOcvSigmaCell); defineGroupVisitor("ocv_sigma_rise_transition", - &LibertyReader::beginOcvSigmaRiseTransition, - &LibertyReader::endOcvSigmaTransition); + &LibertyReader::beginOcvSigmaRiseTransition, + &LibertyReader::endOcvSigmaTransition); defineGroupVisitor("ocv_sigma_fall_transition", - &LibertyReader::beginOcvSigmaFallTransition, - &LibertyReader::endOcvSigmaTransition); + &LibertyReader::beginOcvSigmaFallTransition, + &LibertyReader::endOcvSigmaTransition); defineGroupVisitor("ocv_sigma_rise_constraint", - &LibertyReader::beginOcvSigmaRiseConstraint, - &LibertyReader::endOcvSigmaConstraint); + &LibertyReader::beginOcvSigmaRiseConstraint, + &LibertyReader::endOcvSigmaConstraint); defineGroupVisitor("ocv_sigma_fall_constraint", - &LibertyReader::beginOcvSigmaFallConstraint, - &LibertyReader::endOcvSigmaConstraint); + &LibertyReader::beginOcvSigmaFallConstraint, + &LibertyReader::endOcvSigmaConstraint); defineAttrVisitor("sigma_type", &LibertyReader::visitSigmaType); defineAttrVisitor("cell_leakage_power", &LibertyReader::visitCellLeakagePower); defineGroupVisitor("pg_pin", &LibertyReader::beginPgPin, - &LibertyReader::endPgPin); + &LibertyReader::endPgPin); defineAttrVisitor("pg_type", &LibertyReader::visitPgType); defineAttrVisitor("voltage_name", &LibertyReader::visitVoltageName); @@ -539,28 +540,28 @@ LibertyReader::defineVisitors() // ccsn (not implemented, this is needed to properly ignore ccsn groups) defineGroupVisitor("ccsn_first_stage", &LibertyReader::beginCcsn, - &LibertyReader::endCcsn); + &LibertyReader::endCcsn); defineGroupVisitor("ccsn_last_stage", &LibertyReader::beginCcsn, - &LibertyReader::endCcsn); + &LibertyReader::endCcsn); defineGroupVisitor("output_voltage_rise", &LibertyReader::beginCcsn, - &LibertyReader::endCcsn); + &LibertyReader::endCcsn); defineGroupVisitor("output_voltage_fall", &LibertyReader::beginCcsn, - &LibertyReader::endCcsn); + &LibertyReader::endCcsn); defineGroupVisitor("propagated_noise_low", &LibertyReader::beginCcsn, - &LibertyReader::endCcsn); + &LibertyReader::endCcsn); defineGroupVisitor("propagated_noise_high", &LibertyReader::beginCcsn, - &LibertyReader::endCcsn); + &LibertyReader::endCcsn); defineGroupVisitor("input_ccb", &LibertyReader::beginCcsn, - &LibertyReader::endCcsn); + &LibertyReader::endCcsn); defineGroupVisitor("output_ccb", &LibertyReader::beginCcsn, - &LibertyReader::endCcsn); + &LibertyReader::endCcsn); defineGroupVisitor("ecsm_waveform", &LibertyReader::beginEcsmWaveform, - &LibertyReader::endEcsmWaveform); + &LibertyReader::endEcsmWaveform); defineGroupVisitor("ecsm_waveform_set", &LibertyReader::beginEcsmWaveform, - &LibertyReader::endEcsmWaveform); + &LibertyReader::endEcsmWaveform); defineGroupVisitor("ecsm_capacitance", &LibertyReader::beginEcsmWaveform, - &LibertyReader::endEcsmWaveform); + &LibertyReader::endEcsmWaveform); } void @@ -573,40 +574,40 @@ LibertyReader::defineScalingFactorVisitors() ScaleFactorPvt pvt = static_cast(pvt_index); const char *pvt_name = scaleFactorPvtName(pvt); if (scaleFactorTypeRiseFallSuffix(type)) { - for (auto tr : RiseFall::range()) { - const char *tr_name = (tr == RiseFall::rise()) ? "rise":"fall"; - string attr_name; + for (auto tr : RiseFall::range()) { + const char *tr_name = (tr == RiseFall::rise()) ? "rise":"fall"; + string attr_name; stringPrint(attr_name, "k_%s_%s_%s", pvt_name, type_name, tr_name); - defineAttrVisitor(attr_name.c_str() ,&LibertyReader::visitScaleFactorSuffix); - } + defineAttrVisitor(attr_name.c_str() ,&LibertyReader::visitScaleFactorSuffix); + } } else if (scaleFactorTypeRiseFallPrefix(type)) { - for (auto tr : RiseFall::range()) { - const char *tr_name = (tr == RiseFall::rise()) ? "rise":"fall"; - string attr_name; + for (auto tr : RiseFall::range()) { + const char *tr_name = (tr == RiseFall::rise()) ? "rise":"fall"; + string attr_name; stringPrint(attr_name, "k_%s_%s_%s", pvt_name, tr_name, type_name); - defineAttrVisitor(attr_name.c_str(),&LibertyReader::visitScaleFactorPrefix); - } + defineAttrVisitor(attr_name.c_str(),&LibertyReader::visitScaleFactorPrefix); + } } else if (scaleFactorTypeLowHighSuffix(type)) { - for (auto tr : RiseFall::range()) { - const char *tr_name = (tr == RiseFall::rise()) ? "high":"low"; - string attr_name; + for (auto tr : RiseFall::range()) { + const char *tr_name = (tr == RiseFall::rise()) ? "high":"low"; + string attr_name; stringPrint(attr_name, "k_%s_%s_%s", pvt_name, tr_name, type_name); - defineAttrVisitor(attr_name.c_str(),&LibertyReader::visitScaleFactorHiLow); - } + defineAttrVisitor(attr_name.c_str(),&LibertyReader::visitScaleFactorHiLow); + } } else { - string attr_name; + string attr_name; stringPrint(attr_name, "k_%s_%s", pvt_name, type_name); @@ -619,25 +620,25 @@ LibertyReader::defineScalingFactorVisitors() void LibertyReader::visitAttr(LibertyAttr *attr) { - LibraryAttrVisitor visitor = attr_visitor_map_.findKey(attr->name()); + LibraryAttrVisitor *visitor = findKeyValuePtr(attr_visitor_map_, attr->name()); if (visitor) - (this->*visitor)(attr); + (this->**visitor)(attr); } void LibertyReader::begin(LibertyGroup *group) { - LibraryGroupVisitor visitor = group_begin_map_.findKey(group->type()); + LibraryGroupVisitor *visitor = findKeyValuePtr(group_begin_map_, group->type()); if (visitor) - (this->*visitor)(group); + (this->**visitor)(group); } void LibertyReader::end(LibertyGroup *group) { - LibraryGroupVisitor visitor = group_end_map_.findKey(group->type()); + LibraryGroupVisitor *visitor = findKeyValuePtr(group_end_map_, group->type()); if (visitor) - (this->*visitor)(group); + (this->**visitor)(group); } void @@ -718,7 +719,7 @@ LibertyReader::endLibraryAttrs(LibertyGroup *group) library_->setDefaultWireloadSelection(selection); else libWarn(1143, group, "default_wire_selection %s not found.", - default_wireload_selection_); + default_wireload_selection_); stringDelete(default_wireload_selection_); default_wireload_selection_ = nullptr; } @@ -730,7 +731,7 @@ LibertyReader::endLibraryAttrs(LibertyGroup *group) library_->setDefaultOperatingConditions(op_cond); else libWarn(1144, group, "default_operating_condition %s not found.", - default_operating_condition_); + default_operating_condition_); stringDelete(default_operating_condition_); default_operating_condition_ = nullptr; } @@ -757,7 +758,7 @@ LibertyReader::endLibraryAttrs(LibertyGroup *group) } if (missing_threshold) libError(1149, group, "Library %s is missing one or more thresholds.", - library_->name()); + library_->name()); } void @@ -772,7 +773,7 @@ LibertyReader::visitPullingResistanceUnit(LibertyAttr *attr) { if (library_) parseUnits(attr, "ohm", res_scale_, - library_->units()->resistanceUnit()); + library_->units()->resistanceUnit()); } void @@ -813,9 +814,9 @@ LibertyReader::visitDistanceUnit(LibertyAttr *attr) void LibertyReader::parseUnits(LibertyAttr *attr, - const char *unit_suffix, - float &scale_var, - Unit *unit) + const char *unit_suffix, + float &scale_var, + Unit *unit) { string units = getAttrString(attr); if (!units.empty()) { @@ -875,48 +876,46 @@ LibertyReader::visitCapacitiveLoadUnit(LibertyAttr *attr) { if (library_) { if (attr->isComplex()) { - LibertyAttrValueIterator value_iter(attr->values()); - if (value_iter.hasNext()) { - LibertyAttrValue *value = value_iter.next(); - bool valid = false; - float scale; - if (value->isFloat()) { - scale = value->floatValue(); - valid = true; - } - else if (value->isString()) { - try { - scale = std::stof(value->stringValue()); - valid = true; - } - catch (...) { - valid = false; - } - } + LibertyAttrValueSeq *values = attr->values(); + if (values->size() == 2) { + LibertyAttrValue *value = (*values)[0]; + bool valid = false; + float scale; + if (value->isFloat()) { + scale = value->floatValue(); + valid = true; + } + else if (value->isString()) { + try { + scale = std::stof(value->stringValue()); + valid = true; + } + catch (...) { + valid = false; + } + } - if (valid) { - if (value_iter.hasNext()) { - value = value_iter.next(); - if (value->isString()) { - const char *suffix = value->stringValue(); - if (stringEqual(suffix, "ff")) - cap_scale_ = scale * 1E-15F; - else if (stringEqual(suffix, "pf")) - cap_scale_ = scale * 1E-12F; - else - libWarn(1154, attr, "capacitive_load_units are not ff or pf."); - } - else - libWarn(1155, attr, "capacitive_load_units are not a string."); - } - else - libWarn(1156, attr, "capacitive_load_units missing suffix."); - } - else - libWarn(1157, attr, "capacitive_load_units scale is not a float."); + if (valid) { + value = (*values)[1]; + if (value->isString()) { + const char *suffix = value->stringValue(); + if (stringEqual(suffix, "ff")) + cap_scale_ = scale * 1E-15F; + else if (stringEqual(suffix, "pf")) + cap_scale_ = scale * 1E-12F; + else + libWarn(1154, attr, "capacitive_load_units are not ff or pf."); + } + else + libWarn(1155, attr, "capacitive_load_units are not a string."); + } + else + libWarn(1157, attr, "capacitive_load_units scale is not a float."); } + else if (values->size() == 1) + libWarn(1156, attr, "capacitive_load_units missing suffix."); else - libWarn(1158, attr, "capacitive_load_units missing scale and suffix."); + libWarn(1158, attr, "capacitive_load_units missing scale and suffix."); } else libWarn(1159, attr, "capacitive_load_unit missing values suffix."); @@ -932,28 +931,28 @@ LibertyReader::visitDelayModel(LibertyAttr *attr) const char *type_name = getAttrString(attr); if (type_name) { if (stringEq(type_name, "table_lookup")) - library_->setDelayModelType(DelayModelType::table); + library_->setDelayModelType(DelayModelType::table); else if (stringEq(type_name, "generic_cmos")) - library_->setDelayModelType(DelayModelType::cmos_linear); + library_->setDelayModelType(DelayModelType::cmos_linear); else if (stringEq(type_name, "piecewise_cmos")) { - library_->setDelayModelType(DelayModelType::cmos_pwl); - libWarn(1160, attr, "delay_model %s not supported.", type_name); + library_->setDelayModelType(DelayModelType::cmos_pwl); + libWarn(1160, attr, "delay_model %s not supported.", type_name); } else if (stringEq(type_name, "cmos2")) { - library_->setDelayModelType(DelayModelType::cmos2); - libWarn(1161, attr, "delay_model %s not supported.", type_name); + library_->setDelayModelType(DelayModelType::cmos2); + libWarn(1161, attr, "delay_model %s not supported.", type_name); } else if (stringEq(type_name, "polynomial")) { - library_->setDelayModelType(DelayModelType::polynomial); - libWarn(1162, attr, "delay_model %s not supported.", type_name); + library_->setDelayModelType(DelayModelType::polynomial); + libWarn(1162, attr, "delay_model %s not supported.", type_name); } // Evil IBM garbage. else if (stringEq(type_name, "dcm")) { - library_->setDelayModelType(DelayModelType::dcm); - libWarn(1163, attr, "delay_model %s not supported..", type_name); + library_->setDelayModelType(DelayModelType::dcm); + libWarn(1163, attr, "delay_model %s not supported..", type_name); } else - libWarn(1164, attr, "unknown delay_model %s.", type_name); + libWarn(1164, attr, "unknown delay_model %s.", type_name); } } } @@ -965,11 +964,11 @@ LibertyReader::visitBusStyle(LibertyAttr *attr) const char *bus_style = getAttrString(attr); // Assume bus style is of the form "%s[%d]". if (bus_style - && strlen(bus_style) == 6 - && bus_style[0] == '%' - && bus_style[1] == 's' - && bus_style[3] == '%' - && bus_style[4] == 'd') + && strlen(bus_style) == 6 + && bus_style[0] == '%' + && bus_style[1] == 's' + && bus_style[3] == '%' + && bus_style[4] == 'd') library_->setBusBrkts(bus_style[2], bus_style[5]); else libWarn(1165, attr, "unknown bus_naming_style format."); @@ -981,42 +980,42 @@ LibertyReader::visitVoltageMap(LibertyAttr *attr) { if (library_) { if (attr->isComplex()) { - LibertyAttrValueIterator value_iter(attr->values()); - if (value_iter.hasNext()) { - LibertyAttrValue *value = value_iter.next(); - if (value->isString()) { - const char *supply_name = value->stringValue(); - if (value_iter.hasNext()) { - value = value_iter.next(); + LibertyAttrValueSeq *values = attr->values(); + if (values->size() >= 1) { + LibertyAttrValue *value = (*values)[0]; + if (value->isString()) { + const char *supply_name = value->stringValue(); + if (values->size() == 2) { + value = (*values)[1]; bool valid = false; - float voltage; - if (value->isFloat()) { - voltage = value->floatValue(); - valid = true; - } - else if (value->isString()) { - try { + float voltage; + if (value->isFloat()) { + voltage = value->floatValue(); + valid = true; + } + else if (value->isString()) { + try { voltage = std::stof(value->stringValue()); valid = true; - } - catch (...) { - valid = false; - } - } + } + catch (...) { + valid = false; + } + } - if (valid) - library_->addSupplyVoltage(supply_name, voltage); - else - libWarn(1166, attr, "voltage_map voltage is not a float."); - } - else - libWarn(1167, attr, "voltage_map missing voltage."); - } - else - libWarn(1168, attr, "voltage_map supply name is not a string."); + if (valid) + library_->addSupplyVoltage(supply_name, voltage); + else + libWarn(1166, attr, "voltage_map voltage is not a float."); + } + else + libWarn(1167, attr, "voltage_map missing voltage."); + } + else + libWarn(1168, attr, "voltage_map supply name is not a string."); } else - libWarn(1169, attr, "voltage_map missing supply name and voltage."); + libWarn(1169, attr, "voltage_map missing supply name and voltage."); } else libWarn(1170, attr, "voltage_map missing values suffix."); @@ -1104,7 +1103,7 @@ LibertyReader::visitDefaultMaxTransition(LibertyAttr *attr) getAttrFloat(attr, value, exists); if (exists) { if (value == 0.0) - libWarn(1171, attr, "default_max_transition is 0.0."); + libWarn(1171, attr, "default_max_transition is 0.0."); library_->setDefaultMaxSlew(value * time_scale_); } } @@ -1119,7 +1118,7 @@ LibertyReader::visitDefaultMaxFanout(LibertyAttr *attr) getAttrFloat(attr, value, exists); if (exists) { if (value == 0.0) - libWarn(1172, attr, "default_max_fanout is 0.0."); + libWarn(1172, attr, "default_max_fanout is 0.0."); library_->setDefaultMaxFanout(value); } } @@ -1139,7 +1138,7 @@ LibertyReader::visitDefaultIntrinsicFall(LibertyAttr *attr) void LibertyReader::visitDefaultIntrinsic(LibertyAttr *attr, - const RiseFall *rf) + const RiseFall *rf) { if (library_) { float value; @@ -1164,7 +1163,7 @@ LibertyReader::visitDefaultInoutPinFallRes(LibertyAttr *attr) void LibertyReader::visitDefaultInoutPinRes(LibertyAttr *attr, - const RiseFall *rf) + const RiseFall *rf) { if (library_) { float value; @@ -1189,7 +1188,7 @@ LibertyReader::visitDefaultOutputPinFallRes(LibertyAttr *attr) void LibertyReader::visitDefaultOutputPinRes(LibertyAttr *attr, - const RiseFall *rf) + const RiseFall *rf) { if (library_) { float value; @@ -1209,7 +1208,7 @@ LibertyReader::visitDefaultFanoutLoad(LibertyAttr *attr) getAttrFloat(attr, value, exists); if (exists) { if (value == 0.0) - libWarn(1173, attr, "default_fanout_load is 0.0."); + libWarn(1173, attr, "default_fanout_load is 0.0."); library_->setDefaultFanoutLoad(value); } } @@ -1235,10 +1234,10 @@ LibertyReader::visitDefaultWireLoadMode(LibertyAttr *attr) if (wire_load_mode) { WireloadMode mode = stringWireloadMode(wire_load_mode); if (mode != WireloadMode::unknown) - library_->setDefaultWireloadMode(mode); + library_->setDefaultWireloadMode(mode); else - libWarn(1174, attr, "default_wire_load_mode %s not found.", - wire_load_mode); + libWarn(1174, attr, "default_wire_load_mode %s not found.", + wire_load_mode); } } } @@ -1281,7 +1280,7 @@ LibertyReader::visitInputThresholdPctRise(LibertyAttr *attr) void LibertyReader::visitInputThresholdPct(LibertyAttr *attr, - const RiseFall *rf) + const RiseFall *rf) { if (library_) { float value; @@ -1307,7 +1306,7 @@ LibertyReader::visitOutputThresholdPctRise(LibertyAttr *attr) void LibertyReader::visitOutputThresholdPct(LibertyAttr *attr, - const RiseFall *rf) + const RiseFall *rf) { if (library_) { float value; @@ -1333,7 +1332,7 @@ LibertyReader::visitSlewLowerThresholdPctRise(LibertyAttr *attr) void LibertyReader::visitSlewLowerThresholdPct(LibertyAttr *attr, - const RiseFall *rf) + const RiseFall *rf) { if (library_) { float value; @@ -1359,7 +1358,7 @@ LibertyReader::visitSlewUpperThresholdPctRise(LibertyAttr *attr) void LibertyReader::visitSlewUpperThresholdPct(LibertyAttr *attr, - const RiseFall *rf) + const RiseFall *rf) { if (library_) { float value; @@ -1414,7 +1413,7 @@ LibertyReader::beginTableTemplateOutputCurrent(LibertyGroup *group) void LibertyReader::beginTableTemplate(LibertyGroup *group, - TableTemplateType type) + TableTemplateType type) { if (library_) { const char *name = group->firstName(); @@ -1455,7 +1454,7 @@ LibertyReader::endTableTemplate(LibertyGroup *group) TableAxisPtr LibertyReader::makeAxis(int index, - LibertyGroup *group) + LibertyGroup *group) { TableAxisVariable axis_var = axis_var_[index]; FloatSeq *axis_values = axis_values_[index]; @@ -1504,7 +1503,7 @@ LibertyReader::visitVariable3(LibertyAttr *attr) void LibertyReader::visitVariable(int index, - LibertyAttr *attr) + LibertyAttr *attr) { if (tbl_template_) { const char *type = getAttrString(attr); @@ -1536,7 +1535,7 @@ LibertyReader::visitIndex3(LibertyAttr *attr) void LibertyReader::visitIndex(int index, - LibertyAttr *attr) + LibertyAttr *attr) { if (tbl_template_ // Ignore index_xx in ecsm_waveform groups. @@ -1576,15 +1575,15 @@ LibertyReader::endType(LibertyGroup *group) if (type_bit_from_exists_ && type_bit_to_exists_) { BusDcl *bus_dcl = new BusDcl(name, type_bit_from_, type_bit_to_); if (cell_) - cell_->addBusDcl(bus_dcl); + cell_->addBusDcl(bus_dcl); else if (library_) - library_->addBusDcl(bus_dcl); + library_->addBusDcl(bus_dcl); } else { if (!type_bit_from_exists_) - libWarn(1179, group, "bus type %s missing bit_from.", name); + libWarn(1179, group, "bus type %s missing bit_from.", name); if (!type_bit_to_exists_) - libWarn(1180, group, "bus type %s missing bit_to.", name); + libWarn(1180, group, "bus type %s missing bit_to.", name); } } else @@ -1646,18 +1645,18 @@ LibertyReader::visitScaleFactorSuffix(LibertyAttr *attr) if (parser.hasNext()) { const char *tr_name = parser.next(); if (stringEq(tr_name, "rise")) - rf = RiseFall::rise(); + rf = RiseFall::rise(); else if (stringEq(tr_name, "fall")) - rf = RiseFall::fall(); + rf = RiseFall::fall(); } if (pvt != ScaleFactorPvt::unknown - && type != ScaleFactorType::unknown - && rf) { + && type != ScaleFactorType::unknown + && rf) { float value; bool exists; getAttrFloat(attr, value, exists); if (exists) - scale_factors_->setScale(type, pvt, rf, value); + scale_factors_->setScale(type, pvt, rf, value); } } } @@ -1680,22 +1679,22 @@ LibertyReader::visitScaleFactorPrefix(LibertyAttr *attr) if (parser.hasNext()) { const char *tr_name = parser.next(); if (stringEq(tr_name, "rise")) - rf = RiseFall::rise(); + rf = RiseFall::rise(); else if (stringEq(tr_name, "fall")) - rf = RiseFall::fall(); + rf = RiseFall::fall(); } if (parser.hasNext()) { const char *type_name = parser.next(); type = findScaleFactorType(type_name); } if (pvt != ScaleFactorPvt::unknown - && type != ScaleFactorType::unknown - && rf) { + && type != ScaleFactorType::unknown + && rf) { float value; bool exists; getAttrFloat(attr, value, exists); if (exists) - scale_factors_->setScale(type, pvt, rf, value); + scale_factors_->setScale(type, pvt, rf, value); } } } @@ -1725,18 +1724,18 @@ LibertyReader::visitScaleFactorHiLow(LibertyAttr *attr) if (parser.hasNext()) { tr_name = parser.next(); if (stringEq(tr_name, "high")) - rf = RiseFall::rise(); + rf = RiseFall::rise(); else if (stringEq(tr_name, "low")) - rf = RiseFall::fall(); + rf = RiseFall::fall(); } if (pvt != ScaleFactorPvt::unknown - && type != ScaleFactorType::unknown - && rf) { + && type != ScaleFactorType::unknown + && rf) { float value; bool exists; getAttrFloat(attr, value, exists); if (exists) - scale_factors_->setScale(type, pvt, rf, value); + scale_factors_->setScale(type, pvt, rf, value); } } } @@ -1762,12 +1761,12 @@ LibertyReader::visitScaleFactor(LibertyAttr *attr) type = findScaleFactorType(type_name); } if (pvt != ScaleFactorPvt::unknown - && type != ScaleFactorType::unknown) { + && type != ScaleFactorType::unknown) { float value; bool exists; getAttrFloat(attr, value, exists); if (exists) - scale_factors_->setScale(type, pvt, value); + scale_factors_->setScale(type, pvt, value); } } } @@ -1927,37 +1926,38 @@ LibertyReader::visitWireloadFromArea(LibertyAttr *attr) { if (wireload_selection_) { if (attr->isComplex()) { - LibertyAttrValueIterator value_iter(attr->values()); - if (value_iter.hasNext()) { - LibertyAttrValue *value = value_iter.next(); - if (value->isFloat()) { - float min_area = value->floatValue(); - value = value_iter.next(); - if (value->isFloat()) { - float max_area = value->floatValue(); - value = value_iter.next(); - if (value->isString()) { - const char *wireload_name = value->stringValue(); - const Wireload *wireload = - library_->findWireload(wireload_name); - if (wireload) - wireload_selection_->addWireloadFromArea(min_area, max_area, - wireload); - else - libWarn(1187, attr, "wireload %s not found.", wireload_name); - } - else - libWarn(1188, attr, - "wire_load_from_area wireload name not a string."); - } - else - libWarn(1189, attr, "wire_load_from_area min not a float."); - } - else - libWarn(1190, attr, "wire_load_from_area max not a float."); + LibertyAttrValueSeq *values = attr->values(); + if (values->size() == 3) { + LibertyAttrValue *value = (*values)[0]; + if (value->isFloat()) { + float min_area = value->floatValue(); + value = (*values)[1]; + if (value->isFloat()) { + float max_area = value->floatValue(); + + value = (*values)[2]; + if (value->isString()) { + const char *wireload_name = value->stringValue(); + const Wireload *wireload = + library_->findWireload(wireload_name); + if (wireload) + wireload_selection_->addWireloadFromArea(min_area, max_area, + wireload); + else + libWarn(1187, attr, "wireload %s not found.", wireload_name); + } + else + libWarn(1188, attr, + "wire_load_from_area wireload name not a string."); + } + else + libWarn(1189, attr, "wire_load_from_area min not a float."); + } + else + libWarn(1190, attr, "wire_load_from_area max not a float."); } else - libWarn(1191, attr, "wire_load_from_area missing parameters."); + libWarn(1191, attr, "wire_load_from_area missing parameters."); } else libWarn(1192, attr, "wire_load_from_area missing parameters."); @@ -1999,12 +1999,12 @@ LibertyReader::endCell(LibertyGroup *group) if (ocv_derate_name_) { OcvDerate *derate = cell_->findOcvDerate(ocv_derate_name_); if (derate == nullptr) - derate = library_->findOcvDerate(ocv_derate_name_); + derate = library_->findOcvDerate(ocv_derate_name_); if (derate) - cell_->setOcvDerate(derate); + cell_->setOcvDerate(derate); else - libWarn(1194, group, "cell %s ocv_derate_group %s not found.", - cell_->name(), ocv_derate_name_); + libWarn(1194, group, "cell %s ocv_derate_group %s not found.", + cell_->name(), ocv_derate_name_); stringDelete(ocv_derate_name_); ocv_derate_name_ = nullptr; } @@ -2031,13 +2031,13 @@ LibertyReader::finishPortGroups() void LibertyReader::checkPort(LibertyPort *port, - int line) + int line) { FuncExpr *func_expr = port->function(); if (func_expr) { if (func_expr->checkSize(port)) { libWarn(1195, line, "port %s function size does not match port size.", - port->name()); + port->name()); } } if (port->tristateEnable() @@ -2170,9 +2170,9 @@ LibertyReader::makeCellSequential(SequentialGroup *seq) } } cell_->makeSequential(size, is_register, clk_expr, data_expr, clr_expr, - preset_expr, seq->clrPresetVar1(), - seq->clrPresetVar2(), - seq->outPort(), seq->outInvPort()); + preset_expr, seq->clrPresetVar1(), + seq->clrPresetVar2(), + seq->outPort(), seq->outInvPort()); if (!is_register) checkLatchEnableSense(clk_expr, line); @@ -2189,11 +2189,10 @@ LibertyReader::makeCellSequential(SequentialGroup *seq) void LibertyReader::checkLatchEnableSense(FuncExpr *enable_func, - int line) + int line) { - FuncExprPortIterator enable_iter(enable_func); - while (enable_iter.hasNext()) { - LibertyPort *enable_port = enable_iter.next(); + LibertyPortSet enable_ports = enable_func->ports(); + for (LibertyPort *enable_port : enable_ports) { TimingSense enable_sense = enable_func->portTimingSense(enable_port); switch (enable_sense) { case TimingSense::positive_unate: @@ -2201,12 +2200,12 @@ LibertyReader::checkLatchEnableSense(FuncExpr *enable_func, break; case TimingSense::non_unate: libWarn(1200, line, "latch enable function is non-unate for port %s.", - enable_port->name()); + enable_port->name()); break; case TimingSense::none: case TimingSense::unknown: libWarn(1201, line, "latch enable function is unknown for port %s.", - enable_port->name()); + enable_port->name()); break; } } @@ -2224,14 +2223,14 @@ LibertyReader::makeStatetable() if (port) input_ports.push_back(port); else - libWarn(1298, statetable_->line(), "statetable input port %s not found.", + libWarn(1298, statetable_->line(), "statetable input port %s not found.", input.c_str()); } LibertyPortSeq internal_ports; for (const string &internal : statetable_->internalPorts()) { LibertyPort *port = cell_->findLibertyPort(internal.c_str()); if (port == nullptr) - port = makePort(cell_, internal.c_str()); + port = makePort(cell_, internal.c_str()); internal_ports.push_back(port); } cell_->makeStatetable(input_ports, internal_ports, statetable_->table()); @@ -2257,9 +2256,9 @@ LibertyReader::makeLeakagePowers() void LibertyReader::makeLibertyFunc(const char *expr, LibertySetFunc set_func, - bool invert, - const char *attr_name, - LibertyStmt *stmt) + bool invert, + const char *attr_name, + LibertyStmt *stmt) { LibertyFunc *func = new LibertyFunc(expr, set_func, invert, attr_name, stmt->line()); @@ -2272,13 +2271,13 @@ LibertyReader::parseCellFuncs() for (LibertyFunc *func : cell_funcs_) { FuncExpr *expr = parseFunc(func->expr(), func->attrName(), func->line()); if (func->invert() && expr) { - if (expr->op() == FuncExpr::op_not) { - FuncExpr *inv = expr; - expr = expr->left(); - delete inv; + if (expr->op() == FuncExpr::Op::not_) { + FuncExpr *inv = expr; + expr = expr->left(); + delete inv; } else - expr = FuncExpr::makeNot(expr); + expr = FuncExpr::makeNot(expr); } if (expr) func->setFunc()(expr); @@ -2296,17 +2295,17 @@ LibertyReader::beginScaledCell(LibertyGroup *group) if (scaled_cell_owner_) { const char *op_cond_name = group->secondName(); if (op_cond_name) { - op_cond_ = library_->findOperatingConditions(op_cond_name); - if (op_cond_) { - debugPrint(debug_, "liberty", 1, "scaled cell %s %s", + op_cond_ = library_->findOperatingConditions(op_cond_name); + if (op_cond_) { + debugPrint(debug_, "liberty", 1, "scaled cell %s %s", name, op_cond_name); - cell_ = library_->makeScaledCell(name, filename_); - } - else - libWarn(1202, group, "operating conditions %s not found.", op_cond_name); + cell_ = library_->makeScaledCell(name, filename_); + } + else + libWarn(1202, group, "operating conditions %s not found.", op_cond_name); } else - libWarn(1203, group, "scaled_cell missing operating condition."); + libWarn(1203, group, "scaled_cell missing operating condition."); } else libWarn(1204, group, "scaled_cell cell %s has not been defined.", name); @@ -2339,25 +2338,25 @@ LibertyReader::checkScaledCell(LibertyGroup *group) if (equivCellPorts(cell_, scaled_cell_owner_)) { if (!equivCellPorts(cell_, scaled_cell_owner_)) libWarn(1206, group, "scaled_cell %s, %s ports do not match cell ports", - cell_->name(), - op_cond_->name()); + cell_->name(), + op_cond_->name()); if (!equivCellFuncs(cell_, scaled_cell_owner_)) libWarn(1206, group, "scaled_cell %s, %s port functions do not match cell port functions.", - cell_->name(), - op_cond_->name()); + cell_->name(), + op_cond_->name()); } else libWarn(1207, group, "scaled_cell ports do not match cell ports."); if (!equivCellTimingArcSets(cell_, scaled_cell_owner_)) libWarn(1208, group, "scaled_cell %s, %s timing does not match cell timing.", - cell_->name(), - op_cond_->name()); + cell_->name(), + op_cond_->name()); } void LibertyReader::makeTimingArcs(LibertyPort *to_port, - TimingGroup *timing) + TimingGroup *timing) { LibertyPort *related_out_port = nullptr; const char *related_out_port_name = timing->relatedOutputPortName(); @@ -2387,7 +2386,7 @@ LibertyReader::makeTimingArcs(LibertyPort *to_port, void TimingGroup::makeTimingModels(LibertyCell *cell, - LibertyReader *visitor) + LibertyReader *visitor) { switch (cell->libertyLibrary()->delayModelType()) { case DelayModelType::cmos_linear: @@ -2417,18 +2416,18 @@ TimingGroup::makeLinearModels(LibertyCell *cell) TimingModel *model = nullptr; if (timingTypeIsCheck(attrs_->timingType())) { if (intr_exists) - model = new CheckLinearModel(cell, intr); + model = new CheckLinearModel(cell, intr); } else { float res = resistance_[rf_index]; bool res_exists = resistance_exists_[rf_index]; if (!res_exists) - library->defaultPinResistance(rf, PortDirection::output(), - res, res_exists); + library->defaultPinResistance(rf, PortDirection::output(), + res, res_exists); if (!res_exists) - res = 0.0F; + res = 0.0F; if (intr_exists) - model = new GateLinearModel(cell, intr, res); + model = new GateLinearModel(cell, intr, res); } attrs_->setModel(rf, model); } @@ -2451,22 +2450,22 @@ TimingGroup::makeTableModels(LibertyCell *cell, output_waveforms_[rf_index])); TimingType timing_type = attrs_->timingType(); if (timing_type == TimingType::clear - || timing_type == TimingType::combinational - || timing_type == TimingType::combinational_fall - || timing_type == TimingType::combinational_rise - || timing_type == TimingType::falling_edge - || timing_type == TimingType::preset - || timing_type == TimingType::rising_edge - || timing_type == TimingType::three_state_disable - || timing_type == TimingType::three_state_disable_rise - || timing_type == TimingType::three_state_disable_fall - || timing_type == TimingType::three_state_enable - || timing_type == TimingType::three_state_enable_fall - || timing_type == TimingType::three_state_enable_rise) { - if (transition == nullptr) - reader->libWarn(1210, line_, "missing %s_transition.", rf->name()); - if (delay == nullptr) - reader->libWarn(1211, line_, "missing cell_%s.", rf->name()); + || timing_type == TimingType::combinational + || timing_type == TimingType::combinational_fall + || timing_type == TimingType::combinational_rise + || timing_type == TimingType::falling_edge + || timing_type == TimingType::preset + || timing_type == TimingType::rising_edge + || timing_type == TimingType::three_state_disable + || timing_type == TimingType::three_state_disable_rise + || timing_type == TimingType::three_state_disable_fall + || timing_type == TimingType::three_state_enable + || timing_type == TimingType::three_state_enable_fall + || timing_type == TimingType::three_state_enable_rise) { + if (transition == nullptr) + reader->libWarn(1210, line_, "missing %s_transition.", rf->name()); + if (delay == nullptr) + reader->libWarn(1211, line_, "missing cell_%s.", rf->name()); } } else if (constraint) @@ -2477,10 +2476,10 @@ TimingGroup::makeTableModels(LibertyCell *cell, void LibertyReader::makeTimingArcs(const char *from_port_name, - PortNameBitIterator &from_port_iter, - LibertyPort *to_port, - LibertyPort *related_out_port, - TimingGroup *timing) + PortNameBitIterator &from_port_iter, + LibertyPort *to_port, + LibertyPort *related_out_port, + TimingGroup *timing) { if (from_port_iter.size() == 1 && !to_port->hasMembers()) { // one -> one @@ -2510,8 +2509,8 @@ LibertyReader::makeTimingArcs(const char *from_port_name, libWarn(1214, timing->line(), "timing group from output port."); LibertyPortMemberIterator bit_iter(to_port); while (bit_iter.hasNext()) { - LibertyPort *to_port_bit = bit_iter.next(); - builder_.makeTimingArcs(cell_, from_port, to_port_bit, related_out_port, + LibertyPort *to_port_bit = bit_iter.next(); + builder_.makeTimingArcs(cell_, from_port, to_port_bit, related_out_port, timing->attrs(), timing->line()); } } @@ -2524,42 +2523,42 @@ LibertyReader::makeTimingArcs(const char *from_port_name, LibertyPortMemberIterator to_port_iter(to_port); // warn about different sizes if (from_size != to_size) - libWarn(1216, timing->line(), - "timing port %s and related port %s are different sizes.", - from_port_name, - to_port->name()); + libWarn(1216, timing->line(), + "timing port %s and related port %s are different sizes.", + from_port_name, + to_port->name()); // align to/from iterators for one-to-one mapping while (from_size > to_size) { - from_size--; - from_port_iter.next(); + from_size--; + from_port_iter.next(); } while (to_size > from_size) { - to_size--; - to_port_iter.next(); + to_size--; + to_port_iter.next(); } // make timing arcs while (from_port_iter.hasNext() && to_port_iter.hasNext()) { - LibertyPort *from_port_bit = from_port_iter.next(); - LibertyPort *to_port_bit = to_port_iter.next(); - if (from_port_bit->direction()->isOutput()) - libWarn(1215, timing->line(), "timing group from output port."); - builder_.makeTimingArcs(cell_, from_port_bit, to_port_bit, - related_out_port, timing->attrs(), - timing->line()); + LibertyPort *from_port_bit = from_port_iter.next(); + LibertyPort *to_port_bit = to_port_iter.next(); + if (from_port_bit->direction()->isOutput()) + libWarn(1215, timing->line(), "timing group from output port."); + builder_.makeTimingArcs(cell_, from_port_bit, to_port_bit, + related_out_port, timing->attrs(), + timing->line()); } } else { while (from_port_iter.hasNext()) { - LibertyPort *from_port_bit = from_port_iter.next(); + LibertyPort *from_port_bit = from_port_iter.next(); if (from_port_bit->direction()->isOutput()) libWarn(1217, timing->line(), "timing group from output port."); - LibertyPortMemberIterator to_iter(to_port); - while (to_iter.hasNext()) { - LibertyPort *to_port_bit = to_iter.next(); - builder_.makeTimingArcs(cell_, from_port_bit, to_port_bit, + LibertyPortMemberIterator to_iter(to_port); + while (to_iter.hasNext()) { + LibertyPort *to_port_bit = to_iter.next(); + builder_.makeTimingArcs(cell_, from_port_bit, to_port_bit, related_out_port, timing->attrs(), timing->line()); - } + } } } } @@ -2568,7 +2567,7 @@ LibertyReader::makeTimingArcs(const char *from_port_name, void LibertyReader::makeTimingArcs(LibertyPort *to_port, LibertyPort *related_out_port, - TimingGroup *timing) + TimingGroup *timing) { if (to_port->hasMembers()) { LibertyPortMemberIterator bit_iter(to_port); @@ -2707,17 +2706,17 @@ void LibertyReader::endOutputCurrentRiseFall(LibertyGroup *group) { if (timing_) { - Set slew_set, cap_set; + std::set slew_set, cap_set; FloatSeq *slew_values = new FloatSeq; FloatSeq *cap_values = new FloatSeq; for (OutputWaveform *waveform : output_currents_) { float slew = waveform->slew(); - if (!slew_set.hasKey(slew)) { + if (!slew_set.contains(slew)) { slew_set.insert(slew); slew_values->push_back(slew); } float cap = waveform->cap(); - if (!cap_set.hasKey(cap)) { + if (!cap_set.contains(cap)) { cap_set.insert(cap); cap_values->push_back(cap); } @@ -2750,7 +2749,7 @@ LibertyReader::endOutputCurrentRiseFall(LibertyGroup *group) current_waveforms, ref_time_tbl); timing_->setOutputWaveforms(rf_, output_current); - output_currents_.deleteContentsClear(); + deleteContents(output_currents_); } } @@ -2878,7 +2877,7 @@ LibertyReader::visitDriverWaveformRiseFall(LibertyAttr *attr, void LibertyReader::makeInternalPowers(LibertyPort *port, - InternalPowerGroup *power_group) + InternalPowerGroup *power_group) { int line = power_group->line(); StringSeq *related_port_names = power_group->relatedPortNames(); @@ -2886,9 +2885,9 @@ LibertyReader::makeInternalPowers(LibertyPort *port, for (const char *related_port_name : *related_port_names) { PortNameBitIterator related_port_iter(cell_, related_port_name, this, line); if (related_port_iter.hasNext()) { - debugPrint(debug_, "liberty", 2, " power %s -> %s", + debugPrint(debug_, "liberty", 2, " power %s -> %s", related_port_name, port->name()); - makeInternalPowers(port, related_port_name, related_port_iter, power_group); + makeInternalPowers(port, related_port_name, related_port_iter, power_group); } } } @@ -2896,8 +2895,8 @@ LibertyReader::makeInternalPowers(LibertyPort *port, if (port->hasMembers()) { LibertyPortMemberIterator bit_iter(port); while (bit_iter.hasNext()) { - LibertyPort *port_bit = bit_iter.next(); - builder_.makeInternalPower(cell_, port_bit, nullptr, power_group); + LibertyPort *port_bit = bit_iter.next(); + builder_.makeInternalPower(cell_, port_bit, nullptr, power_group); } } else @@ -2907,9 +2906,9 @@ LibertyReader::makeInternalPowers(LibertyPort *port, void LibertyReader::makeInternalPowers(LibertyPort *port, - const char *related_port_name, - PortNameBitIterator &related_port_iter, - InternalPowerGroup *power_group) + const char *related_port_name, + PortNameBitIterator &related_port_iter, + InternalPowerGroup *power_group) { if (related_port_iter.size() == 1 && !port->hasMembers()) { // one -> one @@ -2931,8 +2930,8 @@ LibertyReader::makeInternalPowers(LibertyPort *port, LibertyPort *related_port = related_port_iter.next(); LibertyPortMemberIterator bit_iter(port); while (bit_iter.hasNext()) { - LibertyPort *port_bit = bit_iter.next(); - builder_.makeInternalPower(cell_, port_bit, related_port, power_group); + LibertyPort *port_bit = bit_iter.next(); + builder_.makeInternalPower(cell_, port_bit, related_port, power_group); } } } @@ -2940,27 +2939,27 @@ LibertyReader::makeInternalPowers(LibertyPort *port, // bus -> bus if (power_group->isOneToOne()) { if (static_cast(related_port_iter.size()) == port->size()) { - LibertyPortMemberIterator to_iter(port); - while (related_port_iter.hasNext() && to_iter.hasNext()) { - LibertyPort *related_port_bit = related_port_iter.next(); - LibertyPort *port_bit = to_iter.next(); - builder_.makeInternalPower(cell_, port_bit, related_port_bit, power_group); - } + LibertyPortMemberIterator to_iter(port); + while (related_port_iter.hasNext() && to_iter.hasNext()) { + LibertyPort *related_port_bit = related_port_iter.next(); + LibertyPort *port_bit = to_iter.next(); + builder_.makeInternalPower(cell_, port_bit, related_port_bit, power_group); + } } else - libWarn(1227, power_group->line(), - "internal_power port %s and related port %s are different sizes.", - related_port_name, - port->name()); + libWarn(1227, power_group->line(), + "internal_power port %s and related port %s are different sizes.", + related_port_name, + port->name()); } else { while (related_port_iter.hasNext()) { - LibertyPort *related_port_bit = related_port_iter.next(); - LibertyPortMemberIterator to_iter(port); - while (to_iter.hasNext()) { - LibertyPort *port_bit = to_iter.next(); - builder_.makeInternalPower(cell_, port_bit, related_port_bit, power_group); - } + LibertyPort *related_port_bit = related_port_iter.next(); + LibertyPortMemberIterator to_iter(port); + while (to_iter.hasNext()) { + LibertyPort *port_bit = to_iter.next(); + builder_.makeInternalPower(cell_, port_bit, related_port_bit, power_group); + } } } } @@ -3136,11 +3135,11 @@ LibertyReader::visitClockGatingIntegratedCell(LibertyAttr *attr) const char *clock_gate_type = getAttrString(attr); if (clock_gate_type) { if (stringBeginEqual(clock_gate_type, "latch_posedge")) - cell_->setClockGateType(ClockGateType::latch_posedge); + cell_->setClockGateType(ClockGateType::latch_posedge); else if (stringBeginEqual(clock_gate_type, "latch_negedge")) - cell_->setClockGateType(ClockGateType::latch_negedge); + cell_->setClockGateType(ClockGateType::latch_negedge); else - cell_->setClockGateType(ClockGateType::other); + cell_->setClockGateType(ClockGateType::other); } } } @@ -3176,17 +3175,17 @@ LibertyReader::beginPin(LibertyGroup *group) saved_port_group_ = port_group_; ports_ = new LibertyPortSeq; for (LibertyAttrValue *param : *group->params()) { - if (param->isString()) { - const char *port_name = param->stringValue(); - debugPrint(debug_, "liberty", 1, " port %s", port_name); - PortNameBitIterator port_iter(cell_, port_name, this, group->line()); - while (port_iter.hasNext()) { - LibertyPort *port = port_iter.next(); - ports_->push_back(port); - } - } - else - libWarn(1231, group, "pin name is not a string."); + if (param->isString()) { + const char *port_name = param->stringValue(); + debugPrint(debug_, "liberty", 1, " port %s", port_name); + PortNameBitIterator port_iter(cell_, port_name, this, group->line()); + while (port_iter.hasNext()) { + LibertyPort *port = port_iter.next(); + ports_->push_back(port); + } + } + else + libWarn(1231, group, "pin name is not a string."); } } else if (in_bundle_) { @@ -3194,30 +3193,30 @@ LibertyReader::beginPin(LibertyGroup *group) saved_port_group_ = port_group_; ports_ = new LibertyPortSeq; for (LibertyAttrValue *param : *group->params()) { - if (param->isString()) { - const char *name = param->stringValue(); - debugPrint(debug_, "liberty", 1, " port %s", name); - LibertyPort *port = findPort(name); - if (port == nullptr) - port = makePort(cell_, name); - ports_->push_back(port); - } - else - libWarn(1232, group, "pin name is not a string."); + if (param->isString()) { + const char *name = param->stringValue(); + debugPrint(debug_, "liberty", 1, " port %s", name); + LibertyPort *port = findPort(name); + if (port == nullptr) + port = makePort(cell_, name); + ports_->push_back(port); + } + else + libWarn(1232, group, "pin name is not a string."); } } else { ports_ = new LibertyPortSeq; // Multiple port names can share group def. for (LibertyAttrValue *param : *group->params()) { - if (param->isString()) { - const char *name = param->stringValue(); - debugPrint(debug_, "liberty", 1, " port %s", name); - LibertyPort *port = makePort(cell_, name); - ports_->push_back(port); - } - else - libWarn(1233, group, "pin name is not a string."); + if (param->isString()) { + const char *name = param->stringValue(); + debugPrint(debug_, "liberty", 1, " port %s", name); + LibertyPort *port = makePort(cell_, name); + ports_->push_back(port); + } + else + libWarn(1233, group, "pin name is not a string."); } } port_group_ = new PortGroup(ports_, group->line()); @@ -3289,7 +3288,7 @@ LibertyReader::setPortCapDefault(LibertyPort *port) bool exists; port->capacitance(tr, min_max, cap, exists); if (!exists) - port->setCapacitance(tr, min_max, defaultCap(port)); + port->setCapacitance(tr, min_max, defaultCap(port)); } } } @@ -3322,7 +3321,7 @@ LibertyReader::beginBusOrBundle(LibertyGroup *group) if (param->isString()) { const char *name = param->stringValue(); if (name) - bus_names_.push_back(stringCopy(name)); + bus_names_.push_back(stringCopy(name)); } } ports_ = new LibertyPortSeq; @@ -3350,17 +3349,17 @@ LibertyReader::visitBusType(LibertyAttr *attr) // Look for bus dcl local to cell first. BusDcl *bus_dcl = cell_->findBusDcl(bus_type); if (bus_dcl == nullptr) - bus_dcl = library_->findBusDcl(bus_type); + bus_dcl = library_->findBusDcl(bus_type); if (bus_dcl) { for (const char *name : bus_names_) { - debugPrint(debug_, "liberty", 1, " bus %s", name); - LibertyPort *port = makeBusPort(cell_, name, bus_dcl->from(), + debugPrint(debug_, "liberty", 1, " bus %s", name); + LibertyPort *port = makeBusPort(cell_, name, bus_dcl->from(), bus_dcl->to(), bus_dcl); - ports_->push_back(port); - } + ports_->push_back(port); + } } else - libWarn(1235, attr, "bus_type %s not found.", bus_type); + libWarn(1235, attr, "bus_type %s not found.", bus_type); } else libWarn(1236, attr, "bus_type is not a string."); @@ -3393,21 +3392,21 @@ LibertyReader::visitMembers(LibertyAttr *attr) if (cell_) { if (attr->isComplex()) { for (const char *name : bus_names_) { - debugPrint(debug_, "liberty", 1, " bundle %s", name); - ConcretePortSeq *members = new ConcretePortSeq; + debugPrint(debug_, "liberty", 1, " bundle %s", name); + ConcretePortSeq *members = new ConcretePortSeq; for (LibertyAttrValue *value : *attr->values()) { - if (value->isString()) { - const char *port_name = value->stringValue(); - LibertyPort *port = findPort(port_name); - if (port == nullptr) - port = makePort(cell_, port_name); - members->push_back(port); - } - else - libWarn(1238, attr, "member is not a string."); - } - LibertyPort *port = builder_.makeBundlePort(cell_, name, members); - ports_->push_back(port); + if (value->isString()) { + const char *port_name = value->stringValue(); + LibertyPort *port = findPort(port_name); + if (port == nullptr) + port = makePort(cell_, port_name); + members->push_back(port); + } + else + libWarn(1238, attr, "member is not a string."); + } + LibertyPort *port = builder_.makeBundlePort(cell_, name, members); + ports_->push_back(port); } } else @@ -3441,7 +3440,7 @@ libertyReaderFindPort(LibertyCell *cell, LibertyPort * LibertyReader::findPort(LibertyCell *cell, - const char *port_name) + const char *port_name) { return libertyReaderFindPort(cell, port_name); } @@ -3454,21 +3453,21 @@ LibertyReader::visitDirection(LibertyAttr *attr) if (dir) { PortDirection *port_dir = PortDirection::unknown(); if (stringEq(dir, "input")) - port_dir = PortDirection::input(); + port_dir = PortDirection::input(); else if (stringEq(dir, "output")) - port_dir = PortDirection::output(); + port_dir = PortDirection::output(); else if (stringEq(dir, "inout")) - port_dir = PortDirection::bidirect(); + port_dir = PortDirection::bidirect(); else if (stringEq(dir, "internal")) - port_dir = PortDirection::internal(); + port_dir = PortDirection::internal(); else - libWarn(1240, attr, "unknown port direction."); + libWarn(1240, attr, "unknown port direction."); for (LibertyPort *port : *ports_) { - // Tristate enable function sets direction to tristate; don't - // clobber it. - if (!port->direction()->isTristate()) - port->setDirection(port_dir); + // Tristate enable function sets direction to tristate; don't + // clobber it. + if (!port->direction()->isTristate()) + port->setDirection(port_dir); } } } @@ -3495,7 +3494,7 @@ LibertyReader::visitThreeState(LibertyAttr *attr) const char *three_state = getAttrString(attr); if (three_state) { for (LibertyPort *port : *ports_) - makeLibertyFunc(three_state, + makeLibertyFunc(three_state, [port] (FuncExpr *expr) { port->setTristateEnable(expr); }, true, "three_state", attr); } @@ -3523,7 +3522,7 @@ LibertyReader::visitClock(LibertyAttr *attr) getAttrBool(attr, is_clk, exists); if (exists) { for (LibertyPort *port : *ports_) - port->setIsClock(is_clk); + port->setIsClock(is_clk); } } } @@ -3551,7 +3550,7 @@ LibertyReader::visitCapacitance(LibertyAttr *attr) if (exists) { cap *= cap_scale_; for (LibertyPort *port : *ports_) - port->setCapacitance(cap); + port->setCapacitance(cap); } } if (wireload_) { @@ -3573,8 +3572,8 @@ LibertyReader::visitRiseCap(LibertyAttr *attr) if (exists) { cap *= cap_scale_; for (LibertyPort *port : *ports_) { - port->setCapacitance(RiseFall::rise(), MinMax::min(), cap); - port->setCapacitance(RiseFall::rise(), MinMax::max(), cap); + port->setCapacitance(RiseFall::rise(), MinMax::min(), cap); + port->setCapacitance(RiseFall::rise(), MinMax::max(), cap); } } } @@ -3590,8 +3589,8 @@ LibertyReader::visitFallCap(LibertyAttr *attr) if (exists) { cap *= cap_scale_; for (LibertyPort *port : *ports_) { - port->setCapacitance(RiseFall::fall(), MinMax::min(), cap); - port->setCapacitance(RiseFall::fall(), MinMax::max(), cap); + port->setCapacitance(RiseFall::fall(), MinMax::min(), cap); + port->setCapacitance(RiseFall::fall(), MinMax::max(), cap); } } } @@ -3608,8 +3607,8 @@ LibertyReader::visitRiseCapRange(LibertyAttr *attr) min *= cap_scale_; max *= cap_scale_; for (LibertyPort *port : *ports_) { - port->setCapacitance(RiseFall::rise(), MinMax::min(), min); - port->setCapacitance(RiseFall::rise(), MinMax::max(), max); + port->setCapacitance(RiseFall::rise(), MinMax::min(), min); + port->setCapacitance(RiseFall::rise(), MinMax::max(), max); } } } @@ -3626,8 +3625,8 @@ LibertyReader::visitFallCapRange(LibertyAttr *attr) min *= cap_scale_; max *= cap_scale_; for (LibertyPort *port : *ports_) { - port->setCapacitance(RiseFall::fall(), MinMax::min(), min); - port->setCapacitance(RiseFall::fall(), MinMax::max(), max); + port->setCapacitance(RiseFall::fall(), MinMax::min(), min); + port->setCapacitance(RiseFall::fall(), MinMax::max(), max); } } } @@ -3641,7 +3640,7 @@ LibertyReader::defaultCap(LibertyPort *port) if (dir->isInput()) cap = library_->defaultInputPinCap(); else if (dir->isOutput() - || dir->isTristate()) + || dir->isTristate()) cap = library_->defaultOutputPinCap(); else if (dir->isBidirect()) cap = library_->defaultBidirectPinCap(); @@ -3657,8 +3656,8 @@ LibertyReader::visitFanoutLoad(LibertyAttr *attr) getAttrFloat(attr, fanout, exists); if (exists) { visitPorts([&] (LibertyPort *port) { - port->setFanoutLoad(fanout); - }); + port->setFanoutLoad(fanout); + }); } } } @@ -3677,7 +3676,7 @@ LibertyReader::visitMinFanout(LibertyAttr *attr) void LibertyReader::visitFanout(LibertyAttr *attr, - const MinMax *min_max) + const MinMax *min_max) { if (ports_) { float fanout; @@ -3685,8 +3684,8 @@ LibertyReader::visitFanout(LibertyAttr *attr, getAttrFloat(attr, fanout, exists); if (exists) { visitPorts([&] (LibertyPort *port) { - port->setFanoutLimit(fanout, min_max); - }); + port->setFanoutLimit(fanout, min_max); + }); } } } @@ -3713,11 +3712,11 @@ LibertyReader::visitMinMaxTransition(LibertyAttr *attr, getAttrFloat(attr, value, exists); if (exists) { if (min_max == MinMax::max() && value == 0.0) - libWarn(1241, attr, "max_transition is 0.0."); + libWarn(1241, attr, "max_transition is 0.0."); value *= time_scale_; visitPorts([&] (LibertyPort *port) { - port->setSlewLimit(value, min_max); - }); + port->setSlewLimit(value, min_max); + }); } } } @@ -3736,7 +3735,7 @@ LibertyReader::visitMinCapacitance(LibertyAttr *attr) void LibertyReader::visitMinMaxCapacitance(LibertyAttr *attr, - const MinMax *min_max) + const MinMax *min_max) { if (cell_) { float value; @@ -3744,10 +3743,9 @@ LibertyReader::visitMinMaxCapacitance(LibertyAttr *attr, getAttrFloat(attr, value, exists); if (exists) { value *= cap_scale_; - LibertyPortSeq::Iterator port_iter(ports_); visitPorts([&] (LibertyPort *port) { - port->setCapacitanceLimit(value, min_max); - }); + port->setCapacitanceLimit(value, min_max); + }); } } } @@ -3761,7 +3759,7 @@ LibertyReader::visitMinPeriod(LibertyAttr *attr) getAttrFloat(attr, value, exists); if (exists) { for (LibertyPort *port : *ports_) - port->setMinPeriod(value * time_scale_); + port->setMinPeriod(value * time_scale_); } } } @@ -3780,7 +3778,7 @@ LibertyReader::visitMinPulseWidthHigh(LibertyAttr *attr) void LibertyReader::visitMinPulseWidth(LibertyAttr *attr, - const RiseFall *rf) + const RiseFall *rf) { if (cell_) { float value; @@ -3789,7 +3787,7 @@ LibertyReader::visitMinPulseWidth(LibertyAttr *attr, if (exists) { value *= time_scale_; for (LibertyPort *port : *ports_) - port->setMinPulseWidth(rf, value); + port->setMinPulseWidth(rf, value); } } } @@ -3803,26 +3801,26 @@ LibertyReader::visitPulseClock(LibertyAttr *attr) const RiseFall *trigger = nullptr; const RiseFall *sense = nullptr; if (stringEq(pulse_clk, "rise_triggered_high_pulse")) { - trigger = RiseFall::rise(); - sense = RiseFall::rise(); + trigger = RiseFall::rise(); + sense = RiseFall::rise(); } else if (stringEq(pulse_clk, "rise_triggered_low_pulse")) { - trigger = RiseFall::rise(); - sense = RiseFall::fall(); + trigger = RiseFall::rise(); + sense = RiseFall::fall(); } else if (stringEq(pulse_clk, "fall_triggered_high_pulse")) { - trigger = RiseFall::fall(); - sense = RiseFall::rise(); + trigger = RiseFall::fall(); + sense = RiseFall::rise(); } else if (stringEq(pulse_clk, "fall_triggered_low_pulse")) { - trigger = RiseFall::fall(); - sense = RiseFall::fall(); + trigger = RiseFall::fall(); + sense = RiseFall::fall(); } else - libWarn(1242,attr, "pulse_latch unknown pulse type."); + libWarn(1242,attr, "pulse_latch unknown pulse type."); if (trigger) { for (LibertyPort *port : *ports_) - port->setPulseClk(trigger, sense); + port->setPulseClk(trigger, sense); } } } @@ -3920,7 +3918,7 @@ LibertyReader::visitPortBoolAttr(LibertyAttr *attr, getAttrBool(attr, value, exists); if (exists) { for (LibertyPort *port : *ports_) - (port->*setter)(value); + (port->*setter)(value); } } } @@ -3992,8 +3990,8 @@ LibertyReader::endLatchBank(LibertyGroup *) void LibertyReader::beginSequential(LibertyGroup *group, - bool is_register, - bool is_bank) + bool is_register, + bool is_bank) { if (cell_) { // Define ff/latch state variables as internal ports. @@ -4005,31 +4003,31 @@ LibertyReader::beginSequential(LibertyGroup *group, LibertyPort *out_port_inv = nullptr; if (out_name) { if (has_size) - out_port = makeBusPort(cell_, out_name, size - 1, 0, nullptr); + out_port = makeBusPort(cell_, out_name, size - 1, 0, nullptr); else - out_port = makePort(cell_, out_name); + out_port = makePort(cell_, out_name); out_port->setDirection(PortDirection::internal()); } if (out_inv_name) { if (has_size) - out_port_inv = makeBusPort(cell_, out_inv_name, size - 1, 0, nullptr); + out_port_inv = makeBusPort(cell_, out_inv_name, size - 1, 0, nullptr); else - out_port_inv = makePort(cell_, out_inv_name); + out_port_inv = makePort(cell_, out_inv_name); out_port_inv->setDirection(PortDirection::internal()); } sequential_ = new SequentialGroup(is_register, is_bank, - out_port, out_port_inv, size, - group->line()); + out_port, out_port_inv, size, + group->line()); cell_sequentials_.push_back(sequential_); } } void LibertyReader::seqPortNames(LibertyGroup *group, - const char *&out_name, - const char *&out_inv_name, - bool &has_size, - int &size) + const char *&out_name, + const char *&out_inv_name, + bool &has_size, + int &size) { out_name = nullptr; out_inv_name = nullptr; @@ -4262,14 +4260,14 @@ LibertyReader::endTiming(LibertyGroup *group) for (auto rf : RiseFall::range()) { TableModel *model = timing_->constraint(rf); if (model) { - ScaleFactorType type=timingTypeScaleFactorType(timing_->attrs()->timingType()); - model->setScaleFactorType(type); + ScaleFactorType type=timingTypeScaleFactorType(timing_->attrs()->timingType()); + model->setScaleFactorType(type); } } TimingType timing_type = timing_->attrs()->timingType(); if (timing_->relatedPortNames() == nullptr && !(timing_type == TimingType::min_pulse_width - || timing_type == TimingType::minimum_period + || timing_type == TimingType::minimum_period || timing_type == TimingType::min_clock_tree_path || timing_type == TimingType::max_clock_tree_path)) libWarn(1243, group, "timing group missing related_pin/related_bus_pin."); @@ -4289,7 +4287,7 @@ LibertyReader::visitRelatedPin(LibertyAttr *attr) void LibertyReader::visitRelatedPin(LibertyAttr *attr, - RelatedPortGroup *group) + RelatedPortGroup *group) { const char *port_names = getAttrString(attr); if (port_names) { @@ -4344,7 +4342,7 @@ LibertyReader::visitRelatedBusPins(LibertyAttr *attr) void LibertyReader::visitRelatedBusPins(LibertyAttr *attr, - RelatedPortGroup *group) + RelatedPortGroup *group) { const char *port_names = getAttrString(attr); if (port_names) { @@ -4371,9 +4369,9 @@ LibertyReader::visitTimingType(LibertyAttr *attr) if (type_name) { TimingType type = findTimingType(type_name); if (type == TimingType::unknown) - libWarn(1244, attr, "unknown timing_type %s.", type_name); + libWarn(1244, attr, "unknown timing_type %s.", type_name); else - timing_->attrs()->setTimingType(type); + timing_->attrs()->setTimingType(type); } } } @@ -4385,13 +4383,13 @@ LibertyReader::visitTimingSense(LibertyAttr *attr) const char *sense_name = getAttrString(attr); if (sense_name) { if (stringEq(sense_name, "non_unate")) - timing_->attrs()->setTimingSense(TimingSense::non_unate); + timing_->attrs()->setTimingSense(TimingSense::non_unate); else if (stringEq(sense_name, "positive_unate")) - timing_->attrs()->setTimingSense(TimingSense::positive_unate); + timing_->attrs()->setTimingSense(TimingSense::positive_unate); else if (stringEq(sense_name, "negative_unate")) - timing_->attrs()->setTimingSense(TimingSense::negative_unate); + timing_->attrs()->setTimingSense(TimingSense::negative_unate); else - libWarn(1245, attr, "unknown timing_sense %s.", sense_name); + libWarn(1245, attr, "unknown timing_sense %s.", sense_name); } } } @@ -4421,26 +4419,22 @@ LibertyReader::visitMode(LibertyAttr *attr) { if (timing_) { if (attr->isComplex()) { - LibertyAttrValueIterator value_iter(attr->values()); - if (value_iter.hasNext()) { - LibertyAttrValue *value = value_iter.next(); - if (value->isString()) { - timing_->attrs()->setModeName(value->stringValue()); - if (value_iter.hasNext()) { - value = value_iter.next(); - if (value->isString()) - timing_->attrs()->setModeValue(value->stringValue()); - else - libWarn(1246, attr, "mode value is not a string."); - } - else - libWarn(1247, attr, "missing mode value."); - } - else - libWarn(1248, attr, "mode name is not a string."); + LibertyAttrValueSeq *values = attr->values(); + if (values->size() == 2) { + LibertyAttrValue *value = (*values)[0]; + if (value->isString()) + timing_->attrs()->setModeName(value->stringValue()); + else + libWarn(1248, attr, "mode name is not a string."); + + value = (*values)[1]; + if (value->isString()) + timing_->attrs()->setModeValue(value->stringValue()); + else + libWarn(1246, attr, "mode value is not a string."); } else - libWarn(1249, attr, "mode missing values."); + libWarn(1249, attr, "mode requirees 2 values."); } else libWarn(1250, attr, "mode missing mode name and value."); @@ -4461,7 +4455,7 @@ LibertyReader::visitIntrinsicFall(LibertyAttr *attr) void LibertyReader::visitIntrinsic(LibertyAttr *attr, - const RiseFall *rf) + const RiseFall *rf) { if (timing_) { float value; @@ -4486,7 +4480,7 @@ LibertyReader::visitFallResistance(LibertyAttr *attr) void LibertyReader::visitRiseFallResistance(LibertyAttr *attr, - const RiseFall *rf) + const RiseFall *rf) { if (timing_) { float value; @@ -4587,8 +4581,8 @@ LibertyReader::beginRiseTransitionDegredation(LibertyGroup *group) { if (library_) beginTableModel(group, TableTemplateType::delay, - RiseFall::rise(), time_scale_, - ScaleFactorType::transition); + RiseFall::rise(), time_scale_, + ScaleFactorType::transition); } void @@ -4596,8 +4590,8 @@ LibertyReader::beginFallTransitionDegredation(LibertyGroup *group) { if (library_) beginTableModel(group, TableTemplateType::delay, - RiseFall::fall(), time_scale_, - ScaleFactorType::transition); + RiseFall::fall(), time_scale_, + ScaleFactorType::transition); } void @@ -4619,22 +4613,22 @@ LibertyReader::endRiseFallTransitionDegredation(LibertyGroup *group) void LibertyReader::beginTimingTableModel(LibertyGroup *group, - const RiseFall *rf, - ScaleFactorType scale_factor_type) + const RiseFall *rf, + ScaleFactorType scale_factor_type) { if (timing_) beginTableModel(group, TableTemplateType::delay, rf, - time_scale_, scale_factor_type); + time_scale_, scale_factor_type); else libWarn(1255, group, "%s group not in timing group.", group->firstName()); } void LibertyReader::beginTableModel(LibertyGroup *group, - TableTemplateType type, - const RiseFall *rf, - float scale, - ScaleFactorType scale_factor_type) + TableTemplateType type, + const RiseFall *rf, + float scale, + ScaleFactorType scale_factor_type) { beginTable(group, type, scale); rf_ = rf; @@ -4653,8 +4647,8 @@ LibertyReader::endTableModel() void LibertyReader::beginTable(LibertyGroup *group, - TableTemplateType type, - float scale) + TableTemplateType type, + float scale) { const char *template_name = group->firstName(); if (library_ && template_name) { @@ -4720,8 +4714,8 @@ LibertyReader::makeTable(LibertyAttr *attr, // Column index1*size(index2) + index2 // Row index3 FloatTable *table = makeFloatTable(attr, - axis_[0]->size()*axis_[1]->size(), - axis_[2]->size(), scale); + axis_[0]->size()*axis_[1]->size(), + axis_[2]->size(), scale); table_ = make_shared(table, axis_[0], axis_[1], axis_[2]); } else if (axis_[0] && axis_[1]) { @@ -4729,7 +4723,7 @@ LibertyReader::makeTable(LibertyAttr *attr, // Row variable1/axis[0] // Column variable2/axis[1] FloatTable *table = makeFloatTable(attr, axis_[0]->size(), - axis_[1]->size(), scale); + axis_[1]->size(), scale); table_ = make_shared(table, axis_[0], axis_[1]); } else if (axis_[0]) { @@ -4754,9 +4748,9 @@ LibertyReader::makeTable(LibertyAttr *attr, FloatTable * LibertyReader::makeFloatTable(LibertyAttr *attr, - size_t rows, - size_t cols, - float scale) + size_t rows, + size_t cols, + float scale) { FloatTable *table = new FloatTable; table->reserve(rows); @@ -4775,24 +4769,24 @@ LibertyReader::makeFloatTable(LibertyAttr *attr, libWarn(1258, attr, "%s is not a list of floats.", attr->name()); if (row->size() != cols) { libWarn(1259, attr, "table row has %zu columns but axis has %zu.", - row->size(), - cols); + row->size(), + cols); // Fill out row columns with zeros. for (size_t c = row->size(); c < cols; c++) - row->push_back(0.0); + row->push_back(0.0); } } if (table->size() != rows) { libWarn(1260, attr, "table has %zu rows but axis has %zu.", - table->size(), - rows); + table->size(), + rows); // Fill with zero'd rows. for (size_t r = table->size(); r < rows; r++) { FloatSeq *row = new FloatSeq; table->push_back(row); // Fill out row with zeros. for (size_t c = row->size(); c < cols; c++) - row->push_back(0.0); + row->push_back(0.0); } } return table; @@ -4827,19 +4821,19 @@ LibertyReader::beginLut(LibertyGroup *group) if (cell_) { for (LibertyAttrValue *param : *group->params()) { if (param->isString()) { - const char *names = param->stringValue(); - // Parse space separated list of related port names. - TokenParser parser(names, " "); - while (parser.hasNext()) { - char *name = parser.next(); - if (name[0] != '\0') { - LibertyPort *port = makePort(cell_, name); - port->setDirection(PortDirection::internal()); - } - } + const char *names = param->stringValue(); + // Parse space separated list of related port names. + TokenParser parser(names, " "); + while (parser.hasNext()) { + char *name = parser.next(); + if (name[0] != '\0') { + LibertyPort *port = makePort(cell_, name); + port->setDirection(PortDirection::internal()); + } + } } else - libWarn(1261, group, "lut output is not a string."); + libWarn(1261, group, "lut output is not a string."); } } } @@ -5008,9 +5002,9 @@ LibertyReader::getAttrString(LibertyAttr *attr) void LibertyReader::getAttrInt(LibertyAttr *attr, - // Return values. - int &value, - bool &exists) + // Return values. + int &value, + bool &exists) { value = 0; exists = false; @@ -5030,9 +5024,9 @@ LibertyReader::getAttrInt(LibertyAttr *attr, void LibertyReader::getAttrFloat(LibertyAttr *attr, - // Return values. - float &value, - bool &valid) + // Return values. + float &value, + bool &valid) { valid = false; if (attr->isSimple()) @@ -5043,10 +5037,10 @@ LibertyReader::getAttrFloat(LibertyAttr *attr, void LibertyReader::getAttrFloat(LibertyAttr *attr, - LibertyAttrValue *attr_value, - // Return values. - float &value, - bool &valid) + LibertyAttrValue *attr_value, + // Return values. + float &value, + bool &valid) { if (attr_value->isFloat()) { valid = true; @@ -5064,9 +5058,9 @@ LibertyReader::getAttrFloat(LibertyAttr *attr, if ((*end && !isspace(*end)) // strtof support INF as a valid float. || stringEqual(string, "inf")) - libWarn(1271, attr, "%s value %s is not a float.", - attr->name(), - string); + libWarn(1271, attr, "%s value %s is not a float.", + attr->name(), + string); valid = true; } } @@ -5076,31 +5070,30 @@ LibertyReader::getAttrFloat(LibertyAttr *attr, // attr(float1, float2); void LibertyReader::getAttrFloat2(LibertyAttr *attr, - // Return values. - float &value1, - float &value2, - bool &exists) + // Return values. + float &value1, + float &value2, + bool &exists) { exists = false; if (attr->isComplex()) { - LibertyAttrValueIterator value_iter(attr->values()); - if (value_iter.hasNext()) { - LibertyAttrValue *value = value_iter.next(); + LibertyAttrValueSeq *values = attr->values(); + if (values->size() == 2) { + LibertyAttrValue *value = (*values)[0]; getAttrFloat(attr, value, value1, exists); - if (exists) { - if (value_iter.hasNext()) { - value = value_iter.next(); - getAttrFloat(attr, value, value2, exists); - } - else - libWarn(1272, attr, "%s missing values.", attr->name()); - } + if (!exists) + libWarn(1272, attr, "%s is not a float.", attr->name()); + + value = (*values)[1]; + getAttrFloat(attr, value, value2, exists); + if (!exists) + libWarn(1273, attr, "%s is not a float.", attr->name()); } else - libWarn(1273, attr, "%s missing values.", attr->name()); + libWarn(1274, attr, "%s requires 2 valules.", attr->name()); } else - libWarn(1274, attr, "%s is not a complex attribute.", attr->name()); + libWarn(1345, attr, "%s requires 2 valules.", attr->name()); } // Parse string of comma separated floats. @@ -5108,9 +5101,9 @@ LibertyReader::getAttrFloat2(LibertyAttr *attr, // consistent about including the delimiters. void LibertyReader::parseStringFloatList(const char *float_list, - float scale, - FloatSeq *values, - LibertyAttr *attr) + float scale, + FloatSeq *values, + LibertyAttr *attr) { const char *delimiters = ", "; TokenParser parser(float_list, delimiters); @@ -5122,10 +5115,10 @@ LibertyReader::parseStringFloatList(const char *float_list, char *end; float value = strtof(token, &end) * scale; if (end == token - || (end && !(*end == '\0' - || isspace(*end) - || strchr(delimiters, *end) != nullptr - || *end == '}'))) + || (end && !(*end == '\0' + || isspace(*end) + || strchr(delimiters, *end) != nullptr + || *end == '}'))) libWarn(1275, attr, "%s is not a float.", token); values->push_back(value); } @@ -5133,25 +5126,25 @@ LibertyReader::parseStringFloatList(const char *float_list, FloatSeq * LibertyReader::readFloatSeq(LibertyAttr *attr, - float scale) + float scale) { FloatSeq *values = nullptr; if (attr->isComplex()) { - LibertyAttrValueIterator value_iter(attr->values()); - if (value_iter.hasNext()) { - LibertyAttrValue *value = value_iter.next(); + LibertyAttrValueSeq *attr_values = attr->values(); + if (attr_values->size() == 1) { + LibertyAttrValue *value = (*attr_values)[0]; if (value->isString()) { - values = new FloatSeq; - parseStringFloatList(value->stringValue(), scale, values, attr); + values = new FloatSeq; + parseStringFloatList(value->stringValue(), scale, values, attr); } else if (value->isFloat()) { - values = new FloatSeq; + values = new FloatSeq; values->push_back(value->floatValue()); } else - libWarn(1276, attr, "%s is missing values.", attr->name()); + libWarn(1276, attr, "%s is missing values.", attr->name()); } - if (value_iter.hasNext()) + else libWarn(1277, attr, "%s has more than one string.", attr->name()); } else { @@ -5168,9 +5161,9 @@ LibertyReader::readFloatSeq(LibertyAttr *attr, void LibertyReader::getAttrBool(LibertyAttr *attr, - // Return values. - bool &value, - bool &exists) + // Return values. + bool &value, + bool &exists) { exists = false; if (attr->isSimple()) { @@ -5178,15 +5171,15 @@ LibertyReader::getAttrBool(LibertyAttr *attr, if (val->isString()) { const char *str = val->stringValue(); if (stringEqual(str, "true")) { - value = true; - exists = true; + value = true; + exists = true; } else if (stringEqual(str, "false")) { - value = false; - exists = true; + value = false; + exists = true; } else - libWarn(1279, attr, "%s attribute is not boolean.", attr->name()); + libWarn(1279, attr, "%s attribute is not boolean.", attr->name()); } else libWarn(1280, attr, "%s attribute is not boolean.", attr->name()); @@ -5209,7 +5202,7 @@ LibertyReader::getAttrLogicValue(LibertyAttr *attr) return LogicValue::unknown; else libWarn(1282, attr, "attribute %s value %s not recognized.", - attr->name(), str); + attr->name(), str); // fall thru } return LogicValue::unknown; @@ -5217,12 +5210,12 @@ LibertyReader::getAttrLogicValue(LibertyAttr *attr) FuncExpr * LibertyReader::parseFunc(const char *func, - const char *attr_name, - int line) + const char *attr_name, + int line) { string error_msg; stringPrint(error_msg, "%s, line %d %s", - filename_, + filename_, line, attr_name); return parseFuncExpr(func, cell_, error_msg.c_str(), report_); @@ -5255,7 +5248,7 @@ LibertyReader::visitVariable(LibertyVariable *var) string key; float value; bool exists; - var_map_->findKey(var_name, key, value, exists); + findKeyValue(var_map_, var_name, value, exists); if (exists) { // Duplicate variable name. (*var_map_)[key] = var->value(); @@ -5266,11 +5259,11 @@ LibertyReader::visitVariable(LibertyVariable *var) void LibertyReader::variableValue(const char *var, - float &value, - bool &exists) + float &value, + bool &exists) { if (var_map_) - var_map_->findKey(var, value, exists); + findKeyValue(var_map_, var, value, exists); else exists = false; } @@ -5280,8 +5273,8 @@ LibertyReader::variableValue(const char *var, void LibertyReader::libWarn(int id, LibertyStmt *stmt, - const char *fmt, - ...) + const char *fmt, + ...) { va_list args; va_start(args, fmt); @@ -5292,8 +5285,8 @@ LibertyReader::libWarn(int id, void LibertyReader::libWarn(int id, int line, - const char *fmt, - ...) + const char *fmt, + ...) { va_list args; va_start(args, fmt); @@ -5304,8 +5297,8 @@ LibertyReader::libWarn(int id, void LibertyReader::libError(int id, LibertyStmt *stmt, - const char *fmt, - ...) + const char *fmt, + ...) { va_list args; va_start(args, fmt); @@ -5362,8 +5355,8 @@ LibertyReader::beginFallPower(LibertyGroup *group) { if (internal_power_) beginTableModel(group, TableTemplateType::power, - RiseFall::fall(), energy_scale_, - ScaleFactorType::internal_power); + RiseFall::fall(), energy_scale_, + ScaleFactorType::internal_power); } void @@ -5371,8 +5364,8 @@ LibertyReader::beginRisePower(LibertyGroup *group) { if (internal_power_) beginTableModel(group, TableTemplateType::power, - RiseFall::rise(), energy_scale_, - ScaleFactorType::internal_power); + RiseFall::rise(), energy_scale_, + ScaleFactorType::internal_power); } void @@ -5505,12 +5498,12 @@ LibertyReader::endOcvDerateFactors(LibertyGroup *) if (ocv_derate_) { for (auto early_late : derate_type_->range()) { for (auto rf : rf_type_->range()) { - if (path_type_ == PathType::clk_and_data) { - ocv_derate_->setDerateTable(rf, early_late, PathType::clk, table_); - ocv_derate_->setDerateTable(rf, early_late, PathType::data, table_); - } - else - ocv_derate_->setDerateTable(rf, early_late, path_type_, table_); + if (path_type_ == PathType::clk_and_data) { + ocv_derate_->setDerateTable(rf, early_late, PathType::clk, table_); + ocv_derate_->setDerateTable(rf, early_late, PathType::data, table_); + } + else + ocv_derate_->setDerateTable(rf, early_late, path_type_, table_); } } } @@ -5573,11 +5566,11 @@ LibertyReader::endOcvSigmaCell(LibertyGroup *group) TableModel *table_model = new TableModel(table_, tbl_template_, scale_factor_type_, rf_); if (sigma_type_ == EarlyLateAll::all()) { - timing_->setDelaySigma(rf_, EarlyLate::min(), table_model); - timing_->setDelaySigma(rf_, EarlyLate::max(), table_model); + timing_->setDelaySigma(rf_, EarlyLate::min(), table_model); + timing_->setDelaySigma(rf_, EarlyLate::max(), table_model); } else - timing_->setDelaySigma(rf_, sigma_type_->asMinMax(), table_model); + timing_->setDelaySigma(rf_, sigma_type_->asMinMax(), table_model); } else libWarn(1288, group, "unsupported model axis."); @@ -5605,11 +5598,11 @@ LibertyReader::endOcvSigmaTransition(LibertyGroup *group) TableModel *table_model = new TableModel(table_, tbl_template_, scale_factor_type_, rf_); if (sigma_type_ == EarlyLateAll::all()) { - timing_->setSlewSigma(rf_, EarlyLate::min(), table_model); - timing_->setSlewSigma(rf_, EarlyLate::max(), table_model); + timing_->setSlewSigma(rf_, EarlyLate::min(), table_model); + timing_->setSlewSigma(rf_, EarlyLate::max(), table_model); } else - timing_->setSlewSigma(rf_, sigma_type_->asMinMax(), table_model); + timing_->setSlewSigma(rf_, sigma_type_->asMinMax(), table_model); } else libWarn(1289, group, "unsupported model axis."); @@ -5637,11 +5630,11 @@ LibertyReader::endOcvSigmaConstraint(LibertyGroup *group) TableModel *table_model = new TableModel(table_, tbl_template_, scale_factor_type_, rf_); if (sigma_type_ == EarlyLateAll::all()) { - timing_->setConstraintSigma(rf_, EarlyLate::min(), table_model); - timing_->setConstraintSigma(rf_, EarlyLate::max(), table_model); + timing_->setConstraintSigma(rf_, EarlyLate::min(), table_model); + timing_->setConstraintSigma(rf_, EarlyLate::max(), table_model); } else - timing_->setConstraintSigma(rf_, sigma_type_->asMinMax(), table_model); + timing_->setConstraintSigma(rf_, sigma_type_->asMinMax(), table_model); } else libWarn(1290, group, "unsupported model axis."); @@ -5750,9 +5743,9 @@ LibertyReader::endEcsmWaveform(LibertyGroup *) LibertyFunc::LibertyFunc(const char *expr, LibertySetFunc set_func, - bool invert, - const char *attr_name, - int line) : + bool invert, + const char *attr_name, + int line) : expr_(stringCopy(expr)), set_func_(set_func), invert_(invert), @@ -5770,7 +5763,7 @@ LibertyFunc::~LibertyFunc() //////////////////////////////////////////////////////////////// PortGroup::PortGroup(LibertyPortSeq *ports, - int line) : + int line) : ports_(ports), line_(line) { @@ -5778,7 +5771,7 @@ PortGroup::PortGroup(LibertyPortSeq *ports, PortGroup::~PortGroup() { - timings_.deleteContents(); + deleteContents(timings_); delete ports_; } @@ -5797,11 +5790,11 @@ PortGroup::addInternalPowerGroup(InternalPowerGroup *internal_power) //////////////////////////////////////////////////////////////// SequentialGroup::SequentialGroup(bool is_register, - bool is_bank, - LibertyPort *out_port, - LibertyPort *out_inv_port, - int size, - int line) : + bool is_bank, + LibertyPort *out_port, + LibertyPort *out_inv_port, + int size, + int line) : is_register_(is_register), is_bank_(is_bank), out_port_(out_port), @@ -5952,7 +5945,7 @@ TimingGroup::setRelatedOutputPortName(const char *name) void TimingGroup::setIntrinsic(const RiseFall *rf, - float value) + float value) { int rf_index = rf->index(); intrinsic_[rf_index] = value; @@ -5961,9 +5954,9 @@ TimingGroup::setIntrinsic(const RiseFall *rf, void TimingGroup::intrinsic(const RiseFall *rf, - // Return values. - float &value, - bool &exists) + // Return values. + float &value, + bool &exists) { int rf_index = rf->index(); value = intrinsic_[rf_index]; @@ -5972,7 +5965,7 @@ TimingGroup::intrinsic(const RiseFall *rf, void TimingGroup::setResistance(const RiseFall *rf, - float value) + float value) { int rf_index = rf->index(); resistance_[rf_index] = value; @@ -5981,9 +5974,9 @@ TimingGroup::setResistance(const RiseFall *rf, void TimingGroup::resistance(const RiseFall *rf, - // Return values. - float &value, - bool &exists) + // Return values. + float &value, + bool &exists) { int rf_index = rf->index(); value = resistance_[rf_index]; @@ -5998,7 +5991,7 @@ TimingGroup::cell(const RiseFall *rf) void TimingGroup::setCell(const RiseFall *rf, - TableModel *model) + TableModel *model) { cell_[rf->index()] = model; } @@ -6011,7 +6004,7 @@ TimingGroup::constraint(const RiseFall *rf) void TimingGroup::setConstraint(const RiseFall *rf, - TableModel *model) + TableModel *model) { constraint_[rf->index()] = model; } @@ -6024,31 +6017,31 @@ TimingGroup::transition(const RiseFall *rf) void TimingGroup::setTransition(const RiseFall *rf, - TableModel *model) + TableModel *model) { transition_[rf->index()] = model; } void TimingGroup::setDelaySigma(const RiseFall *rf, - const EarlyLate *early_late, - TableModel *model) + const EarlyLate *early_late, + TableModel *model) { delay_sigma_[rf->index()][early_late->index()] = model; } void TimingGroup::setSlewSigma(const RiseFall *rf, - const EarlyLate *early_late, - TableModel *model) + const EarlyLate *early_late, + TableModel *model) { slew_sigma_[rf->index()][early_late->index()] = model; } void TimingGroup::setConstraintSigma(const RiseFall *rf, - const EarlyLate *early_late, - TableModel *model) + const EarlyLate *early_late, + TableModel *model) { constraint_sigma_[rf->index()][early_late->index()] = model; } @@ -6099,9 +6092,9 @@ LeakagePowerGroup::~LeakagePowerGroup() //////////////////////////////////////////////////////////////// PortNameBitIterator::PortNameBitIterator(LibertyCell *cell, - const char *port_name, - LibertyReader *visitor, - int line) : + const char *port_name, + LibertyReader *visitor, + int line) : cell_(cell), visitor_(visitor), line_(line), @@ -6137,29 +6130,29 @@ PortNameBitIterator::init(const char *port_name) if (is_range) { port = visitor_->findPort(port_name); if (port) { - if (port->isBus()) { - if (port->busIndexInRange(from) - && port->busIndexInRange(to)) { - range_bus_port_ = port; - range_from_ = from; - range_to_ = to; - range_bit_ = from; - } - else - visitor_->libWarn(1292, line_, "port %s subscript out of range.", - port_name); - } - else - visitor_->libWarn(1293, line_, "port range %s of non-bus port %s.", - port_name, - bus_name.c_str()); + if (port->isBus()) { + if (port->busIndexInRange(from) + && port->busIndexInRange(to)) { + range_bus_port_ = port; + range_from_ = from; + range_to_ = to; + range_bit_ = from; + } + else + visitor_->libWarn(1292, line_, "port %s subscript out of range.", + port_name); + } + else + visitor_->libWarn(1293, line_, "port range %s of non-bus port %s.", + port_name, + bus_name.c_str()); } else { - range_bus_name_ = bus_name; - range_from_ = from; - range_to_ = to; - range_bit_ = from; - findRangeBusNameNext(); + range_bus_name_ = bus_name; + range_from_ = from; + range_to_ = to; + range_bit_ = from; + findRangeBusNameNext(); } size_ = abs(from - to) + 1; } @@ -6179,11 +6172,11 @@ PortNameBitIterator::hasNext() return port_ || (bit_iterator_ && bit_iterator_->hasNext()) || (range_bus_port_ - && ((range_from_ > range_to_) - ? range_bit_ >= range_to_ - : range_bit_ <= range_from_)) + && ((range_from_ > range_to_) + ? range_bit_ >= range_to_ + : range_bit_ <= range_from_)) || (!range_bus_name_.empty() - && range_name_next_); + && range_name_next_); } LibertyPort * @@ -6229,9 +6222,9 @@ PortNameBitIterator::findRangeBusNameNext() range_name_next_ = visitor_->findPort(bus_bit_name.c_str()); if (range_name_next_) { if (range_from_ > range_to_) - range_bit_--; + range_bit_--; else - range_bit_++; + range_bit_++; } else visitor_->libWarn(1295, line_, "port %s not found.", bus_bit_name.c_str()); diff --git a/liberty/LibertyReader.hh b/liberty/LibertyReader.hh index bc1a47a7..648e8f1f 100644 --- a/liberty/LibertyReader.hh +++ b/liberty/LibertyReader.hh @@ -31,7 +31,7 @@ class LibertyLibrary; LibertyLibrary * readLibertyFile(const char *filename, - bool infer_latches, - Network *network); + bool infer_latches, + Network *network); } // namespace diff --git a/liberty/LibertyReaderPvt.hh b/liberty/LibertyReaderPvt.hh index c31888f7..a87a2039 100644 --- a/liberty/LibertyReaderPvt.hh +++ b/liberty/LibertyReaderPvt.hh @@ -26,9 +26,8 @@ #include #include +#include -#include "Vector.hh" -#include "Map.hh" #include "StringSeq.hh" #include "MinMax.hh" #include "NetworkClass.hh" @@ -60,20 +59,20 @@ class TimingArcBuilder; class LibertyAttr; class OutputWaveform; -typedef void (LibertyReader::*LibraryAttrVisitor)(LibertyAttr *attr); -typedef void (LibertyReader::*LibraryGroupVisitor)(LibertyGroup *group); -typedef Map LibraryAttrMap; -typedef Map LibraryGroupMap; -typedef Vector PortGroupSeq; -typedef Vector SequentialGroupSeq; -typedef Vector LibertyFuncSeq; -typedef Vector TimingGroupSeq; -typedef Vector InternalPowerGroupSeq; -typedef Vector LeakagePowerGroupSeq; -typedef void (LibertyPort::*LibertyPortBoolSetter)(bool value); -typedef Vector OutputWaveformSeq; -typedef std::vector StdStringSeq; -typedef std::function LibertySetFunc; +using LibraryAttrVisitor = void (LibertyReader::*)(LibertyAttr *attr); +using LibraryGroupVisitor = void (LibertyReader::*)(LibertyGroup *group); +using LibraryAttrMap = std::map; +using LibraryGroupMap = std::map; +using PortGroupSeq = std::vector; +using SequentialGroupSeq = std::vector; +using LibertyFuncSeq = std::vector; +using TimingGroupSeq = std::vector; +using InternalPowerGroupSeq = std::vector; +using LeakagePowerGroupSeq = std::vector; +using LibertyPortBoolSetter = void (LibertyPort::*)(bool value); +using OutputWaveformSeq = std::vector; +using StdStringSeq = std::vector; +using LibertySetFunc = std::function; class LibertyReader : public LibertyGroupVisitor { @@ -104,9 +103,9 @@ public: virtual void visitPowerUnit(LibertyAttr *attr); virtual void visitDistanceUnit(LibertyAttr *attr); virtual void parseUnits(LibertyAttr *attr, - const char *suffix, - float &scale_var, - Unit *unit_suffix); + const char *suffix, + float &scale_var, + Unit *unit_suffix); virtual void visitDelayModel(LibertyAttr *attr); virtual void visitVoltageMap(LibertyAttr *attr); virtual void visitBusStyle(LibertyAttr *attr); @@ -121,15 +120,15 @@ public: virtual void visitDefaultIntrinsicRise(LibertyAttr *attr); virtual void visitDefaultIntrinsicFall(LibertyAttr *attr); virtual void visitDefaultIntrinsic(LibertyAttr *attr, - const RiseFall *rf); + const RiseFall *rf); virtual void visitDefaultInoutPinRiseRes(LibertyAttr *attr); virtual void visitDefaultInoutPinFallRes(LibertyAttr *attr); virtual void visitDefaultInoutPinRes(LibertyAttr *attr, - const RiseFall *rf); + const RiseFall *rf); virtual void visitDefaultOutputPinRiseRes(LibertyAttr *attr); virtual void visitDefaultOutputPinFallRes(LibertyAttr *attr); virtual void visitDefaultOutputPinRes(LibertyAttr *attr, - const RiseFall *rf); + const RiseFall *rf); virtual void visitDefaultFanoutLoad(LibertyAttr *attr); virtual void visitDefaultWireLoad(LibertyAttr *attr); virtual void visitDefaultWireLoadMode(LibertyAttr *attr); @@ -138,19 +137,19 @@ public: virtual void visitInputThresholdPctFall(LibertyAttr *attr); virtual void visitInputThresholdPctRise(LibertyAttr *attr); virtual void visitInputThresholdPct(LibertyAttr *attr, - const RiseFall *rf); + const RiseFall *rf); virtual void visitOutputThresholdPctFall(LibertyAttr *attr); virtual void visitOutputThresholdPctRise(LibertyAttr *attr); virtual void visitOutputThresholdPct(LibertyAttr *attr, - const RiseFall *rf); + const RiseFall *rf); virtual void visitSlewLowerThresholdPctFall(LibertyAttr *attr); virtual void visitSlewLowerThresholdPctRise(LibertyAttr *attr); virtual void visitSlewLowerThresholdPct(LibertyAttr *attr, - const RiseFall *rf); + const RiseFall *rf); virtual void visitSlewUpperThresholdPctFall(LibertyAttr *attr); virtual void visitSlewUpperThresholdPctRise(LibertyAttr *attr); virtual void visitSlewUpperThresholdPct(LibertyAttr *attr, - const RiseFall *rf); + const RiseFall *rf); virtual void visitSlewDerateFromLibrary(LibertyAttr *attr); virtual void beginTechnology(LibertyGroup *group); @@ -158,7 +157,7 @@ public: virtual void beginTableTemplateDelay(LibertyGroup *group); virtual void beginTableTemplateOutputCurrent(LibertyGroup *group); virtual void beginTableTemplate(LibertyGroup *group, - TableTemplateType type); + TableTemplateType type); virtual void endTableTemplate(LibertyGroup *group); virtual void visitVariable1(LibertyAttr *attr); virtual void visitVariable2(LibertyAttr *attr); @@ -179,7 +178,7 @@ public: virtual void checkScaledCell(LibertyGroup *group); virtual void finishPortGroups(); virtual void checkPort(LibertyPort *port, - int line); + int line); virtual void makeTimingArcs(PortGroup *port_group); virtual void makeInternalPowers(PortGroup *port_group); virtual void makeCellSequentials(); @@ -189,19 +188,19 @@ public: virtual void parseCellFuncs(); virtual void makeLibertyFunc(const char *expr, LibertySetFunc set_func, - bool invert, - const char *attr_name, - LibertyStmt *stmt); + bool invert, + const char *attr_name, + LibertyStmt *stmt); virtual void makeTimingArcs(LibertyPort *to_port, - TimingGroup *timing); + TimingGroup *timing); virtual void makeTimingArcs(const char *from_port_name, - PortNameBitIterator &from_port_iter, - LibertyPort *to_port, - LibertyPort *related_out_port, - TimingGroup *timing); + PortNameBitIterator &from_port_iter, + LibertyPort *to_port, + LibertyPort *related_out_port, + TimingGroup *timing); virtual void makeTimingArcs(LibertyPort *to_port, LibertyPort *related_out_port, - TimingGroup *timing); + TimingGroup *timing); virtual void visitClockGatingIntegratedCell(LibertyAttr *attr); virtual void visitArea(LibertyAttr *attr); @@ -246,20 +245,20 @@ public: virtual void visitMaxFanout(LibertyAttr *attr); virtual void visitMinFanout(LibertyAttr *attr); virtual void visitFanout(LibertyAttr *attr, - const MinMax *min_max); + const MinMax *min_max); virtual void visitMaxTransition(LibertyAttr *attr); virtual void visitMinTransition(LibertyAttr *attr); virtual void visitMinMaxTransition(LibertyAttr *attr, - const MinMax *min_max); + const MinMax *min_max); virtual void visitMaxCapacitance(LibertyAttr *attr); virtual void visitMinCapacitance(LibertyAttr *attr); virtual void visitMinMaxCapacitance(LibertyAttr *attr, - const MinMax *min_max); + const MinMax *min_max); virtual void visitMinPeriod(LibertyAttr *attr); virtual void visitMinPulseWidthLow(LibertyAttr *attr); virtual void visitMinPulseWidthHigh(LibertyAttr *attr); virtual void visitMinPulseWidth(LibertyAttr *attr, - const RiseFall *rf); + const RiseFall *rf); virtual void visitPulseClock(LibertyAttr *attr); virtual void visitClockGateClockPin(LibertyAttr *attr); virtual void visitClockGateEnablePin(LibertyAttr *attr); @@ -312,15 +311,15 @@ public: virtual void beginLatchBank(LibertyGroup *group); virtual void endLatchBank(LibertyGroup *group); virtual void beginSequential(LibertyGroup *group, - bool is_register, - bool is_bank); + bool is_register, + bool is_bank); virtual void seqPortNames(LibertyGroup *group, - const char *&out_name, - const char *&out_inv_name, - bool &has_size, - int &size); + const char *&out_name, + const char *&out_inv_name, + bool &has_size, + int &size); virtual void checkLatchEnableSense(FuncExpr *enable_func, - int line); + int line); virtual void visitClockedOn(LibertyAttr *attr); virtual void visitDataIn(LibertyAttr *attr); virtual void visitClear(LibertyAttr *attr); @@ -336,10 +335,10 @@ public: virtual void endTiming(LibertyGroup *group); virtual void visitRelatedPin(LibertyAttr *attr); virtual void visitRelatedPin(LibertyAttr *attr, - RelatedPortGroup *group); + RelatedPortGroup *group); virtual void visitRelatedBusPins(LibertyAttr *attr); virtual void visitRelatedBusPins(LibertyAttr *attr, - RelatedPortGroup *group); + RelatedPortGroup *group); virtual void visitRelatedOutputPin(LibertyAttr *attr); virtual void visitTimingType(LibertyAttr *attr); virtual void visitTimingSense(LibertyAttr *attr); @@ -349,11 +348,11 @@ public: virtual void visitIntrinsicRise(LibertyAttr *attr); virtual void visitIntrinsicFall(LibertyAttr *attr); virtual void visitIntrinsic(LibertyAttr *attr, - const RiseFall *rf); + const RiseFall *rf); virtual void visitRiseResistance(LibertyAttr *attr); virtual void visitFallResistance(LibertyAttr *attr); virtual void visitRiseFallResistance(LibertyAttr *attr, - const RiseFall *rf); + const RiseFall *rf); virtual void visitValue(LibertyAttr *attr); virtual void visitValues(LibertyAttr *attr); virtual void beginCellRise(LibertyGroup *group); @@ -371,24 +370,24 @@ public: virtual void endRiseFallTransitionDegredation(LibertyGroup *group); virtual void beginTableModel(LibertyGroup *group, - TableTemplateType type, - const RiseFall *rf, - float scale, - ScaleFactorType scale_factor_type); + TableTemplateType type, + const RiseFall *rf, + float scale, + ScaleFactorType scale_factor_type); virtual void endTableModel(); virtual void beginTimingTableModel(LibertyGroup *group, - const RiseFall *rf, - ScaleFactorType scale_factor_type); + const RiseFall *rf, + ScaleFactorType scale_factor_type); virtual void beginTable(LibertyGroup *group, - TableTemplateType type, - float scale); + TableTemplateType type, + float scale); virtual void endTable(); virtual void makeTable(LibertyAttr *attr, - float scale); + float scale); virtual FloatTable *makeFloatTable(LibertyAttr *attr, - size_t rows, - size_t cols, - float scale); + size_t rows, + size_t cols, + float scale); virtual void beginLut(LibertyGroup *group); virtual void endLut(LibertyGroup *group); @@ -418,11 +417,11 @@ public: virtual void visitRelatedPowerPin(LibertyAttr *attr); virtual void visitRelatedPgPin(LibertyAttr *attr); virtual void makeInternalPowers(LibertyPort *port, - InternalPowerGroup *power_group); + InternalPowerGroup *power_group); virtual void makeInternalPowers(LibertyPort *port, - const char *related_port_name, - PortNameBitIterator &related_port_iter, - InternalPowerGroup *power_group); + const char *related_port_name, + PortNameBitIterator &related_port_iter, + InternalPowerGroup *power_group); // AOCV attributes. virtual void beginTableTemplateOcv(LibertyGroup *group); @@ -496,7 +495,7 @@ public: void beginEcsmWaveform(LibertyGroup *group); void endEcsmWaveform(LibertyGroup *group); LibertyPort *findPort(LibertyCell *cell, - const char *port_name); + const char *port_name); protected: LibertyPort *makePort(LibertyCell *cell, @@ -517,10 +516,10 @@ protected: virtual void begin(LibertyGroup *group); virtual void end(LibertyGroup *group); void defineGroupVisitor(const char *type, - LibraryGroupVisitor begin_visitor, - LibraryGroupVisitor end_visitor); + LibraryGroupVisitor begin_visitor, + LibraryGroupVisitor end_visitor); void defineAttrVisitor(const char *attr_name, - LibraryAttrVisitor visitor); + LibraryAttrVisitor visitor); void parseNames(const char *name_str); void clearAxisValues(); void makeTableAxis(int index, @@ -540,59 +539,59 @@ protected: const char *getAttrString(LibertyAttr *attr); void getAttrInt(LibertyAttr *attr, - // Return values. - int &value, - bool &exists); + // Return values. + int &value, + bool &exists); void getAttrFloat(LibertyAttr *attr, - // Return values. - float &value, - bool &valid); + // Return values. + float &value, + bool &valid); void getAttrFloat(LibertyAttr *attr, - LibertyAttrValue *attr_value, - // Return values. - float &value, - bool &valid); + LibertyAttrValue *attr_value, + // Return values. + float &value, + bool &valid); void getAttrFloat2(LibertyAttr *attr, - // Return values. - float &value1, - float &value2, - bool &exists); + // Return values. + float &value1, + float &value2, + bool &exists); void parseStringFloatList(const char *float_list, - float scale, - FloatSeq *values, - LibertyAttr *attr); + float scale, + FloatSeq *values, + LibertyAttr *attr); LogicValue getAttrLogicValue(LibertyAttr *attr); void getAttrBool(LibertyAttr *attr, - // Return values. - bool &value, - bool &exists); + // Return values. + bool &value, + bool &exists); void visitVariable(int index, - LibertyAttr *attr); + LibertyAttr *attr); void visitIndex(int index, - LibertyAttr *attr); + LibertyAttr *attr); TableAxisPtr makeAxis(int index, LibertyGroup *group); FloatSeq *readFloatSeq(LibertyAttr *attr, - float scale); + float scale); void variableValue(const char *var, - float &value, - bool &exists); + float &value, + bool &exists); FuncExpr *parseFunc(const char *func, - const char *attr_name, - int line); + const char *attr_name, + int line); void libWarn(int id, LibertyStmt *stmt, - const char *fmt, - ...) + const char *fmt, + ...) __attribute__((format (printf, 4, 5))); void libWarn(int id, int line, - const char *fmt, - ...) + const char *fmt, + ...) __attribute__((format (printf, 4, 5))); void libError(int id, LibertyStmt *stmt, - const char *fmt, ...) + const char *fmt, ...) __attribute__((format (printf, 4, 5))); const char *filename_; @@ -697,9 +696,9 @@ class LibertyFunc public: LibertyFunc(const char *expr, LibertySetFunc set_func, - bool invert, - const char *attr_name, - int line); + bool invert, + const char *attr_name, + int line); ~LibertyFunc(); const char *expr() const { return expr_; } LibertySetFunc setFunc() const { return set_func_; } @@ -722,7 +721,7 @@ class PortGroup { public: PortGroup(LibertyPortSeq *ports, - int line); + int line); ~PortGroup(); LibertyPortSeq *ports() const { return ports_; } TimingGroupSeq &timingGroups() { return timings_; } @@ -745,7 +744,7 @@ private: class RelatedPortGroup { public: - explicit RelatedPortGroup(int line); + RelatedPortGroup(int line); virtual ~RelatedPortGroup(); int line() const { return line_; } StringSeq *relatedPortNames() const { return related_port_names_; } @@ -763,11 +762,11 @@ class SequentialGroup { public: SequentialGroup(bool is_register, - bool is_bank, - LibertyPort *out_port, - LibertyPort *out_inv_port, - int size, - int line); + bool is_bank, + LibertyPort *out_port, + LibertyPort *out_inv_port, + int size, + int line); ~SequentialGroup(); LibertyPort *outPort() const { return out_port_; } LibertyPort *outInvPort() const { return out_inv_port_; } @@ -827,43 +826,43 @@ private: class TimingGroup : public RelatedPortGroup { public: - explicit TimingGroup(int line); + TimingGroup(int line); virtual ~TimingGroup(); TimingArcAttrsPtr attrs() { return attrs_; } const char *relatedOutputPortName()const {return related_output_port_name_;} void setRelatedOutputPortName(const char *name); void intrinsic(const RiseFall *rf, - // Return values. - float &value, - bool &exists); + // Return values. + float &value, + bool &exists); void setIntrinsic(const RiseFall *rf, - float value); + float value); void resistance(const RiseFall *rf, - // Return values. - float &value, - bool &exists); + // Return values. + float &value, + bool &exists); void setResistance(const RiseFall *rf, - float value); + float value); TableModel *cell(const RiseFall *rf); void setCell(const RiseFall *rf, - TableModel *model); + TableModel *model); TableModel *constraint(const RiseFall *rf); void setConstraint(const RiseFall *rf, - TableModel *model); + TableModel *model); TableModel *transition(const RiseFall *rf); void setTransition(const RiseFall *rf, - TableModel *model); + TableModel *model); void makeTimingModels(LibertyCell *cell, - LibertyReader *visitor); + LibertyReader *visitor); void setDelaySigma(const RiseFall *rf, - const EarlyLate *early_late, - TableModel *model); + const EarlyLate *early_late, + TableModel *model); void setSlewSigma(const RiseFall *rf, - const EarlyLate *early_late, - TableModel *model); + const EarlyLate *early_late, + TableModel *model); void setConstraintSigma(const RiseFall *rf, - const EarlyLate *early_late, - TableModel *model); + const EarlyLate *early_late, + TableModel *model); void setReceiverModel(ReceiverModelPtr receiver_model); OutputWaveforms *outputWaveforms(const RiseFall *rf); void setOutputWaveforms(const RiseFall *rf, @@ -893,14 +892,14 @@ protected: class InternalPowerGroup : public InternalPowerAttrs, public RelatedPortGroup { public: - explicit InternalPowerGroup(int line); + InternalPowerGroup(int line); virtual ~InternalPowerGroup(); }; class LeakagePowerGroup : public LeakagePowerAttrs { public: - explicit LeakagePowerGroup(int line); + LeakagePowerGroup(int line); virtual ~LeakagePowerGroup(); protected: @@ -915,9 +914,9 @@ class PortNameBitIterator : public Iterator { public: PortNameBitIterator(LibertyCell *cell, - const char *port_name, - LibertyReader *visitor, - int line); + const char *port_name, + LibertyReader *visitor, + int line); ~PortNameBitIterator(); virtual bool hasNext(); virtual LibertyPort *next(); diff --git a/liberty/LibertyWriter.cc b/liberty/LibertyWriter.cc index 2c4dd1a7..4afa66f0 100644 --- a/liberty/LibertyWriter.cc +++ b/liberty/LibertyWriter.cc @@ -312,7 +312,7 @@ LibertyWriter::writeCell(const LibertyCell *cell) const LibertyPort *port = port_iter.next(); if (!port->direction()->isInternal()) { if (port->isPwrGnd()) - writePwrGndPort(port); + writePwrGndPort(port); else if (port->isBus()) writeBusPort(port); else if (port->isBundle()) @@ -364,13 +364,14 @@ LibertyWriter::writePortAttrs(const LibertyPort *port) fprintf(stream_, " function : \"%s\";\n", func->to_string().c_str()); auto tristate_enable = port->tristateEnable(); if (tristate_enable) { - if (tristate_enable->op() == FuncExpr::op_not) { + if (tristate_enable->op() == FuncExpr::Op::not_) { FuncExpr *three_state = tristate_enable->left(); fprintf(stream_, " three_state : \"%s\";\n", three_state->to_string().c_str()); } else { - FuncExpr three_state(FuncExpr::op_not, tristate_enable, nullptr, nullptr); + FuncExpr three_state(FuncExpr::Op::not_, tristate_enable, + nullptr, nullptr); fprintf(stream_, " three_state : \"%s\";\n", three_state.to_string().c_str()); } @@ -460,24 +461,24 @@ LibertyWriter::writeTimingModels(const TimingArc *arc, if (gate_model) { const TableModel *delay_model = gate_model->delayModel(); const char *template_name = delay_model->tblTemplate()->name(); - fprintf(stream_, " cell_%s(%s) {\n", rf->name(), template_name); + fprintf(stream_, " cell_%s(%s) {\n", rf->name(), template_name); writeTableModel(delay_model); - fprintf(stream_, " }\n"); + fprintf(stream_, " }\n"); const TableModel *slew_model = gate_model->slewModel(); if (slew_model) { template_name = slew_model->tblTemplate()->name(); - fprintf(stream_, " %s_transition(%s) {\n", rf->name(), template_name); + fprintf(stream_, " %s_transition(%s) {\n", rf->name(), template_name); writeTableModel(slew_model); - fprintf(stream_, " }\n"); + fprintf(stream_, " }\n"); } } else if (check_model) { const TableModel *model = check_model->model(); const char *template_name = model->tblTemplate()->name(); - fprintf(stream_, " %s_constraint(%s) {\n", rf->name(), template_name); + fprintf(stream_, " %s_constraint(%s) {\n", rf->name(), template_name); writeTableModel(model); - fprintf(stream_, " }\n"); + fprintf(stream_, " }\n"); } else report_->error(1341, "%s/%s/%s timing model not supported.", diff --git a/liberty/LinearModel.cc b/liberty/LinearModel.cc index fbb47d9e..1001e74b 100644 --- a/liberty/LinearModel.cc +++ b/liberty/LinearModel.cc @@ -33,7 +33,7 @@ using std::string; GateLinearModel::GateLinearModel(LibertyCell *cell, float intrinsic, - float resistance) : + float resistance) : GateTimingModel(cell), intrinsic_(intrinsic), resistance_(resistance) @@ -42,12 +42,12 @@ GateLinearModel::GateLinearModel(LibertyCell *cell, void GateLinearModel::gateDelay(const Pvt *, - float, - float load_cap, - bool, - // return values - ArcDelay &gate_delay, - Slew &drvr_slew) const + float, + float load_cap, + bool, + // return values + ArcDelay &gate_delay, + Slew &drvr_slew) const { gate_delay = intrinsic_ + resistance_ * load_cap; drvr_slew = 0.0; @@ -55,10 +55,10 @@ GateLinearModel::gateDelay(const Pvt *, string GateLinearModel::reportGateDelay(const Pvt *, - float, - float load_cap, - bool, - int digits) const + float, + float load_cap, + bool, + int digits) const { const LibertyLibrary *library = cell_->libertyLibrary(); const Units *units = library->units(); @@ -97,22 +97,22 @@ CheckLinearModel::CheckLinearModel(LibertyCell *cell, ArcDelay CheckLinearModel::checkDelay(const Pvt *, - float, - float, - float, - bool) const + float, + float, + float, + bool) const { return intrinsic_; } string CheckLinearModel::reportCheckDelay(const Pvt *, - float, - const char *, - float, - float, - bool, - int digits) const + float, + const char *, + float, + float, + bool, + int digits) const { const LibertyLibrary *library = cell_->libertyLibrary(); const Units *units = library->units(); diff --git a/liberty/Sequential.cc b/liberty/Sequential.cc index 559c6158..a89ae99b 100644 --- a/liberty/Sequential.cc +++ b/liberty/Sequential.cc @@ -29,14 +29,14 @@ namespace sta { Sequential::Sequential(bool is_register, - FuncExpr *clock, - FuncExpr *data, - FuncExpr *clear, - FuncExpr *preset, - LogicValue clr_preset_out, - LogicValue clr_preset_out_inv, - LibertyPort *output, - LibertyPort *output_inv) : + FuncExpr *clock, + FuncExpr *data, + FuncExpr *clear, + FuncExpr *preset, + LogicValue clr_preset_out, + LogicValue clr_preset_out_inv, + LibertyPort *output, + LibertyPort *output_inv) : is_register_(is_register), clock_(clock), data_(data), diff --git a/liberty/TableModel.cc b/liberty/TableModel.cc index b4a0b325..28741630 100644 --- a/liberty/TableModel.cc +++ b/liberty/TableModel.cc @@ -29,6 +29,7 @@ #include "Error.hh" #include "EnumNameMap.hh" +#include "ContainerHelpers.hh" #include "Units.hh" #include "Liberty.hh" @@ -48,10 +49,10 @@ deleteSigmaModels(TableModel *models[EarlyLate::index_count]); static string reportPvt(const LibertyCell *cell, const Pvt *pvt, - int digits); + int digits); static void appendSpaces(string &result, - int count); + int count); TimingModel::TimingModel(LibertyCell *cell) : cell_(cell) @@ -60,9 +61,9 @@ TimingModel::TimingModel(LibertyCell *cell) : GateTableModel::GateTableModel(LibertyCell *cell, TableModel *delay_model, - TableModel *delay_sigma_models[EarlyLate::index_count], - TableModel *slew_model, - TableModel *slew_sigma_models[EarlyLate::index_count], + TableModel *delay_sigma_models[EarlyLate::index_count], + TableModel *slew_model, + TableModel *slew_sigma_models[EarlyLate::index_count], ReceiverModelPtr receiver_model, OutputWaveforms *output_waveforms) : GateTimingModel(cell), @@ -114,31 +115,31 @@ GateTableModel::setIsScaled(bool is_scaled) void GateTableModel::gateDelay(const Pvt *pvt, - float in_slew, - float load_cap, - bool pocv_enabled, - // return values - ArcDelay &gate_delay, - Slew &drvr_slew) const + float in_slew, + float load_cap, + bool pocv_enabled, + // return values + ArcDelay &gate_delay, + Slew &drvr_slew) const { float delay = findValue(pvt, delay_model_, in_slew, load_cap, 0.0); float sigma_early = 0.0; float sigma_late = 0.0; if (pocv_enabled && delay_sigma_models_[EarlyLate::earlyIndex()]) sigma_early = findValue(pvt, delay_sigma_models_[EarlyLate::earlyIndex()], - in_slew, load_cap, 0.0); + in_slew, load_cap, 0.0); if (pocv_enabled && delay_sigma_models_[EarlyLate::lateIndex()]) sigma_late = findValue(pvt, delay_sigma_models_[EarlyLate::lateIndex()], - in_slew, load_cap, 0.0); + in_slew, load_cap, 0.0); gate_delay = makeDelay(delay, sigma_early, sigma_late); float slew = findValue(pvt, slew_model_, in_slew, load_cap, 0.0); if (pocv_enabled && slew_sigma_models_[EarlyLate::earlyIndex()]) sigma_early = findValue(pvt, slew_sigma_models_[EarlyLate::earlyIndex()], - in_slew, load_cap, 0.0); + in_slew, load_cap, 0.0); if (pocv_enabled && slew_sigma_models_[EarlyLate::lateIndex()]) sigma_late = findValue(pvt, slew_sigma_models_[EarlyLate::lateIndex()], - in_slew, load_cap, 0.0); + in_slew, load_cap, 0.0); // Clip negative slews to zero. if (slew < 0.0) slew = 0.0; @@ -159,10 +160,10 @@ GateTableModel::gateDelay(const Pvt *pvt, string GateTableModel::reportGateDelay(const Pvt *pvt, - float in_slew, - float load_cap, - bool pocv_enabled, - int digits) const + float in_slew, + float load_cap, + bool pocv_enabled, + int digits) const { string result = reportPvt(cell_, pvt, digits); result += reportTableLookup("Delay", pvt, delay_model_, in_slew, @@ -180,11 +181,11 @@ GateTableModel::reportGateDelay(const Pvt *pvt, load_cap, 9.0, digits); if (pocv_enabled && slew_sigma_models_[EarlyLate::earlyIndex()]) result += reportTableLookup("Slew sigma(early)", pvt, - slew_sigma_models_[EarlyLate::earlyIndex()], - in_slew, load_cap, 0.0, digits); + slew_sigma_models_[EarlyLate::earlyIndex()], + in_slew, load_cap, 0.0, digits); if (pocv_enabled && slew_sigma_models_[EarlyLate::lateIndex()]) result += reportTableLookup("Slew sigma(late)", pvt, - slew_sigma_models_[EarlyLate::lateIndex()], + slew_sigma_models_[EarlyLate::lateIndex()], in_slew, load_cap, 0.0, digits); float drvr_slew = findValue(pvt, slew_model_, in_slew, load_cap, 0.0); if (drvr_slew < 0.0) @@ -194,17 +195,17 @@ GateTableModel::reportGateDelay(const Pvt *pvt, string GateTableModel::reportTableLookup(const char *result_name, - const Pvt *pvt, - const TableModel *model, - float in_slew, - float load_cap, - float related_out_cap, - int digits) const + const Pvt *pvt, + const TableModel *model, + float in_slew, + float load_cap, + float related_out_cap, + int digits) const { if (model) { float axis_value1, axis_value2, axis_value3; findAxisValues(model, in_slew, load_cap, related_out_cap, - axis_value1, axis_value2, axis_value3); + axis_value1, axis_value2, axis_value3); const LibertyLibrary *library = cell_->libertyLibrary(); return model->reportValue(result_name, cell_, pvt, axis_value1, nullptr, axis_value2, axis_value3, @@ -215,15 +216,15 @@ GateTableModel::reportTableLookup(const char *result_name, float GateTableModel::findValue(const Pvt *pvt, - const TableModel *model, - float in_slew, - float load_cap, - float related_out_cap) const + const TableModel *model, + float in_slew, + float load_cap, + float related_out_cap) const { if (model) { float axis_value1, axis_value2, axis_value3; findAxisValues(model, in_slew, load_cap, related_out_cap, - axis_value1, axis_value2, axis_value3); + axis_value1, axis_value2, axis_value3); return model->findValue(cell_, pvt, axis_value1, axis_value2, axis_value3); } else @@ -232,13 +233,13 @@ GateTableModel::findValue(const Pvt *pvt, void GateTableModel::findAxisValues(const TableModel *model, - float in_slew, - float load_cap, - float related_out_cap, - // Return values. - float &axis_value1, - float &axis_value2, - float &axis_value3) const + float in_slew, + float load_cap, + float related_out_cap, + // Return values. + float &axis_value1, + float &axis_value2, + float &axis_value3) const { switch (model->order()) { case 0: @@ -248,24 +249,24 @@ GateTableModel::findAxisValues(const TableModel *model, break; case 1: axis_value1 = axisValue(model->axis1(), in_slew, load_cap, - related_out_cap); + related_out_cap); axis_value2 = 0.0; axis_value3 = 0.0; break; case 2: axis_value1 = axisValue(model->axis1(), in_slew, load_cap, - related_out_cap); + related_out_cap); axis_value2 = axisValue(model->axis2(), in_slew, load_cap, - related_out_cap); + related_out_cap); axis_value3 = 0.0; break; case 3: axis_value1 = axisValue(model->axis1(), in_slew, load_cap, - related_out_cap); + related_out_cap); axis_value2 = axisValue(model->axis2(), in_slew, load_cap, - related_out_cap); + related_out_cap); axis_value3 = axisValue(model->axis3(), in_slew, load_cap, - related_out_cap); + related_out_cap); break; default: axis_value1 = 0.0; @@ -287,9 +288,9 @@ GateTableModel::driveResistance(const Pvt *pvt) const void GateTableModel::maxCapSlew(float in_slew, - const Pvt *pvt, - float &slew, - float &cap) const + const Pvt *pvt, + float &slew, + float &cap) const { const TableAxis *axis1 = slew_model_->axis1(); const TableAxis *axis2 = slew_model_->axis2(); @@ -300,12 +301,12 @@ GateTableModel::maxCapSlew(float in_slew, slew = findValue(pvt, slew_model_, in_slew, cap, 0.0); } else if (axis2 - && axis2->variable()==TableAxisVariable::total_output_net_capacitance) { + && axis2->variable()==TableAxisVariable::total_output_net_capacitance) { cap = axis2->axisValue(axis2->size() - 1); slew = findValue(pvt, slew_model_, in_slew, cap, 0.0); } else if (axis3 - && axis3->variable()==TableAxisVariable::total_output_net_capacitance) { + && axis3->variable()==TableAxisVariable::total_output_net_capacitance) { cap = axis3->axisValue(axis3->size() - 1); slew = findValue(pvt, slew_model_, in_slew, cap, 0.0); } @@ -321,9 +322,9 @@ GateTableModel::maxCapSlew(float in_slew, float GateTableModel::axisValue(const TableAxis *axis, - float in_slew, - float load_cap, - float related_out_cap) const + float in_slew, + float load_cap, + float related_out_cap) const { TableAxisVariable var = axis->variable(); if (var == TableAxisVariable::input_transition_time @@ -405,7 +406,7 @@ ReceiverModel::checkAxes(TablePtr table) CheckTableModel::CheckTableModel(LibertyCell *cell, TableModel *model, - TableModel *sigma_models[EarlyLate::index_count]) : + TableModel *sigma_models[EarlyLate::index_count]) : CheckTimingModel(cell), model_(model) { @@ -427,10 +428,10 @@ CheckTableModel::setIsScaled(bool is_scaled) ArcDelay CheckTableModel::checkDelay(const Pvt *pvt, - float from_slew, - float to_slew, - float related_out_cap, - bool pocv_enabled) const + float from_slew, + float to_slew, + float related_out_cap, + bool pocv_enabled) const { if (model_) { float mean = findValue(pvt, model_, from_slew, to_slew, related_out_cap); @@ -438,10 +439,10 @@ CheckTableModel::checkDelay(const Pvt *pvt, float sigma_late = 0.0; if (pocv_enabled && sigma_models_[EarlyLate::earlyIndex()]) sigma_early = findValue(pvt, sigma_models_[EarlyLate::earlyIndex()], - from_slew, to_slew, related_out_cap); + from_slew, to_slew, related_out_cap); if (pocv_enabled && sigma_models_[EarlyLate::lateIndex()]) sigma_late = findValue(pvt, sigma_models_[EarlyLate::lateIndex()], - from_slew, to_slew, related_out_cap); + from_slew, to_slew, related_out_cap); return makeDelay(mean, sigma_early, sigma_late); } else @@ -450,15 +451,15 @@ CheckTableModel::checkDelay(const Pvt *pvt, float CheckTableModel::findValue(const Pvt *pvt, - const TableModel *model, - float from_slew, - float to_slew, - float related_out_cap) const + const TableModel *model, + float from_slew, + float to_slew, + float related_out_cap) const { if (model) { float axis_value1, axis_value2, axis_value3; findAxisValues(from_slew, to_slew, related_out_cap, - axis_value1, axis_value2, axis_value3); + axis_value1, axis_value2, axis_value3); return model->findValue(cell_, pvt, axis_value1, axis_value2, axis_value3); } else @@ -467,12 +468,12 @@ CheckTableModel::findValue(const Pvt *pvt, string CheckTableModel::reportCheckDelay(const Pvt *pvt, - float from_slew, - const char *from_slew_annotation, - float to_slew, - float related_out_cap, - bool pocv_enabled, - int digits) const + float from_slew, + const char *from_slew_annotation, + float to_slew, + float related_out_cap, + bool pocv_enabled, + int digits) const { string result = reportTableDelay("Check", pvt, model_, from_slew, from_slew_annotation, to_slew, @@ -492,18 +493,18 @@ CheckTableModel::reportCheckDelay(const Pvt *pvt, string CheckTableModel::reportTableDelay(const char *result_name, - const Pvt *pvt, - const TableModel *model, - float from_slew, - const char *from_slew_annotation, - float to_slew, - float related_out_cap, - int digits) const + const Pvt *pvt, + const TableModel *model, + float from_slew, + const char *from_slew_annotation, + float to_slew, + float related_out_cap, + int digits) const { if (model) { float axis_value1, axis_value2, axis_value3; findAxisValues(from_slew, to_slew, related_out_cap, - axis_value1, axis_value2, axis_value3); + axis_value1, axis_value2, axis_value3); string result = reportPvt(cell_, pvt, digits); result += model_->reportValue(result_name, cell_, pvt, axis_value1, from_slew_annotation, axis_value2, @@ -516,12 +517,12 @@ CheckTableModel::reportTableDelay(const char *result_name, void CheckTableModel::findAxisValues(float from_slew, - float to_slew, - float related_out_cap, - // Return values. - float &axis_value1, - float &axis_value2, - float &axis_value3) const + float to_slew, + float related_out_cap, + // Return values. + float &axis_value1, + float &axis_value2, + float &axis_value3) const { switch (model_->order()) { case 0: @@ -531,24 +532,24 @@ CheckTableModel::findAxisValues(float from_slew, break; case 1: axis_value1 = axisValue(model_->axis1(), from_slew, to_slew, - related_out_cap); + related_out_cap); axis_value2 = 0.0; axis_value3 = 0.0; break; case 2: axis_value1 = axisValue(model_->axis1(), from_slew, to_slew, - related_out_cap); + related_out_cap); axis_value2 = axisValue(model_->axis2(), from_slew, to_slew, - related_out_cap); + related_out_cap); axis_value3 = 0.0; break; case 3: axis_value1 = axisValue(model_->axis1(), from_slew, to_slew, - related_out_cap); + related_out_cap); axis_value2 = axisValue(model_->axis2(), from_slew, to_slew, - related_out_cap); + related_out_cap); axis_value3 = axisValue(model_->axis3(), from_slew, to_slew, - related_out_cap); + related_out_cap); break; default: criticalError(241, "unsupported table order"); @@ -557,9 +558,9 @@ CheckTableModel::findAxisValues(float from_slew, float CheckTableModel::axisValue(const TableAxis *axis, - float from_slew, - float to_slew, - float related_out_cap) const + float from_slew, + float to_slew, + float related_out_cap) const { TableAxisVariable var = axis->variable(); if (var == TableAxisVariable::related_pin_transition) @@ -603,8 +604,8 @@ CheckTableModel::checkAxis(const TableAxis *axis) TableModel::TableModel(TablePtr table, TableTemplate *tbl_template, - ScaleFactorType scale_factor_type, - const RiseFall *rf) : + ScaleFactorType scale_factor_type, + const RiseFall *rf) : table_(table), tbl_template_(tbl_template), scale_factor_type_(int(scale_factor_type)), @@ -659,18 +660,18 @@ TableModel::value(size_t axis_index1, float TableModel::findValue(float axis_value1, - float axis_value2, - float axis_value3) const + float axis_value2, + float axis_value3) const { return table_->findValue(axis_value1, axis_value2, axis_value3); } float TableModel::findValue(const LibertyCell *cell, - const Pvt *pvt, - float axis_value1, - float axis_value2, - float axis_value3) const + const Pvt *pvt, + float axis_value1, + float axis_value2, + float axis_value3) const { return table_->findValue(axis_value1, axis_value2, axis_value3) * scaleFactor(cell, pvt); @@ -678,7 +679,7 @@ TableModel::findValue(const LibertyCell *cell, float TableModel::scaleFactor(const LibertyCell *cell, - const Pvt *pvt) const + const Pvt *pvt) const { if (is_scaled_) // Scaled tables are not derated because scale factors are wrt @@ -691,14 +692,14 @@ TableModel::scaleFactor(const LibertyCell *cell, string TableModel::reportValue(const char *result_name, - const LibertyCell *cell, - const Pvt *pvt, - float value1, - const char *comment1, - float value2, - float value3, + const LibertyCell *cell, + const Pvt *pvt, + float value1, + const char *comment1, + float value2, + float value3, const Unit *table_unit, - int digits) const + int digits) const { string result = table_->reportValue("Table value", cell, pvt, value1, comment1, value2, value3, table_unit, digits); @@ -714,8 +715,8 @@ TableModel::reportValue(const char *result_name, static string reportPvt(const LibertyCell *cell, - const Pvt *pvt, - int digits) + const Pvt *pvt, + int digits) { const LibertyLibrary *library = cell->libertyLibrary(); if (pvt == nullptr) @@ -723,9 +724,9 @@ reportPvt(const LibertyCell *cell, if (pvt) { string result; stringPrint(result, "P = %.*f V = %.*f T = %.*f\n", - digits, pvt->process(), - digits, pvt->voltage(), - digits, pvt->temperature()); + digits, pvt->process(), + digits, pvt->voltage(), + digits, pvt->temperature()); return result; } return ""; @@ -733,16 +734,16 @@ reportPvt(const LibertyCell *cell, string TableModel::reportPvtScaleFactor(const LibertyCell *cell, - const Pvt *pvt, - int digits) const + const Pvt *pvt, + int digits) const { if (pvt == nullptr) pvt = cell->libertyLibrary()->defaultOperatingConditions(); if (pvt) { string result; stringPrint(result, "PVT scale factor = %.*f\n", - digits, - scaleFactor(cell, pvt)); + digits, + scaleFactor(cell, pvt)); return result; } return ""; @@ -766,22 +767,22 @@ Table0::value(size_t, float Table0::findValue(float, - float, - float) const + float, + float) const { return value_; } string Table0::reportValue(const char *result_name, - const LibertyCell *, - const Pvt *, - float value1, - const char *comment1, - float value2, - float value3, + const LibertyCell *, + const Pvt *, + float value1, + const char *comment1, + float value2, + float value3, const Unit *table_unit, - int digits) const + int digits) const { string result = result_name; result += " constant = "; @@ -794,7 +795,7 @@ Table0::reportValue(const char *result_name, void Table0::report(const Units *units, - Report *report) const + Report *report) const { int digits = 4; const Unit *table_unit = units->timeUnit(); @@ -811,7 +812,7 @@ Table1::Table1() : } Table1::Table1(FloatSeq *values, - TableAxisPtr axis1) : + TableAxisPtr axis1) : Table(), values_(values), axis1_(axis1) @@ -865,8 +866,8 @@ Table1::value(size_t axis_index1) const float Table1::findValue(float axis_value1, - float, - float) const + float, + float) const { return findValue(axis_value1); } @@ -913,14 +914,14 @@ Table1::findValueClip(float axis_value1) const string Table1::reportValue(const char *result_name, - const LibertyCell *cell, - const Pvt *, - float value1, - const char *comment1, - float value2, - float value3, + const LibertyCell *cell, + const Pvt *, + float value1, + const char *comment1, + float value2, + float value3, const Unit *table_unit, - int digits) const + int digits) const { const Units *units = cell->libertyLibrary()->units(); const Unit *unit1 = axis1_->unit(units); @@ -946,7 +947,7 @@ Table1::reportValue(const char *result_name, result += table_unit->asString(value(index1), digits); result += " "; result += table_unit->asString(value(index1 + 1), - digits); + digits); result += '\n'; } @@ -959,7 +960,7 @@ Table1::reportValue(const char *result_name, void Table1::report(const Units *units, - Report *report) const + Report *report) const { int digits = 4; const Unit *unit1 = axis1_->unit(units); @@ -984,8 +985,8 @@ Table1::report(const Units *units, //////////////////////////////////////////////////////////////// Table2::Table2(FloatTable *values, - TableAxisPtr axis1, - TableAxisPtr axis2) : + TableAxisPtr axis1, + TableAxisPtr axis2) : Table(), values_(values), axis1_(axis1), @@ -995,7 +996,7 @@ Table2::Table2(FloatTable *values, Table2::~Table2() { - values_->deleteContents(); + deleteContents(*values_); delete values_; } @@ -1018,8 +1019,8 @@ Table2::value(size_t axis_index1, // Bilinear Interpolation. float Table2::findValue(float axis_value1, - float axis_value2, - float) const + float axis_value2, + float) const { size_t size1 = axis1_->size(); size_t size2 = axis2_->size(); @@ -1035,8 +1036,8 @@ Table2::findValue(float axis_value1, double dx2 = (x2 - x2l) / (x2u - x2l); double y01 = value(0, axis_index2 + 1); double tbl_value - = (1 - dx2) * y00 - + dx2 * y01; + = (1 - dx2) * y00 + + dx2 * y01; return tbl_value; } } @@ -1079,14 +1080,14 @@ Table2::findValue(float axis_value1, string Table2::reportValue(const char *result_name, - const LibertyCell *cell, - const Pvt *, - float value1, - const char *comment1, - float value2, - float value3, + const LibertyCell *cell, + const Pvt *, + float value1, + const char *comment1, + float value2, + float value3, const Unit *table_unit, - int digits) const + int digits) const { const Units *units = cell->libertyLibrary()->units(); const Unit *unit1 = axis1_->unit(units); @@ -1146,7 +1147,7 @@ Table2::reportValue(const char *result_name, void Table2::report(const Units *units, - Report *report) const + Report *report) const { int digits = 4; const Unit *table_unit = units->timeUnit(); @@ -1175,9 +1176,9 @@ Table2::report(const Units *units, //////////////////////////////////////////////////////////////// Table3::Table3(FloatTable *values, - TableAxisPtr axis1, - TableAxisPtr axis2, - TableAxisPtr axis3) : + TableAxisPtr axis1, + TableAxisPtr axis2, + TableAxisPtr axis3) : Table2(values, axis1, axis2), axis3_(axis3) { @@ -1195,8 +1196,8 @@ Table3::value(size_t axis_index1, // Bilinear Interpolation. float Table3::findValue(float axis_value1, - float axis_value2, - float axis_value3) const + float axis_value2, + float axis_value3) const { size_t axis_index1 = axis1_->findAxisIndex(axis_value1); size_t axis_index2 = axis2_->findAxisIndex(axis_value2); @@ -1226,7 +1227,7 @@ Table3::findValue(float axis_value1, if (axis2_->size() != 1) { y110 = value(axis_index1 + 1, axis_index2 + 1, axis_index3); if (axis3_->size() != 1) - y111 = value(axis_index1 + 1, axis_index2 + 1, axis_index3 + 1); + y111 = value(axis_index1 + 1, axis_index2 + 1, axis_index3 + 1); } } if (axis2_->size() != 1) { @@ -1269,14 +1270,14 @@ Table3::findValue(float axis_value1, // 0.40 | 0.20 0.30 string Table3::reportValue(const char *result_name, - const LibertyCell *cell, - const Pvt *, - float value1, - const char *comment1, - float value2, - float value3, + const LibertyCell *cell, + const Pvt *, + float value1, + const char *comment1, + float value2, + float value3, const Unit *table_unit, - int digits) const + int digits) const { const Units *units = cell->libertyLibrary()->units(); const Unit *unit1 = axis1_->unit(units); @@ -1322,11 +1323,11 @@ Table3::reportValue(const char *result_name, result += unit1->asString(axis1_->axisValue(axis_index1+1), digits); result += " v / "; result += table_unit->asString(value(axis_index1+1,axis_index2,axis_index3), - digits); + digits); if (axis3_->size() != 1) { result += " "; result += table_unit->asString(value(axis_index1+1,axis_index2,axis_index3+1), - digits); + digits); } } else { @@ -1343,7 +1344,7 @@ Table3::reportValue(const char *result_name, if (axis3_->size() != 1) { result += " "; result += table_unit->asString(value(axis_index1, axis_index2, axis_index3+1), - digits); + digits); } result += '\n'; @@ -1351,11 +1352,11 @@ Table3::reportValue(const char *result_name, if (axis1_->size() != 1 && axis2_->size() != 1) { result += table_unit->asString(value(axis_index1+1,axis_index2+1,axis_index3), - digits); + digits); if (axis3_->size() != 1) { result += " "; result +=table_unit->asString(value(axis_index1+1,axis_index2+1,axis_index3+1), - digits); + digits); } } result += '\n'; @@ -1383,7 +1384,7 @@ Table3::reportValue(const char *result_name, static void appendSpaces(string &result, - int count) + int count) { while (count--) result += ' '; @@ -1391,7 +1392,7 @@ appendSpaces(string &result, void Table3::report(const Units *units, - Report *report) const + Report *report) const { int digits = 4; const Unit *table_unit = units->timeUnit(); @@ -1426,7 +1427,7 @@ Table3::report(const Units *units, //////////////////////////////////////////////////////////////// TableAxis::TableAxis(TableAxisVariable variable, - FloatSeq *values) : + FloatSeq *values) : variable_(variable), values_(values) { @@ -1489,9 +1490,9 @@ findValueIndex(float value, while (upper - lower > 1) { int mid = (upper + lower) >> 1; if (value >= (*values)[mid]) - lower = mid; + lower = mid; else - upper = mid; + upper = mid; } return lower; } @@ -1517,9 +1518,9 @@ TableAxis::findAxisIndex(float value, return; } if (value > (*values_)[mid]) - lower = mid; + lower = mid; else - upper = mid; + upper = mid; } } exists = false; @@ -1539,9 +1540,9 @@ TableAxis::findAxisClosestIndex(float value) const while (upper - lower > 1) { int mid = (upper + lower) >> 1; if (value >= (*values_)[mid]) - lower = mid; + lower = mid; else - upper = mid; + upper = mid; } if ((value - (*values_)[lower]) < ((*values_)[upper] - value)) return lower; @@ -1599,7 +1600,7 @@ tableVariableString(TableAxisVariable variable) const Unit * tableVariableUnit(TableAxisVariable variable, - const Units *units) + const Units *units) { switch (variable) { case TableAxisVariable::total_output_net_capacitance: @@ -1649,9 +1650,9 @@ OutputWaveforms::OutputWaveforms(TableAxisPtr slew_axis, OutputWaveforms::~OutputWaveforms() { - current_waveforms_.deleteContents(); - voltage_waveforms_.deleteContents(); - voltage_currents_.deleteContents(); + deleteContents(current_waveforms_);; + deleteContents(voltage_waveforms_); + deleteContents(voltage_currents_); delete ref_times_; } diff --git a/liberty/TimingArc.cc b/liberty/TimingArc.cc index f203a4af..0a7acff5 100644 --- a/liberty/TimingArc.cc +++ b/liberty/TimingArc.cc @@ -24,13 +24,14 @@ #include "TimingModel.hh" +#include "ContainerHelpers.hh" #include "EnumNameMap.hh" #include "FuncExpr.hh" #include "TimingRole.hh" #include "Liberty.hh" #include "TimingArc.hh" -#include "DcalcAnalysisPt.hh" #include "TableModel.hh" +#include "Sdc.hh" namespace sta { @@ -39,10 +40,10 @@ using std::make_shared; static bool timingArcsEquiv(const TimingArcSet *set1, - const TimingArcSet *set2); + const TimingArcSet *set2); static bool timingArcsLess(const TimingArcSet *set1, - const TimingArcSet *set2); + const TimingArcSet *set2); //////////////////////////////////////////////////////////////// @@ -151,7 +152,7 @@ TimingArcAttrs::model(const RiseFall *rf) const void TimingArcAttrs::setModel(const RiseFall *rf, - TimingModel *model) + TimingModel *model) { models_[rf->index()] = model; } @@ -192,11 +193,11 @@ TimingArcAttrsPtr TimingArcSet::wire_timing_arc_attrs_ = nullptr; TimingArcSet *TimingArcSet::wire_timing_arc_set_ = nullptr; TimingArcSet::TimingArcSet(LibertyCell *cell, - LibertyPort *from, - LibertyPort *to, - LibertyPort *related_out, - const TimingRole *role, - TimingArcAttrsPtr attrs) : + LibertyPort *from, + LibertyPort *to, + LibertyPort *related_out, + const TimingRole *role, + TimingArcAttrsPtr attrs) : from_(from), to_(to), related_out_(related_out), @@ -204,7 +205,6 @@ TimingArcSet::TimingArcSet(LibertyCell *cell, attrs_(attrs), is_cond_default_(false), index_(cell->addTimingArcSet(this)), - is_disabled_constraint_(false), from_arc1_{nullptr, nullptr}, from_arc2_{nullptr, nullptr}, to_arc_{nullptr, nullptr} @@ -220,7 +220,6 @@ TimingArcSet::TimingArcSet(const TimingRole *role, attrs_(attrs), is_cond_default_(false), index_(0), - is_disabled_constraint_(false), from_arc1_{nullptr, nullptr}, from_arc2_{nullptr, nullptr}, to_arc_{nullptr, nullptr} @@ -229,7 +228,7 @@ TimingArcSet::TimingArcSet(const TimingRole *role, TimingArcSet::~TimingArcSet() { - arcs_.deleteContents(); + deleteContents(arcs_); } bool @@ -312,9 +311,9 @@ TimingArcSet::setIsCondDefault(bool is_default) void TimingArcSet::arcsFrom(const RiseFall *from_rf, - // Return values. - TimingArc *&arc1, - TimingArc *&arc2) const + // Return values. + TimingArc *&arc1, + TimingArc *&arc2) const { int rf_index = from_rf->index(); arc1 = from_arc1_[rf_index]; @@ -349,12 +348,6 @@ TimingArcSet::isRisingFallingEdge() const return nullptr; } -void -TimingArcSet::setIsDisabledConstraint(bool is_disabled) -{ - is_disabled_constraint_ = is_disabled; -} - float TimingArcSet::ocvArcDepth() const { @@ -366,11 +359,11 @@ TimingArcSet::ocvArcDepth() const LibertyCell *cell = from_->libertyCell(); depth = cell->ocvArcDepth(); if (depth != 0.0) - return depth; + return depth; else { - depth = cell->libertyLibrary()->ocvArcDepth(); - if (depth != 0.0) - return depth; + depth = cell->libertyLibrary()->ocvArcDepth(); + if (depth != 0.0) + return depth; } } } @@ -380,7 +373,7 @@ TimingArcSet::ocvArcDepth() const bool TimingArcSet::equiv(const TimingArcSet *set1, - const TimingArcSet *set2) + const TimingArcSet *set2) { return LibertyPort::equiv(set1->from(), set2->from()) && LibertyPort::equiv(set1->to(), set2->to()) @@ -394,7 +387,7 @@ TimingArcSet::equiv(const TimingArcSet *set1, static bool timingArcsEquiv(const TimingArcSet *arc_set1, - const TimingArcSet *arc_set2) + const TimingArcSet *arc_set2) { const TimingArcSeq &arcs1 = arc_set1->arcs(); const TimingArcSeq &arcs2 = arc_set2->arcs(); @@ -414,14 +407,14 @@ timingArcsEquiv(const TimingArcSet *arc_set1, bool TimingArcSet::less(const TimingArcSet *set1, - const TimingArcSet *set2) + const TimingArcSet *set2) { return timingArcSetLess(set1, set2); } bool timingArcSetLess(const TimingArcSet *set1, - const TimingArcSet *set2) + const TimingArcSet *set2) { LibertyPort *from1 = set1->from(); LibertyPort *from2 = set2->from(); @@ -432,45 +425,45 @@ timingArcSetLess(const TimingArcSet *set1, const TimingRole *role1 = set1->role(); const TimingRole *role2 = set2->role(); if (role1 == role2) { - const FuncExpr *cond1 = set1->cond(); - const FuncExpr *cond2 = set2->cond(); - if (FuncExpr::equiv(cond1, cond2)) { - const char *sdf_cond1 = set1->sdfCond(); - const char *sdf_cond2 = set2->sdfCond(); - if (stringEqIf(sdf_cond1, sdf_cond2)) { - const char *sdf_cond_start1 = set1->sdfCondStart(); - const char *sdf_cond_start2 = set2->sdfCondStart(); - if (stringEqIf(sdf_cond_start1, sdf_cond_start2)) { - const char *sdf_cond_end1 = set1->sdfCondEnd(); - const char *sdf_cond_end2 = set2->sdfCondEnd(); - if (stringEqIf(sdf_cond_end1, sdf_cond_end2)) { - const char *mode_name1 = set1->modeName(); - const char *mode_name2 = set2->modeName(); - if (stringEqIf(mode_name1, mode_name2)) { - const char *mode_value1 = set1->modeValue(); - const char *mode_value2 = set2->modeValue(); - if (stringEqIf(mode_value1, mode_value2)) - return timingArcsLess(set1, set2); - else - return stringLessIf(mode_value1, mode_value2); - } - else - return stringLessIf(mode_name1, mode_name2); - } - else - return stringLessIf(sdf_cond_end1, sdf_cond_end2); - } - else - return stringLessIf(sdf_cond_start1, sdf_cond_start2); - } - else - return stringLessIf(sdf_cond1, sdf_cond2); - } - else - return FuncExpr::less(cond1, cond2); + const FuncExpr *cond1 = set1->cond(); + const FuncExpr *cond2 = set2->cond(); + if (FuncExpr::equiv(cond1, cond2)) { + const char *sdf_cond1 = set1->sdfCond(); + const char *sdf_cond2 = set2->sdfCond(); + if (stringEqIf(sdf_cond1, sdf_cond2)) { + const char *sdf_cond_start1 = set1->sdfCondStart(); + const char *sdf_cond_start2 = set2->sdfCondStart(); + if (stringEqIf(sdf_cond_start1, sdf_cond_start2)) { + const char *sdf_cond_end1 = set1->sdfCondEnd(); + const char *sdf_cond_end2 = set2->sdfCondEnd(); + if (stringEqIf(sdf_cond_end1, sdf_cond_end2)) { + const char *mode_name1 = set1->modeName(); + const char *mode_name2 = set2->modeName(); + if (stringEqIf(mode_name1, mode_name2)) { + const char *mode_value1 = set1->modeValue(); + const char *mode_value2 = set2->modeValue(); + if (stringEqIf(mode_value1, mode_value2)) + return timingArcsLess(set1, set2); + else + return stringLessIf(mode_value1, mode_value2); + } + else + return stringLessIf(mode_name1, mode_name2); + } + else + return stringLessIf(sdf_cond_end1, sdf_cond_end2); + } + else + return stringLessIf(sdf_cond_start1, sdf_cond_start2); + } + else + return stringLessIf(sdf_cond1, sdf_cond2); + } + else + return FuncExpr::less(cond1, cond2); } else - return TimingRole::less(role1, role2); + return TimingRole::less(role1, role2); } else return LibertyPort::less(to1, to2); @@ -481,7 +474,7 @@ timingArcSetLess(const TimingArcSet *set1, static bool timingArcsLess(const TimingArcSet *arc_set1, - const TimingArcSet *arc_set2) + const TimingArcSet *arc_set2) { const TimingArcSeq &arcs1 = arc_set1->arcs(); const TimingArcSeq &arcs2 = arc_set2->arcs(); @@ -527,9 +520,9 @@ TimingArcSet::init() wire_timing_arc_attrs_ = make_shared(TimingSense::positive_unate); wire_timing_arc_set_ = new TimingArcSet(TimingRole::wire(), wire_timing_arc_attrs_); new TimingArc(wire_timing_arc_set_, Transition::rise(), - Transition::rise(), nullptr); + Transition::rise(), nullptr); new TimingArc(wire_timing_arc_set_, Transition::fall(), - Transition::fall(), nullptr); + Transition::fall(), nullptr); } void @@ -543,9 +536,9 @@ TimingArcSet::destroy() //////////////////////////////////////////////////////////////// TimingArc::TimingArc(TimingArcSet *set, - const Transition *from_rf, - const Transition *to_rf, - TimingModel *model) : + const Transition *from_rf, + const Transition *to_rf, + TimingModel *model) : set_(set), from_rf_(from_rf), to_rf_(to_rf), @@ -585,9 +578,10 @@ TimingArc::to_string() const } GateTimingModel * -TimingArc::gateModel(const DcalcAnalysisPt *dcalc_ap) const +TimingArc::gateModel(const Scene *scene, + const MinMax *min_max) const { - return dynamic_cast(model(dcalc_ap)); + return dynamic_cast(model(scene, min_max)); } GateTableModel * @@ -597,34 +591,38 @@ TimingArc::gateTableModel() const } GateTableModel * -TimingArc::gateTableModel(const DcalcAnalysisPt *dcalc_ap) const +TimingArc::gateTableModel(const Scene *scene, + const MinMax *min_max) const { - return dynamic_cast(model(dcalc_ap)); + return dynamic_cast(model(scene, min_max)); } CheckTimingModel * -TimingArc::checkModel(const DcalcAnalysisPt *dcalc_ap) const +TimingArc::checkModel(const Scene *scene, + const MinMax *min_max) const { - return dynamic_cast(model(dcalc_ap)); + return dynamic_cast(model(scene, min_max)); } TimingModel * -TimingArc::model(const DcalcAnalysisPt *dcalc_ap) const +TimingArc::model(const Scene *scene, + const MinMax *min_max) const { - const TimingArc *corner_arc = cornerArc(dcalc_ap->libertyIndex()); - ScaledTimingModelMap *scaled_models = corner_arc->scaled_models_; + const TimingArc *scene_arc = sceneArc(scene->libertyIndex(min_max)); + ScaledTimingModelMap *scaled_models = scene_arc->scaled_models_; if (scaled_models) { - const OperatingConditions *op_cond = dcalc_ap->operatingConditions(); - TimingModel *scaled_model = scaled_models->findKey(op_cond); + const OperatingConditions *op_cond = + scene->sdc()->operatingConditions(min_max); + TimingModel *scaled_model = findKey(*scaled_models, op_cond); if (scaled_model) return scaled_model; } - return corner_arc->model(); + return scene_arc->model(); } void TimingArc::addScaledModel(const OperatingConditions *op_cond, - TimingModel *scaled_model) + TimingModel *scaled_model) { if (scaled_models_ == nullptr) scaled_models_ = new ScaledTimingModelMap; @@ -633,7 +631,7 @@ TimingArc::addScaledModel(const OperatingConditions *op_cond, bool TimingArc::equiv(const TimingArc *arc1, - const TimingArc *arc2) + const TimingArc *arc2) { return arc1->fromEdge() == arc2->fromEdge() && arc1->toEdge() == arc2->toEdge(); @@ -646,23 +644,23 @@ TimingArc::setIndex(unsigned index) } const TimingArc * -TimingArc::cornerArc(int ap_index) const +TimingArc::sceneArc(int ap_index) const { - if (ap_index < static_cast(corner_arcs_.size())) { - TimingArc *corner_arc = corner_arcs_[ap_index]; - if (corner_arc) - return corner_arc; + if (ap_index < static_cast(scene_arcs_.size())) { + TimingArc *scene_arc = scene_arcs_[ap_index]; + if (scene_arc) + return scene_arc; } return this; } void -TimingArc::setCornerArc(TimingArc *corner_arc, - int ap_index) +TimingArc::setSceneArc(TimingArc *scene_arc, + int ap_index) { - if (ap_index >= static_cast(corner_arcs_.size())) - corner_arcs_.resize(ap_index + 1); - corner_arcs_[ap_index] = corner_arc; + if (ap_index >= static_cast(scene_arcs_.size())) + scene_arcs_.resize(ap_index + 1); + scene_arcs_[ap_index] = scene_arc; } //////////////////////////////////////////////////////////////// @@ -673,12 +671,12 @@ TimingArc::sense() const if ((from_rf_ == Transition::rise() && to_rf_ == Transition::rise()) || (from_rf_ == Transition::fall() - && to_rf_ == Transition::fall())) + && to_rf_ == Transition::fall())) return TimingSense::positive_unate; else if ((from_rf_ == Transition::rise() && to_rf_ == Transition::fall()) || (from_rf_ == Transition::fall() - && to_rf_ == Transition::rise())) + && to_rf_ == Transition::rise())) return TimingSense::negative_unate; else return TimingSense::non_unate; diff --git a/liberty/TimingRole.cc b/liberty/TimingRole.cc index 819ba929..1839e52f 100644 --- a/liberty/TimingRole.cc +++ b/liberty/TimingRole.cc @@ -90,12 +90,12 @@ const TimingRole TimingRole::clock_tree_path_max_("max clock tree path", false, false, MinMax::max(), nullptr, 28); TimingRole::TimingRole(const char *name, - bool is_sdf_iopath, - bool is_timing_check, - bool is_non_seq_check, - const MinMax *path_min_max, - const TimingRole *generic_role, - int index) : + bool is_sdf_iopath, + bool is_timing_check, + bool is_non_seq_check, + const MinMax *path_min_max, + const TimingRole *generic_role, + int index) : name_(name), is_timing_check_(is_timing_check), is_sdf_iopath_(is_sdf_iopath), @@ -173,7 +173,7 @@ TimingRole::isTimingCheckBetween() const bool TimingRole::less(const TimingRole *role1, - const TimingRole *role2) + const TimingRole *role2) { return role1->index() < role2->index(); } diff --git a/liberty/Units.cc b/liberty/Units.cc index 8dcbb4f0..97e33309 100644 --- a/liberty/Units.cc +++ b/liberty/Units.cc @@ -44,8 +44,8 @@ Unit::Unit(const char *suffix) : } Unit::Unit(float scale, - const char *suffix, - int digits) : + const char *suffix, + int digits) : scale_(scale), suffix_(suffix), digits_(digits) @@ -172,7 +172,7 @@ Unit::asString(double value) const const char * Unit::asString(float value, - int digits) const + int digits) const { // Special case INF because it blows up otherwise. if (abs(value) >= INF * .1) diff --git a/liberty/Wireload.cc b/liberty/Wireload.cc index 9c8ea3e5..e85ee603 100644 --- a/liberty/Wireload.cc +++ b/liberty/Wireload.cc @@ -32,7 +32,7 @@ namespace sta { Wireload::Wireload(const char *name, - LibertyLibrary *library) : + LibertyLibrary *library) : name_(stringCopy(name)), library_(library), area_(0.0F), @@ -43,11 +43,11 @@ Wireload::Wireload(const char *name, } Wireload::Wireload(const char *name, - LibertyLibrary *library, - float area, - float resistance, - float capacitance, - float slope) : + LibertyLibrary *library, + float area, + float resistance, + float capacitance, + float slope) : name_(stringCopy(name)), library_(library), area_(area), @@ -59,7 +59,7 @@ Wireload::Wireload(const char *name, Wireload::~Wireload() { - fanout_lengths_.deleteContents(); + deleteContents(fanout_lengths_); stringDelete(name_); } @@ -90,7 +90,7 @@ Wireload::setSlope(float slope) struct FanoutLess { bool operator()(FanoutLength *fanout1, - FanoutLength *fanout2) const + FanoutLength *fanout2) const { return fanout1->first < fanout2->first; } @@ -98,7 +98,7 @@ struct FanoutLess void Wireload::addFanoutLength(float fanout, - float length) + float length) { FanoutLength *fanout_length = new FanoutLength(fanout, length); fanout_lengths_.push_back(fanout_length); @@ -110,9 +110,9 @@ Wireload::addFanoutLength(float fanout, void Wireload::findWireload(float fanout, - const OperatingConditions *op_cond, - float &cap, - float &res) const + const OperatingConditions *op_cond, + float &cap, + float &res) const { size_t size = fanout_lengths_.size(); float length; @@ -126,7 +126,7 @@ Wireload::findWireload(float fanout, // Extrapolate from lowest fanout entry. length = fanout_lengths_[0]->second - (fanout0 - fanout) * slope_; if (length < 0) - length = 0; + length = 0; } else if (fanout == fanout0) length = fanout_lengths_[0]->second; @@ -138,11 +138,11 @@ Wireload::findWireload(float fanout, int lower = -1; int upper = size; while (upper - lower > 1) { - int mid = (upper + lower) >> 1; - if (fanout >= fanout_lengths_[mid]->first) - lower = mid; - else - upper = mid; + int mid = (upper + lower) >> 1; + if (fanout >= fanout_lengths_[mid]->first) + lower = mid; + else + upper = mid; } // Interpolate between lower and lower+1 entries. float fanout1 = fanout_lengths_[lower]->first; @@ -165,8 +165,8 @@ class WireloadForArea { public: WireloadForArea(float min_area, - float max_area, - const Wireload *wireload); + float max_area, + const Wireload *wireload); float minArea() const { return min_area_; } float maxArea() const { return max_area_; } const Wireload *wireload() const { return wireload_; } @@ -178,8 +178,8 @@ private: }; WireloadForArea::WireloadForArea(float min_area, - float max_area, - const Wireload *wireload) : + float max_area, + const Wireload *wireload) : min_area_(min_area), max_area_(max_area), wireload_(wireload) @@ -193,14 +193,14 @@ WireloadSelection::WireloadSelection(const char *name) : WireloadSelection::~WireloadSelection() { - wireloads_.deleteContents(); + deleteContents(wireloads_); stringDelete(name_); } struct WireloadForAreaMinLess { bool operator()(WireloadForArea *wireload1, - WireloadForArea *wireload2) const + WireloadForArea *wireload2) const { return wireload1->minArea() < wireload2->minArea(); } @@ -208,11 +208,11 @@ struct WireloadForAreaMinLess void WireloadSelection::addWireloadFromArea(float min_area, - float max_area, - const Wireload *wireload) + float max_area, + const Wireload *wireload) { WireloadForArea *wireload_area = new WireloadForArea(min_area, max_area, - wireload); + wireload); wireloads_.push_back(wireload_area); // Keep wireloads sorted by area for lookup. if (wireloads_.size() > 1 diff --git a/network/ConcreteLibrary.cc b/network/ConcreteLibrary.cc index 2dedc9f4..0ecba436 100644 --- a/network/ConcreteLibrary.cc +++ b/network/ConcreteLibrary.cc @@ -27,6 +27,7 @@ #include #include +#include "ContainerHelpers.hh" #include "PatternMatch.hh" #include "PortDirection.hh" #include "ParseBus.hh" @@ -44,8 +45,8 @@ using std::swap; static constexpr char escape_ = '\\'; ConcreteLibrary::ConcreteLibrary(const char *name, - const char *filename, - bool is_liberty) : + const char *filename, + bool is_liberty) : name_(name), id_(ConcreteNetwork::nextObjectId()), filename_(filename ? filename : ""), @@ -57,13 +58,13 @@ ConcreteLibrary::ConcreteLibrary(const char *name, ConcreteLibrary::~ConcreteLibrary() { - cell_map_.deleteContents(); + deleteContents(cell_map_); } ConcreteCell * ConcreteLibrary::makeCell(const char *name, - bool is_leaf, - const char *filename) + bool is_leaf, + const char *filename) { ConcreteCell *cell = new ConcreteCell(name, filename, is_leaf, this); addCell(cell); @@ -78,7 +79,7 @@ ConcreteLibrary::addCell(ConcreteCell *cell) void ConcreteLibrary::renameCell(ConcreteCell *cell, - const char *cell_name) + const char *cell_name) { cell_map_.erase(cell->name()); cell_map_[cell_name] = cell; @@ -100,17 +101,15 @@ ConcreteLibrary::cellIterator() const ConcreteCell * ConcreteLibrary::findCell(const char *name) const { - return cell_map_.findKey(name); + return findKey(cell_map_, name); } CellSeq ConcreteLibrary::findCellsMatching(const PatternMatch *pattern) const { CellSeq matches; - ConcreteLibraryCellIterator cell_iter=ConcreteLibraryCellIterator(cell_map_); - while (cell_iter.hasNext()) { - ConcreteCell *cell = cell_iter.next(); - if (pattern->match(cell->name())) + for (auto [name, cell] : cell_map_) { + if (pattern->match(name)) matches.push_back(reinterpret_cast(cell)); } return matches; @@ -118,7 +117,7 @@ ConcreteLibrary::findCellsMatching(const PatternMatch *pattern) const void ConcreteLibrary::setBusBrkts(char left, - char right) + char right) { bus_brkt_left_ = left; bus_brkt_right_ = right; @@ -127,8 +126,8 @@ ConcreteLibrary::setBusBrkts(char left, //////////////////////////////////////////////////////////////// ConcreteCell::ConcreteCell(const char *name, - const char *filename, - bool is_leaf, + const char *filename, + bool is_leaf, ConcreteLibrary *library) : name_(name), id_(ConcreteNetwork::nextObjectId()), @@ -143,7 +142,7 @@ ConcreteCell::ConcreteCell(const char *name, ConcreteCell::~ConcreteCell() { - ports_.deleteContents(); + deleteContents(ports_); } void @@ -175,7 +174,7 @@ ConcreteCell::makePort(const char *name) ConcretePort * ConcreteCell::makeBundlePort(const char *name, - ConcretePortSeq *members) + ConcretePortSeq *members) { ConcretePort *port = new ConcretePort(name, false, -1, -1, true, members, this); addPort(port); @@ -186,11 +185,11 @@ ConcreteCell::makeBundlePort(const char *name, ConcretePort * ConcreteCell::makeBusPort(const char *name, - int from_index, - int to_index) + int from_index, + int to_index) { ConcretePort *port = new ConcretePort(name, true, from_index, to_index, - false, new ConcretePortSeq, this); + false, new ConcretePortSeq, this); addPort(port); makeBusPortBits(port, name, from_index, to_index); return port; @@ -198,21 +197,21 @@ ConcreteCell::makeBusPort(const char *name, ConcretePort * ConcreteCell::makeBusPort(const char *name, - int from_index, - int to_index, - ConcretePortSeq *members) + int from_index, + int to_index, + ConcretePortSeq *members) { ConcretePort *port = new ConcretePort(name, true, from_index, to_index, - false, members, this); + false, members, this); addPort(port); return port; } void ConcreteCell::makeBusPortBits(ConcretePort *bus_port, - const char *name, - int from_index, - int to_index) + const char *name, + int from_index, + int to_index) { if (from_index < to_index) { for (int index = from_index; index <= to_index; index++) @@ -226,15 +225,15 @@ ConcreteCell::makeBusPortBits(ConcretePort *bus_port, void ConcreteCell::makeBusPortBit(ConcretePort *bus_port, - const char *bus_name, - int bit_index) + const char *bus_name, + int bit_index) { string bit_name; stringPrint(bit_name, "%s%c%d%c", - bus_name, - library_->busBrktLeft(), - bit_index, - library_->busBrktRight()); + bus_name, + library_->busBrktLeft(), + bit_index, + library_->busBrktRight()); ConcretePort *port = makePort(bit_name.c_str(), bit_index); bus_port->addPortBit(port); addPortBit(port); @@ -242,10 +241,10 @@ ConcreteCell::makeBusPortBit(ConcretePort *bus_port, ConcretePort * ConcreteCell::makePort(const char *bit_name, - int bit_index) + int bit_index) { ConcretePort *port = new ConcretePort(bit_name, false, bit_index, - bit_index, false, nullptr, this); + bit_index, false, nullptr, this); addPortBit(port); return port; } @@ -291,7 +290,7 @@ ConcreteCell::getAttribute(const string &key) const ConcretePort * ConcreteCell::findPort(const char *name) const { - return port_map_.findKey(name); + return findKey(port_map_, name); } size_t @@ -358,7 +357,7 @@ BusPort::addBusBit(ConcretePort *port, void ConcreteCell::groupBusPorts(const char bus_brkt_left, - const char bus_brkt_right, + const char bus_brkt_right, std::function port_msb_first) { const char bus_brkts_left[2]{bus_brkt_left, '\0'}; @@ -376,11 +375,11 @@ ConcreteCell::groupBusPorts(const char bus_brkt_left, string bus_name; int index; parseBusName(port_name, bus_brkts_left, bus_brkts_right, escape_, - is_bus, bus_name, index); + is_bus, bus_name, index); if (is_bus) { if (!port->isBusBit()) { BusPort &bus_port = bus_map[bus_name]; - bus_port.addBusBit(port, index); + bus_port.addBusBit(port, index); port->setBusBitIndex(index); bus_port.setDirection(port->direction()); } @@ -412,11 +411,11 @@ ConcreteCell::groupBusPorts(const char bus_brkt_left, //////////////////////////////////////////////////////////////// ConcretePort::ConcretePort(const char *name, - bool is_bus, - int from_index, - int to_index, - bool is_bundle, - ConcretePortSeq *member_ports, + bool is_bus, + int from_index, + int to_index, + bool is_bundle, + ConcretePortSeq *member_ports, ConcreteCell *cell) : name_(name), id_(ConcreteNetwork::nextObjectId()), @@ -439,7 +438,7 @@ ConcretePort::~ConcretePort() // The member ports of a bus are owned by the bus port. // The member ports of a bundle are NOT owned by the bus port. if (is_bus_) - member_ports_->deleteContents(); + deleteContents(member_ports_); delete member_ports_; } @@ -473,11 +472,11 @@ ConcretePort::busName() const if (is_bus_) { ConcreteLibrary *lib = cell_->library(); return stringPrintTmp("%s%c%d:%d%c", - name(), - lib->busBrktLeft(), - from_index_, - to_index_, - lib->busBrktRight()); + name(), + lib->busBrktLeft(), + from_index_, + to_index_, + lib->busBrktRight()); } else return name(); @@ -548,8 +547,8 @@ ConcretePort::findBusBit(int index) const && index >= from_index_) return (*member_ports_)[index - from_index_]; else if (from_index_ >= to_index_ - && index >= to_index_ - && index <= from_index_) + && index >= to_index_ + && index <= from_index_) return (*member_ports_)[from_index_ - index]; else return nullptr; @@ -559,11 +558,11 @@ bool ConcretePort::busIndexInRange(int index) const { return (from_index_ <= to_index_ - && index <= to_index_ - && index >= from_index_) + && index <= to_index_ + && index >= from_index_) || (from_index_ > to_index_ - && index >= to_index_ - && index <= from_index_); + && index >= to_index_ + && index <= from_index_); } bool @@ -580,9 +579,9 @@ ConcretePort::memberIterator() const //////////////////////////////////////////////////////////////// -ConcreteCellPortBitIterator::ConcreteCellPortBitIterator(const ConcreteCell* - cell) : - port_iter_(cell->ports_), +ConcreteCellPortBitIterator::ConcreteCellPortBitIterator(const ConcreteCell* cell) : + ports_(cell->ports_), + port_iter_(ports_.begin()), member_iter_(nullptr), next_(nullptr) { @@ -616,8 +615,8 @@ ConcreteCellPortBitIterator::findNext() member_iter_ = nullptr; } } - while (port_iter_.hasNext()) { - ConcretePort *next = port_iter_.next(); + while (port_iter_ != ports_.end()) { + ConcretePort *next = *port_iter_++; if (next->isBus()) { member_iter_ = next->memberIterator(); next_ = member_iter_->next(); diff --git a/network/ConcreteNetwork.cc b/network/ConcreteNetwork.cc index d165e9f3..6f4b2632 100644 --- a/network/ConcreteNetwork.cc +++ b/network/ConcreteNetwork.cc @@ -24,6 +24,8 @@ #include "ConcreteNetwork.hh" +#include + #include "PatternMatch.hh" #include "Report.hh" #include "Liberty.hh" @@ -37,17 +39,17 @@ using std::string; static void makeChildNetwork(Instance *proto, - Instance *parent, - ConcreteBindingTbl *parent_bindings, - NetworkReader *network); + Instance *parent, + ConcreteBindingTbl *parent_bindings, + NetworkReader *network); static void makeClonePins(Instance *proto, - Instance *clone, - Instance *clone_view, - ConcreteBindingTbl *bindings, - Instance *parent, - ConcreteBindingTbl *parent_bindings, - NetworkReader *network); + Instance *clone, + Instance *clone_view, + ConcreteBindingTbl *bindings, + Instance *parent, + ConcreteBindingTbl *parent_bindings, + NetworkReader *network); //////////////////////////////////////////////////////////////// @@ -61,49 +63,56 @@ makeConcreteNetwork() class ConcreteInstanceChildIterator : public InstanceChildIterator { public: - explicit ConcreteInstanceChildIterator(ConcreteInstanceChildMap *map); + ConcreteInstanceChildIterator(ConcreteInstanceChildMap *map); bool hasNext(); Instance *next(); private: - ConcreteInstanceChildMap::ConstIterator iter_; + ConcreteInstanceChildMap *map_; + ConcreteInstanceChildMap::const_iterator iter_; }; ConcreteInstanceChildIterator:: ConcreteInstanceChildIterator(ConcreteInstanceChildMap *map) : - iter_(map) + map_(map) { + if (map_) + iter_ = map_->begin(); } bool ConcreteInstanceChildIterator::hasNext() { - return iter_.hasNext(); + return map_ && iter_ != map_->end(); } Instance * ConcreteInstanceChildIterator::next() { - return reinterpret_cast(iter_.next()); + Instance *next = reinterpret_cast(iter_->second); + iter_++; + return next; } class ConcreteInstanceNetIterator : public InstanceNetIterator { public: - explicit ConcreteInstanceNetIterator(ConcreteInstanceNetMap *nets); + ConcreteInstanceNetIterator(ConcreteInstanceNetMap *nets); bool hasNext(); Net *next(); private: void findNext(); - ConcreteInstanceNetMap::Iterator iter_; + ConcreteInstanceNetMap *nets_; + ConcreteInstanceNetMap::iterator iter_; ConcreteNet *next_; }; ConcreteInstanceNetIterator:: ConcreteInstanceNetIterator(ConcreteInstanceNetMap *nets): - iter_(nets), + nets_(nets), + iter_(nets->begin()), next_(nullptr) { findNext(); @@ -119,8 +128,9 @@ ConcreteInstanceNetIterator::hasNext() void ConcreteInstanceNetIterator::findNext() { - while (iter_.hasNext()) { - next_ = iter_.next(); + while (iter_ != nets_->end()) { + next_ = iter_->second; + iter_++; if (next_->mergedInto() == nullptr) return; } @@ -141,7 +151,7 @@ class ConcreteInstancePinIterator : public InstancePinIterator { public: ConcreteInstancePinIterator(const ConcreteInstance *inst, - int pin_count); + int pin_count); bool hasNext(); Pin *next(); @@ -156,7 +166,7 @@ private: ConcreteInstancePinIterator:: ConcreteInstancePinIterator(const ConcreteInstance *inst, - int pin_count) : + int pin_count) : pins_(inst->pins_), pin_count_(pin_count), pin_index_(0) @@ -195,7 +205,7 @@ ConcreteInstancePinIterator::findNext() class ConcreteNetPinIterator : public NetPinIterator { public: - explicit ConcreteNetPinIterator(const ConcreteNet *net); + ConcreteNetPinIterator(const ConcreteNet *net); bool hasNext(); Pin *next(); @@ -227,7 +237,7 @@ ConcreteNetPinIterator::next() class ConcreteNetTermIterator : public NetTermIterator { public: - explicit ConcreteNetTermIterator(const ConcreteNet *net); + ConcreteNetTermIterator(const ConcreteNet *net); bool hasNext(); Term *next(); @@ -276,7 +286,7 @@ ConcreteNetwork::clear() { deleteTopInstance(); deleteCellNetworkViews(); - library_seq_.deleteContentsClear(); + deleteContents(library_seq_); library_map_.clear(); Network::clear(); } @@ -293,9 +303,7 @@ ConcreteNetwork::deleteTopInstance() void ConcreteNetwork::deleteCellNetworkViews() { - CellNetworkViewMap::Iterator view_iter(cell_network_view_map_); - while (view_iter.hasNext()) { - Instance *view = view_iter.next(); + for (auto [cell, view] : cell_network_view_map_) { if (view) deleteInstance(view); } @@ -313,29 +321,31 @@ ConcreteNetwork::topInstance() const class ConcreteLibraryIterator1 : public Iterator { public: - explicit ConcreteLibraryIterator1(const ConcreteLibrarySeq &lib_seq_); + ConcreteLibraryIterator1(const ConcreteLibrarySeq &libs); virtual bool hasNext(); virtual Library *next(); private: - ConcreteLibraryIterator iter_; + const ConcreteLibrarySeq &libs_; + ConcreteLibrarySeq::const_iterator iter_; }; -ConcreteLibraryIterator1::ConcreteLibraryIterator1(const ConcreteLibrarySeq &lib_seq_): - iter_(lib_seq_) +ConcreteLibraryIterator1::ConcreteLibraryIterator1(const ConcreteLibrarySeq &libs): + libs_(libs), + iter_(libs.begin()) { } bool ConcreteLibraryIterator1::hasNext() { - return iter_.hasNext(); + return iter_ != libs_.end(); } Library * ConcreteLibraryIterator1::next() { - return reinterpret_cast(iter_.next()); + return reinterpret_cast(*iter_++); } LibraryIterator * @@ -349,7 +359,7 @@ ConcreteNetwork::libraryIterator() const class ConcreteLibertyLibraryIterator : public Iterator { public: - explicit ConcreteLibertyLibraryIterator(const ConcreteNetwork *network); + ConcreteLibertyLibraryIterator(const ConcreteNetwork *network); virtual ~ConcreteLibertyLibraryIterator(); virtual bool hasNext(); virtual LibertyLibrary *next(); @@ -357,13 +367,15 @@ public: private: void findNext(); - ConcreteLibrarySeq::ConstIterator iter_; + const ConcreteLibrarySeq &libs_; + ConcreteLibrarySeq::const_iterator iter_; LibertyLibrary *next_; }; ConcreteLibertyLibraryIterator:: ConcreteLibertyLibraryIterator(const ConcreteNetwork *network): - iter_(network->library_seq_), + libs_(network->library_seq_), + iter_(libs_.begin()), next_(nullptr) { findNext(); @@ -391,13 +403,13 @@ void ConcreteLibertyLibraryIterator::findNext() { next_ = nullptr; - while (iter_.hasNext()) { - ConcreteLibrary *lib = iter_.next(); + while (iter_ != libs_.end()) { + ConcreteLibrary *lib = *iter_++; if (lib->isLiberty()) { LibertyLibrary *liberty = static_cast(lib); if (liberty) { - next_ = liberty; - break; + next_ = liberty; + break; } } } @@ -413,7 +425,7 @@ ConcreteNetwork::libertyLibraryIterator() const Library * ConcreteNetwork::makeLibrary(const char *name, - const char *filename) + const char *filename) { ConcreteLibrary *library = new ConcreteLibrary(name, filename, false); addLibrary(library); @@ -422,7 +434,7 @@ ConcreteNetwork::makeLibrary(const char *name, LibertyLibrary * ConcreteNetwork::makeLibertyLibrary(const char *name, - const char *filename) + const char *filename) { LibertyLibrary *library = new LibertyLibrary(name, filename); addLibrary(library); @@ -439,7 +451,7 @@ ConcreteNetwork::addLibrary(ConcreteLibrary *library) Library * ConcreteNetwork::findLibrary(const char *name) { - return reinterpret_cast(library_map_.findKey(name)); + return reinterpret_cast(findKey(library_map_, name)); } void @@ -447,7 +459,7 @@ ConcreteNetwork::deleteLibrary(Library *library) { ConcreteLibrary *clib = reinterpret_cast(library); library_map_.erase(clib->name()); - library_seq_.eraseObject(clib); + library_seq_.erase(std::find(library_seq_.begin(), library_seq_.end(), clib)); delete clib; } @@ -470,16 +482,16 @@ ConcreteNetwork::id(const Library *library) const LibertyLibrary * ConcreteNetwork::findLiberty(const char *name) { - ConcreteLibrary *lib = library_map_.findKey(name); + ConcreteLibrary *lib = findKey(library_map_, name); if (lib) { if (lib->isLiberty()) return static_cast(lib); // Potential name conflict else { for (ConcreteLibrary *lib : library_seq_) { - if (stringEq(lib->name(), name) - && lib->isLiberty()) - return static_cast(lib); + if (stringEq(lib->name(), name) + && lib->isLiberty()) + return static_cast(lib); } } } @@ -488,9 +500,9 @@ ConcreteNetwork::findLiberty(const char *name) Cell * ConcreteNetwork::makeCell(Library *library, - const char *name, - bool is_leaf, - const char *filename) + const char *name, + bool is_leaf, + const char *filename) { ConcreteLibrary *clib = reinterpret_cast(library); return reinterpret_cast(clib->makeCell(name, is_leaf, filename)); @@ -498,7 +510,7 @@ ConcreteNetwork::makeCell(Library *library, Cell * ConcreteNetwork::findCell(const Library *library, - const char *name) const + const char *name) const { const ConcreteLibrary *clib = reinterpret_cast(library); @@ -508,9 +520,7 @@ ConcreteNetwork::findCell(const Library *library, Cell * ConcreteNetwork::findAnyCell(const char *name) { - ConcreteLibrarySeq::Iterator lib_iter(library_seq_); - while (lib_iter.hasNext()) { - ConcreteLibrary *lib = lib_iter.next(); + for (ConcreteLibrary *lib : library_seq_) { ConcreteCell *cell = lib->findCell(name); if (cell) return reinterpret_cast(cell); @@ -520,7 +530,7 @@ ConcreteNetwork::findAnyCell(const char *name) CellSeq ConcreteNetwork::findCellsMatching(const Library *library, - const PatternMatch *pattern) const + const PatternMatch *pattern) const { const ConcreteLibrary *clib = reinterpret_cast(library); @@ -553,7 +563,7 @@ ConcreteNetwork::id(const Cell *cell) const void ConcreteNetwork::setName(Cell *cell, - const char *name) + const char *name) { ConcreteCell *ccell = reinterpret_cast(cell); ccell->setName(name); @@ -561,7 +571,7 @@ ConcreteNetwork::setName(Cell *cell, void ConcreteNetwork::setIsLeaf(Cell *cell, - bool is_leaf) + bool is_leaf) { ConcreteCell *ccell = reinterpret_cast(cell); ccell->setIsLeaf(is_leaf); @@ -633,7 +643,7 @@ ConcreteNetwork::attributeMap(const Cell *cell) const Port * ConcreteNetwork::findPort(const Cell *cell, - const char *name) const + const char *name) const { const ConcreteCell *ccell = reinterpret_cast(cell); return reinterpret_cast(ccell->findPort(name)); @@ -648,7 +658,7 @@ ConcreteNetwork::isLeaf(const Cell *cell) const Port * ConcreteNetwork::makePort(Cell *cell, - const char *name) + const char *name) { ConcreteCell *ccell = reinterpret_cast(cell); ConcretePort *port = ccell->makePort(name); @@ -657,9 +667,9 @@ ConcreteNetwork::makePort(Cell *cell, Port * ConcreteNetwork::makeBusPort(Cell *cell, - const char *name, - int from_index, - int to_index) + const char *name, + int from_index, + int to_index) { ConcreteCell *ccell = reinterpret_cast(cell); ConcretePort *port = ccell->makeBusPort(name, from_index, to_index); @@ -679,8 +689,8 @@ ConcreteNetwork::groupBusPorts(Cell *cell, Port * ConcreteNetwork::makeBundlePort(Cell *cell, - const char *name, - PortSeq *members) + const char *name, + PortSeq *members) { ConcreteCell *ccell = reinterpret_cast(cell); ConcretePortSeq *cmembers = reinterpret_cast(members); @@ -690,7 +700,7 @@ ConcreteNetwork::makeBundlePort(Cell *cell, void ConcreteNetwork::setDirection(Port *port, - PortDirection *dir) + PortDirection *dir) { ConcretePort *cport = reinterpret_cast(port); cport->setDirection(dir); @@ -707,7 +717,7 @@ ConcreteNetwork::nextObjectId() class ConcreteCellPortIterator1 : public CellPortIterator { public: - explicit ConcreteCellPortIterator1(const ConcreteCell *cell); + ConcreteCellPortIterator1(const ConcreteCell *cell); ~ConcreteCellPortIterator1(); virtual bool hasNext() { return iter_->hasNext(); } virtual Port *next(); @@ -744,7 +754,7 @@ ConcreteNetwork::portIterator(const Cell *cell) const class ConcreteCellPortBitIterator1 : public CellPortIterator { public: - explicit ConcreteCellPortBitIterator1(const ConcreteCell *cell); + ConcreteCellPortBitIterator1(const ConcreteCell *cell); ~ConcreteCellPortBitIterator1(); virtual bool hasNext() { return iter_->hasNext(); } virtual Port *next(); @@ -864,7 +874,7 @@ ConcreteNetwork::toIndex(const Port *port) const Port * ConcreteNetwork::findBusBit(const Port *port, - int index) const + int index) const { const ConcretePort *cport = reinterpret_cast(port); return reinterpret_cast(cport->findBusBit(index)); @@ -872,7 +882,7 @@ ConcreteNetwork::findBusBit(const Port *port, Port * ConcreteNetwork::findMember(const Port *port, - int index) const + int index) const { const ConcretePort *cport = reinterpret_cast(port); return reinterpret_cast(cport->findMember(index)); @@ -891,7 +901,7 @@ ConcreteNetwork::hasMembers(const Port *port) const class ConcretePortMemberIterator1 : public PortMemberIterator { public: - explicit ConcretePortMemberIterator1(const ConcretePort *port); + ConcretePortMemberIterator1(const ConcretePort *port); ~ConcretePortMemberIterator1(); virtual bool hasNext(); virtual Port *next(); @@ -902,7 +912,7 @@ private: }; ConcretePortMemberIterator1::ConcretePortMemberIterator1(const ConcretePort * - port) : + port) : iter_(port->memberIterator()), next_(nullptr) { @@ -997,7 +1007,7 @@ ConcreteNetwork::isLeaf(const Instance *instance) const Instance * ConcreteNetwork::findChild(const Instance *parent, - const char *name) const + const char *name) const { const ConcreteInstance *inst = reinterpret_cast(parent); @@ -1006,7 +1016,7 @@ ConcreteNetwork::findChild(const Instance *parent, Pin * ConcreteNetwork::findPin(const Instance *instance, - const char *port_name) const + const char *port_name) const { const ConcreteInstance *inst = reinterpret_cast(instance); @@ -1015,7 +1025,7 @@ ConcreteNetwork::findPin(const Instance *instance, Pin * ConcreteNetwork::findPin(const Instance *instance, - const Port *port) const + const Port *port) const { const ConcreteInstance *inst = reinterpret_cast(instance); @@ -1024,7 +1034,7 @@ ConcreteNetwork::findPin(const Instance *instance, Net * ConcreteNetwork::findNet(const Instance *instance, - const char *net_name) const + const char *net_name) const { const ConcreteInstance *inst = reinterpret_cast(instance); @@ -1033,8 +1043,8 @@ ConcreteNetwork::findNet(const Instance *instance, void ConcreteNetwork::findInstNetsMatching(const Instance *instance, - const PatternMatch *pattern, - NetSeq &matches) const + const PatternMatch *pattern, + NetSeq &matches) const { const ConcreteInstance *inst = reinterpret_cast(instance); @@ -1123,7 +1133,7 @@ ConcreteNetwork::vertexId(const Pin *pin) const void ConcreteNetwork::setVertexId(Pin *pin, - VertexId id) + VertexId id) { ConcretePin *cpin = reinterpret_cast(pin); cpin->setVertexId(id); @@ -1178,13 +1188,13 @@ ConcreteNetwork::instance(const Net *net) const bool ConcreteNetwork::isPower(const Net *net) const { - return constant_nets_[int(LogicValue::one)].hasKey(const_cast(net)); + return constant_nets_[int(LogicValue::one)].contains(const_cast(net)); } bool ConcreteNetwork::isGround(const Net *net) const { - return constant_nets_[int(LogicValue::zero)].hasKey(const_cast(net)); + return constant_nets_[int(LogicValue::zero)].contains(const_cast(net)); } NetPinIterator * @@ -1203,7 +1213,7 @@ ConcreteNetwork::termIterator(const Net *net) const void ConcreteNetwork::mergeInto(Net *net, - Net *into_net) + Net *into_net) { ConcreteNet *cnet = reinterpret_cast(net); ConcreteNet *cinto_net = reinterpret_cast(into_net); @@ -1228,8 +1238,8 @@ ConcreteInstance::cell() const Instance * ConcreteNetwork::makeInstance(Cell *cell, - const char *name, - Instance *parent) + const char *name, + Instance *parent) { ConcreteCell *ccell = reinterpret_cast(cell); return makeConcreteInstance(ccell, name, parent); @@ -1237,16 +1247,16 @@ ConcreteNetwork::makeInstance(Cell *cell, Instance * ConcreteNetwork::makeInstance(LibertyCell *cell, - const char *name, - Instance *parent) + const char *name, + Instance *parent) { return makeConcreteInstance(cell, name, parent); } Instance * ConcreteNetwork::makeConcreteInstance(ConcreteCell *cell, - const char *name, - Instance *parent) + const char *name, + Instance *parent) { ConcreteInstance *cparent = reinterpret_cast(parent); @@ -1269,7 +1279,7 @@ ConcreteNetwork::makePins(Instance *inst) void ConcreteNetwork::replaceCell(Instance *inst, - Cell *cell) + Cell *cell) { ConcreteCell *ccell = reinterpret_cast(cell); int port_count = ccell->portBitCount(); @@ -1297,20 +1307,22 @@ void ConcreteNetwork::deleteInstance(Instance *inst) { ConcreteInstance *cinst = reinterpret_cast(inst); - - // Delete nets first (so children pin deletes are not required). - ConcreteInstanceNetMap::Iterator net_iter(cinst->nets_); - while (net_iter.hasNext()) { - ConcreteNet *cnet = net_iter.next(); - Net *net = reinterpret_cast(cnet); - // Delete terminals connected to net. - NetTermIterator *term_iter = termIterator(net); - while (term_iter->hasNext()) { - ConcreteTerm *term = reinterpret_cast(term_iter->next()); - delete term; + ConcreteInstanceNetMap *nets = cinst->nets_; + if (nets) { + // Delete nets first (so children pin deletes are not required). + for (auto itr = nets->begin(); itr != nets->end(); /*no incr*/) { + auto [name, cnet] = *itr; + Net *net = reinterpret_cast(cnet); + // Delete terminals connected to net. + NetTermIterator *term_iter = termIterator(net); + while (term_iter->hasNext()) { + ConcreteTerm *term = reinterpret_cast(term_iter->next()); + delete term; + } + delete term_iter; + itr = nets->erase(itr); + deleteNet(net); } - delete term_iter; - deleteNet(net); } // Delete children. @@ -1339,8 +1351,8 @@ ConcreteNetwork::deleteInstance(Instance *inst) Pin * ConcreteNetwork::makePin(Instance *inst, - Port *port, - Net *net) + Port *port, + Net *net) { ConcreteInstance *cinst = reinterpret_cast(inst); ConcretePort *cport = reinterpret_cast(port); @@ -1354,7 +1366,7 @@ ConcreteNetwork::makePin(Instance *inst, Term * ConcreteNetwork::makeTerm(Pin *pin, - Net *net) + Net *net) { ConcretePin *cpin = reinterpret_cast(pin); ConcreteNet *cnet = reinterpret_cast(net); @@ -1367,8 +1379,8 @@ ConcreteNetwork::makeTerm(Pin *pin, Pin * ConcreteNetwork::connect(Instance *inst, - LibertyPort *port, - Net *net) + LibertyPort *port, + Net *net) { return connect(inst, reinterpret_cast(port), net); } @@ -1384,8 +1396,8 @@ ConcreteNetwork::setAttribute(Instance *inst, Pin * ConcreteNetwork::connect(Instance *inst, - Port *port, - Net *net) + Port *port, + Net *net) { ConcreteNet *cnet = reinterpret_cast(net); ConcreteInstance *cinst = reinterpret_cast(inst); @@ -1417,7 +1429,7 @@ ConcreteNetwork::connect(Instance *inst, void ConcreteNetwork::connectNetPin(ConcreteNet *cnet, - ConcretePin *cpin) + ConcretePin *cpin) { cnet->addPin(cpin); @@ -1427,9 +1439,9 @@ ConcreteNetwork::connectNetPin(ConcreteNet *cnet, if (isDriver(pin)) { if (cnet->terms_ == nullptr) { Net *net = reinterpret_cast(cnet); - PinSet *drvrs = net_drvr_pin_map_.findKey(net); + PinSet *drvrs = findKey(net_drvr_pin_map_, net); if (drvrs) - drvrs->insert(pin); + drvrs->insert(pin); } else clearNetDrvrPinMap(); @@ -1445,8 +1457,8 @@ ConcreteNetwork::disconnectPin(Pin *pin) if (cterm) { ConcreteNet *cnet = cterm->net_; if (cnet) { - cnet->deleteTerm(cterm); - clearNetDrvrPinMap(); + cnet->deleteTerm(cterm); + clearNetDrvrPinMap(); } cpin->term_ = nullptr; delete cterm; @@ -1462,7 +1474,7 @@ ConcreteNetwork::disconnectPin(Pin *pin) void ConcreteNetwork::disconnectNetPin(ConcreteNet *cnet, - ConcretePin *cpin) + ConcretePin *cpin) { cnet->deletePin(cpin); @@ -1473,9 +1485,9 @@ ConcreteNetwork::disconnectNetPin(ConcreteNet *cnet, // and it is safe to incrementally update the drivers. if (cnet->terms_ == nullptr) { Net *net = reinterpret_cast(cnet); - PinSet *drvrs = net_drvr_pin_map_.findKey(net); + PinSet *drvrs = findKey(net_drvr_pin_map_, net); if (drvrs) - drvrs->erase(pin); + drvrs->erase(pin); } else clearNetDrvrPinMap(); @@ -1498,7 +1510,7 @@ ConcreteNetwork::deletePin(Pin *pin) Net * ConcreteNetwork::makeNet(const char *name, - Instance *parent) + Instance *parent) { ConcreteInstance *cparent = reinterpret_cast(parent); ConcreteNet *net = new ConcreteNet(name, cparent); @@ -1520,7 +1532,7 @@ ConcreteNetwork::deleteNet(Net *net) constant_nets_[int(LogicValue::zero)].erase(net); constant_nets_[int(LogicValue::one)].erase(net); - PinSet *drvrs = net_drvr_pin_map_.findKey(net); + PinSet *drvrs = findKey(net_drvr_pin_map_, net); if (drvrs) { delete drvrs; net_drvr_pin_map_.erase(net); @@ -1541,7 +1553,7 @@ ConcreteNetwork::clearConstantNets() void ConcreteNetwork::addConstantNet(Net *net, - LogicValue value) + LogicValue value) { if (value == LogicValue::zero || value == LogicValue::one) @@ -1552,8 +1564,8 @@ ConstantPinIterator * ConcreteNetwork::constantPinIterator() { return new NetworkConstantPinIterator(this, - constant_nets_[int(LogicValue::zero)], - constant_nets_[int(LogicValue::one)]); + constant_nets_[int(LogicValue::zero)], + constant_nets_[int(LogicValue::one)]); } //////////////////////////////////////////////////////////////// @@ -1561,22 +1573,22 @@ ConcreteNetwork::constantPinIterator() // Optimized version of Network::visitConnectedPins. void ConcreteNetwork::visitConnectedPins(const Net *net, - PinVisitor &visitor, - NetSet &visited_nets) const + PinVisitor &visitor, + NetSet &visited_nets) const { - if (!visited_nets.hasKey(net)) { + if (!visited_nets.contains(net)) { visited_nets.insert(net); // Search up from net terminals. const ConcreteNet *cnet = reinterpret_cast(net); for (ConcreteTerm *term = cnet->terms_; term; term = term->net_next_) { ConcretePin *above_pin = term->pin_; if (above_pin) { - ConcreteNet *above_net = above_pin->net_; - if (above_net) - visitConnectedPins(reinterpret_cast(above_net), - visitor, visited_nets); - else - visitor(reinterpret_cast(above_pin)); + ConcreteNet *above_net = above_pin->net_; + if (above_net) + visitConnectedPins(reinterpret_cast(above_net), + visitor, visited_nets); + else + visitor(reinterpret_cast(above_pin)); } } @@ -1585,10 +1597,10 @@ ConcreteNetwork::visitConnectedPins(const Net *net, visitor(reinterpret_cast(pin)); ConcreteTerm *below_term = pin->term_; if (below_term) { - ConcreteNet *below_net = below_term->net_; - if (below_net) - visitConnectedPins(reinterpret_cast(below_net), - visitor, visited_nets); + ConcreteNet *below_net = below_term->net_; + if (below_net) + visitConnectedPins(reinterpret_cast(below_net), + visitor, visited_nets); } } } @@ -1597,7 +1609,7 @@ ConcreteNetwork::visitConnectedPins(const Net *net, //////////////////////////////////////////////////////////////// ConcreteInstance::ConcreteInstance(const char *name, - ConcreteCell *cell, + ConcreteCell *cell, ConcreteInstance *parent) : name_(stringCopy(name)), id_(ConcreteNetwork::nextObjectId()), @@ -1627,7 +1639,7 @@ Instance * ConcreteInstance::findChild(const char *name) const { if (children_) - return reinterpret_cast(children_->findKey(name)); + return reinterpret_cast(findKey(children_, name)); else return nullptr; } @@ -1661,11 +1673,11 @@ ConcreteInstance::findNet(const char *net_name) const { ConcreteNet *net = nullptr; if (nets_) { - net = nets_->findKey(net_name); + net = findKey(nets_, net_name); // Follow merge pointer to surviving net. if (net) { while (net->mergedInto()) - net = net->mergedInto(); + net = net->mergedInto(); } } return net; @@ -1675,20 +1687,18 @@ void ConcreteInstance::findNetsMatching(const PatternMatch *pattern, NetSeq &matches) const { - if (pattern->hasWildcards()) { - ConcreteInstanceNetMap::Iterator net_iter(nets_); - while (net_iter.hasNext()) { - const char *net_name; - ConcreteNet *cnet; - net_iter.next(net_name, cnet); - if (pattern->match(net_name)) - matches.push_back(reinterpret_cast(cnet)); + if (nets_) { + if (pattern->hasWildcards()) { + for (auto [net_name, cnet] : *nets_) { + if (pattern->match(net_name)) + matches.push_back(reinterpret_cast(cnet)); + } + } + else { + ConcreteNet *cnet = findNet(pattern->pattern()); + if (cnet) + matches.push_back(reinterpret_cast(cnet)); } - } - else { - ConcreteNet *cnet = findNet(pattern->pattern()); - if (cnet) - matches.push_back(reinterpret_cast(cnet)); } } @@ -1762,7 +1772,7 @@ ConcreteInstance::addNet(ConcreteNet *net) void ConcreteInstance::addNet(const char *name, - ConcreteNet *net) + ConcreteNet *net) { if (nets_ == nullptr) nets_ = new ConcreteInstanceNetMap; @@ -1784,8 +1794,8 @@ ConcreteInstance::setCell(ConcreteCell *cell) //////////////////////////////////////////////////////////////// ConcretePin::ConcretePin(ConcreteInstance *instance, - ConcretePort *port, - ConcreteNet *net) : + ConcretePort *port, + ConcreteNet *net) : instance_(instance), port_(port), net_(net), @@ -1821,7 +1831,7 @@ ConcreteTerm::name() const } ConcreteTerm::ConcreteTerm(ConcretePin *pin, - ConcreteNet *net) : + ConcreteNet *net) : pin_(pin), net_(net), id_(ConcreteNetwork::nextObjectId()), @@ -1832,7 +1842,7 @@ ConcreteTerm::ConcreteTerm(ConcretePin *pin, //////////////////////////////////////////////////////////////// ConcreteNet::ConcreteNet(const char *name, - ConcreteInstance *instance) : + ConcreteInstance *instance) : name_(stringCopy(name)), id_(ConcreteNetwork::nextObjectId()), instance_(instance), @@ -1912,9 +1922,9 @@ ConcreteNet::deleteTerm(ConcreteTerm *term) for (ConcreteTerm *net_term=terms_;net_term;net_term=net_term->net_next_) { if (net_term == term) { if (net_prev_term) - net_prev_term->net_next_ = term->net_next_; + net_prev_term->net_next_ = term->net_next_; else - terms_ = term->net_next_; + terms_ = term->net_next_; break; } net_prev_term = net_term; @@ -1923,18 +1933,18 @@ ConcreteNet::deleteTerm(ConcreteTerm *term) //////////////////////////////////////////////////////////////// -typedef Map BindingMap; +using BindingMap = std::map ; // Binding table used for linking/expanding network. class ConcreteBindingTbl { public: - explicit ConcreteBindingTbl(NetworkEdit *network); + ConcreteBindingTbl(NetworkEdit *network); Net *ensureBinding(Net *proto_net, - Instance *parent); + Instance *parent); Net *find(Net *net); void bind(Net *proto_net, - Net *clone_net); + Net *clone_net); private: BindingMap map_; @@ -1943,7 +1953,7 @@ private: void ConcreteNetwork::setCellNetworkView(Cell *cell, - Instance *inst) + Instance *inst) { cell_network_view_map_[cell] = inst; } @@ -1951,7 +1961,7 @@ ConcreteNetwork::setCellNetworkView(Cell *cell, Instance * ConcreteNetwork::cellNetworkView(Cell *cell) { - return cell_network_view_map_.findKey(cell); + return findKey(cell_network_view_map_, cell); } void @@ -1981,15 +1991,15 @@ ConcreteNetwork::setLinkFunc(LinkNetworkFunc link) bool ConcreteNetwork::linkNetwork(const char *top_cell_name, - bool make_black_boxes, - Report *report) + bool make_black_boxes, + Report *report) { if (link_func_) { clearConstantNets(); deleteTopInstance(); top_instance_ = link_func_(top_cell_name, make_black_boxes); if (top_instance_) - checkNetworkLibertyCorners(); + checkNetworkLibertyScenes(); return top_instance_ != nullptr; } else { @@ -2000,8 +2010,8 @@ ConcreteNetwork::linkNetwork(const char *top_cell_name, Instance * linkReaderNetwork(Cell *top_cell, - bool, Report *, - NetworkReader *network) + bool, Report *, + NetworkReader *network) { Instance *view = network->cellNetworkView(top_cell); if (view) { @@ -2023,13 +2033,13 @@ linkReaderNetwork(Cell *top_cell, static void makeChildNetwork(Instance *proto, - Instance *parent, - ConcreteBindingTbl *parent_bindings, - NetworkReader *network) + Instance *parent, + ConcreteBindingTbl *parent_bindings, + NetworkReader *network) { Cell *proto_cell = network->cell(proto); Instance *clone = network->makeInstance(proto_cell, network->name(proto), - parent); + parent); if (network->isLeaf(proto_cell)) makeClonePins(proto, clone, nullptr, nullptr, parent, parent_bindings, network); else { @@ -2037,12 +2047,12 @@ makeChildNetwork(Instance *proto, ConcreteBindingTbl bindings(network); Instance *clone_view = network->cellNetworkView(proto_cell); makeClonePins(proto, clone, clone_view, &bindings, parent, - parent_bindings, network); + parent_bindings, network); if (clone_view) { InstanceChildIterator *child_iter = network->childIterator(clone_view); while (child_iter->hasNext()) { - Instance *child = child_iter->next(); - makeChildNetwork(child, clone, &bindings, network); + Instance *child = child_iter->next(); + makeChildNetwork(child, clone, &bindings, network); } delete child_iter; } @@ -2051,12 +2061,12 @@ makeChildNetwork(Instance *proto, static void makeClonePins(Instance *proto, - Instance *clone, - Instance *clone_view, - ConcreteBindingTbl *bindings, - Instance *parent, - ConcreteBindingTbl *parent_bindings, - NetworkReader *network) + Instance *clone, + Instance *clone_view, + ConcreteBindingTbl *bindings, + Instance *parent, + ConcreteBindingTbl *parent_bindings, + NetworkReader *network) { InstancePinIterator *proto_pin_iter = network->pinIterator(proto); while (proto_pin_iter->hasNext()) { @@ -2072,7 +2082,7 @@ makeClonePins(Instance *proto, Net *clone_proto_net = network->net(clone_proto_pin); Net *clone_child_net = nullptr; if (clone_proto_net) - clone_child_net = bindings->ensureBinding(clone_proto_net, clone); + clone_child_net = bindings->ensureBinding(clone_proto_net, clone); network->makeTerm(clone_pin, clone_child_net); } } @@ -2092,7 +2102,7 @@ ConcreteBindingTbl::ConcreteBindingTbl(NetworkEdit *network) : Net * ConcreteBindingTbl::find(Net *proto_net) { - ConcreteNet *net = reinterpret_cast(map_.findKey(proto_net)); + ConcreteNet *net = reinterpret_cast(findKey(map_, proto_net)); while (net && net->mergedInto()) net = net->mergedInto(); return reinterpret_cast(net); @@ -2100,14 +2110,14 @@ ConcreteBindingTbl::find(Net *proto_net) void ConcreteBindingTbl::bind(Net *proto_net, - Net *net) + Net *net) { map_[proto_net] = net; } Net * ConcreteBindingTbl::ensureBinding(Net *proto_net, - Instance *parent) + Instance *parent) { Net *net = find(proto_net); if (net == nullptr) { diff --git a/network/HpinDrvrLoad.cc b/network/HpinDrvrLoad.cc index 94477739..a6f1bb1f 100644 --- a/network/HpinDrvrLoad.cc +++ b/network/HpinDrvrLoad.cc @@ -25,39 +25,41 @@ #include "HpinDrvrLoad.hh" #include +#include +#include "ContainerHelpers.hh" #include "Network.hh" namespace sta { -typedef Set HpinDrvrLoads; +typedef std::set HpinDrvrLoads; static void visitPinsAboveNet2(const Pin *hpin, - Net *above_net, - NetSet &visited, - HpinDrvrLoads &above_drvrs, - HpinDrvrLoads &above_loads, - PinSet *hpin_path, - const Network *network); + Net *above_net, + NetSet &visited, + HpinDrvrLoads &above_drvrs, + HpinDrvrLoads &above_loads, + PinSet *hpin_path, + const Network *network); static void visitPinsBelowNet2(const Pin *hpin, - Net *above_net, - Net *below_net, - NetSet &visited, - HpinDrvrLoads &below_drvrs, - HpinDrvrLoads &below_loads, - PinSet *hpin_path, - const Network *network); + Net *above_net, + Net *below_net, + NetSet &visited, + HpinDrvrLoads &below_drvrs, + HpinDrvrLoads &below_loads, + PinSet *hpin_path, + const Network *network); static void visitHpinDrvrLoads(HpinDrvrLoads drvrs, - HpinDrvrLoads loads, - HpinDrvrLoadVisitor *visitor); + HpinDrvrLoads loads, + HpinDrvrLoadVisitor *visitor); void visitHpinDrvrLoads(const Pin *pin, - const Network *network, - HpinDrvrLoadVisitor *visitor) + const Network *network, + HpinDrvrLoadVisitor *visitor) { NetSet visited(network); HpinDrvrLoads above_drvrs; @@ -66,8 +68,8 @@ visitHpinDrvrLoads(const Pin *pin, Net *above_net = network->net(pin); if (above_net) { visitPinsAboveNet2(pin, above_net, visited, - above_drvrs, above_loads, - &hpin_path, network); + above_drvrs, above_loads, + &hpin_path, network); } // Search down from hpin terminal. @@ -78,8 +80,8 @@ visitHpinDrvrLoads(const Pin *pin, Net *below_net = network->net(term); if (below_net) visitPinsBelowNet2(pin, above_net, below_net, visited, - below_drvrs, below_loads, - &hpin_path, network); + below_drvrs, below_loads, + &hpin_path, network); } if (network->isHierarchical(pin)) { visitHpinDrvrLoads(above_drvrs, below_loads, visitor); @@ -102,20 +104,20 @@ visitHpinDrvrLoads(const Pin *pin, visitHpinDrvrLoads(above_drvrs, loads, visitor); } } - above_drvrs.deleteContents(); - above_loads.deleteContents(); - below_drvrs.deleteContents(); - below_loads.deleteContents(); + deleteContents(above_drvrs); + deleteContents(above_loads); + deleteContents(below_drvrs); + deleteContents(below_loads); } static void visitPinsAboveNet2(const Pin *hpin, - Net *above_net, - NetSet &visited, - HpinDrvrLoads &above_drvrs, - HpinDrvrLoads &above_loads, - PinSet *hpin_path, - const Network *network) + Net *above_net, + NetSet &visited, + HpinDrvrLoads &above_drvrs, + HpinDrvrLoads &above_loads, + PinSet *hpin_path, + const Network *network) { visited.insert(above_net); // Visit above net pins. @@ -124,25 +126,25 @@ visitPinsAboveNet2(const Pin *hpin, const Pin *above_pin = pin_iter->next(); if (above_pin != hpin) { if (network->isDriver(above_pin)) { - HpinDrvrLoad *drvr = new HpinDrvrLoad(above_pin, nullptr, - hpin_path, nullptr); - above_drvrs.insert(drvr); + HpinDrvrLoad *drvr = new HpinDrvrLoad(above_pin, nullptr, + hpin_path, nullptr); + above_drvrs.insert(drvr); } if (network->isLoad(above_pin)) { - HpinDrvrLoad *load = new HpinDrvrLoad(nullptr, above_pin, - nullptr, hpin_path); - above_loads.insert(load); + HpinDrvrLoad *load = new HpinDrvrLoad(nullptr, above_pin, + nullptr, hpin_path); + above_loads.insert(load); } Term *above_term = network->term(above_pin); if (above_term) { - Net *above_net1 = network->net(above_term); - if (above_net1 && !visited.hasKey(above_net1)) { - hpin_path->insert(above_pin); - visitPinsAboveNet2(above_pin, above_net1, visited, - above_drvrs, above_loads, - hpin_path, network); - hpin_path->erase(above_pin); - } + Net *above_net1 = network->net(above_term); + if (above_net1 && !visited.contains(above_net1)) { + hpin_path->insert(above_pin); + visitPinsAboveNet2(above_pin, above_net1, visited, + above_drvrs, above_loads, + hpin_path, network); + hpin_path->erase(above_pin); + } } } } @@ -154,25 +156,25 @@ visitPinsAboveNet2(const Pin *hpin, Term *term = term_iter->next(); Pin *above_pin = network->pin(term); if (above_pin - && above_pin != hpin) { + && above_pin != hpin) { Net *above_net1 = network->net(above_pin); - if (above_net1 && !visited.hasKey(above_net1)) { - hpin_path->insert(above_pin); - visitPinsAboveNet2(above_pin, above_net1, visited, - above_drvrs, above_loads, - hpin_path, network); - hpin_path->erase(above_pin); + if (above_net1 && !visited.contains(above_net1)) { + hpin_path->insert(above_pin); + visitPinsAboveNet2(above_pin, above_net1, visited, + above_drvrs, above_loads, + hpin_path, network); + hpin_path->erase(above_pin); } if (network->isDriver(above_pin)) { - HpinDrvrLoad *drvr = new HpinDrvrLoad(above_pin, nullptr, - hpin_path, nullptr); - above_drvrs.insert(drvr); + HpinDrvrLoad *drvr = new HpinDrvrLoad(above_pin, nullptr, + hpin_path, nullptr); + above_drvrs.insert(drvr); } if (network->isLoad(above_pin)) { - HpinDrvrLoad *load = new HpinDrvrLoad(nullptr, above_pin, - nullptr, hpin_path); - above_loads.insert(load); + HpinDrvrLoad *load = new HpinDrvrLoad(nullptr, above_pin, + nullptr, hpin_path); + above_loads.insert(load); } } } @@ -181,13 +183,13 @@ visitPinsAboveNet2(const Pin *hpin, static void visitPinsBelowNet2(const Pin *hpin, - Net *above_net, - Net *below_net, - NetSet &visited, - HpinDrvrLoads &below_drvrs, - HpinDrvrLoads &below_loads, - PinSet *hpin_path, - const Network *network) + Net *above_net, + Net *below_net, + NetSet &visited, + HpinDrvrLoads &below_drvrs, + HpinDrvrLoads &below_loads, + PinSet *hpin_path, + const Network *network) { visited.insert(below_net); // Visit below net pins. @@ -195,32 +197,32 @@ visitPinsBelowNet2(const Pin *hpin, while (pin_iter->hasNext()) { const Pin *below_pin = pin_iter->next(); if (below_pin != hpin) { - if (above_net && !visited.hasKey(above_net)) - visitPinsAboveNet2(below_pin, above_net, - visited, below_drvrs, below_loads, - hpin_path, network); + if (above_net && !visited.contains(above_net)) + visitPinsAboveNet2(below_pin, above_net, + visited, below_drvrs, below_loads, + hpin_path, network); if (network->isDriver(below_pin)) { - HpinDrvrLoad *drvr = new HpinDrvrLoad(below_pin, nullptr, - hpin_path, nullptr); - below_drvrs.insert(drvr); + HpinDrvrLoad *drvr = new HpinDrvrLoad(below_pin, nullptr, + hpin_path, nullptr); + below_drvrs.insert(drvr); } if (network->isLoad(below_pin)) { - HpinDrvrLoad *load = new HpinDrvrLoad(nullptr, below_pin, - nullptr, hpin_path); - below_loads.insert(load); + HpinDrvrLoad *load = new HpinDrvrLoad(nullptr, below_pin, + nullptr, hpin_path); + below_loads.insert(load); } if (network->isHierarchical(below_pin)) { - Term *term = network->term(below_pin); - if (term) { - Net *below_net1 = network->net(term); - if (below_net1 && !visited.hasKey(below_net1)) { - hpin_path->insert(below_pin); - visitPinsBelowNet2(below_pin, below_net, below_net1, visited, - below_drvrs, below_loads, - hpin_path, network); - hpin_path->erase(below_pin); - } - } + Term *term = network->term(below_pin); + if (term) { + Net *below_net1 = network->net(term); + if (below_net1 && !visited.contains(below_net1)) { + hpin_path->insert(below_pin); + visitPinsBelowNet2(below_pin, below_net, below_net1, visited, + below_drvrs, below_loads, + hpin_path, network); + hpin_path->erase(below_pin); + } + } } } } @@ -232,14 +234,14 @@ visitPinsBelowNet2(const Pin *hpin, Term *term = term_iter->next(); Pin *above_pin = network->pin(term); if (above_pin - && above_pin != hpin) { + && above_pin != hpin) { Net *above_net1 = network->net(above_pin); - if (above_net1 && !visited.hasKey(above_net1)) { - hpin_path->insert(above_pin); - visitPinsAboveNet2(above_pin, above_net1, - visited, below_drvrs, below_loads, - hpin_path, network); - hpin_path->erase(above_pin); + if (above_net1 && !visited.contains(above_net1)) { + hpin_path->insert(above_pin); + visitPinsAboveNet2(above_pin, above_net1, + visited, below_drvrs, below_loads, + hpin_path, network); + hpin_path->erase(above_pin); } } } @@ -248,19 +250,15 @@ visitPinsBelowNet2(const Pin *hpin, static void visitHpinDrvrLoads(HpinDrvrLoads drvrs, - HpinDrvrLoads loads, - HpinDrvrLoadVisitor *visitor) + HpinDrvrLoads loads, + HpinDrvrLoadVisitor *visitor) { - HpinDrvrLoads::Iterator drvr_iter(drvrs); - while (drvr_iter.hasNext()) { - HpinDrvrLoad *drvr = drvr_iter.next(); - HpinDrvrLoads::Iterator load_iter(loads); - while (load_iter.hasNext()) { - HpinDrvrLoad *load = load_iter.next(); + for (HpinDrvrLoad *drvr : drvrs) { + for (HpinDrvrLoad *load : loads) { HpinDrvrLoad clone(drvr->drvr(), - load->load(), - drvr->hpinsFromDrvr(), - load->hpinsToLoad()); + load->load(), + drvr->hpinsFromDrvr(), + load->hpinsToLoad()); visitor->visit(&clone); } } @@ -269,9 +267,9 @@ visitHpinDrvrLoads(HpinDrvrLoads drvrs, //////////////////////////////////////////////////////////////// HpinDrvrLoad::HpinDrvrLoad(const Pin *drvr, - const Pin *load, - PinSet *hpins_from_drvr, - PinSet *hpins_to_load) : + const Pin *load, + PinSet *hpins_from_drvr, + PinSet *hpins_to_load) : drvr_(drvr), load_(load), hpins_from_drvr_(hpins_from_drvr ? new PinSet(*hpins_from_drvr) : nullptr), @@ -280,7 +278,7 @@ HpinDrvrLoad::HpinDrvrLoad(const Pin *drvr, } HpinDrvrLoad::HpinDrvrLoad(const Pin *drvr, - const Pin *load) : + const Pin *load) : drvr_(drvr), load_(load) { @@ -296,19 +294,13 @@ void HpinDrvrLoad::report(const Network *network) { printf("%s -> %s: ", - drvr_ ? network->pathName(drvr_) : "-", - load_ ? network->pathName(load_) : "-"); - PinSet::Iterator pin_iter(hpins_from_drvr_); - while (pin_iter.hasNext()) { - const Pin *pin = pin_iter.next(); + drvr_ ? network->pathName(drvr_) : "-", + load_ ? network->pathName(load_) : "-"); + for (const Pin *pin : *hpins_from_drvr_) printf("%s ", network->pathName(pin)); - } printf("* "); - PinSet::Iterator pin_iter2(hpins_to_load_); - while (pin_iter2.hasNext()) { - const Pin *pin = pin_iter2.next(); + for (const Pin *pin : *hpins_to_load_) printf("%s ", network->pathName(pin)); - } printf("\n"); } @@ -320,7 +312,7 @@ HpinDrvrLoad::setDrvr(const Pin *drvr) bool HpinDrvrLoadLess::operator()(const HpinDrvrLoad *drvr_load1, - const HpinDrvrLoad *drvr_load2) const + const HpinDrvrLoad *drvr_load2) const { const Pin *load1 = drvr_load1->load(); const Pin *load2 = drvr_load2->load(); diff --git a/network/Network.cc b/network/Network.cc index 578c0664..8e03a704 100644 --- a/network/Network.cc +++ b/network/Network.cc @@ -25,11 +25,14 @@ #include "Network.hh" +#include + +#include "ContainerHelpers.hh" #include "StringUtil.hh" #include "PatternMatch.hh" #include "Liberty.hh" #include "PortDirection.hh" -#include "Corner.hh" +#include "Scene.hh" #include "ParseBus.hh" namespace sta { @@ -45,7 +48,7 @@ Network::Network() : Network::~Network() { - net_drvr_pin_map_.deleteContents(); + deleteContents(net_drvr_pin_map_); } void @@ -105,8 +108,8 @@ Network::findPortsMatching(const Cell *cell, else { // bus[0] Port *port_bit = findBusBit(port, from); - if (port_bit != nullptr) - matches.push_back(port_bit); + if (port_bit != nullptr) + matches.push_back(port_bit); } } } @@ -165,9 +168,9 @@ Network::setDefaultLibertyLibrary(LibertyLibrary *library) } void -Network::checkLibertyCorners() +Network::checkLibertyScenes() { - if (corners_->count() > 1) { + if (multiScene()) { LibertyLibraryIterator *lib_iter = libertyLibraryIterator(); LibertyCellSet cells; while (lib_iter->hasNext()) { @@ -182,14 +185,14 @@ Network::checkLibertyCorners() delete lib_iter; for (LibertyCell *cell : cells) - LibertyLibrary::checkCorners(cell, corners_, report_); + LibertyLibrary::checkScenes(cell, scenes_, report_); } } void -Network::checkNetworkLibertyCorners() +Network::checkNetworkLibertyScenes() { - if (corners_->count() > 1) { + if (multiScene()) { LibertyCellSet network_cells; LeafInstanceIterator *leaf_iter = network_->leafInstanceIterator(); while (leaf_iter->hasNext()) { @@ -201,7 +204,7 @@ Network::checkNetworkLibertyCorners() delete leaf_iter; for (LibertyCell *cell : network_cells) - LibertyLibrary::checkCorners(cell, corners_, report_); + LibertyLibrary::checkScenes(cell, scenes_, report_); } } @@ -239,16 +242,16 @@ Network::libertyPort(const Pin *pin) const bool Network::busIndexInRange(const Port *port, - int index) + int index) { int from_index = fromIndex(port); int to_index = toIndex(port); return (from_index <= to_index - && index <= to_index - && index >= from_index) + && index <= to_index + && index >= from_index) || (from_index > to_index - && index >= to_index - && index <= from_index); + && index >= to_index + && index <= from_index); } bool @@ -263,11 +266,8 @@ Network::pathName(const Instance *instance) const InstanceSeq inst_path; path(instance, inst_path); size_t name_length = 0; - InstanceSeq::Iterator path_iter1(inst_path); - while (path_iter1.hasNext()) { - const Instance *inst = path_iter1.next(); + for (const Instance *inst : inst_path) name_length += strlen(name(inst)) + 1; - } char *path_name = makeTmpString(name_length + 1); char *path_ptr = path_name; // Top instance has null string name, so terminate the string here. @@ -287,14 +287,14 @@ Network::pathName(const Instance *instance) const bool Network::pathNameLess(const Instance *inst1, - const Instance *inst2) const + const Instance *inst2) const { return pathNameCmp(inst1, inst2) < 0; } int Network::pathNameCmp(const Instance *inst1, - const Instance *inst2) const + const Instance *inst2) const { if (inst1 == nullptr && inst2) return -1; @@ -312,7 +312,7 @@ Network::pathNameCmp(const Instance *inst1, const Instance *inst2 = path2.back(); int cmp = strcmp(name(inst1), name(inst2)); if (cmp != 0) - return cmp; + return cmp; path1.pop_back(); path2.pop_back(); } @@ -327,8 +327,8 @@ Network::pathNameCmp(const Instance *inst1, void Network::path(const Instance *inst, - // Return value. - InstanceSeq &path) const + // Return value. + InstanceSeq &path) const { while (!isTopInstance(inst)) { path.push_back(inst); @@ -344,7 +344,7 @@ Network::isTopInstance(const Instance *inst) const bool Network::isInside(const Instance *inst, - const Instance *hier_inst) const + const Instance *hier_inst) const { while (inst) { if (inst == hier_inst) @@ -398,14 +398,14 @@ Network::pathName(const Pin *pin) const bool Network::pathNameLess(const Pin *pin1, - const Pin *pin2) const + const Pin *pin2) const { return pathNameCmp(pin1, pin2) < 0; } int Network::pathNameCmp(const Pin *pin1, - const Pin *pin2) const + const Pin *pin2) const { int inst_cmp = pathNameCmp(instance(pin1), instance(pin2)); if (inst_cmp == 0) @@ -416,7 +416,7 @@ Network::pathNameCmp(const Pin *pin1, bool Network::isInside(const Net *net, - const Instance *hier_inst) const + const Instance *hier_inst) const { return isInside(instance(net), hier_inst); } @@ -441,21 +441,21 @@ Network::isTopLevelPort(const Pin *pin) const bool Network::isInside(const Pin *pin, - const Pin *hier_pin) const + const Pin *hier_pin) const { return isInside(pin, instance(hier_pin)); } bool Network::isInside(const Pin *pin, - const Instance *hier_inst) const + const Instance *hier_inst) const { return isInside(instance(pin), hier_inst); } bool Network::pinLess(const Pin *pin1, - const Pin *pin2) const + const Pin *pin2) const { return pathNameLess(pin1, pin2); } @@ -486,14 +486,14 @@ Network::pathName(const Net *net) const bool Network::pathNameLess(const Net *net1, - const Net *net2) const + const Net *net2) const { return pathNameCmp(net1, net2) < 0; } int Network::pathNameCmp(const Net *net1, - const Net *net2) const + const Net *net2) const { int inst_cmp = pathNameCmp(instance(net1), instance(net2)); if (inst_cmp == 0) @@ -514,8 +514,8 @@ Network::highestNetAbove(Net *net) const if (above_pin) { Net *above_net = this->net(above_pin); if (above_net) { - highest_net = highestNetAbove(above_net); - break; + highest_net = highestNetAbove(above_net); + break; } } } @@ -530,13 +530,11 @@ Network::highestConnectedNet(Net *net) const connectedNets(net, &nets); const Net *highest_net = net; int highest_level = hierarchyLevel(net); - NetSet::Iterator net_iter(nets); - while (net_iter.hasNext()) { - const Net *net1 = net_iter.next(); + for (const Net *net1 : nets) { int level = hierarchyLevel(net1); if (level < highest_level - || (level == highest_level - && stringLess(pathName(net1), pathName(highest_net)))) { + || (level == highest_level + && stringLess(pathName(net1), pathName(highest_net)))) { highest_net = net1; highest_level = level; } @@ -546,9 +544,9 @@ Network::highestConnectedNet(Net *net) const void Network::connectedNets(Net *net, - NetSet *nets) const + NetSet *nets) const { - if (!nets->hasKey(net)) { + if (!nets->contains(net)) { nets->insert(net); // Search up from net terminals. NetTermIterator *term_iter = termIterator(net); @@ -556,9 +554,9 @@ Network::connectedNets(Net *net, Term *term = term_iter->next(); Pin *above_pin = pin(term); if (above_pin) { - Net *above_net = this->net(above_pin); - if (above_net) - connectedNets(above_net, nets); + Net *above_net = this->net(above_pin); + if (above_net) + connectedNets(above_net, nets); } } delete term_iter; @@ -569,9 +567,9 @@ Network::connectedNets(Net *net, const Pin *pin1 = pin_iter->next(); Term *below_term = term(pin1); if (below_term) { - Net *below_net = this->net(below_term); - if (below_net) - connectedNets(below_net, nets); + Net *below_net = this->net(below_term); + if (below_net) + connectedNets(below_net, nets); } } delete pin_iter; @@ -580,7 +578,7 @@ Network::connectedNets(Net *net, void Network::connectedNets(const Pin *pin, - NetSet *nets) const + NetSet *nets) const { Net *net = this->net(pin); if (net) @@ -590,7 +588,7 @@ Network::connectedNets(const Pin *pin, if (term) { Net *below_net = this->net(term); if (below_net) - connectedNets(below_net, nets); + connectedNets(below_net, nets); } } } @@ -605,8 +603,8 @@ Network::hierarchyLevel(const Net *net) const if (pin) { Net *above_net = network_->net(pin); if (above_net) { - delete term_iter; - return hierarchyLevel(above_net) + 1; + delete term_iter; + return hierarchyLevel(above_net) + 1; } } } @@ -696,7 +694,7 @@ Network::findInstance(const char *path_name) const Instance * Network::findInstanceRelative(const Instance *inst, - const char *path_name) const + const char *path_name) const { char *first, *tail; pathNameFirst(path_name, first, tail); @@ -707,11 +705,11 @@ Network::findInstanceRelative(const Instance *inst, char *next_tail; pathNameFirst(tail, first, next_tail); if (first) { - inst1 = findChild(inst1, first); - stringDelete(first); + inst1 = findChild(inst1, first); + stringDelete(first); } else - inst1 = findChild(inst1, tail); + inst1 = findChild(inst1, tail); stringDelete(tail); tail = next_tail; } @@ -724,7 +722,7 @@ Network::findInstanceRelative(const Instance *inst, InstanceSeq Network::findInstancesMatching(const Instance *context, - const PatternMatch *pattern) const + const PatternMatch *pattern) const { InstanceSeq matches; if (pattern->hasWildcards()) { @@ -744,9 +742,9 @@ Network::findInstancesMatching(const Instance *context, void Network::findInstancesMatching1(const Instance *context, - size_t context_name_length, - const PatternMatch *pattern, - InstanceSeq &matches) const + size_t context_name_length, + const PatternMatch *pattern, + InstanceSeq &matches) const { InstanceChildIterator *child_iter = childIterator(context); while (child_iter->hasNext()) { @@ -764,7 +762,7 @@ Network::findInstancesMatching1(const Instance *context, InstanceSeq Network::findInstancesHierMatching(const Instance *instance, - const PatternMatch *pattern) const + const PatternMatch *pattern) const { InstanceSeq matches; findInstancesHierMatching1(instance, pattern, matches); @@ -789,15 +787,15 @@ Network::findInstancesHierMatching1(const Instance *instance, void Network::findChildrenMatching(const Instance *parent, - const PatternMatch *pattern, - InstanceSeq &matches) const + const PatternMatch *pattern, + InstanceSeq &matches) const { if (pattern->hasWildcards()) { InstanceChildIterator *child_iter = childIterator(parent); while (child_iter->hasNext()) { Instance *child = child_iter->next(); if (pattern->match(name(child))) - matches.push_back(child); + matches.push_back(child); } delete child_iter; } @@ -816,7 +814,7 @@ Network::findPin(const char *path_name) const Pin * Network::findPinRelative(const Instance *inst, - const char *path_name) const + const char *path_name) const { char *inst_path, *port_name; pathNameLast(path_name, inst_path, port_name); @@ -839,7 +837,7 @@ Network::findPinRelative(const Instance *inst, Pin * Network::findPinLinear(const Instance *instance, - const char *port_name) const + const char *port_name) const { InstancePinIterator *pin_iter = pinIterator(instance); while (pin_iter->hasNext()) { @@ -855,14 +853,14 @@ Network::findPinLinear(const Instance *instance, Pin * Network::findPin(const Instance *instance, - const Port *port) const + const Port *port) const { return findPin(instance, name(port)); } Pin * Network::findPin(const Instance *instance, - const LibertyPort *port) const + const LibertyPort *port) const { return findPin(instance, port->name()); } @@ -875,7 +873,7 @@ Network::findNet(const char *path_name) const Net * Network::findNetRelative(const Instance *inst, - const char *path_name) const + const char *path_name) const { char *inst_path, *net_name; pathNameLast(path_name, inst_path, net_name); @@ -898,7 +896,7 @@ Network::findNetRelative(const Instance *inst, Net * Network::findNetLinear(const Instance *instance, - const char *net_name) const + const char *net_name) const { InstanceNetIterator *net_iter = netIterator(instance); while (net_iter->hasNext()) { @@ -914,7 +912,7 @@ Network::findNetLinear(const Instance *instance, NetSeq Network::findNetsMatching(const Instance *context, - const PatternMatch *pattern) const + const PatternMatch *pattern) const { NetSeq matches; findNetsMatching(context, pattern, matches); @@ -923,7 +921,7 @@ Network::findNetsMatching(const Instance *context, void Network::findNetsMatching(const Instance *context, - const PatternMatch *pattern, + const PatternMatch *pattern, NetSeq &matches) const { if (pattern->hasWildcards()) { @@ -933,11 +931,8 @@ Network::findNetsMatching(const Instance *context, PatternMatch inst_pattern(inst_path, pattern); PatternMatch net_pattern(net_name, pattern); InstanceSeq insts = findInstancesMatching(context, &inst_pattern); - InstanceSeq::Iterator inst_iter(insts); - while (inst_iter.hasNext()) { - const Instance *inst = inst_iter.next(); - findNetsMatching(inst, &net_pattern, matches); - } + for (const Instance *inst : insts) + findNetsMatching(inst, &net_pattern, matches); stringDelete(inst_path); stringDelete(net_name); } @@ -954,7 +949,7 @@ Network::findNetsMatching(const Instance *context, NetSeq Network::findNetsHierMatching(const Instance *instance, - const PatternMatch *pattern) const + const PatternMatch *pattern) const { NetSeq matches; findNetsHierMatching(instance, pattern, matches); @@ -963,7 +958,7 @@ Network::findNetsHierMatching(const Instance *instance, void Network::findNetsHierMatching(const Instance *instance, - const PatternMatch *pattern, + const PatternMatch *pattern, NetSeq &matches) const { findInstNetsMatching(instance, pattern, matches); @@ -977,7 +972,7 @@ Network::findNetsHierMatching(const Instance *instance, NetSeq Network::findNetsMatchingLinear(const Instance *instance, - const PatternMatch *pattern) const + const PatternMatch *pattern) const { NetSeq matches; InstanceNetIterator *net_iter = netIterator(instance); @@ -992,7 +987,7 @@ Network::findNetsMatchingLinear(const Instance *instance, PinSeq Network::findPinsMatching(const Instance *instance, - const PatternMatch *pattern) const + const PatternMatch *pattern) const { PinSeq matches; if (pattern->hasWildcards()) { @@ -1002,11 +997,8 @@ Network::findPinsMatching(const Instance *instance, PatternMatch inst_pattern(inst_path, pattern); PatternMatch port_pattern(port_name, pattern); InstanceSeq insts = findInstancesMatching(instance, &inst_pattern); - InstanceSeq::Iterator inst_iter(insts); - while (inst_iter.hasNext()) { - const Instance *inst = inst_iter.next(); - findInstPinsMatching(inst, &port_pattern, matches); - } + for (const Instance *inst : insts) + findInstPinsMatching(inst, &port_pattern, matches); stringDelete(inst_path); stringDelete(port_name); } @@ -1024,7 +1016,7 @@ Network::findPinsMatching(const Instance *instance, PinSeq Network::findPinsHierMatching(const Instance *instance, - const PatternMatch *pattern) const + const PatternMatch *pattern) const { PinSeq matches; findPinsHierMatching(instance, pattern, matches); @@ -1033,7 +1025,7 @@ Network::findPinsHierMatching(const Instance *instance, void Network::findPinsHierMatching(const Instance *instance, - const PatternMatch *pattern, + const PatternMatch *pattern, // Return value. PinSeq &matches) const { @@ -1048,9 +1040,9 @@ Network::findPinsHierMatching(const Instance *instance, void Network::findInstPinsHierMatching(const Instance *instance, - const PatternMatch *pattern, - // Return value. - PinSeq &matches) const + const PatternMatch *pattern, + // Return value. + PinSeq &matches) const { string inst_name = name(instance); InstancePinIterator *pin_iter = pinIterator(instance); @@ -1066,15 +1058,15 @@ Network::findInstPinsHierMatching(const Instance *instance, void Network::findInstPinsMatching(const Instance *instance, - const PatternMatch *pattern, - PinSeq &matches) const + const PatternMatch *pattern, + PinSeq &matches) const { if (pattern->hasWildcards()) { InstancePinIterator *pin_iter = pinIterator(instance); while (pin_iter->hasNext()) { const Pin *pin = pin_iter->next(); if (pattern->match(name(pin))) - matches.push_back(pin); + matches.push_back(pin); } delete pin_iter; } @@ -1087,10 +1079,10 @@ Network::findInstPinsMatching(const Instance *instance, void Network::location(const Pin *, - // Return values. - double &x, - double &y, - bool &exists) const + // Return values. + double &x, + double &y, + bool &exists) const { x = y = 0.0; exists = false; @@ -1225,13 +1217,13 @@ Network::setPathEscape(char escape) //////////////////////////////////////////////////////////////// -typedef Vector InstanceChildIteratorSeq; +typedef std::vector InstanceChildIteratorSeq; class LeafInstanceIterator1 : public LeafInstanceIterator { public: LeafInstanceIterator1(const Instance *inst, - const Network *network); + const Network *network); bool hasNext() { return next_; } Instance *next(); @@ -1246,7 +1238,7 @@ private: }; LeafInstanceIterator1::LeafInstanceIterator1(const Instance *inst, - const Network *network) : + const Network *network) : network_(network), child_iter_(network->childIterator(inst)), next_(nullptr) @@ -1305,7 +1297,7 @@ Network::leafInstanceIterator(const Instance *hier_inst) const void Network::visitConnectedPins(const Pin *pin, - PinVisitor &visitor) const + PinVisitor &visitor) const { NetSet visited_nets(network_); Net *pin_net = net(pin); @@ -1326,7 +1318,7 @@ Network::visitConnectedPins(const Pin *pin, void Network::visitConnectedPins(const Net *net, - PinVisitor &visitor) const + PinVisitor &visitor) const { NetSet visited_nets(this); visitConnectedPins(net, visitor, visited_nets); @@ -1334,10 +1326,10 @@ Network::visitConnectedPins(const Net *net, void Network::visitConnectedPins(const Net *net, - PinVisitor &visitor, - NetSet &visited_nets) const + PinVisitor &visitor, + NetSet &visited_nets) const { - if (!visited_nets.hasKey(net)) { + if (!visited_nets.contains(net)) { visited_nets.insert(net); // Search up from net terminals. NetTermIterator *term_iter = termIterator(net); @@ -1345,11 +1337,11 @@ Network::visitConnectedPins(const Net *net, Term *term = term_iter->next(); Pin *above_pin = pin(term); if (above_pin) { - Net *above_net = this->net(above_pin); - if (above_net) - visitConnectedPins(above_net, visitor, visited_nets); - else - visitor(above_pin); + Net *above_net = this->net(above_pin); + if (above_net) + visitConnectedPins(above_net, visitor, visited_nets); + else + visitor(above_pin); } } delete term_iter; @@ -1361,9 +1353,9 @@ Network::visitConnectedPins(const Net *net, visitor(pin); Term *below_term = term(pin); if (below_term) { - Net *below_net = this->net(below_term); - if (below_net) - visitConnectedPins(below_net, visitor, visited_nets); + Net *below_net = this->net(below_term); + if (below_net) + visitConnectedPins(below_net, visitor, visited_nets); } } delete pin_iter; @@ -1375,41 +1367,43 @@ Network::visitConnectedPins(const Net *net, class ConnectedPinIterator1 : public ConnectedPinIterator { public: - explicit ConnectedPinIterator1(PinSet *pins); + ConnectedPinIterator1(PinSet *pins); virtual ~ConnectedPinIterator1(); virtual bool hasNext(); virtual const Pin *next(); protected: - PinSet::Iterator pin_iter_; + PinSet *pins_; + PinSet::iterator pin_iter_; }; ConnectedPinIterator1::ConnectedPinIterator1(PinSet *pins) : - pin_iter_(pins) + pins_(pins), + pin_iter_(pins_->begin()) { } ConnectedPinIterator1::~ConnectedPinIterator1() { - delete pin_iter_.container(); + delete pins_; } bool ConnectedPinIterator1::hasNext() { - return pin_iter_.hasNext(); + return pin_iter_ != pins_->end(); } const Pin * ConnectedPinIterator1::next() { - return pin_iter_.next(); + return *pin_iter_++; } class FindConnectedPins : public PinVisitor { public: - explicit FindConnectedPins(PinSet *pins); + FindConnectedPins(PinSet *pins); virtual void operator()(const Pin *pin); protected: @@ -1462,7 +1456,7 @@ Network::connectedPinIterator(const Pin *pin) const bool Network::isConnected(const Net *net, - const Pin *pin) const + const Pin *pin) const { if (this->net(pin) == net) return true; @@ -1474,10 +1468,10 @@ Network::isConnected(const Net *net, bool Network::isConnected(const Net *net, - const Pin *pin, - NetSet &nets) const + const Pin *pin, + NetSet &nets) const { - if (!nets.hasKey(net)) { + if (!nets.contains(net)) { nets.insert(net); // Search up from net terminals. NetTermIterator *term_iter = termIterator(net); @@ -1485,17 +1479,17 @@ Network::isConnected(const Net *net, Term *term = term_iter->next(); Pin *above_pin = this->pin(term); if (above_pin) { - if (above_pin == pin) { - delete term_iter; - return true; - } - else { - Net *above_net = this->net(above_pin); - if (above_net && isConnected(above_net, pin, nets)) { - delete term_iter; - return true; - } - } + if (above_pin == pin) { + delete term_iter; + return true; + } + else { + Net *above_net = this->net(above_pin); + if (above_net && isConnected(above_net, pin, nets)) { + delete term_iter; + return true; + } + } } } delete term_iter; @@ -1505,18 +1499,18 @@ Network::isConnected(const Net *net, while (pin_iter->hasNext()) { const Pin *pin1 = pin_iter->next(); if (pin1 == pin) { - delete pin_iter; - return true; + delete pin_iter; + return true; } else { - Term *below_term = term(pin1); - if (below_term) { - Net *below_net = this->net(below_term); - if (below_net && isConnected(below_net, pin, nets)) { - delete pin_iter; - return true; - } - } + Term *below_term = term(pin1); + if (below_term) { + Net *below_net = this->net(below_term); + if (below_net && isConnected(below_net, pin, nets)) { + delete pin_iter; + return true; + } + } } } delete pin_iter; @@ -1526,7 +1520,7 @@ Network::isConnected(const Net *net, bool Network::isConnected(const Net *net1, - const Net *net2) const + const Net *net2) const { NetSet nets(this); return isConnected(net1, net2, nets); @@ -1534,12 +1528,12 @@ Network::isConnected(const Net *net1, bool Network::isConnected(const Net *net1, - const Net *net2, - NetSet &nets) const + const Net *net2, + NetSet &nets) const { if (net1 == net2) return true; - else if (!nets.hasKey(net1)) { + else if (!nets.contains(net1)) { nets.insert(net1); // Search up from net terminals. NetTermIterator *term_iter = termIterator(net1); @@ -1547,11 +1541,11 @@ Network::isConnected(const Net *net1, Term *term = term_iter->next(); Pin *above_pin = pin(term); if (above_pin) { - Net *above_net = net(above_pin); - if (above_net && isConnected(above_net, net2, nets)) { - delete term_iter; - return true; - } + Net *above_net = net(above_pin); + if (above_net && isConnected(above_net, net2, nets)) { + delete term_iter; + return true; + } } } delete term_iter; @@ -1562,11 +1556,11 @@ Network::isConnected(const Net *net1, const Pin *pin1 = pin_iter->next(); Term *below_term = term(pin1); if (below_term) { - Net *below_net = net(below_term); - if (below_net && isConnected(below_net, net2, nets)) { - delete pin_iter; - return true; - } + Net *below_net = net(below_term); + if (below_net && isConnected(below_net, net2, nets)) { + delete pin_iter; + return true; + } } } delete pin_iter; @@ -1579,8 +1573,8 @@ Network::isConnected(const Net *net1, class FindDrvrPins : public PinVisitor { public: - explicit FindDrvrPins(PinSet *pins, - const Network *network); + FindDrvrPins(PinSet *pins, + const Network *network); virtual void operator()(const Pin *pin); protected: @@ -1589,7 +1583,7 @@ protected: }; FindDrvrPins::FindDrvrPins(PinSet *pins, - const Network *network) : + const Network *network) : PinVisitor(), pins_(pins), network_(network) @@ -1616,13 +1610,13 @@ Network::drivers(const Pin *pin) void Network::clearNetDrvrPinMap() { - net_drvr_pin_map_.deleteContentsClear(); + deleteContents(net_drvr_pin_map_); } PinSet * Network::drivers(const Net *net) { - PinSet *drvrs = net_drvr_pin_map_.findKey(net); + PinSet *drvrs = findKey(net_drvr_pin_map_, net); if (drvrs == nullptr) { drvrs = new PinSet(this); FindDrvrPins visitor(drvrs, this); @@ -1636,16 +1630,16 @@ Network::drivers(const Net *net) void Network::pathNameFirst(const char *path_name, - char *&first, - char *&tail) const + char *&first, + char *&tail) const { char escape = pathEscape(); char divider = pathDivider(); const char *d = strchr(path_name, divider); // Skip escaped dividers. while (d != nullptr - && d > path_name - && d[-1] == escape) + && d > path_name + && d[-1] == escape) d = strchr(d + 1, divider); if (d) { first = new char[d - path_name + 1]; @@ -1665,8 +1659,8 @@ Network::pathNameFirst(const char *path_name, void Network::pathNameLast(const char *path_name, - char *&head, - char *&last) const + char *&head, + char *&last) const { char escape = pathEscape(); char divider = pathDivider(); @@ -1674,10 +1668,10 @@ Network::pathNameLast(const char *path_name, // Search for a non-escaped divider. if (d) { while (d > path_name - && (d[0] != divider - || (d[0] == divider - && d > &path_name[1] - && d[-1] == escape))) + && (d[0] != divider + || (d[0] == divider + && d > &path_name[1] + && d[-1] == escape))) d--; } if (d && d != path_name) { @@ -1705,7 +1699,7 @@ NetworkEdit::NetworkEdit() : void NetworkEdit::connectPin(Pin *pin, - Net *net) + Net *net) { connect(instance(pin), port(pin), net); } @@ -1714,8 +1708,8 @@ NetworkEdit::connectPin(Pin *pin, NetworkConstantPinIterator:: NetworkConstantPinIterator(const Network *network, - NetSet &zero_nets, - NetSet &one_nets) : + NetSet &zero_nets, + NetSet &one_nets) : ConstantPinIterator(), network_(network), constant_pins_{PinSet(network), PinSet(network)} @@ -1723,21 +1717,14 @@ NetworkConstantPinIterator(const Network *network, findConstantPins(zero_nets, constant_pins_[0]); findConstantPins(one_nets, constant_pins_[1]); value_ = LogicValue::zero; - pin_iter_ = new PinSet::Iterator(constant_pins_[0]); -} - -NetworkConstantPinIterator::~NetworkConstantPinIterator() -{ - delete pin_iter_; + pin_iter_ = constant_pins_[0].begin(); } void NetworkConstantPinIterator::findConstantPins(NetSet &nets, - PinSet &pins) + PinSet &pins) { - NetSet::Iterator net_iter(nets); - while (net_iter.hasNext()) { - const Net *net = net_iter.next(); + for (const Net *net : nets) { NetConnectedPinIterator *pin_iter = network_->connectedPinIterator(net); while (pin_iter->hasNext()) { const Pin *pin = pin_iter->next(); @@ -1750,13 +1737,12 @@ NetworkConstantPinIterator::findConstantPins(NetSet &nets, bool NetworkConstantPinIterator::hasNext() { - if (pin_iter_->hasNext()) + if (pin_iter_ != constant_pins_[(int)value_].end()) return true; else if (value_ == LogicValue::zero) { - delete pin_iter_; value_ = LogicValue::one; - pin_iter_ = new PinSet::Iterator(constant_pins_[1]); - return pin_iter_->hasNext(); + pin_iter_ = constant_pins_[1].begin(); + return pin_iter_ != constant_pins_[1].end(); } else return false; @@ -1764,19 +1750,19 @@ NetworkConstantPinIterator::hasNext() void NetworkConstantPinIterator::next(const Pin *&pin, - LogicValue &value) + LogicValue &value) { - pin = pin_iter_->next(); + pin = *pin_iter_++; value = value_; } //////////////////////////////////////////////////////////////// FindNetDrvrLoads::FindNetDrvrLoads(const Pin *drvr_pin, - PinSet &visited_drvrs, - PinSeq &loads, - PinSeq &drvrs, - const Network *network) : + PinSet &visited_drvrs, + PinSeq &loads, + PinSeq &drvrs, + const Network *network) : drvr_pin_(drvr_pin), visited_drvrs_(visited_drvrs), loads_(loads), @@ -1801,11 +1787,11 @@ FindNetDrvrLoads::operator()(const Pin *pin) static void visitPinsAboveNet1(const Pin *hpin, - Net *above_net, - NetSet &visited, - PinSet &above_drvrs, - PinSet &above_loads, - const Network *network) + Net *above_net, + NetSet &visited, + PinSet &above_drvrs, + PinSet &above_loads, + const Network *network) { visited.insert(above_net); // Visit above net pins. @@ -1814,15 +1800,15 @@ visitPinsAboveNet1(const Pin *hpin, const Pin *above_pin = pin_iter->next(); if (above_pin != hpin) { if (network->isDriver(above_pin)) - above_drvrs.insert(above_pin); + above_drvrs.insert(above_pin); if (network->isLoad(above_pin)) - above_loads.insert(above_pin); + above_loads.insert(above_pin); Term *above_term = network->term(above_pin); if (above_term) { - Net *above_net1 = network->net(above_term); - if (above_net1 && !visited.hasKey(above_net1)) - visitPinsAboveNet1(above_pin, above_net1, visited, - above_drvrs, above_loads, network); + Net *above_net1 = network->net(above_term); + if (above_net1 && !visited.contains(above_net1)) + visitPinsAboveNet1(above_pin, above_net1, visited, + above_drvrs, above_loads, network); } } } @@ -1834,15 +1820,15 @@ visitPinsAboveNet1(const Pin *hpin, Term *term = term_iter->next(); Pin *above_pin = network->pin(term); if (above_pin - && above_pin != hpin) { + && above_pin != hpin) { Net *above_net1 = network->net(above_pin); - if (above_net1 && !visited.hasKey(above_net1)) - visitPinsAboveNet1(above_pin, above_net1, visited, - above_drvrs, above_loads, network); + if (above_net1 && !visited.contains(above_net1)) + visitPinsAboveNet1(above_pin, above_net1, visited, + above_drvrs, above_loads, network); if (network->isDriver(above_pin)) - above_drvrs.insert(above_pin); + above_drvrs.insert(above_pin); if (network->isLoad(above_pin)) - above_loads.insert(above_pin); + above_loads.insert(above_pin); } } delete term_iter; @@ -1850,11 +1836,11 @@ visitPinsAboveNet1(const Pin *hpin, static void visitPinsBelowNet1(const Pin *hpin, - Net *below_net, - NetSet &visited, - PinSet &below_drvrs, - PinSet &below_loads, - const Network *network) + Net *below_net, + NetSet &visited, + PinSet &below_drvrs, + PinSet &below_loads, + const Network *network) { visited.insert(below_net); // Visit below net pins. @@ -1864,17 +1850,17 @@ visitPinsBelowNet1(const Pin *hpin, if (below_pin != hpin) { NetSet visited_above(network); if (network->isDriver(below_pin)) - below_drvrs.insert(below_pin); + below_drvrs.insert(below_pin); if (network->isLoad(below_pin)) - below_loads.insert(below_pin); + below_loads.insert(below_pin); if (network->isHierarchical(below_pin)) { - Term *term = network->term(below_pin); - if (term) { - Net *below_net1 = network->net(term); - if (below_net1 && !visited.hasKey(below_net1)) - visitPinsBelowNet1(below_pin, below_net1, visited, - below_drvrs, below_loads, network); - } + Term *term = network->term(below_pin); + if (term) { + Net *below_net1 = network->net(term); + if (below_net1 && !visited.contains(below_net1)) + visitPinsBelowNet1(below_pin, below_net1, visited, + below_drvrs, below_loads, network); + } } } } @@ -1883,24 +1869,19 @@ visitPinsBelowNet1(const Pin *hpin, static void visitDrvrLoads(PinSet drvrs, - PinSet loads, - HierPinThruVisitor *visitor) + PinSet loads, + HierPinThruVisitor *visitor) { - PinSet::Iterator drvr_iter(drvrs); - while (drvr_iter.hasNext()) { - const Pin *drvr = drvr_iter.next(); - PinSet::Iterator load_iter(loads); - while (load_iter.hasNext()) { - const Pin *load = load_iter.next(); + for (const Pin *drvr : drvrs) { + for (const Pin *load : loads) visitor->visit(drvr, load); - } } } void visitDrvrLoadsThruHierPin(const Pin *hpin, - const Network *network, - HierPinThruVisitor *visitor) + const Network *network, + HierPinThruVisitor *visitor) { Net *above_net = network->net(hpin); if (above_net) { @@ -1909,17 +1890,17 @@ visitDrvrLoadsThruHierPin(const Pin *hpin, if (term) { Net *below_net = network->net(term); if (below_net) { - NetSet visited(network); - PinSet above_drvrs(network); - PinSet above_loads(network); - visitPinsAboveNet1(hpin, above_net, visited, - above_drvrs, above_loads, network); - PinSet below_drvrs(network); - PinSet below_loads(network); - visitPinsBelowNet1(hpin, below_net, visited, - below_drvrs, below_loads, network); - visitDrvrLoads(above_drvrs, below_loads, visitor); - visitDrvrLoads(below_drvrs, above_loads, visitor); + NetSet visited(network); + PinSet above_drvrs(network); + PinSet above_loads(network); + visitPinsAboveNet1(hpin, above_net, visited, + above_drvrs, above_loads, network); + PinSet below_drvrs(network); + PinSet below_loads(network); + visitPinsBelowNet1(hpin, below_net, visited, + below_drvrs, below_loads, network); + visitDrvrLoads(above_drvrs, below_loads, visitor); + visitDrvrLoads(below_drvrs, above_loads, visitor); } } } @@ -1927,8 +1908,8 @@ visitDrvrLoadsThruHierPin(const Pin *hpin, void visitDrvrLoadsThruNet(const Net *net, - const Network *network, - HierPinThruVisitor *visitor) + const Network *network, + HierPinThruVisitor *visitor) { NetSet visited(network); PinSet above_drvrs(network); @@ -1944,18 +1925,18 @@ visitDrvrLoadsThruNet(const Net *net, // Search down from pin terminal. const Term *term = network->term(pin); if (term) { - Net *below_net = network->net(term); - if (below_net) { - visitPinsBelowNet1(pin, below_net, visited, - below_drvrs, below_loads, network); - } + Net *below_net = network->net(term); + if (below_net) { + visitPinsBelowNet1(pin, below_net, visited, + below_drvrs, below_loads, network); + } } } else { if (network->isDriver(pin)) - net_drvrs.insert(pin); + net_drvrs.insert(pin); if (network->isLoad(pin)) - net_loads.insert(pin); + net_loads.insert(pin); } } delete pin_iter; @@ -1966,13 +1947,13 @@ visitDrvrLoadsThruNet(const Net *net, Pin *above_pin = network->pin(term); if (above_pin) { if (network->isDriver(above_pin)) - above_drvrs.insert(above_pin); + above_drvrs.insert(above_pin); if (network->isLoad(above_pin)) - above_loads.insert(above_pin); + above_loads.insert(above_pin); Net *above_net = network->net(above_pin); if (above_net) - visitPinsAboveNet1(above_pin, above_net, visited, - above_drvrs, above_loads, network); + visitPinsAboveNet1(above_pin, above_net, visited, + above_drvrs, above_loads, network); } } delete term_iter; @@ -2070,152 +2051,43 @@ NetIdLess::operator()(const Net *net1, //////////////////////////////////////////////////////////////// CellSet::CellSet(const Network *network) : - Set(CellIdLess(network)) + std::set(CellIdLess(network)) { } PortSet::PortSet(const Network *network) : - Set(PortIdLess(network)) + std::set(PortIdLess(network)) { } InstanceSet::InstanceSet() : - Set(InstanceIdLess(nullptr)) + std::set(InstanceIdLess(nullptr)) { } InstanceSet::InstanceSet(const Network *network) : - Set(InstanceIdLess(network)) + std::set(InstanceIdLess(network)) { } -int -InstanceSet::compare(const InstanceSet *set1, - const InstanceSet *set2, - const Network *network) -{ - size_t size1 = set1 ? set1->size() : 0; - size_t size2 = set2 ? set2->size() : 0; - if (size1 == size2) { - InstanceSet::ConstIterator iter1(set1); - InstanceSet::ConstIterator iter2(set2); - while (iter1.hasNext() && iter2.hasNext()) { - const Instance *inst1 = iter1.next(); - const Instance *inst2 = iter2.next(); - ObjectId id1 = network->id(inst1); - ObjectId id2 = network->id(inst2); - if (id1 < id2) - return -1; - else if (id1 > id2) - return 1; - } - // Sets are equal. - return 0; - } - else - return (size1 > size2) ? 1 : -1; -} - -bool -InstanceSet::intersects(const InstanceSet *set1, - const InstanceSet *set2, - const Network *network) -{ - return Set::intersects(set1, set2, InstanceIdLess(network)); -} - -//////////////////////////////////////////////////////////////// - PinSet::PinSet() : - Set(PinIdLess(nullptr)) + std::set(PinIdLess(nullptr)) { } PinSet::PinSet(const Network *network) : - Set(PinIdLess(network)) + std::set(PinIdLess(network)) { } -int -PinSet::compare(const PinSet *set1, - const PinSet *set2, - const Network *network) -{ - size_t size1 = set1 ? set1->size() : 0; - size_t size2 = set2 ? set2->size() : 0; - if (size1 == size2) { - PinSet::ConstIterator iter1(set1); - PinSet::ConstIterator iter2(set2); - while (iter1.hasNext() && iter2.hasNext()) { - const Pin *pin1 = iter1.next(); - const Pin *pin2 = iter2.next(); - ObjectId id1 = network->id(pin1); - ObjectId id2 = network->id(pin2); - if (id1 < id2) - return -1; - else if (id1 > id2) - return 1; - } - // Sets are equal. - return 0; - } - else - return (size1 > size2) ? 1 : -1; -} - -bool -PinSet::intersects(const PinSet *set1, - const PinSet *set2, - const Network *network) -{ - return Set::intersects(set1, set2, PinIdLess(network)); -} - -//////////////////////////////////////////////////////////////// - NetSet::NetSet() : - Set(NetIdLess(nullptr)) + std::set(NetIdLess(nullptr)) { } NetSet::NetSet(const Network *network) : - Set(NetIdLess(network)) + std::set(NetIdLess(network)) { } -int -NetSet::compare(const NetSet *set1, - const NetSet *set2, - const Network *network) -{ - size_t size1 = set1 ? set1->size() : 0; - size_t size2 = set2 ? set2->size() : 0; - if (size1 == size2) { - NetSet::ConstIterator iter1(set1); - NetSet::ConstIterator iter2(set2); - while (iter1.hasNext() && iter2.hasNext()) { - const Net *net1 = iter1.next(); - const Net *net2 = iter2.next(); - ObjectId id1 = network->id(net1); - ObjectId id2 = network->id(net2); - if (id1 < id2) - return -1; - else if (id1 > id2) - return 1; - } - // Sets are equal. - return 0; - } - else - return (size1 > size2) ? 1 : -1; -} - -bool -NetSet::intersects(const NetSet *set1, - const NetSet *set2, - const Network *network) -{ - return Set::intersects(set1, set2, NetIdLess(network)); -} - } // namespace diff --git a/network/Network.i b/network/Network.i index 52bf1ca0..349e9405 100644 --- a/network/Network.i +++ b/network/Network.i @@ -234,8 +234,8 @@ library_iterator() CellSeq find_cells_matching(const char *pattern, - bool regexp, - bool nocase) + bool regexp, + bool nocase) { Network *network = Sta::sta()->ensureLinked(); PatternMatch matcher(pattern, regexp, nocase, Sta::sta()->tclInterp()); @@ -289,7 +289,7 @@ port_direction(const Port *port) { return Sta::sta()->ensureLinked()->direction(port)->name(); } - + const char * pin_direction(const Pin *pin) { @@ -298,8 +298,8 @@ pin_direction(const Pin *pin) PortSeq find_ports_matching(const char *pattern, - bool regexp, - bool nocase) + bool regexp, + bool nocase) { Sta *sta = Sta::sta(); Network *network = sta->ensureLinked(); @@ -310,11 +310,11 @@ find_ports_matching(const char *pattern, PortSeq matches; for (const Port *port : matches1) { if (network->isBus(port) - || network->isBundle(port)) { + || network->isBundle(port)) { PortMemberIterator *member_iter = network->memberIterator(port); while (member_iter->hasNext()) { - Port *member = member_iter->next(); - matches.push_back(member); + Port *member = member_iter->next(); + matches.push_back(member); } delete member_iter; } @@ -326,8 +326,8 @@ find_ports_matching(const char *pattern, PinSeq find_port_pins_matching(const char *pattern, - bool regexp, - bool nocase) + bool regexp, + bool nocase) { Sta *sta = Sta::sta(); Network *network = sta->ensureLinked(); @@ -338,20 +338,20 @@ find_port_pins_matching(const char *pattern, PinSeq pins; for (const Port *port : ports) { if (network->isBus(port) - || network->isBundle(port)) { + || network->isBundle(port)) { PortMemberIterator *member_iter = network->memberIterator(port); while (member_iter->hasNext()) { - Port *member = member_iter->next(); - Pin *pin = network->findPin(top_inst, member); - if (pin) - pins.push_back(pin); + Port *member = member_iter->next(); + Pin *pin = network->findPin(top_inst, member); + if (pin) + pins.push_back(pin); } delete member_iter; } else { Pin *pin = network->findPin(top_inst, port); if (pin) - pins.push_back(pin); + pins.push_back(pin); } } return pins; @@ -373,8 +373,8 @@ get_port_pin(const Port *port) PinSeq find_pins_matching(const char *pattern, - bool regexp, - bool nocase) + bool regexp, + bool nocase) { Sta *sta = Sta::sta(); Network *network = sta->ensureLinked(); @@ -386,8 +386,8 @@ find_pins_matching(const char *pattern, PinSeq find_pins_hier_matching(const char *pattern, - bool regexp, - bool nocase) + bool regexp, + bool nocase) { Sta *sta = Sta::sta(); Network *network = sta->ensureLinked(); @@ -411,8 +411,8 @@ network_leaf_instances() InstanceSeq find_instances_matching(const char *pattern, - bool regexp, - bool nocase) + bool regexp, + bool nocase) { Sta *sta = Sta::sta(); Network *network = sta->ensureLinked(); @@ -424,8 +424,8 @@ find_instances_matching(const char *pattern, InstanceSeq find_instances_hier_matching(const char *pattern, - bool regexp, - bool nocase) + bool regexp, + bool nocase) { Sta *sta = Sta::sta(); Network *network = sta->ensureLinked(); @@ -435,72 +435,6 @@ find_instances_hier_matching(const char *pattern, return matches; } -InstanceSet -find_register_instances(ClockSet *clks, - const RiseFallBoth *clk_tr, - bool edge_triggered, - bool latches) -{ - Sta *sta = Sta::sta(); - InstanceSet insts = sta->findRegisterInstances(clks, clk_tr, - edge_triggered, - latches); - delete clks; - return insts; -} - -PinSet -find_register_data_pins(ClockSet *clks, - const RiseFallBoth *clk_tr, - bool edge_triggered, - bool latches) -{ - Sta *sta = Sta::sta(); - PinSet pins = sta->findRegisterDataPins(clks, clk_tr, - edge_triggered, latches); - delete clks; - return pins; -} - -PinSet -find_register_clk_pins(ClockSet *clks, - const RiseFallBoth *clk_tr, - bool edge_triggered, - bool latches) -{ - Sta *sta = Sta::sta(); - PinSet pins = sta->findRegisterClkPins(clks, clk_tr, - edge_triggered, latches); - delete clks; - return pins; -} - -PinSet -find_register_async_pins(ClockSet *clks, - const RiseFallBoth *clk_tr, - bool edge_triggered, - bool latches) -{ - Sta *sta = Sta::sta(); - PinSet pins = sta->findRegisterAsyncPins(clks, clk_tr, - edge_triggered, latches); - delete clks; - return pins; -} - -PinSet -find_register_output_pins(ClockSet *clks, - const RiseFallBoth *clk_tr, - bool edge_triggered, - bool latches) -{ - Sta *sta = Sta::sta(); - PinSet pins = sta->findRegisterOutputPins(clks, clk_tr, - edge_triggered, latches); - delete clks; - return pins; -} - Net * find_net(char *path_name) { @@ -509,8 +443,8 @@ find_net(char *path_name) NetSeq find_nets_matching(const char *pattern, - bool regexp, - bool nocase) + bool regexp, + bool nocase) { Sta *sta = Sta::sta(); Network *network = sta->ensureLinked(); @@ -522,8 +456,8 @@ find_nets_matching(const char *pattern, NetSeq find_nets_hier_matching(const char *pattern, - bool regexp, - bool nocase) + bool regexp, + bool nocase) { Sta *sta = Sta::sta(); Network *network = sta->ensureLinked(); @@ -621,8 +555,8 @@ find_cell(const char *name) CellSeq find_cells_matching(const char *pattern, - bool regexp, - bool nocase) + bool regexp, + bool nocase) { Sta *sta = Sta::sta(); Network *network = sta->ensureLinked(); @@ -646,7 +580,8 @@ LibertyCell *liberty_cell() { return Sta::sta()->cmdNetwork()->libertyCell(self) bool is_leaf() { return Sta::sta()->cmdNetwork()->isLeaf(self); } CellPortIterator * port_iterator() { return Sta::sta()->cmdNetwork()->portIterator(self); } -string get_attribute(const char *key) +std::string +get_attribute(const char *key) { return Sta::sta()->cmdNetwork()->getAttribute(self, key); } @@ -659,8 +594,8 @@ find_port(const char *name) PortSeq find_ports_matching(const char *pattern, - bool regexp, - bool nocase) + bool regexp, + bool nocase) { Sta *sta = Sta::sta(); Network *network = sta->ensureLinked(); @@ -708,7 +643,8 @@ find_pin(const char *name) { return Sta::sta()->ensureLinked()->findPin(self, name); } -string get_attribute(const char *key) { +std::string +get_attribute(const char *key) { return Sta::sta()->ensureLinked()->getAttribute(self, key); } @@ -801,35 +737,35 @@ bool is_power() { return Sta::sta()->ensureLinked()->isPower(self);} bool is_ground() { return Sta::sta()->ensureLinked()->isGround(self);} float -capacitance(Corner *corner, - const MinMax *min_max) +capacitance(Scene *scene, + const MinMax *min_max) { Sta *sta = Sta::sta(); sta->ensureLibLinked(); float pin_cap, wire_cap; - sta->connectedCap(self, corner, min_max, pin_cap, wire_cap); + sta->connectedCap(self, scene, min_max, pin_cap, wire_cap); return pin_cap + wire_cap; } float -pin_capacitance(Corner *corner, - const MinMax *min_max) +pin_capacitance(Scene *scene, + const MinMax *min_max) { Sta *sta = Sta::sta(); sta->ensureLibLinked(); float pin_cap, wire_cap; - sta->connectedCap(self, corner, min_max, pin_cap, wire_cap); + sta->connectedCap(self, scene, min_max, pin_cap, wire_cap); return pin_cap; } float -wire_capacitance(Corner *corner, - const MinMax *min_max) +wire_capacitance(Scene *scene, + const MinMax *min_max) { Sta *sta = Sta::sta(); sta->ensureLibLinked(); float pin_cap, wire_cap; - sta->connectedCap(self, corner, min_max, pin_cap, wire_cap); + sta->connectedCap(self, scene, min_max, pin_cap, wire_cap); return wire_cap; } diff --git a/network/Network.tcl b/network/Network.tcl index b9d958a6..a8cd501c 100644 --- a/network/Network.tcl +++ b/network/Network.tcl @@ -87,8 +87,8 @@ proc report_instance_pins1 {instance header header_optional dirs} { set dir [pin_direction $pin] if { [lsearch $dirs $dir] != -1 } { if { !$header_shown } { - report_line $header - set header_shown 1 + report_line $header + set header_shown 1 } report_instance_pin $pin } @@ -140,14 +140,14 @@ proc instance_sorted_children { instance } { ################################################################ -define_cmd_args "report_net" {[-corner corner] [-digits digits]\ +define_cmd_args "report_net" {[-scene scene] [-digits digits]\ net_path [> filename] [>> filename]} # -hpins to show hierarchical pins proc_redirect report_net { global sta_report_default_digits - parse_key_args "report_net" args keys {-corner -digits} \ + parse_key_args "report_net" args keys {-corner -scene -digits} \ flags {-connections -verbose -hier_pins} check_argc_eq1 "report_net" $args @@ -164,7 +164,7 @@ proc_redirect report_net { sta_warn 237 "report_net -hier_pins is deprecated." } - set corner [parse_corner_or_all keys] + set scene [parse_scene_or_default keys] set digits $sta_report_default_digits if { [info exists keys(-digits)] } { set digits $keys(-digits) @@ -173,15 +173,15 @@ proc_redirect report_net { set net_path [lindex $args 0] set net [find_net $net_path] if { $net != "NULL" } { - report_net1 $net $corner $digits + report_net1 $net $scene $digits } else { set pin [find_pin $net_path] if { $pin != "NULL" } { set net [$pin net] if { $net != "NULL" } { - report_net1 $net $corner $digits + report_net1 $net $scene $digits } else { - sta_error 231 "net $net_path not found." + sta_error 231 "net $net_path not found." } } else { sta_error 232 "net $net_path not found." @@ -189,14 +189,14 @@ proc_redirect report_net { } } -proc report_net1 { net corner digits } { +proc report_net1 { net scene digits } { report_line "Net [get_full_name $net]" set pins [net_connected_pins_sorted $net] - report_net_caps $net $pins $corner $digits - report_net_pins $pins "Driver pins" "is_driver" $corner $digits - report_net_pins $pins "Load pins" "is_load" $corner $digits - report_net_pins $pins "Hierarchical pins" "is_hierarchical" $corner $digits - report_net_other_pins $pins $corner $digits + report_net_caps $net $pins $scene $digits + report_net_pins $pins "Driver pins" "is_driver" $scene $digits + report_net_pins $pins "Load pins" "is_load" $scene $digits + report_net_pins $pins "Hierarchical pins" "is_hierarchical" $scene $digits + report_net_other_pins $pins $scene $digits } proc net_connected_pins_sorted { net } { @@ -211,10 +211,10 @@ proc net_connected_pins_sorted { net } { return $pins } -proc report_net_caps { net pins corner digits } { - report_net_cap $net "Pin" "pin_capacitance" $corner $digits - report_net_cap $net "Wire" "wire_capacitance" $corner $digits - report_net_cap $net "Total" "capacitance" $corner $digits +proc report_net_caps { net pins scene digits } { + report_net_cap $net "Pin" "pin_capacitance" $scene $digits + report_net_cap $net "Wire" "wire_capacitance" $scene $digits + report_net_cap $net "Total" "capacitance" $scene $digits set pin_count 0 set driver_count 0 @@ -236,13 +236,13 @@ proc report_net_caps { net pins corner digits } { report_line "" } -proc report_net_cap { net caption cap_msg corner digits } { - set cap_min [$net $cap_msg $corner "min"] - set cap_max [$net $cap_msg $corner "max"] +proc report_net_cap { net caption cap_msg scene digits } { + set cap_min [$net $cap_msg $scene "min"] + set cap_max [$net $cap_msg $scene "max"] report_line " $caption capacitance: [capacitance_range_str $cap_min $cap_max $digits]" } -proc report_net_pins { pins header pin_pred corner digits } { +proc report_net_pins { pins header pin_pred scene digits } { set found 0 foreach pin $pins { if {[$pin $pin_pred]} { @@ -250,7 +250,7 @@ proc report_net_pins { pins header pin_pred corner digits } { report_line $header set found 1 } - report_net_pin $pin $corner $digits + report_net_pin $pin $scene $digits } } if { $found } { @@ -258,43 +258,42 @@ proc report_net_pins { pins header pin_pred corner digits } { } } -proc report_net_other_pins { pins corner digits } { +proc report_net_other_pins { pins scene digits } { set header 0 foreach pin $pins { if { !([$pin is_driver] || [$pin is_load] || [$pin is_hierarchical]) } { if { !$header } { - report_line "" - report_line "Other pins" - set header 1 + report_line "" + report_line "Other pins" + set header 1 } - report_net_pin $pin $corner $digits + report_net_pin $pin $scene $digits } } } -proc report_net_pin { pin corner digits } { +proc report_net_pin { pin scene digits } { if [$pin is_leaf] { set cell_name [get_name [[$pin instance] cell]] set cap "" set liberty_port [$pin liberty_port] if { $liberty_port != "NULL" } { - set cap [port_capacitance_str $liberty_port $corner $digits] + set cap [port_capacitance_str $liberty_port $scene $digits] } report_line " [get_full_name $pin] [pin_direction $pin] ($cell_name)$cap[pin_location_str $pin]" } elseif [$pin is_top_level_port] { set wire_cap "" set pin_cap "" - set corner [sta::cmd_corner] set port [$pin port] - set cap_min [port_ext_wire_cap $port $corner "min"] - set cap_max [port_ext_wire_cap $port $corner "max"] + set cap_min [port_ext_wire_cap $port "min"] + set cap_max [port_ext_wire_cap $port "max"] if { $cap_min > 0 || $cap_max > 0 } { set wire_cap " wire [capacitance_range_str $cap_min $cap_max $digits]" } - set cap_min [port_ext_pin_cap $port $corner "min"] - set cap_max [port_ext_pin_cap $port $corner "max"] + set cap_min [port_ext_pin_cap $port "min"] + set cap_max [port_ext_pin_cap $port "max"] if { $cap_min > 0 || $cap_max > 0} { set pin_cap " pin [capacitance_range_str $cap_min $cap_max $digits]" } @@ -317,10 +316,10 @@ proc pin_location_str { pin } { ################################################################ -proc report_pin_ { pin corner digits } { +proc report_pin_ { pin scene digits } { set liberty_port [$pin liberty_port] if { $liberty_port != "NULL" } { - set cap [port_capacitance_str $liberty_port $corner $digits] + set cap [port_capacitance_str $liberty_port $scene $digits] } else { set cap "" } @@ -354,9 +353,9 @@ proc pin_direction_desc { pin } { } # Do not preceed this field by a space in the caller. -proc port_capacitance_str { liberty_port corner digits } { - set cap_min [$liberty_port capacitance $corner "min"] - set cap_max [$liberty_port capacitance $corner "max"] +proc port_capacitance_str { liberty_port scene digits } { + set cap_min [$liberty_port capacitance $scene "min"] + set cap_max [$liberty_port capacitance $scene "max"] if { $cap_min > 0 || $cap_max > 0 } { return " [capacitance_range_str $cap_min $cap_max $digits]" } else { @@ -374,13 +373,13 @@ proc capacitance_range_str { cap_min cap_max digits } { proc capacitances_str { cap_r_min cap_r_max cap_f_min cap_f_max digits } { if { $cap_r_min == $cap_r_max \ - && $cap_f_min == $cap_f_max \ - && $cap_r_max == $cap_f_max } { + && $cap_f_min == $cap_f_max \ + && $cap_r_max == $cap_f_max } { # All 4 values are the same. set cap $cap_r_min return "[format_capacitance $cap $digits]" } elseif { $cap_r_min == $cap_r_max \ - && $cap_f_min == $cap_f_max } { + && $cap_f_min == $cap_f_max } { # Mins equal maxes. return "r [format_capacitance $cap_r_min $digits] f [format_capacitance $cap_f_min $digits]" } else { diff --git a/network/NetworkCmp.cc b/network/NetworkCmp.cc index e00df131..dd82c344 100644 --- a/network/NetworkCmp.cc +++ b/network/NetworkCmp.cc @@ -39,7 +39,7 @@ PortNameLess::PortNameLess(const Network *network) : bool PortNameLess::operator()(const Port *port1, - const Port *port2) const + const Port *port2) const { return stringLess(network_->name(port1), network_->name(port2)); } @@ -51,7 +51,7 @@ PinPathNameLess::PinPathNameLess(const Network *network) : bool PinPathNameLess::operator()(const Pin *pin1, - const Pin *pin2) const + const Pin *pin2) const { return network_->pathNameLess(pin1, pin2); } @@ -63,7 +63,7 @@ NetPathNameLess::NetPathNameLess(const Network *network) : bool NetPathNameLess::operator()(const Net *net1, - const Net *net2) const + const Net *net2) const { return network_->pathNameLess(net1, net2); } @@ -75,7 +75,7 @@ InstancePathNameLess::InstancePathNameLess(const Network *network) : bool InstancePathNameLess::operator()(const Instance *inst1, - const Instance *inst2) const + const Instance *inst2) const { return network_->pathNameLess(inst1, inst2); } @@ -93,6 +93,17 @@ sortByPathName(const PinSet *set, return pins; } +PinSeq +sortByPathName(const PinUnorderedSet *set, + const Network *network) +{ + PinSeq pins; + for (const Pin *pin : *set) + pins.push_back(pin); + sort(pins, PinPathNameLess(network)); + return pins; +} + PortSeq sortByName(const PortSet *set, const Network *network) diff --git a/network/NetworkEdit.i b/network/NetworkEdit.i index c0fa6527..8584ff0a 100644 --- a/network/NetworkEdit.i +++ b/network/NetworkEdit.i @@ -44,8 +44,8 @@ using sta::NetworkEdit; Instance * make_instance_cmd(const char *name, - LibertyCell *cell, - Instance *parent) + LibertyCell *cell, + Instance *parent) { return Sta::sta()->makeInstance(name, cell, parent); } @@ -58,14 +58,14 @@ delete_instance_cmd(Instance *inst) void replace_cell_cmd(Instance *inst, - LibertyCell *to_cell) + LibertyCell *to_cell) { Sta::sta()->replaceCell(inst, to_cell); } Net * make_net_cmd(const char *name, - Instance *parent) + Instance *parent) { return Sta::sta()->makeNet(name, parent); } @@ -85,8 +85,8 @@ delete_net_cmd(Net *net) void connect_pin_cmd(Instance *inst, - Port *port, - Net *net) + Port *port, + Net *net) { Sta::sta()->connectPin(inst, port, net); } diff --git a/network/NetworkEdit.tcl b/network/NetworkEdit.tcl index 0f70b461..a13285fd 100644 --- a/network/NetworkEdit.tcl +++ b/network/NetworkEdit.tcl @@ -35,11 +35,11 @@ proc make_instance { inst_path lib_cell } { if {[regexp $path_regexp $inst_path ignore path_name inst_name]} { set parent [find_instance $path_name] if { $parent == "NULL" } { - # Parent instance not found. This could be a typo, but since - # SDC does not escape hierarchy dividers it can also be - # an escaped name. - set inst_name $inst_path - set parent [top_instance] + # Parent instance not found. This could be a typo, but since + # SDC does not escape hierarchy dividers it can also be + # an escaped name. + set inst_name $inst_path + set parent [top_instance] } } else { set inst_name $inst_path @@ -118,7 +118,7 @@ proc parse_connect_pin { arg } { if {[regexp $path_regexp $arg ignore path_name port_name]} { set inst [find_instance $path_name] if { $inst == "NULL" } { - return 0 + return 0 } } else { set inst [top_instance] @@ -134,8 +134,8 @@ proc parse_connect_pin { arg } { # Make sure the pin is not currently connected to a net. if { $pin != "NULL" \ - && ![$pin is_hierarchical] \ - && [$pin net] != "NULL" } { + && ![$pin is_hierarchical] \ + && [$pin net] != "NULL" } { return 0 } return [list $inst $port] @@ -217,7 +217,7 @@ proc replace_cell { instance lib_cell } { set inst [get_instance_error "instance" $instance] set inst_cell [$inst liberty_cell] if { $inst_cell == "NULL" \ - || ![equiv_cell_ports $inst_cell $cell] } { + || ![equiv_cell_ports $inst_cell $cell] } { return 0 } replace_cell_cmd $inst $cell diff --git a/network/ParseBus.cc b/network/ParseBus.cc index 18ca03f3..17108412 100644 --- a/network/ParseBus.cc +++ b/network/ParseBus.cc @@ -36,9 +36,9 @@ using std::string; bool isBusName(const char *name, - const char brkt_left, - const char brkt_right, - char escape) + const char brkt_left, + const char brkt_right, + char escape) { size_t len = strlen(name); // Shortest bus name is a[0]. @@ -55,13 +55,13 @@ isBusName(const char *name, void parseBusName(const char *name, - const char brkt_left, - const char brkt_right, - const char escape, - // Return values. - bool &is_bus, - string &bus_name, - int &index) + const char brkt_left, + const char brkt_right, + const char escape, + // Return values. + bool &is_bus, + string &bus_name, + int &index) { const char brkts_left[2] = {brkt_left, '\0'}; const char brkts_right[2] = {brkt_right, '\0'}; @@ -71,13 +71,13 @@ parseBusName(const char *name, void parseBusName(const char *name, - const char *brkts_left, - const char *brkts_right, - char escape, - // Return values. - bool &is_bus, - string &bus_name, - int &index) + const char *brkts_left, + const char *brkts_right, + char escape, + // Return values. + bool &is_bus, + string &bus_name, + int &index) { is_bus = false; size_t len = strlen(name); @@ -93,10 +93,10 @@ parseBusName(const char *name, const char *left = strrchr(name, brkt_left); if (left) { is_bus = true; - size_t bus_name_len = left - name; - bus_name.append(name, bus_name_len); - // Simple bus subscript. - index = atoi(left + 1); + size_t bus_name_len = left - name; + bus_name.append(name, bus_name_len); + // Simple bus subscript. + index = atoi(left + 1); } } } @@ -150,20 +150,20 @@ parseBusName(const char *name, const char *left = strrchr(name, brkt_left); if (left) { is_bus = true; - // Check for bus range. - const char range_sep = ':'; - const char *range = strchr(name, range_sep); - if (range) { + // Check for bus range. + const char range_sep = ':'; + const char *range = strchr(name, range_sep); + if (range) { is_range = true; bus_name.append(name, left - name); - // No need to terminate bus subscript because atoi stops - // scanning at first non-digit character. - from = atoi(left + 1); - to = atoi(range + 1); - } + // No need to terminate bus subscript because atoi stops + // scanning at first non-digit character. + from = atoi(left + 1); + to = atoi(range + 1); + } else { bus_name.append(name, left - name); - if (left[1] == '*') + if (left[1] == '*') subscript_wild = true; else from = to = atoi(left + 1); @@ -175,9 +175,9 @@ parseBusName(const char *name, string escapeChars(const char *token, - const char ch1, - const char ch2, - const char escape) + const char ch1, + const char ch2, + const char escape) { string escaped; for (const char *s = token; *s; s++) { diff --git a/network/PortDirection.cc b/network/PortDirection.cc index 693f6908..4c6946af 100644 --- a/network/PortDirection.cc +++ b/network/PortDirection.cc @@ -72,7 +72,7 @@ PortDirection::destroy() } PortDirection::PortDirection(const char *name, - int index) : + int index) : name_(name), index_(index) { diff --git a/network/SdcNetwork.cc b/network/SdcNetwork.cc index 3967a82b..29a0037e 100644 --- a/network/SdcNetwork.cc +++ b/network/SdcNetwork.cc @@ -35,10 +35,10 @@ using std::to_string; static string escapeDividers(const char *token, - const Network *network); + const Network *network); static string escapeBrackets(const char *token, - const Network *network); + const Network *network); NetworkNameAdapter::NetworkNameAdapter(Network *network) : NetworkEdit(), @@ -49,8 +49,8 @@ NetworkNameAdapter::NetworkNameAdapter(Network *network) : bool NetworkNameAdapter::linkNetwork(const char *top_cell_name, - bool make_black_boxes, - Report *report) + bool make_black_boxes, + Report *report) { return network_->linkNetwork(top_cell_name, make_black_boxes, report); } @@ -111,14 +111,14 @@ NetworkNameAdapter::id(const Library *library) const Cell * NetworkNameAdapter::findCell(const Library *library, - const char *name) const + const char *name) const { return network_->findCell(library, name); } CellSeq NetworkNameAdapter::findCellsMatching(const Library *library, - const PatternMatch *pattern) const + const PatternMatch *pattern) const { return network_->findCellsMatching(library, pattern); } @@ -188,14 +188,14 @@ NetworkNameAdapter::cell(const LibertyCell *cell) const Port * NetworkNameAdapter::findPort(const Cell *cell, - const char *name) const + const char *name) const { return network_->findPort(cell, name); } PortSeq NetworkNameAdapter::findPortsMatching(const Cell *cell, - const PatternMatch *pattern) const + const PatternMatch *pattern) const { return network_->findPortsMatching(cell, pattern); } @@ -264,17 +264,17 @@ NetworkNameAdapter::vertexId(const Pin *pin) const void NetworkNameAdapter::setVertexId(Pin *pin, - VertexId id) + VertexId id) { network_->setVertexId(pin, id); } void NetworkNameAdapter::location(const Pin *pin, - // Return values. - double &x, - double &y, - bool &exists) const + // Return values. + double &x, + double &y, + bool &exists) const { network_->location(pin, x, y, exists); } @@ -299,7 +299,7 @@ NetworkNameAdapter::busName(const Port *port) const Port * NetworkNameAdapter::findBusBit(const Port *port, - int index) const + int index) const { return network_->findMember(port, index); } @@ -330,7 +330,7 @@ NetworkNameAdapter::hasMembers(const Port *port) const Port * NetworkNameAdapter::findMember(const Port *port, - int index) const + int index) const { return network_->findMember(port, index); } @@ -382,14 +382,14 @@ NetworkNameAdapter::isLeaf(const Instance *instance) const Pin * NetworkNameAdapter::findPin(const Instance *instance, - const Port *port) const + const Port *port) const { return network_->findPin(instance, port); } Pin * NetworkNameAdapter::findPin(const Instance *instance, - const LibertyPort *port) const + const LibertyPort *port) const { return network_->findPin(instance, port); } @@ -541,15 +541,15 @@ NetworkNameAdapter::isEditable() const LibertyLibrary * NetworkNameAdapter::makeLibertyLibrary(const char *name, - const char *filename) + const char *filename) { return network_edit_->makeLibertyLibrary(name, filename); } Instance * NetworkNameAdapter::makeInstance(LibertyCell *cell, - const char *name, - Instance *parent) + const char *name, + Instance *parent) { return network_edit_->makeInstance(cell, name, parent); } @@ -562,7 +562,7 @@ NetworkNameAdapter::makePins(Instance *inst) void NetworkNameAdapter::mergeInto(Net *net, - Net *into_net) + Net *into_net) { network_edit_->mergeInto(net, into_net); } @@ -575,30 +575,30 @@ NetworkNameAdapter::mergedInto(Net *net) Net * NetworkNameAdapter::makeNet(const char *name, - Instance *parent) + Instance *parent) { return network_edit_->makeNet(name, parent); } void NetworkNameAdapter::replaceCell(Instance *inst, - Cell *to_cell) + Cell *to_cell) { network_edit_->replaceCell(inst, to_cell); } Pin * NetworkNameAdapter::connect(Instance *inst, - Port *port, - Net *net) + Port *port, + Net *net) { return network_edit_->connect(inst, port, net); } Pin * NetworkNameAdapter::connect(Instance *inst, - LibertyPort *port, - Net *net) + LibertyPort *port, + Net *net) { return network_edit_->connect(inst, port, net); } @@ -654,9 +654,9 @@ SdcNetwork::staToSdc(const char *sta_name) const char next_ch = s[1]; // Escaped escape. if (next_ch == escape) { - *d++ = ch; - *d++ = next_ch; - s++; + *d++ = ch; + *d++ = next_ch; + s++; } } else @@ -669,7 +669,7 @@ SdcNetwork::staToSdc(const char *sta_name) const Port * SdcNetwork::findPort(const Cell *cell, - const char *name) const + const char *name) const { Port *port = network_->findPort(cell, name); if (port == nullptr) { @@ -682,13 +682,13 @@ SdcNetwork::findPort(const Cell *cell, string escaped1 = escapeBrackets(name, this); port = network_->findPort(cell, escaped1.c_str()); if (port == nullptr) { - // Try escaping base foo\[0\][1] + // Try escaping base foo\[0\][1] string escaped2; string escaped_bus_name = escapeBrackets(bus_name.c_str(), this); stringPrint(escaped2, "%s[%d]", escaped_bus_name.c_str(), index); - port = network_->findPort(cell, escaped2.c_str()); + port = network_->findPort(cell, escaped2.c_str()); } } else { @@ -702,7 +702,7 @@ SdcNetwork::findPort(const Cell *cell, PortSeq SdcNetwork::findPortsMatching(const Cell *cell, - const PatternMatch *pattern) const + const PatternMatch *pattern) const { PortSeq matches = network_->findPortsMatching(cell, pattern); if (matches.empty()) { @@ -717,13 +717,13 @@ SdcNetwork::findPortsMatching(const Cell *cell, PatternMatch escaped_pattern1(escaped1.c_str(), pattern); matches = network_->findPortsMatching(cell, &escaped_pattern1); if (matches.empty()) { - // Try escaping base foo\[0\][1] + // Try escaping base foo\[0\][1] string escaped_name = escapeBrackets(bus_name.c_str(), this); escaped_name += '['; escaped_name += to_string(index); escaped_name += ']'; - PatternMatch escaped_pattern2(escaped_name.c_str(), pattern); - matches = network_->findPortsMatching(cell, &escaped_pattern2); + PatternMatch escaped_pattern2(escaped_name.c_str(), pattern); + matches = network_->findPortsMatching(cell, &escaped_pattern2); } } else { @@ -820,7 +820,7 @@ SdcNetwork::findInstanceRelative(const Instance *inst, InstanceSeq SdcNetwork::findInstancesMatching(const Instance *context, - const PatternMatch *pattern) const + const PatternMatch *pattern) const { InstanceSeq matches; findInstancesMatching1(context, pattern, matches); @@ -833,18 +833,18 @@ SdcNetwork::findInstancesMatching1(const Instance *context, InstanceSeq &matches) const { visitMatches(context, pattern, - [&](const Instance *instance, - const PatternMatch *tail) - { - size_t match_count = matches.size(); - network_->findChildrenMatching(instance, tail, matches); - return matches.size() != match_count; - }); + [&](const Instance *instance, + const PatternMatch *tail) + { + size_t match_count = matches.size(); + network_->findChildrenMatching(instance, tail, matches); + return matches.size() != match_count; + }); } Instance * SdcNetwork::findChild(const Instance *parent, - const char *name) const + const char *name) const { Instance *child = network_->findChild(parent, name); if (child == nullptr) { @@ -894,8 +894,8 @@ SdcNetwork::findNetRelative(const Instance *inst, net = network_->findNetRelative(inst, path_name2.c_str()); if (net == nullptr) { - string path_name3 = escapeDividers(path_name2.c_str(), network_); - net = network_->findNetRelative(inst, path_name3.c_str()); + string path_name3 = escapeDividers(path_name2.c_str(), network_); + net = network_->findNetRelative(inst, path_name3.c_str()); } } } @@ -904,24 +904,24 @@ SdcNetwork::findNetRelative(const Instance *inst, NetSeq SdcNetwork::findNetsMatching(const Instance *parent, - const PatternMatch *pattern) const + const PatternMatch *pattern) const { NetSeq matches; visitMatches(parent, pattern, - [&](const Instance *instance, - const PatternMatch *tail) - { - size_t match_count = matches.size(); - network_->findInstNetsMatching(instance, tail, matches); - return matches.size() != match_count; - }); + [&](const Instance *instance, + const PatternMatch *tail) + { + size_t match_count = matches.size(); + network_->findInstNetsMatching(instance, tail, matches); + return matches.size() != match_count; + }); return matches; } void SdcNetwork::findInstNetsMatching(const Instance *instance, - const PatternMatch *pattern, - NetSeq &matches) const + const PatternMatch *pattern, + NetSeq &matches) const { network_->findInstNetsMatching(instance, pattern, matches); if (matches.empty()) { @@ -953,7 +953,7 @@ SdcNetwork::findPin(const char *path_name) const Pin * SdcNetwork::findPin(const Instance *instance, - const char *port_name) const + const char *port_name) const { Pin *pin = network_->findPin(instance, port_name); if (pin == nullptr) { @@ -967,11 +967,11 @@ SdcNetwork::findPin(const Instance *instance, string escaped1 = escapeBrackets(port_name, this); pin = network_->findPin(instance, escaped1.c_str()); if (pin == nullptr) { - // Try escaping base foo\[0\][1] + // Try escaping base foo\[0\][1] string escaped_bus_name = escapeBrackets(bus_name.c_str(), this); string escaped2; stringPrint(escaped2, "%s[%d]", escaped_bus_name.c_str(), index); - pin = network_->findPin(instance, escaped2.c_str()); + pin = network_->findPin(instance, escaped2.c_str()); } } else { @@ -986,7 +986,7 @@ SdcNetwork::findPin(const Instance *instance, // Top level ports are not considered pins by get_pins. PinSeq SdcNetwork::findPinsMatching(const Instance *instance, - const PatternMatch *pattern) const + const PatternMatch *pattern) const { PinSeq matches; if (stringEq(pattern->pattern(), "*")) { @@ -996,8 +996,8 @@ SdcNetwork::findPinsMatching(const Instance *instance, Instance *child = child_iter->next(); InstancePinIterator *pin_iter = pinIterator(child); while (pin_iter->hasNext()) { - const Pin *pin = pin_iter->next(); - matches.push_back(pin); + const Pin *pin = pin_iter->next(); + matches.push_back(pin); } delete pin_iter; } @@ -1005,18 +1005,18 @@ SdcNetwork::findPinsMatching(const Instance *instance, } else visitMatches(instance, pattern, - [&](const Instance *instance, - const PatternMatch *tail) - { - return visitPinTail(instance, tail, matches); - }); + [&](const Instance *instance, + const PatternMatch *tail) + { + return visitPinTail(instance, tail, matches); + }); return matches; } bool SdcNetwork::visitPinTail(const Instance *instance, - const PatternMatch *tail, - PinSeq &matches) const + const PatternMatch *tail, + PinSeq &matches) const { bool found_match = false; if (instance != network_->topInstance()) { @@ -1026,35 +1026,35 @@ SdcNetwork::visitPinTail(const Instance *instance, Port *port = port_iter->next(); const char *port_name = network_->name(port); if (network_->hasMembers(port)) { - bool bus_matches = tail->match(port_name); + bool bus_matches = tail->match(port_name); if (!bus_matches) { string escaped_name = escapeDividers(port_name, network_); - bus_matches = tail->match(escaped_name); + bus_matches = tail->match(escaped_name); } - PortMemberIterator *member_iter = network_->memberIterator(port); - while (member_iter->hasNext()) { - Port *member_port = member_iter->next(); - const Pin *pin = network_->findPin(instance, member_port); - if (pin) { - if (bus_matches) { - matches.push_back(pin); - found_match = true; - } - else { - const char *member_name = network_->name(member_port); - bool member_matches = tail->match(member_name); + PortMemberIterator *member_iter = network_->memberIterator(port); + while (member_iter->hasNext()) { + Port *member_port = member_iter->next(); + const Pin *pin = network_->findPin(instance, member_port); + if (pin) { + if (bus_matches) { + matches.push_back(pin); + found_match = true; + } + else { + const char *member_name = network_->name(member_port); + bool member_matches = tail->match(member_name); if (!member_matches) { string escaped_name = escapeDividers(member_name, network_); member_matches = tail->match(escaped_name); } if (member_matches) { - matches.push_back(pin); - found_match = true; - } - } - } - } - delete member_iter; + matches.push_back(pin); + found_match = true; + } + } + } + } + delete member_iter; } else { bool port_matches = tail->match(port_name); @@ -1078,8 +1078,8 @@ SdcNetwork::visitPinTail(const Instance *instance, Instance * SdcNetwork::makeInstance(LibertyCell *cell, - const char *name, - Instance *parent) + const char *name, + Instance *parent) { string escaped_name = escapeDividers(name, this); return network_edit_->makeInstance(cell, escaped_name.c_str(), parent); @@ -1087,7 +1087,7 @@ SdcNetwork::makeInstance(LibertyCell *cell, Net * SdcNetwork::makeNet(const char *name, - Instance *parent) + Instance *parent) { string escaped_name = escapeDividers(name, this); return network_edit_->makeNet(escaped_name.c_str(), parent); @@ -1104,9 +1104,9 @@ SdcNetwork::makeNet(const char *name, // a\/b\/c void SdcNetwork::parsePath(const char *path, - // Return values. - Instance *&inst, - const char *&path_tail) const + // Return values. + Instance *&inst, + const char *&path_tail) const { int divider_count, path_length; scanPath(path, divider_count, path_length); @@ -1121,10 +1121,10 @@ SdcNetwork::parsePath(const char *path, // Scan the path for unescaped dividers. void SdcNetwork::scanPath(const char *path, - // Return values. - // Unescaped divider count. - int ÷r_count, - int &path_length) const + // Return values. + // Unescaped divider count. + int ÷r_count, + int &path_length) const { divider_count = 0; path_length = 0; @@ -1133,8 +1133,8 @@ SdcNetwork::scanPath(const char *path, if (ch == escape_) { // Make sure we don't skip the null if escape is the last char. if (s[1] != '\0') { - s++; - path_length++; + s++; + path_length++; } } else if (ch == divider_) @@ -1145,11 +1145,11 @@ SdcNetwork::scanPath(const char *path, void SdcNetwork::parsePath(const char *path, - int divider_count, - int path_length, - // Return values. - Instance *&inst, - const char *&path_tail) const + int divider_count, + int path_length, + // Return values. + Instance *&inst, + const char *&path_tail) const { Instance *parent = topInstance(); // Leave room to escape all the dividers and '\0'. @@ -1163,9 +1163,9 @@ SdcNetwork::parsePath(const char *path, if (ch == escape_) { // Make sure we don't skip the null if escape is the last char. if (s[1] != '\0') { - *p++ = ch; - *p++ = s[1]; - s++; + *p++ = ch; + *p++ = s[1]; + s++; } } else if (ch == divider_) { @@ -1173,16 +1173,16 @@ SdcNetwork::parsePath(const char *path, *p = '\0'; Instance *child = findChild(parent, inst_path); if (child) { - // Found an instance for the sub-path up to this divider. - parent = inst = child; - // Reset the instance path. - p = inst_path; - path_tail = s + 1; + // Found an instance for the sub-path up to this divider. + parent = inst = child; + // Reset the instance path. + p = inst_path; + path_tail = s + 1; } else { - // No match for sub-path. Escape the divider and keep looking. - *p++ = escape_; - *p++ = divider_; + // No match for sub-path. Escape the divider and keep looking. + *p++ = escape_; + *p++ = divider_; } } else @@ -1203,10 +1203,10 @@ SdcNetwork::parsePath(const char *path, // a\/b\/c bool SdcNetwork::visitMatches(const Instance *parent, - const PatternMatch *pattern, - const std::function - visit_tail) const + const PatternMatch *pattern, + const std::function + visit_tail) const { int divider_count, path_length; scanPath(pattern->pattern(), divider_count, path_length); @@ -1222,9 +1222,9 @@ SdcNetwork::visitMatches(const Instance *parent, if (ch == escape_) { // Make sure we don't skip the null if escape is the last char. if (s[1] != '\0') { - *p++ = ch; - *p++ = s[1]; - s++; + *p++ = ch; + *p++ = s[1]; + s++; } } else if (ch == divider_) { @@ -1234,21 +1234,18 @@ SdcNetwork::visitMatches(const Instance *parent, InstanceSeq matches; network_->findChildrenMatching(parent, &matcher, matches); if (has_brkts && matches.empty()) { - // Look for matches after escaping brackets. + // Look for matches after escaping brackets. string escaped_brkts = escapeBrackets(inst_path, this); - const PatternMatch escaped_pattern(escaped_brkts, pattern); - network_->findChildrenMatching(parent, &escaped_pattern, matches); + const PatternMatch escaped_pattern(escaped_brkts, pattern); + network_->findChildrenMatching(parent, &escaped_pattern, matches); } if (!matches.empty()) { - // Found instance matches for the sub-path up to this divider. - const PatternMatch tail_pattern(s + 1, pattern); - InstanceSeq::Iterator match_iter(matches); - while (match_iter.hasNext()) { - const Instance *match = match_iter.next(); - // Recurse to save the iterator state so we can iterate over - // multiple nested partial matches. - found_match |= visitMatches(match, &tail_pattern, visit_tail); - } + // Found instance matches for the sub-path up to this divider. + const PatternMatch tail_pattern(s + 1, pattern); + for (const Instance *match : matches) + // Recurse to save the iterator state so we can iterate over + // multiple nested partial matches. + found_match |= visitMatches(match, &tail_pattern, visit_tail); } // Escape the divider and keep looking. *p++ = escape_; @@ -1256,7 +1253,7 @@ SdcNetwork::visitMatches(const Instance *parent, } else { if (ch == '[' || ch == ']') - has_brkts = true; + has_brkts = true; *p++ = ch; } if (p - inst_path + 1 > inst_path_length) @@ -1281,15 +1278,15 @@ SdcNetwork::visitMatches(const Instance *parent, static string escapeDividers(const char *token, - const Network *network) + const Network *network) { return escapeChars(token, network->pathDivider(), '\0', - network->pathEscape()); + network->pathEscape()); } static string escapeBrackets(const char *token, - const Network *network) + const Network *network) { return escapeChars(token, '[', ']', network->pathEscape()); } diff --git a/network/VerilogNamespace.cc b/network/VerilogNamespace.cc index 94cc2f3f..5a1dc8e0 100644 --- a/network/VerilogNamespace.cc +++ b/network/VerilogNamespace.cc @@ -90,17 +90,17 @@ staToVerilog(const char *sta_name) if (ch == verilog_escape) { char next_ch = s[1]; if (next_ch == verilog_escape) { - escaped_name += ch; - escaped_name += next_ch; - s++; + escaped_name += ch; + escaped_name += next_ch; + s++; } else - // Skip escape. - escaped = true; + // Skip escape. + escaped = true; } else { if ((!(isalnum(ch) || ch == '_'))) - escaped = true; + escaped = true; escaped_name += ch; } } @@ -128,19 +128,19 @@ staToVerilog2(const char *sta_name) if (ch == verilog_escape) { char next_ch = s[1]; if (next_ch == verilog_escape) { - escaped_name += ch; - escaped_name += next_ch; - s++; + escaped_name += ch; + escaped_name += next_ch; + s++; } else - // Skip escape. - escaped = true; + // Skip escape. + escaped = true; } else { bool is_brkt = (ch == bus_brkt_left || ch == bus_brkt_right); if ((!(isalnum(ch) || ch == '_') && !is_brkt) - || is_brkt) - escaped = true; + || is_brkt) + escaped = true; escaped_name += ch; } } @@ -199,7 +199,7 @@ verilogToSta(const string *verilog_name) || ch == divider || ch == verilog_escape) // Escape bus brackets, dividers and escapes. - sta_name += verilog_escape; + sta_name += verilog_escape; sta_name += ch; } return sta_name; diff --git a/parasitics/ConcreteParasitics.cc b/parasitics/ConcreteParasitics.cc index 9d7f5844..dd866664 100644 --- a/parasitics/ConcreteParasitics.cc +++ b/parasitics/ConcreteParasitics.cc @@ -30,16 +30,14 @@ #include "Debug.hh" #include "Error.hh" #include "Mutex.hh" -#include "Set.hh" #include "MinMax.hh" #include "Network.hh" #include "Wireload.hh" #include "Liberty.hh" #include "Sdc.hh" #include "Parasitics.hh" -#include "MakeConcreteParasitics.hh" #include "ConcreteParasiticsPvt.hh" -#include "Corner.hh" +#include "Scene.hh" // Multiple inheritance is used to share elmore and pi model base // classes, but care is taken to make sure there are no loops in the @@ -85,15 +83,15 @@ ConcreteParasitic::isParasiticNetwork() const void ConcreteParasitic::piModel(float &, - float &, - float &) const + float &, + float &) const { } void ConcreteParasitic::setPiModel(float, - float, - float) + float, + float) { } @@ -110,15 +108,15 @@ ConcreteParasitic::setIsReduced(bool) void ConcreteParasitic::findElmore(const Pin *, - float &, - bool &exists) const + float &, + bool &exists) const { exists = false; } void ConcreteParasitic::setElmore(const Pin *, - float) + float) { } @@ -130,16 +128,16 @@ ConcreteParasitic::findPoleResidue(const Pin *) const void ConcreteParasitic::setPoleResidue(const Pin *, - ComplexFloatSeq *, - ComplexFloatSeq *) + ComplexFloatSeq *, + ComplexFloatSeq *) { } //////////////////////////////////////////////////////////////// ConcretePi::ConcretePi(float c2, - float rpi, - float c1) : + float rpi, + float c1) : c2_(c2), rpi_(rpi), c1_(c1), @@ -155,8 +153,8 @@ ConcretePi::capacitance() const void ConcretePi::setPiModel(float c2, - float rpi, - float c1) + float rpi, + float c1) { c2_ = c2; rpi_ = rpi; @@ -165,8 +163,8 @@ ConcretePi::setPiModel(float c2, void ConcretePi::piModel(float &c2, - float &rpi, - float &c1) const + float &rpi, + float &c1) const { c2 = c2_; rpi = rpi_; @@ -182,8 +180,8 @@ ConcretePi::setIsReduced(bool reduced) //////////////////////////////////////////////////////////////// ConcretePiElmore::ConcretePiElmore(float c2, - float rpi, - float c1) : + float rpi, + float c1) : ConcretePi(c2, rpi, c1) { } @@ -196,16 +194,16 @@ ConcretePiElmore::capacitance() const void ConcretePiElmore::piModel(float &c2, - float &rpi, - float &c1) const + float &rpi, + float &c1) const { ConcretePi::piModel(c2, rpi, c1); } void ConcretePiElmore::setPiModel(float c2, - float rpi, - float c1) + float rpi, + float c1) { ConcretePi::setPiModel(c2, rpi, c1); } @@ -224,8 +222,8 @@ ConcretePiElmore::setIsReduced(bool reduced) void ConcretePiElmore::findElmore(const Pin *load_pin, - float &elmore, - bool &exists) const + float &elmore, + bool &exists) const { auto itr = loads_.find(load_pin); if (itr == loads_.end()) @@ -238,7 +236,7 @@ ConcretePiElmore::findElmore(const Pin *load_pin, void ConcretePiElmore::setElmore(const Pin *load_pin, - float elmore) + float elmore) { loads_[load_pin] = elmore; } @@ -261,8 +259,7 @@ ConcretePiElmore::unannotatedLoads(const Pin *drvr_pin, //////////////////////////////////////////////////////////////// -ConcretePoleResidue:: -ConcretePoleResidue() : +ConcretePoleResidue::ConcretePoleResidue() : poles_(nullptr), residues_(nullptr) { @@ -282,8 +279,8 @@ ConcretePoleResidue::poleResidueCount() const void ConcretePoleResidue::poleResidue(int index, - ComplexFloat &pole, - ComplexFloat &residue) const + ComplexFloat &pole, + ComplexFloat &residue) const { pole = (*poles_)[index]; residue = (*residues_)[index]; @@ -291,7 +288,7 @@ ConcretePoleResidue::poleResidue(int index, void ConcretePoleResidue::setPoleResidue(ComplexFloatSeq *poles, - ComplexFloatSeq *residues) + ComplexFloatSeq *residues) { poles_ = poles; residues_ = residues; @@ -307,8 +304,8 @@ ConcretePoleResidue::unannotatedLoads(const Pin *, //////////////////////////////////////////////////////////////// ConcretePiPoleResidue::ConcretePiPoleResidue(float c2, - float rpi, - float c1) : + float rpi, + float c1) : ConcretePi(c2, rpi, c1) { } @@ -321,16 +318,16 @@ ConcretePiPoleResidue::capacitance() const void ConcretePiPoleResidue::piModel(float &c2, - float &rpi, - float &c1) const + float &rpi, + float &c1) const { ConcretePi::piModel(c2, rpi, c1); } void ConcretePiPoleResidue::setPiModel(float c2, - float rpi, - float c1) + float rpi, + float c1) { ConcretePi::setPiModel(c2, rpi, c1); } @@ -359,8 +356,8 @@ ConcretePiPoleResidue::findPoleResidue(const Pin *load_pin) const void ConcretePiPoleResidue::setPoleResidue(const Pin *load_pin, - ComplexFloatSeq *poles, - ComplexFloatSeq *residues) + ComplexFloatSeq *poles, + ComplexFloatSeq *residues) { ConcretePoleResidue &pole_residue = load_pole_residue_[load_pin]; pole_residue.setPoleResidue(poles, residues); @@ -453,9 +450,9 @@ ConcreteParasiticNode::net(const Network *network) const ConcreteParasiticDevice::ConcreteParasiticDevice(size_t id, - float value, - ConcreteParasiticNode *node1, - ConcreteParasiticNode *node2) : + float value, + ConcreteParasiticNode *node1, + ConcreteParasiticNode *node2) : id_(id), value_(value), node1_(node1), @@ -502,6 +499,15 @@ ConcreteParasiticNetwork::ConcreteParasiticNetwork(const Net *net, { } +ConcreteParasiticNetwork::ConcreteParasiticNetwork(ConcreteParasiticNetwork &¶sitic): + net_(parasitic.net_), + sub_nodes_(parasitic.sub_nodes_), + pin_nodes_(parasitic.pin_nodes_), + max_node_id_(parasitic.max_node_id_), + includes_pin_caps_(parasitic.includes_pin_caps_) +{ +} + ConcreteParasiticNetwork::~ConcreteParasiticNetwork() { deleteDevices(); @@ -603,7 +609,7 @@ ConcreteParasiticNetwork::findParasiticNode(const Pin *pin) const ConcreteParasiticNode * ConcreteParasiticNetwork::ensureParasiticNode(const Net *net, - int id, + int id, const Network *network) { ConcreteParasiticNode *node; @@ -679,12 +685,12 @@ ConcreteParasiticNetwork::unannotatedLoads(ParasiticNode *node, visited_nodes.insert(node); ParasiticResistorSeq &resistors = resistor_map[node]; for (ParasiticResistor *resistor : resistors) { - if (loop_resistors.find(resistor) == loop_resistors.end()) { + if (!loop_resistors.contains(resistor)) { ParasiticNode *onode = parasitics->otherNode(resistor, node); // One commercial extractor creates resistors with identical from/to nodes. if (onode != node - && resistor != from_res) { - if (visited_nodes.find(onode) == visited_nodes.end()) + && resistor != from_res) { + if (!visited_nodes.contains(onode)) unannotatedLoads(onode, resistor, loads, visited_nodes, loop_resistors, resistor_map, parasitics); else @@ -700,7 +706,7 @@ ConcreteParasiticNetwork::unannotatedLoads(ParasiticNode *node, void ConcreteParasiticNetwork::disconnectPin(const Pin *pin, - const Net *net, + const Net *net, const Network *network) { auto pin_node = pin_nodes_.find(pin); @@ -737,31 +743,27 @@ bool NetIdPairLess::operator()(const NetIdPair &net_id1, const NetIdPair &net_id2) const { - const Net *net1 = net_id1.first; - const Net *net2 = net_id2.first; - int id1 = net_id1.second; - int id2 = net_id2.second; + const auto& [net1, id1] = net_id1; + const auto& [net2, id2] = net_id2; return net_less_(net1, net2) || (net1 == net2 - && id1 < id2); + && id1 < id2); } //////////////////////////////////////////////////////////////// -Parasitics * -makeConcreteParasitics(StaState *sta) -{ - return new ConcreteParasitics(sta); -} - -ConcreteParasitics::ConcreteParasitics(StaState *sta) : - Parasitics(sta) +ConcreteParasitics::ConcreteParasitics(std::string name, + std::string filename, + StaState *sta) : + Parasitics(sta), + name_(name), + filename_(filename) { } ConcreteParasitics::~ConcreteParasitics() { - clear(); + deleteParasitics(); } bool @@ -777,78 +779,38 @@ ConcreteParasitics::clear() deleteParasitics(); } -int -ConcreteParasitics::parasiticAnalysisPtIndex(const ParasiticAnalysisPt *ap, - const RiseFall *rf) const -{ - return ap->index() * RiseFall::index_count + rf->index(); -} - void ConcreteParasitics::deleteParasitics() { - int ap_count = corners_->parasiticAnalysisPtCount(); - int ap_rf_count = ap_count * RiseFall::index_count; - for (const auto [drvr, parasitics] : drvr_parasitic_map_) { - if (parasitics) { - for (int i = 0; i < ap_rf_count; i++) - delete parasitics[i]; - delete [] parasitics; - } + for (auto &[drvr, parasitics] : drvr_parasitic_map_) { + for (size_t i = 0; i < min_max_rise_fall_count; i++) + delete parasitics[i]; } drvr_parasitic_map_.clear(); - for (const auto [net, parasitics] : parasitic_network_map_) { - if (parasitics) { - for (int i = 0; i < ap_count; i++) - delete parasitics[i]; - delete [] parasitics; - } - } parasitic_network_map_.clear(); } -void -ConcreteParasitics::deleteParasitics(const Pin *drvr_pin, - const ParasiticAnalysisPt *ap) -{ - ConcreteParasitic **parasitics = drvr_parasitic_map_[drvr_pin]; - if (parasitics) { - for (auto rf : RiseFall::range()) { - int ap_rf_index = parasiticAnalysisPtIndex(ap, rf); - delete parasitics[ap_rf_index]; - parasitics[ap_rf_index] = nullptr; - } - } -} - void ConcreteParasitics::deleteParasitics(const Pin *drvr_pin) { - ConcreteParasitic **parasitics = drvr_parasitic_map_[drvr_pin]; - if (parasitics) { - int ap_count = corners_->parasiticAnalysisPtCount(); - int ap_rf_count = ap_count * RiseFall::index_count; - for (int i = 0; i < ap_rf_count; i++) { + auto itr = drvr_parasitic_map_.find(drvr_pin); + if (itr != drvr_parasitic_map_.end()) { + const MinMaxRiseFallParasitics ¶sitics = itr->second; + for (size_t i = 0; i < min_max_rise_fall_count; i++) delete parasitics[i]; - parasitics[i] = nullptr; - } + drvr_parasitic_map_.erase(itr); } } void -ConcreteParasitics::deleteParasitics(const Net *net, - const ParasiticAnalysisPt *ap) +ConcreteParasitics::deleteParasitics(const Net *net) { PinSet *drivers = network_->drivers(net); for (auto drvr_pin : *drivers) - deleteParasitics(drvr_pin, ap); + deleteParasitics(drvr_pin); - ConcreteParasiticNetwork **parasitics = parasitic_network_map_[net]; - if (parasitics) { - delete parasitics[ap->index()]; - parasitics[ap->index()] = nullptr; - } + parasitic_network_map_.erase(net); } float @@ -867,30 +829,24 @@ ConcreteParasitics::isReducedParasiticNetwork(const Parasitic *parasitic) const void ConcreteParasitics::setIsReducedParasiticNetwork(Parasitic *parasitic, - bool is_reduced) + bool is_reduced) { ConcreteParasitic *cparasitic = static_cast(parasitic); cparasitic->setIsReduced(is_reduced); } void -ConcreteParasitics::disconnectPinBefore(const Pin *pin, - const Network *network) +ConcreteParasitics::disconnectPinBefore(const Pin *pin) { if (haveParasitics()) { deleteReducedParasitics(pin); const Net *net = findParasiticNet(pin); if (net) { - ConcreteParasiticNetwork **parasitics = parasitic_network_map_[net]; - if (parasitics) { - int ap_count = corners_->parasiticAnalysisPtCount(); - for (int i = 0; i < ap_count; i++) { - ConcreteParasiticNetwork *parasitic = parasitics[i]; - if (parasitic) - parasitic->disconnectPin(pin, net, network); - } - } + ConcreteParasiticNetwork *parasitic = + static_cast(findParasiticNetwork(pin)); + if (parasitic) + parasitic->disconnectPin(pin, net, network_); } } } @@ -899,7 +855,7 @@ void ConcreteParasitics::deletePinBefore(const Pin *pin) { // Actions are the same. - disconnectPinBefore(pin, network_); + disconnectPinBefore(pin); } void @@ -910,14 +866,13 @@ ConcreteParasitics::loadPinCapacitanceChanged(const Pin *pin) } void -ConcreteParasitics::deleteReducedParasitics(const Net *net, - const ParasiticAnalysisPt *ap) +ConcreteParasitics::deleteReducedParasitics(const Net *net) { if (!drvr_parasitic_map_.empty()) { PinSet *drivers = network_->drivers(net); if (drivers) { for (auto drvr_pin : *drivers) - deleteDrvrReducedParasitics(drvr_pin, ap); + deleteDrvrReducedParasitics(drvr_pin); } } } @@ -930,7 +885,7 @@ ConcreteParasitics::deleteReducedParasitics(const Pin *pin) PinSet *drivers = network_->drivers(pin); if (drivers) { for (auto drvr_pin : *drivers) - deleteDrvrReducedParasitics(drvr_pin); + deleteDrvrReducedParasitics(drvr_pin); } } } @@ -938,29 +893,7 @@ ConcreteParasitics::deleteReducedParasitics(const Pin *pin) void ConcreteParasitics::deleteDrvrReducedParasitics(const Pin *drvr_pin) { - LockGuard lock(lock_); - ConcreteParasitic **parasitics = drvr_parasitic_map_[drvr_pin]; - if (parasitics) { - int ap_count = corners_->parasiticAnalysisPtCount(); - int ap_rf_count = ap_count * RiseFall::index_count; - for (int i = 0; i < ap_rf_count; i++) - delete parasitics[i]; - delete [] parasitics; - } - drvr_parasitic_map_[drvr_pin] = nullptr; -} - -void -ConcreteParasitics::deleteDrvrReducedParasitics(const Pin *drvr_pin, - const ParasiticAnalysisPt *ap) -{ - LockGuard lock(lock_); - ConcreteParasitic **parasitics = drvr_parasitic_map_[drvr_pin]; - if (parasitics) { - int ap_index = ap->index(); - delete parasitics[ap_index]; - parasitics[ap_index] = nullptr; - } + deleteParasitics(drvr_pin); } //////////////////////////////////////////////////////////////// @@ -972,59 +905,61 @@ ConcreteParasitics::isPiElmore(const Parasitic *parasitic) const return cparasitic && cparasitic->isPiElmore(); } +size_t +minMaxRiseFallIndex(const MinMax *min_max, + const RiseFall *rf) +{ + return min_max->index() * RiseFall::index_count + rf->index(); +} + Parasitic * ConcreteParasitics::findPiElmore(const Pin *drvr_pin, - const RiseFall *rf, - const ParasiticAnalysisPt *ap) const + const RiseFall *rf, + const MinMax *min_max) const { LockGuard lock(lock_); - if (!drvr_parasitic_map_.empty()) { - int ap_rf_index = parasiticAnalysisPtIndex(ap, rf); - ConcreteParasitic **parasitics = drvr_parasitic_map_.findKey(drvr_pin); - if (parasitics) { - ConcreteParasitic *parasitic = parasitics[ap_rf_index]; - if (parasitic && parasitic->isPiElmore()) - return parasitic; - } + auto itr = drvr_parasitic_map_.find(drvr_pin); + if (itr != drvr_parasitic_map_.end()) { + const MinMaxRiseFallParasitics ¶sitics = itr->second; + ConcreteParasitic *parasitic = parasitics[minMaxRiseFallIndex(min_max, rf)]; + if (parasitic && parasitic->isPiElmore()) + return parasitic; } return nullptr; } Parasitic * ConcreteParasitics::makePiElmore(const Pin *drvr_pin, - const RiseFall *rf, - const ParasiticAnalysisPt *ap, - float c2, - float rpi, - float c1) + const RiseFall *rf, + const MinMax *min_max, + float c2, + float rpi, + float c1) { LockGuard lock(lock_); - ConcreteParasitic **parasitics = drvr_parasitic_map_.findKey(drvr_pin); - if (parasitics == nullptr) { - int ap_count = corners_->parasiticAnalysisPtCount(); - int ap_rf_count = ap_count * RiseFall::index_count; - parasitics = new ConcreteParasitic*[ap_rf_count]; - for (int i = 0; i < ap_rf_count; i++) - parasitics[i] = nullptr; - drvr_parasitic_map_[drvr_pin] = parasitics; - } - int ap_rf_index = parasiticAnalysisPtIndex(ap, rf); - ConcreteParasitic *parasitic = parasitics[ap_rf_index]; + auto itr = drvr_parasitic_map_.find(drvr_pin); ConcretePiElmore *pi_elmore = nullptr; - if (parasitic) { - if (parasitic->isPiElmore()) { + size_t mm_rf_index = minMaxRiseFallIndex(min_max, rf); + if (itr != drvr_parasitic_map_.end()) { + MinMaxRiseFallParasitics ¶sitics = itr->second; + ConcreteParasitic *parasitic = parasitics[mm_rf_index]; + if (parasitic && parasitic->isPiElmore()) { pi_elmore = dynamic_cast(parasitic); pi_elmore->setPiModel(c2, rpi, c1); + pi_elmore->loads().clear(); } else { delete parasitic; pi_elmore = new ConcretePiElmore(c2, rpi, c1); - parasitics[ap_rf_index] = pi_elmore; + parasitics[mm_rf_index] = pi_elmore; } } else { + MinMaxRiseFallParasitics ¶sitics = drvr_parasitic_map_[drvr_pin]; + for (size_t i = 0; i < min_max_rise_fall_count; i++) + parasitics[i] = nullptr; pi_elmore = new ConcretePiElmore(c2, rpi, c1); - parasitics[ap_rf_index] = pi_elmore; + parasitics[mm_rf_index] = pi_elmore; } return pi_elmore; } @@ -1040,9 +975,9 @@ ConcreteParasitics::isPiModel(const Parasitic *parasitic) const void ConcreteParasitics::piModel(const Parasitic *parasitic, - float &c2, - float &rpi, - float &c1) const + float &c2, + float &rpi, + float &c1) const { const ConcreteParasitic *cparasitic = static_cast(parasitic); cparasitic->piModel(c2, rpi, c1); @@ -1050,9 +985,9 @@ ConcreteParasitics::piModel(const Parasitic *parasitic, void ConcreteParasitics::setPiModel(Parasitic *parasitic, - float c2, - float rpi, - float c1) + float c2, + float rpi, + float c1) { ConcreteParasitic *cparasitic = static_cast(parasitic); cparasitic->setPiModel(c2, rpi, c1); @@ -1062,9 +997,9 @@ ConcreteParasitics::setPiModel(Parasitic *parasitic, void ConcreteParasitics::findElmore(const Parasitic *parasitic, - const Pin *load_pin, - float &elmore, - bool &exists) const + const Pin *load_pin, + float &elmore, + bool &exists) const { const ConcreteParasitic *cparasitic = static_cast(parasitic); cparasitic->findElmore(load_pin, elmore, exists); @@ -1072,8 +1007,8 @@ ConcreteParasitics::findElmore(const Parasitic *parasitic, void ConcreteParasitics::setElmore(Parasitic *parasitic, - const Pin *load_pin, - float elmore) + const Pin *load_pin, + float elmore) { ConcreteParasitic *cparasitic = static_cast(parasitic); cparasitic->setElmore(load_pin, elmore); @@ -1090,68 +1025,60 @@ ConcreteParasitics::isPiPoleResidue(const Parasitic* parasitic) const Parasitic * ConcreteParasitics::findPiPoleResidue(const Pin *drvr_pin, - const RiseFall *rf, - const ParasiticAnalysisPt *ap) const + const RiseFall *rf, + const MinMax *min_max) const { - if (!drvr_parasitic_map_.empty()) { - int ap_rf_index = parasiticAnalysisPtIndex(ap, rf); - LockGuard lock(lock_); - ConcreteParasitic **parasitics = drvr_parasitic_map_.findKey(drvr_pin); - if (parasitics) { - ConcreteParasitic *parasitic = parasitics[ap_rf_index]; - if (parasitic == nullptr && rf == RiseFall::fall()) { - ap_rf_index = parasiticAnalysisPtIndex(ap, RiseFall::rise()); - parasitic = parasitics[ap_rf_index]; - } - if (parasitic && parasitic->isPiPoleResidue()) - return parasitic; - } + LockGuard lock(lock_); + auto itr = drvr_parasitic_map_.find(drvr_pin); + if (itr != drvr_parasitic_map_.end()) { + const MinMaxRiseFallParasitics ¶sitics = itr->second; + size_t mm_rf_index = minMaxRiseFallIndex(min_max, rf); + ConcreteParasitic *parasitic = parasitics[mm_rf_index]; + if (parasitic && parasitic->isPiPoleResidue()) + return parasitic; } return nullptr; } Parasitic * ConcreteParasitics::makePiPoleResidue(const Pin *drvr_pin, - const RiseFall *rf, - const ParasiticAnalysisPt *ap, - float c2, - float rpi, - float c1) + const RiseFall *rf, + const MinMax *min_max, + float c2, + float rpi, + float c1) { LockGuard lock(lock_); - ConcreteParasitic **parasitics = drvr_parasitic_map_.findKey(drvr_pin); - if (parasitics == nullptr) { - int ap_count = corners_->parasiticAnalysisPtCount(); - int ap_rf_count = ap_count * RiseFall::index_count; - parasitics = new ConcreteParasitic*[ap_rf_count]; - for (int i = 0; i < ap_rf_count; i++) - parasitics[i] = nullptr; - drvr_parasitic_map_[drvr_pin] = parasitics; - } - int ap_rf_index = parasiticAnalysisPtIndex(ap, rf); - ConcreteParasitic *parasitic = parasitics[ap_rf_index]; + auto itr = drvr_parasitic_map_.find(drvr_pin); ConcretePiPoleResidue *pi_pole_residue = nullptr; - if (parasitic) { - if (parasitic->isPiElmore()) { + size_t mm_rf_index = minMaxRiseFallIndex(min_max, rf); + if (itr != drvr_parasitic_map_.end()) { + MinMaxRiseFallParasitics ¶sitics = itr->second; + ConcreteParasitic *parasitic = parasitics[mm_rf_index]; + if (parasitic && parasitic->isPoleResidue()) { pi_pole_residue = dynamic_cast(parasitic); pi_pole_residue->setPiModel(c2, rpi, c1); + pi_pole_residue->loadResidues().clear(); } else { delete parasitic; pi_pole_residue = new ConcretePiPoleResidue(c2, rpi, c1); - parasitics[ap_rf_index] = pi_pole_residue; + parasitics[mm_rf_index] = pi_pole_residue; } } else { + MinMaxRiseFallParasitics ¶sitics = drvr_parasitic_map_[drvr_pin]; + for (size_t i = 0; i < min_max_rise_fall_count; i++) + parasitics[i] = nullptr; pi_pole_residue = new ConcretePiPoleResidue(c2, rpi, c1); - parasitics[ap_rf_index] = pi_pole_residue; + parasitics[mm_rf_index] = pi_pole_residue; } return pi_pole_residue; } Parasitic * ConcreteParasitics::findPoleResidue(const Parasitic *parasitic, - const Pin *load_pin) const + const Pin *load_pin) const { const ConcreteParasitic *cparasitic = static_cast(parasitic); @@ -1160,9 +1087,9 @@ ConcreteParasitics::findPoleResidue(const Parasitic *parasitic, void ConcreteParasitics::setPoleResidue(Parasitic *parasitic, - const Pin *load_pin, - ComplexFloatSeq *poles, - ComplexFloatSeq *residues) + const Pin *load_pin, + ComplexFloatSeq *poles, + ComplexFloatSeq *residues) { ConcreteParasitic *cparasitic = static_cast(parasitic); @@ -1189,9 +1116,9 @@ ConcreteParasitics::poleResidueCount(const Parasitic *parasitic) const void ConcreteParasitics::poleResidue(const Parasitic *parasitic, - int pole_index, - ComplexFloat &pole, - ComplexFloat &residue) const + int pole_index, + ComplexFloat &pole, + ComplexFloat &residue) const { const ConcretePoleResidue *pr_parasitic = static_cast(parasitic); @@ -1208,39 +1135,29 @@ ConcreteParasitics::isParasiticNetwork(const Parasitic *parasitic) const } Parasitic * -ConcreteParasitics::findParasiticNetwork(const Net *net, - const ParasiticAnalysisPt *ap) const +ConcreteParasitics::findParasiticNetwork(const Net *net) { - if (!parasitic_network_map_.empty()) { - LockGuard lock(lock_); - if (!parasitic_network_map_.empty()) { - ConcreteParasiticNetwork **parasitics=parasitic_network_map_.findKey(net); - if (parasitics) { - ConcreteParasiticNetwork *parasitic = parasitics[ap->index()]; - if (parasitic == nullptr) - parasitic = parasitics[ap->indexMax()]; - return parasitic; - } - } - } - return nullptr; + LockGuard lock(lock_); + auto itr = parasitic_network_map_.find(net); + if (itr != parasitic_network_map_.end()) + return &itr->second; + else + return nullptr; } Parasitic * -ConcreteParasitics::findParasiticNetwork(const Pin *pin, - const ParasiticAnalysisPt *ap) const +ConcreteParasitics::findParasiticNetwork(const Pin *pin) { if (!parasitic_network_map_.empty()) { LockGuard lock(lock_); if (!parasitic_network_map_.empty()) { // Only call findParasiticNet if parasitics exist. const Net *net = findParasiticNet(pin); - ConcreteParasiticNetwork **parasitics=parasitic_network_map_.findKey(net); - if (parasitics) { - ConcreteParasiticNetwork *parasitic = parasitics[ap->index()]; - if (parasitic == nullptr) - parasitic = parasitics[ap->indexMax()]; - return parasitic; + + if (!parasitic_network_map_.empty()) { + auto itr = parasitic_network_map_.find(net); + if (itr != parasitic_network_map_.end()) + return &itr->second; } } } @@ -1249,74 +1166,25 @@ ConcreteParasitics::findParasiticNetwork(const Pin *pin, Parasitic * ConcreteParasitics::makeParasiticNetwork(const Net *net, - bool includes_pin_caps, - const ParasiticAnalysisPt *ap) + bool includes_pin_caps) { LockGuard lock(lock_); - ConcreteParasiticNetwork **parasitics = parasitic_network_map_.findKey(net); - if (parasitics == nullptr) { - int ap_count = corners_->parasiticAnalysisPtCount(); - parasitics = new ConcreteParasiticNetwork*[ap_count]; - for (int i = 0; i < ap_count; i++) - parasitics[i] = nullptr; - parasitic_network_map_[net] = parasitics; + auto itr = parasitic_network_map_.find(net); + if (itr != parasitic_network_map_.end()) { + parasitic_network_map_.erase(itr); + for (const Pin *drvr_pin : *network_->drivers(net)) + deleteParasitics(drvr_pin); } - int ap_index = ap->index(); - ConcreteParasiticNetwork *parasitic = parasitics[ap_index]; - if (parasitic) { - delete parasitic; - if (net) { - for (const Pin *drvr_pin : *network_->drivers(net)) - deleteParasitics(drvr_pin); - } - } - parasitic = new ConcreteParasiticNetwork(net, includes_pin_caps, network_); - parasitics[ap_index] = parasitic; - return parasitic; + parasitic_network_map_.emplace(net, ConcreteParasiticNetwork(net, includes_pin_caps, + network_)); + return ¶sitic_network_map_.find(net)->second; } void -ConcreteParasitics::deleteParasiticNetwork(const Net *net, - const ParasiticAnalysisPt *ap) +ConcreteParasitics::deleteParasiticNetwork(const Net *net) { - if (!parasitic_network_map_.empty()) { - LockGuard lock(lock_); - ConcreteParasiticNetwork **parasitics = parasitic_network_map_.findKey(net); - if (parasitics) { - int ap_index = ap->index(); - delete parasitics[ap_index]; - parasitics[ap_index] = nullptr; - - int ap_count = corners_->parasiticAnalysisPtCount(); - bool have_parasitics = false; - for (int i = 0; i < ap_count; i++) { - if (parasitics[i]) { - have_parasitics = true; - break; - } - } - if (!have_parasitics) { - delete [] parasitics; - parasitic_network_map_.erase(net); - } - } - } -} - -void -ConcreteParasitics::deleteParasiticNetworks(const Net *net) -{ - if (!parasitic_network_map_.empty()) { - LockGuard lock(lock_); - ConcreteParasiticNetwork **parasitics = parasitic_network_map_.findKey(net); - if (parasitics) { - int ap_count = corners_->parasiticAnalysisPtCount(); - for (int i = 0; i < ap_count; i++) - delete parasitics[i]; - delete [] parasitics; - parasitic_network_map_.erase(net); - } - } + LockGuard lock(lock_); + parasitic_network_map_.erase(net); } const Net * @@ -1351,8 +1219,8 @@ ConcreteParasitics::findParasiticNode(Parasitic *parasitic, ParasiticNode * ConcreteParasitics::ensureParasiticNode(Parasitic *parasitic, - const Net *net, - int id, + const Net *net, + int id, const Network *network) { ConcreteParasiticNetwork *cparasitic = @@ -1371,7 +1239,7 @@ ConcreteParasitics::findParasiticNode(const Parasitic *parasitic, ParasiticNode * ConcreteParasitics::ensureParasiticNode(Parasitic *parasitic, - const Pin *pin, + const Pin *pin, const Network *network) { ConcreteParasiticNetwork *cparasitic = @@ -1381,7 +1249,7 @@ ConcreteParasitics::ensureParasiticNode(Parasitic *parasitic, void ConcreteParasitics::incrCap(ParasiticNode *node, - float cap) + float cap) { ConcreteParasiticNode *cnode = static_cast(node); cnode->incrCapacitance(cap); @@ -1407,8 +1275,8 @@ void ConcreteParasitics::makeResistor(Parasitic *parasitic, size_t index, float res, - ParasiticNode *node1, - ParasiticNode *node2) + ParasiticNode *node1, + ParasiticNode *node2) { ConcreteParasiticNode *cnode1 = static_cast(node1); ConcreteParasiticNode *cnode2 = static_cast(node2); diff --git a/parasitics/ConcreteParasitics.hh b/parasitics/ConcreteParasitics.hh index 9a06058d..bf5ca547 100644 --- a/parasitics/ConcreteParasitics.hh +++ b/parasitics/ConcreteParasitics.hh @@ -25,9 +25,9 @@ #pragma once #include +#include +#include -#include "Map.hh" -#include "Set.hh" #include "MinMax.hh" #include "Parasitics.hh" @@ -36,24 +36,31 @@ namespace sta { class ConcreteParasitic; class ConcreteParasiticNetwork; -typedef Map ConcreteParasiticMap; -typedef Map ConcreteParasiticNetworkMap; +constexpr size_t min_max_rise_fall_count = MinMax::index_count * RiseFall::index_count; +// Min/maxrise/fall reduced parasitics for each driver pin. +// When min parastitic network != max parasitic network only +// the min values are populated for the min parasitics and +// max values for max parasitics. +using MinMaxRiseFallParasitics = std::array; +using ConcreteParasiticMap = std::map; +using ConcreteParasiticNetworkMap = std::map; // This class acts as a BUILDER for parasitics. class ConcreteParasitics : public Parasitics { public: - ConcreteParasitics(StaState *sta); + ConcreteParasitics(std::string name, + std::string filename, + StaState *sta); virtual ~ConcreteParasitics(); + const std::string &name() const override { return name_; }; + const std::string &filename() const override { return filename_; }; bool haveParasitics() override; void clear() override; void deleteParasitics() override; - void deleteParasitics(const Net *net, - const ParasiticAnalysisPt *ap) override; - void deleteParasitics(const Pin *drvr_pin, - const ParasiticAnalysisPt *ap) override; - void deleteParasitics(const Pin *drvr_pin); + void deleteParasitics(const Net *net) override; + void deleteParasitics(const Pin *drvr_pin) override; bool isReducedParasiticNetwork(const Parasitic *parasitic) const override; void setIsReducedParasiticNetwork(Parasitic *parasitic, @@ -64,10 +71,10 @@ public: bool isPiElmore(const Parasitic *parasitic) const override; Parasitic *findPiElmore(const Pin *drvr_pin, const RiseFall *rf, - const ParasiticAnalysisPt *ap) const override; + const MinMax *min_max) const override; Parasitic *makePiElmore(const Pin *drvr_pin, const RiseFall *rf, - const ParasiticAnalysisPt *ap, + const MinMax *min_max, float c2, float rpi, float c1) override; @@ -93,13 +100,15 @@ public: bool isPiPoleResidue(const Parasitic* parasitic) const override; Parasitic *findPiPoleResidue(const Pin *drvr_pin, const RiseFall *rf, - const ParasiticAnalysisPt *ap) const override; + const MinMax *min_max) const override; Parasitic *findPoleResidue(const Parasitic *parasitic, const Pin *load_pin) const override; Parasitic *makePiPoleResidue(const Pin *drvr_pin, const RiseFall *rf, - const ParasiticAnalysisPt *ap, - float c2, float rpi, float c1) override; + const MinMax *min_max, + float c2, + float rpi, + float c1) override; void setPoleResidue(Parasitic *parasitic, const Pin *load_pin, ComplexFloatSeq *poles, ComplexFloatSeq *residues) override; @@ -111,16 +120,11 @@ public: ComplexFloat &residue) const override; bool isParasiticNetwork(const Parasitic *parasitic) const override; - Parasitic *findParasiticNetwork(const Net *net, - const ParasiticAnalysisPt *ap) const override; - Parasitic *findParasiticNetwork(const Pin *pin, - const ParasiticAnalysisPt *ap) const override; + Parasitic *findParasiticNetwork(const Net *net) override; + Parasitic *findParasiticNetwork(const Pin *pin) override; Parasitic *makeParasiticNetwork(const Net *net, - bool includes_pin_caps, - const ParasiticAnalysisPt *ap) override; - void deleteParasiticNetwork(const Net *net, - const ParasiticAnalysisPt *ap) override; - void deleteParasiticNetworks(const Net *net) override; + bool includes_pin_caps) override; + void deleteParasiticNetwork(const Net *net) override; const Net *net(const Parasitic *parasitic) const override; bool includesPinCaps(const Parasitic *parasitic) const override; ParasiticNode *findParasiticNode(Parasitic *parasitic, @@ -171,23 +175,20 @@ public: PinSet unannotatedLoads(const Parasitic *parasitic, const Pin *drvr_pin) const override; - void disconnectPinBefore(const Pin *pin, - const Network *network) override; + void disconnectPinBefore(const Pin *pin) override; void deletePinBefore(const Pin *pin) override; void loadPinCapacitanceChanged(const Pin *pin) override; - void deleteReducedParasitics(const Net *net, - const ParasiticAnalysisPt *ap) override; + void deleteReducedParasitics(const Net *net) override; void deleteDrvrReducedParasitics(const Pin *drvr_pin) override; protected: - int parasiticAnalysisPtIndex(const ParasiticAnalysisPt *ap, - const RiseFall *rf) const; Parasitic *ensureRspf(const Pin *drvr_pin); void makeAnalysisPtAfter(); void deleteReducedParasitics(const Pin *pin); - void deleteDrvrReducedParasitics(const Pin *drvr_pin, - const ParasiticAnalysisPt *ap); + + std::string name_; + std::string filename_; // Driver pin to array of parasitics indexed by analysis pt index // and transition. diff --git a/parasitics/ConcreteParasiticsPvt.hh b/parasitics/ConcreteParasiticsPvt.hh index 72c44a9c..597512dc 100644 --- a/parasitics/ConcreteParasiticsPvt.hh +++ b/parasitics/ConcreteParasiticsPvt.hh @@ -35,26 +35,27 @@ class ConcretePoleResidue; class ConcreteParasiticDevice; class ConcreteParasiticNode; -typedef std::pair NetIdPair; +using NetIdPair = std::pair; + class NetIdPairLess { public: NetIdPairLess(const Network *network); bool operator()(const NetIdPair &net_id1, - const NetIdPair &net_id2) const; + const NetIdPair &net_id2) const; private: const NetIdLess net_less_; }; -typedef std::map ConcreteElmoreLoadMap; -typedef std::map ConcretePoleResidueMap; -typedef std::map ConcreteParasiticSubNodeMap; -typedef std::map ConcreteParasiticPinNodeMap; -typedef std::set ParasiticNodeSet; -typedef std::set ParasiticResistorSet; -typedef std::vector ParasiticResistorSeq; +using ConcreteElmoreLoadMap = std::map; +using ConcretePoleResidueMap = std::map; +using ConcreteParasiticSubNodeMap = std::map; +using ConcreteParasiticPinNodeMap = std::map; +using ParasiticNodeSet = std::set; +using ParasiticResistorSet = std::set; +using ParasiticResistorSeq = std::vector; // Empty base class definitions so casts are not required on returned // objects. @@ -76,22 +77,22 @@ public: virtual bool isPoleResidue() const; virtual bool isParasiticNetwork() const; virtual void piModel(float &c2, - float &rpi, - float &c1) const; + float &rpi, + float &c1) const; virtual void setPiModel(float c2, - float rpi, - float c1); + float rpi, + float c1); virtual bool isReducedParasiticNetwork() const; virtual void setIsReduced(bool reduced); virtual void findElmore(const Pin *load_pin, - float &elmore, - bool &exists) const; + float &elmore, + bool &exists) const; virtual void setElmore(const Pin *load_pin, - float elmore); + float elmore); virtual Parasitic *findPoleResidue(const Pin *load_pin) const; virtual void setPoleResidue(const Pin *load_pin, - ComplexFloatSeq *poles, - ComplexFloatSeq *residues); + ComplexFloatSeq *poles, + ComplexFloatSeq *residues); virtual PinSet unannotatedLoads(const Pin *drvr_pin, const Parasitics *parasitics) const = 0; }; @@ -101,15 +102,15 @@ class ConcretePi { public: ConcretePi(float c2, - float rpi, - float c1); + float rpi, + float c1); float capacitance() const; void piModel(float &c2, - float &rpi, - float &c1) const; + float &rpi, + float &c1) const; void setPiModel(float c2, - float rpi, - float c1); + float rpi, + float c1); bool isReducedParasiticNetwork() const { return is_reduced_; } void setIsReduced(bool reduced); @@ -122,12 +123,12 @@ protected: // Pi model for a driver pin and the elmore delay to each load. class ConcretePiElmore : public ConcretePi, - public ConcreteParasitic + public ConcreteParasitic { public: ConcretePiElmore(float c2, - float rpi, - float c1); + float rpi, + float c1); bool isPiElmore() const override { return true; } bool isPiModel() const override { return true; } float capacitance() const override; @@ -147,6 +148,7 @@ public: PinSet unannotatedLoads(const Pin *drvr_pin, const Parasitics *parasitics) const override; void deleteLoad(const Pin *load_pin); + ConcreteElmoreLoadMap &loads() { return loads_; } private: ConcreteElmoreLoadMap loads_; @@ -177,42 +179,44 @@ private: // Pi model for a driver pin and the pole/residues to each load. class ConcretePiPoleResidue : public ConcretePi, - public ConcreteParasitic + public ConcreteParasitic { public: ConcretePiPoleResidue(float c2, - float rpi, - float c1); + float rpi, + float c1); virtual bool isPiPoleResidue() const override { return true; } virtual bool isPiModel() const override { return true; } virtual float capacitance() const override; virtual void piModel(float &c2, - float &rpi, - float &c1) const override; + float &rpi, + float &c1) const override; virtual void setPiModel(float c2, - float rpi, - float c1) override; + float rpi, + float c1) override; virtual bool isReducedParasiticNetwork() const override; virtual void setIsReduced(bool reduced) override; virtual Parasitic *findPoleResidue(const Pin *load_pin) const override; virtual void setPoleResidue(const Pin *load_pin, - ComplexFloatSeq *poles, - ComplexFloatSeq *residues) override; + ComplexFloatSeq *poles, + ComplexFloatSeq *residues) override; virtual PinSet unannotatedLoads(const Pin *drvr_pin, const Parasitics *parasitics) const override; void deleteLoad(const Pin *load_pin); + ConcretePoleResidueMap &loadResidues() { return load_pole_residue_; } private: ConcretePoleResidueMap load_pole_residue_; }; class ConcreteParasiticNetwork : public ParasiticNetwork, - public ConcreteParasitic + public ConcreteParasitic { public: ConcreteParasiticNetwork(const Net *net, bool includes_pin_caps, const Network *network); + ConcreteParasiticNetwork(ConcreteParasiticNetwork &¶sitic); virtual ~ConcreteParasiticNetwork(); virtual bool isParasiticNetwork() const { return true; } const Net *net() const { return net_; } @@ -221,7 +225,7 @@ public: int id, const Network *network) const; ConcreteParasiticNode *ensureParasiticNode(const Net *net, - int id, + int id, const Network *network); ConcreteParasiticNode *findParasiticNode(const Pin *pin) const; ConcreteParasiticNode *ensureParasiticNode(const Pin *pin, @@ -229,7 +233,7 @@ public: virtual float capacitance() const; ParasiticNodeSeq nodes() const; void disconnectPin(const Pin *pin, - const Net *net, + const Net *net, const Network *network); ParasiticResistorSeq resistors() const { return resistors_; } void addResistor(ParasiticResistor *resistor); diff --git a/parasitics/EstimateParasitics.cc b/parasitics/EstimateParasitics.cc index 5f656cfb..415a7f1c 100644 --- a/parasitics/EstimateParasitics.cc +++ b/parasitics/EstimateParasitics.cc @@ -42,20 +42,21 @@ EstimateParasitics::EstimateParasitics(StaState *sta) : // loads when driven by a different pin. void EstimateParasitics::estimatePiElmore(const Pin *drvr_pin, - const RiseFall *rf, - const Wireload *wireload, - float fanout, - float net_pin_cap, - const Corner *corner, - const MinMax *min_max, - float &c2, - float &rpi, - float &c1, - float &elmore_res, - float &elmore_cap, - bool &elmore_use_load_cap) + const RiseFall *rf, + const Wireload *wireload, + float fanout, + float net_pin_cap, + const Scene *scene, + const MinMax *min_max, + float &c2, + float &rpi, + float &c1, + float &elmore_res, + float &elmore_cap, + bool &elmore_use_load_cap) { - const OperatingConditions *op_cond = sdc_->operatingConditions(min_max); + const Sdc *sdc = scene->sdc(); + const OperatingConditions *op_cond = sdc->operatingConditions(min_max); float wireload_cap, wireload_res; wireload->findWireload(fanout, op_cond, wireload_cap, wireload_res); @@ -65,22 +66,22 @@ EstimateParasitics::estimatePiElmore(const Pin *drvr_pin, switch (tree) { case WireloadTree::worst_case: estimatePiElmoreWorst(drvr_pin, wireload_cap, wireload_res, - fanout, net_pin_cap, rf, corner, min_max, - c2, rpi, c1, elmore_res, - elmore_cap, elmore_use_load_cap); + fanout, net_pin_cap, rf, scene, min_max, + c2, rpi, c1, elmore_res, + elmore_cap, elmore_use_load_cap); break; case WireloadTree::balanced: case WireloadTree::unknown: estimatePiElmoreBalanced(drvr_pin, wireload_cap, wireload_res, - fanout, net_pin_cap, rf, corner, min_max, - c2, rpi, c1, elmore_res, - elmore_cap, elmore_use_load_cap); + fanout, net_pin_cap, rf, scene, min_max, + c2, rpi, c1, elmore_res, + elmore_cap, elmore_use_load_cap); break; case WireloadTree::best_case: estimatePiElmoreBest(drvr_pin, wireload_cap, net_pin_cap, - rf, corner, min_max, - c2, rpi, c1, elmore_res, elmore_cap, - elmore_use_load_cap); + rf, scene, min_max, + c2, rpi, c1, elmore_res, elmore_cap, + elmore_use_load_cap); break; } } @@ -88,17 +89,17 @@ EstimateParasitics::estimatePiElmore(const Pin *drvr_pin, // No wire resistance, so load is lumped capacitance. void EstimateParasitics::estimatePiElmoreBest(const Pin *, - float wireload_cap, - float net_pin_cap, - const RiseFall *, - const Corner *, - const MinMax *, - float &c2, - float &rpi, - float &c1, - float &elmore_res, - float &elmore_cap, - bool &elmore_use_load_cap) const + float wireload_cap, + float net_pin_cap, + const RiseFall *, + const Scene *, + const MinMax *, + float &c2, + float &rpi, + float &c1, + float &elmore_res, + float &elmore_cap, + bool &elmore_use_load_cap) const { c2 = wireload_cap + net_pin_cap; rpi = 0.0; @@ -112,22 +113,23 @@ EstimateParasitics::estimatePiElmoreBest(const Pin *, // the resistor. void EstimateParasitics::estimatePiElmoreWorst(const Pin *drvr_pin, - float wireload_cap, - float wireload_res, - float, - float net_pin_cap, - const RiseFall *rf, - const Corner *corner, - const MinMax *min_max, - float &c2, - float &rpi, - float &c1, - float &elmore_res, - float &elmore_cap, - bool &elmore_use_load_cap) + float wireload_cap, + float wireload_res, + float, + float net_pin_cap, + const RiseFall *rf, + const Scene *scene, + const MinMax *min_max, + float &c2, + float &rpi, + float &c1, + float &elmore_res, + float &elmore_cap, + bool &elmore_use_load_cap) { + const Sdc *sdc = scene->sdc(); float drvr_pin_cap = 0.0; - drvr_pin_cap = sdc_->pinCapacitance(drvr_pin, rf, corner, min_max); + drvr_pin_cap = sdc->pinCapacitance(drvr_pin, rf, scene, min_max); c2 = drvr_pin_cap; rpi = wireload_res; c1 = net_pin_cap - drvr_pin_cap + wireload_cap; @@ -141,19 +143,19 @@ EstimateParasitics::estimatePiElmoreWorst(const Pin *drvr_pin, // Use O'Brien/Savarino reduction to rspf (pi elmore) model. void EstimateParasitics::estimatePiElmoreBalanced(const Pin *drvr_pin, - float wireload_cap, - float wireload_res, - float fanout, - float net_pin_cap, - const RiseFall *rf, - const Corner *corner, - const MinMax *min_max, - float &c2, - float &rpi, - float &c1, - float &elmore_res, - float &elmore_cap, - bool &elmore_use_load_cap) + float wireload_cap, + float wireload_res, + float fanout, + float net_pin_cap, + const RiseFall *rf, + const Scene *scene, + const MinMax *min_max, + float &c2, + float &rpi, + float &c1, + float &elmore_res, + float &elmore_cap, + bool &elmore_use_load_cap) { if (wireload_res == 0.0 || fanout == 0.0) { @@ -172,7 +174,8 @@ EstimateParasitics::estimatePiElmoreBalanced(const Pin *drvr_pin, double y1 = 0.0; double y2 = 0.0; double y3 = 0.0; - y1 = sdc_->pinCapacitance(drvr_pin, rf, corner, min_max); + const Sdc *sdc = scene->sdc(); + y1 = sdc->pinCapacitance(drvr_pin, rf, scene, min_max); PinConnectedPinIterator *load_iter = network_->connectedPinIterator(drvr_pin); while (load_iter->hasNext()) { @@ -181,11 +184,11 @@ EstimateParasitics::estimatePiElmoreBalanced(const Pin *drvr_pin, double cap = 0.0; // Bidirects don't count themselves as loads. if (load_pin == drvr_pin) - cap = sdc_->portExtCap(port, rf, corner, min_max); + cap = sdc->portExtCap(port, rf, min_max); else if (network_->isLeaf(load_pin)) - cap = sdc_->pinCapacitance(load_pin, rf, corner, min_max) + cap_fanout; + cap = sdc->pinCapacitance(load_pin, rf, scene, min_max) + cap_fanout; else if (network_->isTopLevelPort(load_pin)) - cap = sdc_->portExtCap(port, rf, corner, min_max) + cap_fanout; + cap = sdc->portExtCap(port, rf, min_max) + cap_fanout; double y2_ = res_fanout * cap * cap; y1 += cap; y2 += -y2_; @@ -224,7 +227,7 @@ selectWireload(Network *network) static float instanceArea(Instance *inst, - Network *network) + Network *network) { float area = 0.0; LeafInstanceIterator *inst_iter = network->leafInstanceIterator(); diff --git a/parasitics/EstimateParasitics.hh b/parasitics/EstimateParasitics.hh index 689183ea..a6adf42e 100644 --- a/parasitics/EstimateParasitics.hh +++ b/parasitics/EstimateParasitics.hh @@ -32,7 +32,7 @@ namespace sta { -class Corner; +class Scene; class StaState; class EstimateParasitics : public StaState @@ -41,58 +41,58 @@ public: EstimateParasitics(StaState *sta); // Helper function for wireload estimation. void estimatePiElmore(const Pin *drvr_pin, - const RiseFall *rf, - const Wireload *wireload, - float fanout, - float net_pin_cap, - const Corner *corner, - const MinMax *min_max, - // Return values. - float &c2, - float &rpi, - float &c1, - float &elmore_res, - float &elmore_cap, - bool &elmore_use_load_cap); + const RiseFall *rf, + const Wireload *wireload, + float fanout, + float net_pin_cap, + const Scene *scene, + const MinMax *min_max, + // Return values. + float &c2, + float &rpi, + float &c1, + float &elmore_res, + float &elmore_cap, + bool &elmore_use_load_cap); protected: void estimatePiElmoreBest(const Pin *drvr_pin, - float net_pin_cap, - float wireload_cap, - const RiseFall *rf, - const Corner *corner, - const MinMax *min_max, - // Return values. - float &c2, - float &rpi, - float &c1, - float &elmore_res, - float &elmore_cap, - bool &elmore_use_load_cap) const; + float net_pin_cap, + float wireload_cap, + const RiseFall *rf, + const Scene *scene, + const MinMax *min_max, + // Return values. + float &c2, + float &rpi, + float &c1, + float &elmore_res, + float &elmore_cap, + bool &elmore_use_load_cap) const; void estimatePiElmoreWorst(const Pin *drvr_pin, - float wireload_cap, - float wireload_res, - float fanout, - float net_pin_cap, - const RiseFall *rf, - const Corner *corner, - const MinMax *min_max, - // Return values. - float &c2, float &rpi, float &c1, - float &elmore_res, float &elmore_cap, - bool &elmore_use_load_cap); + float wireload_cap, + float wireload_res, + float fanout, + float net_pin_cap, + const RiseFall *rf, + const Scene *scene, + const MinMax *min_max, + // Return values. + float &c2, float &rpi, float &c1, + float &elmore_res, float &elmore_cap, + bool &elmore_use_load_cap); void estimatePiElmoreBalanced(const Pin *drvr_pin, - float wireload_cap, - float wireload_res, - float fanout, - float net_pin_cap, - const RiseFall *rf, - const Corner *corner, - const MinMax *min_max, - // Return values. - float &c2, float &rpi, float &c1, - float &elmore_res, float &elmore_cap, - bool &elmore_use_load_cap); + float wireload_cap, + float wireload_res, + float fanout, + float net_pin_cap, + const RiseFall *rf, + const Scene *scene, + const MinMax *min_max, + // Return values. + float &c2, float &rpi, float &c1, + float &elmore_res, float &elmore_cap, + bool &elmore_use_load_cap); }; } // namespace diff --git a/parasitics/Parasitics.cc b/parasitics/Parasitics.cc index 400e9239..cd7da4e3 100644 --- a/parasitics/Parasitics.cc +++ b/parasitics/Parasitics.cc @@ -32,7 +32,7 @@ #include "Network.hh" #include "PortDirection.hh" #include "Sdc.hh" -#include "Corner.hh" +#include "Scene.hh" #include "ReduceParasitics.hh" #include "EstimateParasitics.hh" @@ -182,26 +182,24 @@ Parasitic * Parasitics::reduceToPiElmore(const Parasitic *parasitic, const Pin *drvr_pin, const RiseFall *rf, - const Corner *corner, - const MinMax *cnst_min_max, - const ParasiticAnalysisPt *ap) + const Scene *scene, + const MinMax *min_max) { - return sta::reduceToPiElmore(parasitic, drvr_pin, rf, ap->couplingCapFactor(), - corner, cnst_min_max, ap, this); + return sta::reduceToPiElmore(parasitic, drvr_pin, rf, + coupling_cap_factor_, + scene, min_max, this); } Parasitic * Parasitics::reduceToPiPoleResidue2(const Parasitic *parasitic, const Pin *drvr_pin, const RiseFall *rf, - const Corner *corner, - const MinMax *cnst_min_max, - const ParasiticAnalysisPt *ap) + const Scene *scene, + const MinMax *min_max) { return sta::reduceToPiPoleResidue2(parasitic, drvr_pin, rf, - ap->couplingCapFactor(), - corner, cnst_min_max, - ap, this); + coupling_cap_factor_, + scene, min_max, this); } //////////////////////////////////////////////////////////////// @@ -212,27 +210,27 @@ Parasitics::estimatePiElmore(const Pin *drvr_pin, const Wireload *wireload, float fanout, float net_pin_cap, - const Corner *corner, + const Scene *scene, const MinMax *min_max) { EstimateParasitics estimate(this); float c2, rpi, c1, elmore_res, elmore_cap; bool elmore_use_load_cap; estimate.estimatePiElmore(drvr_pin, rf, wireload, fanout, net_pin_cap, - corner, min_max, + scene, min_max, c2, rpi, c1, elmore_res, elmore_cap, elmore_use_load_cap); if (c1 > 0.0 || c2 > 0.0) { - ParasiticAnalysisPt *ap = corner->findParasiticAnalysisPt(min_max); - Parasitic *parasitic = makePiElmore(drvr_pin, rf, ap, c2, rpi, c1); + Parasitic *parasitic = makePiElmore(drvr_pin, rf, min_max, c2, rpi, c1); + const Sdc *sdc = scene->sdc(); NetConnectedPinIterator *pin_iter = network_->connectedPinIterator(drvr_pin); while (pin_iter->hasNext()) { const Pin *pin = pin_iter->next(); if (network_->isLoad(pin)) { float load_cap = 0.0; if (elmore_use_load_cap) - load_cap = sdc_->pinCapacitance(pin, rf, corner, min_max); + load_cap = sdc->pinCapacitance(pin, rf, scene, min_max); float elmore = elmore_res * (elmore_cap + load_cap); setElmore(parasitic, pin, elmore); } @@ -248,16 +246,17 @@ Parasitics::estimatePiElmore(const Pin *drvr_pin, Parasitic * Parasitics::makeWireloadNetwork(const Pin *drvr_pin, - const Wireload *wireload, - float fanout, - const MinMax *min_max, - const ParasiticAnalysisPt *ap) + const Wireload *wireload, + float fanout, + const Scene *scene, + const MinMax *min_max) { Parasitic *parasitic = nullptr; const Net *net = findParasiticNet(drvr_pin); if (net) { - parasitic = makeParasiticNetwork(net, false, ap); - const OperatingConditions *op_cond = sdc_->operatingConditions(min_max); + parasitic = makeParasiticNetwork(net, false); + const Sdc *sdc = scene->sdc(); + const OperatingConditions *op_cond = sdc->operatingConditions(min_max); float wireload_cap, wireload_res; wireload->findWireload(fanout, op_cond, wireload_cap, wireload_res); @@ -287,23 +286,23 @@ Parasitics::makeWireloadNetwork(const Pin *drvr_pin, // the resistor. void Parasitics::makeWireloadNetworkWorst(Parasitic *parasitic, - const Pin *drvr_pin, + const Pin *drvr_pin, const Net *net, - float wireload_cap, - float wireload_res, - float /* fanout */) + float wireload_cap, + float wireload_res, + float /* fanout */) { ParasiticNode *drvr_node = ensureParasiticNode(parasitic, drvr_pin, network_); size_t resistor_index = 1; ParasiticNode *load_node = ensureParasiticNode(parasitic, net, 0, network_); makeResistor(parasitic, resistor_index++, wireload_res, drvr_node, load_node); - parasitics_->incrCap(load_node, wireload_cap); + incrCap(load_node, wireload_cap); PinConnectedPinIterator *load_iter = network_->connectedPinIterator(drvr_pin); while (load_iter->hasNext()) { const Pin *load_pin = load_iter->next(); if (load_pin != drvr_pin - && network_->isLoad(load_pin)) { + && network_->isLoad(load_pin)) { ParasiticNode *load_node1 = ensureParasiticNode(parasitic, load_pin, network_); makeResistor(parasitic, resistor_index++, 0.0, load_node, load_node1); } @@ -313,20 +312,20 @@ Parasitics::makeWireloadNetworkWorst(Parasitic *parasitic, // No wire resistance, so load is lumped capacitance. void Parasitics::makeWireloadNetworkBest(Parasitic *parasitic, - const Pin *drvr_pin, - float wireload_cap, - float /* wireload_res */, - float /* fanout */) + const Pin *drvr_pin, + float wireload_cap, + float /* wireload_res */, + float /* fanout */) { ParasiticNode *drvr_node = ensureParasiticNode(parasitic, drvr_pin, network_); - parasitics_->incrCap(drvr_node, wireload_cap); + incrCap(drvr_node, wireload_cap); PinConnectedPinIterator *load_iter = network_->connectedPinIterator(drvr_pin); size_t resistor_index = 1; while (load_iter->hasNext()) { const Pin *load_pin = load_iter->next(); if (load_pin != drvr_pin - && network_->isLoad(load_pin)) { + && network_->isLoad(load_pin)) { ParasiticNode *load_node1 = ensureParasiticNode(parasitic, load_pin, network_); makeResistor(parasitic, resistor_index++, 0.0, drvr_node, load_node1); } @@ -337,10 +336,10 @@ Parasitics::makeWireloadNetworkBest(Parasitic *parasitic, // connecting it to the driver. void Parasitics::makeWireloadNetworkBalanced(Parasitic *parasitic, - const Pin *drvr_pin, - float wireload_cap, - float wireload_res, - float fanout) + const Pin *drvr_pin, + float wireload_cap, + float wireload_res, + float fanout) { float fanout_cap = wireload_cap / fanout; float fanout_res = wireload_res / fanout; @@ -351,34 +350,28 @@ Parasitics::makeWireloadNetworkBalanced(Parasitic *parasitic, while (load_iter->hasNext()) { const Pin *load_pin = load_iter->next(); if (load_pin != drvr_pin - && network_->isLoad(load_pin)) { + && network_->isLoad(load_pin)) { ParasiticNode *load_node1 = ensureParasiticNode(parasitic, load_pin, network_); makeResistor(parasitic, resistor_index++, fanout_res, drvr_node, load_node1); - parasitics_->incrCap(load_node1, fanout_cap); + incrCap(load_node1, fanout_cap); } } } -//////////////////////////////////////////////////////////////// - -ParasiticAnalysisPt::ParasiticAnalysisPt(const char *name, - int index, - int index_max) : - name_(name), - index_(index), - index_max_(index_max), - coupling_cap_factor_(1.0) -{ -} - void -ParasiticAnalysisPt::setCouplingCapFactor(float factor) +Parasitics::setCouplingCapFactor(float factor) { coupling_cap_factor_ = factor; } //////////////////////////////////////////////////////////////// +ParasiticNodeLess::ParasiticNodeLess() : + parasitics_(nullptr), + network_(nullptr) +{ +} + ParasiticNodeLess::ParasiticNodeLess(const Parasitics *parasitics, const Network *network) : parasitics_(parasitics), @@ -386,12 +379,6 @@ ParasiticNodeLess::ParasiticNodeLess(const Parasitics *parasitics, { } -ParasiticNodeLess::ParasiticNodeLess(const ParasiticNodeLess &less) : - parasitics_(less.parasitics_), - network_(less.network_) -{ -} - bool ParasiticNodeLess::operator()(const ParasiticNode *node1, const ParasiticNode *node2) const diff --git a/parasitics/Parasitics.i b/parasitics/Parasitics.i index 2854d38e..548b5014 100644 --- a/parasitics/Parasitics.i +++ b/parasitics/Parasitics.i @@ -38,31 +38,33 @@ using sta::Pin; %inline %{ bool -read_spef_cmd(const char *filename, - Instance *instance, - const Corner *corner, +read_spef_cmd(const char *name, + const char *filename, + Instance *instance, + Scene *scene, const MinMaxAll *min_max, - bool pin_cap_included, - bool keep_coupling_caps, - float coupling_cap_factor, - bool reduce) + bool pin_cap_included, + bool keep_coupling_caps, + float coupling_cap_factor, + bool reduce) { - return Sta::sta()->readSpef(filename, instance, corner, min_max, - pin_cap_included, keep_coupling_caps, + return Sta::sta()->readSpef(name, filename, instance, + scene, min_max, + pin_cap_included, keep_coupling_caps, coupling_cap_factor, reduce); } void -report_parasitic_annotation_cmd(bool report_unannotated, - const Corner *corner) +report_parasitic_annotation_cmd(const char *spef_name, + bool report_unannotated) { - Sta::sta()->reportParasiticAnnotation(report_unannotated, corner); + Sta::sta()->reportParasiticAnnotation(spef_name, report_unannotated); } FloatSeq find_pi_elmore(Pin *drvr_pin, - RiseFall *rf, - MinMax *min_max) + RiseFall *rf, + MinMax *min_max) { float c2, rpi, c1; bool exists; @@ -78,9 +80,9 @@ find_pi_elmore(Pin *drvr_pin, float find_elmore(Pin *drvr_pin, - Pin *load_pin, - RiseFall *rf, - MinMax *min_max) + Pin *load_pin, + RiseFall *rf, + MinMax *min_max) { float elmore = 0.0; bool exists; @@ -90,21 +92,21 @@ find_elmore(Pin *drvr_pin, void set_pi_model_cmd(Pin *drvr_pin, - RiseFall *rf, - MinMaxAll *min_max, - float c2, - float rpi, - float c1) + RiseFall *rf, + MinMaxAll *min_max, + float c2, + float rpi, + float c1) { Sta::sta()->makePiElmore(drvr_pin, rf, min_max, c2, rpi, c1); } void set_elmore_cmd(Pin *drvr_pin, - Pin *load_pin, - RiseFall *rf, - MinMaxAll *min_max, - float elmore) + Pin *load_pin, + RiseFall *rf, + MinMaxAll *min_max, + float elmore) { Sta::sta()->setElmore(drvr_pin, load_pin, rf, min_max, elmore); } diff --git a/parasitics/Parasitics.tcl b/parasitics/Parasitics.tcl index 15e8e81d..2b4ce36e 100644 --- a/parasitics/Parasitics.tcl +++ b/parasitics/Parasitics.tcl @@ -25,7 +25,8 @@ namespace eval sta { define_cmd_args "read_spef" \ - {[-corner corner]\ + {[-name spef_name] + [-corner corner]\ [-min]\ [-max]\ [-path path]\ @@ -33,16 +34,19 @@ define_cmd_args "read_spef" \ [-keep_capacitive_coupling]\ [-coupling_reduction_factor factor]\ [-reduce]\ - [-delete_after_reduce]\ filename} +# -scene/-min/-max are for compatibilty, Deprecated 11/21/2025 proc_redirect read_spef { parse_key_args "read_spef" args \ - keys {-path -coupling_reduction_factor -corner -name} \ + keys {-name -path -coupling_reduction_factor -corner} \ flags {-min -max -increment -pin_cap_included -keep_capacitive_coupling -reduce} - check_argc_eq1 "read_spef" $args - set reduce [info exists flags(-reduce)] + check_argc_eq1 "read_spef" $args + set name "" + if [info exists keys(-name)] { + set name $keys(-name) + } set instance [top_instance] if [info exists keys(-path)] { set path $keys(-path) @@ -51,7 +55,7 @@ proc_redirect read_spef { sta_error 276 "path instance '$path' not found." } } - set corner [parse_corner_or_all keys] + set scene [parse_scene_or_null keys] set min_max [parse_min_max_all_flags flags] set coupling_reduction_factor 1.0 if [info exists keys(-coupling_reduction_factor)] { @@ -60,22 +64,28 @@ proc_redirect read_spef { } set keep_coupling_caps [info exists flags(-keep_capacitive_coupling)] set pin_cap_included [info exists flags(-pin_cap_included)] + set reduce [info exists flags(-reduce)] set filename [file nativename [lindex $args 0]] - return [read_spef_cmd $filename $instance $corner $min_max \ - $pin_cap_included $keep_coupling_caps \ + return [read_spef_cmd $name $filename $instance $scene $min_max \ + $pin_cap_included $keep_coupling_caps \ $coupling_reduction_factor $reduce] } -define_cmd_args "report_parasitic_annotation" {[-report_unannotated]} +define_cmd_args "report_parasitic_annotation" {[-name spef_name]\ + [-report_unannotated]} proc_redirect report_parasitic_annotation { parse_key_args "report_parasitic_annotation" args \ - keys {} flags {-report_unannotated} + keys {-name} flags {-report_unannotated} check_argc_eq0 "report_parasitic_annotation" $args + set spef_name "" + if { [info exists keys(-name)] } { + set spef_name $keys(-name) + } set report_unannotated [info exists flags(-report_unannotated)] - report_parasitic_annotation_cmd $report_unannotated [sta::cmd_corner] + report_parasitic_annotation_cmd $spef_name $report_unannotated } # set_pi_model [-min] [-max] drvr_pin c2 rpi c1 diff --git a/parasitics/ReduceParasitics.cc b/parasitics/ReduceParasitics.cc index 7f2f4ef1..1650f8e3 100644 --- a/parasitics/ReduceParasitics.cc +++ b/parasitics/ReduceParasitics.cc @@ -24,23 +24,26 @@ #include "ReduceParasitics.hh" +#include +#include + #include "Error.hh" #include "Debug.hh" #include "MinMax.hh" #include "Liberty.hh" #include "Network.hh" #include "Sdc.hh" -#include "Corner.hh" +#include "Scene.hh" #include "Parasitics.hh" namespace sta { using std::max; -typedef Map ParasiticNodeValueMap; -typedef Map ResistorCurrentMap; -typedef Set ParasiticResistorSet; -typedef Set ParasiticNodeSet; +typedef std::map ParasiticNodeValueMap; +typedef std::map ResistorCurrentMap; +typedef std::set ParasiticResistorSet; +typedef std::set ParasiticNodeSet; class ReduceToPi : public StaState { @@ -48,43 +51,42 @@ public: ReduceToPi(StaState *sta); void reduceToPi(const Parasitic *parasitic_network, const Pin *drvr_pin, - ParasiticNode *drvr_node, - float coupling_cap_factor, - const RiseFall *rf, - const Corner *corner, - const MinMax *min_max, - const ParasiticAnalysisPt *ap, - float &c2, - float &rpi, - float &c1); + ParasiticNode *drvr_node, + float coupling_cap_factor, + const RiseFall *rf, + const Scene *scene, + const MinMax *min_max, + float &c2, + float &rpi, + float &c1); bool pinCapsOneValue() { return pin_caps_one_value_; } protected: void reducePiDfs(const Pin *drvr_pin, - ParasiticNode *node, - ParasiticResistor *from_res, + ParasiticNode *node, + ParasiticResistor *from_res, double src_resistance, - double &y1, - double &y2, - double &y3, - double &dwn_cap, + double &y1, + double &y2, + double &y3, + double &dwn_cap, double &max_resistance); void visit(ParasiticNode *node); bool isVisited(ParasiticNode *node); void leave(ParasiticNode *node); void setDownstreamCap(ParasiticNode *node, - float cap); + float cap); float downstreamCap(ParasiticNode *node); float pinCapacitance(ParasiticNode *node); bool isLoopResistor(ParasiticResistor *resistor); void markLoopResistor(ParasiticResistor *resistor); + Parasitics *parasitics_; bool includes_pin_caps_; float coupling_cap_multiplier_; const RiseFall *rf_; - const Corner *corner_; + const Scene *scene_; const MinMax *min_max_; - const ParasiticAnalysisPt *ap_; ParasiticNodeResistorMap resistor_map_; ParasiticNodeCapacitorMap capacitor_map_; @@ -98,7 +100,7 @@ ReduceToPi::ReduceToPi(StaState *sta) : StaState(sta), coupling_cap_multiplier_(1.0), rf_(nullptr), - corner_(nullptr), + scene_(nullptr), min_max_(nullptr), pin_caps_one_value_(true) { @@ -111,22 +113,21 @@ ReduceToPi::ReduceToPi(StaState *sta) : void ReduceToPi::reduceToPi(const Parasitic *parasitic_network, const Pin *drvr_pin, - ParasiticNode *drvr_node, - float coupling_cap_factor, - const RiseFall *rf, - const Corner *corner, - const MinMax *min_max, - const ParasiticAnalysisPt *ap, - float &c2, - float &rpi, - float &c1) + ParasiticNode *drvr_node, + float coupling_cap_factor, + const RiseFall *rf, + const Scene *scene, + const MinMax *min_max, + float &c2, + float &rpi, + float &c1) { - includes_pin_caps_ = parasitics_->includesPinCaps(parasitic_network), coupling_cap_multiplier_ = coupling_cap_factor; rf_ = rf; - corner_ = corner; + scene_ = scene; min_max_ = min_max; - ap_ = ap; + parasitics_ = scene_->parasitics(min_max); + includes_pin_caps_ = parasitics_->includesPinCaps(parasitic_network), resistor_map_ = parasitics_->parasiticNodeResistorMap(parasitic_network); capacitor_map_ = parasitics_->parasiticNodeCapacitorMap(parasitic_network); @@ -154,13 +155,13 @@ ReduceToPi::reduceToPi(const Parasitic *parasitic_network, // Find admittance moments. void ReduceToPi::reducePiDfs(const Pin *drvr_pin, - ParasiticNode *node, - ParasiticResistor *from_res, - double src_resistance, - double &y1, - double &y2, - double &y3, - double &dwn_cap, + ParasiticNode *node, + ParasiticResistor *from_res, + double src_resistance, + double &y1, + double &y2, + double &y3, + double &dwn_cap, double &max_resistance) { double coupling_cap = 0.0; @@ -220,14 +221,15 @@ ReduceToPi::pinCapacitance(ParasiticNode *node) if (pin) { Port *port = network_->port(pin); LibertyPort *lib_port = network_->libertyPort(port); + const Sdc *sdc = scene_->sdc(); if (lib_port) { if (!includes_pin_caps_) { - pin_cap = sdc_->pinCapacitance(pin, rf_, corner_, min_max_); - pin_caps_one_value_ &= lib_port->capacitanceIsOneValue(); + pin_cap = sdc->pinCapacitance(pin, rf_, scene_, min_max_); + pin_caps_one_value_ &= lib_port->capacitanceIsOneValue(); } } else if (network_->isTopLevelPort(pin)) - pin_cap = sdc_->portExtCap(port, rf_, corner_, min_max_); + pin_cap = sdc->portExtCap(port, rf_, min_max_); } return pin_cap; } @@ -241,7 +243,7 @@ ReduceToPi::visit(ParasiticNode *node) bool ReduceToPi::isVisited(ParasiticNode *node) { - return visited_nodes_.hasKey(node); + return visited_nodes_.contains(node); } void @@ -253,7 +255,7 @@ ReduceToPi::leave(ParasiticNode *node) bool ReduceToPi::isLoopResistor(ParasiticResistor *resistor) { - return loop_resistors_.hasKey(resistor); + return loop_resistors_.contains(resistor); } void @@ -264,7 +266,7 @@ ReduceToPi::markLoopResistor(ParasiticResistor *resistor) void ReduceToPi::setDownstreamCap(ParasiticNode *node, - float cap) + float cap) { node_values_[node] = cap; } @@ -286,27 +288,25 @@ public: ParasiticNode *drvr_node, float coupling_cap_factor, const RiseFall *rf, - const Corner *corner, - const MinMax *min_max, - const ParasiticAnalysisPt *ap); + const Scene *scene, + const MinMax *min_max); void reduceElmoreDfs(const Pin *drvr_pin, - ParasiticNode *node, - ParasiticResistor *from_res, - double elmore, - Parasitic *pi_elmore); + ParasiticNode *node, + ParasiticResistor *from_res, + double elmore, + Parasitic *pi_elmore); }; Parasitic * reduceToPiElmore(const Parasitic *parasitic_network, - const Pin *drvr_pin, + const Pin *drvr_pin, const RiseFall *rf, float coupling_cap_factor, - const Corner *corner, - const MinMax *min_max, - const ParasiticAnalysisPt *ap, - StaState *sta) + const Scene *scene, + const MinMax *min_max, + StaState *sta) { - Parasitics *parasitics = sta->parasitics(); + Parasitics *parasitics = scene->parasitics(min_max); ParasiticNode *drvr_node = parasitics->findParasiticNode(parasitic_network, drvr_pin); if (drvr_node) { @@ -316,8 +316,7 @@ reduceToPiElmore(const Parasitic *parasitic_network, min_max->to_string().c_str()); ReduceToPiElmore reducer(sta); return reducer.makePiElmore(parasitic_network, drvr_pin, drvr_node, - coupling_cap_factor, rf, corner, - min_max, ap); + coupling_cap_factor, rf, scene, min_max); } return nullptr; } @@ -329,19 +328,18 @@ ReduceToPiElmore::ReduceToPiElmore(StaState *sta) : Parasitic * ReduceToPiElmore::makePiElmore(const Parasitic *parasitic_network, - const Pin *drvr_pin, - ParasiticNode *drvr_node, - float coupling_cap_factor, - const RiseFall *rf, - const Corner *corner, - const MinMax *min_max, - const ParasiticAnalysisPt *ap) + const Pin *drvr_pin, + ParasiticNode *drvr_node, + float coupling_cap_factor, + const RiseFall *rf, + const Scene *scene, + const MinMax *min_max) { float c2, rpi, c1; reduceToPi(parasitic_network, drvr_pin, drvr_node, coupling_cap_factor, - rf, corner, min_max, ap, c2, rpi, c1); - Parasitic *pi_elmore = parasitics_->makePiElmore(drvr_pin, rf, ap, - c2, rpi, c1); + rf, scene, min_max, c2, rpi, c1); + Parasitic *pi_elmore = parasitics_->makePiElmore(drvr_pin, rf, min_max, + c2, rpi, c1); parasitics_->setIsReducedParasiticNetwork(pi_elmore, true); reduceElmoreDfs(drvr_pin, drvr_node, 0, 0.0, pi_elmore); return pi_elmore; @@ -351,10 +349,10 @@ ReduceToPiElmore::makePiElmore(const Parasitic *parasitic_network, // set by reducePiDfs. void ReduceToPiElmore::reduceElmoreDfs(const Pin *drvr_pin, - ParasiticNode *node, - ParasiticResistor *from_res, - double elmore, - Parasitic *pi_elmore) + ParasiticNode *node, + ParasiticResistor *from_res, + double elmore, + Parasitic *pi_elmore) { const Pin *pin = parasitics_->pin(node); if (from_res && pin) { @@ -389,42 +387,41 @@ public: ~ReduceToPiPoleResidue2(); void findPolesResidues(const Parasitic *parasitic_network, Parasitic *pi_pole_residue, - const Pin *drvr_pin, - ParasiticNode *drvr_node); + const Pin *drvr_pin, + ParasiticNode *drvr_node); Parasitic *makePiPoleResidue2(const Parasitic *parasitic_network, const Pin *drvr_pin, ParasiticNode *drvr_node, float coupling_cap_factor, const RiseFall *rf, - const Corner *corner, - const MinMax *min_max, - const ParasiticAnalysisPt *ap); + const Scene *scene, + const MinMax *min_max); private: void findMoments(const Pin *drvr_pin, - ParasiticNode *drvr_node, - int moment_count); + ParasiticNode *drvr_node, + int moment_count); void findMoments(const Pin *drvr_pin, - ParasiticNode *node, - double from_volt, - ParasiticResistor *from_res, - int moment_index); + ParasiticNode *node, + double from_volt, + ParasiticResistor *from_res, + int moment_index); double findBranchCurrents(const Pin *drvr_pin, - ParasiticNode *node, - ParasiticResistor *from_res, - int moment_index); + ParasiticNode *node, + ParasiticResistor *from_res, + int moment_index); double moment(ParasiticNode *node, - int moment_index); + int moment_index); void setMoment(ParasiticNode *node, - double moment, - int moment_index); + double moment, + int moment_index); double current(ParasiticResistor *res); void setCurrent(ParasiticResistor *res, - double i); + double i); void findPolesResidues(Parasitic *pi_pole_residue, - const Pin *drvr_pin, - const Pin *load_pin, - ParasiticNode *load_node); + const Pin *drvr_pin, + const Pin *load_pin, + ParasiticNode *load_node); // Resistor/capacitor currents. ResistorCurrentMap currents_; @@ -449,15 +446,14 @@ ReduceToPiPoleResidue2::ReduceToPiPoleResidue2(StaState *sta) : // Design Automation Conference, 1996, pg 611-616. Parasitic * reduceToPiPoleResidue2(const Parasitic *parasitic_network, - const Pin *drvr_pin, + const Pin *drvr_pin, const RiseFall *rf, - float coupling_cap_factor, - const Corner *corner, - const MinMax *min_max, - const ParasiticAnalysisPt *ap, - StaState *sta) + float coupling_cap_factor, + const Scene *scene, + const MinMax *min_max, + StaState *sta) { - Parasitics *parasitics = sta->parasitics(); + Parasitics *parasitics = scene->parasitics(min_max); ParasiticNode *drvr_node = parasitics->findParasiticNode(parasitic_network, drvr_pin); if (drvr_node) { @@ -466,28 +462,27 @@ reduceToPiPoleResidue2(const Parasitic *parasitic_network, ReduceToPiPoleResidue2 reducer(sta); return reducer.makePiPoleResidue2(parasitic_network, drvr_pin, drvr_node, coupling_cap_factor, rf, - corner, min_max, ap); + scene, min_max); } return nullptr; } Parasitic * ReduceToPiPoleResidue2::makePiPoleResidue2(const Parasitic *parasitic_network, - const Pin *drvr_pin, - ParasiticNode *drvr_node, - float coupling_cap_factor, - const RiseFall *rf, - const Corner *corner, - const MinMax *min_max, - const ParasiticAnalysisPt *ap) + const Pin *drvr_pin, + ParasiticNode *drvr_node, + float coupling_cap_factor, + const RiseFall *rf, + const Scene *scene, + const MinMax *min_max) { float c2, rpi, c1; reduceToPi(parasitic_network, drvr_pin, drvr_node, - coupling_cap_factor, rf, corner, min_max, ap, - c2, rpi, c1); + coupling_cap_factor, rf, scene, min_max, + c2, rpi, c1); Parasitic *pi_pole_residue = parasitics_->makePiPoleResidue(drvr_pin, - rf, ap, - c2, rpi, c1); + rf, min_max, + c2, rpi, c1); parasitics_->setIsReducedParasiticNetwork(pi_pole_residue, true); findPolesResidues(parasitic_network, pi_pole_residue, drvr_pin, drvr_node); return pi_pole_residue; @@ -501,8 +496,8 @@ ReduceToPiPoleResidue2::~ReduceToPiPoleResidue2() void ReduceToPiPoleResidue2::findPolesResidues(const Parasitic *parasitic_network, Parasitic *pi_pole_residue, - const Pin *drvr_pin, - ParasiticNode *drvr_node) + const Pin *drvr_pin, + ParasiticNode *drvr_node) { moments_ = new ParasiticNodeValueMap[4]; findMoments(drvr_pin, drvr_node, 4); @@ -514,7 +509,7 @@ ReduceToPiPoleResidue2::findPolesResidues(const Parasitic *parasitic_network, ParasiticNode *load_node = parasitics_->findParasiticNode(parasitic_network, pin); if (load_node) { - findPolesResidues(pi_pole_residue, drvr_pin, pin, load_node); + findPolesResidues(pi_pole_residue, drvr_pin, pin, load_node); } } } @@ -523,8 +518,8 @@ ReduceToPiPoleResidue2::findPolesResidues(const Parasitic *parasitic_network, void ReduceToPiPoleResidue2::findMoments(const Pin *drvr_pin, - ParasiticNode *drvr_node, - int moment_count) + ParasiticNode *drvr_node, + int moment_count) { // Driver model thevenin resistance. double rd = 0.0; @@ -541,9 +536,9 @@ ReduceToPiPoleResidue2::findMoments(const Pin *drvr_pin, double ReduceToPiPoleResidue2::findBranchCurrents(const Pin *drvr_pin, - ParasiticNode *node, - ParasiticResistor *from_res, - int moment_index) + ParasiticNode *node, + ParasiticResistor *from_res, + int moment_index) { visit(node); double branch_i = 0.0; @@ -577,10 +572,10 @@ ReduceToPiPoleResidue2::findBranchCurrents(const Pin *drvr_pin, void ReduceToPiPoleResidue2::findMoments(const Pin *drvr_pin, - ParasiticNode *node, - double from_volt, - ParasiticResistor *from_res, - int moment_index) + ParasiticNode *node, + double from_volt, + ParasiticResistor *from_res, + int moment_index) { visit(node); ParasiticResistorSeq &resistors = resistor_map_[node]; @@ -607,7 +602,7 @@ ReduceToPiPoleResidue2::findMoments(const Pin *drvr_pin, double ReduceToPiPoleResidue2::moment(ParasiticNode *node, - int moment_index) + int moment_index) { // Zero'th moments are all 1. if (moment_index == 0) @@ -620,8 +615,8 @@ ReduceToPiPoleResidue2::moment(ParasiticNode *node, void ReduceToPiPoleResidue2::setMoment(ParasiticNode *node, - double moment, - int moment_index) + double moment, + int moment_index) { // Zero'th moments are all 1. if (moment_index > 0) { @@ -638,16 +633,16 @@ ReduceToPiPoleResidue2::current(ParasiticResistor *res) void ReduceToPiPoleResidue2::setCurrent(ParasiticResistor *res, - double i) + double i) { currents_[res] = i; } void ReduceToPiPoleResidue2::findPolesResidues(Parasitic *pi_pole_residue, - const Pin *, - const Pin *load_pin, - ParasiticNode *load_node) + const Pin *, + const Pin *load_pin, + ParasiticNode *load_node) { double m1 = moment(load_node, 1); double m2 = moment(load_node, 2); diff --git a/parasitics/ReduceParasitics.hh b/parasitics/ReduceParasitics.hh index 84a51e64..283822f7 100644 --- a/parasitics/ReduceParasitics.hh +++ b/parasitics/ReduceParasitics.hh @@ -29,7 +29,7 @@ namespace sta { -class Corner; +class Scene; class Parasitic; class ParasiticAnalysisPt; class StaState; @@ -37,24 +37,22 @@ class StaState; // Reduce parasitic network to pi elmore model for drvr_pin. Parasitic * reduceToPiElmore(const Parasitic *parasitic_network, - const Pin *drvr_pin, + const Pin *drvr_pin, const RiseFall *rf, - float coupling_cap_factor, - const Corner *corner, - const MinMax *min_max, - const ParasiticAnalysisPt *ap, - StaState *sta); + float coupling_cap_factor, + const Scene *scene, + const MinMax *min_max, + StaState *sta); // Reduce parasitic network to pi and 2nd order pole/residue models // for drvr_pin. Parasitic * reduceToPiPoleResidue2(const Parasitic *parasitic_network, - const Pin *drvr_pin, + const Pin *drvr_pin, const RiseFall *rf, - float coupling_cap_factor, - const Corner *corner, - const MinMax *min_max, - const ParasiticAnalysisPt *ap, - StaState *sta); + float coupling_cap_factor, + const Scene *scene, + const MinMax *min_max, + StaState *sta); } // namespace diff --git a/parasitics/ReportParasiticAnnotation.cc b/parasitics/ReportParasiticAnnotation.cc index d27ac0f4..dc327468 100644 --- a/parasitics/ReportParasiticAnnotation.cc +++ b/parasitics/ReportParasiticAnnotation.cc @@ -24,14 +24,14 @@ #include "ReportParasiticAnnotation.hh" +#include "ContainerHelpers.hh" #include "Report.hh" #include "Network.hh" #include "NetworkCmp.hh" #include "PortDirection.hh" #include "Graph.hh" -#include "Corner.hh" +#include "Scene.hh" #include "Parasitics.hh" -#include "DcalcAnalysisPt.hh" #include "ArcDelayCalc.hh" namespace sta { @@ -39,8 +39,9 @@ namespace sta { class ReportParasiticAnnotation : public StaState { public: - ReportParasiticAnnotation(bool report_unannotated, - const Corner *corner, + ReportParasiticAnnotation(Parasitics *parasitics, + bool report_unannotated, + const Scene *scene, StaState *sta); void report(); @@ -50,31 +51,34 @@ private: void findCounts(Instance *inst); void findCounts(Net *net); + Parasitics *parasitics_; bool report_unannotated_; - const Corner *corner_; + const Scene *scene_; const MinMax *min_max_; - const ParasiticAnalysisPt *parasitic_ap_; PinSeq unannotated_; PinSeq partially_annotated_; }; void -reportParasiticAnnotation(bool report_unannotated, - const Corner *corner, +reportParasiticAnnotation(Parasitics *parasitics, + bool report_unannotated, + const Scene *scene, StaState *sta) { - ReportParasiticAnnotation report_annotation(report_unannotated, corner, sta); + ReportParasiticAnnotation report_annotation(parasitics, report_unannotated, + scene, sta); report_annotation.report(); } -ReportParasiticAnnotation::ReportParasiticAnnotation(bool report_unannotated, - const Corner *corner, +ReportParasiticAnnotation::ReportParasiticAnnotation(Parasitics *parasitics, + bool report_unannotated, + const Scene *scene, StaState *sta) : StaState(sta), + parasitics_(parasitics), report_unannotated_(report_unannotated), - corner_(corner), - min_max_(MinMax::max()), - parasitic_ap_(corner_->findParasiticAnalysisPt(min_max_)) + scene_(scene), + min_max_(MinMax::max()) { } @@ -102,7 +106,7 @@ ReportParasiticAnnotation::reportAnnotationCounts() for (const Pin *drvr_pin : partially_annotated_) { report_->reportLine(" %s", network_->pathName(drvr_pin)); - Parasitic *parasitic = parasitics_->findParasiticNetwork(drvr_pin, parasitic_ap_); + Parasitic *parasitic = parasitics_->findParasiticNetwork(drvr_pin); if (parasitic) { PinSet unannotated_loads = parasitics_->unannotatedLoads(parasitic, drvr_pin); for (const Pin *load_pin : unannotated_loads) @@ -115,7 +119,6 @@ ReportParasiticAnnotation::reportAnnotationCounts() void ReportParasiticAnnotation::findCounts() { - DcalcAnalysisPt *dcalc_ap = corner_->findDcalcAnalysisPt(min_max_); VertexIterator vertex_iter(graph_); while (vertex_iter.hasNext()) { Vertex *vertex = vertex_iter.next(); @@ -123,9 +126,10 @@ ReportParasiticAnnotation::findCounts() PortDirection *dir = network_->direction(pin); if (vertex->isDriver(network_) && !dir->isInternal()) { - Parasitic *parasitic = parasitics_->findParasiticNetwork(pin, parasitic_ap_); + Parasitic *parasitic = parasitics_->findParasiticNetwork(pin); if (parasitic == nullptr) - parasitic = arc_delay_calc_->findParasitic(pin, RiseFall::rise(), dcalc_ap); + parasitic = arc_delay_calc_->findParasitic(pin, RiseFall::rise(), + scene_, min_max_); if (parasitic) { PinSet unannotated_loads = parasitics_->unannotatedLoads(parasitic, pin); if (unannotated_loads.size() > 0) diff --git a/parasitics/ReportParasiticAnnotation.hh b/parasitics/ReportParasiticAnnotation.hh index eb446c05..a3c7e6a8 100644 --- a/parasitics/ReportParasiticAnnotation.hh +++ b/parasitics/ReportParasiticAnnotation.hh @@ -26,12 +26,14 @@ namespace sta { +class Parasitics; class StaState; -class Corner; +class Scene; void -reportParasiticAnnotation(bool report_unannotated, - const Corner *corner, +reportParasiticAnnotation(Parasitics *parasitics, + bool report_unannotated, + const Scene *scene, StaState *sta); } // namespace diff --git a/parasitics/SpefNamespace.cc b/parasitics/SpefNamespace.cc index b9178a1f..e9c1ab7d 100644 --- a/parasitics/SpefNamespace.cc +++ b/parasitics/SpefNamespace.cc @@ -32,7 +32,7 @@ namespace sta { char * spefToSta(const char *token, char spef_divider, - char path_divider, + char path_divider, char path_escape) { const char spef_escape = '\\'; @@ -44,21 +44,21 @@ spefToSta(const char *token, if (ch == spef_escape) { char next_ch = s[1]; if (next_ch == spef_divider) { - // Translate spef escape to network escape. - *t++ = path_escape; - // Translate spef divider to network divider. - *t++ = path_divider; + // Translate spef escape to network escape. + *t++ = path_escape; + // Translate spef divider to network divider. + *t++ = path_divider; } else if (next_ch == '[' - || next_ch == ']' - || next_ch == spef_escape) { - // Translate spef escape to network escape. - *t++ = path_escape; - *t++ = next_ch; + || next_ch == ']' + || next_ch == spef_escape) { + // Translate spef escape to network escape. + *t++ = path_escape; + *t++ = next_ch; } else - // No need to escape other characters. - *t++ = next_ch; + // No need to escape other characters. + *t++ = next_ch; s++; } else if (ch == spef_divider) @@ -75,7 +75,7 @@ spefToSta(const char *token, char * staToSpef(const char *token, char spef_divider, - char path_divider, + char path_divider, char path_escape) { const char spef_escape = '\\'; @@ -87,20 +87,20 @@ staToSpef(const char *token, if (ch == path_escape) { char next_ch = s[1]; if (next_ch == path_divider) { - // Translate network escape to spef escape. - *t++ = spef_escape; - // Translate network divider to spef divider. - *t++ = spef_divider; + // Translate network escape to spef escape. + *t++ = spef_escape; + // Translate network divider to spef divider. + *t++ = spef_divider; } else if (next_ch == '[' - || next_ch == ']') { - // Translate network escape to spef escape. - *t++ = spef_escape; - *t++ = next_ch; + || next_ch == ']') { + // Translate network escape to spef escape. + *t++ = spef_escape; + *t++ = next_ch; } else - // No need to escape other characters. - *t++ = next_ch; + // No need to escape other characters. + *t++ = next_ch; s++; } else if (ch == path_divider) diff --git a/parasitics/SpefNamespace.hh b/parasitics/SpefNamespace.hh index 15f47ded..17b15046 100644 --- a/parasitics/SpefNamespace.hh +++ b/parasitics/SpefNamespace.hh @@ -30,12 +30,12 @@ namespace sta { // Caller owns the result string. char * spefToSta(const char *token, char spef_divider, - char path_escape, char path_divider); + char path_escape, char path_divider); // Translate from sta namespace to spf/spef namespace. // Caller owns the result string. char * staToSpef(const char *token, char spef_divider, - char path_divider, char path_escape); + char path_divider, char path_escape); } // namespace diff --git a/parasitics/SpefParse.yy b/parasitics/SpefParse.yy index b8fbb0c2..39ad246f 100755 --- a/parasitics/SpefParse.yy +++ b/parasitics/SpefParse.yy @@ -41,7 +41,7 @@ void sta::SpefParse::error(const location_type &loc, const std::string &msg) { - reader->report()->fileError(164,reader->filename(), + reader->report()->fileError(164,reader->filename().c_str(), loc.begin.line,"%s",msg.c_str()); } %} diff --git a/parasitics/SpefReader.cc b/parasitics/SpefReader.cc index e81d691f..b27efe6c 100644 --- a/parasitics/SpefReader.cc +++ b/parasitics/SpefReader.cc @@ -29,14 +29,13 @@ #include "Report.hh" #include "Debug.hh" #include "StringUtil.hh" -#include "Map.hh" #include "Transition.hh" #include "Liberty.hh" #include "Network.hh" #include "PortDirection.hh" #include "Sdc.hh" #include "Parasitics.hh" -#include "Corner.hh" +#include "Scene.hh" #include "ArcDelayCalc.hh" #include "SpefReaderPvt.hh" #include "SpefNamespace.hh" @@ -47,42 +46,42 @@ namespace sta { using std::string; bool -readSpefFile(const char *filename, - Instance *instance, - ParasiticAnalysisPt *ap, - bool pin_cap_included, - bool keep_coupling_caps, - float coupling_cap_factor, - bool reduce, - const Corner *corner, - const MinMaxAll *min_max, +readSpefFile(const std::string &filename, + Instance *instance, + bool pin_cap_included, + bool keep_coupling_caps, + float coupling_cap_factor, + bool reduce, + const Scene *scene, + const MinMaxAll *min_max, + Parasitics *parasitics, StaState *sta) { - SpefReader reader(filename, instance, ap, - pin_cap_included, keep_coupling_caps, coupling_cap_factor, - reduce, corner, min_max, sta); + SpefReader reader(filename, instance, pin_cap_included, + keep_coupling_caps, coupling_cap_factor, + reduce, scene, min_max, parasitics, sta); bool success = reader.read(); return success; } -SpefReader::SpefReader(const char *filename, - Instance *instance, - ParasiticAnalysisPt *ap, - bool pin_cap_included, - bool keep_coupling_caps, - float coupling_cap_factor, - bool reduce, - const Corner *corner, - const MinMaxAll *min_max, - StaState *sta) : +SpefReader::SpefReader(const std::string &filename, + Instance *instance, + bool pin_cap_included, + bool keep_coupling_caps, + float coupling_cap_factor, + bool reduce, + const Scene *scene, + const MinMaxAll *min_max, + Parasitics *parasitics, + StaState *sta) : StaState(sta), filename_(filename), instance_(instance), - ap_(ap), pin_cap_included_(pin_cap_included), keep_coupling_caps_(keep_coupling_caps), + coupling_cap_factor_(coupling_cap_factor), reduce_(reduce), - corner_(corner), + scene_(scene), min_max_(min_max), // defaults divider_('\0'), @@ -96,9 +95,10 @@ SpefReader::SpefReader(const char *filename, res_scale_(1.0), induct_scale_(1.0), design_flow_(nullptr), + parasitics_(parasitics), parasitic_(nullptr) { - ap->setCouplingCapFactor(coupling_cap_factor); + parasitics->setCouplingCapFactor(coupling_cap_factor); } SpefReader::~SpefReader() @@ -114,7 +114,7 @@ bool SpefReader::read() { bool success; - gzstream::igzstream stream(filename_); + gzstream::igzstream stream(filename_.c_str()); if (stream.is_open()) { Stats stats(debug_, report_); SpefScanner scanner(&stream, filename_, this, report_); @@ -126,7 +126,7 @@ SpefReader::read() stats.report("Read spef"); } else - throw FileNotReadable(filename_); + throw FileNotReadable(filename_.c_str()); return success; } @@ -147,11 +147,11 @@ SpefReader::setBusBrackets(char left, char right) { if (!((left == '[' && right == ']') - || (left == '{' && right == '}') - || (left == '(' && right == ')') - || (left == '<' && right == '>') - || (left == ':' && right == '\0') - || (left == '.' && right == '\0'))) + || (left == '{' && right == '}') + || (left == '(' && right == ')') + || (left == '<' && right == '>') + || (left == ':' && right == '\0') + || (left == '.' && right == '\0'))) warn(1640, "illegal bus delimiters."); bus_brkt_left_ = left; bus_brkt_right_ = right; @@ -190,7 +190,7 @@ char * SpefReader::translated(const char *token) { return spefToSta(token, divider_, network_->pathDivider(), - network_->pathEscape()); + network_->pathEscape()); } void @@ -198,13 +198,13 @@ SpefReader::warn(int id, const char *fmt, ...) { va_list args; va_start(args, fmt); - report_->vfileWarn(id, filename_, scanner_->line(), fmt, args); + report_->vfileWarn(id, filename_.c_str(), scanner_->line(), fmt, args); va_end(args); } void SpefReader::setTimeScale(float scale, - const char *units) + const char *units) { if (stringEq(units, "NS")) time_scale_ = scale * 1E-9F; @@ -217,7 +217,7 @@ SpefReader::setTimeScale(float scale, void SpefReader::setCapScale(float scale, - const char *units) + const char *units) { if (stringEq(units, "PF")) cap_scale_ = scale * 1E-12F; @@ -230,7 +230,7 @@ SpefReader::setCapScale(float scale, void SpefReader::setResScale(float scale, - const char *units) + const char *units) { if (stringEq(units, "OHM")) res_scale_ = scale; @@ -243,7 +243,7 @@ SpefReader::setResScale(float scale, void SpefReader::setInductScale(float scale, - const char *units) + const char *units) { if (stringEq(units, "HENRY")) induct_scale_ = scale; @@ -258,7 +258,7 @@ SpefReader::setInductScale(float scale, void SpefReader::makeNameMapEntry(const char *index, - const char *name) + const char *name) { int i = atoi(index + 1); name_map_[i] = name; @@ -330,7 +330,7 @@ SpefReader::findPin(char *name) else { pin = findPortPinRelative(name); if (pin == nullptr) - warn(1649, "pin %s not found.", name); + warn(1649, "pin %s not found.", name); } } return pin; @@ -351,10 +351,10 @@ SpefReader::findNet(const char *name) void SpefReader::rspfBegin(Net *net, - SpefTriple *total_cap) + SpefTriple *total_cap) { if (net) - parasitics_->deleteParasitics(net, ap_); + parasitics_->deleteParasitics(net); // Net total capacitance is ignored. delete total_cap; } @@ -366,14 +366,16 @@ SpefReader::rspfFinish() void SpefReader::rspfDrvrBegin(Pin *drvr_pin, - SpefRspfPi *pi) + SpefRspfPi *pi) { if (drvr_pin) { float c2 = pi->c2()->value(triple_index_) * cap_scale_; float rpi = pi->r1()->value(triple_index_) * res_scale_; float c1 = pi->c1()->value(triple_index_) * cap_scale_; // Only one parasitic, save it under rise transition. - parasitic_ = parasitics_->makePiElmore(drvr_pin, RiseFall::rise(), ap_, + parasitic_ = parasitics_->makePiElmore(drvr_pin, + RiseFall::rise(), + MinMax::max(), c2, rpi, c1); } delete pi; @@ -381,7 +383,7 @@ SpefReader::rspfDrvrBegin(Pin *drvr_pin, void SpefReader::rspfLoad(Pin *load_pin, - SpefTriple *rc) + SpefTriple *rc) { if (parasitic_ && load_pin) { float elmore = rc->value(triple_index_) * time_scale_; @@ -399,12 +401,12 @@ SpefReader::rspfDrvrFinish() // Net cap (total_cap) is ignored. void SpefReader::dspfBegin(Net *net, - SpefTriple *total_cap) + SpefTriple *total_cap) { if (net) { if (network_->isTopInstance(instance_)) { - parasitics_->deleteReducedParasitics(net, ap_); - parasitic_ = parasitics_->makeParasiticNetwork(net, pin_cap_included_, ap_); + parasitics_->deleteReducedParasitics(net); + parasitic_ = parasitics_->makeParasiticNetwork(net, pin_cap_included_); } else { Net *parasitic_owner = net; @@ -415,10 +417,10 @@ SpefReader::dspfBegin(Net *net, parasitic_owner = network_->net(hpin); } delete term_iter; - parasitic_ = parasitics_->findParasiticNetwork(parasitic_owner, ap_); + parasitic_ = parasitics_->findParasiticNetwork(parasitic_owner); if (parasitic_ == nullptr) parasitic_ = parasitics_->makeParasiticNetwork(parasitic_owner, - pin_cap_included_, ap_); + pin_cap_included_); } net_ = net; } @@ -433,8 +435,8 @@ void SpefReader::dspfFinish() { if (parasitic_ && reduce_) { - arc_delay_calc_->reduceParasitic(parasitic_, net_, corner_, min_max_); - parasitics_->deleteParasiticNetwork(net_, ap_); + arc_delay_calc_->reduceParasitic(parasitic_, net_, scene_, min_max_); + parasitics_->deleteParasiticNetwork(net_); } parasitic_ = nullptr; net_ = nullptr; @@ -442,7 +444,7 @@ SpefReader::dspfFinish() ParasiticNode * SpefReader::findParasiticNode(char *name, - bool local_only) + bool local_only) { if (name && parasitic_) { char *delim = strrchr(name, delimiter_); @@ -459,7 +461,7 @@ SpefReader::findParasiticNode(char *name, if (local_only && !network_->isConnected(net_, pin)) warn(1651, "%s not connected to net %s.", - name1, sdc_network_->pathName(net_)); + name1, sdc_network_->pathName(net_)); return parasitics_->ensureParasiticNode(parasitic_, pin, network_); } else { @@ -513,7 +515,7 @@ SpefReader::findParasiticNode(char *name, void SpefReader::makeCapacitor(int, char *node_name, - SpefTriple *cap) + SpefTriple *cap) { ParasiticNode *node = findParasiticNode(node_name, true); if (node) { @@ -526,9 +528,9 @@ SpefReader::makeCapacitor(int, char *node_name, void SpefReader::makeCapacitor(int id, - char *node_name1, - char *node_name2, - SpefTriple *cap) + char *node_name1, + char *node_name2, + SpefTriple *cap) { ParasiticNode *node1 = findParasiticNode(node_name1, false); ParasiticNode *node2 = findParasiticNode(node_name2, false); @@ -537,7 +539,7 @@ SpefReader::makeCapacitor(int id, if (keep_coupling_caps_) parasitics_->makeCapacitor(parasitic_, id, cap1, node1, node2); else { - float scaled_cap = cap1 * ap_->couplingCapFactor(); + float scaled_cap = cap1 * coupling_cap_factor_; if (node1 && parasitics_->net(node1, network_) == net_) parasitics_->incrCap(node1, scaled_cap); if (node2 && parasitics_->net(node2, network_) == net_) @@ -551,9 +553,9 @@ SpefReader::makeCapacitor(int id, void SpefReader::makeResistor(int id, - char *node_name1, - char *node_name2, - SpefTriple *res) + char *node_name1, + char *node_name2, + SpefTriple *res) { ParasiticNode *node1 = findParasiticNode(node_name1, true); ParasiticNode *node2 = findParasiticNode(node_name2, true); @@ -569,8 +571,8 @@ SpefReader::makeResistor(int id, //////////////////////////////////////////////////////////////// SpefRspfPi::SpefRspfPi(SpefTriple *c2, - SpefTriple *r1, - SpefTriple *c1) : + SpefTriple *r1, + SpefTriple *c1) : c2_(c2), r1_(r1), c1_(c1) @@ -593,8 +595,8 @@ SpefTriple::SpefTriple(float value) : } SpefTriple::SpefTriple(float value1, - float value2, - float value3) : + float value2, + float value3) : is_triple_(true) { values_[0] = value1; diff --git a/parasitics/SpefReader.hh b/parasitics/SpefReader.hh index 3e391348..a3cae771 100644 --- a/parasitics/SpefReader.hh +++ b/parasitics/SpefReader.hh @@ -24,6 +24,8 @@ #pragma once +#include + #include "Zlib.hh" #include "MinMax.hh" #include "ParasiticsClass.hh" @@ -32,25 +34,24 @@ namespace sta { class ParasiticAnalysisPt; class Instance; -class Corner; +class Scene; class OperatingConditions; class StaState; // Read a file single value parasitics into analysis point ap. // In a Spef file with triplet values the first value is used. -// Constraint min/max cnst_min_max and operating condition op_cond -// are used for parasitic network reduction. +// Min/max and operating condition op_cond are used for parasitic network reduction. // Return true if successful. bool -readSpefFile(const char *filename, - Instance *instance, - ParasiticAnalysisPt *ap, - bool pin_cap_included, - bool keep_coupling_caps, - float coupling_cap_factor, - bool reduce, - const Corner *corner, - const MinMaxAll *min_max, - StaState *sta); +readSpefFile(const std::string &filename, + Instance *instance, + bool pin_cap_included, + bool keep_coupling_caps, + float coupling_cap_factor, + bool reduce, + const Scene *scene, + const MinMaxAll *min_max, + Parasitics *parasirics, + StaState *sta); } // namespace diff --git a/parasitics/SpefReaderPvt.hh b/parasitics/SpefReaderPvt.hh index 033a3431..f96480c4 100644 --- a/parasitics/SpefReaderPvt.hh +++ b/parasitics/SpefReaderPvt.hh @@ -38,23 +38,23 @@ class Report; class MinMaxAll; class SpefRspfPi; class SpefTriple; -class Corner; +class Scene; class SpefScanner; -typedef std::map SpefNameMap; +using SpefNameMap = std::map; class SpefReader : public StaState { public: - SpefReader(const char *filename, - Instance *instance, - ParasiticAnalysisPt *ap, - bool pin_cap_included, - bool keep_coupling_caps, - float coupling_cap_factor, - bool reduce, - const Corner *corner, - const MinMaxAll *min_max, + SpefReader(const std::string &filename, + Instance *instance, + bool pin_cap_included, + bool keep_coupling_caps, + float coupling_cap_factor, + bool reduce, + const Scene *scene, + const MinMaxAll *min_max, + Parasitics *parasitics, StaState *sta); virtual ~SpefReader(); bool read(); @@ -62,7 +62,7 @@ public: void setDivider(char divider); char delimiter() const { return delimiter_; } void setDelimiter(char delimiter); - const char *filename() const { return filename_; } + const std::string &filename() const { return filename_; } // Translate from spf/spef namespace to sta namespace. char *translated(const char *token); void warn(int id, @@ -70,43 +70,43 @@ public: ...) __attribute__((format (printf, 3, 4))); void setBusBrackets(char left, - char right); + char right); void setTimeScale(float scale, - const char *units); + const char *units); void setCapScale(float scale, - const char *units); + const char *units); void setResScale(float scale, - const char *units); + const char *units); void setInductScale(float scale, - const char *units); + const char *units); void makeNameMapEntry(const char *index, - const char *name); + const char *name); const char *nameMapLookup(const char *index); void setDesignFlow(StringSeq *flow_keys); Pin *findPin(char *name); Net *findNet(const char *name); void rspfBegin(Net *net, - SpefTriple *total_cap); + SpefTriple *total_cap); void rspfFinish(); void rspfDrvrBegin(Pin *drvr_pin, - SpefRspfPi *pi); + SpefRspfPi *pi); void rspfLoad(Pin *load_pin, - SpefTriple *rc); + SpefTriple *rc); void rspfDrvrFinish(); void dspfBegin(Net *net, - SpefTriple *total_cap); + SpefTriple *total_cap); void dspfFinish(); void makeCapacitor(int id, - char *node_name, - SpefTriple *cap); + char *node_name, + SpefTriple *cap); void makeCapacitor(int id, - char *node_name1, - char *node_name2, - SpefTriple *cap); + char *node_name1, + char *node_name2, + SpefTriple *cap); void makeResistor(int id, - char *node_name1, - char *node_name2, - SpefTriple *res); + char *node_name1, + char *node_name2, + SpefTriple *res); PortDirection *portDirection(char *spef_dir); private: @@ -117,14 +117,14 @@ private: ParasiticNode *findParasiticNode(char *name, bool local_only); - const char *filename_; + const std::string filename_; SpefScanner *scanner_; Instance *instance_; - const ParasiticAnalysisPt *ap_; bool pin_cap_included_; bool keep_coupling_caps_; + bool coupling_cap_factor_; bool reduce_; - const Corner *corner_; + const Scene *scene_; const MinMaxAll *min_max_; // Normally no need to keep device names. char divider_; @@ -140,6 +140,7 @@ private: float induct_scale_; SpefNameMap name_map_; StringSeq *design_flow_; + Parasitics *parasitics_; Parasitic *parasitic_; }; @@ -148,8 +149,8 @@ class SpefTriple public: SpefTriple(float value); SpefTriple(float value1, - float value2, - float value3); + float value2, + float value3); float value(int index) const; bool isTriple() const { return is_triple_; } diff --git a/power/Power.cc b/power/Power.cc index 3265fe96..6cc8795f 100644 --- a/power/Power.cc +++ b/power/Power.cc @@ -28,6 +28,7 @@ #include // abs #include "cudd.h" +#include "ContainerHelpers.hh" #include "Stats.hh" #include "Debug.hh" #include "EnumNameMap.hh" @@ -46,16 +47,17 @@ #include "Network.hh" #include "Clock.hh" #include "Sdc.hh" +#include "Mode.hh" #include "Graph.hh" -#include "DcalcAnalysisPt.hh" #include "GraphDelayCalc.hh" -#include "Corner.hh" +#include "Scene.hh" #include "Path.hh" #include "search/Levelize.hh" #include "search/Sim.hh" #include "Search.hh" #include "Bfs.hh" #include "ClkNetwork.hh" +#include "ReportPower.hh" // Related liberty not supported: // library @@ -96,20 +98,21 @@ static EnumNameMap pwr_activity_origin_map = Power::Power(StaState *sta) : StaState(sta), + scene_(nullptr), global_activity_(), - input_activity_(), // default set in ensureActivities() + input_activity_(), // default set in ensureActivities. seq_activity_map_(100, SeqPinHash(network_), SeqPinEqual()), activities_valid_(false), bdd_(sta), instance_powers_(InstanceIdLess(network_)), - instance_powers_valid_(false), - corner_(nullptr) + instance_powers_valid_(false) { } void Power::clear() { + scene_ = nullptr; global_activity_.init(); input_activity_.init(); user_activity_map_.clear(); @@ -117,7 +120,6 @@ Power::clear() activity_map_.clear(); activities_valid_ = false; instance_powers_.clear(); - corner_ = nullptr; } void @@ -207,7 +209,7 @@ Power::userActivity(const Pin *pin) bool Power::hasUserActivity(const Pin *pin) { - return user_activity_map_.hasKey(pin); + return user_activity_map_.contains(pin); } void @@ -231,7 +233,7 @@ Power::activity(const Pin *pin) bool Power::hasActivity(const Pin *pin) { - return activity_map_.hasKey(pin); + return activity_map_.contains(pin); } // Sequential internal pins may not be in the netlist so their @@ -249,7 +251,7 @@ bool Power::hasSeqActivity(const Instance *reg, LibertyPort *output) { - return seq_activity_map_.hasKey(SeqPin(reg, output)); + return seq_activity_map_.contains(SeqPin(reg, output)); } PwrActivity & @@ -267,21 +269,157 @@ SeqPinHash::SeqPinHash(const Network *network) : size_t SeqPinHash::operator()(const SeqPin &pin) const { - return hashSum(network_->id(pin.first), pin.second->id()); + const auto& [inst, port] = pin; + return hashSum(network_->id(inst), port->id()); } bool SeqPinEqual::operator()(const SeqPin &pin1, const SeqPin &pin2) const { - return pin1.first == pin2.first - && pin1.second == pin2.second; + const auto& [inst1, port1] = pin1; + const auto& [inst2, port2] = pin2; + return inst1 == inst2 + && port1 == port2; } //////////////////////////////////////////////////////////////// void -Power::power(const Corner *corner, +Power::reportDesign(const Scene *scene, + int digits) +{ + PowerResult total, sequential, combinational, clock, macro, pad; + power(scene, total, sequential, combinational, clock, macro, pad); + ReportPower report_power(this); + report_power.reportDesign(total, sequential, combinational, clock, macro, pad, digits); +} + +void +Power::reportInsts(const InstanceSeq &insts, + const Scene *scene, + int digits) +{ + InstPowers inst_pwrs = sortInstsByPower(insts, scene); + ReportPower report_power(this); + report_power.reportInsts(inst_pwrs, digits); +} + +void +Power::reportHighestInsts(size_t count, + const Scene *scene, + int digits) +{ + InstPowers inst_pwrs = highestInstPowers(count, scene); + ReportPower report_power(this); + report_power.reportInsts(inst_pwrs, digits); +} + +void +Power::reportDesignJson(const Scene *scene, + int digits) +{ + PowerResult total, sequential, combinational, clock, macro, pad; + power(scene, total, sequential, combinational, clock, macro, pad); + + report_->reportLine("{"); + reportPowerRowJson("Sequential", sequential, digits, ","); + reportPowerRowJson("Combinational", combinational, digits, ","); + reportPowerRowJson("Clock", clock, digits, ","); + reportPowerRowJson("Macro", macro, digits, ","); + reportPowerRowJson("Pad", pad, digits, ","); + reportPowerRowJson("Total", total, digits, ""); + report_->reportLine("}"); +} + +void +Power::reportInstsJson(const InstanceSeq &insts, + const Scene *scene, + int digits) +{ + InstPowers inst_pwrs = sortInstsByPower(insts, scene); + + report_->reportLine("["); + bool first = true; + for (const InstPower &inst_pwr : inst_pwrs) { + if (!first) { + report_->reportLine(","); + } + first = false; + reportPowerInstJson(inst_pwr.first, inst_pwr.second, digits); + } + report_->reportLine("]"); +} + +void +Power::reportPowerRowJson(const char *name, + const PowerResult &power, + int digits, + const char *separator) +{ + float internal = power.internal(); + float switching = power.switching(); + float leakage = power.leakage(); + float total = power.total(); + + report_->reportLine(" \"%s\": {", name); + report_->reportLine(" \"internal\": %.*e,", digits, internal); + report_->reportLine(" \"switching\": %.*e,", digits, switching); + report_->reportLine(" \"leakage\": %.*e,", digits, leakage); + report_->reportLine(" \"total\": %.*e", digits, total); + std::string line = " }"; + if (separator && separator[0] != '\0') + line += separator; + report_->reportLineString(line); +} + +void +Power::reportPowerInstJson(const Instance *inst, + const PowerResult &power, + int digits) +{ + float internal = power.internal(); + float switching = power.switching(); + float leakage = power.leakage(); + float total = power.total(); + + const char *inst_name = network_->pathName(inst); + report_->reportLine("{"); + report_->reportLine(" \"name\": \"%s\",", inst_name); + report_->reportLine(" \"internal\": %.*e,", digits, internal); + report_->reportLine(" \"switching\": %.*e,", digits, switching); + report_->reportLine(" \"leakage\": %.*e,", digits, leakage); + report_->reportLine(" \"total\": %.*e", digits, total); + report_->reportLine("}"); +} + +static bool +instPowerGreater(const InstPower &pwr1, + const InstPower &pwr2) +{ + return pwr1.second.total() > pwr2.second.total(); +} + +InstPowers +Power::sortInstsByPower(const InstanceSeq &insts, + const Scene *scene) +{ + // Collect instance powers. + InstPowers inst_pwrs; + for (const Instance *inst : insts) { + PowerResult inst_power = power(inst, scene); + inst_pwrs.push_back(std::make_pair(inst, inst_power)); + } + + // Sort by total power (descending) + sort(inst_pwrs, instPowerGreater); + return inst_pwrs; +} + +//////////////////////////////////////////////////////////////// + +void +Power::power(const Scene *scene, // Return values. PowerResult &total, PowerResult &sequential, @@ -297,8 +435,9 @@ Power::power(const Corner *corner, macro.clear(); pad.clear(); - ensureActivities(); - ensureInstPowers(corner); + ensureActivities(scene); + ensureInstPowers(); + ClkNetwork *clk_network = scene_->mode()->clkNetwork(); for (auto [inst, inst_power] : instance_powers_) { LibertyCell *cell = network_->libertyCell(inst); if (cell) { @@ -308,7 +447,7 @@ Power::power(const Corner *corner, macro.incr(inst_power); else if (cell->isPad()) pad.incr(inst_power); - else if (inClockNetwork(inst)) + else if (inClockNetwork(inst, clk_network)) clock.incr(inst_power); else if (cell->hasSequentials()) sequential.incr(inst_power); @@ -320,13 +459,14 @@ Power::power(const Corner *corner, } bool -Power::inClockNetwork(const Instance *inst) +Power::inClockNetwork(const Instance *inst, + const ClkNetwork *clk_network) { InstancePinIterator *pin_iter = network_->pinIterator(inst); while (pin_iter->hasNext()) { const Pin *pin = pin_iter->next(); if (network_->direction(pin)->isAnyOutput() - && !clk_network_->isClock(pin)) { + && !clk_network->isClock(pin)) { delete pin_iter; return false; } @@ -337,13 +477,13 @@ Power::inClockNetwork(const Instance *inst) PowerResult Power::power(const Instance *inst, - const Corner *corner) + const Scene *scene) { - ensureActivities(); - ensureInstPowers(corner); + ensureActivities(scene); + ensureInstPowers(); if (network_->isHierarchical(inst)) { PowerResult result; - powerInside(inst, corner, result); + powerInside(inst, scene, result); return result; } else @@ -352,66 +492,89 @@ Power::power(const Instance *inst, void Power::powerInside(const Instance *hinst, - const Corner *corner, + const Scene *scene, PowerResult &result) { InstanceChildIterator *child_iter = network_->childIterator(hinst); while (child_iter->hasNext()) { Instance *child = child_iter->next(); if (network_->isHierarchical(child)) - powerInside(child, corner, result); + powerInside(child, scene, result); else result.incr(instance_powers_[child]); } delete child_iter; } -typedef std::pair InstPower; +//////////////////////////////////////////////////////////////// -InstanceSeq -Power::highestPowerInstances(size_t count, - const Corner *corner) +InstPowers +Power::highestInstPowers(size_t count, + const Scene *scene) { - vector inst_pwrs; + InstPowers inst_pwrs; LeafInstanceIterator *inst_iter = network_->leafInstanceIterator(); while (inst_iter->hasNext()) { Instance *inst = inst_iter->next(); - PowerResult pwr = power(inst, corner); - inst_pwrs.push_back({inst, pwr.total()}); + PowerResult pwr = power(inst, scene); + inst_pwrs.push_back(std::make_pair(inst, pwr)); } delete inst_iter; - sort(inst_pwrs.begin(), inst_pwrs.end(), [](InstPower &inst_pwr1, - InstPower &inst_pwr2) { - return inst_pwr1.second > inst_pwr2.second; - }); - - InstanceSeq insts; - for (size_t i = 0; i < count; i++) - insts.push_back(inst_pwrs[i].first); - return insts; + sort(inst_pwrs, instPowerGreater); + if (inst_pwrs.size() > count) + inst_pwrs.resize(count); + return inst_pwrs; } //////////////////////////////////////////////////////////////// -class ActivitySrchPred : public SearchPredNonLatch2 +class ActivitySrchPred : public SearchPred { public: - explicit ActivitySrchPred(const StaState *sta); - virtual bool searchThru(Edge *edge); + ActivitySrchPred(const StaState *sta); + bool searchFrom(const Vertex *from_vertex, + const Mode *mode) const override; + bool searchThru(Edge *edge, + const Mode *mode) const override; + bool searchTo(const Vertex *to_vertex, + const Mode *mode) const override; }; ActivitySrchPred::ActivitySrchPred(const StaState *sta) : - SearchPredNonLatch2(sta) + SearchPred(sta) { } bool -ActivitySrchPred::searchThru(Edge *edge) +ActivitySrchPred::searchFrom(const Vertex *from_vertex, + const Mode *mode) const { + const Pin *from_pin = from_vertex->pin(); + const Sdc *sdc = mode->sdc(); + return !sdc->isDisabledConstraint(from_pin); +} + +bool +ActivitySrchPred::searchThru(Edge *edge, + const Mode *mode) const +{ + const Sdc *sdc = mode->sdc(); const TimingRole *role = edge->role(); - return SearchPredNonLatch2::searchThru(edge) - && role != TimingRole::regClkToQ(); + return !(edge->role()->isTimingCheck() + || sdc->isDisabledConstraint(edge) + || sdc->isDisabledCondDefault(edge) + || edge->isBidirectInstPath() + || edge->isDisabledLoop() + || role == TimingRole::regClkToQ() + || role->isLatchDtoQ()); +} + +bool +ActivitySrchPred::searchTo(const Vertex *, + const Mode *) const +{ + return true; } //////////////////////////////////////////////////////////////// @@ -420,44 +583,52 @@ class PropActivityVisitor : public VertexVisitor, StaState { public: PropActivityVisitor(Power *power, + const Mode *mode, BfsFwdIterator *bfs); virtual VertexVisitor *copy() const; virtual void visit(Vertex *vertex); InstanceSet &visitedRegs() { return visited_regs_; } void init(); float maxChange() const { return max_change_; } + const Pin *maxChangePin() const { return max_change_pin_; } private: bool setActivityCheck(const Pin *pin, PwrActivity &activity); - static constexpr float change_tolerance_ = .001; + static constexpr float change_tolerance_ = .01; InstanceSet visited_regs_; float max_change_; - Power *power_; + const Pin *max_change_pin_; BfsFwdIterator *bfs_; + Power *power_; + const Mode *mode_; }; PropActivityVisitor::PropActivityVisitor(Power *power, + const Mode *mode, BfsFwdIterator *bfs) : StaState(power), visited_regs_(network_), max_change_(0.0), + max_change_pin_(nullptr), + bfs_(bfs), power_(power), - bfs_(bfs) + mode_(mode) { } VertexVisitor * PropActivityVisitor::copy() const { - return new PropActivityVisitor(power_, bfs_); + return new PropActivityVisitor(power_, mode_, bfs_); } void PropActivityVisitor::init() { max_change_ = 0.0; + max_change_pin_ = nullptr; } void @@ -547,11 +718,25 @@ PropActivityVisitor::visit(Vertex *vertex) } } } - bfs_->enqueueAdjacentVertices(vertex); + bfs_->enqueueAdjacentVertices(vertex, mode_); } } } +static float +percentChange(float value, + float prev) +{ + if (prev == 0.0) { + if (value == 0.0) + return 0.0; + else + return 1.0; + } + else + return abs(value - prev) / prev; +} + // Return true if the activity changed. bool PropActivityVisitor::setActivityCheck(const Pin *pin, @@ -562,20 +747,26 @@ PropActivityVisitor::setActivityCheck(const Pin *pin, if (activity.density() > max_density) activity.setDensity(max_density); PwrActivity &prev_activity = power_->activity(pin); - float density_delta = abs(activity.density() - prev_activity.density()); - float duty_delta = abs(activity.duty() - prev_activity.duty()); - if (density_delta > change_tolerance_ - || duty_delta > change_tolerance_ - || activity.origin() != prev_activity.origin()) { - max_change_ = max(max_change_, density_delta); - max_change_ = max(max_change_, duty_delta); - power_->setActivity(pin, activity); - return true; + float density_delta = percentChange(activity.density(), + prev_activity.density()); + float duty_delta = percentChange(activity.duty(), prev_activity.duty()); + if (density_delta > max_change_) { + max_change_ = density_delta; + max_change_pin_ = pin; } - else - return false; + if (duty_delta > max_change_) { + max_change_ = duty_delta; + max_change_pin_ = pin; + } + bool changed = density_delta > change_tolerance_ + || duty_delta > change_tolerance_ + || activity.origin() != prev_activity.origin();; + power_->setActivity(pin, activity); + return changed; } +//////////////////////////////////////////////////////////////// + void Power::clockGatePins(const Instance *inst, // Return values. @@ -708,9 +899,15 @@ Power::evalBddActivity(DdNode *bdd, //////////////////////////////////////////////////////////////// void -Power::ensureActivities() +Power::ensureActivities(const Scene *scene) { Stats stats(debug_, report_); + if (scene != scene_) { + scene_ = scene; + activities_valid_ = false; + instance_powers_.clear(); + } + if (!activities_valid_) { // No need to propagate activites if global activity is set. if (!global_activity_.isSet()) { @@ -721,7 +918,7 @@ Power::ensureActivities() // Initialize default input activity (after sdc is defined) // unless it has been set by command. if (input_activity_.origin() == PwrActivityOrigin::unknown) { - float min_period = clockMinPeriod(); + float min_period = clockMinPeriod(scene_->mode()->sdc()); float density = 0.1 / (min_period != 0.0 ? min_period : units_->timeUnit()->scale()); @@ -730,7 +927,7 @@ Power::ensureActivities() ActivitySrchPred activity_srch_pred(this); BfsFwdIterator bfs(BfsIndex::other, &activity_srch_pred, this); seedActivities(bfs); - PropActivityVisitor visitor(this, &bfs); + PropActivityVisitor visitor(this, scene_->mode(), &bfs); // Propagate activities through combinational logic. bfs.visit(levelize_->maxLevel(), &visitor); // Propagate activiities through registers. @@ -745,8 +942,10 @@ Power::ensureActivities() // combinational logic. bfs.visit(levelize_->maxLevel(), &visitor); regs = std::move(visitor.visitedRegs()); - debugPrint(debug_, "power_activity", 1, "Pass %d change %.2f", - pass, visitor.maxChange()); + debugPrint(debug_, "power_activity", 1, "Pass %d change %.2f %s", + pass, + visitor.maxChange(), + network_->pathName(visitor.maxChangePin())); pass++; } } @@ -761,7 +960,7 @@ Power::seedActivities(BfsFwdIterator &bfs) for (Vertex *vertex : levelize_->roots()) { const Pin *pin = vertex->pin(); // Clock activities are baked in. - if (!sdc_->isLeafPinClock(pin) + if (!scene_->mode()->sdc()->isLeafPinClock(pin) && !network_->direction(pin)->isInternal()) { debugPrint(debug_, "power_activity", 3, "seed %s", vertex->to_string(this).c_str()); @@ -771,7 +970,7 @@ Power::seedActivities(BfsFwdIterator &bfs) // Default inputs without explicit activities to the input default. setActivity(pin, input_activity_); Vertex *vertex = graph_->pinDrvrVertex(pin); - bfs.enqueueAdjacentVertices(vertex); + bfs.enqueueAdjacentVertices(vertex, scene_->mode()); } } } @@ -851,8 +1050,8 @@ Power::seedRegOutputActivities(const Instance *reg, float clk_duty = clk_activity.duty(); FuncExpr *clk_func = seq->clock(); bool clk_invert = clk_func - && clk_func->op() == FuncExpr::op_not - && clk_func->left()->op() == FuncExpr::op_port; + && clk_func->op() == FuncExpr::Op::not_ + && clk_func->left()->op() == FuncExpr::Op::port; if (clk_invert) out_density = in_density * (1 - clk_duty); else @@ -869,17 +1068,16 @@ Power::seedRegOutputActivities(const Instance *reg, //////////////////////////////////////////////////////////////// void -Power::ensureInstPowers(const Corner *corner) +Power::ensureInstPowers() { - if (!instance_powers_valid_ - || corner != corner_) { - findInstPowers(corner); + if (!instance_powers_valid_) { + findInstPowers(); instance_powers_valid_ = true; } } void -Power::findInstPowers(const Corner *corner) +Power::findInstPowers() { Stats stats(debug_, report_); LeafInstanceIterator *inst_iter = network_->leafInstanceIterator(); @@ -887,24 +1085,23 @@ Power::findInstPowers(const Corner *corner) Instance *inst = inst_iter->next(); LibertyCell *cell = network_->libertyCell(inst); if (cell) { - PowerResult inst_power = power(inst, cell, corner); + PowerResult inst_power = power(inst, cell, scene_); instance_powers_[inst] = inst_power; } } delete inst_iter; - corner_ = corner; stats.report("Find power"); } PowerResult Power::power(const Instance *inst, LibertyCell *cell, - const Corner *corner) + const Scene *scene) { PowerResult result; - findInternalPower(inst, cell, corner, result); - findSwitchingPower(inst, cell, corner, result); - findLeakagePower(inst, cell, corner, result); + findInternalPower(inst, cell, scene, result); + findSwitchingPower(inst, cell, scene, result); + findLeakagePower(inst, cell, scene, result); return result; } @@ -928,26 +1125,25 @@ Power::findInstClk(const Instance *inst) void Power::findInternalPower(const Instance *inst, LibertyCell *cell, - const Corner *corner, + const Scene *scene, // Return values. PowerResult &result) { - const DcalcAnalysisPt *dcalc_ap = corner->findDcalcAnalysisPt(MinMax::max()); InstancePinIterator *pin_iter = network_->pinIterator(inst); while (pin_iter->hasNext()) { const Pin *to_pin = pin_iter->next(); LibertyPort *to_port = network_->libertyPort(to_pin); if (to_port) { float load_cap = to_port->direction()->isAnyOutput() - ? graph_delay_calc_->loadCap(to_pin, dcalc_ap) + ? graph_delay_calc_->loadCap(to_pin, scene, MinMax::max()) : 0.0; PwrActivity activity = findActivity(to_pin); if (to_port->direction()->isAnyOutput()) findOutputInternalPower(to_port, inst, cell, activity, - load_cap, corner, result); + load_cap, scene, result); if (to_port->direction()->isAnyInput()) findInputInternalPower(to_pin, to_port, inst, cell, activity, - load_cap, corner, result); + load_cap, scene, result); } } delete pin_iter; @@ -960,23 +1156,22 @@ Power::findInputInternalPower(const Pin *pin, LibertyCell *cell, PwrActivity &activity, float load_cap, - const Corner *corner, + const Scene *scene, // Return values. PowerResult &result) { const MinMax *min_max = MinMax::max(); - LibertyCell *corner_cell = cell->cornerCell(corner, min_max); - const LibertyPort *corner_port = port->cornerPort(corner, min_max); - if (corner_cell && corner_port) { - const InternalPowerSeq &internal_pwrs = corner_cell->internalPowers(corner_port); + LibertyCell *scene_cell = cell->sceneCell(scene, min_max); + const LibertyPort *scene_port = port->scenePort(scene, min_max); + if (scene_cell && scene_port) { + const InternalPowerSeq &internal_pwrs = scene_cell->internalPowers(scene_port); if (!internal_pwrs.empty()) { debugPrint(debug_, "power", 2, "internal input %s/%s cap %s", network_->pathName(inst), port->name(), units_->capacitanceUnit()->asString(load_cap)); debugPrint(debug_, "power", 2, " when act/ns duty energy power"); - const DcalcAnalysisPt *dcalc_ap = corner->findDcalcAnalysisPt(MinMax::max()); - const Pvt *pvt = dcalc_ap->operatingConditions(); + const Pvt *pvt = scene->sdc()->operatingConditions(MinMax::max()); Vertex *vertex = graph_->pinLoadVertex(pin); float internal = 0.0; for (InternalPower *pwr : internal_pwrs) { @@ -984,7 +1179,7 @@ Power::findInputInternalPower(const Pin *pin, float energy = 0.0; int rf_count = 0; for (const RiseFall *rf : RiseFall::range()) { - float slew = getSlew(vertex, rf, corner); + float slew = getSlew(vertex, rf, scene); if (!delayInf(slew)) { float table_energy = pwr->power(rf, pvt, slew, load_cap); energy += table_energy; @@ -996,9 +1191,9 @@ Power::findInputInternalPower(const Pin *pin, float duty = 1.0; // fallback default FuncExpr *when = pwr->when(); if (when) { - const LibertyPort *out_corner_port = findExprOutPort(when); - if (out_corner_port) { - LibertyPort *out_port = findLinkPort(cell, out_corner_port); + const LibertyPort *out_scene_port = findExprOutPort(when); + if (out_scene_port) { + LibertyPort *out_port = findLinkPort(cell, out_scene_port); if (out_port) { FuncExpr *func = out_port->function(); if (func && func->hasPort(port)) @@ -1029,14 +1224,18 @@ Power::findInputInternalPower(const Pin *pin, float Power::getSlew(Vertex *vertex, const RiseFall *rf, - const Corner *corner) + const Scene *scene) { - const DcalcAnalysisPt *dcalc_ap = corner->findDcalcAnalysisPt(MinMax::max()); + + const MinMax *min_max = MinMax::max(); const Pin *pin = vertex->pin(); - if (clk_network_->isIdealClock(pin)) - return clk_network_->idealClkSlew(pin, rf, MinMax::max()); - else - return delayAsFloat(graph_->slew(vertex, rf, dcalc_ap->index())); + const ClkNetwork *clk_network = scene->mode()->clkNetwork(); + if (clk_network->isIdealClock(pin)) + return clk_network->idealClkSlew(pin, rf, min_max); + else { + DcalcAPIndex slew_index = scene->dcalcAnalysisPtIndex(min_max); + return delayAsFloat(graph_->slew(vertex, rf, slew_index)); + } } float @@ -1047,8 +1246,9 @@ Power::getMinRfSlew(const Pin *pin) if (vertex) { const MinMax *min_max = MinMax::min(); Slew mm_slew = min_max->initValue(); - for (const DcalcAnalysisPt *dcalc_ap : corners_->dcalcAnalysisPts()) { - DcalcAPIndex ap_index = dcalc_ap->index(); + for (DcalcAPIndex ap_index = 0; + ap_index < dcalcAnalysisPtCount(); + ap_index++) { const Slew &slew1 = graph_->slew(vertex, RiseFall::rise(), ap_index); const Slew &slew2 = graph_->slew(vertex, RiseFall::fall(), ap_index); Slew slew = delayAsFloat(slew1 + slew2) / 2.0; @@ -1065,19 +1265,19 @@ Power::findExprOutPort(FuncExpr *expr) { LibertyPort *port; switch (expr->op()) { - case FuncExpr::op_port: + case FuncExpr::Op::port: port = expr->port(); if (port && port->direction()->isAnyOutput()) return expr->port(); return nullptr; - case FuncExpr::op_not: + case FuncExpr::Op::not_: port = findExprOutPort(expr->left()); if (port) return port; return nullptr; - case FuncExpr::op_or: - case FuncExpr::op_and: - case FuncExpr::op_xor: + case FuncExpr::Op::or_: + case FuncExpr::Op::and_: + case FuncExpr::Op::xor_: port = findExprOutPort(expr->left()); if (port) return port; @@ -1085,8 +1285,8 @@ Power::findExprOutPort(FuncExpr *expr) if (port) return port; return nullptr; - case FuncExpr::op_one: - case FuncExpr::op_zero: + case FuncExpr::Op::one: + case FuncExpr::Op::zero: return nullptr; } return nullptr; @@ -1098,7 +1298,7 @@ Power::findOutputInternalPower(const LibertyPort *to_port, LibertyCell *cell, PwrActivity &to_activity, float load_cap, - const Corner *corner, + const Scene *scene, // Return values. PowerResult &result) { @@ -1106,17 +1306,17 @@ Power::findOutputInternalPower(const LibertyPort *to_port, network_->pathName(inst), to_port->name(), units_->capacitanceUnit()->asString(load_cap)); - const DcalcAnalysisPt *dcalc_ap = corner->findDcalcAnalysisPt(MinMax::max()); - const Pvt *pvt = dcalc_ap->operatingConditions(); - LibertyCell *corner_cell = cell->cornerCell(dcalc_ap); - const LibertyPort *to_corner_port = to_port->cornerPort(dcalc_ap); + const MinMax *min_max = MinMax::max(); + const Pvt *pvt = scene->sdc()->operatingConditions(min_max); + LibertyCell *scene_cell = cell->sceneCell(scene, min_max); + const LibertyPort *to_scene_port = to_port->scenePort(scene, min_max); FuncExpr *func = to_port->function(); map pg_duty_sum; - for (InternalPower *pwr : corner_cell->internalPowers(to_corner_port)) { - const LibertyPort *from_corner_port = pwr->relatedPort(); - if (from_corner_port) { - const Pin *from_pin = findLinkPin(inst, from_corner_port); + for (InternalPower *pwr : scene_cell->internalPowers(to_scene_port)) { + const LibertyPort *from_scene_port = pwr->relatedPort(); + if (from_scene_port) { + const Pin *from_pin = findLinkPin(inst, from_scene_port); float from_density = findActivity(from_pin).density(); float duty = findInputDuty(inst, func, pwr); const char *related_pg_pin = pwr->relatedPgPin(); @@ -1128,17 +1328,17 @@ Power::findOutputInternalPower(const LibertyPort *to_port, debugPrint(debug_, "power", 2, " when act/ns duty wgt energy power"); float internal = 0.0; - for (InternalPower *pwr : corner_cell->internalPowers(to_corner_port)) { + for (InternalPower *pwr : scene_cell->internalPowers(to_scene_port)) { FuncExpr *when = pwr->when(); const char *related_pg_pin = pwr->relatedPgPin(); float duty = findInputDuty(inst, func, pwr); Vertex *from_vertex = nullptr; bool positive_unate = true; - const LibertyPort *from_corner_port = pwr->relatedPort(); + const LibertyPort *from_scene_port = pwr->relatedPort(); const Pin *from_pin = nullptr; - if (from_corner_port) { - positive_unate = isPositiveUnate(corner_cell, from_corner_port, to_corner_port); - from_pin = findLinkPin(inst, from_corner_port); + if (from_scene_port) { + positive_unate = isPositiveUnate(scene_cell, from_scene_port, to_scene_port); + from_pin = findLinkPin(inst, from_scene_port); if (from_pin) from_vertex = graph_->pinLoadVertex(from_pin); } @@ -1148,7 +1348,7 @@ Power::findOutputInternalPower(const LibertyPort *to_port, // Use unateness to find from_rf. const RiseFall *from_rf = positive_unate ? to_rf : to_rf->opposite(); float slew = from_vertex - ? getSlew(from_vertex, from_rf, corner) + ? getSlew(from_vertex, from_rf, scene) : 0.0; if (!delayInf(slew)) { float table_energy = pwr->power(to_rf, pvt, slew, load_cap); @@ -1169,7 +1369,7 @@ Power::findOutputInternalPower(const LibertyPort *to_port, } float port_internal = weight * energy * to_activity.density(); debugPrint(debug_, "power", 2, "%3s -> %-3s %6s %.3f %.3f %.3f %9.2e %9.2e %s", - from_corner_port ? from_corner_port->name() : "-" , + from_scene_port ? from_scene_port->name() : "-" , to_port->name(), when ? when->to_string().c_str() : "", to_activity.density() * 1e-9, @@ -1189,10 +1389,10 @@ Power::findInputDuty(const Instance *inst, InternalPower *pwr) { - const LibertyPort *from_corner_port = pwr->relatedPort(); - if (from_corner_port) { + const LibertyPort *from_scene_port = pwr->relatedPort(); + if (from_scene_port) { LibertyPort *from_port = findLinkPort(network_->libertyCell(inst), - from_corner_port); + from_scene_port); const Pin *from_pin = network_->findPin(inst, from_port); if (from_pin) { FuncExpr *when = pwr->when(); @@ -1203,7 +1403,7 @@ Power::findInputDuty(const Instance *inst, } else if (when) return evalActivity(when, inst).duty(); - else if (search_->isClock(from_vertex)) + else if (scene_->mode()->clkNetwork()->isClock(from_vertex->pin())) return 0.5; return 0.5; } @@ -1211,20 +1411,20 @@ Power::findInputDuty(const Instance *inst, return 0.0; } -// Hack to find cell port that corresponds to corner_port. +// Hack to find cell port that corresponds to scene_port. LibertyPort * Power::findLinkPort(const LibertyCell *cell, - const LibertyPort *corner_port) + const LibertyPort *scene_port) { - return cell->findLibertyPort(corner_port->name()); + return cell->findLibertyPort(scene_port->name()); } Pin * Power::findLinkPin(const Instance *inst, - const LibertyPort *corner_port) + const LibertyPort *scene_port) { const LibertyCell *cell = network_->libertyCell(inst); - LibertyPort *port = findLinkPort(cell, corner_port); + LibertyPort *port = findLinkPort(cell, scene_port); return network_->findPin(inst, port); } @@ -1248,23 +1448,22 @@ isPositiveUnate(const LibertyCell *cell, void Power::findSwitchingPower(const Instance *inst, LibertyCell *cell, - const Corner *corner, + const Scene *scene, // Return values. PowerResult &result) { - const DcalcAnalysisPt *dcalc_ap = corner->findDcalcAnalysisPt(MinMax::max()); - LibertyCell *corner_cell = cell->cornerCell(dcalc_ap); + LibertyCell *scene_cell = cell->sceneCell(scene, MinMax::max()); InstancePinIterator *pin_iter = network_->pinIterator(inst); while (pin_iter->hasNext()) { const Pin *to_pin = pin_iter->next(); const LibertyPort *to_port = network_->libertyPort(to_pin); if (to_port) { float load_cap = to_port->direction()->isAnyOutput() - ? graph_delay_calc_->loadCap(to_pin, dcalc_ap) + ? graph_delay_calc_->loadCap(to_pin, scene, MinMax::max()) : 0.0; PwrActivity activity = findActivity(to_pin); if (to_port->direction()->isAnyOutput()) { - float volt = portVoltage(corner_cell, to_port, dcalc_ap); + float volt = portVoltage(scene_cell, to_port, scene, MinMax::max()); float switching = .5 * load_cap * volt * volt * activity.density(); debugPrint(debug_, "power", 2, "switching %s/%s activity = %.2e volt = %.2f %.3e", cell->name(), @@ -1285,17 +1484,17 @@ Power::findSwitchingPower(const Instance *inst, void Power::findLeakagePower(const Instance *inst, LibertyCell *cell, - const Corner *corner, + const Scene *scene, // Return values. PowerResult &result) { - LibertyCell *corner_cell = cell->cornerCell(corner, MinMax::max()); + LibertyCell *scene_cell = cell->sceneCell(scene, MinMax::max()); float cond_leakage = 0.0; bool found_cond = false; float uncond_leakage = 0.0; bool found_uncond = false; float cond_duty_sum = 0.0; - for (LeakagePower *leak : *corner_cell->leakagePowers()) { + for (LeakagePower *leak : *scene_cell->leakagePowers()) { FuncExpr *when = leak->when(); if (when) { PwrActivity cond_activity = evalActivity(when, inst); @@ -1345,34 +1544,34 @@ Power::findLeakagePower(const Instance *inst, // External. PwrActivity -Power::pinActivity(const Pin *pin) +Power::pinActivity(const Pin *pin, + const Scene *scene) { - ensureActivities(); + ensureActivities(scene); return findActivity(pin); } PwrActivity Power::findActivity(const Pin *pin) { + const Mode *mode = scene_->mode(); Vertex *vertex = graph_->pinLoadVertex(pin); - if (vertex && vertex->isConstant()) - return PwrActivity(0.0, 0.0, PwrActivityOrigin::constant); - else if (vertex && search_->isClock(vertex)) { - if (activity_map_.hasKey(pin)) { - PwrActivity &activity = activity_map_[pin]; - if (activity.origin() != PwrActivityOrigin::unknown) - return activity; - } + if (vertex && mode->clkNetwork()->isClock(pin)) { + PwrActivity *activity = findKeyValuePtr(activity_map_, pin); + if (activity + && activity->origin() != PwrActivityOrigin::unknown) + return *activity; const Clock *clk = findClk(pin); float duty = clockDuty(clk); return PwrActivity(2.0 / clk->period(), duty, PwrActivityOrigin::clock); } else if (global_activity_.isSet()) return global_activity_; - else if (activity_map_.hasKey(pin)) { - PwrActivity &activity = activity_map_[pin]; - if (activity.origin() != PwrActivityOrigin::unknown) - return activity; + else { + PwrActivity *activity = findKeyValuePtr(activity_map_, pin); + if (activity + && activity->origin() != PwrActivityOrigin::unknown) + return *activity; } return PwrActivity(0.0, 0.0, PwrActivityOrigin::unknown); } @@ -1412,15 +1611,17 @@ Power::findSeqActivity(const Instance *inst, float Power::portVoltage(LibertyCell *cell, const LibertyPort *port, - const DcalcAnalysisPt *dcalc_ap) + const Scene *scene, + const MinMax *min_max) { - return pgNameVoltage(cell, port->relatedPowerPin(), dcalc_ap); + return pgNameVoltage(cell, port->relatedPowerPin(), scene, min_max); } float Power::pgNameVoltage(LibertyCell *cell, const char *pg_port_name, - const DcalcAnalysisPt *dcalc_ap) + const Scene *scene, + const MinMax *min_max) { if (pg_port_name) { LibertyPort *pg_port = cell->findLibertyPort(pg_port_name); @@ -1435,7 +1636,7 @@ Power::pgNameVoltage(LibertyCell *cell, } } - const Pvt *pvt = dcalc_ap->operatingConditions(); + Pvt *pvt = scene->sdc()->operatingConditions(min_max); if (pvt == nullptr) pvt = cell->libertyLibrary()->defaultOperatingConditions(); if (pvt) @@ -1502,7 +1703,7 @@ Power::reportActivityAnnotation(bool report_unannotated, PinSeq annotated_pins; for (auto const& [pin, activity] : user_activity_map_) annotated_pins.push_back(pin); - sort(annotated_pins.begin(), annotated_pins.end(), PinPathNameLess(sdc_network_)); + sort(annotated_pins, PinPathNameLess(sdc_network_)); report_->reportLine("Annotated pins:"); for (const Pin *pin : annotated_pins) { const PwrActivity &activity = user_activity_map_[pin]; @@ -1523,8 +1724,7 @@ Power::reportActivityAnnotation(bool report_unannotated, } delete inst_iter; - sort(unannotated_pins.begin(), unannotated_pins.end(), - PinPathNameLess(sdc_network_)); + sort(unannotated_pins, PinPathNameLess(sdc_network_)); report_->reportLine("Unannotated pins:"); for (const Pin *pin : unannotated_pins) { report_->reportLine(" %s", sdc_network_->pathName(pin)); @@ -1543,7 +1743,7 @@ Power::findUnannotatedPins(const Instance *inst, if (!network_->direction(pin)->isInternal() && !network_->direction(pin)->isPowerGround() && !(liberty_port && liberty_port->isPwrGnd()) - && user_activity_map_.find(pin) == user_activity_map_.end()) + && !user_activity_map_.contains(pin)) unannotated_pins.push_back(pin); } delete pin_iter; @@ -1581,12 +1781,12 @@ Power::pinCount() } float -Power::clockMinPeriod() +Power::clockMinPeriod(const Sdc *sdc) { - ClockSeq *clks = sdc_->clocks(); - if (clks && !clks->empty()) { + const ClockSeq &clks = sdc->clocks(); + if (!clks.empty()) { float min_period = INF; - for (const Clock *clk : *clks) + for (const Clock *clk : clks) min_period = min(min_period, clk->period()); return min_period; } @@ -1599,7 +1799,7 @@ Power::deleteInstanceBefore(const Instance *) { activities_valid_ = false; instance_powers_.clear(); - corner_ = nullptr; + scene_ = nullptr; } void @@ -1607,7 +1807,7 @@ Power::deletePinBefore(const Pin *) { activities_valid_ = false; instance_powers_.clear(); - corner_ = nullptr; + scene_ = nullptr; } //////////////////////////////////////////////////////////////// diff --git a/power/Power.hh b/power/Power.hh index abed2f40..83930253 100644 --- a/power/Power.hh +++ b/power/Power.hh @@ -25,9 +25,10 @@ #pragma once #include +#include +#include #include "StaConfig.hh" // CUDD -#include "UnorderedMap.hh" #include "Network.hh" #include "SdcClass.hh" #include "PowerClass.hh" @@ -40,13 +41,13 @@ struct DdManager; namespace sta { class Sta; -class Corner; -class DcalcAnalysisPt; +class Scene; class PropActivityVisitor; class BfsFwdIterator; class Vertex; +class ClkNetwork; -typedef std::pair SeqPin; +using SeqPin = std::pair; class SeqPinHash { @@ -65,9 +66,9 @@ public: const SeqPin &pin2) const; }; -typedef UnorderedMap PwrActivityMap; -typedef UnorderedMap PwrSeqActivityMap; +using PwrActivityMap = std::unordered_map; +using PwrSeqActivityMap = std::unordered_map; // The Power class has access to Sta components directly for // convenience but also requires access to the Sta class member functions. @@ -77,7 +78,25 @@ public: Power(StaState *sta); void clear(); void activitiesInvalid(); - void power(const Corner *corner, + void reportDesign(const Scene *scene, + int digits); + void reportInsts(const InstanceSeq &insts, + const Scene *scene, + int digits); + void reportHighestInsts(size_t count, + const Scene *scene, + int digits); + void reportDesignJson(const Scene *scene, + int digits); + void reportInstsJson(const InstanceSeq &insts, + const Scene *scene, + int digits); + InstPowers highestInstPowers(size_t count, + const Scene *scene); + InstPowers sortInstsByPower(const InstanceSeq &insts, + const Scene *scene); + + void power(const Scene *scene, // Return values. PowerResult &total, PowerResult &sequential, @@ -86,7 +105,8 @@ public: PowerResult ¯o, PowerResult &pad); PowerResult power(const Instance *inst, - const Corner *corner); + const Scene *scene); + void setGlobalActivity(float activity, float duty); void unsetGlobalActivity(); @@ -97,7 +117,8 @@ public: float activity, float duty); void unsetInputPortActivity(const Port *input_port); - PwrActivity pinActivity(const Pin *pin); + PwrActivity pinActivity(const Pin *pin, + const Scene *scene); void setUserActivity(const Pin *pin, float activity, float duty, @@ -105,19 +126,18 @@ public: void unsetUserActivity(const Pin *pin); void reportActivityAnnotation(bool report_unannotated, bool report_annotated); - float clockMinPeriod(); - InstanceSeq highestPowerInstances(size_t count, - const Corner *corner); + float clockMinPeriod(const Sdc *sdc); void deleteInstanceBefore(const Instance *inst); void deletePinBefore(const Pin *pin); protected: PwrActivity &activity(const Pin *pin); - bool inClockNetwork(const Instance *inst); + bool inClockNetwork(const Instance *inst, + const ClkNetwork *clk_network); void powerInside(const Instance *hinst, - const Corner *corner, + const Scene *scene, PowerResult &result); - void ensureActivities(); + void ensureActivities(const Scene *scene); bool hasUserActivity(const Pin *pin); PwrActivity &userActivity(const Pin *pin); void setSeqActivity(const Instance *reg, @@ -131,15 +151,22 @@ protected: void setActivity(const Pin *pin, PwrActivity &activity); PwrActivity findActivity(const Pin *pin); + void reportPowerRowJson(const char *name, + const PowerResult &power, + int digits, + const char *separator); + void reportPowerInstJson(const Instance *inst, + const PowerResult &power, + int digits); - void ensureInstPowers(const Corner *corner); - void findInstPowers(const Corner *corner); + void ensureInstPowers(); + void findInstPowers(); PowerResult power(const Instance *inst, LibertyCell *cell, - const Corner *corner); + const Scene *scene); void findInternalPower(const Instance *inst, LibertyCell *cell, - const Corner *corner, + const Scene *scene, // Return values. PowerResult &result); void findInputInternalPower(const Pin *to_pin, @@ -148,7 +175,7 @@ protected: LibertyCell *cell, PwrActivity &to_activity, float load_cap, - const Corner *corner, + const Scene *scene, // Return values. PowerResult &result); void findOutputInternalPower(const LibertyPort *to_port, @@ -156,22 +183,22 @@ protected: LibertyCell *cell, PwrActivity &to_activity, float load_cap, - const Corner *corner, + const Scene *scene, // Return values. PowerResult &result); void findLeakagePower(const Instance *inst, LibertyCell *cell, - const Corner *corner, + const Scene *scene, // Return values. PowerResult &result); void findSwitchingPower(const Instance *inst, LibertyCell *cell, - const Corner *corner, + const Scene *scene, // Return values. PowerResult &result); float getSlew(Vertex *vertex, const RiseFall *rf, - const Corner *corner); + const Scene *scene); float getMinRfSlew(const Pin *pin); const Clock *findInstClk(const Instance *inst); const Clock *findClk(const Pin *to_pin); @@ -180,10 +207,12 @@ protected: LibertyPort *port); float portVoltage(LibertyCell *cell, const LibertyPort *port, - const DcalcAnalysisPt *dcalc_ap); + const Scene *scene, + const MinMax *min_max); float pgNameVoltage(LibertyCell *cell, const char *pg_port_name, - const DcalcAnalysisPt *dcalc_ap); + const Scene *scene, + const MinMax *min_max); void seedActivities(BfsFwdIterator &bfs); void seedRegOutputActivities(const Instance *reg, Sequential *seq, @@ -209,9 +238,9 @@ protected: LibertyPort *from_port, const Instance *inst); LibertyPort *findLinkPort(const LibertyCell *cell, - const LibertyPort *corner_port); + const LibertyPort *scene_port); Pin *findLinkPin(const Instance *inst, - const LibertyPort *corner_port); + const LibertyPort *scene_port); void clockGatePins(const Instance *inst, // Return values. const Pin *&enable, @@ -226,6 +255,7 @@ protected: size_t pinCount(); private: + const Scene *scene_; // Port/pin activities set by set_pin_activity. // set_pin_activity -global PwrActivity global_activity_; @@ -240,9 +270,8 @@ private: Bdd bdd_; std::map instance_powers_; bool instance_powers_valid_; - const Corner *corner_; - static constexpr int max_activity_passes_ = 100; + static constexpr int max_activity_passes_ = 50; friend class PropActivityVisitor; }; diff --git a/power/Power.i b/power/Power.i index cdc59840..9ff3438a 100644 --- a/power/Power.i +++ b/power/Power.i @@ -27,6 +27,7 @@ %{ #include "Sta.hh" #include "Sdc.hh" +#include "Mode.hh" #include "power/Power.hh" #include "power/VcdReader.hh" #include "power/SaifReader.hh" @@ -37,9 +38,54 @@ using namespace sta; %inline %{ +void +report_power_design(const Scene *scene, + int digits) +{ + Sta *sta = Sta::sta(); + sta->reportPowerDesign(scene, digits); +} + +void +report_power_insts(const InstanceSeq insts, + const Scene *scene, + int digits) +{ + Sta *sta = Sta::sta(); + sta->reportPowerInsts(insts, scene, digits); +} + +void +report_power_highest_insts(size_t count, + const Scene *scene, + int digits) +{ + Sta *sta = Sta::sta(); + sta->reportPowerHighestInsts(count, scene, digits); +} + +void +report_power_design_json(const Scene *scene, + int digits) +{ + Sta *sta = Sta::sta(); + sta->reportPowerDesignJson(scene, digits); +} + +void +report_power_insts_json(const InstanceSeq insts, + const Scene *scene, + int digits) +{ + Sta *sta = Sta::sta(); + sta->reportPowerInstsJson(insts, scene, digits); +} + +//////////////////////////////////////////////////////////////// + static void pushPowerResultFloats(PowerResult &power, - FloatSeq &powers) + FloatSeq &powers) { powers.push_back(power.internal()); powers.push_back(power.switching()); @@ -47,11 +93,12 @@ pushPowerResultFloats(PowerResult &power, powers.push_back(power.total()); } +// Use lassign to retrieve power values. FloatSeq -design_power(const Corner *corner) +design_power(const Scene *scene) { PowerResult total, sequential, combinational, clock, macro, pad; - Sta::sta()->power(corner, total, sequential, combinational, clock, macro, pad); + Sta::sta()->power(scene, total, sequential, combinational, clock, macro, pad); FloatSeq powers; pushPowerResultFloats(total, powers); pushPowerResultFloats(sequential, powers); @@ -64,10 +111,10 @@ design_power(const Corner *corner) FloatSeq instance_power(Instance *inst, - const Corner *corner) + const Scene *scene) { Sta *sta = Sta::sta(); - PowerResult power = sta->power(inst, corner); + PowerResult power = sta->power(inst, scene); FloatSeq powers; powers.push_back(power.internal()); powers.push_back(power.switching()); @@ -78,7 +125,7 @@ instance_power(Instance *inst, void set_power_global_activity(float activity, - float duty) + float duty) { Power *power = Sta::sta()->power(); power->setGlobalActivity(activity, duty); @@ -93,7 +140,7 @@ unset_power_global_activity() void set_power_input_activity(float activity, - float duty) + float duty) { Power *power = Sta::sta()->power(); return power->setInputActivity(activity, duty); @@ -108,8 +155,8 @@ unset_power_input_activity() void set_power_input_port_activity(const Port *input_port, - float activity, - float duty) + float activity, + float duty) { Power *power = Sta::sta()->power(); return power->setInputPortActivity(input_port, activity, duty); @@ -124,8 +171,8 @@ unset_power_input_port_activity(const Port *input_port) void set_power_pin_activity(const Pin *pin, - float activity, - float duty) + float activity, + float duty) { Power *power = Sta::sta()->power(); return power->setUserActivity(pin, activity, duty, PwrActivityOrigin::user); @@ -139,29 +186,27 @@ unset_power_pin_activity(const Pin *pin) } float -clock_min_period() +clock_min_period(const char *mode_name) { - Power *power = Sta::sta()->power(); - return power->clockMinPeriod(); -} - -InstanceSeq -highest_power_instances(size_t count, - const Corner *corner) -{ - Power *power = Sta::sta()->power(); - return power->highestPowerInstances(count, corner); + Sta *sta = Sta::sta(); + Power *power = sta->power(); + const Mode *mode = sta->findMode(mode_name); + if (mode) + return power->clockMinPeriod(mode->sdc()); + else + return 0.0; } //////////////////////////////////////////////////////////////// void read_vcd_file(const char *filename, - const char *scope) + const char *scope, + const char *mode_name) { Sta *sta = Sta::sta(); sta->ensureLibLinked(); - readVcdActivities(filename, scope, sta); + readVcdActivities(filename, scope, mode_name, sta); } //////////////////////////////////////////////////////////////// diff --git a/power/Power.tcl b/power/Power.tcl index 97769501..f56681d6 100644 --- a/power/Power.tcl +++ b/power/Power.tcl @@ -33,7 +33,7 @@ namespace eval sta { define_cmd_args "report_power" \ { [-instances instances]\ [-highest_power_instances count]\ - [-corner corner]\ + [-scene scene]\ [-digits digits]\ [-format format]\ [> filename] [>> filename] } @@ -42,7 +42,8 @@ proc_redirect report_power { global sta_report_default_digits parse_key_args "report_power" args \ - keys {-instances -highest_power_instances -corner -digits -format} flags {} + keys {-instances -highest_power_instances -corner -scene -format -digits}\ + flags {} check_argc_eq0 "report_power" $args @@ -55,7 +56,7 @@ proc_redirect report_power { } else { set digits $sta_report_default_digits } - set corner [parse_corner keys] + set scene [parse_scene keys] if { [info exists keys(-format)] } { set format $keys(-format) @@ -69,24 +70,24 @@ proc_redirect report_power { if { [info exists keys(-instances)] } { set insts [get_instances_error "-instances" $keys(-instances)] if { $format == "json" } { - report_power_insts_json $insts $corner $digits + report_power_insts_json $insts $scene $digits } else { - report_power_insts $insts $corner $digits + report_power_insts $insts $scene $digits } } elseif { [info exists keys(-highest_power_instances)] } { set count $keys(-highest_power_instances) check_positive_integer "-highest_power_instances" $count - set insts [highest_power_instances $count $corner] + set insts [highest_power_instances $count $scene] if { $format == "json" } { - report_power_insts_json $insts $corner $digits + report_power_insts_json $insts $scene $digits } else { - report_power_insts $insts $corner $digits + report_power_insts $insts $scene $digits } } else { if { $format == "json" } { - report_power_design_json $corner $digits + report_power_design_json $scene $digits } else { - report_power_design $corner $digits + report_power_design $scene $digits } } } @@ -101,223 +102,14 @@ proc liberty_libraries_exist {} { return $have_liberty } -proc report_power_design { corner digits } { - set power_result [design_power $corner] - set totals [lrange $power_result 0 3] - set sequential [lrange $power_result 4 7] - set combinational [lrange $power_result 8 11] - set clock [lrange $power_result 12 15] - set macro [lrange $power_result 16 19] - set pad [lrange $power_result 20 end] - lassign $totals design_internal design_switching design_leakage design_total - - set field_width [max [expr $digits + 6] 10] - report_power_title5 "Group" "Internal" "Switching" "Leakage" "Total" $field_width - report_power_title5_units " " "Power" "Power" "Power" "Power" "(Watts)" $field_width - report_title_dashes5 $field_width - report_power_row "Sequential" $sequential $design_total $field_width $digits - report_power_row "Combinational" $combinational $design_total $field_width $digits - report_power_row "Clock" $clock $design_total $field_width $digits - report_power_row "Macro" $macro $design_total $field_width $digits - report_power_row "Pad" $pad $design_total $field_width $digits - report_title_dashes5 $field_width - report_power_row "Total" $power_result $design_total $field_width $digits - - report_line "[format %-20s {}][power_col_percent $design_internal $design_total $field_width][power_col_percent $design_switching $design_total $field_width][power_col_percent $design_leakage $design_total $field_width]" -} - -proc report_power_design_json { corner digits } { - set power_result [design_power $corner] - set totals [lrange $power_result 0 3] - set sequential [lrange $power_result 4 7] - set combinational [lrange $power_result 8 11] - set clock [lrange $power_result 12 15] - set macro [lrange $power_result 16 19] - set pad [lrange $power_result 20 end] - - report_line "\{" - report_power_row_json "Sequential" $sequential $digits "," - report_power_row_json "Combinational" $combinational $digits "," - report_power_row_json "Clock" $clock $digits "," - report_power_row_json "Macro" $macro $digits "," - report_power_row_json "Pad" $pad $digits "," - report_power_row_json "Total" $totals $digits "" - report_line "\}" -} - -proc report_power_row_json { name row_result digits separator } { - lassign $row_result internal switching leakage total - report_line " \"$name\": \{" - report_line " \"internal\": [format %.${digits}e $internal]," - report_line " \"switching\": [format %.${digits}e $switching]," - report_line " \"leakage\": [format %.${digits}e $leakage]," - report_line " \"total\": [format %.${digits}e $total]" - report_line " \}$separator" -} - -proc max { x y } { - if { $x >= $y } { - return $x - } else { - return $y - } -} - -proc report_power_title5 { title1 title2 title3 title4 title5 field_width } { - report_line "[format %-20s $title1] [format %${field_width}s $title2] [format %${field_width}s $title3] [format %${field_width}s $title4] [format %${field_width}s $title5]" -} - -proc report_power_title5_units { title1 title2 title3 title4 title5 units field_width } { - report_line "[format %-20s $title1] [format %${field_width}s $title2] [format %${field_width}s $title3] [format %${field_width}s $title4] [format %${field_width}s $title5] $units" -} - -proc report_power_title4 { title1 title2 title3 title4 field_width } { - report_line " [format %${field_width}s $title1] [format %${field_width}s $title2] [format %${field_width}s $title3] [format %${field_width}s $title4]" -} - -proc report_power_title4_units { title1 title2 title3 title4 units field_width } { - report_line " [format %${field_width}s $title1] [format %${field_width}s $title2] [format %${field_width}s $title3] [format %${field_width}s $title4] $units" -} - -proc report_title_dashes5 { field_width } { - set count [expr 20 + ($field_width + 1) * 4] - report_title_dashes $count -} - -proc report_title_dashes4 { field_width } { - set count [expr ($field_width + 1) * 4] - report_title_dashes $count -} - -proc report_title_dashes { count } { - set line "" - for {set i 0} {$i < $count} {incr i} { - set line "-$line" - } - report_line $line -} - -proc report_power_row { type row_result design_total field_width digits } { - lassign $row_result internal switching leakage total - if { $design_total == 0.0 || [is_nan $design_total] } { - set percent 0.0 - } else { - set percent [expr $total / $design_total * 100] - } - report_line "[format %-20s $type][power_col $internal $field_width $digits][power_col $switching $field_width $digits][power_col $leakage $field_width $digits][power_col $total $field_width $digits] [format %5.1f $percent]%" -} - -proc is_nan { str } { - return [string match "*NaN" $str] -} - -proc power_col { pwr field_width digits } { - if { [is_nan $pwr] } { - format " %${field_width}s" $pwr - } else { - format " %$field_width.${digits}e" $pwr - } -} - -proc power_col_percent { col_total total field_width } { - if { $total == 0.0 || [is_nan $total]} { - set percent 0.0 - } else { - set percent [expr $col_total / $total * 100] - } - format "%$field_width.1f%%" $percent -} - -proc report_power_line { type pwr digits } { - if { [is_nan $pwr] } { - report_line [format "%-16s %s" $type $pwr] - } else { - report_line [format "%-16s %.${digits}e" $type $pwr] - } -} - -proc report_power_insts { insts corner digits } { - set inst_pwrs {} - foreach inst $insts { - set power_result [instance_power $inst $corner] - lappend inst_pwrs [list $inst $power_result] - } - set inst_pwrs [lsort -command inst_pwr_cmp $inst_pwrs] - - set field_width [max [expr $digits + 6] 10] - - report_power_title4 "Internal" "Switching" "Leakage" "Total" $field_width - report_power_title4_units "Power" "Power" "Power" "Power" "(Watts)" $field_width - report_title_dashes4 $field_width - - foreach inst_pwr $inst_pwrs { - set inst [lindex $inst_pwr 0] - set power [lindex $inst_pwr 1] - report_power_inst $inst $power $field_width $digits - } -} - -proc report_power_insts_json { insts corner digits } { - set inst_pwrs {} - foreach inst $insts { - set power_result [instance_power $inst $corner] - lappend inst_pwrs [list $inst $power_result] - } - set inst_pwrs [lsort -command inst_pwr_cmp $inst_pwrs] - - report_line "\[" - set first 1 - foreach inst_pwr $inst_pwrs { - set inst [lindex $inst_pwr 0] - set power [lindex $inst_pwr 1] - if { !$first } { - report_line "," - } - set first 0 - report_power_inst_json $inst $power $digits - } - report_line "\]" -} - -proc report_power_inst_json { inst power digits } { - lassign $power internal switching leakage total - set inst_name [get_full_name $inst] - report_line "\{" - report_line " \"name\": \"$inst_name\"," - report_line " \"internal\": [format %.${digits}e $internal]," - report_line " \"switching\": [format %.${digits}e $switching]," - report_line " \"leakage\": [format %.${digits}e $leakage]," - report_line " \"total\": [format %.${digits}e $total]" - report_line "\}" -} - -proc inst_pwr_cmp { inst_pwr1 inst_pwr2 } { - set pwr1 [lindex $inst_pwr1 1] - set pwr2 [lindex $inst_pwr2 1] - lassign $pwr1 internal1 switching1 leakage1 total1 - lassign $pwr2 internal2 switching2 leakage2 total2 - if { $total1 < $total2 } { - return 1 - } elseif { $total1 == $total2 } { - return 0 - } else { - return -1 - } -} - -proc report_power_inst { inst power_result field_width digits } { - lassign $power_result internal switching leakage total - report_line "[power_col $internal $field_width $digits][power_col $switching $field_width $digits][power_col $leakage $field_width $digits][power_col $total $field_width $digits] [get_full_name $inst]" -} - ################################################################ define_cmd_args "set_power_activity" { [-global]\ - [-input]\ - [-input_ports ports]\ - [-pins pins]\ - [-activity activity | -density density]\ - [-duty duty]\ + [-input]\ + [-input_ports ports]\ + [-pins pins]\ + [-activity activity | -density density]\ + [-duty duty]\ [-clock clock]} proc set_power_activity { args } { @@ -343,7 +135,7 @@ proc set_power_activity { args } { sta_error 307 "-activity requires a clock to be defined" } } - set density [expr $activity / [clock_min_period]] + set density [expr $activity / [clock_min_period [sta::cmd_mode]]] } if { [info exists keys(-density)] } { @@ -373,7 +165,7 @@ proc set_power_activity { args } { set ports [get_ports_error "input_ports" $keys(-input_ports)] foreach port $ports { if { [get_property $port "direction"] == "input" } { - if { [is_clock_src [sta::get_port_pin $port]] } { + if { [is_clock_src [sta::get_port_pin $port]] } { sta_warn 310 "activity cannot be set on clock ports." } else { set_power_input_port_activity $port $density $duty @@ -414,7 +206,7 @@ proc unset_power_activity { args } { set ports [get_ports_error "input_ports" $keys(-input_ports)] foreach port $ports { if { [get_property $port "direction"] == "input" } { - if { [is_clock_src [sta::get_port_pin $port]] } { + if { [is_clock_src [sta::get_port_pin $port]] } { sta_warn 303 "activity cannot be set on clock ports." } else { unset_power_input_port_activity $port @@ -451,11 +243,11 @@ proc read_power_activities { args } { ################################################################ -define_cmd_args "read_vcd" { [-scope scope] filename } +define_cmd_args "read_vcd" { [-scope scope] [-mode mode_name] filename } proc read_vcd { args } { parse_key_args "read_vcd" args \ - keys {-scope} flags {} + keys {-scope -mode_name} flags {} check_argc_eq1 "read_vcd" $args set filename [file nativename [lindex $args 0]] @@ -463,7 +255,11 @@ proc read_vcd { args } { if { [info exists keys(-scope)] } { set scope $keys(-scope) } - read_vcd_file $filename $scope + set mode_name [sta::cmd_mode] + if { [info exists keys(-mode)] } { + set mode_name $keys(-mode) + } + read_vcd_file $filename $scope $mode_name } ################################################################ @@ -499,9 +295,9 @@ proc_redirect report_activity_annotation { ################################################################ proc power_find_nan { } { - set corner [cmd_corner] + set scene [cmd_scene] foreach inst [network_leaf_instances] { - set power_result [instance_power $inst $corner] + set power_result [instance_power $inst $scene] lassign $power_result internal switching leakage total if { [is_nan $internal] || [is_nan $switching] || [is_nan $leakage] } { report_line "[get_full_name $inst] $internal $switching $leakage" @@ -510,5 +306,9 @@ proc power_find_nan { } { } } +proc is_nan { str } { + return [string match "*NaN" $str] +} + # sta namespace end. } diff --git a/power/ReportPower.cc b/power/ReportPower.cc new file mode 100644 index 00000000..3cd77090 --- /dev/null +++ b/power/ReportPower.cc @@ -0,0 +1,247 @@ +// OpenSTA, Static Timing Analyzer +// Copyright (c) 2025, Parallax Software, Inc. +// +// This program is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see . +// +// The origin of this software must not be misrepresented; you must not +// claim that you wrote the original software. +// +// Altered source versions must be plainly marked as such, and must not be +// misrepresented as being the original software. +// +// This notice may not be removed or altered from any source distribution. + +#include "ReportPower.hh" + +#include +#include + +#include "Report.hh" +#include "Network.hh" +#include "StringUtil.hh" + +namespace sta { + +ReportPower::ReportPower(StaState *sta) : + StaState(sta) +{ +} + +void +ReportPower::reportDesign(PowerResult &total, + PowerResult &sequential, + PowerResult &combinational, + PowerResult &clock, + PowerResult ¯o, + PowerResult &pad, + int digits) +{ + float design_internal = total.internal(); + float design_switching = total.switching(); + float design_leakage = total.leakage(); + float design_total = total.total(); + + int field_width = std::max(digits + 6, 10); + + reportTitle5("Group", "Internal", "Switching", "Leakage", "Total", + field_width); + reportTitle5Units(" ", "Power", "Power", "Power", "Power", "(Watts)", + field_width); + reportTitleDashes5(field_width); + + reportRow("Sequential", sequential, design_total, field_width, digits); + reportRow("Combinational", combinational, design_total, field_width, digits); + reportRow("Clock", clock, design_total, field_width, digits); + reportRow("Macro", macro, design_total, field_width, digits); + reportRow("Pad", pad, design_total, field_width, digits); + + reportTitleDashes5(field_width); + + // Report total row using the totals PowerResult + reportRow("Total", total, design_total, field_width, digits); + + // Report percentage line + std::string percent_line = stdstrPrint("%-20s", ""); + percent_line += powerColPercent(design_internal, design_total, field_width); + percent_line += powerColPercent(design_switching, design_total, field_width); + percent_line += powerColPercent(design_leakage, design_total, field_width); + report_->reportLineString(percent_line); +} + +void +ReportPower::reportInsts(const InstPowers &inst_pwrs, + int digits) +{ + int field_width = std::max(digits + 6, 10); + + reportTitle4("Internal", "Switching", "Leakage", "Total", + field_width); + reportTitle4Units("Power", "Power", "Power", "Power", "(Watts)", + field_width); + reportTitleDashes4(field_width); + + for (const InstPower &inst_pwr : inst_pwrs) { + reportInst(inst_pwr.first, inst_pwr.second, field_width, digits); + } +} + +void +ReportPower::reportInst(const Instance *inst, + const PowerResult &power, + int field_width, + int digits) +{ + float internal = power.internal(); + float switching = power.switching(); + float leakage = power.leakage(); + float total = power.total(); + + std::string line = powerCol(internal, field_width, digits); + line += powerCol(switching, field_width, digits); + line += powerCol(leakage, field_width, digits); + line += powerCol(total, field_width, digits); + line += " "; + line += network_->pathName(inst); + report_->reportLineString(line); +} + +std::string +ReportPower::powerCol(float pwr, + int field_width, + int digits) +{ + if (std::isnan(pwr)) + return stdstrPrint(" %*s", field_width, "NaN"); + else + return stdstrPrint(" %*.*e", field_width, digits, pwr); +} + +std::string +ReportPower::powerColPercent(float col_total, + float total, + int field_width) +{ + float percent = 0.0; + if (total != 0.0 && !std::isnan(total)) { + percent = col_total / total * 100.0; + } + return stdstrPrint("%*.*f%%", field_width, 1, percent); +} + +void +ReportPower::reportTitle5(const char *title1, + const char *title2, + const char *title3, + const char *title4, + const char *title5, + int field_width) +{ + report_->reportLine("%-20s %*s %*s %*s %*s", + title1, + field_width, title2, + field_width, title3, + field_width, title4, + field_width, title5); +} + +void +ReportPower::reportTitle5Units(const char *title1, + const char *title2, + const char *title3, + const char *title4, + const char *title5, + const char *units, + int field_width) +{ + report_->reportLine("%-20s %*s %*s %*s %*s %s", + title1, + field_width, title2, + field_width, title3, + field_width, title4, + field_width, title5, + units); +} + +void +ReportPower::reportTitleDashes5(int field_width) +{ + int count = 20 + (field_width + 1) * 4; + std::string dashes(count, '-'); + report_->reportLineString(dashes); +} + +void +ReportPower::reportRow(const char *type, + const PowerResult &power, + float design_total, + int field_width, + int digits) +{ + float internal = power.internal(); + float switching = power.switching(); + float leakage = power.leakage(); + float total = power.total(); + + float percent = 0.0; + if (design_total != 0.0 && !std::isnan(design_total)) + percent = total / design_total * 100.0; + + std::string line = stdstrPrint("%-20s", type); + line += powerCol(internal, field_width, digits); + line += powerCol(switching, field_width, digits); + line += powerCol(leakage, field_width, digits); + line += powerCol(total, field_width, digits); + line += stdstrPrint(" %5.1f%%", percent); + report_->reportLineString(line); +} + +void +ReportPower::reportTitle4(const char *title1, + const char *title2, + const char *title3, + const char *title4, + int field_width) +{ + report_->reportLine(" %*s %*s %*s %*s", + field_width, title1, + field_width, title2, + field_width, title3, + field_width, title4); +} + +void +ReportPower::reportTitle4Units(const char *title1, + const char *title2, + const char *title3, + const char *title4, + const char *units, + int field_width) +{ + report_->reportLine(" %*s %*s %*s %*s %s", + field_width, title1, + field_width, title2, + field_width, title3, + field_width, title4, + units); +} + +void +ReportPower::reportTitleDashes4(int field_width) +{ + int count = (field_width + 1) * 4; + std::string dashes(count, '-'); + report_->reportLineString(dashes); +} + +} // namespace diff --git a/power/ReportPower.hh b/power/ReportPower.hh new file mode 100644 index 00000000..c069a8b2 --- /dev/null +++ b/power/ReportPower.hh @@ -0,0 +1,91 @@ +// OpenSTA, Static Timing Analyzer +// Copyright (c) 2025, Parallax Software, Inc. +// +// This program is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see . +// +// The origin of this software must not be misrepresented; you must not +// claim that you wrote the original software. +// +// Altered source versions must be plainly marked as such, and must not be +// misrepresented as being the original software. +// +// This notice may not be removed or altered from any source distribution. + +#pragma once + +#include "StaState.hh" +#include "NetworkClass.hh" +#include "PowerClass.hh" + +namespace sta { + +class ReportPower : public StaState +{ +public: + ReportPower(StaState *sta); + void reportDesign(PowerResult &total, + PowerResult &sequential, + PowerResult &combinational, + PowerResult &clock, + PowerResult ¯o, + PowerResult &pad, + int digits); + void reportInsts(const InstPowers &inst_pwrs, + int digits); + +private: + std::string powerCol(float pwr, + int field_width, + int digits); + std::string powerColPercent(float col_total, + float total, + int field_width); + void reportTitle5(const char *title1, + const char *title2, + const char *title3, + const char *title4, + const char *title5, + int field_width); + void reportTitle5Units(const char *title1, + const char *title2, + const char *title3, + const char *title4, + const char *title5, + const char *units, + int field_width); + void reportTitleDashes5(int field_width); + void reportRow(const char *type, + const PowerResult &power, + float design_total, + int field_width, + int digits); + void reportTitle4(const char *title1, + const char *title2, + const char *title3, + const char *title4, + int field_width); + void reportTitle4Units(const char *title1, + const char *title2, + const char *title3, + const char *title4, + const char *units, + int field_width); + void reportTitleDashes4(int field_width); + void reportInst(const Instance *inst, + const PowerResult &power, + int field_width, + int digits); +}; + +} // namespace diff --git a/power/SaifReader.cc b/power/SaifReader.cc index ecd14277..3a758ba2 100644 --- a/power/SaifReader.cc +++ b/power/SaifReader.cc @@ -63,7 +63,7 @@ SaifReader::SaifReader(const char *filename, scope_(scope), divider_('/'), escape_('\\'), - timescale_(1.0E-9F), // default units of ns + timescale_(1.0E-9F), // default units of ns duration_(0.0), in_scope_level_(0), power_(sta->power()) @@ -173,7 +173,7 @@ SaifReader::setNetDurations(const char *net_name, if (pin && !sdc_network_->isHierarchical(pin) && !sdc_network_->direction(pin)->isInternal() - && !(liberty_port && liberty_port->isPwrGnd())) { + && !(liberty_port && liberty_port->isPwrGnd())) { double t1 = durations[static_cast(SaifState::T1)]; float duty = t1 / duration_; double tc = durations[static_cast(SaifState::TC)]; diff --git a/power/SaifReaderPvt.hh b/power/SaifReaderPvt.hh index b5a57bdb..cfbb7dd2 100644 --- a/power/SaifReaderPvt.hh +++ b/power/SaifReaderPvt.hh @@ -46,7 +46,7 @@ class SaifScanner; enum class SaifState { T0, T1, TX, TZ, TB, TC, IG }; -typedef std::array(SaifState::IG)+1> SaifStateDurations; +using SaifStateDurations = std::array(SaifState::IG)+1>; class SaifReader : public StaState { diff --git a/power/VcdParse.hh b/power/VcdParse.hh index 267aff3c..0fdb2301 100644 --- a/power/VcdParse.hh +++ b/power/VcdParse.hh @@ -33,8 +33,8 @@ namespace sta { -typedef int64_t VcdTime; -typedef std::vector VcdScope; +using VcdTime = int64_t; +using VcdScope = std::vector; enum class VcdVarType { wire, diff --git a/power/VcdReader.cc b/power/VcdReader.cc index 2adebfda..420e1449 100644 --- a/power/VcdReader.cc +++ b/power/VcdReader.cc @@ -35,6 +35,7 @@ #include "VerilogNamespace.hh" #include "ParseBus.hh" #include "Sdc.hh" +#include "Mode.hh" #include "Power.hh" #include "Sta.hh" @@ -123,8 +124,8 @@ typedef unordered_map VcdIdCountsMap; class VcdCountReader : public VcdReader { public: - VcdCountReader(const char *scope, - Network *sdc_network, + VcdCountReader(const std::string &scope, + const Network *sdc_network, Report *report, Debug *debug); VcdTime timeMax() const { return time_max_; } @@ -161,28 +162,29 @@ private: size_t width, size_t bit_idx); - const char *scope_; - Network *sdc_network_; - Report *report_; - Debug *debug_; + const std::string scope_; double time_scale_; VcdTime time_min_; VcdTime time_max_; VcdIdCountsMap vcd_count_map_; + + const Network *sdc_network_; + Report *report_; + Debug *debug_; }; -VcdCountReader::VcdCountReader(const char *scope, - Network *sdc_network, +VcdCountReader::VcdCountReader(const std::string &scope, + const Network *sdc_network, Report *report, Debug *debug) : scope_(scope), - sdc_network_(sdc_network), - report_(report), - debug_(debug), time_scale_(1.0), time_min_(0), - time_max_(0) + time_max_(0), + sdc_network_(sdc_network), + report_(report), + debug_(debug) { } @@ -229,7 +231,7 @@ VcdCountReader::makeVar(const VcdScope &scope, path_name += context; first = false; } - size_t scope_length = strlen(scope_); + size_t scope_length = scope_.size(); // string::starts_with in c++20 if (scope_length == 0 || path_name.substr(0, scope_length) == scope_) { @@ -361,8 +363,9 @@ VcdCountReader::varAppendBusValue(const string &id, class ReadVcdActivities : public StaState { public: - ReadVcdActivities(const char *filename, - const char *scope, + ReadVcdActivities(const std::string &filename, + const std::string &scope, + const Sdc *sdc, Sta *sta); void readActivities(); @@ -371,32 +374,38 @@ private: void checkClkPeriod(const Pin *pin, double transition_count); - const char *filename_; + const std::string filename_; + + std::set annotated_pins_; VcdCountReader vcd_reader_; VcdParse vcd_parse_; - + const Sdc *sdc_; Power *power_; - std::set annotated_pins_; static constexpr double sim_clk_period_tolerance_ = .1; }; void -readVcdActivities(const char *filename, - const char *scope, +readVcdActivities(const std::string &filename, + const std::string &scope, + const std::string &mode_name, Sta *sta) { - ReadVcdActivities reader(filename, scope, sta); + const Mode *mode = sta->findMode(mode_name); + const Sdc *sdc = mode->sdc(); + ReadVcdActivities reader(filename, scope, sdc, sta); reader.readActivities(); } -ReadVcdActivities::ReadVcdActivities(const char *filename, - const char *scope, +ReadVcdActivities::ReadVcdActivities(const std::string &filename, + const std::string &scope, + const Sdc *sdc, Sta *sta) : StaState(sta), filename_(filename), vcd_reader_(scope, sdc_network_, report_, debug_), vcd_parse_(report_, debug_), + sdc_(sdc), power_(sta->power()) { } @@ -404,11 +413,11 @@ ReadVcdActivities::ReadVcdActivities(const char *filename, void ReadVcdActivities::readActivities() { - ClockSeq *clks = sdc_->clocks(); - if (clks->empty()) + const ClockSeq &clks = sdc_->clocks(); + if (clks.empty()) report_->error(820, "No clocks have been defined."); - vcd_parse_.read(filename_, &vcd_reader_); + vcd_parse_.read(filename_.c_str(), &vcd_reader_); if (vcd_reader_.timeMax() > 0) setActivities(); @@ -462,7 +471,7 @@ ReadVcdActivities::checkClkPeriod(const Pin *pin, double sim_period = (time_max - time_min) * time_scale / (transition_count / 2.0); for (Clock *clk : *clks) { if (transition_count == 0) - report_->warn(1452, "clock %s pin %s has no vcd transitions.", + report_->warn(1453, "clock %s pin %s has no vcd transitions.", clk->name(), sdc_network_->pathName(pin)); else { diff --git a/power/VcdReader.hh b/power/VcdReader.hh index a5a67ef3..ca1d6d2e 100644 --- a/power/VcdReader.hh +++ b/power/VcdReader.hh @@ -24,13 +24,16 @@ #pragma once +#include + namespace sta { class Sta; void -readVcdActivities(const char *filename, - const char *scope, +readVcdActivities(const std::string &filename, + const std::string &scope, + const std::string &mode_name, Sta *sta); } // namespace diff --git a/sdc/Clock.cc b/sdc/Clock.cc index 8e7aadd1..3960f670 100644 --- a/sdc/Clock.cc +++ b/sdc/Clock.cc @@ -26,6 +26,7 @@ #include +#include "ContainerHelpers.hh" #include "Error.hh" #include "StringUtil.hh" #include "MinMax.hh" @@ -41,7 +42,7 @@ static bool isPowerOfTwo(int i); Clock::Clock(const char *name, - int index, + int index, const Network *network) : name_(stringCopy(name)), pins_(network), @@ -71,11 +72,11 @@ Clock::Clock(const char *name, void Clock::initClk(PinSet *pins, - bool add_to_pins, - float period, - FloatSeq *waveform, - const char *comment, - const Network *network) + bool add_to_pins, + float period, + FloatSeq *waveform, + const char *comment, + const Network *network) { is_generated_ = false; setPins(pins, network); @@ -96,7 +97,7 @@ Clock::isVirtual() const void Clock::setPins(PinSet *pins, - const Network *network) + const Network *network) { if (pins) pins_ = *pins; @@ -108,11 +109,8 @@ void Clock::makeLeafPins(const Network *network) { leaf_pins_.clear(); - PinSet::Iterator pin_iter(pins_); - while (pin_iter.hasNext()) { - const Pin *pin = pin_iter.next(); + for (const Pin *pin : pins_) findLeafDriverPins(pin, network, &leaf_pins_); - } } void @@ -181,9 +179,9 @@ Clock::setClkEdgeTime(const RiseFall *rf) const Pin * Clock::defaultPin() const { - PinSet::ConstIterator pin_iter(leaf_pins_); - if (pin_iter.hasNext()) - return pin_iter.next(); + auto itr = leaf_pins_.begin(); + if (itr != leaf_pins_.end()) + return *itr; else return nullptr; } @@ -202,17 +200,17 @@ Clock::setIsPropagated(bool propagated) void Clock::slew(const RiseFall *rf, - const MinMax *min_max, - // Return values. - float &slew, - bool &exists) const + const MinMax *min_max, + // Return values. + float &slew, + bool &exists) const { slews_.value(rf, min_max, slew, exists); } float Clock::slew(const RiseFall *rf, - const MinMax *min_max) const + const MinMax *min_max) const { float slew; bool exists; @@ -224,16 +222,16 @@ Clock::slew(const RiseFall *rf, void Clock::setSlew(const RiseFallBoth *rf, - const MinMaxAll *min_max, - float slew) + const MinMaxAll *min_max, + float slew) { slews_.setValue(rf, min_max, slew); } void Clock::setSlew(const RiseFall *rf, - const MinMax *min_max, - float slew) + const MinMax *min_max, + float slew) { slews_.setValue(rf, min_max, slew); } @@ -246,29 +244,29 @@ Clock::removeSlew() void Clock::setSlewLimit(const RiseFallBoth *rf, - const PathClkOrData clk_data, - const MinMax *min_max, - float slew) + const PathClkOrData clk_data, + const MinMax *min_max, + float slew) { slew_limits_[int(clk_data)].setValue(rf, min_max, slew); } void Clock::slewLimit(const RiseFall *rf, - const PathClkOrData clk_data, - const MinMax *min_max, - // Return values. - float &slew, - bool &exists) const + const PathClkOrData clk_data, + const MinMax *min_max, + // Return values. + float &slew, + bool &exists) const { slew_limits_[int(clk_data)].value(rf, min_max, slew, exists); } void Clock::uncertainty(const SetupHold *setup_hold, - // Return values. - float &uncertainty, - bool &exists) const + // Return values. + float &uncertainty, + bool &exists) const { if (uncertainties_) uncertainties_->value(setup_hold, uncertainty, exists); @@ -280,7 +278,7 @@ Clock::uncertainty(const SetupHold *setup_hold, void Clock::setUncertainty(const SetupHoldAll *setup_hold, - float uncertainty) + float uncertainty) { if (uncertainties_ == nullptr) uncertainties_ = new ClockUncertainties; @@ -289,7 +287,7 @@ Clock::setUncertainty(const SetupHoldAll *setup_hold, void Clock::setUncertainty(const SetupHold *setup_hold, - float uncertainty) + float uncertainty) { if (uncertainties_ == nullptr) uncertainties_ = new ClockUncertainties; @@ -318,19 +316,19 @@ Clock::waveformInvalid() void Clock::initGeneratedClk(PinSet *pins, - bool add_to_pins, - Pin *src_pin, - Clock *master_clk, - int divide_by, - int multiply_by, - float duty_cycle, - bool invert, - bool combinational, - IntSeq *edges, - FloatSeq *edge_shifts, - bool is_propagated, - const char *comment, - const Network *network) + bool add_to_pins, + Pin *src_pin, + Clock *master_clk, + int divide_by, + int multiply_by, + float duty_cycle, + bool invert, + bool combinational, + IntSeq *edges, + FloatSeq *edge_shifts, + bool is_propagated, + const char *comment, + const Network *network) { is_generated_ = true; setPins(pins, network); @@ -431,7 +429,7 @@ Clock::generate(const Clock *src_clk) void Clock::generateScaledClk(const Clock *src_clk, - float scale) + float scale) { period_ = src_clk->period() * scale; if (duty_cycle_ != 0.0) { @@ -440,11 +438,8 @@ Clock::generateScaledClk(const Clock *src_clk, waveform_->push_back(rise + period_ * duty_cycle_ / 100.0F); } else { - FloatSeq::ConstIterator wave_iter(src_clk->waveform()); - while (wave_iter.hasNext()) { - float time = wave_iter.next(); + for (float time : *src_clk->waveform()) waveform_->push_back(time * scale); - } } } @@ -499,22 +494,20 @@ Clock::masterClkEdgeTr(const RiseFall *rf) const void Clock::srcPinVertices(VertexSet &src_vertices, - const Network *network, - Graph *graph) + const Network *network, + Graph *graph) { if (network->isHierarchical(src_pin_)) { // Use the clocks on a non-hierarchical pin on the same net. PinSet leaf_pins(network); findLeafDriverPins(src_pin_, network, &leaf_pins); - PinSet::Iterator pin_iter(leaf_pins); - while (pin_iter.hasNext()) { - const Pin *pin = pin_iter.next(); + for (const Pin *pin : leaf_pins) { Vertex *vertex, *bidirect_drvr_vertex; graph->pinVertices(pin, vertex, bidirect_drvr_vertex); if (vertex) - src_vertices.insert(vertex); + src_vertices.insert(vertex); if (bidirect_drvr_vertex) - src_vertices.insert(bidirect_drvr_vertex); + src_vertices.insert(bidirect_drvr_vertex); } } else { @@ -535,7 +528,7 @@ Clock::isDivideByOneCombinational() const //////////////////////////////////////////////////////////////// ClockEdge::ClockEdge(Clock *clock, - const RiseFall *rf) : + const RiseFall *rf) : clock_(clock), rf_(rf), name_(stringPrint("%s %s", clock_->name(), rf_->to_string().c_str())), @@ -597,7 +590,7 @@ clkCmp(const Clock *clk1, int clkEdgeCmp(const ClockEdge *clk_edge1, - const ClockEdge *clk_edge2) + const ClockEdge *clk_edge2) { if (clk_edge1 == nullptr && clk_edge2) return -1; @@ -619,7 +612,7 @@ clkEdgeCmp(const ClockEdge *clk_edge1, bool clkEdgeLess(const ClockEdge *clk_edge1, - const ClockEdge *clk_edge2) + const ClockEdge *clk_edge2) { return clkEdgeCmp(clk_edge1, clk_edge2) < 0; } @@ -627,7 +620,7 @@ clkEdgeLess(const ClockEdge *clk_edge1, //////////////////////////////////////////////////////////////// InterClockUncertainty::InterClockUncertainty(const Clock *src, - const Clock *target) : + const Clock *target) : src_(src), target_(target) { @@ -642,20 +635,20 @@ InterClockUncertainty::empty() const void InterClockUncertainty::uncertainty(const RiseFall *src_rf, - const RiseFall *tgt_rf, - const SetupHold *setup_hold, - float &uncertainty, - bool &exists) const + const RiseFall *tgt_rf, + const SetupHold *setup_hold, + float &uncertainty, + bool &exists) const { uncertainties_[src_rf->index()].value(tgt_rf, setup_hold, - uncertainty, exists); + uncertainty, exists); } void InterClockUncertainty::setUncertainty(const RiseFallBoth *src_rf, - const RiseFallBoth *tgt_rf, - const SetupHoldAll *setup_hold, - float uncertainty) + const RiseFallBoth *tgt_rf, + const SetupHoldAll *setup_hold, + float uncertainty) { for (auto src_rf_index : src_rf->rangeIndex()) uncertainties_[src_rf_index].setValue(tgt_rf, setup_hold, uncertainty); @@ -663,8 +656,8 @@ InterClockUncertainty::setUncertainty(const RiseFallBoth *src_rf, void InterClockUncertainty::removeUncertainty(const RiseFallBoth *src_rf, - const RiseFallBoth *tgt_rf, - const SetupHoldAll *setup_hold) + const RiseFallBoth *tgt_rf, + const SetupHoldAll *setup_hold) { for (auto src_rf_index : src_rf->rangeIndex()) uncertainties_[src_rf_index].removeValue(tgt_rf, setup_hold); @@ -678,18 +671,18 @@ InterClockUncertainty::uncertainties(const RiseFall *src_rf) const bool InterClockUncertaintyLess::operator()(const InterClockUncertainty *inter1, - const InterClockUncertainty *inter2)const + const InterClockUncertainty *inter2)const { return inter1->src()->index() < inter2->src()->index() || (inter1->src() == inter2->src() - && inter1->target()->index() < inter2->target()->index()); + && inter1->target()->index() < inter2->target()->index()); } //////////////////////////////////////////////////////////////// bool ClockNameLess::operator()(const Clock *clk1, - const Clock *clk2) + const Clock *clk2) { return stringLess(clk1->name(), clk2->name()); } @@ -727,26 +720,7 @@ int compare(const ClockSet *set1, const ClockSet *set2) { - size_t size1 = set1 ? set1->size() : 0; - size_t size2 = set2 ? set2->size() : 0; - if (size1 == size2) { - ClockSet::ConstIterator iter1(set1); - ClockSet::ConstIterator iter2(set2); - while (iter1.hasNext() && iter2.hasNext()) { - Clock *clk1 = iter1.next(); - Clock *clk2 = iter2.next(); - int id1 = clk1->index(); - int id2 = clk2->index(); - if (id1 < id2) - return -1; - else if (id1 > id2) - return 1; - } - // Sets are equal. - return 0; - } - else - return (size1 > size2) ? 1 : -1; + return sta::compare(set1, set2, ClockIndexLess()); } } // namespace diff --git a/sdc/ClockGroups.cc b/sdc/ClockGroups.cc index 850611e5..7a67fca7 100644 --- a/sdc/ClockGroups.cc +++ b/sdc/ClockGroups.cc @@ -24,16 +24,17 @@ #include "ClockGroups.hh" +#include "ContainerHelpers.hh" #include "StringUtil.hh" namespace sta { ClockGroups::ClockGroups(const char *name, - bool logically_exclusive, - bool physically_exclusive, - bool asynchronous, - bool allow_paths, - const char *comment) : + bool logically_exclusive, + bool physically_exclusive, + bool asynchronous, + bool allow_paths, + const char *comment) : SdcCmdComment(comment), name_(stringCopy(name)), logically_exclusive_(logically_exclusive), @@ -46,7 +47,7 @@ ClockGroups::ClockGroups(const char *name, ClockGroups::~ClockGroups() { stringDelete(name_); - groups_.deleteContentsClear(); + deleteContents(groups_); } void diff --git a/sdc/ClockInsertion.cc b/sdc/ClockInsertion.cc index 4c245518..ee317e4b 100644 --- a/sdc/ClockInsertion.cc +++ b/sdc/ClockInsertion.cc @@ -27,7 +27,7 @@ namespace sta { ClockInsertion::ClockInsertion(const Clock *clk, - const Pin *pin) : + const Pin *pin) : clk_(clk), pin_(pin) { @@ -35,9 +35,9 @@ ClockInsertion::ClockInsertion(const Clock *clk, void ClockInsertion::setDelay(const RiseFallBoth *rf, - const MinMaxAll *min_max, - const EarlyLateAll *early_late, - float delay) + const MinMaxAll *min_max, + const EarlyLateAll *early_late, + float delay) { for (auto el_index : early_late->rangeIndex()) delays_[el_index].setValue(rf, min_max, delay); @@ -45,8 +45,8 @@ ClockInsertion::setDelay(const RiseFallBoth *rf, float ClockInsertion::delay(const RiseFall *rf, - const MinMax *min_max, - const EarlyLate *early_late) + const MinMax *min_max, + const EarlyLate *early_late) { float insertion; bool exists; @@ -59,11 +59,11 @@ ClockInsertion::delay(const RiseFall *rf, void ClockInsertion::delay(const RiseFall *rf, - const MinMax *min_max, - const EarlyLate *early_late, - // Return values. - float &insertion, - bool &exists) + const MinMax *min_max, + const EarlyLate *early_late, + // Return values. + float &insertion, + bool &exists) { delays_[early_late->index()].value(rf, min_max, insertion, exists); @@ -73,9 +73,9 @@ ClockInsertion::delay(const RiseFall *rf, void ClockInsertion::setDelay(const RiseFall *rf, - const MinMax *min_max, - const EarlyLate *early_late, - float delay) + const MinMax *min_max, + const EarlyLate *early_late, + float delay) { delays_[early_late->index()].setValue(rf, min_max, delay); } diff --git a/sdc/ClockLatency.cc b/sdc/ClockLatency.cc index 22fe82ba..d9267663 100644 --- a/sdc/ClockLatency.cc +++ b/sdc/ClockLatency.cc @@ -27,7 +27,7 @@ namespace sta { ClockLatency::ClockLatency(const Clock *clk, - const Pin *pin) : + const Pin *pin) : clk_(clk), pin_(pin) { @@ -35,15 +35,15 @@ ClockLatency::ClockLatency(const Clock *clk, void ClockLatency::setDelay(const RiseFallBoth *rf, - const MinMaxAll *min_max, - float delay) + const MinMaxAll *min_max, + float delay) { delays_.setValue(rf, min_max, delay); } float ClockLatency::delay(const RiseFall *rf, - const MinMax *min_max) + const MinMax *min_max) { float latency; bool exists; @@ -56,10 +56,10 @@ ClockLatency::delay(const RiseFall *rf, void ClockLatency::delay(const RiseFall *rf, - const MinMax *min_max, - // Return values. - float &latency, - bool &exists) + const MinMax *min_max, + // Return values. + float &latency, + bool &exists) { delays_.value(rf, min_max, latency, exists); @@ -69,8 +69,8 @@ ClockLatency::delay(const RiseFall *rf, void ClockLatency::setDelay(const RiseFall *rf, - const MinMax *min_max, - float delay) + const MinMax *min_max, + float delay) { delays_.setValue(rf, min_max, delay); } diff --git a/sdc/CycleAccting.cc b/sdc/CycleAccting.cc index 6ac5f875..9df530e5 100644 --- a/sdc/CycleAccting.cc +++ b/sdc/CycleAccting.cc @@ -27,6 +27,7 @@ #include // ceil #include // max +#include "ContainerHelpers.hh" #include "Debug.hh" #include "Fuzzy.hh" #include "Units.hh" @@ -49,7 +50,7 @@ CycleAcctings::~CycleAcctings() void CycleAcctings::clear() { - cycle_acctings_.deleteContentsClear(); + deleteContents(cycle_acctings_); } // Determine cycle accounting "on demand". @@ -60,7 +61,7 @@ CycleAcctings::cycleAccting(const ClockEdge *src, if (src == nullptr) src = tgt; CycleAccting probe(src, tgt); - CycleAccting *acct = cycle_acctings_.findKey(&probe); + CycleAccting *acct = findKey(cycle_acctings_, &probe); if (acct == nullptr) { acct = new CycleAccting(src, tgt); if (src == sdc_->defaultArrivalClockEdge()) @@ -78,20 +79,20 @@ CycleAcctings::reportClkToClkMaxCycleWarnings(Report *report) // Find cycle acctings that exceed max cycle count. Eliminate // duplicate warnings between different src/tgt clk edges. ClockPairSet clk_warnings; - for (Clock *src_clk : *sdc_->clocks()) { + for (Clock *src_clk : sdc_->clocks()) { for (const RiseFall *src_rf : RiseFall::range()) { ClockEdge *src = src_clk->edge(src_rf); - for (Clock *tgt_clk : *sdc_->clocks()) { + for (Clock *tgt_clk : sdc_->clocks()) { for (const RiseFall *tgt_rf : RiseFall::range()) { ClockEdge *tgt = tgt_clk->edge(tgt_rf); CycleAccting probe(src, tgt); - CycleAccting *acct = cycle_acctings_.findKey(&probe); + CycleAccting *acct = findKey(cycle_acctings_, &probe); if (acct && acct->maxCyclesExceeded()) { // Canonicalize the warning wrt src/tgt. ClockPair clk_pair1(src_clk, tgt_clk); ClockPair clk_pair2(tgt_clk, src_clk); - if (!clk_warnings.hasKey(clk_pair1) - && !clk_warnings.hasKey(clk_pair2)) { + if (!clk_warnings.contains(clk_pair1) + && !clk_warnings.contains(clk_pair2)) { report->warn(1010, "No common period was found between clocks %s and %s.", src_clk->name(), tgt_clk->name()); @@ -107,7 +108,7 @@ CycleAcctings::reportClkToClkMaxCycleWarnings(Report *report) //////////////////////////////////////////////////////////////// CycleAccting::CycleAccting(const ClockEdge *src, - const ClockEdge *tgt) : + const ClockEdge *tgt) : src_(src), tgt_(tgt), max_cycles_exceeded_(false) @@ -157,121 +158,121 @@ CycleAccting::findDelays(StaState *sta) double tgt_time = tgt_cycle_start + tgt_->time(); double tgt_opp_time = tgt_cycle_start + tgt_opp_time1; for (src_cycle = firstCycle(src_); - ; - src_cycle++) { - double src_cycle_start = src_cycle * src_period; - double src_time = src_cycle_start + src_->time(); + ; + src_cycle++) { + double src_cycle_start = src_cycle * src_period; + double src_time = src_cycle_start + src_->time(); - // Make sure both setup and hold required are determined. - if (tgt_past_src && src_past_tgt - // Synchronicity achieved. - && fuzzyEqual(src_cycle_start, tgt_cycle_start)) { - debugPrint(debug, "cycle_acct", 1, " setup = %s, required = %s", + // Make sure both setup and hold required are determined. + if (tgt_past_src && src_past_tgt + // Synchronicity achieved. + && fuzzyEqual(src_cycle_start, tgt_cycle_start)) { + debugPrint(debug, "cycle_acct", 1, " setup = %s, required = %s", time_unit->asString(delay_[setup_index]), time_unit->asString(required_[setup_index])); - debugPrint(debug, "cycle_acct", 1, " hold = %s, required = %s", + debugPrint(debug, "cycle_acct", 1, " hold = %s, required = %s", time_unit->asString(delay_[hold_index]), time_unit->asString(required_[hold_index])); - debugPrint(debug, "cycle_acct", 1, + debugPrint(debug, "cycle_acct", 1, " converged at src cycles = %d tgt cycles = %d", src_cycle, tgt_cycle); - return; - } + return; + } - if (fuzzyGreater(src_cycle_start, tgt_cycle_start + tgt_period) - && src_past_tgt) - break; - debugPrint(debug, "cycle_acct", 2, " %s src cycle %d %s + %s = %s", + if (fuzzyGreater(src_cycle_start, tgt_cycle_start + tgt_period) + && src_past_tgt) + break; + debugPrint(debug, "cycle_acct", 2, " %s src cycle %d %s + %s = %s", src_->name(), src_cycle, time_unit->asString(src_cycle_start), time_unit->asString(src_->time()), time_unit->asString(src_time)); - debugPrint(debug, "cycle_acct", 2, " %s tgt cycle %d %s + %s = %s", + debugPrint(debug, "cycle_acct", 2, " %s tgt cycle %d %s + %s = %s", tgt_->name(), tgt_cycle, time_unit->asString(tgt_cycle_start), time_unit->asString(tgt_->time()), time_unit->asString(tgt_time)); - // For setup checks, target has to be AFTER source. - if (fuzzyGreater(tgt_time, src_time)) { - tgt_past_src = true; - double delay = tgt_time - src_time; - if (fuzzyLess(delay, delay_[setup_index])) { - double required = tgt_time - src_cycle_start; - setSetupAccting(src_cycle, tgt_cycle, delay, required); - debugPrint(debug, "cycle_acct", 2, + // For setup checks, target has to be AFTER source. + if (fuzzyGreater(tgt_time, src_time)) { + tgt_past_src = true; + double delay = tgt_time - src_time; + if (fuzzyLess(delay, delay_[setup_index])) { + double required = tgt_time - src_cycle_start; + setSetupAccting(src_cycle, tgt_cycle, delay, required); + debugPrint(debug, "cycle_acct", 2, " setup min delay = %s, required = %s", time_unit->asString(delay_[setup_index]), time_unit->asString(required_[setup_index])); - } - } + } + } - // Data check setup checks are zero cycle. - if (fuzzyLessEqual(tgt_time, src_time)) { - double setup_delay = src_time - tgt_time; - if (fuzzyLess(setup_delay, delay_[data_check_setup_index])) { - double setup_required = tgt_time - src_cycle_start; - setAccting(TimingRole::dataCheckSetup(), src_cycle, tgt_cycle, - setup_delay, setup_required); - double hold_required = tgt_time - (src_cycle_start + src_period); - double hold_delay = (src_period + src_time) - tgt_time; - setAccting(TimingRole::dataCheckHold(), - src_cycle + 1, tgt_cycle, hold_delay, hold_required); - } - } + // Data check setup checks are zero cycle. + if (fuzzyLessEqual(tgt_time, src_time)) { + double setup_delay = src_time - tgt_time; + if (fuzzyLess(setup_delay, delay_[data_check_setup_index])) { + double setup_required = tgt_time - src_cycle_start; + setAccting(TimingRole::dataCheckSetup(), src_cycle, tgt_cycle, + setup_delay, setup_required); + double hold_required = tgt_time - (src_cycle_start + src_period); + double hold_delay = (src_period + src_time) - tgt_time; + setAccting(TimingRole::dataCheckHold(), + src_cycle + 1, tgt_cycle, hold_delay, hold_required); + } + } - // Latch setup cycle accting for the enable is the data clk edge - // closest to the disable (opposite) edge. - if (fuzzyGreater(tgt_opp_time, src_time)) { - double delay = tgt_opp_time - src_time; - if (fuzzyLess(delay, delay_[latch_setup_index])) { - double latch_tgt_time = tgt_time; - int latch_tgt_cycle = tgt_cycle; - // Enable time is the edge before the disable. - if (tgt_time > tgt_opp_time) { - latch_tgt_time -= tgt_period; - latch_tgt_cycle--; - } - double required = latch_tgt_time - src_cycle_start; - setAccting(TimingRole::latchSetup(), - src_cycle, latch_tgt_cycle, delay, required); - debugPrint(debug, "cycle_acct", 2, + // Latch setup cycle accting for the enable is the data clk edge + // closest to the disable (opposite) edge. + if (fuzzyGreater(tgt_opp_time, src_time)) { + double delay = tgt_opp_time - src_time; + if (fuzzyLess(delay, delay_[latch_setup_index])) { + double latch_tgt_time = tgt_time; + int latch_tgt_cycle = tgt_cycle; + // Enable time is the edge before the disable. + if (tgt_time > tgt_opp_time) { + latch_tgt_time -= tgt_period; + latch_tgt_cycle--; + } + double required = latch_tgt_time - src_cycle_start; + setAccting(TimingRole::latchSetup(), + src_cycle, latch_tgt_cycle, delay, required); + debugPrint(debug, "cycle_acct", 2, " latch setup min delay = %s, required = %s", time_unit->asString(delay_[latch_setup_index]), time_unit->asString(required_[latch_setup_index])); - } - } + } + } - // For hold checks, target has to be BEFORE source. - if (fuzzyLessEqual(tgt_time, src_time)) { - double delay = src_time - tgt_time; - src_past_tgt = true; - if (fuzzyLess(delay, delay_[hold_index])) { - double required = tgt_time - src_cycle_start; - setHoldAccting(src_cycle, tgt_cycle, delay, required); - debugPrint(debug, "cycle_acct", 2, + // For hold checks, target has to be BEFORE source. + if (fuzzyLessEqual(tgt_time, src_time)) { + double delay = src_time - tgt_time; + src_past_tgt = true; + if (fuzzyLess(delay, delay_[hold_index])) { + double required = tgt_time - src_cycle_start; + setHoldAccting(src_cycle, tgt_cycle, delay, required); + debugPrint(debug, "cycle_acct", 2, " hold min delay = %s, required = %s", time_unit->asString(delay_[hold_index]), time_unit->asString(required_[hold_index])); - } - } + } + } - // Gated clock hold checks are in the same cycle as the - // setup check. - if (fuzzyLessEqual(tgt_opp_time, src_time)) { - double delay = src_time - tgt_time; - if (fuzzyLess(delay, delay_[gclk_hold_index])) { - double required = tgt_time - src_cycle_start; - setAccting(TimingRole::gatedClockHold(), - src_cycle, tgt_cycle, delay, required); - debugPrint(debug, "cycle_acct", 2, + // Gated clock hold checks are in the same cycle as the + // setup check. + if (fuzzyLessEqual(tgt_opp_time, src_time)) { + double delay = src_time - tgt_time; + if (fuzzyLess(delay, delay_[gclk_hold_index])) { + double required = tgt_time - src_cycle_start; + setAccting(TimingRole::gatedClockHold(), + src_cycle, tgt_cycle, delay, required); + debugPrint(debug, "cycle_acct", 2, " gated clk hold min delay = %s, required = %s", time_unit->asString(delay_[gclk_hold_index]), time_unit->asString(required_[gclk_hold_index])); - } - } + } + } } tgt_cycle++; } @@ -297,9 +298,9 @@ CycleAccting::firstCycle(const ClockEdge *clk_edge) const void CycleAccting::setSetupAccting(int src_cycle, - int tgt_cycle, - float delay, - float req) + int tgt_cycle, + float delay, + float req) { setAccting(TimingRole::setup(), src_cycle, tgt_cycle, delay, req); setAccting(TimingRole::outputSetup(), src_cycle, tgt_cycle, delay, req); @@ -309,9 +310,9 @@ CycleAccting::setSetupAccting(int src_cycle, void CycleAccting::setHoldAccting(int src_cycle, - int tgt_cycle, - float delay, - float req) + int tgt_cycle, + float delay, + float req) { setAccting(TimingRole::hold(), src_cycle, tgt_cycle, delay, req); setAccting(TimingRole::outputHold(), src_cycle, tgt_cycle, delay, req); @@ -321,10 +322,10 @@ CycleAccting::setHoldAccting(int src_cycle, void CycleAccting::setAccting(const TimingRole *role, - int src_cycle, - int tgt_cycle, - float delay, - float req) + int src_cycle, + int tgt_cycle, + float delay, + float req) { int index = role->index(); src_cycle_[index] = src_cycle; @@ -351,9 +352,9 @@ CycleAccting::findDefaultArrivalSrcDelays() void CycleAccting::setDefaultSetupAccting(int src_cycle, - int tgt_cycle, - float delay, - float req) + int tgt_cycle, + float delay, + float req) { setSetupAccting(src_cycle, tgt_cycle, delay, req); setAccting(TimingRole::latchSetup(), src_cycle, tgt_cycle, delay, req); @@ -362,9 +363,9 @@ CycleAccting::setDefaultSetupAccting(int src_cycle, void CycleAccting::setDefaultHoldAccting(int src_cycle, - int tgt_cycle, - float delay, - float req) + int tgt_cycle, + float delay, + float req) { setHoldAccting(src_cycle, tgt_cycle, delay, req); setAccting(TimingRole::dataCheckHold(), src_cycle, tgt_cycle, delay, req); @@ -404,14 +405,14 @@ CycleAccting::targetTimeOffset(const TimingRole *check_role) bool CycleAcctingLess::operator()(const CycleAccting *acct1, - const CycleAccting *acct2) const + const CycleAccting *acct2) const { int src_index1 = acct1->src()->index(); int src_index2 = acct2->src()->index(); return src_index1 < src_index2 || (src_index1 == src_index2 - && acct1->target()->index() < acct2->target()->index()); + && acct1->target()->index() < acct2->target()->index()); } size_t @@ -422,7 +423,7 @@ CycleAcctingHash::operator()(const CycleAccting *acct) const bool CycleAcctingEqual::operator()(const CycleAccting *acct1, - const CycleAccting *acct2) const + const CycleAccting *acct2) const { return acct1->src() == acct2->src() && acct1->target() == acct2->target(); diff --git a/sdc/DataCheck.cc b/sdc/DataCheck.cc index 15a839ba..23d3abd2 100644 --- a/sdc/DataCheck.cc +++ b/sdc/DataCheck.cc @@ -30,8 +30,8 @@ namespace sta { DataCheck::DataCheck(Pin *from, - Pin *to, - Clock *clk) : + Pin *to, + Clock *clk) : from_(from), to_(to), clk_(clk) @@ -40,21 +40,21 @@ DataCheck::DataCheck(Pin *from, void DataCheck::margin(const RiseFall *from_rf, - const RiseFall *to_rf, - const SetupHold *setup_hold, - // Return values. - float &margin, - bool &exists) const + const RiseFall *to_rf, + const SetupHold *setup_hold, + // Return values. + float &margin, + bool &exists) const { return margins_[from_rf->index()].value(to_rf, setup_hold, - margin, exists); + margin, exists); } void DataCheck::setMargin(const RiseFallBoth *from_rf, - const RiseFallBoth *to_rf, - const SetupHoldAll *setup_hold, - float margin) + const RiseFallBoth *to_rf, + const SetupHoldAll *setup_hold, + float margin) { for (auto from_rf_index : from_rf->rangeIndex()) margins_[from_rf_index].setValue(to_rf, setup_hold, margin); @@ -62,8 +62,8 @@ DataCheck::setMargin(const RiseFallBoth *from_rf, void DataCheck::removeMargin(const RiseFallBoth *from_rf, - const RiseFallBoth *to_rf, - const SetupHoldAll *setup_hold) + const RiseFallBoth *to_rf, + const SetupHoldAll *setup_hold) { for (int from_rf_index : from_rf->rangeIndex()) margins_[from_rf_index].removeValue(to_rf, setup_hold); @@ -81,9 +81,9 @@ DataCheck::empty() const void DataCheck::marginIsOneValue(const SetupHold *setup_hold, - // Return values. - float &value, - bool &one_value) const + // Return values. + float &value, + bool &one_value) const { float value1, value2; if (margins_[RiseFall::riseIndex()].isOneValue(setup_hold, value1) @@ -105,7 +105,7 @@ DataCheckLess::DataCheckLess(const Network *network) : bool DataCheckLess::operator()(const DataCheck *check1, - const DataCheck *check2) const + const DataCheck *check2) const { const Pin *from1 = check1->from(); const Pin *from2 = check2->from(); @@ -115,9 +115,9 @@ DataCheckLess::operator()(const DataCheck *check1, const Clock *clk2 = check2->clk(); return network_->id(from1) < network_->id(from2) || (from1 == from2 - && (network_->id(to1) < network_->id(to2) - || (to1 == to2 - && clkCmp(clk1, clk2) < 0))); + && (network_->id(to1) < network_->id(to2) + || (to1 == to2 + && clkCmp(clk1, clk2) < 0))); } } // namespace diff --git a/sdc/DeratingFactors.cc b/sdc/DeratingFactors.cc index 34609412..3da41c41 100644 --- a/sdc/DeratingFactors.cc +++ b/sdc/DeratingFactors.cc @@ -45,9 +45,9 @@ DeratingFactors::DeratingFactors() void DeratingFactors::setFactor(PathClkOrData clk_data, - const RiseFallBoth *rf, - const EarlyLate *early_late, - float factor) + const RiseFallBoth *rf, + const EarlyLate *early_late, + float factor) { for (auto rf1 : rf->range()) factors_[int(clk_data)].setValue(rf1, early_late, factor); @@ -55,10 +55,10 @@ DeratingFactors::setFactor(PathClkOrData clk_data, void DeratingFactors::factor(PathClkOrData clk_data, - const RiseFall *rf, - const EarlyLate *early_late, - float &factor, - bool &exists) const + const RiseFall *rf, + const EarlyLate *early_late, + float &factor, + bool &exists) const { factors_[int(clk_data)].value(rf, early_late, factor, exists); } @@ -72,8 +72,8 @@ DeratingFactors::clear() void DeratingFactors::isOneValue(const EarlyLate *early_late, - bool &is_one_value, - float &value) const + bool &is_one_value, + float &value) const { bool is_one_value0, is_one_value1; float value0, value1; @@ -87,9 +87,9 @@ DeratingFactors::isOneValue(const EarlyLate *early_late, void DeratingFactors::isOneValue(PathClkOrData clk_data, - const EarlyLate *early_late, - bool &is_one_value, - float &value) const + const EarlyLate *early_late, + bool &is_one_value, + float &value) const { is_one_value = factors_[int(clk_data)].isOneValue(early_late, value); } @@ -110,32 +110,32 @@ DeratingFactorsGlobal::DeratingFactorsGlobal() void DeratingFactorsGlobal::setFactor(TimingDerateType type, - PathClkOrData clk_data, - const RiseFallBoth *rf, - const EarlyLate *early_late, - float factor) + PathClkOrData clk_data, + const RiseFallBoth *rf, + const EarlyLate *early_late, + float factor) { factors_[index(type)].setFactor(clk_data, rf, early_late, factor); } void DeratingFactorsGlobal::factor(TimingDerateType type, - PathClkOrData clk_data, - const RiseFall *rf, - const EarlyLate *early_late, - float &factor, - bool &exists) const + PathClkOrData clk_data, + const RiseFall *rf, + const EarlyLate *early_late, + float &factor, + bool &exists) const { factors_[index(type)].factor(clk_data, rf, early_late, factor, exists); } void DeratingFactorsGlobal::factor(TimingDerateCellType type, - PathClkOrData clk_data, - const RiseFall *rf, - const EarlyLate *early_late, - float &factor, - bool &exists) const + PathClkOrData clk_data, + const RiseFall *rf, + const EarlyLate *early_late, + float &factor, + bool &exists) const { factors_[index(type)].factor(clk_data, rf, early_late, factor, exists); } @@ -162,21 +162,21 @@ DeratingFactorsCell::DeratingFactorsCell() void DeratingFactorsCell::setFactor(TimingDerateCellType type, - PathClkOrData clk_data, - const RiseFallBoth *rf, - const EarlyLate *early_late, - float factor) + PathClkOrData clk_data, + const RiseFallBoth *rf, + const EarlyLate *early_late, + float factor) { factors_[index(type)].setFactor(clk_data, rf, early_late, factor); } void DeratingFactorsCell::factor(TimingDerateCellType type, - PathClkOrData clk_data, - const RiseFall *rf, - const EarlyLate *early_late, - float &factor, - bool &exists) const + PathClkOrData clk_data, + const RiseFall *rf, + const EarlyLate *early_late, + float &factor, + bool &exists) const { factors_[index(type)].factor(clk_data, rf, early_late, factor, exists); } @@ -196,8 +196,8 @@ DeratingFactorsCell::factors(TimingDerateCellType type) void DeratingFactorsCell::isOneValue(const EarlyLate *early_late, - bool &is_one_value, - float &value) const + bool &is_one_value, + float &value) const { bool is_one_value1, is_one_value2; float value1, value2; diff --git a/sdc/DisabledPorts.cc b/sdc/DisabledPorts.cc index 20f2cc36..99c99350 100644 --- a/sdc/DisabledPorts.cc +++ b/sdc/DisabledPorts.cc @@ -113,14 +113,14 @@ DisabledPorts::removeDisabledFromTo(LibertyPort *from, bool DisabledPorts::isDisabled(LibertyPort *from, LibertyPort *to, - const TimingRole *role) + const TimingRole *role) { LibertyPortPair from_to(from, to); // set_disable_timing instance does not disable timing checks. return (all_ && !role->isTimingCheck()) - || (from_ && from_->hasKey(from)) - || (to_ && to_->hasKey(to)) - || (from_to_ && from_to_->hasKey(from_to)); + || (from_ && from_->contains(from)) + || (to_ && to_->contains(to)) + || (from_to_ && from_to_->contains(from_to)); } //////////////////////////////////////////////////////////////// @@ -157,7 +157,7 @@ bool DisabledCellPorts::isDisabled(TimingArcSet *arc_set) const { return arc_sets_ - && arc_sets_->hasKey(arc_set); + && arc_sets_->contains(arc_set); } class DisabledCellPortsLess @@ -165,7 +165,7 @@ class DisabledCellPortsLess public: DisabledCellPortsLess(); bool operator()(const DisabledCellPorts *disable1, - const DisabledCellPorts *disable2); + const DisabledCellPorts *disable2); }; DisabledCellPortsLess::DisabledCellPortsLess() @@ -174,14 +174,14 @@ DisabledCellPortsLess::DisabledCellPortsLess() bool DisabledCellPortsLess::operator()(const DisabledCellPorts *disable1, - const DisabledCellPorts *disable2) + const DisabledCellPorts *disable2) { return stringLess(disable1->cell()->name(), - disable2->cell()->name()); + disable2->cell()->name()); } DisabledCellPortsSeq -sortByName(DisabledCellPortsMap *cell_map) +sortByName(const DisabledCellPortsMap *cell_map) { DisabledCellPortsSeq disables; for (auto cell_disable : *cell_map) { @@ -203,9 +203,9 @@ DisabledInstancePorts::DisabledInstancePorts(Instance *inst) : class DisabledInstPortsLess { public: - explicit DisabledInstPortsLess(const Network *network); + DisabledInstPortsLess(const Network *network); bool operator()(const DisabledInstancePorts *disable1, - const DisabledInstancePorts *disable2); + const DisabledInstancePorts *disable2); private: const Network *network_; @@ -221,7 +221,7 @@ DisabledInstPortsLess::operator()(const DisabledInstancePorts *disable1, const DisabledInstancePorts *disable2) { return stringLess(network_->pathName(disable1->instance()), - network_->pathName(disable2->instance())); + network_->pathName(disable2->instance())); } DisabledInstancePortsSeq @@ -243,12 +243,12 @@ class LibertyPortPairNameLess { public: bool operator()(const LibertyPortPair &pair1, - const LibertyPortPair &pair2); + const LibertyPortPair &pair2); }; bool LibertyPortPairNameLess::operator()(const LibertyPortPair &pair1, - const LibertyPortPair &pair2) + const LibertyPortPair &pair2) { const char *from1 = pair1.first->name(); const char *from2 = pair2.first->name(); diff --git a/sdc/ExceptionPath.cc b/sdc/ExceptionPath.cc index 163dcf65..70d131c9 100644 --- a/sdc/ExceptionPath.cc +++ b/sdc/ExceptionPath.cc @@ -26,6 +26,7 @@ #include +#include "ContainerHelpers.hh" #include "MinMax.hh" #include "TimingRole.hh" #include "Units.hh" @@ -41,20 +42,20 @@ using std::string; static bool thrusIntersectPts(ExceptionThruSeq *thrus1, - ExceptionThruSeq *thrus2, + ExceptionThruSeq *thrus2, const Network *network); static void insertPinPairsThruHierPin(const Pin *hpin, - const Network *network, - PinPairSet *pairs); + const Network *network, + PinPairSet *pairs); static void insertPinPairsThruNet(const Net *net, - const Network *network, - PinPairSet *pairs); + const Network *network, + PinPairSet *pairs); static void deletePinPairsThruHierPin(const Pin *hpin, - const Network *network, - PinPairSet *pairs); + const Network *network, + PinPairSet *pairs); //////////////////////////////////////////////////////////////// @@ -66,20 +67,20 @@ EmptyExpceptionPt::what() const noexcept void checkFromThrusTo(ExceptionFrom *from, - ExceptionThruSeq *thrus, - ExceptionTo *to) + ExceptionThruSeq *thrus, + ExceptionTo *to) { bool found_empty = ((from && !from->hasObjects()) - || (to - && (!to->hasObjects() - && to->transition() - == RiseFallBoth::riseFall() - && (to->endTransition() - == RiseFallBoth::riseFall())))); + || (to + && (!to->hasObjects() + && to->transition() + == RiseFallBoth::riseFall() + && (to->endTransition() + == RiseFallBoth::riseFall())))); if (thrus) { for (ExceptionThru *thru : *thrus) { if (!thru->hasObjects()) - found_empty = true; + found_empty = true; } } if (found_empty) @@ -87,12 +88,12 @@ checkFromThrusTo(ExceptionFrom *from, } ExceptionPath::ExceptionPath(ExceptionFrom *from, - ExceptionThruSeq *thrus, - ExceptionTo *to, - const MinMaxAll *min_max, - bool own_pts, - int priority, - const char *comment) : + ExceptionThruSeq *thrus, + ExceptionTo *to, + const MinMaxAll *min_max, + bool own_pts, + int priority, + const char *comment) : SdcCmdComment(comment), from_(from), thrus_(thrus), @@ -111,7 +112,7 @@ ExceptionPath::~ExceptionPath() delete from_; delete to_; if (thrus_) { - thrus_->deleteContents(); + deleteContents(*thrus_); delete thrus_; } } @@ -156,7 +157,7 @@ ExceptionPath::firstPt() bool ExceptionPath::matchesFirstPt(const RiseFall *to_rf, - const MinMax *min_max) + const MinMax *min_max) { ExceptionPt *first_pt = firstPt(); return first_pt->transition()->matches(to_rf) @@ -165,7 +166,7 @@ ExceptionPath::matchesFirstPt(const RiseFall *to_rf, bool ExceptionPath::matches(const MinMax *min_max, - bool) const + bool) const { return min_max_->matches(min_max); } @@ -190,8 +191,8 @@ ExceptionPath::setPriority(int priority) // priority over an exception without this type of qualifier. int ExceptionPath::fromThruToPriority(ExceptionFrom *from, - ExceptionThruSeq *thrus, - ExceptionTo *to) + ExceptionThruSeq *thrus, + ExceptionTo *to) { int priority = 0; if (from && (from->hasPins() || from->hasInstances())) @@ -244,44 +245,47 @@ ExceptionPath::mergeablePts(ExceptionPath *exception) const bool ExceptionPath::mergeablePts(ExceptionPath *exception2, - ExceptionPt *missing_pt2, - ExceptionPt *&missing_pt) const + ExceptionPt *missing_pt2, + ExceptionPt *&missing_pt) const { missing_pt = nullptr; ExceptionFrom *from2 = exception2->from(); if ((from_ && from2 && !(from_->transition() == from2->transition() - && (from2 == missing_pt2 - || from_->equal(from2)))) + && (from2 == missing_pt2 + || from_->equal(from2)))) || (from_ && from2 == nullptr) || (from_ == nullptr && from2)) return false; if (from2 == missing_pt2) missing_pt = from_; - ExceptionThruSeq::Iterator thru_iter(thrus_); - ExceptionThruSeq::Iterator thru_iter2(exception2->thrus()); - while (thru_iter.hasNext() - && thru_iter2.hasNext()) { - ExceptionThru *thru = thru_iter.next(); - ExceptionThru *thru2 = thru_iter2.next(); - if (!(thru->transition() == thru2->transition() - && (thru2 == missing_pt2 - || thru->equal(thru)))) + ExceptionThruSeq *thrus2 = exception2->thrus(); + if (thrus_ && thrus2) { + ExceptionThruSeq::iterator thru_iter1 = thrus_->begin(); + ExceptionThruSeq::iterator thru_iter2 = thrus2->begin(); + while (thru_iter1 != thrus_->end() + && thru_iter2 != thrus2->end()) { + ExceptionThru *thru1 = *thru_iter1++; + ExceptionThru *thru2 = *thru_iter2++; + if (!(thru1->transition() == thru2->transition() + && (thru2 == missing_pt2 + || thru1->equal(thru2)))) + return false; + if (thru2 == missing_pt2) + missing_pt = thru1; + } + if (thru_iter1 != thrus_->end() + || thru_iter2 != thrus2->end()) return false; - if (thru2 == missing_pt2) - missing_pt = thru; } - if (thru_iter.hasNext() - || thru_iter2.hasNext()) - return false; ExceptionTo *to2 = exception2->to(); if ((to_ && to2 && !(to_->transition() == to2->transition() - && to_->endTransition() == to2->endTransition() - && (to2 == missing_pt2 - || to_->equal(to2)))) + && to_->endTransition() == to2->endTransition() + && (to2 == missing_pt2 + || to_->equal(to2)))) || (to_ && to2 == nullptr) || (to_ == nullptr && to2)) return false; @@ -300,16 +304,19 @@ ExceptionPath::intersectsPts(ExceptionPath *exception, if (((from_ == nullptr && from2 == nullptr) || (from_ && from2 && from_->intersectsPts(from2, network))) && ((thrus_ == nullptr && thrus2 == nullptr) - || (thrus_ && thrus2 && thrus_->size() == thrus2->size())) + || (thrus_ && thrus2 && thrus_->size() == thrus2->size())) && ((to_ == nullptr && to2 == nullptr) - || (to_ && to2 && to_->intersectsPts(to2, network)))) { - ExceptionThruSeq::Iterator thrus_iter1(thrus_); - ExceptionThruSeq::Iterator thrus_iter2(thrus2); - while (thrus_iter1.hasNext() && thrus_iter2.hasNext()) { - ExceptionThru *thru1 = thrus_iter1.next(); - ExceptionThru *thru2 = thrus_iter2.next(); - if (!thru1->intersectsPts(thru2, network)) - return false; + || (to_ && to2 && to_->intersectsPts(to2, network)))) { + if (thrus_ && thrus2) { + ExceptionThruSeq::iterator thru_iter1 = thrus_->begin(); + ExceptionThruSeq::iterator thru_iter2 = thrus2->begin(); + while (thru_iter1 != thrus_->end() + && thru_iter2 != thrus2->end()) { + ExceptionThru *thru1 = *thru_iter1++; + ExceptionThru *thru2 = *thru_iter2++; + if (!thru1->intersectsPts(thru2, network)) + return false; + } } return true; } @@ -390,9 +397,9 @@ ExceptionPath::makeStates() bool ExceptionPath::resetMatch(ExceptionFrom *from, - ExceptionThruSeq *thrus, - ExceptionTo *to, - const MinMaxAll *min_max, + ExceptionThruSeq *thrus, + ExceptionTo *to, + const MinMaxAll *min_max, const Network *network) { // Only the reset expception points need to match. @@ -400,58 +407,59 @@ ExceptionPath::resetMatch(ExceptionFrom *from, // exceptions that match the -from even if they are more specific. // -from return ((from && from_ - && thrus == nullptr - && to == nullptr - && from_->intersectsPts(from, network)) - // -thru - || (from == nullptr - && thrus && thrus_ - && to == nullptr - && thrusIntersectPts(thrus_, thrus, network)) - // -to - || (from == nullptr - && thrus == nullptr - && to && to_ - && to_->intersectsPts(to, network)) - // -from -thru - || (from && from_ - && thrus && thrus_ - && to == nullptr - && from_->intersectsPts(from, network) - && thrusIntersectPts(thrus_, thrus, network)) - // -from -to - || (from && from_ - && thrus == nullptr - && to && to_ - && from_->intersectsPts(from, network) - && to_->intersectsPts(to, network)) - // -thru -to - || (from == nullptr - && thrus && thrus_ - && to && to_ - && thrusIntersectPts(thrus_, thrus, network) - && to_->intersectsPts(to, network)) - // -from -thru -to - || (from && from_ - && thrus && thrus_ - && to && to_ - && from_->intersectsPts(from, network) - && thrusIntersectPts(thrus_, thrus, network) - && to_->intersectsPts(to, network))) + && thrus == nullptr + && to == nullptr + && from_->intersectsPts(from, network)) + // -thru + || (from == nullptr + && thrus && thrus_ + && to == nullptr + && thrusIntersectPts(thrus_, thrus, network)) + // -to + || (from == nullptr + && thrus == nullptr + && to && to_ + && to_->intersectsPts(to, network)) + // -from -thru + || (from && from_ + && thrus && thrus_ + && to == nullptr + && from_->intersectsPts(from, network) + && thrusIntersectPts(thrus_, thrus, network)) + // -from -to + || (from && from_ + && thrus == nullptr + && to && to_ + && from_->intersectsPts(from, network) + && to_->intersectsPts(to, network)) + // -thru -to + || (from == nullptr + && thrus && thrus_ + && to && to_ + && thrusIntersectPts(thrus_, thrus, network) + && to_->intersectsPts(to, network)) + // -from -thru -to + || (from && from_ + && thrus && thrus_ + && to && to_ + && from_->intersectsPts(from, network) + && thrusIntersectPts(thrus_, thrus, network) + && to_->intersectsPts(to, network))) && (min_max == MinMaxAll::all() - || min_max_ == min_max); + || min_max_ == min_max); } static bool thrusIntersectPts(ExceptionThruSeq *thrus1, - ExceptionThruSeq *thrus2, + ExceptionThruSeq *thrus2, const Network *network) { - ExceptionThruSeq::Iterator thrus_iter1(thrus1); - ExceptionThruSeq::Iterator thrus_iter2(thrus2); - while (thrus_iter1.hasNext() && thrus_iter2.hasNext()) { - ExceptionThru *thru1 = thrus_iter1.next(); - ExceptionThru *thru2 = thrus_iter2.next(); + ExceptionThruSeq::iterator thru_iter1 = thrus1->begin(); + ExceptionThruSeq::iterator thru_iter2 = thrus2->begin(); + while (thru_iter1 != thrus1->end() + && thru_iter2 != thrus2->end()) { + ExceptionThru *thru1 = *thru_iter1++; + ExceptionThru *thru2 = *thru_iter2++; if (!thru1->intersectsPts(thru2, network)) return false; } @@ -475,17 +483,17 @@ ExceptionPath::deleteInstance(const Instance *inst, //////////////////////////////////////////////////////////////// PathDelay::PathDelay(ExceptionFrom *from, - ExceptionThruSeq *thrus, - ExceptionTo *to, - const MinMax *min_max, - bool ignore_clk_latency, + ExceptionThruSeq *thrus, + ExceptionTo *to, + const MinMax *min_max, + bool ignore_clk_latency, bool break_path, - float delay, - bool own_pts, - const char *comment) : + float delay, + bool own_pts, + const char *comment) : ExceptionPath(from, thrus, to, min_max->asMinMaxAll(), own_pts, - pathDelayPriority() + fromThruToPriority(from, thrus, to), - comment), + pathDelayPriority() + fromThruToPriority(from, thrus, to), + comment), ignore_clk_latency_(ignore_clk_latency), break_path_(break_path), delay_(delay) @@ -494,12 +502,12 @@ PathDelay::PathDelay(ExceptionFrom *from, ExceptionPath * PathDelay::clone(ExceptionFrom *from, - ExceptionThruSeq *thrus, - ExceptionTo *to, - bool own_pts) + ExceptionThruSeq *thrus, + ExceptionTo *to, + bool own_pts) { return new PathDelay(from, thrus, to, min_max_->asMinMax(), - ignore_clk_latency_, break_path_, delay_, + ignore_clk_latency_, break_path_, delay_, own_pts, comment_); } @@ -523,8 +531,8 @@ PathDelay::asString(const Network *network) const { const char *from_thru_to = fromThruToString(network); const char *result = stringPrintTmp("PathDelay %.3fns%s", - delay_ * 1E+9F, - from_thru_to); + delay_ * 1E+9F, + from_thru_to); return result; } @@ -565,33 +573,33 @@ PathDelay::overrides(ExceptionPath *exception) const //////////////////////////////////////////////////////////////// FalsePath::FalsePath(ExceptionFrom *from, - ExceptionThruSeq *thrus, - ExceptionTo *to, - const MinMaxAll *min_max, - bool own_pts, - const char *comment) : + ExceptionThruSeq *thrus, + ExceptionTo *to, + const MinMaxAll *min_max, + bool own_pts, + const char *comment) : ExceptionPath(from, thrus, to, min_max, own_pts, - falsePathPriority() + fromThruToPriority(from, thrus, to), - comment) + falsePathPriority() + fromThruToPriority(from, thrus, to), + comment) { } FalsePath::FalsePath(ExceptionFrom *from, - ExceptionThruSeq *thrus, - ExceptionTo *to, - const MinMaxAll *min_max, - bool own_pts, - int priority, - const char *comment) : + ExceptionThruSeq *thrus, + ExceptionTo *to, + const MinMaxAll *min_max, + bool own_pts, + int priority, + const char *comment) : ExceptionPath(from, thrus, to, min_max, own_pts, priority, comment) { } ExceptionPath * FalsePath::clone(ExceptionFrom *from, - ExceptionThruSeq *thrus, - ExceptionTo *to, - bool own_pts) + ExceptionThruSeq *thrus, + ExceptionTo *to, + bool own_pts) { return new FalsePath(from, thrus, to, min_max_, own_pts, comment_); } @@ -631,10 +639,10 @@ FalsePath::overrides(ExceptionPath *exception) const //////////////////////////////////////////////////////////////// LoopPath::LoopPath(ExceptionThruSeq *thrus, - bool own_pts) : + bool own_pts) : FalsePath(nullptr, thrus, nullptr, MinMaxAll::all(), own_pts, - falsePathPriority() + fromThruToPriority(nullptr, thrus, nullptr), - nullptr) + falsePathPriority() + fromThruToPriority(nullptr, thrus, nullptr), + nullptr) { } @@ -653,16 +661,16 @@ LoopPath::mergeable(ExceptionPath *) const //////////////////////////////////////////////////////////////// MultiCyclePath::MultiCyclePath(ExceptionFrom *from, - ExceptionThruSeq *thrus, - ExceptionTo *to, - const MinMaxAll *min_max, - bool use_end_clk, - int path_multiplier, - bool own_pts, - const char *comment) : + ExceptionThruSeq *thrus, + ExceptionTo *to, + const MinMaxAll *min_max, + bool use_end_clk, + int path_multiplier, + bool own_pts, + const char *comment) : ExceptionPath(from, thrus, to, min_max, own_pts, - multiCyclePathPriority() + fromThruToPriority(from, thrus, to), - comment), + multiCyclePathPriority() + fromThruToPriority(from, thrus, to), + comment), use_end_clk_(use_end_clk), path_multiplier_(path_multiplier) { @@ -670,12 +678,12 @@ MultiCyclePath::MultiCyclePath(ExceptionFrom *from, ExceptionPath * MultiCyclePath::clone(ExceptionFrom *from, - ExceptionThruSeq *thrus, - ExceptionTo *to, - bool own_pts) + ExceptionThruSeq *thrus, + ExceptionTo *to, + bool own_pts) { return new MultiCyclePath(from, thrus, to, min_max_, use_end_clk_, - path_multiplier_, own_pts, comment_); + path_multiplier_, own_pts, comment_); } int @@ -714,7 +722,7 @@ MultiCyclePath::tighterThan(ExceptionPath *exception) const bool MultiCyclePath::matches(const MinMax *min_max, - bool exactly) const + bool exactly) const { return min_max_->matches(min_max) // set_multicycle_path -setup determines hold check accounting, @@ -727,9 +735,9 @@ MultiCyclePath::asString(const Network *network) const { const char *from_thru_to = fromThruToString(network); const char *result = stringPrintTmp("Multicycle %s %d%s", - (use_end_clk_) ? "-end" : "-start", - path_multiplier_, - from_thru_to); + (use_end_clk_) ? "-end" : "-start", + path_multiplier_, + from_thru_to); return result; } @@ -758,12 +766,12 @@ MultiCyclePath::overrides(ExceptionPath *exception) const //////////////////////////////////////////////////////////////// FilterPath::FilterPath(ExceptionFrom *from, - ExceptionThruSeq *thrus, - ExceptionTo *to, - bool own_pts) : + ExceptionThruSeq *thrus, + ExceptionTo *to, + bool own_pts) : ExceptionPath(from, thrus, to, MinMaxAll::all(), own_pts, - filterPathPriority() + fromThruToPriority(from, thrus, to), - nullptr) + filterPathPriority() + fromThruToPriority(from, thrus, to), + nullptr) { } @@ -775,9 +783,9 @@ FilterPath::typeString() const ExceptionPath * FilterPath::clone(ExceptionFrom *from, - ExceptionThruSeq *thrus, - ExceptionTo *to, - bool own_pts) + ExceptionThruSeq *thrus, + ExceptionTo *to, + bool own_pts) { return new FilterPath(from, thrus, to, own_pts); } @@ -810,9 +818,9 @@ FilterPath::overrides(ExceptionPath *) const bool FilterPath::resetMatch(ExceptionFrom *, - ExceptionThruSeq *, - ExceptionTo *, - const MinMaxAll *, + ExceptionThruSeq *, + ExceptionTo *, + const MinMaxAll *, const Network *) { return false; @@ -821,15 +829,15 @@ FilterPath::resetMatch(ExceptionFrom *, //////////////////////////////////////////////////////////////// GroupPath::GroupPath(const char *name, - bool is_default, - ExceptionFrom *from, - ExceptionThruSeq *thrus, - ExceptionTo *to, - bool own_pts, - const char *comment) : + bool is_default, + ExceptionFrom *from, + ExceptionThruSeq *thrus, + ExceptionTo *to, + bool own_pts, + const char *comment) : ExceptionPath(from, thrus, to, MinMaxAll::all(), own_pts, - groupPathPriority() + fromThruToPriority(from, thrus, to), - comment), + groupPathPriority() + fromThruToPriority(from, thrus, to), + comment), name_(stringCopy(name)), is_default_(is_default) { @@ -848,12 +856,12 @@ GroupPath::typeString() const ExceptionPath * GroupPath::clone(ExceptionFrom *from, - ExceptionThruSeq *thrus, - ExceptionTo *to, - bool own_pts) + ExceptionThruSeq *thrus, + ExceptionTo *to, + bool own_pts) { return new GroupPath(name_, is_default_, from, thrus, to, own_pts, - comment_); + comment_); } int @@ -889,7 +897,7 @@ GroupPath::overrides(ExceptionPath *exception) const const int ExceptionPt::as_string_max_objects_ = 20; ExceptionPt::ExceptionPt(const RiseFallBoth *rf, - bool own_pts) : + bool own_pts) : rf_(rf), own_pts_(own_pts), hash_(0) @@ -905,10 +913,10 @@ ExceptionPt::hash() const } ExceptionFromTo::ExceptionFromTo(PinSet *pins, - ClockSet *clks, - InstanceSet *insts, - const RiseFallBoth *rf, - bool own_pts, + ClockSet *clks, + InstanceSet *insts, + const RiseFallBoth *rf, + bool own_pts, const Network *network) : ExceptionPt(rf, own_pts), pins_(pins), @@ -979,8 +987,8 @@ ExceptionFromTo::allPins(const Network *network) for (const Instance *inst : *insts_) { InstancePinIterator *pin_iter = network->pinIterator(inst); while (pin_iter->hasNext()) { - const Pin *pin = pin_iter->next(); - pins.insert(pin); + const Pin *pin = pin_iter->next(); + pins.insert(pin); } delete pin_iter; } @@ -1015,30 +1023,33 @@ ExceptionFromTo::findHash(const Network *network) bool ExceptionFromTo::equal(ExceptionFromTo *from_to) const { - return PinSet::equal(from_to->pins_, pins_) - && ClockSet::equal(from_to->clks_, clks_) - && InstanceSet::equal(from_to->insts_, insts_) + return ((from_to->pins_ == nullptr && pins_ == nullptr) + || (from_to->pins_ && pins_ && *from_to->pins_ == *pins_)) + && ((from_to->clks_ == nullptr && clks_ == nullptr) + || (from_to->clks_ && clks_ && *from_to->clks_ == *clks_)) + && ((from_to->insts_ == nullptr && insts_ == nullptr) + || (from_to->insts_ && insts_ && *from_to->insts_ == *insts_)) && from_to->transition() == rf_; } int ExceptionFromTo::compare(ExceptionPt *pt2, - const Network *network) const + const Network *network) const { int priority_cmp = typePriority() - pt2->typePriority(); if (priority_cmp == 0) { - int pin_cmp = PinSet::compare(pins_, pt2->pins(), network); + int pin_cmp = sta::compare(pins_, pt2->pins(), network); if (pin_cmp == 0) { int clk_cmp = sta::compare(clks_, pt2->clks()); if (clk_cmp == 0) { - int inst_cmp = InstanceSet::compare(insts_, pt2->instances(), network); - if (inst_cmp == 0) - return rf_->index() - pt2->transition()->index(); - else - return inst_cmp; + int inst_cmp = sta::compare(insts_, pt2->instances(), network); + if (inst_cmp == 0) + return rf_->index() - pt2->transition()->index(); + else + return inst_cmp; } else - return clk_cmp; + return clk_cmp; } else return pin_cmp; @@ -1092,7 +1103,7 @@ ExceptionFromTo::addPin(const Pin *pin, { if (pins_ == nullptr) pins_ = new PinSet(network); - if (!pins_->hasKey(pin)) { + if (!pins_->contains(pin)) { pins_->insert(pin); // Incrementally update hash. hash_ += network->id(pin) * hash_pin; @@ -1104,7 +1115,7 @@ ExceptionFromTo::addClock(Clock *clk) { if (clks_ == nullptr) clks_ = new ClockSet; - if (!clks_->hasKey(clk)) { + if (!clks_->contains(clk)) { clks_->insert(clk); // Incrementally update hash. hash_ += clk->index() * hash_clk; @@ -1117,7 +1128,7 @@ ExceptionFromTo::addInstance(const Instance *inst, { if (insts_ == nullptr) insts_ = new InstanceSet(network); - if (!insts_->hasKey(inst)) { + if (!insts_->contains(inst)) { insts_->insert(inst); // Incrementally update hash. hash_ += network->id(inst) * hash_inst; @@ -1186,7 +1197,7 @@ ExceptionFromTo::asString(const Network *network) const PinSeq pins = sortByPathName(pins_, network); for (const Pin *pin : pins) { if (!first) - str += ", "; + str += ", "; str += network->pathName(pin); first = false; obj_count++; @@ -1198,7 +1209,7 @@ ExceptionFromTo::asString(const Network *network) const ClockSeq clks = sortByName(clks_); for (Clock *clk : clks) { if (!first) - str += ", "; + str += ", "; str += clk->name(); first = false; obj_count++; @@ -1210,7 +1221,7 @@ ExceptionFromTo::asString(const Network *network) const InstanceSeq insts = sortByPathName(insts_, network); for (const Instance *inst : insts) { if (!first) - str += ", "; + str += ", "; str += network->pathName(inst); first = false; obj_count++; @@ -1244,10 +1255,10 @@ ExceptionFromTo::objectCount() const //////////////////////////////////////////////////////////////// ExceptionFrom::ExceptionFrom(PinSet *pins, - ClockSet *clks, - InstanceSet *insts, - const RiseFallBoth *rf, - bool own_pts, + ClockSet *clks, + InstanceSet *insts, + const RiseFallBoth *rf, + bool own_pts, const Network *network) : ExceptionFromTo(pins, clks, insts, rf, own_pts, network) { @@ -1275,14 +1286,35 @@ ExceptionFrom::clone(const Network *network) return new ExceptionFrom(pins, clks, insts, rf_, true, network); } +bool +clkSetIntersects(ClockSet *set1, + ClockSet *set2) +{ + if (set1 && set2) { + auto iter1 = set1->begin(); + auto end1 = set1->end(); + auto iter2 = set2->begin(); + auto end2 = set2->end(); + while (iter1 != end1 && iter2 != end2) { + if (ClockIndexLess()(*iter1, *iter2)) + iter1++; + else if (ClockIndexLess()(*iter2, *iter1)) + iter2++; + else + return true; + } + } + return false; +} + bool ExceptionFrom::intersectsPts(ExceptionFrom *from, const Network *network) const { return from->transition() == rf_ - && ((pins_ && PinSet::intersects(pins_, from->pins(), network)) - || (clks_ && ClockSet::intersects(clks_, from->clks(), ClockIndexLess())) - || (insts_ && InstanceSet::intersects(insts_, from->instances(), network))); + && ((pins_ && intersects(pins_, from->pins(), network)) + || (clks_ && clkSetIntersects(clks_, from->clks())) + || (insts_ && intersects(insts_, from->instances(), network))); } const char * @@ -1299,11 +1331,11 @@ ExceptionFrom::cmdKeyword() const //////////////////////////////////////////////////////////////// ExceptionTo::ExceptionTo(PinSet *pins, - ClockSet *clks, - InstanceSet *insts, - const RiseFallBoth *rf, - const RiseFallBoth *end_rf, - bool own_pts, + ClockSet *clks, + InstanceSet *insts, + const RiseFallBoth *rf, + const RiseFallBoth *end_rf, + bool own_pts, const Network *network) : ExceptionFromTo(pins, clks, insts, rf, own_pts, network), end_rf_(end_rf) @@ -1346,16 +1378,16 @@ ExceptionTo::intersectsPts(ExceptionTo *to, { return to->transition() == rf_ && to->endTransition() == end_rf_ - && ((pins_ && PinSet::intersects(pins_, to->pins(), network)) - || (clks_ && ClockSet::intersects(clks_, to->clks(), ClockIndexLess())) - || (insts_ && InstanceSet::intersects(insts_, to->instances(), network))); + && ((pins_ && intersects(pins_, to->pins(), network)) + || (clks_ && clkSetIntersects(clks_, to->clks())) + || (insts_ && intersects(insts_, to->instances(), network))); } bool ExceptionTo::matchesFilter(const Pin *pin, - const ClockEdge *clk_edge, - const RiseFall *end_rf, - const Network *network) const + const ClockEdge *clk_edge, + const RiseFall *end_rf, + const Network *network) const { // "report -to reg" matches clock pins. return matches(pin, clk_edge, end_rf, true, network); @@ -1363,9 +1395,9 @@ ExceptionTo::matchesFilter(const Pin *pin, bool ExceptionTo::matches(const Pin *pin, - const ClockEdge *clk_edge, - const RiseFall *end_rf, - const Network *network) const + const ClockEdge *clk_edge, + const RiseFall *end_rf, + const Network *network) const { // "exception -to reg" does not match reg clock pins. return matches(pin, clk_edge, end_rf, false, network); @@ -1373,71 +1405,71 @@ ExceptionTo::matches(const Pin *pin, bool ExceptionTo::matches(const Pin *pin, - const ClockEdge *clk_edge, - const RiseFall *end_rf, - bool inst_matches_reg_clk_pin, - const Network *network) const + const ClockEdge *clk_edge, + const RiseFall *end_rf, + bool inst_matches_reg_clk_pin, + const Network *network) const { return (pins_ - && pins_->hasKey(const_cast(pin)) - && rf_->matches(end_rf) - && end_rf_->matches(end_rf)) + && pins_->contains(const_cast(pin)) + && rf_->matches(end_rf) + && end_rf_->matches(end_rf)) || (clk_edge - && clks_ - && clks_->hasKey(const_cast(clk_edge->clock())) - && rf_->matches(clk_edge->transition()) - && end_rf_->matches(end_rf)) + && clks_ + && clks_->contains(clk_edge->clock()) + && rf_->matches(clk_edge->transition()) + && end_rf_->matches(end_rf)) || (insts_ - && (inst_matches_reg_clk_pin - || !network->isRegClkPin(pin)) - && insts_->hasKey(network->instance(pin)) - && (network->direction(pin)->isAnyInput() + && (inst_matches_reg_clk_pin + || !network->isRegClkPin(pin)) + && insts_->contains(network->instance(pin)) + && (network->direction(pin)->isAnyInput() || network->direction(pin)->isInternal()) - && rf_->matches(end_rf) - && end_rf_->matches(end_rf)) + && rf_->matches(end_rf) + && end_rf_->matches(end_rf)) || (pins_ == nullptr - && clks_ == nullptr - && insts_ == nullptr - && end_rf_->matches(end_rf)); + && clks_ == nullptr + && insts_ == nullptr + && end_rf_->matches(end_rf)); } bool ExceptionTo::matches(const Pin *pin, - const RiseFall *end_rf, - const Network *network) const + const RiseFall *end_rf, + const Network *network) const { return (pins_ - && pins_->hasKey(const_cast(pin)) - && rf_->matches(end_rf) - && end_rf_->matches(end_rf)) + && pins_->contains(const_cast(pin)) + && rf_->matches(end_rf) + && end_rf_->matches(end_rf)) || (insts_ - && insts_->hasKey(network->instance(pin)) - && (network->direction(pin)->isAnyInput() + && insts_->contains(network->instance(pin)) + && (network->direction(pin)->isAnyInput() || network->direction(pin)->isInternal()) - && rf_->matches(end_rf) - && end_rf_->matches(end_rf)); + && rf_->matches(end_rf) + && end_rf_->matches(end_rf)); } bool ExceptionTo::matches(const Pin *pin, - const RiseFall *end_rf) const + const RiseFall *end_rf) const { return (pins_ - && pins_->hasKey(const_cast(pin)) - && rf_->matches(end_rf) - && end_rf_->matches(end_rf)) + && pins_->contains(const_cast(pin)) + && rf_->matches(end_rf) + && end_rf_->matches(end_rf)) || (pins_ == nullptr - && clks_ == nullptr - && insts_ == nullptr - && end_rf_->matches(end_rf)); + && clks_ == nullptr + && insts_ == nullptr + && end_rf_->matches(end_rf)); } bool ExceptionTo::matches(const Clock *clk) const { return clks_ - && clks_->hasKey(const_cast(clk)); + && clks_->contains(const_cast(clk)); } const char * @@ -1453,7 +1485,7 @@ ExceptionTo::cmdKeyword() const int ExceptionTo::compare(ExceptionPt *pt2, - const Network *network) const + const Network *network) const { ExceptionTo *to2 = dynamic_cast(pt2); int cmp = ExceptionFromTo::compare(pt2, network); @@ -1466,11 +1498,11 @@ ExceptionTo::compare(ExceptionPt *pt2, //////////////////////////////////////////////////////////////// ExceptionThru::ExceptionThru(PinSet *pins, - NetSet *nets, - InstanceSet *insts, - const RiseFallBoth *rf, - bool own_pts, - const Network *network) : + NetSet *nets, + InstanceSet *insts, + const RiseFallBoth *rf, + bool own_pts, + const Network *network) : ExceptionPt(rf, own_pts), pins_(pins), edges_(nullptr), @@ -1521,7 +1553,7 @@ ExceptionThru::makePinEdges(const Network *network) // but before the pin has been deleted from the netlist. void ExceptionThru::deletePinEdges(const Pin *pin, - Network *network) + Network *network) { // Incrementally delete only edges through (hier) or from/to (leaf) the pin. if (edges_ && network->net(pin)) { @@ -1530,12 +1562,12 @@ ExceptionThru::deletePinEdges(const Pin *pin, // deletePinPairsThruHierPin. PinSet *drvrs = network->drivers(pin); if (drvrs) { - // Some edges originating at drvrs may not actually go through pin, so - // still must use deletePinPairsThruHierPin to identify specific edges. - if (edges_) { - for (const EdgePins &edge_pins : *edges_) { + // Some edges originating at drvrs may not actually go through pin, so + // still must use deletePinPairsThruHierPin to identify specific edges. + if (edges_) { + for (const EdgePins &edge_pins : *edges_) { const Pin *p_first = edge_pins.first; - if (drvrs->hasKey(p_first)) { + if (drvrs->contains(p_first)) { deletePinPairsThruHierPin(pin, network, edges_); break; } @@ -1545,13 +1577,13 @@ ExceptionThru::deletePinEdges(const Pin *pin, } else { // erase prevents range iteration. - EdgePinsSet::Iterator edge_iter(edges_); - while (edge_iter.hasNext()) { - const EdgePins &edge_pins = edge_iter.next(); + for (auto itr = edges_->begin(); itr != edges_->end(); /* no incr */) { + const EdgePins &edge_pins = *itr; if (edge_pins.first == pin - || edge_pins.second == pin) { - edges_->erase(edge_pins); - } + || edge_pins.second == pin) + itr = edges_->erase(itr); + else + itr++; } } } @@ -1559,7 +1591,7 @@ ExceptionThru::deletePinEdges(const Pin *pin, void ExceptionThru::makeHpinEdges(const Pin *pin, - const Network *network) + const Network *network) { if (edges_ == nullptr) edges_ = new EdgePinsSet(network); @@ -1580,7 +1612,7 @@ ExceptionThru::makeNetEdges(const Network *network) void ExceptionThru::makeNetEdges(const Net *net, - const Network *network) + const Network *network) { if (edges_ == nullptr) edges_ = new EdgePinsSet(network); @@ -1595,8 +1627,8 @@ ExceptionThru::makeInstEdges(const Network *network) if (network->isHierarchical(inst)) { InstancePinIterator *pin_iter = network->pinIterator(inst); while (pin_iter->hasNext()) { - Pin *pin = pin_iter->next(); - makeHpinEdges(pin, network); + Pin *pin = pin_iter->next(); + makeHpinEdges(pin, network); } delete pin_iter; } @@ -1605,7 +1637,7 @@ ExceptionThru::makeInstEdges(const Network *network) void ExceptionThru::makeInstEdges(Instance *inst, - Network *network) + Network *network) { if (network->isHierarchical(inst)) { InstancePinIterator *pin_iter = network->pinIterator(inst); @@ -1621,7 +1653,7 @@ ExceptionThru::makeInstEdges(Instance *inst, // but before the inst has been deleted from the netlist. void ExceptionThru::deleteInstEdges(Instance *inst, - Network *network) + Network *network) { // Incrementally delete edges through each hier pin. if (edges_) { @@ -1654,7 +1686,7 @@ ExceptionThru::asString(const Network *network) const PinSeq pins = sortByPathName(pins_, network); for (const Pin *pin : pins) { if (!first) - str += ", "; + str += ", "; str += network->pathName(pin); first = false; obj_count++; @@ -1666,7 +1698,7 @@ ExceptionThru::asString(const Network *network) const NetSeq nets = sortByPathName(nets_, network); for (const Net *net : nets) { if (!first) - str += ", "; + str += ", "; str += network->pathName(net); first = false; obj_count++; @@ -1678,7 +1710,7 @@ ExceptionThru::asString(const Network *network) const InstanceSeq insts = sortByPathName(insts_, network); for (const Instance *inst : insts) { if (!first) - str += ", "; + str += ", "; str += network->pathName(inst); first = false; obj_count++; @@ -1700,7 +1732,7 @@ ExceptionThru::asString(const Network *network) const ExceptionThruSeq * exceptionThrusClone(ExceptionThruSeq *thrus, - const Network *network) + const Network *network) { if (thrus) { ExceptionThruSeq *thrus_cpy = new ExceptionThruSeq; @@ -1744,7 +1776,7 @@ ExceptionThru::addPin(const Pin *pin, { if (pins_ == nullptr) pins_ = new PinSet(network); - if (!pins_->hasKey(pin)) { + if (!pins_->contains(pin)) { pins_->insert(pin); // Incrementally update hash. hash_ += network->id(pin) * hash_pin; @@ -1757,7 +1789,7 @@ ExceptionThru::addNet(const Net *net, { if (nets_ == nullptr) nets_ = new NetSet(network); - if (!nets_->hasKey(net)) { + if (!nets_->contains(net)) { nets_->insert(net); // Incrementally update hash. hash_ += network->id(net) * hash_net; @@ -1770,7 +1802,7 @@ ExceptionThru::addInstance(const Instance *inst, { if (insts_ == nullptr) insts_ = new InstanceSet(network); - if (!insts_->hasKey(inst)) { + if (!insts_->contains(inst)) { insts_->insert(inst); // Incrementally update hash. hash_ += network->id(inst) * hash_inst; @@ -1849,8 +1881,8 @@ ExceptionThru::allPins(const Network *network) for (const Instance *inst : *insts_) { InstancePinIterator *pin_iter = network->pinIterator(inst); while (pin_iter->hasNext()) { - Pin *pin = pin_iter->next(); - pins.insert(pin); + Pin *pin = pin_iter->next(); + pins.insert(pin); } delete pin_iter; } @@ -1859,8 +1891,8 @@ ExceptionThru::allPins(const Network *network) for (const Net *net : *nets_) { NetConnectedPinIterator *pin_iter = network->connectedPinIterator(net); while (pin_iter->hasNext()) { - const Pin *pin = pin_iter->next(); - pins.insert(pin); + const Pin *pin = pin_iter->next(); + pins.insert(pin); } delete pin_iter; } @@ -1870,15 +1902,15 @@ ExceptionThru::allPins(const Network *network) bool ExceptionThru::matches(const Pin *from_pin, - const Pin *to_pin, - const RiseFall *to_rf, - const Network *network) + const Pin *to_pin, + const RiseFall *to_rf, + const Network *network) { EdgePins edge_pins(from_pin, to_pin); - return ((pins_ && to_pin && pins_->hasKey(to_pin)) - || (edges_ && from_pin && to_pin && edges_->hasKey(edge_pins)) - || (nets_ && to_pin && nets_->hasKey(network->net(to_pin))) - || (insts_ && to_pin && insts_->hasKey(network->instance(to_pin)))) + return ((pins_ && to_pin && pins_->contains(to_pin)) + || (edges_ && from_pin && to_pin && edges_->contains(edge_pins)) + || (nets_ && to_pin && nets_->contains(network->net(to_pin))) + || (insts_ && to_pin && insts_->contains(network->instance(to_pin)))) && rf_->matches(to_rf); } @@ -1911,30 +1943,33 @@ bool ExceptionThru::equal(ExceptionThru *thru) const { // Edges_ are derived from pins_ so matching pins is sufficient. - return PinSet::equal(thru->pins_, pins_) - && NetSet::equal(thru->nets_, nets_) - && InstanceSet::equal(thru->insts_, insts_) + return ((thru->pins_ == nullptr && pins_ == nullptr) + || (thru->pins_ && pins_ && *thru->pins_ == *pins_)) + && ((thru->nets_ == nullptr && nets_ == nullptr) + || (thru->nets_ && nets_ && *thru->nets_ == *nets_)) + && ((thru->insts_ == nullptr && insts_ == nullptr) + || (thru->insts_ && insts_ && *thru->insts_ == *insts_)) && rf_ == thru->rf_; } int ExceptionThru::compare(ExceptionPt *pt2, - const Network *network) const + const Network *network) const { int priority_cmp = typePriority() - pt2->typePriority(); if (priority_cmp == 0) { - int pin_cmp = PinSet::compare(pins_, pt2->pins(), network); + int pin_cmp = sta::compare(pins_, pt2->pins(), network); if (pin_cmp == 0) { - int net_cmp = NetSet::compare(nets_, pt2->nets(), network); + int net_cmp = sta::compare(nets_, pt2->nets(), network); if (net_cmp == 0) { - int inst_cmp = InstanceSet::compare(insts_, pt2->instances(), network); - if (inst_cmp == 0) - return rf_->index() - pt2->transition()->index(); - else - return inst_cmp; + int inst_cmp = sta::compare(insts_, pt2->instances(), network); + if (inst_cmp == 0) + return rf_->index() - pt2->transition()->index(); + else + return inst_cmp; } else - return net_cmp; + return net_cmp; } else return pin_cmp; @@ -1998,9 +2033,9 @@ ExceptionThru::intersectsPts(ExceptionThru *thru, const Network *network) const { return thru->transition() == rf_ - && ((pins_ && PinSet::intersects(pins_, thru->pins(), network)) - || (nets_ && NetSet::intersects(nets_, thru->nets(), network)) - || (insts_ && InstanceSet::intersects(insts_, thru->instances(), network))); + && ((pins_ && intersects(pins_, thru->pins(), network)) + || (nets_ && intersects(nets_, thru->nets(), network)) + || (insts_ && intersects(insts_, thru->instances(), network))); } size_t @@ -2018,7 +2053,7 @@ ExceptionThru::objectCount() const void ExceptionThru::connectPinAfter(PinSet *drvrs, - Network *network) + Network *network) { // - Tricky to detect exactly what needs to be updated. In theory, // at most, only edges starting/ending (pin is leaf) or spanning @@ -2042,7 +2077,7 @@ ExceptionThru::connectPinAfter(PinSet *drvrs, for (const Pin *thru_pin : *pins_) { if (network->isHierarchical(thru_pin)) { PinSet *thru_pin_drvrs = network->drivers(thru_pin); - if (PinSet::intersects(drvrs, thru_pin_drvrs, network)) + if (intersects(drvrs, thru_pin_drvrs, network)) makePinEdges(thru_pin, network); } } @@ -2054,7 +2089,7 @@ ExceptionThru::connectPinAfter(PinSet *drvrs, while (inst_pin_iter->hasNext()) { Pin *inst_pin = inst_pin_iter->next(); PinSet *inst_pin_drvrs = network->drivers(inst_pin); - if (PinSet::intersects(drvrs, inst_pin_drvrs, network)) + if (intersects(drvrs, inst_pin_drvrs, network)) makePinEdges(inst_pin, network); } delete inst_pin_iter; @@ -2064,7 +2099,7 @@ ExceptionThru::connectPinAfter(PinSet *drvrs, if (nets_) { for (const Net *net : *nets_) { PinSet *net_drvrs = network->drivers(net); - if (PinSet::intersects(drvrs, net_drvrs, network)) + if (intersects(drvrs, net_drvrs, network)) makeNetEdges(net, network); } } @@ -2073,7 +2108,7 @@ ExceptionThru::connectPinAfter(PinSet *drvrs, void ExceptionThru::makePinEdges(const Pin *pin, - const Network *network) + const Network *network) { if (network->isHierarchical(pin)) makeHpinEdges(pin, network); @@ -2096,14 +2131,14 @@ ExceptionPtIterator::ExceptionPtIterator(const ExceptionPath *exception) : to_done_(false) { if (exception->thrus()) - thru_iter_.init(exception->thrus()); + thru_iter_ = exception->thrus()->begin(); } bool ExceptionPtIterator::hasNext() { return (!from_done_ && exception_->from()) - || thru_iter_.hasNext() + || (exception_->thrus() && thru_iter_ != exception_->thrus()->end()) || (!to_done_ && exception_->to()); } @@ -2115,8 +2150,9 @@ ExceptionPtIterator::next() from_done_ = true; return exception_->from(); } - else if (thru_iter_.hasNext()) - return thru_iter_.next(); + else if (exception_->thrus() + && thru_iter_ != exception_->thrus()->end()) + return *thru_iter_++; else { to_done_ = true; return exception_->to(); @@ -2126,7 +2162,7 @@ ExceptionPtIterator::next() //////////////////////////////////////////////////////////////// ExpandedExceptionVisitor::ExpandedExceptionVisitor(ExceptionPath *exception, - const Network *network) : + const Network *network) : exception_(exception), network_(network) { @@ -2182,8 +2218,8 @@ ExpandedExceptionVisitor::expandThrus(ExceptionFrom *expanded_from) void ExpandedExceptionVisitor::expandThru(ExceptionFrom *expanded_from, - size_t next_thru_idx, - ExceptionThruSeq *expanded_thrus) + size_t next_thru_idx, + ExceptionThruSeq *expanded_thrus) { ExceptionThruSeq *thrus = exception_->thrus(); if (next_thru_idx < thrus->size()) { @@ -2191,32 +2227,32 @@ ExpandedExceptionVisitor::expandThru(ExceptionFrom *expanded_from, const RiseFallBoth *rf = thru->transition(); if (thru->pins()) { for (const Pin *pin : *thru->pins()) { - PinSet pins(network_); - pins.insert(pin); - ExceptionThru expanded_thru(&pins, nullptr, nullptr, rf, false, network_); - expanded_thrus->push_back(&expanded_thru); - expandThru(expanded_from, next_thru_idx + 1, expanded_thrus); - expanded_thrus->pop_back(); + PinSet pins(network_); + pins.insert(pin); + ExceptionThru expanded_thru(&pins, nullptr, nullptr, rf, false, network_); + expanded_thrus->push_back(&expanded_thru); + expandThru(expanded_from, next_thru_idx + 1, expanded_thrus); + expanded_thrus->pop_back(); } } if (thru->nets()) { for (const Net *net : *thru->nets()) { - NetSet nets(network_); - nets.insert(net); - ExceptionThru expanded_thru(nullptr, &nets, nullptr, rf, false, network_); - expanded_thrus->push_back(&expanded_thru); - expandThru(expanded_from, next_thru_idx + 1, expanded_thrus); - expanded_thrus->pop_back(); + NetSet nets(network_); + nets.insert(net); + ExceptionThru expanded_thru(nullptr, &nets, nullptr, rf, false, network_); + expanded_thrus->push_back(&expanded_thru); + expandThru(expanded_from, next_thru_idx + 1, expanded_thrus); + expanded_thrus->pop_back(); } } if (thru->instances()) { for (const Instance *inst : *thru->instances()) { - InstanceSet insts(network_); - insts.insert(inst); - ExceptionThru expanded_thru(nullptr, nullptr, &insts, rf, false, network_); - expanded_thrus->push_back(&expanded_thru); - expandThru(expanded_from, next_thru_idx + 1, expanded_thrus); - expanded_thrus->pop_back(); + InstanceSet insts(network_); + insts.insert(inst); + ExceptionThru expanded_thru(nullptr, nullptr, &insts, rf, false, network_); + expanded_thrus->push_back(&expanded_thru); + expandThru(expanded_from, next_thru_idx + 1, expanded_thrus); + expanded_thrus->pop_back(); } } } @@ -2227,7 +2263,7 @@ ExpandedExceptionVisitor::expandThru(ExceptionFrom *expanded_from, void ExpandedExceptionVisitor::expandTo(ExceptionFrom *expanded_from, - ExceptionThruSeq *expanded_thrus) + ExceptionThruSeq *expanded_thrus) { ExceptionTo *to = exception_->to(); if (to) { @@ -2265,8 +2301,8 @@ ExpandedExceptionVisitor::expandTo(ExceptionFrom *expanded_from, //////////////////////////////////////////////////////////////// ExceptionState::ExceptionState(ExceptionPath *exception, - ExceptionThru *next_thru, - int index) : + ExceptionThru *next_thru, + int index) : exception_(exception), next_thru_(next_thru), next_state_(nullptr), @@ -2282,10 +2318,10 @@ ExceptionState::setNextState(ExceptionState *next_state) bool ExceptionState::matchesNextThru(const Pin *from_pin, - const Pin *to_pin, - const RiseFall *to_rf, - const MinMax *min_max, - const Network *network) const + const Pin *to_pin, + const RiseFall *to_rf, + const MinMax *min_max, + const Network *network) const { // Don't advance the state if the exception is complete (no next_thru_). return next_thru_ @@ -2306,22 +2342,33 @@ ExceptionState::hash() const return hashSum(exception_->hash(), index_); } -bool -exceptionStateLess(const ExceptionState *state1, - const ExceptionState *state2) +int +exceptionStateCmp(const ExceptionState *state1, + const ExceptionState *state2) { - const ExceptionPath *except1 = state1->exception(); - const ExceptionPath *except2 = state2->exception(); - return except1->id() < except2->id() - || (except1 == except2 - && state1->index() < state2->index()); + size_t id1 = state1->exception()->id(); + size_t id2 = state2->exception()->id(); + if (id1 < id2) + return -1; + else if (id1 > id2) + return 1; + else { + size_t state_index1 = state1->index(); + size_t state_index2 = state2->index(); + if (state_index1 < state_index2) + return -1; + else if (state_index1 > state_index2) + return 1; + else + return 0; + } } bool ExceptionStateLess::operator()(const ExceptionState *state1, const ExceptionState *state2) const { - return exceptionStateLess(state1, state2); + return exceptionStateCmp(state1, state2) < 0; } //////////////////////////////////////////////////////////////// @@ -2345,7 +2392,7 @@ ExceptionPathLess::operator()(const ExceptionPath *except1, ExceptionPt *pt2 = pt_iter2.next(); int cmp = pt1->compare(pt2, network_); if (cmp != 0) - return cmp < 0; + return cmp < 0; } // Lesser has fewer exception pts. return !pt_iter1.hasNext() && pt_iter2.hasNext(); @@ -2360,18 +2407,18 @@ class InsertPinPairsThru : public HierPinThruVisitor { public: InsertPinPairsThru(PinPairSet *pairs, - const Network *network); + const Network *network); protected: virtual void visit(const Pin *drvr, - const Pin *load); + const Pin *load); PinPairSet *pairs_; const Network *network_; }; InsertPinPairsThru::InsertPinPairsThru(PinPairSet *pairs, - const Network *network) : + const Network *network) : HierPinThruVisitor(), pairs_(pairs), network_(network) @@ -2380,7 +2427,7 @@ InsertPinPairsThru::InsertPinPairsThru(PinPairSet *pairs, void InsertPinPairsThru::visit(const Pin *drvr, - const Pin *load) + const Pin *load) { PinPair pair(drvr, load); pairs_->insert(pair); @@ -2388,8 +2435,8 @@ InsertPinPairsThru::visit(const Pin *drvr, static void insertPinPairsThruHierPin(const Pin *hpin, - const Network *network, - PinPairSet *pairs) + const Network *network, + PinPairSet *pairs) { InsertPinPairsThru visitor(pairs, network); visitDrvrLoadsThruHierPin(hpin, network, &visitor); @@ -2397,8 +2444,8 @@ insertPinPairsThruHierPin(const Pin *hpin, static void insertPinPairsThruNet(const Net *net, - const Network *network, - PinPairSet *pairs) + const Network *network, + PinPairSet *pairs) { InsertPinPairsThru visitor(pairs, network); visitDrvrLoadsThruNet(net, network, &visitor); @@ -2408,7 +2455,7 @@ class DeletePinPairsThru : public HierPinThruVisitor { public: DeletePinPairsThru(PinPairSet *pairs, - const Network *network); + const Network *network); protected: virtual void visit(const Pin *drvr, @@ -2419,7 +2466,7 @@ protected: }; DeletePinPairsThru::DeletePinPairsThru(PinPairSet *pairs, - const Network *network) : + const Network *network) : HierPinThruVisitor(), pairs_(pairs), network_(network) @@ -2428,7 +2475,7 @@ DeletePinPairsThru::DeletePinPairsThru(PinPairSet *pairs, void DeletePinPairsThru::visit(const Pin *drvr, - const Pin *load) + const Pin *load) { PinPair pair(drvr, load); pairs_->erase(pair); @@ -2436,8 +2483,8 @@ DeletePinPairsThru::visit(const Pin *drvr, static void deletePinPairsThruHierPin(const Pin *hpin, - const Network *network, - PinPairSet *pairs) + const Network *network, + PinPairSet *pairs) { DeletePinPairsThru visitor(pairs, network); visitDrvrLoadsThruHierPin(hpin, network, &visitor); diff --git a/sdc/InputDrive.cc b/sdc/InputDrive.cc index 845bb5cf..2c647562 100644 --- a/sdc/InputDrive.cc +++ b/sdc/InputDrive.cc @@ -46,25 +46,25 @@ InputDrive::~InputDrive() void InputDrive::setSlew(const RiseFallBoth *rf, - const MinMaxAll *min_max, - float slew) + const MinMaxAll *min_max, + float slew) { slews_.setValue(rf, min_max, slew); } void InputDrive::setDriveResistance(const RiseFallBoth *rf, - const MinMaxAll *min_max, - float res) + const MinMaxAll *min_max, + float res) { drive_resistances_.setValue(rf, min_max, res); } void InputDrive::driveResistance(const RiseFall *rf, - const MinMax *min_max, - float &res, - bool &exists) const + const MinMax *min_max, + float &res, + bool &exists) const { drive_resistances_.value(rf, min_max, res, exists); } @@ -88,27 +88,27 @@ InputDrive::driveResistanceMinMaxEqual(const RiseFall *rf) const void InputDrive::setDriveCell(const LibertyLibrary *library, - const LibertyCell *cell, - const LibertyPort *from_port, - float *from_slews, - const LibertyPort *to_port, - const RiseFallBoth *rf, - const MinMaxAll *min_max) + const LibertyCell *cell, + const LibertyPort *from_port, + float *from_slews, + const LibertyPort *to_port, + const RiseFallBoth *rf, + const MinMaxAll *min_max) { for (auto rf_index : rf->rangeIndex()) { for (auto mm_index : min_max->rangeIndex()) { InputDriveCell *drive = drive_cells_[rf_index][mm_index]; if (drive) { - drive->setLibrary(library); - drive->setCell(cell); - drive->setFromPort(from_port); - drive->setFromSlews(from_slews); - drive->setToPort(to_port); + drive->setLibrary(library); + drive->setCell(cell); + drive->setFromPort(from_port); + drive->setFromSlews(from_slews); + drive->setToPort(to_port); } else { - drive = new InputDriveCell(library, cell, from_port, - from_slews, to_port); - drive_cells_[rf_index][mm_index] = drive; + drive = new InputDriveCell(library, cell, from_port, + from_slews, to_port); + drive_cells_[rf_index][mm_index] = drive; } } } @@ -116,12 +116,12 @@ InputDrive::setDriveCell(const LibertyLibrary *library, void InputDrive::driveCell(const RiseFall *rf, - const MinMax *min_max, + const MinMax *min_max, // Return values. - const LibertyCell *&cell, - const LibertyPort *&from_port, - float *&from_slews, - const LibertyPort *&to_port) const + const LibertyCell *&cell, + const LibertyPort *&from_port, + float *&from_slews, + const LibertyPort *&to_port) const { InputDriveCell *drive = drive_cells_[rf->index()][min_max->index()]; if (drive) { @@ -140,14 +140,14 @@ InputDrive::driveCell(const RiseFall *rf, InputDriveCell * InputDrive::driveCell(const RiseFall *rf, - const MinMax *min_max) const + const MinMax *min_max) const { return drive_cells_[rf->index()][min_max->index()]; } bool InputDrive::hasDriveCell(const RiseFall *rf, - const MinMax *min_max) const + const MinMax *min_max) const { return drive_cells_[rf->index()][min_max->index()] != nullptr; } @@ -170,9 +170,9 @@ InputDrive::driveCellsEqual() const void InputDrive::slew(const RiseFall *rf, - const MinMax *min_max, - float &slew, - bool &exists) const + const MinMax *min_max, + float &slew, + bool &exists) const { slews_.value(rf, min_max, slew, exists); } @@ -180,10 +180,10 @@ InputDrive::slew(const RiseFall *rf, //////////////////////////////////////////////////////////////// InputDriveCell::InputDriveCell(const LibertyLibrary *library, - const LibertyCell *cell, - const LibertyPort *from_port, - float *from_slews, - const LibertyPort *to_port) : + const LibertyCell *cell, + const LibertyPort *from_port, + float *from_slews, + const LibertyPort *to_port) : library_(library), cell_(cell), from_port_(from_port), diff --git a/sdc/PinPair.cc b/sdc/PinPair.cc index 6178a9dd..e88801da 100644 --- a/sdc/PinPair.cc +++ b/sdc/PinPair.cc @@ -35,7 +35,7 @@ PinPairLess::PinPairLess(const Network *network) : bool PinPairLess::operator()(const PinPair &pair1, - const PinPair &pair2) const + const PinPair &pair2) const { const Pin *pair1_pin1 = pair1.first; const Pin *pair1_pin2 = pair1.second; @@ -52,7 +52,7 @@ PinPairLess::operator()(const PinPair &pair1, bool PinPairEqual::operator()(const PinPair &pair1, - const PinPair &pair2) const + const PinPair &pair2) const { return pair1.first == pair2.first && pair1.second == pair2.second; @@ -73,7 +73,7 @@ PinPairHash::operator()(const PinPair &pair) const } PinPairSet::PinPairSet(const Network *network) : - Set(PinPairLess(network)) + std::set(PinPairLess(network)) { } diff --git a/sdc/PortDelay.cc b/sdc/PortDelay.cc index e2381216..073c8e26 100644 --- a/sdc/PortDelay.cc +++ b/sdc/PortDelay.cc @@ -30,7 +30,7 @@ namespace sta { PortDelay::PortDelay(const Pin *pin, - const ClockEdge *clk_edge, + const ClockEdge *clk_edge, const Network *network) : pin_(pin), clk_edge_(clk_edge), @@ -92,9 +92,9 @@ PortDelay::refTransition() const } InputDelay::InputDelay(const Pin *pin, - const ClockEdge *clk_edge, - int index, - const Network *network) : + const ClockEdge *clk_edge, + int index, + const Network *network) : PortDelay(pin, clk_edge, network), index_(index) { @@ -102,8 +102,8 @@ InputDelay::InputDelay(const Pin *pin, } OutputDelay::OutputDelay(const Pin *pin, - const ClockEdge *clk_edge, - const Network *network) : + const ClockEdge *clk_edge, + const Network *network) : PortDelay(pin, clk_edge, network) { if (network) diff --git a/sdc/PortExtCap.cc b/sdc/PortExtCap.cc index 5dfd2180..48287fec 100644 --- a/sdc/PortExtCap.cc +++ b/sdc/PortExtCap.cc @@ -26,60 +26,66 @@ namespace sta { -PortExtCap::PortExtCap(const Port *port) : - port_(port) +PortExtCap::PortExtCap() : + port_(nullptr) { } void PortExtCap::pinCap(const RiseFall *rf, - const MinMax *min_max, - // Return values. - float &cap, - bool &exists) + const MinMax *min_max, + // Return values. + float &cap, + bool &exists) const { pin_cap_.value(rf, min_max, cap, exists); } void -PortExtCap::setPinCap(float cap, - const RiseFall *rf, - const MinMax *min_max) +PortExtCap::setPinCap(const Port *port, + float cap, + const RiseFall *rf, + const MinMax *min_max) { + port_ = port; pin_cap_.setValue(rf, min_max, cap); } void PortExtCap::wireCap(const RiseFall *rf, - const MinMax *min_max, - // Return values. - float &cap, - bool &exists) + const MinMax *min_max, + // Return values. + float &cap, + bool &exists) const { wire_cap_.value(rf, min_max, cap, exists); } void -PortExtCap::setWireCap(float cap, - const RiseFall *rf, - const MinMax *min_max) +PortExtCap::setWireCap(const Port *port, + float cap, + const RiseFall *rf, + const MinMax *min_max) { + port_ = port; wire_cap_.setValue(rf, min_max, cap); } void -PortExtCap::setFanout(int fanout, - const MinMax *min_max) +PortExtCap::setFanout(const Port *port, + int fanout, + const MinMax *min_max) { + port_ = port; fanout_.setValue(min_max, fanout); } void PortExtCap::fanout(const MinMax *min_max, - // Return values. - int &fanout, - bool &exists) + // Return values. + int &fanout, + bool &exists) const { fanout_.value(min_max, fanout, exists); } diff --git a/sdc/Sdc.cc b/sdc/Sdc.cc index daca9186..0c11320a 100644 --- a/sdc/Sdc.cc +++ b/sdc/Sdc.cc @@ -25,7 +25,9 @@ #include "Sdc.hh" #include +#include +#include "ContainerHelpers.hh" #include "Stats.hh" #include "Debug.hh" #include "Mutex.hh" @@ -55,7 +57,7 @@ #include "DeratingFactors.hh" #include "HpinDrvrLoad.hh" #include "search/Levelize.hh" -#include "Corner.hh" +#include "Scene.hh" #include "Graph.hh" namespace sta { @@ -64,25 +66,25 @@ using std::swap; bool ClockPairLess::operator()(const ClockPair &pair1, - const ClockPair &pair2) const + const ClockPair &pair2) const { - int first1 = pair1.first->index(); - int second1 = pair1.second->index(); + const auto& [clk1_1, clk2_1] = pair1; + int first1 = clk1_1->index(); + int second1 = clk2_1->index(); if (first1 > second1) std::swap(first1, second1); - int first2 = pair2.first->index(); - int second2 = pair2.second->index(); + const auto& [clk1_2, clk2_2] = pair2; + int first2 = clk1_2->index(); + int second2 = clk2_2->index(); if (first2 > second2) std::swap(first2, second2); return (first1 < first2) || (first1 == first2 - && second1 < second2); + && second1 < second2); } -//////////////////////////////////////////////////////////////// - -typedef Vector ClockPairSeq; -typedef Set PvtSet; +using ClockPairSeq = std::vector; +using PvtSet = std::set; static ExceptionThruSeq * clone(ExceptionThruSeq *thrus, @@ -90,15 +92,18 @@ clone(ExceptionThruSeq *thrus, //////////////////////////////////////////////////////////////// -Sdc::Sdc(StaState *sta) : +Sdc::Sdc(Mode *mode, + StaState *sta) : StaState(sta), + mode_(mode), derating_factors_(nullptr), clk_index_(0), - clock_pin_map_(PinIdHash(network_)), - clock_leaf_pin_map_(PinIdHash(network_)), + clock_pin_map_(10, PinIdHash(network_)), + clock_leaf_pin_map_(10, PinIdHash(network_)), clk_hpin_disables_(network_), propagated_clk_pins_(network_), clk_latencies_(network_), + edge_clk_latency_map_(network_), clk_insertions_(network_), clk_sense_map_(network_), clk_gating_check_(nullptr), @@ -114,6 +119,10 @@ Sdc::Sdc(StaState *sta) : output_delay_ref_pin_map_(PinIdLess(network_)), output_delay_leaf_pin_map_(PinIdLess(network_)), + port_ext_cap_map_(network_), + net_wire_cap_map_(network_), + drvr_pin_wire_cap_map_(network_), + disabled_pins_(network_), disabled_ports_(network_), disabled_wire_edges_(network_), @@ -125,12 +134,10 @@ Sdc::Sdc(StaState *sta) : path_delay_internal_from_(network_), path_delay_internal_from_break_(network_), path_delay_internal_to_(network_), - path_delay_internal_to_break_(network_) + path_delay_internal_to_break_(network_), + filter_(nullptr) { - sdc_ = this; initVariables(); - if (corners_) - makeCornersAfter(corners_); setWireload(nullptr, MinMaxAll::all()); setWireloadSelection(nullptr, MinMaxAll::all()); setOperatingConditions(nullptr, MinMaxAll::all()); @@ -157,7 +164,6 @@ Sdc::~Sdc() void Sdc::clear() { - removeLibertyAnnotations(); deleteConstraints(); propagated_clk_pins_.clear(); clocks_.clear(); @@ -165,7 +171,7 @@ Sdc::clear() clock_pin_map_.clear(); clock_leaf_pin_map_.clear(); clk_latencies_.clear(); - edge_clk_latency_.clear(); + edge_clk_latency_map_.clear(); clk_insertions_.clear(); pin_clk_uncertainty_map_.clear(); @@ -246,53 +252,53 @@ Sdc::initVariables() void Sdc::deleteConstraints() { - clocks_.deleteContents(); + deleteContents(clocks_);; delete default_arrival_clk_; - clock_pin_map_.deleteContents(); - clock_leaf_pin_map_.deleteContents(); - clk_latencies_.deleteContents(); - clk_insertions_.deleteContents(); + deleteContents(clock_pin_map_); + deleteContents(clock_leaf_pin_map_); + deleteContents(clk_latencies_); + deleteContents(clk_insertions_); - clk_groups_name_map_.deleteContents(); + deleteContents(clk_groups_name_map_); clearClkGroupExclusions(); - pin_clk_uncertainty_map_.deleteContents(); - inter_clk_uncertainties_.deleteContents(); + deleteContents(pin_clk_uncertainty_map_); + deleteContents(inter_clk_uncertainties_); delete clk_gating_check_; clk_gating_check_ = nullptr; - clk_gating_check_map_.deleteContents(); - inst_clk_gating_check_map_.deleteContents(); - pin_clk_gating_check_map_.deleteContents(); - input_drive_map_.deleteContents(); - disabled_cell_ports_.deleteContents(); - disabled_inst_ports_.deleteContents(); - pin_min_pulse_width_map_.deleteContentsClear(); - inst_min_pulse_width_map_.deleteContentsClear(); - clk_min_pulse_width_map_.deleteContentsClear(); + deleteContents(clk_gating_check_map_); + deleteContents(inst_clk_gating_check_map_); + deleteContents(pin_clk_gating_check_map_); + deleteContents(input_drive_map_); + deleteContents(disabled_cell_ports_); + deleteContents(disabled_inst_ports_); + deleteContents(pin_min_pulse_width_map_); + deleteContents(inst_min_pulse_width_map_); + deleteContents(clk_min_pulse_width_map_); for (auto [pin, checks] : data_checks_from_map_) { - checks->deleteContents(); + deleteContents(*checks); delete checks; } - for (auto [pin, checks] : data_checks_to_map_) - delete checks; + deleteContents(data_checks_to_map_); - input_delays_.deleteContents(); - input_delay_pin_map_.deleteContents(); - input_delay_leaf_pin_map_.deleteContents(); - input_delay_ref_pin_map_.deleteContents(); - input_delay_internal_pin_map_.deleteContents(); + deleteContents(input_delays_); + deleteContents(input_delay_pin_map_); + deleteContents(input_delay_leaf_pin_map_); + deleteContents(input_delay_ref_pin_map_); + deleteContents(input_delay_internal_pin_map_); - output_delays_.deleteContents(); - output_delay_pin_map_.deleteContents(); - output_delay_ref_pin_map_.deleteContents(); - output_delay_leaf_pin_map_.deleteContents(); + deleteContents(output_delays_); + deleteContents(output_delay_pin_map_); + deleteContents(output_delay_ref_pin_map_); + deleteContents(output_delay_leaf_pin_map_); - clk_hpin_disables_.deleteContentsClear(); + deleteContents(clk_hpin_disables_); clk_hpin_disables_valid_ = false; clearCycleAcctings(); deleteExceptions(); + deleteFilter(); clearGroupPathMap(); deleteDeratingFactors(); @@ -301,66 +307,30 @@ Sdc::deleteConstraints() clk_sense_map_.clear(); for (int mm_index : MinMax::rangeIndex()) - instance_pvt_maps_[mm_index].deleteContentsClear(); + deleteContents(instance_pvt_maps_[mm_index]); +} + +void +Sdc::searchPreamble() +{ + ensureClkHpinDisables(); + ensureClkGroupExclusions(); } void Sdc::removeNetLoadCaps() { - if (!net_wire_cap_maps_.empty()) { - for (int corner_index = 0; corner_index < corners_->count(); corner_index++) { - net_wire_cap_maps_[corner_index].clear(); - drvr_pin_wire_cap_maps_[corner_index].clear(); - port_ext_cap_maps_[corner_index].deleteContentsClear(); - } - } -} - -void -Sdc::removeLibertyAnnotations() -{ - for (auto [cell, disable] : disabled_cell_ports_) { - if (disable->all()) - cell->setIsDisabledConstraint(false); - - if (disable->from()) { - for (LibertyPort *from : *disable->from()) - from->setIsDisabledConstraint(false); - } - - if (disable->to()) { - for (LibertyPort *to : *disable->to()) - to->setIsDisabledConstraint(false); - } - - if (disable->timingArcSets()) { - for (TimingArcSet *arc_set : *disable->timingArcSets()) - arc_set->setIsDisabledConstraint(false); - } - - - if (disable->fromTo()) { - for (const LibertyPortPair &pair : *disable->fromTo()) { - const LibertyPort *from = pair.first; - const LibertyPort *to = pair.second; - for (TimingArcSet *arc_set : cell->timingArcSets(from, to)) - arc_set->setIsDisabledConstraint(false); - } - } - } - - for (LibertyPort *port : disabled_lib_ports_) - port->setIsDisabledConstraint(false); + net_wire_cap_map_.clear(); + drvr_pin_wire_cap_map_.clear(); + port_ext_cap_map_.clear(); } void Sdc::deleteNetBefore(const Net *net) { - for (int corner_index = 0; corner_index < corners_->count(); corner_index++) { - net_wire_cap_maps_[corner_index].erase(net); - for (const Pin *pin : *network_->drivers(net)) - drvr_pin_wire_cap_maps_[corner_index].erase(pin); - } + net_wire_cap_map_.erase(net); + for (const Pin *pin : *network_->drivers(net)) + drvr_pin_wire_cap_map_.erase(pin); } // see Sdc::isConstrained @@ -383,82 +353,73 @@ Sdc::deleteInstanceBefore(const Instance *inst) } void -Sdc::makeCornersBefore() +Sdc::makeSceneBefore() { removeNetLoadCaps(); } -void -Sdc::makeCornersAfter(Corners *corners) -{ - corners_ = corners; - port_ext_cap_maps_.resize(corners_->count(), PortExtCapMap(PortIdLess(network_))); - net_wire_cap_maps_.resize(corners_->count(), NetWireCapMap(NetIdLess(network_))); - drvr_pin_wire_cap_maps_.resize(corners_->count(), PinWireCapMap(PinIdLess(network_))); -} - //////////////////////////////////////////////////////////////// bool Sdc::isConstrained(const Pin *pin) const { Port *port = network_->isTopLevelPort(pin) ? network_->port(pin) : nullptr; - return clock_pin_map_.hasKey(pin) - || propagated_clk_pins_.hasKey(pin) + return clock_pin_map_.contains(pin) + || propagated_clk_pins_.contains(pin) || hasClockLatency(pin) || hasClockInsertion(pin) - || pin_clk_uncertainty_map_.hasKey(pin) - || pin_clk_gating_check_map_.hasKey(pin) - || data_checks_from_map_.hasKey(pin) - || data_checks_to_map_.hasKey(pin) - || input_delay_pin_map_.hasKey(pin) - || output_delay_pin_map_.hasKey(pin) - || pin_cap_limit_map_.hasKey(pin) - || disabled_pins_.hasKey(pin) - || disabled_ports_.hasKey(port) - || disabled_clk_gating_checks_pin_.hasKey(pin) - || first_from_pin_exceptions_.hasKey(pin) - || first_thru_pin_exceptions_.hasKey(pin) - || first_to_pin_exceptions_.hasKey(pin) - || input_drive_map_.hasKey(port) - || logic_value_map_.hasKey(pin) - || case_value_map_.hasKey(pin) - || pin_latch_borrow_limit_map_.hasKey(pin) - || pin_min_pulse_width_map_.hasKey(pin) - || (port && (port_slew_limit_map_.hasKey(port) - || port_cap_limit_map_.hasKey(port) - || port_fanout_limit_map_.hasKey(port) + || pin_clk_uncertainty_map_.contains(pin) + || pin_clk_gating_check_map_.contains(pin) + || data_checks_from_map_.contains(pin) + || data_checks_to_map_.contains(pin) + || input_delay_pin_map_.contains(pin) + || output_delay_pin_map_.contains(pin) + || pin_cap_limit_map_.contains(pin) + || disabled_pins_.contains(pin) + || disabled_ports_.contains(port) + || disabled_clk_gating_checks_pin_.contains(pin) + || first_from_pin_exceptions_.contains(pin) + || first_thru_pin_exceptions_.contains(pin) + || first_to_pin_exceptions_.contains(pin) + || input_drive_map_.contains(port) + || logic_value_map_.contains(pin) + || case_value_map_.contains(pin) + || pin_latch_borrow_limit_map_.contains(pin) + || pin_min_pulse_width_map_.contains(pin) + || (port && (port_slew_limit_map_.contains(port) + || port_cap_limit_map_.contains(port) + || port_fanout_limit_map_.contains(port) || hasPortExtCap(port))); } bool Sdc::isConstrained(const Instance *inst) const { - return instance_pvt_maps_[MinMax::minIndex()].hasKey(inst) - || instance_pvt_maps_[MinMax::maxIndex()].hasKey(inst) - || inst_derating_factors_.hasKey(inst) - || inst_clk_gating_check_map_.hasKey(inst) - || disabled_inst_ports_.hasKey(inst) - || first_from_inst_exceptions_.hasKey(inst) - || first_thru_inst_exceptions_.hasKey(inst) - || first_to_inst_exceptions_.hasKey(inst) - || inst_latch_borrow_limit_map_.hasKey(inst) - || inst_min_pulse_width_map_.hasKey(inst); + return instance_pvt_maps_[MinMax::minIndex()].contains(inst) + || instance_pvt_maps_[MinMax::maxIndex()].contains(inst) + || inst_derating_factors_.contains(inst) + || inst_clk_gating_check_map_.contains(inst) + || disabled_inst_ports_.contains(inst) + || first_from_inst_exceptions_.contains(inst) + || first_thru_inst_exceptions_.contains(inst) + || first_to_inst_exceptions_.contains(inst) + || inst_latch_borrow_limit_map_.contains(inst) + || inst_min_pulse_width_map_.contains(inst); } bool Sdc::isConstrained(const Net *net) const { - return net_derating_factors_.hasKey(net) + return net_derating_factors_.contains(net) || hasNetWireCap(net) - || net_res_map_.hasKey(net) - || first_thru_net_exceptions_.hasKey(net); + || net_res_map_.contains(net) + || first_thru_net_exceptions_.contains(net); } //////////////////////////////////////////////////////////////// PortSeq -Sdc::allInputs(bool no_clks) +Sdc::allInputs(bool no_clks) const { PortSeq ports; Instance *top_inst = network_->topInstance(); @@ -476,7 +437,7 @@ Sdc::allInputs(bool no_clks) } PortSeq -Sdc::allOutputs() +Sdc::allOutputs() const { PortSeq ports; Instance *top_inst = network_->topInstance(); @@ -494,7 +455,7 @@ Sdc::allOutputs() void Sdc::portMembers(const Port *port, - PortSeq &ports) + PortSeq &ports) const { if (network_->isBus(port)) { PortMemberIterator *member_iter = network_->memberIterator(port); @@ -516,7 +477,7 @@ Sdc::setAnalysisType(AnalysisType analysis_type) void Sdc::setOperatingConditions(OperatingConditions *op_cond, - const MinMaxAll *min_max) + const MinMaxAll *min_max) { for (auto mm_index : min_max->rangeIndex()) operating_conditions_[mm_index] = op_cond; @@ -524,7 +485,7 @@ Sdc::setOperatingConditions(OperatingConditions *op_cond, void Sdc::setOperatingConditions(OperatingConditions *op_cond, - const MinMax *min_max) + const MinMax *min_max) { int mm_index = min_max->index(); operating_conditions_[mm_index] = op_cond; @@ -539,16 +500,16 @@ Sdc::operatingConditions(const MinMax *min_max) const const Pvt * Sdc::pvt(const Instance *inst, - const MinMax *min_max) const + const MinMax *min_max) const { const InstancePvtMap &pvt_map = instance_pvt_maps_[min_max->index()]; - return pvt_map.findKey(inst); + return findKey(pvt_map, inst); } void Sdc::setPvt(const Instance *inst, const MinMaxAll *min_max, - const Pvt &pvt) + const Pvt &pvt) { for (auto mm_index : min_max->rangeIndex()) { InstancePvtMap &pvt_map = instance_pvt_maps_[mm_index]; @@ -560,7 +521,7 @@ void Sdc::voltage(const MinMax *min_max, // Return values. float &voltage, - bool &exists) + bool &exists) const { voltages_.value(min_max, voltage, exists); } @@ -570,11 +531,14 @@ Sdc::voltage(const Net *net, const MinMax *min_max, // Return values. float &voltage, - bool &exists) + bool &exists) const { exists = false; - if (net_voltage_map_.hasKey(net)) - net_voltage_map_[net].value(min_max, voltage, exists); + auto itr = net_voltage_map_.find(net); + if (itr != net_voltage_map_.end()) { + const MinMaxFloatValues &values = itr->second; + values.value(min_max, voltage, exists); + } } void @@ -596,10 +560,10 @@ Sdc::setVoltage(const Net *net, void Sdc::setTimingDerate(TimingDerateType type, - PathClkOrData clk_data, - const RiseFallBoth *rf, - const EarlyLate *early_late, - float derate) + PathClkOrData clk_data, + const RiseFallBoth *rf, + const EarlyLate *early_late, + float derate) { if (derating_factors_ == nullptr) derating_factors_ = new DeratingFactorsGlobal; @@ -608,12 +572,12 @@ Sdc::setTimingDerate(TimingDerateType type, void Sdc::setTimingDerate(const Net *net, - PathClkOrData clk_data, - const RiseFallBoth *rf, - const EarlyLate *early_late, - float derate) + PathClkOrData clk_data, + const RiseFallBoth *rf, + const EarlyLate *early_late, + float derate) { - DeratingFactorsNet *factors = net_derating_factors_.findKey(net); + DeratingFactorsNet *factors = findKey(net_derating_factors_, net); if (factors == nullptr) { factors = new DeratingFactorsNet; net_derating_factors_[net] = factors; @@ -623,13 +587,13 @@ Sdc::setTimingDerate(const Net *net, void Sdc::setTimingDerate(const Instance *inst, - TimingDerateCellType type, - PathClkOrData clk_data, - const RiseFallBoth *rf, - const EarlyLate *early_late, - float derate) + TimingDerateCellType type, + PathClkOrData clk_data, + const RiseFallBoth *rf, + const EarlyLate *early_late, + float derate) { - DeratingFactorsCell *factors = inst_derating_factors_.findKey(inst); + DeratingFactorsCell *factors = findKey(inst_derating_factors_, inst); if (factors == nullptr) { factors = new DeratingFactorsCell; inst_derating_factors_[inst] = factors; @@ -639,13 +603,13 @@ Sdc::setTimingDerate(const Instance *inst, void Sdc::setTimingDerate(const LibertyCell *cell, - TimingDerateCellType type, - PathClkOrData clk_data, - const RiseFallBoth *rf, - const EarlyLate *early_late, - float derate) + TimingDerateCellType type, + PathClkOrData clk_data, + const RiseFallBoth *rf, + const EarlyLate *early_late, + float derate) { - DeratingFactorsCell *factors = cell_derating_factors_.findKey(cell); + DeratingFactorsCell *factors = findKey(cell_derating_factors_, cell); if (factors == nullptr) { factors = new DeratingFactorsCell; cell_derating_factors_[cell] = factors; @@ -655,13 +619,13 @@ Sdc::setTimingDerate(const LibertyCell *cell, float Sdc::timingDerateInstance(const Pin *pin, - TimingDerateCellType type, - PathClkOrData clk_data, - const RiseFall *rf, - const EarlyLate *early_late) const + TimingDerateCellType type, + PathClkOrData clk_data, + const RiseFall *rf, + const EarlyLate *early_late) const { const Instance *inst = network_->instance(pin); - DeratingFactorsCell *factors = inst_derating_factors_.findKey(inst); + DeratingFactorsCell *factors = findKey(inst_derating_factors_, inst); if (factors) { float factor; bool exists; @@ -672,7 +636,7 @@ Sdc::timingDerateInstance(const Pin *pin, const LibertyCell *cell = network_->libertyCell(inst); if (cell) { - DeratingFactorsCell *factors = cell_derating_factors_.findKey(cell); + DeratingFactorsCell *factors = findKey(cell_derating_factors_, cell); float factor; bool exists; if (factors) { @@ -694,12 +658,12 @@ Sdc::timingDerateInstance(const Pin *pin, float Sdc::timingDerateNet(const Pin *pin, - PathClkOrData clk_data, - const RiseFall *rf, - const EarlyLate *early_late) const + PathClkOrData clk_data, + const RiseFall *rf, + const EarlyLate *early_late) const { const Net *net = network_->net(pin); - DeratingFactorsNet *factors = net_derating_factors_.findKey(net); + DeratingFactorsNet *factors = findKey(net_derating_factors_, net); if (factors) { float factor; bool exists; @@ -712,7 +676,7 @@ Sdc::timingDerateNet(const Pin *pin, float factor; bool exists; derating_factors_->factor(TimingDerateType::net_delay, clk_data, rf, - early_late, factor, exists); + early_late, factor, exists); if (exists) return factor; } @@ -738,9 +702,9 @@ Sdc::swapDeratingFactors(Sdc *sdc1, void Sdc::deleteDeratingFactors() { - net_derating_factors_.deleteContents(); - inst_derating_factors_.deleteContents(); - cell_derating_factors_.deleteContents(); + deleteContents(net_derating_factors_); + deleteContents(inst_derating_factors_); + deleteContents(cell_derating_factors_); delete derating_factors_; derating_factors_ = nullptr; @@ -750,32 +714,32 @@ Sdc::deleteDeratingFactors() void Sdc::setDriveCell(const LibertyLibrary *library, - const LibertyCell *cell, - const Port *port, - const LibertyPort *from_port, - float *from_slews, - const LibertyPort *to_port, - const RiseFallBoth *rf, - const MinMaxAll *min_max) + const LibertyCell *cell, + const Port *port, + const LibertyPort *from_port, + float *from_slews, + const LibertyPort *to_port, + const RiseFallBoth *rf, + const MinMaxAll *min_max) { ensureInputDrive(port)->setDriveCell(library, cell, from_port, from_slews, - to_port, rf, min_max); + to_port, rf, min_max); } void Sdc::setInputSlew(const Port *port, - const RiseFallBoth *rf, - const MinMaxAll *min_max, - float slew) + const RiseFallBoth *rf, + const MinMaxAll *min_max, + float slew) { ensureInputDrive(port)->setSlew(rf, min_max, slew); } void Sdc::setDriveResistance(const Port *port, - const RiseFallBoth *rf, - const MinMaxAll *min_max, - float res) + const RiseFallBoth *rf, + const MinMaxAll *min_max, + float res) { ensureInputDrive(port)->setDriveResistance(rf, min_max, res); } @@ -783,7 +747,7 @@ Sdc::setDriveResistance(const Port *port, InputDrive * Sdc::ensureInputDrive(const Port *port) { - InputDrive *drive = input_drive_map_.findKey(port); + InputDrive *drive = findKey(input_drive_map_, port); if (drive == nullptr) { drive = new InputDrive; input_drive_map_[port] = drive; @@ -795,10 +759,10 @@ Sdc::ensureInputDrive(const Port *port) void Sdc::setSlewLimit(Clock *clk, - const RiseFallBoth *rf, - const PathClkOrData clk_data, - const MinMax *min_max, - float slew) + const RiseFallBoth *rf, + const PathClkOrData clk_data, + const MinMax *min_max, + float slew) { clk->setSlewLimit(rf, clk_data, min_max, slew); have_clk_slew_limits_ = true; @@ -811,33 +775,32 @@ Sdc::haveClkSlewLimits() const } void -Sdc::slewLimit(Clock *clk, +Sdc::slewLimit(const Clock *clk, const RiseFall *rf, - const PathClkOrData clk_data, - const MinMax *min_max, - float &slew, - bool &exists) + const PathClkOrData clk_data, + const MinMax *min_max, + float &slew, + bool &exists) const { clk->slewLimit(rf, clk_data, min_max, slew, exists); } void Sdc::slewLimit(Port *port, - const MinMax *min_max, - float &slew, - bool &exists) + const MinMax *min_max, + float &slew, + bool &exists) const { slew = INF; MinMaxFloatValues values; - port_slew_limit_map_.findKey(port, values, exists); - if (exists) - values.value(min_max, slew, exists); + findKeyValue(port_slew_limit_map_, port, values, exists); + values.value(min_max, slew, exists); } void Sdc::setSlewLimit(Port *port, - const MinMax *min_max, - float slew) + const MinMax *min_max, + float slew) { MinMaxFloatValues &values = port_slew_limit_map_[port]; values.setValue(min_max, slew); @@ -845,21 +808,21 @@ Sdc::setSlewLimit(Port *port, void Sdc::slewLimit(Cell *cell, - const MinMax *min_max, - float &slew, - bool &exists) + const MinMax *min_max, + float &slew, + bool &exists) const { slew = INF; MinMaxFloatValues values; - cell_slew_limit_map_.findKey(cell, values, exists); + findKeyValue(cell_slew_limit_map_, cell, values, exists); if (exists) values.value(min_max, slew, exists); } void Sdc::setSlewLimit(Cell *cell, - const MinMax *min_max, - float slew) + const MinMax *min_max, + float slew) { MinMaxFloatValues &values = cell_slew_limit_map_[cell]; values.setValue(min_max, slew); @@ -867,22 +830,22 @@ Sdc::setSlewLimit(Cell *cell, void Sdc::capacitanceLimit(Cell *cell, - const MinMax *min_max, - float &cap, - bool &exists) + const MinMax *min_max, + float &cap, + bool &exists) const { cap = 0.0; exists = false; MinMaxFloatValues values; - cell_cap_limit_map_.findKey(cell, values, exists); + findKeyValue(cell_cap_limit_map_, cell, values, exists); if (exists) values.value(min_max, cap, exists); } void Sdc::setCapacitanceLimit(Cell *cell, - const MinMax *min_max, - float cap) + const MinMax *min_max, + float cap) { MinMaxFloatValues &values = cell_cap_limit_map_[cell]; values.setValue(min_max, cap); @@ -890,22 +853,22 @@ Sdc::setCapacitanceLimit(Cell *cell, void Sdc::capacitanceLimit(Port *port, - const MinMax *min_max, - float &cap, - bool &exists) + const MinMax *min_max, + float &cap, + bool &exists) const { cap = 0.0; exists = false; MinMaxFloatValues values; - port_cap_limit_map_.findKey(port, values, exists); + findKeyValue(port_cap_limit_map_, port, values, exists); if (exists) values.value(min_max, cap, exists); } void Sdc::setCapacitanceLimit(Port *port, - const MinMax *min_max, - float cap) + const MinMax *min_max, + float cap) { MinMaxFloatValues &values = port_cap_limit_map_[port]; values.setValue(min_max, cap); @@ -913,22 +876,22 @@ Sdc::setCapacitanceLimit(Port *port, void Sdc::capacitanceLimit(Pin *pin, - const MinMax *min_max, - float &cap, - bool &exists) + const MinMax *min_max, + float &cap, + bool &exists) const { cap = 0.0; exists = false; MinMaxFloatValues values; - pin_cap_limit_map_.findKey(pin, values, exists); + findKeyValue(pin_cap_limit_map_, pin, values, exists); if (exists) values.value(min_max, cap, exists); } void Sdc::setCapacitanceLimit(Pin *pin, - const MinMax *min_max, - float cap) + const MinMax *min_max, + float cap) { MinMaxFloatValues &values = pin_cap_limit_map_[pin]; values.setValue(min_max, cap); @@ -936,21 +899,21 @@ Sdc::setCapacitanceLimit(Pin *pin, void Sdc::fanoutLimit(Cell *cell, - const MinMax *min_max, - float &fanout, - bool &exists) + const MinMax *min_max, + float &fanout, + bool &exists) const { fanout = min_max->initValue(); MinMaxFloatValues values; - cell_fanout_limit_map_.findKey(cell, values, exists); + findKeyValue(cell_fanout_limit_map_, cell, values, exists); if (exists) values.value(min_max, fanout, exists); } void Sdc::setFanoutLimit(Cell *cell, - const MinMax *min_max, - float fanout) + const MinMax *min_max, + float fanout) { MinMaxFloatValues &values = cell_fanout_limit_map_[cell]; values.setValue(min_max, fanout); @@ -958,21 +921,21 @@ Sdc::setFanoutLimit(Cell *cell, void Sdc::fanoutLimit(Port *port, - const MinMax *min_max, - float &fanout, - bool &exists) + const MinMax *min_max, + float &fanout, + bool &exists) const { fanout = 0.0; MinMaxFloatValues values; - port_fanout_limit_map_.findKey(port, values, exists); + findKeyValue(port_fanout_limit_map_, port, values, exists); if (exists) values.value(min_max, fanout, exists); } void Sdc::setFanoutLimit(Port *port, - const MinMax *min_max, - float fanout) + const MinMax *min_max, + float fanout) { MinMaxFloatValues &values = port_fanout_limit_map_[port]; values.setValue(min_max, fanout); @@ -994,13 +957,13 @@ Sdc::maxArea() const Clock * Sdc::makeClock(const char *name, - PinSet *pins, - bool add_to_pins, - float period, - FloatSeq *waveform, - const char *comment) + PinSet *pins, + bool add_to_pins, + float period, + FloatSeq *waveform, + const char *comment) { - Clock *clk = clock_name_map_.findKey(name); + Clock *clk = findKey(clock_name_map_, name); if (!add_to_pins) deletePinClocks(clk, pins); if (clk) @@ -1024,20 +987,20 @@ Sdc::makeClock(const char *name, Clock * Sdc::makeGeneratedClock(const char *name, - PinSet *pins, - bool add_to_pins, - Pin *src_pin, - Clock *master_clk, - int divide_by, - int multiply_by, - float duty_cycle, - bool invert, - bool combinational, - IntSeq *edges, - FloatSeq *edge_shifts, - const char *comment) + PinSet *pins, + bool add_to_pins, + Pin *src_pin, + Clock *master_clk, + int divide_by, + int multiply_by, + float duty_cycle, + bool invert, + bool combinational, + IntSeq *edges, + FloatSeq *edge_shifts, + const char *comment) { - Clock *clk = clock_name_map_.findKey(name); + Clock *clk = findKey(clock_name_map_, name); if (!add_to_pins) deletePinClocks(clk, pins); if (clk) @@ -1048,11 +1011,11 @@ Sdc::makeGeneratedClock(const char *name, clock_name_map_[clk->name()] = clk; } clk->initGeneratedClk(pins, add_to_pins, src_pin, master_clk, - divide_by, multiply_by, duty_cycle, - invert, combinational, - edges, edge_shifts, + divide_by, multiply_by, duty_cycle, + invert, combinational, + edges, edge_shifts, variables_->propagateAllClocks(), - comment, network_); + comment, network_); makeClkPinMappings(clk); clearCycleAcctings(); invalidateGeneratedClks(); @@ -1074,14 +1037,14 @@ Sdc::invalidateGeneratedClks() const // is not the clock being defined and has no pins it is removed. void Sdc::deletePinClocks(Clock *defining_clk, - PinSet *pins) + PinSet *pins) { // Find all the clocks defined on pins to avoid finding the clock's // vertex pins multiple times. ClockSet clks; if (pins) { for (const Pin *pin : *pins) { - ClockSet *pin_clks = clock_pin_map_.findKey(pin); + ClockSet *pin_clks = findKey(clock_pin_map_, pin); if (pin_clks) { for (Clock *clk : *pin_clks) clks.insert(clk); @@ -1094,12 +1057,12 @@ Sdc::deletePinClocks(Clock *defining_clk, clk->deletePin(pin); if (clk != defining_clk) { if (clk->pins().empty()) - removeClock(clk); + removeClock(clk); else { - clk->makeLeafPins(network_); - // One of the remaining clock pins may use a vertex pin that - // was deleted above. - makeClkPinMappings(clk); + clk->makeLeafPins(network_); + // One of the remaining clock pins may use a vertex pin that + // was deleted above. + makeClkPinMappings(clk); } } } @@ -1109,23 +1072,23 @@ void Sdc::deleteClkPinMappings(Clock *clk) { for (const Pin *pin : clk->pins()) { - ClockSet *pin_clks = clock_pin_map_.findKey(pin); + ClockSet *pin_clks = findKey(clock_pin_map_, pin); if (pin_clks) { pin_clks->erase(clk); if (pin_clks->empty()) { - clock_pin_map_.erase(pin); - delete pin_clks; + clock_pin_map_.erase(pin); + delete pin_clks; } } } for (const Pin *pin : clk->leafPins()) { - ClockSet *pin_clks = clock_leaf_pin_map_.findKey(pin); + ClockSet *pin_clks = findKey(clock_leaf_pin_map_, pin); if (pin_clks) { pin_clks->erase(clk); if (pin_clks->empty()) { - clock_leaf_pin_map_.erase(pin); - delete pin_clks; + clock_leaf_pin_map_.erase(pin); + delete pin_clks; } } } @@ -1135,19 +1098,19 @@ void Sdc::makeClkPinMappings(Clock *clk) { for (const Pin *pin : clk->pins()) { - ClockSet *pin_clks = clock_pin_map_.findKey(pin); + ClockSet *pin_clks = findKey(clock_pin_map_, pin); if (pin_clks == nullptr) { pin_clks = new ClockSet; - clock_pin_map_.insert(pin, pin_clks); + clock_pin_map_[pin] = pin_clks; } pin_clks->insert(clk); } for (const Pin *pin : clk->leafPins()) { - ClockSet *pin_clks = clock_leaf_pin_map_.findKey(pin); + ClockSet *pin_clks = findKey(clock_leaf_pin_map_, pin); if (pin_clks == nullptr) { pin_clks = new ClockSet; - clock_leaf_pin_map_.insert(pin, pin_clks); + clock_leaf_pin_map_[pin] = pin_clks; } pin_clks->insert(clk); } @@ -1169,7 +1132,7 @@ Sdc::removeClock(Clock *clk) clearCycleAcctings(); deleteClkPinMappings(clk); - clocks_.eraseObject(clk); + clocks_.erase(std::find(clocks_.begin(), clocks_.end(), clk)); clock_name_map_.erase(clk->name()); delete clk; } @@ -1180,7 +1143,7 @@ Sdc::deleteMasterClkRefs(Clock *clk) { for (auto gclk : clocks_) { if (gclk->isGenerated() - && gclk->masterClk() == clk) { + && gclk->masterClk() == clk) { gclk->setMasterClk(nullptr); } } @@ -1189,7 +1152,7 @@ Sdc::deleteMasterClkRefs(Clock *clk) Clock * Sdc::findClock(const char *name) const { - return clock_name_map_.findKey(name); + return findKey(clock_name_map_, name); } bool @@ -1213,7 +1176,7 @@ Sdc::isLeafPinNonGeneratedClock(const Pin *pin) const if (clks) { for (Clock *clk : *clks) { if (!clk->isGenerated()) - return true; + return true; } return false; } @@ -1224,13 +1187,13 @@ Sdc::isLeafPinNonGeneratedClock(const Pin *pin) const ClockSet * Sdc::findLeafPinClocks(const Pin *pin) const { - return clock_leaf_pin_map_.findKey(pin); + return findKey(clock_leaf_pin_map_, pin); } ClockSet * Sdc::findClocks(const Pin *pin) const { - return clock_pin_map_.findKey(pin); + return findKey(clock_pin_map_, pin); } ClockSeq @@ -1245,18 +1208,20 @@ Sdc::findClocksMatching(PatternMatch *pattern) const else { for (auto clk : clocks_) { if (pattern->match(clk->name())) - matches.push_back(clk); + matches.push_back(clk); } } return matches; } -void -Sdc::sortedClocks(ClockSeq &clks) +ClockSeq +Sdc::sortedClocks() const { - for (auto clk : clocks_) + ClockSeq clks; + for (Clock *clk : clocks_) clks.push_back(clk); sort(clks, ClkNameLess()); + return clks; } ClockEdge * @@ -1271,8 +1236,8 @@ class ClkHpinDisable { public: ClkHpinDisable(const Clock *clk, - const Pin *from_pin, - const Pin *to_pin); + const Pin *from_pin, + const Pin *to_pin); const Clock *clk() const { return clk_; } const Pin *fromPin() const { return from_pin_; } const Pin *toPin() const { return to_pin_; } @@ -1284,8 +1249,8 @@ private: }; ClkHpinDisable::ClkHpinDisable(const Clock *clk, - const Pin *from_pin, - const Pin *to_pin) : + const Pin *from_pin, + const Pin *to_pin) : clk_(clk), from_pin_(from_pin), to_pin_(to_pin) @@ -1299,7 +1264,7 @@ ClkHpinDisableLess::ClkHpinDisableLess(const Network *network) : bool ClkHpinDisableLess::operator()(const ClkHpinDisable *disable1, - const ClkHpinDisable *disable2) const + const ClkHpinDisable *disable2) const { int clk_index1 = disable1->clk()->index(); int clk_index2 = disable2->clk()->index(); @@ -1318,10 +1283,10 @@ class FindClkHpinDisables : public HpinDrvrLoadVisitor { public: FindClkHpinDisables(Clock *clk, - const Network *network, - Sdc *sdc); + const Network *network, + Sdc *sdc); bool drvrLoadExists(const Pin *drvr, - const Pin *load); + const Pin *load); protected: virtual void visit(HpinDrvrLoad *drvr_load); @@ -1336,8 +1301,8 @@ protected: }; FindClkHpinDisables::FindClkHpinDisables(Clock *clk, - const Network *network, - Sdc *sdc) : + const Network *network, + Sdc *sdc) : HpinDrvrLoadVisitor(), clk_(clk), drvr_loads_(network), @@ -1362,8 +1327,8 @@ FindClkHpinDisables::visit(HpinDrvrLoad *drvr_load) void FindClkHpinDisables::makeClkHpinDisables(const Pin *clk_src, - const Pin *drvr, - const Pin *load) + const Pin *drvr, + const Pin *load) { ClockSet *clks = sdc_->findClocks(clk_src); if (clks) { @@ -1379,36 +1344,36 @@ FindClkHpinDisables::makeClkHpinDisables(const Pin *clk_src, bool FindClkHpinDisables::drvrLoadExists(const Pin *drvr, - const Pin *load) + const Pin *load) { PinPair probe(drvr, load); - return drvr_loads_.hasKey(probe); + return drvr_loads_.contains(probe); } void Sdc::ensureClkHpinDisables() { if (!clk_hpin_disables_valid_) { - clk_hpin_disables_.deleteContentsClear(); + deleteContents(clk_hpin_disables_); for (auto clk : clocks_) { for (const Pin *src : clk->pins()) { - if (network_->isHierarchical(src)) { - FindClkHpinDisables visitor1(clk, network_, this); - visitHpinDrvrLoads(src, network_, &visitor1); - PinSeq loads, drvrs; - PinSet visited_drvrs(network_); - FindNetDrvrLoads visitor2(nullptr, visited_drvrs, loads, drvrs, network_); - network_->visitConnectedPins(src, visitor2); + if (network_->isHierarchical(src)) { + FindClkHpinDisables visitor1(clk, network_, this); + visitHpinDrvrLoads(src, network_, &visitor1); + PinSeq loads, drvrs; + PinSet visited_drvrs(network_); + FindNetDrvrLoads visitor2(nullptr, visited_drvrs, loads, drvrs, network_); + network_->visitConnectedPins(src, visitor2); - // Disable fanouts from the src driver pins that do - // not go thru the hierarchical src pin. - for (const Pin *drvr : drvrs) { - for (const Pin *load : loads) { - if (!visitor1.drvrLoadExists(drvr, load)) - makeClkHpinDisable(clk, drvr, load); - } - } - } + // Disable fanouts from the src driver pins that do + // not go thru the hierarchical src pin. + for (const Pin *drvr : drvrs) { + for (const Pin *load : loads) { + if (!visitor1.drvrLoadExists(drvr, load)) + makeClkHpinDisable(clk, drvr, load); + } + } + } } } clk_hpin_disables_valid_ = true; @@ -1417,11 +1382,11 @@ Sdc::ensureClkHpinDisables() void Sdc::makeClkHpinDisable(const Clock *clk, - const Pin *drvr, - const Pin *load) + const Pin *drvr, + const Pin *load) { ClkHpinDisable probe(clk, drvr, load); - if (!clk_hpin_disables_.hasKey(&probe)) { + if (!clk_hpin_disables_.contains(&probe)) { ClkHpinDisable *disable = new ClkHpinDisable(clk, drvr, load); clk_hpin_disables_.insert(disable); } @@ -1439,12 +1404,12 @@ Sdc::clkHpinDisablesInvalid() // Check for disable by hierarchical clock pin between driver and load. bool Sdc::clkDisabledByHpinThru(const Clock *clk, - const Pin *from_pin, - const Pin *to_pin) + const Pin *from_pin, + const Pin *to_pin) const { - if (clk->leafPins().hasKey(from_pin)) { + if (clk->leafPins().contains(from_pin)) { ClkHpinDisable probe(clk, from_pin, to_pin); - return clk_hpin_disables_.hasKey(&probe); + return clk_hpin_disables_.contains(&probe); } else return false; @@ -1479,16 +1444,16 @@ Sdc::removePropagatedClock(Pin *pin) } bool -Sdc::isPropagatedClock(const Pin *pin) +Sdc::isPropagatedClock(const Pin *pin) const { - return propagated_clk_pins_.hasKey(pin); + return propagated_clk_pins_.contains(pin); } void Sdc::setClockSlew(Clock *clk, - const RiseFallBoth *rf, - const MinMaxAll *min_max, - float slew) + const RiseFallBoth *rf, + const MinMaxAll *min_max, + float slew) { clk->setSlew(rf, min_max, slew); } @@ -1499,18 +1464,50 @@ Sdc::removeClockSlew(Clock *clk) clk->removeSlew(); } +class MakeClkLatencyEdge : public HierPinThruVisitor +{ +public: + MakeClkLatencyEdge(ClockLatency *latency, + EdgeClockLatencyMap &edge_clk_latency_map); + +private: + void visit(const Pin *drvr, + const Pin *load) override; + + ClockLatency *latency_; + EdgeClockLatencyMap &edge_clk_latency_map_; +}; + +MakeClkLatencyEdge::MakeClkLatencyEdge(ClockLatency *latency, + EdgeClockLatencyMap &edge_clk_latency_map) : + latency_(latency), + edge_clk_latency_map_(edge_clk_latency_map) +{ +} + +void +MakeClkLatencyEdge::visit(const Pin *drvr, + const Pin *load) +{ + edge_clk_latency_map_[{drvr, load}] = latency_; +} + void Sdc::setClockLatency(Clock *clk, - Pin *pin, - const RiseFallBoth *rf, - const MinMaxAll *min_max, - float delay) + Pin *pin, + const RiseFallBoth *rf, + const MinMaxAll *min_max, + float delay) { ClockLatency probe(clk, pin); - ClockLatency *latency = clk_latencies_.findKey(&probe); + ClockLatency *latency = findKey(clk_latencies_, &probe); if (latency == nullptr) { latency = new ClockLatency(clk, pin); clk_latencies_.insert(latency); + if (pin && network_->isHierarchical(pin)) { + MakeClkLatencyEdge visitor(latency, edge_clk_latency_map_); + visitDrvrLoadsThruHierPin(pin, network_, &visitor); + } } latency->setDelay(rf, min_max, delay); @@ -1521,12 +1518,41 @@ Sdc::setClockLatency(Clock *clk, removePropagatedClock(pin); } +ClockLatency * +Sdc::clockLatency(Edge *edge) const +{ + PinPair pins(edge->from(graph_)->pin(), edge->to(graph_)->pin()); + auto itr = edge_clk_latency_map_.find(pins); + if (itr == edge_clk_latency_map_.end()) + return nullptr; + else + return itr->second; +} + +void +Sdc::clockLatency(Edge *edge, + const RiseFall *rf, + const MinMax *min_max, + // Return values. + float &latency, + bool &exists) const + +{ + ClockLatency *latencies = clockLatency(edge); + if (latencies) + latencies->delay(rf, min_max, latency, exists); + else { + latency = 0.0; + exists = false; + } +} + void Sdc::removeClockLatency(const Clock *clk, - const Pin *pin) + const Pin *pin) { ClockLatency probe(clk, pin); - ClockLatency *latency = clk_latencies_.findKey(&probe); + ClockLatency *latency = findKey(clk_latencies_, &probe); if (latency) deleteClockLatency(latency); } @@ -1557,29 +1583,29 @@ bool Sdc::hasClockLatency(const Pin *pin) const { ClockLatency probe(nullptr, pin); - return clk_latencies_.hasKey(&probe); + return clk_latencies_.contains(&probe); } void Sdc::clockLatency(const Clock *clk, - const Pin *pin, - const RiseFall *rf, - const MinMax *min_max, - // Return values. - float &latency, - bool &exists) const + const Pin *pin, + const RiseFall *rf, + const MinMax *min_max, + // Return values. + float &latency, + bool &exists) const { latency = 0.0; exists = false; if (pin && clk) { ClockLatency probe(clk, pin); - ClockLatency *latencies = clk_latencies_.findKey(&probe); + ClockLatency *latencies = findKey(clk_latencies_, &probe); if (latencies) latencies->delay(rf, min_max, latency, exists); } if (!exists) { ClockLatency probe(nullptr, pin); - ClockLatency *latencies = clk_latencies_.findKey(&probe); + ClockLatency *latencies = findKey(clk_latencies_, &probe); if (latencies) latencies->delay(rf, min_max, latency, exists); } @@ -1587,38 +1613,38 @@ Sdc::clockLatency(const Clock *clk, void Sdc::clockLatency(const Clock *clk, - const RiseFall *rf, - const MinMax *min_max, - // Return values. - float &latency, - bool &exists) const + const RiseFall *rf, + const MinMax *min_max, + // Return values. + float &latency, + bool &exists) const { latency = 0.0; exists = false; ClockLatency probe(clk, nullptr); - ClockLatency *latencies = clk_latencies_.findKey(&probe); + ClockLatency *latencies = findKey(clk_latencies_, &probe); if (latencies) latencies->delay(rf, min_max, latency, exists); } float Sdc::clockLatency(const Clock *clk, - const RiseFall *rf, - const MinMax *min_max) const + const RiseFall *rf, + const MinMax *min_max) const { float latency; bool exists; clockLatency(clk, rf, min_max, - latency, exists); + latency, exists); return latency; } void Sdc::setClockUncertainty(Pin *pin, - const SetupHoldAll *setup_hold, - float uncertainty) + const SetupHoldAll *setup_hold, + float uncertainty) { - ClockUncertainties *uncertainties = pin_clk_uncertainty_map_.findKey(pin); + ClockUncertainties *uncertainties = findKey(pin_clk_uncertainty_map_, pin); if (uncertainties == nullptr) { uncertainties = new ClockUncertainties; pin_clk_uncertainty_map_[pin] = uncertainties; @@ -1628,9 +1654,9 @@ Sdc::setClockUncertainty(Pin *pin, void Sdc::removeClockUncertainty(Pin *pin, - const SetupHoldAll *setup_hold) + const SetupHoldAll *setup_hold) { - ClockUncertainties *uncertainties = pin_clk_uncertainty_map_.findKey(pin); + ClockUncertainties *uncertainties = findKey(pin_clk_uncertainty_map_, pin); if (uncertainties) { uncertainties->removeValue(setup_hold); if (uncertainties->empty()) { @@ -1640,19 +1666,19 @@ Sdc::removeClockUncertainty(Pin *pin, } } -ClockUncertainties * -Sdc::clockUncertainties(const Pin *pin) +const ClockUncertainties * +Sdc::clockUncertainties(const Pin *pin) const { - return pin_clk_uncertainty_map_.findKey(pin); + return findKey(pin_clk_uncertainty_map_, pin); } void Sdc::clockUncertainty(const Pin *pin, - const SetupHold *setup_hold, - float &uncertainty, - bool &exists) + const SetupHold *setup_hold, + float &uncertainty, + bool &exists) { - ClockUncertainties *uncertainties = clockUncertainties(pin); + const ClockUncertainties *uncertainties = clockUncertainties(pin); if (uncertainties) uncertainties->value(setup_hold, uncertainty, exists); else { @@ -1663,19 +1689,19 @@ Sdc::clockUncertainty(const Pin *pin, void Sdc::clockUncertainty(const Clock *src_clk, - const RiseFall *src_rf, - const Clock *tgt_clk, - const RiseFall *tgt_rf, - const SetupHold *setup_hold, - float &uncertainty, - bool &exists) + const RiseFall *src_rf, + const Clock *tgt_clk, + const RiseFall *tgt_rf, + const SetupHold *setup_hold, + float &uncertainty, + bool &exists) const { InterClockUncertainty probe(src_clk, tgt_clk); InterClockUncertainty *uncertainties = - inter_clk_uncertainties_.findKey(&probe); + findKey(inter_clk_uncertainties_, &probe); if (uncertainties) uncertainties->uncertainty(src_rf, tgt_rf, setup_hold, - uncertainty, exists); + uncertainty, exists); else { uncertainty = 0.0; exists = false; @@ -1684,15 +1710,15 @@ Sdc::clockUncertainty(const Clock *src_clk, void Sdc::setClockUncertainty(Clock *from_clk, - const RiseFallBoth *from_rf, - Clock *to_clk, - const RiseFallBoth *to_rf, - const SetupHoldAll *setup_hold, - float uncertainty) + const RiseFallBoth *from_rf, + Clock *to_clk, + const RiseFallBoth *to_rf, + const SetupHoldAll *setup_hold, + float uncertainty) { InterClockUncertainty probe(from_clk, to_clk); InterClockUncertainty *uncertainties = - inter_clk_uncertainties_.findKey(&probe); + findKey(inter_clk_uncertainties_, &probe); if (uncertainties == nullptr) { uncertainties = new InterClockUncertainty(from_clk, to_clk); inter_clk_uncertainties_.insert(uncertainties); @@ -1702,14 +1728,14 @@ Sdc::setClockUncertainty(Clock *from_clk, void Sdc::removeClockUncertainty(Clock *from_clk, - const RiseFallBoth *from_rf, - Clock *to_clk, - const RiseFallBoth *to_rf, - const SetupHoldAll *setup_hold) + const RiseFallBoth *from_rf, + Clock *to_clk, + const RiseFallBoth *to_rf, + const SetupHoldAll *setup_hold) { InterClockUncertainty probe(from_clk, to_clk); InterClockUncertainty *uncertainties = - inter_clk_uncertainties_.findKey(&probe); + findKey(inter_clk_uncertainties_, &probe); if (uncertainties) { uncertainties->removeUncertainty(from_rf, to_rf, setup_hold); if (uncertainties->empty()) { @@ -1733,7 +1759,7 @@ Sdc::deleteInterClockUncertaintiesReferencing(Clock *clk) iter != inter_clk_uncertainties_.cend(); ) { InterClockUncertainty *uncertainties = *iter; if (uncertainties->src() == clk - || uncertainties->target() == clk) { + || uncertainties->target() == clk) { iter = inter_clk_uncertainties_.erase(iter); delete uncertainties; } @@ -1746,14 +1772,14 @@ Sdc::deleteInterClockUncertaintiesReferencing(Clock *clk) void Sdc::setClockInsertion(const Clock *clk, - const Pin *pin, - const RiseFallBoth *rf, - const MinMaxAll *min_max, - const EarlyLateAll *early_late, - float delay) + const Pin *pin, + const RiseFallBoth *rf, + const MinMaxAll *min_max, + const EarlyLateAll *early_late, + float delay) { ClockInsertion probe(clk, pin); - ClockInsertion *insertion = clk_insertions_.findKey(&probe); + ClockInsertion *insertion = findKey(clk_insertions_, &probe); if (insertion == nullptr) { insertion = new ClockInsertion(clk, pin); clk_insertions_.insert(insertion); @@ -1763,14 +1789,14 @@ Sdc::setClockInsertion(const Clock *clk, void Sdc::setClockInsertion(const Clock *clk, - const Pin *pin, - const RiseFall *rf, - const MinMax *min_max, - const EarlyLate *early_late, - float delay) + const Pin *pin, + const RiseFall *rf, + const MinMax *min_max, + const EarlyLate *early_late, + float delay) { ClockInsertion probe(clk, pin); - ClockInsertion *insertion = clk_insertions_.findKey(&probe); + ClockInsertion *insertion = findKey(clk_insertions_, &probe); if (insertion == nullptr) { insertion = new ClockInsertion(clk, pin); clk_insertions_.insert(insertion); @@ -1780,10 +1806,10 @@ Sdc::setClockInsertion(const Clock *clk, void Sdc::removeClockInsertion(const Clock *clk, - const Pin *pin) + const Pin *pin) { ClockInsertion probe(clk, pin); - ClockInsertion *insertion = clk_insertions_.findKey(&probe); + ClockInsertion *insertion = findKey(clk_insertions_, &probe); if (insertion != nullptr) deleteClockInsertion(insertion); } @@ -1819,9 +1845,9 @@ Sdc::deleteClockInsertionsReferencing(Clock *clk) float Sdc::clockInsertion(const Clock *clk, - const RiseFall *rf, - const MinMax *min_max, - const EarlyLate *early_late) const + const RiseFall *rf, + const MinMax *min_max, + const EarlyLate *early_late) const { float insertion; bool exists; @@ -1833,31 +1859,31 @@ bool Sdc::hasClockInsertion(const Pin *pin) const { ClockInsertion probe(nullptr, pin); - return clk_insertions_.hasKey(&probe); + return clk_insertions_.contains(&probe); } void Sdc::clockInsertion(const Clock *clk, - const Pin *pin, - const RiseFall *rf, - const MinMax *min_max, - const EarlyLate *early_late, - // Return values. - float &insertion, - bool &exists) const + const Pin *pin, + const RiseFall *rf, + const MinMax *min_max, + const EarlyLate *early_late, + // Return values. + float &insertion, + bool &exists) const { ClockInsertion *insert = nullptr; if (clk && pin) { ClockInsertion probe(clk, pin); - insert = clk_insertions_.findKey(&probe); + insert = findKey(clk_insertions_, &probe); } if (insert == nullptr && pin) { ClockInsertion probe(nullptr, pin); - insert = clk_insertions_.findKey(&probe); + insert = findKey(clk_insertions_, &probe); } if (insert == nullptr && clk) { ClockInsertion probe(clk, nullptr); - insert = clk_insertions_.findKey(&probe); + insert = findKey(clk_insertions_, &probe); } if (insert) @@ -1916,24 +1942,24 @@ ClockInsertionkLess::operator()(const ClockInsertion *insert1, ClockGroups * Sdc::makeClockGroups(const char *name, - bool logically_exclusive, - bool physically_exclusive, - bool asynchronous, - bool allow_paths, - const char *comment) + bool logically_exclusive, + bool physically_exclusive, + bool asynchronous, + bool allow_paths, + const char *comment) { char *gen_name = nullptr; if (name == nullptr || name[0] == '\0') name = gen_name = makeClockGroupsName(); else { - ClockGroups *groups = clk_groups_name_map_.findKey(name); + ClockGroups *groups = findKey(clk_groups_name_map_, name); if (groups) removeClockGroups(groups); } ClockGroups *groups = new ClockGroups(name, logically_exclusive, - physically_exclusive, - asynchronous, allow_paths, comment); + physically_exclusive, + asynchronous, allow_paths, comment); clk_groups_name_map_[groups->name()] = groups; stringDelete(gen_name); return groups; @@ -1949,13 +1975,13 @@ Sdc::makeClockGroupsName() i++; stringDelete(name); name = stringPrint("group%d", i); - } while (clk_groups_name_map_.hasKey(name)); + } while (clk_groups_name_map_.contains(name)); return name; } void Sdc::makeClockGroup(ClockGroups *clk_groups, - ClockSet *clks) + ClockSet *clks) { clk_groups->makeClockGroup(clks); } @@ -1973,7 +1999,7 @@ void Sdc::makeClkGroupExclusions(ClockGroups *clk_groups) { if (!(clk_groups->asynchronous() - && clk_groups->allowPaths())) { + && clk_groups->allowPaths())) { ClockGroupSet *groups = clk_groups->groups(); if (groups->size() == 1) makeClkGroupExclusions1(groups); @@ -1987,13 +2013,12 @@ Sdc::makeClkGroupExclusions(ClockGroups *clk_groups) void Sdc::makeClkGroupExclusions1(ClockGroupSet *groups) { - ClockGroupSet::Iterator group_iter1(groups); - ClockGroup *group1 = group_iter1.next(); - for (auto clk1 : *group1) { + ClockGroup *group1 = *groups->begin(); + for (Clock *clk1 : *group1) { for (Clock *clk2 : clocks_) { if (clk2 != clk1 - && !group1->hasKey(clk2)) - clk_group_exclusions_.insert(ClockPair(clk1, clk2)); + && !group1->contains(clk2)) + clk_group_exclusions_.insert(ClockPair(clk1, clk2)); } } makeClkGroupSame(group1); @@ -2005,14 +2030,14 @@ Sdc::makeClkGroupExclusions(ClockGroupSet *groups) for (auto group1 : *groups) { for (auto group2 : *groups) { if (group1 != group2) { - for (auto clk1 : *group1) { - for (auto clk2 : *group2) { - // ClockPair is symmetric so only add one clk1/clk2 pair. - if (clk1->index() < clk2->index()) { - clk_group_exclusions_.insert(ClockPair(clk1, clk2)); - } - } - } + for (auto clk1 : *group1) { + for (auto clk2 : *group2) { + // ClockPair is symmetric so only add one clk1/clk2 pair. + if (clk1->index() < clk2->index()) { + clk_group_exclusions_.insert(ClockPair(clk1, clk2)); + } + } + } } } makeClkGroupSame(group1); @@ -2025,9 +2050,9 @@ Sdc::makeClkGroupSame(ClockGroup *group) for (auto clk1 : *group) { for (auto clk2 : *group) { if (clk1->index() <= clk2->index()) { - ClockPair clk_pair(clk1, clk2); - if (!clk_group_same_.hasKey(clk_pair)) - clk_group_same_.insert(clk_pair); + ClockPair clk_pair(clk1, clk2); + if (!clk_group_same_.contains(clk_pair)) + clk_group_same_.insert(clk_pair); } } } @@ -2042,11 +2067,11 @@ Sdc::clearClkGroupExclusions() bool Sdc::sameClockGroup(const Clock *clk1, - const Clock *clk2) + const Clock *clk2) const { if (clk1 && clk2) { ClockPair clk_pair(clk1, clk2); - bool excluded = clk_group_exclusions_.hasKey(clk_pair); + bool excluded = clk_group_exclusions_.contains(clk_pair); return !excluded; } else @@ -2055,16 +2080,16 @@ Sdc::sameClockGroup(const Clock *clk1, bool Sdc::sameClockGroupExplicit(const Clock *clk1, - const Clock *clk2) + const Clock *clk2) { ClockPair clk_pair(clk1, clk2); - return clk_group_same_.hasKey(clk_pair); + return clk_group_same_.contains(clk_pair); } void Sdc::removeClockGroups(const char *name) { - ClockGroups *clk_groups = clk_groups_name_map_.findKey(name); + ClockGroups *clk_groups = findKey(clk_groups_name_map_, name); if (clk_groups) removeClockGroups(clk_groups); } @@ -2073,14 +2098,14 @@ void Sdc::removeClockGroupsLogicallyExclusive(const char *name) { if (name) { - ClockGroups *groups = clk_groups_name_map_.findKey(name); + ClockGroups *groups = findKey(clk_groups_name_map_, name); if (groups && groups->logicallyExclusive()) removeClockGroups(groups); } else { for (const auto [name, groups] : clk_groups_name_map_) { if (groups->logicallyExclusive()) - removeClockGroups(groups); + removeClockGroups(groups); } } } @@ -2089,14 +2114,14 @@ void Sdc::removeClockGroupsPhysicallyExclusive(const char *name) { if (name) { - ClockGroups *groups = clk_groups_name_map_.findKey(name); + ClockGroups *groups = findKey(clk_groups_name_map_, name); if (groups && groups->physicallyExclusive()) removeClockGroups(groups); } else { for (const auto [name, groups] : clk_groups_name_map_) { if (groups->physicallyExclusive()) - removeClockGroups(groups); + removeClockGroups(groups); } } } @@ -2105,14 +2130,14 @@ void Sdc::removeClockGroupsAsynchronous(const char *name) { if (name) { - ClockGroups *groups = clk_groups_name_map_.findKey(name); + ClockGroups *groups = findKey(clk_groups_name_map_, name); if (groups && groups->asynchronous()) removeClockGroups(groups); } else { for (const auto [name, groups] : clk_groups_name_map_) { if (groups->asynchronous()) - removeClockGroups(groups); + removeClockGroups(groups); } } } @@ -2139,8 +2164,8 @@ Sdc::clockGroupsDeleteClkRefs(Clock *clk) void Sdc::setClockSense(PinSet *pins, - ClockSet *clks, - ClockSense sense) + ClockSet *clks, + ClockSense sense) { if (clks && clks->empty()) { delete clks; @@ -2149,7 +2174,7 @@ Sdc::setClockSense(PinSet *pins, for (const Pin *pin : *pins) { if (clks) { for (const Clock *clk : *clks) - setClockSense(pin, clk, sense); + setClockSense(pin, clk, sense); } else setClockSense(pin, nullptr, sense); @@ -2164,7 +2189,7 @@ Sdc::setClockSense(const Pin *pin, ClockSense sense) { PinClockPair probe(pin, clk); - if (clk_sense_map_.hasKey(probe)) + if (clk_sense_map_.contains(probe)) clk_sense_map_[probe] = sense; else { PinClockPair pin_clk(pin, clk); @@ -2174,15 +2199,15 @@ Sdc::setClockSense(const Pin *pin, bool Sdc::clkStopPropagation(const Pin *pin, - const Clock *clk) const + const Clock *clk) const { PinClockPair pin_clk(pin, clk); ClockSense sense; bool exists; - clk_sense_map_.findKey(pin_clk, sense, exists); + findKeyValue(clk_sense_map_, pin_clk, sense, exists); if (!exists) { PinClockPair pin_clk1(pin, nullptr); - clk_sense_map_.findKey(pin_clk1, sense, exists); + findKeyValue(clk_sense_map_, pin_clk1, sense, exists); } return exists && sense == ClockSense::stop; @@ -2190,32 +2215,32 @@ Sdc::clkStopPropagation(const Pin *pin, bool Sdc::clkStopSense(const Pin *to_pin, - const Clock *clk, - const RiseFall *from_rf, - const RiseFall *to_rf) const + const Clock *clk, + const RiseFall *from_rf, + const RiseFall *to_rf) const { PinClockPair pin_clk(to_pin, clk); ClockSense sense; bool exists; - clk_sense_map_.findKey(pin_clk, sense, exists); + findKeyValue(clk_sense_map_, pin_clk, sense, exists); if (!exists) { PinClockPair pin(to_pin, nullptr); - clk_sense_map_.findKey(pin, sense, exists); + findKeyValue(clk_sense_map_, pin, sense, exists); } return exists && (sense == ClockSense::stop - || (sense == ClockSense::positive - && from_rf != to_rf) - || (sense == ClockSense::negative - && from_rf == to_rf)); + || (sense == ClockSense::positive + && from_rf != to_rf) + || (sense == ClockSense::negative + && from_rf == to_rf)); } bool Sdc::clkStopPropagation(const Clock *clk, - const Pin *from_pin, - const RiseFall *from_rf, - const Pin *to_pin, - const RiseFall *to_rf) const + const Pin *from_pin, + const RiseFall *from_rf, + const Pin *to_pin, + const RiseFall *to_rf) const { return clkStopPropagation(from_pin, clk) || clkStopSense(to_pin, clk, from_rf, to_rf); @@ -2228,25 +2253,23 @@ PinClockPairLess::PinClockPairLess(const Network *network) : bool PinClockPairLess::operator()(const PinClockPair &pin_clk1, - const PinClockPair &pin_clk2) const + const PinClockPair &pin_clk2) const { - const Pin *pin1 = pin_clk1.first; - const Pin *pin2 = pin_clk2.first; - const Clock *clk1 = pin_clk1.second; - const Clock *clk2 = pin_clk2.second; + const auto& [pin1, clk1] = pin_clk1; + const auto& [pin2, clk2] = pin_clk2; return pin1 < pin2 || (pin1 == pin2 - && ((clk1 == nullptr && clk2) - || (clk1 && clk2 - && clk1->index() < clk2->index()))); + && ((clk1 == nullptr && clk2) + || (clk1 && clk2 + && clk1->index() < clk2->index()))); } //////////////////////////////////////////////////////////////// void Sdc::setClockGatingCheck(const RiseFallBoth *rf, - const SetupHold *setup_hold, - float margin) + const SetupHold *setup_hold, + float margin) { if (clk_gating_check_ == nullptr) clk_gating_check_ = new ClockGatingCheck; @@ -2255,11 +2278,11 @@ Sdc::setClockGatingCheck(const RiseFallBoth *rf, void Sdc::setClockGatingCheck(Clock *clk, - const RiseFallBoth *rf, - const SetupHold *setup_hold, - float margin) + const RiseFallBoth *rf, + const SetupHold *setup_hold, + float margin) { - ClockGatingCheck *check = clk_gating_check_map_.findKey(clk); + ClockGatingCheck *check = findKey(clk_gating_check_map_, clk); if (check == nullptr) { check = new ClockGatingCheck(); clk_gating_check_map_[clk] = check; @@ -2269,12 +2292,12 @@ Sdc::setClockGatingCheck(Clock *clk, void Sdc::setClockGatingCheck(Instance *inst, - const RiseFallBoth *rf, - const SetupHold *setup_hold, - float margin, - LogicValue active_value) + const RiseFallBoth *rf, + const SetupHold *setup_hold, + float margin, + LogicValue active_value) { - ClockGatingCheck *check = inst_clk_gating_check_map_.findKey(inst); + ClockGatingCheck *check = findKey(inst_clk_gating_check_map_, inst); if (check == nullptr) { check = new ClockGatingCheck(); inst_clk_gating_check_map_[inst] = check; @@ -2285,12 +2308,12 @@ Sdc::setClockGatingCheck(Instance *inst, void Sdc::setClockGatingCheck(const Pin *pin, - const RiseFallBoth *rf, - const SetupHold *setup_hold, - float margin, - LogicValue active_value) + const RiseFallBoth *rf, + const SetupHold *setup_hold, + float margin, + LogicValue active_value) { - ClockGatingCheck *check = pin_clk_gating_check_map_.findKey(pin); + ClockGatingCheck *check = findKey(pin_clk_gating_check_map_, pin); if (check == nullptr) { check = new ClockGatingCheck(); pin_clk_gating_check_map_[pin] = check; @@ -2301,11 +2324,11 @@ Sdc::setClockGatingCheck(const Pin *pin, void Sdc::clockGatingMarginEnablePin(const Pin *enable_pin, - const RiseFall *enable_rf, - const SetupHold *setup_hold, - bool &exists, float &margin) + const RiseFall *enable_rf, + const SetupHold *setup_hold, + bool &exists, float &margin) const { - ClockGatingCheck *check = pin_clk_gating_check_map_.findKey(enable_pin); + ClockGatingCheck *check = findKey(pin_clk_gating_check_map_, enable_pin); if (check) check->margins()->value(enable_rf, setup_hold, margin, exists); else @@ -2314,12 +2337,12 @@ Sdc::clockGatingMarginEnablePin(const Pin *enable_pin, void Sdc::clockGatingMarginInstance(Instance *inst, - const RiseFall *enable_rf, - const SetupHold *setup_hold, - bool &exists, - float &margin) + const RiseFall *enable_rf, + const SetupHold *setup_hold, + bool &exists, + float &margin) const { - ClockGatingCheck *check = inst_clk_gating_check_map_.findKey(inst); + ClockGatingCheck *check = findKey(inst_clk_gating_check_map_, inst); if (check) check->margins()->value(enable_rf, setup_hold, margin, exists); else @@ -2328,12 +2351,12 @@ Sdc::clockGatingMarginInstance(Instance *inst, void Sdc::clockGatingMarginClkPin(const Pin *clk_pin, - const RiseFall *enable_rf, - const SetupHold *setup_hold, - bool &exists, - float &margin) + const RiseFall *enable_rf, + const SetupHold *setup_hold, + bool &exists, + float &margin) const { - ClockGatingCheck *check = pin_clk_gating_check_map_.findKey(clk_pin); + ClockGatingCheck *check = findKey(pin_clk_gating_check_map_, clk_pin); if (check) check->margins()->value(enable_rf, setup_hold, margin, exists); else @@ -2342,12 +2365,12 @@ Sdc::clockGatingMarginClkPin(const Pin *clk_pin, void Sdc::clockGatingMarginClk(const Clock *clk, - const RiseFall *enable_rf, - const SetupHold *setup_hold, - bool &exists, - float &margin) + const RiseFall *enable_rf, + const SetupHold *setup_hold, + bool &exists, + float &margin) const { - ClockGatingCheck *check = clk_gating_check_map_.findKey(clk); + ClockGatingCheck *check = findKey(clk_gating_check_map_, clk); if (check) check->margins()->value(enable_rf, setup_hold, margin, exists); else @@ -2356,9 +2379,9 @@ Sdc::clockGatingMarginClk(const Clock *clk, void Sdc::clockGatingMargin(const RiseFall *enable_rf, - const SetupHold *setup_hold, - bool &exists, - float &margin) + const SetupHold *setup_hold, + bool &exists, + float &margin) const { if (clk_gating_check_) clk_gating_check_->margins()->value(enable_rf, setup_hold, margin, exists); @@ -2368,17 +2391,17 @@ Sdc::clockGatingMargin(const RiseFall *enable_rf, LogicValue Sdc::clockGatingActiveValue(const Pin *clk_pin, - const Pin *enable_pin) + const Pin *enable_pin) const { ClockGatingCheck *check; - check = pin_clk_gating_check_map_.findKey(enable_pin); + check = findKey(pin_clk_gating_check_map_, enable_pin); if (check) return check->activeValue(); Instance *inst = network_->instance(enable_pin); - check = inst_clk_gating_check_map_.findKey(inst); + check = findKey(inst_clk_gating_check_map_, inst); if (check) return check->activeValue(); - check = pin_clk_gating_check_map_.findKey(clk_pin); + check = findKey(pin_clk_gating_check_map_, clk_pin); if (check) return check->activeValue(); return LogicValue::unknown; @@ -2389,7 +2412,7 @@ Sdc::clockGatingActiveValue(const Pin *clk_pin, // Determine cycle accounting "on demand". CycleAccting * Sdc::cycleAccting(const ClockEdge *src, - const ClockEdge *tgt) + const ClockEdge *tgt) { LockGuard lock(cycle_acctings_lock_); return cycle_acctings_.cycleAccting(src, tgt); @@ -2411,29 +2434,29 @@ Sdc::clearCycleAcctings() void Sdc::setDataCheck(Pin *from, - const RiseFallBoth *from_rf, - Pin *to, - const RiseFallBoth *to_rf, - Clock *clk, - const SetupHoldAll *setup_hold, - float margin) + const RiseFallBoth *from_rf, + Pin *to, + const RiseFallBoth *to_rf, + Clock *clk, + const SetupHoldAll *setup_hold, + float margin) { DataCheck *check = nullptr; - DataCheckSet *checks = data_checks_from_map_.findKey(from); + DataCheckSet *checks = findKey(data_checks_from_map_, from); if (checks == nullptr) { checks = new DataCheckSet(DataCheckLess(network_)); data_checks_from_map_[from] = checks; } else { DataCheck probe(from, to, clk); - check = checks->findKey(&probe); + check = findKey(*checks, &probe); } if (check == nullptr) check = new DataCheck(from, to, clk); check->setMargin(from_rf, to_rf, setup_hold, margin); checks->insert(check); - checks = data_checks_to_map_.findKey(to); + checks = findKey(data_checks_to_map_, to); if (checks == nullptr) { checks = new DataCheckSet(DataCheckLess(network_)); data_checks_to_map_[to] = checks; @@ -2443,24 +2466,24 @@ Sdc::setDataCheck(Pin *from, void Sdc::removeDataCheck(Pin *from, - const RiseFallBoth *from_rf, - Pin *to, - const RiseFallBoth *to_rf, - Clock *clk, - const SetupHoldAll *setup_hold) + const RiseFallBoth *from_rf, + Pin *to, + const RiseFallBoth *to_rf, + Clock *clk, + const SetupHoldAll *setup_hold) { DataCheck probe(from, to, clk); - DataCheckSet *checks = data_checks_from_map_.findKey(from); + DataCheckSet *checks = findKey(data_checks_from_map_, from); if (checks) { - DataCheck *check = checks->findKey(&probe); + DataCheck *check = findKey(*checks, &probe); if (check) { check->removeMargin(from_rf, to_rf, setup_hold); if (check->empty()) { - checks->erase(check); - checks = data_checks_to_map_.findKey(to); - if (checks) - checks->erase(check); - delete check; + checks->erase(check); + checks = findKey(data_checks_to_map_, to); + if (checks) + checks->erase(check); + delete check; } } } @@ -2469,27 +2492,27 @@ Sdc::removeDataCheck(Pin *from, DataCheckSet * Sdc::dataChecksFrom(const Pin *from) const { - return data_checks_from_map_.findKey(from); + return findKey(data_checks_from_map_, from); } DataCheckSet * Sdc::dataChecksTo(const Pin *to) const { - return data_checks_to_map_.findKey(to); + return findKey(data_checks_to_map_, to); } //////////////////////////////////////////////////////////////// void Sdc::setLatchBorrowLimit(const Pin *pin, - float limit) + float limit) { pin_latch_borrow_limit_map_[pin] = limit; } void Sdc::setLatchBorrowLimit(const Instance *inst, - float limit) + float limit) { inst_latch_borrow_limit_map_[inst] = limit; } @@ -2509,20 +2532,20 @@ Sdc::deleteLatchBorrowLimitsReferencing(Clock *clk) void Sdc::latchBorrowLimit(const Pin *data_pin, - const Pin *enable_pin, - const Clock *clk, - // Return values. - float &limit, - bool &exists) + const Pin *enable_pin, + const Clock *clk, + // Return values. + float &limit, + bool &exists) { - pin_latch_borrow_limit_map_.findKey(data_pin, limit, exists); + findKeyValue(pin_latch_borrow_limit_map_, data_pin, limit, exists); if (!exists) { - pin_latch_borrow_limit_map_.findKey(enable_pin, limit, exists); + findKeyValue(pin_latch_borrow_limit_map_, enable_pin, limit, exists); if (!exists) { Instance *inst = network_->instance(data_pin); - inst_latch_borrow_limit_map_.findKey(inst, limit, exists); + findKeyValue(inst_latch_borrow_limit_map_, inst, limit, exists); if (!exists) - clk_latch_borrow_limit_map_.findKey(clk, limit, exists); + findKeyValue(clk_latch_borrow_limit_map_, clk, limit, exists); } } } @@ -2531,7 +2554,7 @@ Sdc::latchBorrowLimit(const Pin *data_pin, void Sdc::setMinPulseWidth(const RiseFallBoth *rf, - float min_width) + float min_width) { for (auto rf1 : rf->range()) min_pulse_width_.setValue(rf1, min_width); @@ -2539,10 +2562,10 @@ Sdc::setMinPulseWidth(const RiseFallBoth *rf, void Sdc::setMinPulseWidth(const Pin *pin, - const RiseFallBoth *rf, - float min_width) + const RiseFallBoth *rf, + float min_width) { - RiseFallValues *widths = pin_min_pulse_width_map_.findKey(pin); + RiseFallValues *widths = findKey(pin_min_pulse_width_map_, pin); if (widths == nullptr) { widths = new RiseFallValues; pin_min_pulse_width_map_[pin] = widths; @@ -2553,10 +2576,10 @@ Sdc::setMinPulseWidth(const Pin *pin, void Sdc::setMinPulseWidth(const Instance *inst, - const RiseFallBoth *rf, - float min_width) + const RiseFallBoth *rf, + float min_width) { - RiseFallValues *widths = inst_min_pulse_width_map_.findKey(inst); + RiseFallValues *widths = findKey(inst_min_pulse_width_map_, inst); if (widths == nullptr) { widths = new RiseFallValues; inst_min_pulse_width_map_[inst] = widths; @@ -2567,10 +2590,10 @@ Sdc::setMinPulseWidth(const Instance *inst, void Sdc::setMinPulseWidth(const Clock *clk, - const RiseFallBoth *rf, - float min_width) + const RiseFallBoth *rf, + float min_width) { - RiseFallValues *widths = clk_min_pulse_width_map_.findKey(clk); + RiseFallValues *widths = findKey(clk_min_pulse_width_map_, clk); if (widths == nullptr) { widths = new RiseFallValues; clk_min_pulse_width_map_[clk] = widths; @@ -2581,21 +2604,21 @@ Sdc::setMinPulseWidth(const Clock *clk, void Sdc::minPulseWidth(const Pin *pin, - const Clock *clk, - const RiseFall *hi_low, - float &min_width, - bool &exists) const + const Clock *clk, + const RiseFall *hi_low, + float &min_width, + bool &exists) const { - RiseFallValues *widths = pin_min_pulse_width_map_.findKey(pin); + RiseFallValues *widths = findKey(pin_min_pulse_width_map_, pin); if (widths) widths->value(hi_low, min_width, exists); else { if (pin) { const Instance *inst = network_->instance(pin); - widths = inst_min_pulse_width_map_.findKey(inst); + widths = findKey(inst_min_pulse_width_map_, inst); } if (widths == nullptr) - widths = clk_min_pulse_width_map_.findKey(clk); + widths = findKey(clk_min_pulse_width_map_, clk); if (widths) widths->value(hi_low, min_width, exists); else @@ -2606,7 +2629,7 @@ Sdc::minPulseWidth(const Pin *pin, void Sdc::deleteMinPulseWidthReferencing(Clock *clk) { - RiseFallValues *widths = clk_min_pulse_width_map_.findKey(clk); + RiseFallValues *widths = findKey(clk_min_pulse_width_map_, clk); if (widths) { delete widths; clk_min_pulse_width_map_.erase(clk); @@ -2616,22 +2639,22 @@ Sdc::deleteMinPulseWidthReferencing(Clock *clk) //////////////////////////////////////////////////////////////// InputDrive * -Sdc::findInputDrive(Port *port) +Sdc::findInputDrive(Port *port) const { - return input_drive_map_.findKey(port); + return findKey(input_drive_map_, port); } void Sdc::setInputDelay(const Pin *pin, - const RiseFallBoth *rf, - const Clock *clk, - const RiseFall *clk_rf, - const Pin *ref_pin, - bool source_latency_included, - bool network_latency_included, - const MinMaxAll *min_max, - bool add, - float delay) + const RiseFallBoth *rf, + const Clock *clk, + const RiseFall *clk_rf, + const Pin *ref_pin, + bool source_latency_included, + bool network_latency_included, + const MinMaxAll *min_max, + bool add, + float delay) { ClockEdge *clk_edge = clk ? clk->edge(clk_rf) : nullptr; InputDelay *input_delay = findInputDelay(pin, clk_edge); @@ -2648,7 +2671,7 @@ Sdc::setInputDelay(const Pin *pin, } if (ref_pin) { - InputDelaySet *ref_inputs = input_delay_ref_pin_map_.findKey(ref_pin); + InputDelaySet *ref_inputs = findKey(input_delay_ref_pin_map_, ref_pin); if (ref_inputs == nullptr) { ref_inputs = new InputDelaySet; input_delay_ref_pin_map_[ref_pin] = ref_inputs; @@ -2663,12 +2686,12 @@ Sdc::setInputDelay(const Pin *pin, InputDelay * Sdc::makeInputDelay(const Pin *pin, - const ClockEdge *clk_edge) + const ClockEdge *clk_edge) { InputDelay *input_delay = new InputDelay(pin, clk_edge, input_delay_index_++, - network_); + network_); input_delays_.insert(input_delay); - InputDelaySet *inputs = input_delay_pin_map_.findKey(pin); + InputDelaySet *inputs = findKey(input_delay_pin_map_, pin); if (inputs == nullptr) { inputs = new InputDelaySet; input_delay_pin_map_[pin] = inputs; @@ -2686,8 +2709,8 @@ Sdc::makeInputDelay(const Pin *pin, if (!network_->isTopLevelPort(lpin)) { InputDelaySet *internal_inputs = input_delay_internal_pin_map_[lpin]; if (internal_inputs == nullptr) { - internal_inputs = new InputDelaySet; - input_delay_internal_pin_map_[pin] = internal_inputs; + internal_inputs = new InputDelaySet; + input_delay_internal_pin_map_[pin] = internal_inputs; } internal_inputs->insert(input_delay); } @@ -2697,13 +2720,13 @@ Sdc::makeInputDelay(const Pin *pin, InputDelay * Sdc::findInputDelay(const Pin *pin, - const ClockEdge *clk_edge) + const ClockEdge *clk_edge) { - InputDelaySet *inputs = input_delay_pin_map_.findKey(pin); + InputDelaySet *inputs = findKey(input_delay_pin_map_, pin); if (inputs) { for (InputDelay *input_delay : *inputs) { if (input_delay->clkEdge() == clk_edge) - return input_delay; + return input_delay; } } return nullptr; @@ -2711,10 +2734,10 @@ Sdc::findInputDelay(const Pin *pin, void Sdc::removeInputDelay(const Pin *pin, - const RiseFallBoth *rf, - const Clock *clk, - const RiseFall *clk_rf, - const MinMaxAll *min_max) + const RiseFallBoth *rf, + const Clock *clk, + const RiseFall *clk_rf, + const MinMaxAll *min_max) { ClockEdge *clk_edge = clk ? clk->edge(clk_rf) : nullptr; InputDelay *input_delay = findInputDelay(pin, clk_edge); @@ -2728,50 +2751,56 @@ Sdc::removeInputDelay(const Pin *pin, void Sdc::deleteInputDelays(const Pin *pin, - InputDelay *except) + InputDelay *except) { InputDelaySet *input_delays = input_delay_pin_map_[pin]; - InputDelaySet::Iterator iter(input_delays); - while (iter.hasNext()) { - InputDelay *input_delay = iter.next(); - if (input_delay != except) + for (auto itr = input_delays->begin(); itr != input_delays->end(); /* no incr */) { + InputDelay *input_delay = *itr; + if (input_delay != except) { + itr = input_delays->erase(itr); deleteInputDelay(input_delay); + } + else + itr++; } } InputDelaySet * Sdc::refPinInputDelays(const Pin *ref_pin) const { - return input_delay_ref_pin_map_.findKey(ref_pin); + return findKey(input_delay_ref_pin_map_, ref_pin); } InputDelaySet * -Sdc::inputDelaysLeafPin(const Pin *leaf_pin) +Sdc::inputDelaysLeafPin(const Pin *leaf_pin) const { - return input_delay_leaf_pin_map_.findKey(leaf_pin); + return findKey(input_delay_leaf_pin_map_, leaf_pin); } bool Sdc::hasInputDelay(const Pin *leaf_pin) const { - InputDelaySet *input_delays = input_delay_leaf_pin_map_.findKey(leaf_pin); + InputDelaySet *input_delays = findKey(input_delay_leaf_pin_map_, leaf_pin); return input_delays && !input_delays->empty(); } bool Sdc::isInputDelayInternal(const Pin *pin) const { - return input_delay_internal_pin_map_.hasKey(pin); + return input_delay_internal_pin_map_.contains(pin); } void Sdc::deleteInputDelaysReferencing(const Clock *clk) { - InputDelaySet::Iterator iter(input_delays_); - while (iter.hasNext()) { - InputDelay *input_delay = iter.next(); - if (input_delay->clock() == clk) + for (auto itr = input_delays_.begin(); itr != input_delays_.end(); ) { + InputDelay *input_delay = *itr; + if (input_delay->clock() == clk) { + itr = input_delays_.erase(itr); deleteInputDelay(input_delay); + } + else + itr++; } } @@ -2813,15 +2842,15 @@ Sdc::swapPortDelays(Sdc *sdc1, void Sdc::setOutputDelay(const Pin *pin, - const RiseFallBoth *rf, - const Clock *clk, - const RiseFall *clk_rf, - const Pin *ref_pin, - bool source_latency_included, - bool network_latency_included, - const MinMaxAll *min_max, - bool add, - float delay) + const RiseFallBoth *rf, + const Clock *clk, + const RiseFall *clk_rf, + const Pin *ref_pin, + bool source_latency_included, + bool network_latency_included, + const MinMaxAll *min_max, + bool add, + float delay) { ClockEdge *clk_edge = clk ? clk->edge(clk_rf) : nullptr; OutputDelay *output_delay = findOutputDelay(pin, clk_edge); @@ -2838,7 +2867,7 @@ Sdc::setOutputDelay(const Pin *pin, } if (ref_pin) { - OutputDelaySet *ref_outputs = output_delay_ref_pin_map_.findKey(ref_pin); + OutputDelaySet *ref_outputs = findKey(output_delay_ref_pin_map_, ref_pin); if (ref_outputs == nullptr) { ref_outputs = new OutputDelaySet; output_delay_ref_pin_map_[ref_pin] = ref_outputs; @@ -2853,13 +2882,13 @@ Sdc::setOutputDelay(const Pin *pin, OutputDelay * Sdc::findOutputDelay(const Pin *pin, - const ClockEdge *clk_edge) + const ClockEdge *clk_edge) { - OutputDelaySet *outputs = output_delay_pin_map_.findKey(pin); + OutputDelaySet *outputs = findKey(output_delay_pin_map_, pin); if (outputs) { for (OutputDelay *output_delay : *outputs) { if (output_delay->clkEdge() == clk_edge) - return output_delay; + return output_delay; } } return nullptr; @@ -2867,11 +2896,11 @@ Sdc::findOutputDelay(const Pin *pin, OutputDelay * Sdc::makeOutputDelay(const Pin *pin, - const ClockEdge *clk_edge) + const ClockEdge *clk_edge) { OutputDelay *output_delay = new OutputDelay(pin, clk_edge, network_); output_delays_.insert(output_delay); - OutputDelaySet *outputs = output_delay_pin_map_.findKey(pin); + OutputDelaySet *outputs = findKey(output_delay_pin_map_, pin); if (outputs == nullptr) { outputs = new OutputDelaySet; output_delay_pin_map_[pin] = outputs; @@ -2891,10 +2920,10 @@ Sdc::makeOutputDelay(const Pin *pin, void Sdc::removeOutputDelay(const Pin *pin, - const RiseFallBoth *rf, - const Clock *clk, - const RiseFall *clk_rf, - const MinMaxAll *min_max) + const RiseFallBoth *rf, + const Clock *clk, + const RiseFall *clk_rf, + const MinMaxAll *min_max) { ClockEdge *clk_edge = clk ? clk->edge(clk_rf) : nullptr; OutputDelay *output_delay = findOutputDelay(pin, clk_edge); @@ -2906,37 +2935,43 @@ Sdc::removeOutputDelay(const Pin *pin, void Sdc::deleteOutputDelays(const Pin *pin, - OutputDelay *except) + OutputDelay *except) { OutputDelaySet *output_delays = output_delay_pin_map_[pin]; - OutputDelaySet::Iterator iter(output_delays); - while (iter.hasNext()) { - OutputDelay *output_delay = iter.next(); - if (output_delay != except) + for (auto itr = output_delays->begin(); itr != output_delays->end(); ) { + OutputDelay *output_delay = *itr; + if (output_delay != except) { + itr = output_delays->erase(itr); deleteOutputDelay(output_delay); + } + else + itr++; } } OutputDelaySet * -Sdc::outputDelaysLeafPin(const Pin *leaf_pin) +Sdc::outputDelaysLeafPin(const Pin *leaf_pin) const { - return output_delay_leaf_pin_map_.findKey(leaf_pin); + return findKey(output_delay_leaf_pin_map_, leaf_pin); } bool Sdc::hasOutputDelay(const Pin *leaf_pin) const { - return output_delay_leaf_pin_map_.hasKey(leaf_pin); + return output_delay_leaf_pin_map_.contains(leaf_pin); } void Sdc::deleteOutputDelaysReferencing(const Clock *clk) { - OutputDelaySet::Iterator iter(output_delays_); - while (iter.hasNext()) { - OutputDelay *output_delay = iter.next(); - if (output_delay->clock() == clk) + for (auto itr = output_delays_.begin(); itr != output_delays_.end(); ) { + OutputDelay *output_delay = *itr; + if (output_delay->clock() == clk) { + itr = output_delays_.erase(itr); deleteOutputDelay(output_delay); + } + else + itr++; } } @@ -2961,64 +2996,54 @@ Sdc::deleteOutputDelay(OutputDelay *output_delay) void Sdc::setPortExtPinCap(const Port *port, - const RiseFall *rf, - const Corner *corner, - const MinMax *min_max, - float cap) + const RiseFall *rf, + const MinMax *min_max, + float cap) { - PortExtCap *port_cap = ensurePortExtPinCap(port, corner); - port_cap->setPinCap(cap, rf, min_max); + PortExtCap &port_cap = port_ext_cap_map_[port]; + port_cap.setPinCap(port, cap, rf, min_max); } void Sdc::setPortExtWireCap(const Port *port, - bool subtract_pin_cap, - const RiseFall *rf, - const Corner *corner, - const MinMax *min_max, - float cap) + const RiseFall *rf, + const MinMax *min_max, + float cap) { - PortExtCap *port_cap = ensurePortExtPinCap(port, corner); - if (subtract_pin_cap) { - Pin *pin = network_->findPin(network_->name(port)); - cap -= connectedPinCap(pin, rf, corner, min_max); - if (cap < 0.0) - cap = 0.0; - } - port_cap->setWireCap(cap, rf, min_max); + PortExtCap &port_cap = port_ext_cap_map_[port]; + port_cap.setWireCap(port, cap, rf, min_max); } -PortExtCap * -Sdc::portExtCap(const Port *port, - const Corner *corner) const +const PortExtCap * +Sdc::portExtCap(const Port *port) const { - return port_ext_cap_maps_[corner->index()].findKey(port); + auto itr = port_ext_cap_map_.find(port); + if (itr != port_ext_cap_map_.end()) + return &itr->second; + else + return nullptr; } bool Sdc::hasPortExtCap(const Port *port) const { - for (int corner_index = 0; corner_index < corners_->count(); corner_index++) { - if (port_ext_cap_maps_[corner_index].hasKey(port)) - return true; - } - return false; + auto itr = port_ext_cap_map_.find(port); + return itr != port_ext_cap_map_.end(); } void Sdc::portExtCap(const Port *port, - const RiseFall *rf, - const Corner *corner, - const MinMax *min_max, - // Return values. - float &pin_cap, - bool &has_pin_cap, - float &wire_cap, - bool &has_wire_cap, - int &fanout, - bool &has_fanout) const + const RiseFall *rf, + const MinMax *min_max, + // Return values. + float &pin_cap, + bool &has_pin_cap, + float &wire_cap, + bool &has_wire_cap, + int &fanout, + bool &has_fanout) const { - PortExtCap *port_cap = port_ext_cap_maps_[corner->index()].findKey(port); + const PortExtCap *port_cap = portExtCap(port); if (port_cap) { port_cap->pinCap(rf, min_max, pin_cap, has_pin_cap); port_cap->wireCap(rf, min_max, wire_cap, has_wire_cap); @@ -3036,17 +3061,16 @@ Sdc::portExtCap(const Port *port, float Sdc::portExtCap(const Port *port, - const RiseFall *rf, - const Corner *corner, - const MinMax *min_max) const + const RiseFall *rf, + const MinMax *min_max) const { float pin_cap, wire_cap; int fanout; bool has_pin_cap, has_wire_cap, has_fanout; - portExtCap(port, rf, corner, min_max, - pin_cap, has_pin_cap, - wire_cap, has_wire_cap, - fanout, has_fanout); + portExtCap(port, rf, min_max, + pin_cap, has_pin_cap, + wire_cap, has_wire_cap, + fanout, has_fanout); float cap = 0.0; if (has_pin_cap) cap += pin_cap; @@ -3056,22 +3080,20 @@ Sdc::portExtCap(const Port *port, } bool -Sdc::drvrPinHasWireCap(const Pin *pin, - const Corner *corner) +Sdc::drvrPinHasWireCap(const Pin *pin) const { - return drvr_pin_wire_cap_maps_[corner->index()].hasKey(pin); + return drvr_pin_wire_cap_map_.contains(pin); } void Sdc::drvrPinWireCap(const Pin *pin, - const Corner *corner, - const MinMax *min_max, - // Return values. - float &cap, - bool &exists, + const MinMax *min_max, + // Return values. + float &cap, + bool &exists, bool &subtract_pin_cap) const { - NetWireCaps *net_caps = drvr_pin_wire_cap_maps_[corner->index()].findKey(pin); + NetWireCaps *net_caps = findKey(drvr_pin_wire_cap_map_, pin); if (net_caps) { net_caps->value(min_max, cap, exists); subtract_pin_cap = net_caps->subtractPinCap(min_max); @@ -3085,47 +3107,42 @@ Sdc::drvrPinWireCap(const Pin *pin, void Sdc::setNetWireCap(const Net *net, - bool subtract_pin_cap, - const Corner *corner, - const MinMax *min_max, - float wire_cap) + bool subtract_pin_cap, + const MinMax *min_max, + float wire_cap) { - NetWireCaps &net_caps = net_wire_cap_maps_[corner->index()][net]; + NetWireCaps &net_caps = net_wire_cap_map_[net]; net_caps.setValue(min_max, wire_cap); net_caps.setSubtractPinCap(subtract_pin_cap, min_max); for (const Pin *pin : *network_->drivers(net)) - drvr_pin_wire_cap_maps_[corner->index()][pin] = &net_caps; + drvr_pin_wire_cap_map_[pin] = &net_caps; } bool Sdc::hasNetWireCap(const Net *net) const { - for (int i = 0; i < corners_->count(); i++) { - if (net_wire_cap_maps_[i].hasKey(net)) - return true; - } - return false; + return net_wire_cap_map_.contains(net); } //////////////////////////////////////////////////////////////// void Sdc::connectedCap(const Pin *pin, - const RiseFall *rf, - const Corner *corner, - const MinMax *min_max, - // Return values. - float &pin_cap, - float &wire_cap, - float &fanout, + const RiseFall *rf, + const Scene *scene, + const MinMax *min_max, + // Return values. + float &pin_cap, + float &wire_cap, + float &fanout, bool &has_net_load) const { - netCaps(pin, rf, corner, min_max, pin_cap, wire_cap, fanout, has_net_load); + netCaps(pin, rf, scene, min_max, pin_cap, wire_cap, fanout, has_net_load); float net_wire_cap; bool subtract_pin_cap; - drvrPinWireCap(pin, corner, min_max, net_wire_cap, has_net_load, subtract_pin_cap); + drvrPinWireCap(pin, min_max, net_wire_cap, has_net_load, subtract_pin_cap); if (subtract_pin_cap) pin_cap = 0.0; if (has_net_load) @@ -3134,14 +3151,14 @@ Sdc::connectedCap(const Pin *pin, float Sdc::connectedPinCap(const Pin *pin, - const RiseFall *rf, - const Corner *corner, - const MinMax *min_max) + const RiseFall *rf, + const Scene *scene, + const MinMax *min_max) { float pin_cap, wire_cap, fanout; bool has_net_load; - connectedCap(pin, rf, corner, min_max, - pin_cap, wire_cap, fanout, has_net_load); + connectedCap(pin, rf, scene, min_max, + pin_cap, wire_cap, fanout, has_net_load); return pin_cap; } @@ -3149,18 +3166,18 @@ class FindNetCaps : public PinVisitor { public: FindNetCaps(const RiseFall *rf, - const Corner *corner, - const MinMax *min_max, - float &pin_cap, - float &wire_cap, - float &fanout, - bool &has_net_load, - const Sdc *sdc); + const Scene *scene, + const MinMax *min_max, + float &pin_cap, + float &wire_cap, + float &fanout, + bool &has_net_load, + const Sdc *sdc); virtual void operator()(const Pin *pin); protected: const RiseFall *rf_; - const Corner *corner_; + const Scene *scene_; const MinMax *min_max_; float &pin_cap_; float &wire_cap_; @@ -3170,16 +3187,16 @@ protected: }; FindNetCaps::FindNetCaps(const RiseFall *rf, - const Corner *corner, - const MinMax *min_max, - float &pin_cap, - float &wire_cap, - float &fanout, - bool &has_net_load, - const Sdc *sdc) : + const Scene *scene, + const MinMax *min_max, + float &pin_cap, + float &wire_cap, + float &fanout, + bool &has_net_load, + const Sdc *sdc) : PinVisitor(), rf_(rf), - corner_(corner), + scene_(scene), min_max_(min_max), pin_cap_(pin_cap), wire_cap_(wire_cap), @@ -3192,40 +3209,40 @@ FindNetCaps::FindNetCaps(const RiseFall *rf, void FindNetCaps::operator()(const Pin *pin) { - sdc_->pinCaps(pin, rf_, corner_, min_max_, - pin_cap_, wire_cap_, fanout_); + sdc_->pinCaps(pin, rf_, scene_, min_max_, + pin_cap_, wire_cap_, fanout_); } // Capacitances for all pins connected to drvr_pin's net. void Sdc::netCaps(const Pin *drvr_pin, - const RiseFall *rf, - const Corner *corner, - const MinMax *min_max, - // Return values. - float &pin_cap, - float &wire_cap, - float &fanout, + const RiseFall *rf, + const Scene *scene, + const MinMax *min_max, + // Return values. + float &pin_cap, + float &wire_cap, + float &fanout, bool &has_net_load) const { pin_cap = 0.0; wire_cap = 0.0; fanout = 0.0; has_net_load = false; - FindNetCaps visitor(rf, corner, min_max, pin_cap, - wire_cap, fanout, has_net_load, this); + FindNetCaps visitor(rf, scene, min_max, pin_cap, + wire_cap, fanout, has_net_load, this); network_->visitConnectedPins(drvr_pin, visitor); } void Sdc::pinCaps(const Pin *pin, - const RiseFall *rf, - const Corner *corner, - const MinMax *min_max, - // Return values. - float &pin_cap, - float &wire_cap, - float &fanout) const + const RiseFall *rf, + const Scene *scene, + const MinMax *min_max, + // Return values. + float &pin_cap, + float &wire_cap, + float &fanout) const { if (network_->isTopLevelPort(pin)) { Port *port = network_->port(pin); @@ -3233,17 +3250,17 @@ Sdc::pinCaps(const Pin *pin, float port_pin_cap, port_wire_cap; int port_fanout; bool has_pin_cap, has_wire_cap, has_fanout; - portExtCap(port, rf, corner, min_max, - port_pin_cap, has_pin_cap, - port_wire_cap, has_wire_cap, - port_fanout, has_fanout); + portExtCap(port, rf, min_max, + port_pin_cap, has_pin_cap, + port_wire_cap, has_wire_cap, + port_fanout, has_fanout); if (has_pin_cap) pin_cap += port_pin_cap; if (has_wire_cap) wire_cap += port_wire_cap; if (is_output) { if (has_fanout) - fanout += port_fanout; + fanout += port_fanout; // Output port counts as a fanout. fanout++; } @@ -3252,38 +3269,40 @@ Sdc::pinCaps(const Pin *pin, LibertyPort *port = network_->libertyPort(pin); if (port) { Instance *inst = network_->instance(pin); - pin_cap += portCapacitance(inst, port, rf, corner, min_max); + pin_cap += portCapacitance(inst, port, rf, scene, min_max); if (port->direction()->isAnyInput()) - fanout++; + fanout++; } } } float Sdc::portCapacitance(Instance *inst, - LibertyPort *port, - const RiseFall *rf, - const Corner *corner, - const MinMax *min_max) const + LibertyPort *port, + const RiseFall *rf, + const Scene *scene, + const MinMax *min_max) const { const Pvt *inst_pvt = nullptr; if (inst) inst_pvt = pvt(inst, min_max); - LibertyPort *corner_port = port->cornerPort(corner, min_max); + LibertyPort *scene_port = port->scenePort(scene, min_max); + if (scene_port == nullptr) + scene_port = port; OperatingConditions *op_cond = operatingConditions(min_max); - return corner_port->capacitance(rf, min_max, op_cond, inst_pvt); + return scene_port->capacitance(rf, min_max, op_cond, inst_pvt); } float Sdc::pinCapacitance(const Pin *pin, - const RiseFall *rf, - const Corner *corner, - const MinMax *min_max) + const RiseFall *rf, + const Scene *scene, + const MinMax *min_max) const { LibertyPort *port = network_->libertyPort(pin); if (port) { Instance *inst = network_->instance(pin); - return portCapacitance(inst, port, rf, corner, min_max); + return portCapacitance(inst, port, rf, scene, min_max); } else return 0.0; @@ -3293,8 +3312,8 @@ Sdc::pinCapacitance(const Pin *pin, void Sdc::setResistance(const Net *net, - const MinMaxAll *min_max, - float res) + const MinMaxAll *min_max, + float res) { MinMaxFloatValues &values = net_res_map_[net]; values.setValue(min_max, res); @@ -3302,36 +3321,34 @@ Sdc::setResistance(const Net *net, void Sdc::resistance(const Net *net, - const MinMax *min_max, - float &res, - bool &exists) + const MinMax *min_max, + float &res, + bool &exists) const { res = 0.0; MinMaxFloatValues values; - net_res_map_.findKey(net, values, exists); + findKeyValue(net_res_map_, net, values, exists); if (exists) values.value(min_max, res, exists); } void Sdc::setPortExtFanout(const Port *port, - const Corner *corner, - const MinMax *min_max, - int fanout) + const MinMax *min_max, + int fanout) { - PortExtCap *port_cap = ensurePortExtPinCap(port, corner); - port_cap->setFanout(fanout, min_max); + PortExtCap &port_cap = port_ext_cap_map_[port]; + port_cap.setFanout(port, fanout, min_max); } void Sdc::portExtFanout(const Port *port, - const Corner *corner, - const MinMax *min_max, - // Return values. - int &fanout, - bool &exists) + const MinMax *min_max, + // Return values. + int &fanout, + bool &exists) const { - PortExtCap *port_cap = portExtCap(port, corner); + const PortExtCap *port_cap = portExtCap(port); if (port_cap) port_cap->fanout(min_max, fanout, exists); else { @@ -3342,95 +3359,62 @@ Sdc::portExtFanout(const Port *port, int Sdc::portExtFanout(Port *port, - const Corner *corner, - const MinMax *min_max) + const MinMax *min_max) const { int fanout; bool exists; - portExtFanout(port, corner, min_max, fanout, exists); + portExtFanout(port, min_max, fanout, exists); if (exists) return fanout; else return 0.0; } -PortExtCap * -Sdc::ensurePortExtPinCap(const Port *port, - const Corner *corner) -{ - PortExtCap *port_cap = port_ext_cap_maps_[corner->index()].findKey(port); - if (port_cap == nullptr) { - port_cap = new PortExtCap(port); - port_ext_cap_maps_[corner->index()][port] = port_cap; - } - return port_cap; -} - void Sdc::swapPortExtCaps(Sdc *sdc1, Sdc *sdc2) { - for (int corner_index = 0; corner_index < sdc1->corners()->count(); corner_index++) { - swap(sdc1->port_ext_cap_maps_[corner_index], sdc2->port_ext_cap_maps_[corner_index]); - swap(sdc1->net_wire_cap_maps_[corner_index], sdc2->net_wire_cap_maps_[corner_index]); - } + swap(sdc1->port_ext_cap_map_, sdc2->port_ext_cap_map_); + swap(sdc1->net_wire_cap_map_, sdc2->net_wire_cap_map_); } //////////////////////////////////////////////////////////////// void Sdc::disable(LibertyCell *cell, - LibertyPort *from, - LibertyPort *to) + LibertyPort *from, + LibertyPort *to) { - DisabledCellPorts *disabled_cell = disabled_cell_ports_.findKey(cell); + DisabledCellPorts *disabled_cell = findKey(disabled_cell_ports_, cell); if (disabled_cell == nullptr) { disabled_cell = new DisabledCellPorts(cell); disabled_cell_ports_[cell] = disabled_cell; } - if (from && to) { + if (from && to) disabled_cell->setDisabledFromTo(from, to); - for (TimingArcSet *arc_set : cell->timingArcSets(from, to)) - arc_set->setIsDisabledConstraint(true); - } - else if (from) { + else if (from) disabled_cell->setDisabledFrom(from); - from->setIsDisabledConstraint(true); - } - else if (to) { + else if (to) disabled_cell->setDisabledTo(to); - to->setIsDisabledConstraint(true); - } - else { + else disabled_cell->setDisabledAll(); - cell->setIsDisabledConstraint(true); - } } void Sdc::removeDisable(LibertyCell *cell, - LibertyPort *from, - LibertyPort *to) + LibertyPort *from, + LibertyPort *to) { - DisabledCellPorts *disabled_cell = disabled_cell_ports_.findKey(cell); + DisabledCellPorts *disabled_cell = findKey(disabled_cell_ports_, cell); if (disabled_cell) { - if (from && to) { + if (from && to) disabled_cell->removeDisabledFromTo(from, to); - for (TimingArcSet *arc_set : cell->timingArcSets(from, to)) - arc_set->setIsDisabledConstraint(false); - } - else if (from) { + else if (from) disabled_cell->removeDisabledFrom(from); - from->setIsDisabledConstraint(false); - } - else if (to) { + else if (to) disabled_cell->removeDisabledTo(to); - to->setIsDisabledConstraint(false); - } - else { + else disabled_cell->removeDisabledAll(); - cell->setIsDisabledConstraint(false); - } } } @@ -3438,38 +3422,33 @@ void Sdc::disable(TimingArcSet *arc_set) { LibertyCell *cell = arc_set->libertyCell(); - DisabledCellPorts *disabled_cell = disabled_cell_ports_.findKey(cell); + DisabledCellPorts *disabled_cell = findKey(disabled_cell_ports_, cell); if (disabled_cell == nullptr) { disabled_cell = new DisabledCellPorts(cell); disabled_cell_ports_[cell] = disabled_cell; } disabled_cell->setDisabled(arc_set); - arc_set->setIsDisabledConstraint(true); } void Sdc::removeDisable(TimingArcSet *arc_set) { LibertyCell *cell = arc_set->libertyCell(); - DisabledCellPorts *disabled_cell = disabled_cell_ports_.findKey(cell); - if (disabled_cell) { + DisabledCellPorts *disabled_cell = findKey(disabled_cell_ports_, cell); + if (disabled_cell) disabled_cell->removeDisabled(arc_set); - arc_set->setIsDisabledConstraint(false); - } } void Sdc::disable(LibertyPort *port) { disabled_lib_ports_.insert(port); - port->setIsDisabledConstraint(true); } void Sdc::removeDisable(LibertyPort *port) { disabled_lib_ports_.erase(port); - port->setIsDisabledConstraint(false); } void @@ -3486,10 +3465,10 @@ Sdc::removeDisable(Port *port) void Sdc::disable(Instance *inst, - LibertyPort *from, - LibertyPort *to) + LibertyPort *from, + LibertyPort *to) { - DisabledInstancePorts *disabled_inst = disabled_inst_ports_.findKey(inst); + DisabledInstancePorts *disabled_inst = findKey(disabled_inst_ports_, inst); if (disabled_inst == nullptr) { disabled_inst = new DisabledInstancePorts(inst); disabled_inst_ports_[inst] = disabled_inst; @@ -3506,10 +3485,10 @@ Sdc::disable(Instance *inst, void Sdc::removeDisable(Instance *inst, - LibertyPort *from, - LibertyPort *to) + LibertyPort *from, + LibertyPort *to) { - DisabledInstancePorts *disabled_inst = disabled_inst_ports_.findKey(inst); + DisabledInstancePorts *disabled_inst = findKey(disabled_inst_ports_, inst); if (disabled_inst) { if (from && to) disabled_inst->removeDisabledFromTo(from, to); @@ -3523,57 +3502,76 @@ Sdc::removeDisable(Instance *inst, } void -Sdc::disable(Pin *from, - Pin *to) +Sdc::disableWire(const Pin *from, + const Pin *to) { PinPair pair(from, to); disabled_wire_edges_.insert(pair); } void -Sdc::removeDisable(Pin *from, - Pin *to) +Sdc::removeDisableWire(Pin *from, + Pin *to) { PinPair probe(from, to); disabled_wire_edges_.erase(probe); } +bool +Sdc::isDisabledWire(const Pin *from, + const Pin *to) const +{ + PinPair pair(from, to); + return disabled_wire_edges_.contains(pair); +} + void Sdc::disable(Edge *edge) { disabled_edges_.insert(edge); - edge->setIsDisabledConstraint(true); } void Sdc::removeDisable(Edge *edge) { disabled_edges_.erase(edge); - edge->setIsDisabledConstraint(false); } bool -Sdc::isDisabled(Edge *edge) +Sdc::isDisabled(const Edge *edge) const { - return disabled_edges_.hasKey(edge); + return disabled_edges_.contains(const_cast(edge)); +} + +bool +Sdc::isDisabledConstraint(const Edge *edge) const +{ + Pin *from_pin = edge->from(graph_)->pin(); + Pin *to_pin = edge->to(graph_)->pin(); + const Instance *inst = network_->instance(from_pin); + TimingArcSet *arc_set = edge->timingArcSet(); + return isDisabled(inst, from_pin, to_pin, edge->role()) + || isDisabled(edge) + || isDisabledWire(from_pin, to_pin) + || isDisabled(arc_set); } class DisableEdgesThruHierPin : public HierPinThruVisitor { public: DisableEdgesThruHierPin(PinPairSet *pairs, - Graph *graph); + Graph *graph); protected: virtual void visit(const Pin *drvr, - const Pin *load); + const Pin *load); PinPairSet *pairs_; Graph *graph_; }; DisableEdgesThruHierPin::DisableEdgesThruHierPin(PinPairSet *pairs, - Graph *graph) : + Graph *graph) : HierPinThruVisitor(), pairs_(pairs), graph_(graph) @@ -3582,7 +3580,7 @@ DisableEdgesThruHierPin::DisableEdgesThruHierPin(PinPairSet *pairs, void DisableEdgesThruHierPin::visit(const Pin *drvr, - const Pin *load) + const Pin *load) { PinPair pair(drvr, load); pairs_->insert(pair); @@ -3604,7 +3602,7 @@ class RemoveDisableEdgesThruHierPin : public HierPinThruVisitor { public: RemoveDisableEdgesThruHierPin(PinPairSet *pairs, - Graph *graph); + Graph *graph); protected: virtual void visit(const Pin *drvr, @@ -3615,7 +3613,7 @@ protected: }; RemoveDisableEdgesThruHierPin::RemoveDisableEdgesThruHierPin(PinPairSet *pairs, - Graph *graph) : + Graph *graph) : HierPinThruVisitor(), pairs_(pairs), graph_(graph) @@ -3624,7 +3622,7 @@ RemoveDisableEdgesThruHierPin::RemoveDisableEdgesThruHierPin(PinPairSet *pairs, void RemoveDisableEdgesThruHierPin::visit(const Pin *drvr, - const Pin *load) + const Pin *load) { PinPair pair(drvr, load); pairs_->erase(pair); @@ -3643,36 +3641,36 @@ Sdc::removeDisable(Pin *pin) } bool -Sdc::isDisabled(const Pin *pin) const +Sdc::isDisabledConstraint(const Pin *pin) const { Port *port = network_->port(pin); LibertyPort *lib_port = network_->libertyPort(pin); - return disabled_pins_.hasKey(pin) - || disabled_ports_.hasKey(port) - || disabled_lib_ports_.hasKey(lib_port); + return disabled_pins_.contains(pin) + || disabled_ports_.contains(port) + || disabled_lib_ports_.contains(lib_port); } bool Sdc::isDisabled(const Instance *inst, - const Pin *from_pin, - const Pin *to_pin, - const TimingRole *role) const + const Pin *from_pin, + const Pin *to_pin, + const TimingRole *role) const { if (role == TimingRole::wire()) { // Hierarchical thru pin disables. PinPair pair(from_pin, to_pin); - return disabled_wire_edges_.hasKey(pair); + return disabled_wire_edges_.contains(pair); } else { LibertyCell *cell = network_->libertyCell(inst); LibertyPort *from_port = network_->libertyPort(from_pin); LibertyPort *to_port = network_->libertyPort(to_pin); - DisabledInstancePorts *disabled_inst = disabled_inst_ports_.findKey(inst); - DisabledCellPorts *disabled_cell = disabled_cell_ports_.findKey(cell); + DisabledInstancePorts *disabled_inst = findKey(disabled_inst_ports_, inst); + DisabledCellPorts *disabled_cell = findKey(disabled_cell_ports_, cell); return (disabled_inst - && disabled_inst->isDisabled(from_port, to_port, role)) + && disabled_inst->isDisabled(from_port, to_port, role)) || (disabled_cell - && disabled_cell->isDisabled(from_port, to_port, role)); + && disabled_cell->isDisabled(from_port, to_port, role)); } } @@ -3681,7 +3679,7 @@ Sdc::isDisabled(TimingArcSet *arc_set) const { LibertyCell *cell = arc_set->libertyCell(); if (cell) { - DisabledCellPorts *disabled_cell = disabled_cell_ports_.findKey(cell); + DisabledCellPorts *disabled_cell = findKey(disabled_cell_ports_, cell); return disabled_cell && disabled_cell->isDisabled(arc_set); } @@ -3695,12 +3693,26 @@ Sdc::disabledInstancePorts() const return &disabled_inst_ports_; } -DisabledCellPortsMap * -Sdc::disabledCellPorts() +const DisabledCellPortsMap * +Sdc::disabledCellPorts() const { return &disabled_cell_ports_; } +//////////////////////////////////////////////////////////////// + +bool +Sdc::isConstrainedEnd(const Pin *pin) const +{ + // All output pins are considered constrained because + // they may be downstream from a set_min/max_delay -from that + // does not have a set_output_delay. + return (network_->isTopLevelPort(pin) + && network_->direction(pin)->isAnyOutput()) + || output_delay_leaf_pin_map_.contains(pin) + || data_checks_to_map_.contains(pin); +} + void Sdc::disableClockGatingCheck(Instance *inst) { @@ -3726,15 +3738,15 @@ Sdc::removeDisableClockGatingCheck(Pin *pin) } bool -Sdc::isDisableClockGatingCheck(const Instance *inst) +Sdc::isDisableClockGatingCheck(const Instance *inst) const { - return disabled_clk_gating_checks_inst_.hasKey(inst); + return disabled_clk_gating_checks_inst_.contains(inst); } bool -Sdc::isDisableClockGatingCheck(const Pin *pin) +Sdc::isDisableClockGatingCheck(const Pin *pin) const { - return disabled_clk_gating_checks_pin_.hasKey(pin); + return disabled_clk_gating_checks_pin_.contains(pin); } //////////////////////////////////////////////////////////////// @@ -3748,15 +3760,15 @@ Sdc::setLogicValue(const Pin *pin, void Sdc::logicValue(const Pin *pin, - LogicValue &value, - bool &exists) + LogicValue &value, + bool &exists) const { - logic_value_map_.findKey(pin, value, exists); + findKeyValue(logic_value_map_, pin, value, exists); } void Sdc::setCaseAnalysis(const Pin *pin, - LogicValue value) + LogicValue value) { case_value_map_[pin] = value; } @@ -3769,26 +3781,26 @@ Sdc::removeCaseAnalysis(const Pin *pin) void Sdc::caseLogicValue(const Pin *pin, - LogicValue &value, - bool &exists) + LogicValue &value, + bool &exists) const { - case_value_map_.findKey(pin, value, exists); + findKeyValue(case_value_map_, pin, value, exists); } bool -Sdc::hasLogicValue(const Pin *pin) +Sdc::hasLogicValue(const Pin *pin) const { - return case_value_map_.hasKey(pin) - || logic_value_map_.hasKey(pin); + return case_value_map_.contains(pin) + || logic_value_map_.contains(pin); } //////////////////////////////////////////////////////////////// ExceptionFrom * Sdc::makeExceptionFrom(PinSet *from_pins, - ClockSet *from_clks, - InstanceSet *from_insts, - const RiseFallBoth *from_rf) + ClockSet *from_clks, + InstanceSet *from_insts, + const RiseFallBoth *from_rf) const { if ((from_pins && !from_pins->empty()) || (from_clks && !from_clks->empty()) @@ -3817,9 +3829,9 @@ Sdc::isExceptionStartpoint(const Pin *pin) const ExceptionThru * Sdc::makeExceptionThru(PinSet *pins, - NetSet *nets, - InstanceSet *insts, - const RiseFallBoth *rf) + NetSet *nets, + InstanceSet *insts, + const RiseFallBoth *rf) const { if ((pins && !pins->empty()) || (nets && !nets->empty()) @@ -3831,10 +3843,10 @@ Sdc::makeExceptionThru(PinSet *pins, ExceptionTo * Sdc::makeExceptionTo(PinSet *pins, - ClockSet *clks, - InstanceSet *insts, - const RiseFallBoth *rf, - const RiseFallBoth *end_rf) + ClockSet *clks, + InstanceSet *insts, + const RiseFallBoth *rf, + const RiseFallBoth *end_rf) const { if ((pins && !pins->empty()) || (clks && !clks->empty()) @@ -3849,7 +3861,7 @@ Sdc::makeExceptionTo(PinSet *pins, // Valid endpoints include gated clock enables which are not // known until clock arrivals are determined. bool -Sdc::isExceptionEndpoint(const Pin *pin) +Sdc::isExceptionEndpoint(const Pin *pin) const { Net *net = network_->net(pin); bool has_checks = false; @@ -3860,7 +3872,7 @@ Sdc::isExceptionEndpoint(const Pin *pin) LibertyCell *cell = port->libertyCell(); for (TimingArcSet *arc_set : cell->timingArcSets(nullptr, port)) { if (arc_set->role()->isTimingCheck()) { - has_checks = true; + has_checks = true; break; } } @@ -3876,49 +3888,51 @@ Sdc::isExceptionEndpoint(const Pin *pin) && !network_->isHierarchical(pin); } +//////////////////////////////////////////////////////////////// + void Sdc::makeFalsePath(ExceptionFrom *from, - ExceptionThruSeq *thrus, - ExceptionTo *to, - const MinMaxAll *min_max, - const char *comment) + ExceptionThruSeq *thrus, + ExceptionTo *to, + const MinMaxAll *min_max, + const char *comment) { checkFromThrusTo(from, thrus, to); FalsePath *exception = new FalsePath(from, thrus, to, min_max, true, - comment); + comment); addException(exception); } void Sdc::makeMulticyclePath(ExceptionFrom *from, - ExceptionThruSeq *thrus, - ExceptionTo *to, - const MinMaxAll *min_max, - bool use_end_clk, - int path_multiplier, - const char *comment) + ExceptionThruSeq *thrus, + ExceptionTo *to, + const MinMaxAll *min_max, + bool use_end_clk, + int path_multiplier, + const char *comment) { checkFromThrusTo(from, thrus, to); MultiCyclePath *exception = new MultiCyclePath(from, thrus, to, - min_max, use_end_clk, - path_multiplier, true, - comment); + min_max, use_end_clk, + path_multiplier, true, + comment); addException(exception); } void Sdc::makePathDelay(ExceptionFrom *from, - ExceptionThruSeq *thrus, - ExceptionTo *to, - const MinMax *min_max, - bool ignore_clk_latency, + ExceptionThruSeq *thrus, + ExceptionTo *to, + const MinMax *min_max, + bool ignore_clk_latency, bool break_path, - float delay, - const char *comment) + float delay, + const char *comment) { checkFromThrusTo(from, thrus, to); PathDelay *exception = new PathDelay(from, thrus, to, min_max, - ignore_clk_latency, break_path, + ignore_clk_latency, break_path, delay, true, comment); addException(exception); } @@ -3931,7 +3945,7 @@ Sdc::recordPathDelayInternalFrom(ExceptionPath *exception) && from->hasPins()) { for (const Pin *pin : *from->pins()) { if (!isExceptionStartpoint(pin)) { - path_delay_internal_from_.insert(pin); + path_delay_internal_from_.insert(pin); if (exception->breakPath()) path_delay_internal_from_break_.insert(pin); } @@ -3948,8 +3962,8 @@ Sdc::unrecordPathDelayInternalFrom(ExceptionPath *exception) && !path_delay_internal_from_.empty()) { for (const Pin *pin : *from->pins()) { if (!isExceptionStartpoint(pin) - && !pathDelayFrom(pin)) { - path_delay_internal_from_.erase(pin); + && !pathDelayFrom(pin)) { + path_delay_internal_from_.erase(pin); if (exception->breakPath()) path_delay_internal_from_break_.erase(pin); } @@ -3957,28 +3971,14 @@ Sdc::unrecordPathDelayInternalFrom(ExceptionPath *exception) } } -template -const ExceptionPathSet * -findExceptions(const UnorderedMap &map, - const OBJ *obj) -{ - const auto itr = map.find(obj); - if (itr != map.end()) - return &itr->second; - else - return nullptr; -} - bool Sdc::pathDelayFrom(const Pin *pin) { - - const ExceptionPathSet *exceptions = - findExceptions(first_from_pin_exceptions_, pin); + const ExceptionPathSet *exceptions = findKeyValuePtr(first_from_pin_exceptions_, pin); if (exceptions) { for (ExceptionPath *exception : *exceptions) { if (exception->isPathDelay()) - return true; + return true; } } return false; @@ -3987,13 +3987,13 @@ Sdc::pathDelayFrom(const Pin *pin) bool Sdc::isPathDelayInternalFrom(const Pin *pin) const { - return path_delay_internal_from_.hasKey(pin); + return path_delay_internal_from_.contains(pin); } bool Sdc::isPathDelayInternalFromBreak(const Pin *pin) const { - return path_delay_internal_from_break_.hasKey(pin); + return path_delay_internal_from_break_.contains(pin); } const PinSet & @@ -4010,8 +4010,8 @@ Sdc::recordPathDelayInternalTo(ExceptionPath *exception) && to->hasPins()) { for (const Pin *pin : *to->pins()) { if (!(hasLibertyCheckTo(pin) - || network_->isTopLevelPort(pin))) { - path_delay_internal_to_.insert(pin); + || network_->isTopLevelPort(pin))) { + path_delay_internal_to_.insert(pin); if (exception->breakPath()) path_delay_internal_to_break_.insert(pin); } @@ -4028,9 +4028,9 @@ Sdc::unrecordPathDelayInternalTo(ExceptionPath *exception) && !path_delay_internal_to_.empty()) { for (const Pin *pin : *to->pins()) { if (!(hasLibertyCheckTo(pin) - || network_->isTopLevelPort(pin)) - && !pathDelayTo(pin)) { - path_delay_internal_to_.erase(pin); + || network_->isTopLevelPort(pin)) + && !pathDelayTo(pin)) { + path_delay_internal_to_.erase(pin); if (exception->breakPath()) path_delay_internal_to_break_.erase(pin); } @@ -4047,8 +4047,8 @@ Sdc::hasLibertyCheckTo(const Pin *pin) LibertyPort *port = network_->libertyPort(pin); if (port) { for (TimingArcSet *arc_set : cell->timingArcSets(nullptr, port)) { - if (arc_set->role()->isTimingCheckBetween()) - return true; + if (arc_set->role()->isTimingCheckBetween()) + return true; } } } @@ -4058,12 +4058,11 @@ Sdc::hasLibertyCheckTo(const Pin *pin) bool Sdc::pathDelayTo(const Pin *pin) { - const ExceptionPathSet *exceptions = - findExceptions(first_to_pin_exceptions_, pin); + const ExceptionPathSet *exceptions = findKeyValuePtr(first_to_pin_exceptions_, pin); if (exceptions) { for (ExceptionPath *exception : *exceptions) { if (exception->isPathDelay()) - return true; + return true; } } return false; @@ -4072,13 +4071,13 @@ Sdc::pathDelayTo(const Pin *pin) bool Sdc::isPathDelayInternalTo(const Pin *pin) const { - return path_delay_internal_to_.hasKey(pin); + return path_delay_internal_to_.contains(pin); } bool Sdc::isPathDelayInternalToBreak(const Pin *pin) const { - return path_delay_internal_to_break_.hasKey(pin); + return path_delay_internal_to_break_.contains(pin); } //////////////////////////////////////////////////////////////// @@ -4090,7 +4089,7 @@ Sdc::clearGroupPathMap() // Delete group_path name strings. for (auto [name, groups] : group_path_map_) { stringDelete(name); - groups->deleteContents(); + deleteContents(*groups); delete groups; } group_path_map_.clear(); @@ -4098,18 +4097,18 @@ Sdc::clearGroupPathMap() void Sdc::makeGroupPath(const char *name, - bool is_default, - ExceptionFrom *from, - ExceptionThruSeq *thrus, - ExceptionTo *to, - const char *comment) + bool is_default, + ExceptionFrom *from, + ExceptionThruSeq *thrus, + ExceptionTo *to, + const char *comment) { checkFromThrusTo(from, thrus, to); if (name && is_default) report_->critical(1490, "group path name and is_default are mutually exclusive."); else if (name) { GroupPath *group_path = new GroupPath(name, is_default, from, thrus, to, - true, comment); + true, comment); // Clone the group_path because it may get merged and hence deleted // by addException. ExceptionFrom *from1 = group_path->from() @@ -4119,12 +4118,12 @@ Sdc::makeGroupPath(const char *name, ExceptionPath *clone = group_path->clone(from1, thrus1, to1, true); addException(clone); // A named group path can have multiple exceptions. - GroupPathSet *groups = group_path_map_.findKey(name); + GroupPathSet *groups = findKey(group_path_map_, name); if (groups == nullptr) { groups = new GroupPathSet(network_); group_path_map_[stringCopy(name)] = groups; } - if (groups->hasKey(group_path)) + if (groups->contains(group_path)) // Exact copy of existing group path. delete group_path; else @@ -4133,23 +4132,23 @@ Sdc::makeGroupPath(const char *name, else { // is_default GroupPath *group_path = new GroupPath(name, is_default, from, thrus, to, - true, comment); + true, comment); addException(group_path); } } bool -Sdc::isGroupPathName(const char *group_name) +Sdc::isGroupPathName(const char *group_name) const { - return group_path_map_.hasKey(group_name); + return group_path_map_.contains(group_name); } //////////////////////////////////////////////////////////////// FilterPath * Sdc::makeFilterPath(ExceptionFrom *from, - ExceptionThruSeq *thrus, - ExceptionTo *to) + ExceptionThruSeq *thrus, + ExceptionTo *to) { checkFromThrusTo(from, thrus, to); FilterPath *exception = new FilterPath(from, thrus, to, true); @@ -4159,6 +4158,22 @@ Sdc::makeFilterPath(ExceptionFrom *from, return exception; } +void +Sdc::makeFilter(ExceptionFrom *from, + ExceptionThruSeq *thrus) +{ + filter_ = makeFilterPath(from, thrus, nullptr); +} + +void +Sdc::deleteFilter() +{ + if (filter_) { + deleteException(filter_); + filter_ = nullptr; + } +} + //////////////////////////////////////////////////////////////// void @@ -4184,10 +4199,10 @@ Sdc::makeLoopExceptions(GraphLoop *loop) while (in_edge_iter.hasNext()) { Edge *in_edge = in_edge_iter.next(); if (in_edge != edge) { - Pin *loop_input_pin = in_edge->from(graph_)->pin(); - makeLoopException(loop_input_pin, to_pin, from_pin); - // Prevent sub-loops by blocking paths on the main loop also. - makeLoopException(from_pin, to_pin, loop_input_pin); + Pin *loop_input_pin = in_edge->from(graph_)->pin(); + makeLoopException(loop_input_pin, to_pin, from_pin); + // Prevent sub-loops by blocking paths on the main loop also. + makeLoopException(from_pin, to_pin, loop_input_pin); } } } @@ -4195,8 +4210,8 @@ Sdc::makeLoopExceptions(GraphLoop *loop) void Sdc::makeLoopException(const Pin *loop_input_pin, - const Pin *loop_pin, - const Pin *loop_prev_pin) + const Pin *loop_pin, + const Pin *loop_prev_pin) { ExceptionThruSeq *thrus = new ExceptionThruSeq; makeLoopExceptionThru(loop_input_pin, thrus); @@ -4215,13 +4230,13 @@ Sdc::makeLoopPath(ExceptionThruSeq *thrus) void Sdc::makeLoopExceptionThru(const Pin *pin, - ExceptionThruSeq *thrus) + ExceptionThruSeq *thrus) { debugPrint(debug_, "levelize", 2, " %s", network_->pathName(pin)); PinSet *pins = new PinSet(network_); pins->insert(pin); ExceptionThru *thru = makeExceptionThru(pins, nullptr, nullptr, - RiseFallBoth::riseFall()); + RiseFallBoth::riseFall()); thrus->push_back(thru); } @@ -4268,7 +4283,7 @@ Sdc::addException(ExceptionPath *exception) InstanceSet *insts1 = from->instances() ? new InstanceSet(*from->instances()) : nullptr; ExceptionFrom *from1 = new ExceptionFrom(pins1, nullptr, insts1, - from->transition(), true, network_); + from->transition(), true, network_); ExceptionThruSeq *thrus1 = exceptionThrusClone(exception->thrus(), network_); ExceptionTo *to = exception->to(); ExceptionTo *to1 = to ? to->clone(network_) : nullptr; @@ -4279,7 +4294,7 @@ Sdc::addException(ExceptionPath *exception) ClockSet *clks2 = new ClockSet(*from->clks()); ExceptionFrom *from2 = new ExceptionFrom(nullptr, clks2, nullptr, - from->transition(), true, network_); + from->transition(), true, network_); ExceptionThruSeq *thrus2 = exceptionThrusClone(exception->thrus(), network_); ExceptionTo *to2 = to ? to->clone(network_) : nullptr; ExceptionPath *exception2 = exception->clone(from2, thrus2, to2, true); @@ -4305,7 +4320,7 @@ Sdc::addException1(ExceptionPath *exception) PinSet *pins1 = to->pins() ? new PinSet(*to->pins()) : nullptr; InstanceSet *insts1 = to->instances() ? new InstanceSet(*to->instances()) : nullptr; ExceptionTo *to1 = new ExceptionTo(pins1, nullptr, insts1, to->transition(), - to->endTransition(), true, network_); + to->endTransition(), true, network_); ExceptionPath *exception1 = exception->clone(from1, thrus1, to1, true); debugPrint(debug_, "exception_merge", 1, " split exception for %s", exception1->asString(network_)); @@ -4315,7 +4330,7 @@ Sdc::addException1(ExceptionPath *exception) ExceptionThruSeq *thrus2 = exceptionThrusClone(exception->thrus(), network_); ClockSet *clks2 = new ClockSet(*to->clks()); ExceptionTo *to2 = new ExceptionTo(nullptr, clks2, nullptr, to->transition(), - to->endTransition(), true, network_); + to->endTransition(), true, network_); ExceptionPath *exception2 = exception->clone(from2, thrus2, to2, true); debugPrint(debug_, "exception_merge", 1, " split exception for %s", exception2->asString(network_)); @@ -4401,7 +4416,7 @@ Sdc::deleteMatchingExceptions(ExceptionPath *exception) void Sdc::findMatchingExceptions(ExceptionPath *exception, - ExceptionPathSet &matches) + ExceptionPathSet &matches) { if (exception->from()) findMatchingExceptionsFirstFrom(exception, matches); @@ -4413,7 +4428,7 @@ Sdc::findMatchingExceptions(ExceptionPath *exception, void Sdc::findMatchingExceptionsFirstFrom(ExceptionPath *exception, - ExceptionPathSet &matches) + ExceptionPathSet &matches) { ExceptionFrom *from = exception->from(); findMatchingExceptionsPins(exception, from->pins(), @@ -4428,30 +4443,30 @@ Sdc::findMatchingExceptionsFirstFrom(ExceptionPath *exception, void Sdc::findMatchingExceptionsFirstThru(ExceptionPath *exception, - ExceptionPathSet &matches) + ExceptionPathSet &matches) { ExceptionThru *thru = (*exception->thrus())[0]; findMatchingExceptionsPins(exception, thru->pins(), - first_thru_pin_exceptions_, - matches); + first_thru_pin_exceptions_, + matches); findMatchingExceptionsInsts(exception, thru->instances(), - first_thru_inst_exceptions_, - matches); + first_thru_inst_exceptions_, + matches); if (!first_thru_net_exceptions_.empty() && thru->nets()) { for (const Net *net : *thru->nets()) { // Potential matches includes exceptions that match net that are not // the first exception point. const ExceptionPathSet *potential_matches = - findExceptions(first_thru_net_exceptions_, net); + findKeyValuePtr(first_thru_net_exceptions_, net); if (potential_matches) { - for (ExceptionPath *match : *potential_matches) { - ExceptionThru *match_thru = (*match->thrus())[0]; - if (match_thru->nets()->hasKey(net) - && match->overrides(exception) - && match->intersectsPts(exception, network_)) - matches.insert(match); - } + for (ExceptionPath *match : *potential_matches) { + ExceptionThru *match_thru = (*match->thrus())[0]; + if (match_thru->nets()->contains(net) + && match->overrides(exception) + && match->intersectsPts(exception, network_)) + matches.insert(match); + } } } } @@ -4459,30 +4474,30 @@ Sdc::findMatchingExceptionsFirstThru(ExceptionPath *exception, void Sdc::findMatchingExceptionsFirstTo(ExceptionPath *exception, - ExceptionPathSet &matches) + ExceptionPathSet &matches) { ExceptionTo *to = exception->to(); findMatchingExceptionsPins(exception, to->pins(), first_to_pin_exceptions_, - matches); + matches); findMatchingExceptionsInsts(exception, to->instances(), - first_to_inst_exceptions_, - matches); + first_to_inst_exceptions_, + matches); findMatchingExceptionsClks(exception, to->clks(), first_to_clk_exceptions_, - matches); + matches); } void Sdc::findMatchingExceptionsClks(ExceptionPath *exception, - ClockSet *clks, - ClockExceptionsMap &exception_map, - ExceptionPathSet &matches) + ClockSet *clks, + ClockExceptionsMap &exception_map, + ExceptionPathSet &matches) { if (clks) { ExceptionPathSet clks_matches; for (Clock *clk : *clks) { auto itr = exception_map.find(clk); if (itr != exception_map.end()) - clks_matches.insert(itr->second.begin(), itr->second.end()); + clks_matches.insert(itr->second.begin(), itr->second.end()); } findMatchingExceptions(exception, &clks_matches, matches); } @@ -4490,16 +4505,16 @@ Sdc::findMatchingExceptionsClks(ExceptionPath *exception, void Sdc::findMatchingExceptionsPins(ExceptionPath *exception, - PinSet *pins, - PinExceptionsMap &exception_map, - ExceptionPathSet &matches) + PinSet *pins, + PinExceptionsMap &exception_map, + ExceptionPathSet &matches) { if (pins) { ExceptionPathSet pins_matches; for (const Pin *pin : *pins) { auto itr = exception_map.find(pin); if (itr != exception_map.end()) - pins_matches.insert(itr->second.begin(), itr->second.end()); + pins_matches.insert(itr->second.begin(), itr->second.end()); } findMatchingExceptions(exception, &pins_matches, matches); } @@ -4507,16 +4522,16 @@ Sdc::findMatchingExceptionsPins(ExceptionPath *exception, void Sdc::findMatchingExceptionsInsts(ExceptionPath *exception, - InstanceSet *insts, - InstanceExceptionsMap &exception_map, - ExceptionPathSet &matches) + InstanceSet *insts, + InstanceExceptionsMap &exception_map, + ExceptionPathSet &matches) { if (insts) { ExceptionPathSet inst_matches; for (const Instance *inst : *insts) { auto itr = exception_map.find(inst); if (itr != exception_map.end()) - inst_matches.insert(itr->second.begin(), itr->second.end()); + inst_matches.insert(itr->second.begin(), itr->second.end()); } findMatchingExceptions(exception, &inst_matches, matches); } @@ -4524,22 +4539,22 @@ Sdc::findMatchingExceptionsInsts(ExceptionPath *exception, void Sdc::findMatchingExceptions(ExceptionPath *exception, - ExceptionPathSet *potential_matches, - ExceptionPathSet &matches) + ExceptionPathSet *potential_matches, + ExceptionPathSet &matches) { if (potential_matches) { for (ExceptionPath *match : *potential_matches) { if (match->overrides(exception) - && match->intersectsPts(exception, network_)) - matches.insert(match); + && match->intersectsPts(exception, network_)) + matches.insert(match); } } } void Sdc::expandExceptionExcluding(ExceptionPath *exception, - ExceptionPath *excluding, - ExceptionPathSet &expansions) + ExceptionPath *excluding, + ExceptionPathSet &expansions) { ExceptionFrom *from = exception->from(); ExceptionThruSeq *thrus = exception->thrus(); @@ -4550,10 +4565,10 @@ Sdc::expandExceptionExcluding(ExceptionPath *exception, if (from_cpy->hasObjects()) { ExceptionThruSeq *thrus_cpy = nullptr; if (thrus) - thrus_cpy = clone(thrus, network_); + thrus_cpy = clone(thrus, network_); ExceptionTo *to_cpy = nullptr; if (to) - to_cpy = to->clone(network_); + to_cpy = to->clone(network_); ExceptionPath *expand = exception->clone(from_cpy,thrus_cpy,to_cpy,true); expansions.insert(expand); } @@ -4561,36 +4576,37 @@ Sdc::expandExceptionExcluding(ExceptionPath *exception, delete from_cpy; } if (thrus) { - ExceptionThruSeq::Iterator thru_iter(thrus); - ExceptionThruSeq::Iterator thru_iter2(excluding->thrus()); - while (thru_iter.hasNext() - && thru_iter2.hasNext()) { - ExceptionThru *thru = thru_iter.next(); - ExceptionThru *thru2 = thru_iter2.next(); + ExceptionThruSeq *excluding_thrus = excluding->thrus(); + ExceptionThruSeq::iterator thru_iter = thrus->begin(); + ExceptionThruSeq::iterator thru_iter2 = excluding_thrus->begin(); + while (thru_iter != thrus->end() + && thru_iter2 != excluding_thrus->end()) { + ExceptionThru *thru = *thru_iter++; + ExceptionThru *thru2 = *thru_iter2++; ExceptionThru *thru_cpy = thru->clone(network_); thru_cpy->deleteObjects(thru2, network_); if (thru_cpy->hasObjects()) { - ExceptionFrom *from_cpy = nullptr; - if (from) - from_cpy = from->clone(network_); - ExceptionThruSeq *thrus_cpy = new ExceptionThruSeq; + ExceptionFrom *from_cpy = nullptr; + if (from) + from_cpy = from->clone(network_); + ExceptionThruSeq *thrus_cpy = new ExceptionThruSeq; for (ExceptionThru *thru1 : *thrus) { - if (thru1 == thru) - thrus_cpy->push_back(thru_cpy); - else { - ExceptionThru *thru_cpy = thru->clone(network_); - thrus_cpy->push_back(thru_cpy); - } - } - ExceptionTo *to_cpy = nullptr; - if (to) - to_cpy = to->clone(network_); - ExceptionPath *expand = exception->clone(from_cpy, thrus_cpy, to_cpy, - true); - expansions.insert(expand); + if (thru1 == thru) + thrus_cpy->push_back(thru_cpy); + else { + ExceptionThru *thru_cpy = thru->clone(network_); + thrus_cpy->push_back(thru_cpy); + } + } + ExceptionTo *to_cpy = nullptr; + if (to) + to_cpy = to->clone(network_); + ExceptionPath *expand = exception->clone(from_cpy, thrus_cpy, to_cpy, + true); + expansions.insert(expand); } else - delete thru_cpy; + delete thru_cpy; } } if (to) { @@ -4599,10 +4615,10 @@ Sdc::expandExceptionExcluding(ExceptionPath *exception, if (to_cpy->hasObjects()) { ExceptionFrom *from_cpy = nullptr; if (from) - from_cpy = from->clone(network_); + from_cpy = from->clone(network_); ExceptionThruSeq *thrus_cpy = nullptr; if (thrus) - thrus_cpy = clone(thrus, network_); + thrus_cpy = clone(thrus, network_); ExceptionPath *expand = exception->clone(from_cpy,thrus_cpy,to_cpy,true); expansions.insert(expand); } @@ -4662,7 +4678,7 @@ Sdc::recordMergeHashes(ExceptionPath *exception) void Sdc::recordMergeHash(ExceptionPath *exception, - ExceptionPt *missing_pt) + ExceptionPt *missing_pt) { size_t hash = exception->hash(missing_pt); debugPrint(debug_, "exception_merge", 3, @@ -4695,7 +4711,7 @@ Sdc::recordExceptionFirstFrom(ExceptionPath *exception) ExceptionFrom *from = exception->from(); recordExceptionPins(exception, from->pins(), first_from_pin_exceptions_); recordExceptionInsts(exception, from->instances(), - first_from_inst_exceptions_); + first_from_inst_exceptions_); recordExceptionClks(exception, from->clks(), first_from_clk_exceptions_); } @@ -4721,7 +4737,7 @@ Sdc::recordExceptionFirstThru(ExceptionPath *exception) ExceptionThru *thru = (*exception->thrus())[0]; recordExceptionPins(exception, thru->pins(), first_thru_pin_exceptions_); recordExceptionInsts(exception, thru->instances(), - first_thru_inst_exceptions_); + first_thru_inst_exceptions_); recordExceptionEdges(exception, thru->edges(), first_thru_edge_exceptions_); for (ExceptionThru *thru : *exception->thrus()) recordExceptionNets(exception, thru->nets(), first_thru_net_exceptions_); @@ -4738,8 +4754,8 @@ Sdc::recordExceptionFirstTo(ExceptionPath *exception) void Sdc::recordExceptionClks(ExceptionPath *exception, - ClockSet *clks, - ClockExceptionsMap &exception_map) + ClockSet *clks, + ClockExceptionsMap &exception_map) { if (clks) { for (Clock *clk : *clks) { @@ -4751,8 +4767,8 @@ Sdc::recordExceptionClks(ExceptionPath *exception, void Sdc::recordExceptionEdges(ExceptionPath *exception, - EdgePinsSet *edges, - EdgeExceptionsMap &exception_map) + EdgePinsSet *edges, + EdgeExceptionsMap &exception_map) { if (edges) { for (const EdgePins &edge : *edges) { @@ -4764,8 +4780,8 @@ Sdc::recordExceptionEdges(ExceptionPath *exception, void Sdc::recordExceptionPins(ExceptionPath *exception, - PinSet *pins, - PinExceptionsMap &exception_map) + PinSet *pins, + PinExceptionsMap &exception_map) { if (pins) { for (const Pin *pin : *pins) { @@ -4777,8 +4793,8 @@ Sdc::recordExceptionPins(ExceptionPath *exception, void Sdc::recordExceptionHpin(ExceptionPath *exception, - Pin *pin, - PinExceptionsMap &exception_map) + Pin *pin, + PinExceptionsMap &exception_map) { ExceptionPathSet &set = exception_map[pin]; set.insert(exception); @@ -4786,8 +4802,8 @@ Sdc::recordExceptionHpin(ExceptionPath *exception, void Sdc::recordExceptionInsts(ExceptionPath *exception, - InstanceSet *insts, - InstanceExceptionsMap &exception_map) + InstanceSet *insts, + InstanceExceptionsMap &exception_map) { if (insts) { for (const Instance *inst : *insts) { @@ -4799,8 +4815,8 @@ Sdc::recordExceptionInsts(ExceptionPath *exception, void Sdc::recordExceptionNets(ExceptionPath *exception, - NetSet *nets, - NetExceptionsMap &exception_map) + NetSet *nets, + NetExceptionsMap &exception_map) { if (nets) { for (const Net *net : *nets) { @@ -4843,31 +4859,31 @@ Sdc::findMergeMatch(ExceptionPath *exception) if (itr != exception_merge_hash_.end()) { ExceptionPathSet &matches = itr->second; for (ExceptionPath *match : matches) { - ExceptionPt *match_missing_pt; - if (match != exception - // Exceptions are not merged if their priorities are - // different. This allows exceptions to be pruned during - // search at the endpoint. - && exception->mergeable(match) - && match->mergeablePts(exception, missing_pt, match_missing_pt)) { - debugPrint(debug_, "exception_merge", 1, "merge %s", + ExceptionPt *match_missing_pt; + if (match != exception + // Exceptions are not merged if their priorities are + // different. This allows exceptions to be pruned during + // search at the endpoint. + && exception->mergeable(match) + && match->mergeablePts(exception, missing_pt, match_missing_pt)) { + debugPrint(debug_, "exception_merge", 1, "merge %s", exception->asString(network_)); - debugPrint(debug_, "exception_merge", 1, " with %s", + debugPrint(debug_, "exception_merge", 1, " with %s", match->asString(network_)); - // Unrecord the exception that is being merged away. - unrecordException(exception); - unrecordMergeHashes(match); - missing_pt->mergeInto(match_missing_pt, network_); - recordMergeHashes(match); - // First point maps only change if the exception point that - // is being merged is the first exception point. - if (first_pt) - recordExceptionFirstPts(match); + // Unrecord the exception that is being merged away. + unrecordException(exception); + unrecordMergeHashes(match); + missing_pt->mergeInto(match_missing_pt, network_); + recordMergeHashes(match); + // First point maps only change if the exception point that + // is being merged is the first exception point. + if (first_pt) + recordExceptionFirstPts(match); // Have to wait until after exception point merge to delete // the exception. - delete exception; - return match; - } + delete exception; + return match; + } } } first_pt = false; @@ -4919,32 +4935,32 @@ Sdc::deleteExceptionsReferencing(Clock *clk) ExceptionFrom *from = exception->from(); if (from) { ClockSet *clks = from->clks(); - if (clks && clks->hasKey(clk)) { - itr = exceptions_.erase(itr); - unrecordException(exception); - deleted = true; - from->deleteClock(clk); - if (from->hasObjects()) - recordException(exception); - else - deleteException(exception); + if (clks && clks->contains(clk)) { + itr = exceptions_.erase(itr); + unrecordException(exception); + deleted = true; + from->deleteClock(clk); + if (from->hasObjects()) + recordException(exception); + else + deleteException(exception); } } if (!deleted) { ExceptionTo *to = exception->to(); if (to) { - ClockSet *clks = to->clks(); - if (clks && clks->hasKey(clk)) { - itr = exceptions_.erase(itr); - deleted = true; - unrecordException(exception); - to->deleteClock(clk); - if (to->hasObjects()) - recordException(exception); - else - deleteException(exception); - } + ClockSet *clks = to->clks(); + if (clks && clks->contains(clk)) { + itr = exceptions_.erase(itr); + deleted = true; + unrecordException(exception); + to->deleteClock(clk); + if (to->hasObjects()) + recordException(exception); + else + deleteException(exception); + } } } if (!deleted) @@ -4982,7 +4998,7 @@ Sdc::unrecordMergeHashes(ExceptionPath *exception) void Sdc::unrecordMergeHash(ExceptionPath *exception, - ExceptionPt *missing_pt) + ExceptionPt *missing_pt) { size_t hash = exception->hash(missing_pt); debugPrint(debug_, "exception_merge", 3, @@ -5012,16 +5028,16 @@ Sdc::unrecordExceptionFirstPts(ExceptionPath *exception) ExceptionThru *thru = (*thrus)[0]; unrecordExceptionPins(exception, thru->pins(), first_thru_pin_exceptions_); unrecordExceptionInsts(exception, thru->instances(), - first_thru_inst_exceptions_); + first_thru_inst_exceptions_); unrecordExceptionNets(exception, thru->nets(), first_thru_net_exceptions_); unrecordExceptionEdges(exception, thru->edges(), - first_thru_edge_exceptions_); + first_thru_edge_exceptions_); } else if (to) { unrecordExceptionPins(exception, to->pins(), first_to_pin_exceptions_); unrecordExceptionClks(exception, to->clks(), first_to_clk_exceptions_); unrecordExceptionInsts(exception, to->instances(), - first_to_inst_exceptions_); + first_to_inst_exceptions_); } } @@ -5043,14 +5059,14 @@ Sdc::unrecordExceptionPins(ExceptionPath *exception) void Sdc::unrecordExceptionClks(ExceptionPath *exception, - ClockSet *clks, - ClockExceptionsMap &exception_map) + ClockSet *clks, + ClockExceptionsMap &exception_map) { if (clks) { for (Clock *clk : *clks) { auto itr = exception_map.find(clk); if (itr != exception_map.end()) { - ExceptionPathSet &set = itr->second; + ExceptionPathSet &set = itr->second; set.erase(exception); } } @@ -5059,14 +5075,14 @@ Sdc::unrecordExceptionClks(ExceptionPath *exception, void Sdc::unrecordExceptionPins(ExceptionPath *exception, - PinSet *pins, - PinExceptionsMap &exception_map) + PinSet *pins, + PinExceptionsMap &exception_map) { if (pins) { for (const Pin *pin : *pins) { auto itr = exception_map.find(pin); if (itr != exception_map.end()) { - ExceptionPathSet &set = itr->second; + ExceptionPathSet &set = itr->second; set.erase(exception); } } @@ -5075,14 +5091,14 @@ Sdc::unrecordExceptionPins(ExceptionPath *exception, void Sdc::unrecordExceptionInsts(ExceptionPath *exception, - InstanceSet *insts, - InstanceExceptionsMap &exception_map) + InstanceSet *insts, + InstanceExceptionsMap &exception_map) { if (insts) { for (const Instance *inst : *insts) { auto itr = exception_map.find(inst); if (itr != exception_map.end()) { - ExceptionPathSet &set = itr->second; + ExceptionPathSet &set = itr->second; set.erase(exception); } } @@ -5091,14 +5107,14 @@ Sdc::unrecordExceptionInsts(ExceptionPath *exception, void Sdc::unrecordExceptionEdges(ExceptionPath *exception, - EdgePinsSet *edges, - EdgeExceptionsMap &exception_map) + EdgePinsSet *edges, + EdgeExceptionsMap &exception_map) { if (edges) { for (const EdgePins &edge : *edges) { auto itr = exception_map.find(edge); if (itr != exception_map.end()) { - ExceptionPathSet &set = itr->second; + ExceptionPathSet &set = itr->second; set.erase(exception); } } @@ -5107,14 +5123,14 @@ Sdc::unrecordExceptionEdges(ExceptionPath *exception, void Sdc::unrecordExceptionNets(ExceptionPath *exception, - NetSet *nets, - NetExceptionsMap &exception_map) + NetSet *nets, + NetExceptionsMap &exception_map) { if (nets) { for (const Net *net : *nets) { auto itr = exception_map.find(net); if (itr != exception_map.end()) { - ExceptionPathSet &set = itr->second; + ExceptionPathSet &set = itr->second; set.erase(exception); } } @@ -5123,8 +5139,8 @@ Sdc::unrecordExceptionNets(ExceptionPath *exception, void Sdc::unrecordExceptionHpin(ExceptionPath *exception, - Pin *pin, - PinExceptionsMap &exception_map) + Pin *pin, + PinExceptionsMap &exception_map) { auto itr = exception_map.find(pin); if (itr != exception_map.end()) { @@ -5139,19 +5155,19 @@ class ExpandException : public ExpandedExceptionVisitor { public: ExpandException(ExceptionPath *exception, - ExceptionPathSet &expansions, - Network *network); + ExceptionPathSet &expansions, + Network *network); virtual void visit(ExceptionFrom *from, - ExceptionThruSeq *thrus, - ExceptionTo *to); + ExceptionThruSeq *thrus, + ExceptionTo *to); private: ExceptionPathSet &expansions_; }; ExpandException::ExpandException(ExceptionPath *exception, - ExceptionPathSet &expansions, - Network *network) : + ExceptionPathSet &expansions, + Network *network) : ExpandedExceptionVisitor(exception, network), expansions_(expansions) { @@ -5159,8 +5175,8 @@ ExpandException::ExpandException(ExceptionPath *exception, void ExpandException::visit(ExceptionFrom *from, - ExceptionThruSeq *thrus, - ExceptionTo *to) + ExceptionThruSeq *thrus, + ExceptionTo *to) { ExceptionFrom *from_clone = nullptr; if (from) @@ -5177,7 +5193,7 @@ ExpandException::visit(ExceptionFrom *from, if (to) to_clone = to->clone(network_); ExceptionPath *expand = exception_->clone(from_clone, thrus_clone, - to_clone, true); + to_clone, true); expansions_.insert(expand); } @@ -5185,7 +5201,7 @@ ExpandException::visit(ExceptionFrom *from, // point in each from/thru/to. void Sdc::expandException(ExceptionPath *exception, - ExceptionPathSet &expansions) + ExceptionPathSet &expansions) { ExpandException expander(exception, expansions, network_); expander.visitExpansions(); @@ -5195,9 +5211,9 @@ Sdc::expandException(ExceptionPath *exception, void Sdc::resetPath(ExceptionFrom *from, - ExceptionThruSeq *thrus, - ExceptionTo *to, - const MinMaxAll *min_max) + ExceptionThruSeq *thrus, + ExceptionTo *to, + const MinMaxAll *min_max) { checkFromThrusTo(from, thrus, to); // erase prevents range iteration. @@ -5212,13 +5228,13 @@ Sdc::resetPath(ExceptionFrom *from, deleteException(match); for (ExceptionPath *expand : expansions) { - if (expand->resetMatch(from, thrus, to, min_max, network_)) { - unrecordPathDelayInternalFrom(expand); - unrecordPathDelayInternalTo(expand); - delete expand; - } - else - addException(expand); + if (expand->resetMatch(from, thrus, to, min_max, network_)) { + unrecordPathDelayInternalFrom(expand); + unrecordPathDelayInternalTo(expand); + delete expand; + } + else + addException(expand); } } else @@ -5230,57 +5246,56 @@ Sdc::resetPath(ExceptionFrom *from, bool Sdc::exceptionFromStates(const Pin *pin, - const RiseFall *rf, - const Clock *clk, - const RiseFall *clk_rf, - const MinMax *min_max, - ExceptionStateSet *&states) const + const RiseFall *rf, + const Clock *clk, + const RiseFall *clk_rf, + const MinMax *min_max, + ExceptionStateSet *&states) { return exceptionFromStates(pin, rf, clk, clk_rf, min_max, true, states); } bool Sdc::exceptionFromStates(const Pin *pin, - const RiseFall *rf, - const Clock *clk, - const RiseFall *clk_rf, - const MinMax *min_max, - bool include_filter, - ExceptionStateSet *&states) const + const RiseFall *rf, + const Clock *clk, + const RiseFall *clk_rf, + const MinMax *min_max, + bool include_filter, + ExceptionStateSet *&states) { bool srch_from = true; if (pin) { if (srch_from) { const ExceptionPathSet *exceptions = - findExceptions(first_from_pin_exceptions_, pin); + findKeyValuePtr(first_from_pin_exceptions_, pin); srch_from &= exceptionFromStates(exceptions, pin, rf, min_max, - include_filter, states); + include_filter, states); } if (srch_from) { const ExceptionPathSet *exceptions = - findExceptions(first_thru_pin_exceptions_, pin); + findKeyValuePtr(first_thru_pin_exceptions_, pin); srch_from &= exceptionFromStates(exceptions, pin, rf, min_max, - include_filter, states); + include_filter, states); } if (srch_from - && (!first_from_inst_exceptions_.empty() + && (!first_from_inst_exceptions_.empty() || !first_thru_inst_exceptions_.empty())) { Instance *inst = network_->instance(pin); const ExceptionPathSet *exceptions = - findExceptions(first_from_inst_exceptions_, inst); + findKeyValuePtr(first_from_inst_exceptions_, inst); srch_from &= exceptionFromStates(exceptions, pin, rf, min_max, - include_filter, states); + include_filter, states); const ExceptionPathSet *exceptions2 = - findExceptions(first_thru_inst_exceptions_, inst); + findKeyValuePtr(first_thru_inst_exceptions_, inst); srch_from &= exceptionFromStates(exceptions2, pin, rf, min_max, - include_filter, states); + include_filter, states); } } if (srch_from && clk) { - const ExceptionPathSet *exceptions = - findExceptions(first_from_clk_exceptions_, clk); + const ExceptionPathSet *exceptions = findKeyValuePtr(first_from_clk_exceptions_, clk); srch_from &= exceptionFromStates(exceptions, pin, clk_rf, min_max, - include_filter, states); + include_filter, states); } if (!srch_from) { delete states; @@ -5291,40 +5306,40 @@ Sdc::exceptionFromStates(const Pin *pin, bool Sdc::exceptionFromStates(const ExceptionPathSet *exceptions, - const Pin *pin, - const RiseFall *rf, - const MinMax *min_max, - bool include_filter, - ExceptionStateSet *&states) const + const Pin *pin, + const RiseFall *rf, + const MinMax *min_max, + bool include_filter, + ExceptionStateSet *&states) const { if (exceptions) { for (ExceptionPath *exception : *exceptions) { if (exception->matches(min_max, false) - && (exception->from() == nullptr - || exception->from()->transition()->matches(rf)) - && (include_filter || !exception->isFilter())) { - ExceptionState *state = exception->firstState(); - if (state->matchesNextThru(nullptr, pin, rf, min_max, network_)) - // -from clk -thru reg/clk - state = state->nextState(); - // If the exception is -from and has no -to transition it is - // complete out of the gate. - if (state->isComplete() - && exception->isFalse()) { - // Leave the completed false path state as a marker on the tag, - // but flush all other exception states because they are lower - // priority. - if (states == nullptr) - states = new ExceptionStateSet(); - states->clear(); - states->insert(state); - // No need to examine other exceptions from this - // pin/clock/instance. - return false; - } - if (states == nullptr) - states = new ExceptionStateSet(); - states->insert(state); + && (exception->from() == nullptr + || exception->from()->transition()->matches(rf)) + && (include_filter || !exception->isFilter())) { + ExceptionState *state = exception->firstState(); + if (state->matchesNextThru(nullptr, pin, rf, min_max, network_)) + // -from clk -thru reg/clk + state = state->nextState(); + // If the exception is -from and has no -to transition it is + // complete out of the gate. + if (state->isComplete() + && exception->isFalse()) { + // Leave the completed false path state as a marker on the tag, + // but flush all other exception states because they are lower + // priority. + if (states == nullptr) + states = new ExceptionStateSet(); + states->clear(); + states->insert(state); + // No need to examine other exceptions from this + // pin/clock/instance. + return false; + } + if (states == nullptr) + states = new ExceptionStateSet(); + states->insert(state); } } } @@ -5333,50 +5348,48 @@ Sdc::exceptionFromStates(const ExceptionPathSet *exceptions, void Sdc::exceptionFromClkStates(const Pin *pin, - const RiseFall *rf, - const Clock *clk, - const RiseFall *clk_rf, - const MinMax *min_max, - ExceptionStateSet *&states) const + const RiseFall *rf, + const Clock *clk, + const RiseFall *clk_rf, + const MinMax *min_max, + ExceptionStateSet *&states) { if (pin) { const ExceptionPathSet *exceptions = - findExceptions(first_from_pin_exceptions_, pin); + findKeyValuePtr(first_from_pin_exceptions_, pin); exceptionFromStates(exceptions, nullptr, rf, min_max, true, states); if (!first_from_inst_exceptions_.empty()) { Instance *inst = network_->instance(pin); const ExceptionPathSet *exceptions = - findExceptions(first_from_inst_exceptions_, inst); + findKeyValuePtr(first_from_inst_exceptions_, inst); exceptionFromStates(exceptions, pin, rf, min_max, true, states); } - const ExceptionPathSet *exceptions2 = - findExceptions(first_thru_pin_exceptions_, pin); + const ExceptionPathSet *exceptions2 = findKeyValuePtr(first_thru_pin_exceptions_, pin); exceptionThruStates(exceptions2, rf, min_max, states); } - const ExceptionPathSet *exceptions = - findExceptions(first_from_clk_exceptions_, clk); + const ExceptionPathSet *exceptions = findKeyValuePtr(first_from_clk_exceptions_, clk); exceptionFromStates(exceptions, pin, clk_rf, min_max, true, states); } void Sdc::filterRegQStates(const Pin *to_pin, - const RiseFall *to_rf, - const MinMax *min_max, - ExceptionStateSet *&states) const + const RiseFall *to_rf, + const MinMax *min_max, + ExceptionStateSet *&states) const { if (!first_from_pin_exceptions_.empty()) { auto itr = first_from_pin_exceptions_.find(to_pin); if (itr != first_from_pin_exceptions_.end()) { const ExceptionPathSet &exceptions = itr->second; for (ExceptionPath *exception : exceptions) { - // Hack for filter -from reg/Q. - if (exception->isFilter() - && exception->matchesFirstPt(to_rf, min_max)) { - ExceptionState *state = exception->firstState(); - if (states == nullptr) - states = new ExceptionStateSet(); - states->insert(state); - } + // Hack for filter -from reg/Q. + if (exception->isFilter() + && exception->matchesFirstPt(to_rf, min_max)) { + ExceptionState *state = exception->firstState(); + if (states == nullptr) + states = new ExceptionStateSet(); + states->insert(state); + } } } } @@ -5384,13 +5397,13 @@ Sdc::filterRegQStates(const Pin *to_pin, void Sdc::exceptionThruStates(const Pin *from_pin, - const Pin *to_pin, - const RiseFall *to_rf, - const MinMax *min_max, - ExceptionStateSet *&states) const + const Pin *to_pin, + const RiseFall *to_rf, + const MinMax *min_max, + ExceptionStateSet *&states) { const ExceptionPathSet *exceptions = - findExceptions(first_thru_pin_exceptions_, to_pin); + findKeyValuePtr(first_thru_pin_exceptions_, to_pin); exceptionThruStates(exceptions, to_rf, min_max, states); if (!first_thru_edge_exceptions_.empty()) { @@ -5403,28 +5416,28 @@ Sdc::exceptionThruStates(const Pin *from_pin, } if (!first_thru_inst_exceptions_.empty() && (network_->direction(to_pin)->isAnyOutput() - || network_->isLatchData(to_pin))) { + || network_->isLatchData(to_pin))) { const Instance *to_inst = network_->instance(to_pin); const ExceptionPathSet *exceptions = - findExceptions(first_thru_inst_exceptions_, to_inst); + findKeyValuePtr(first_thru_inst_exceptions_, to_inst); exceptionThruStates(exceptions, to_rf, min_max, states); } } void Sdc::exceptionThruStates(const ExceptionPathSet *exceptions, - const RiseFall *to_rf, - const MinMax *min_max, - // Return value. - ExceptionStateSet *&states) const + const RiseFall *to_rf, + const MinMax *min_max, + // Return value. + ExceptionStateSet *&states) const { if (exceptions) { for (ExceptionPath *exception : *exceptions) { if (exception->matchesFirstPt(to_rf, min_max)) { - ExceptionState *state = exception->firstState(); - if (states == nullptr) - states = new ExceptionStateSet(); - states->insert(state); + ExceptionState *state = exception->firstState(); + if (states == nullptr) + states = new ExceptionStateSet(); + states->insert(state); } } } @@ -5434,81 +5447,79 @@ Sdc::exceptionThruStates(const ExceptionPathSet *exceptions, void Sdc::exceptionTo(ExceptionPathType type, - const Pin *pin, - const RiseFall *rf, - const ClockEdge *clk_edge, - const MinMax *min_max, - bool match_min_max_exactly, - // Return values. - ExceptionPath *&hi_priority_exception, - int &hi_priority) const + const Pin *pin, + const RiseFall *rf, + const ClockEdge *clk_edge, + const MinMax *min_max, + bool match_min_max_exactly, + // Return values. + ExceptionPath *&hi_priority_exception, + int &hi_priority) { if (!first_to_inst_exceptions_.empty()) { Instance *inst = network_->instance(pin); - const ExceptionPathSet *exceptions = - findExceptions(first_to_inst_exceptions_, inst); + const ExceptionPathSet *exceptions = findKeyValuePtr(first_to_inst_exceptions_, inst); exceptionTo(exceptions, type, pin, rf, - clk_edge, min_max, match_min_max_exactly, - hi_priority_exception, hi_priority); + clk_edge, min_max, match_min_max_exactly, + hi_priority_exception, hi_priority); } if (!first_to_pin_exceptions_.empty()) { - const ExceptionPathSet *exceptions = - findExceptions(first_to_pin_exceptions_, pin); + const ExceptionPathSet *exceptions = findKeyValuePtr(first_to_pin_exceptions_, pin); exceptionTo(exceptions, type, pin, rf, - clk_edge, min_max, match_min_max_exactly, - hi_priority_exception, hi_priority); + clk_edge, min_max, match_min_max_exactly, + hi_priority_exception, hi_priority); } if (clk_edge && !first_to_clk_exceptions_.empty()) { const ExceptionPathSet *exceptions = - findExceptions(first_to_clk_exceptions_, clk_edge->clock()); + findKeyValuePtr(first_to_clk_exceptions_, clk_edge->clock()); exceptionTo(exceptions, type, pin, rf, clk_edge, - min_max, match_min_max_exactly, - hi_priority_exception, hi_priority); + min_max, match_min_max_exactly, + hi_priority_exception, hi_priority); } } void Sdc::exceptionTo(const ExceptionPathSet *to_exceptions, - ExceptionPathType type, - const Pin *pin, - const RiseFall *rf, - const ClockEdge *clk_edge, - const MinMax *min_max, - bool match_min_max_exactly, - // Return values. - ExceptionPath *&hi_priority_exception, - int &hi_priority) const + ExceptionPathType type, + const Pin *pin, + const RiseFall *rf, + const ClockEdge *clk_edge, + const MinMax *min_max, + bool match_min_max_exactly, + // Return values. + ExceptionPath *&hi_priority_exception, + int &hi_priority) const { if (to_exceptions) { for (ExceptionPath *exception : *to_exceptions) { exceptionTo(exception, type, pin, rf, clk_edge, - min_max, match_min_max_exactly, - hi_priority_exception, hi_priority); + min_max, match_min_max_exactly, + hi_priority_exception, hi_priority); } } } void Sdc::exceptionTo(ExceptionPath *exception, - ExceptionPathType type, - const Pin *pin, - const RiseFall *rf, - const ClockEdge *clk_edge, - const MinMax *min_max, - bool match_min_max_exactly, - // Return values. - ExceptionPath *&hi_priority_exception, - int &hi_priority) const + ExceptionPathType type, + const Pin *pin, + const RiseFall *rf, + const ClockEdge *clk_edge, + const MinMax *min_max, + bool match_min_max_exactly, + // Return values. + ExceptionPath *&hi_priority_exception, + int &hi_priority) const { if ((type == ExceptionPathType::any || exception->type() == type) && exceptionMatchesTo(exception, pin, rf, clk_edge, min_max, - match_min_max_exactly, false)) { + match_min_max_exactly, false)) { int priority = exception->priority(min_max); if (hi_priority_exception == nullptr - || priority > hi_priority - || (priority == hi_priority - && exception->tighterThan(hi_priority_exception))) { + || priority > hi_priority + || (priority == hi_priority + && exception->tighterThan(hi_priority_exception))) { hi_priority = priority; hi_priority_exception = exception; } @@ -5517,40 +5528,40 @@ Sdc::exceptionTo(ExceptionPath *exception, bool Sdc::exceptionMatchesTo(ExceptionPath *exception, - const Pin *pin, - const RiseFall *rf, - const ClockEdge *clk_edge, - const MinMax *min_max, - bool match_min_max_exactly, - bool require_to_pin) const + const Pin *pin, + const RiseFall *rf, + const ClockEdge *clk_edge, + const MinMax *min_max, + bool match_min_max_exactly, + bool require_to_pin) const { ExceptionTo *to = exception->to(); return exception->matches(min_max, match_min_max_exactly) && ((to == nullptr - && !require_to_pin) - || (to - && to->matches(pin, clk_edge, rf, network_))); + && !require_to_pin) + || (to + && to->matches(pin, clk_edge, rf, network_))); } bool Sdc::isCompleteTo(ExceptionState *state, - const Pin *pin, - const RiseFall *rf, - const ClockEdge *clk_edge, - const MinMax *min_max, - bool match_min_max_exactly, - bool require_to_pin) const + const Pin *pin, + const RiseFall *rf, + const ClockEdge *clk_edge, + const MinMax *min_max, + bool match_min_max_exactly, + bool require_to_pin) const { return state->nextThru() == nullptr && exceptionMatchesTo(state->exception(), pin, rf, clk_edge, - min_max, match_min_max_exactly, require_to_pin); + min_max, match_min_max_exactly, require_to_pin); } bool Sdc::isCompleteTo(ExceptionState *state, - const Pin *pin, - const RiseFall *rf, - const MinMax *min_max) const + const Pin *pin, + const RiseFall *rf, + const MinMax *min_max) const { ExceptionPath *exception = state->exception(); ExceptionTo *to = exception->to(); @@ -5564,44 +5575,42 @@ Sdc::isCompleteTo(ExceptionState *state, void Sdc::groupPathsTo(const Pin *pin, - const RiseFall *rf, - const ClockEdge *clk_edge, - const MinMax *min_max, - // Return value. - ExceptionPathSeq &group_paths) const + const RiseFall *rf, + const ClockEdge *clk_edge, + const MinMax *min_max, + // Return value. + ExceptionPathSeq &group_paths) { if (!first_to_inst_exceptions_.empty()) { Instance *inst = network_->instance(pin); - const ExceptionPathSet *exceptions = - findExceptions(first_to_inst_exceptions_, inst); + const ExceptionPathSet *exceptions = findKeyValuePtr(first_to_inst_exceptions_, inst); groupPathsTo(exceptions, pin, rf, clk_edge, min_max, group_paths); } if (!first_to_pin_exceptions_.empty()) { - const ExceptionPathSet *exceptions = - findExceptions(first_to_pin_exceptions_, pin); + const ExceptionPathSet *exceptions = findKeyValuePtr(first_to_pin_exceptions_, pin); groupPathsTo(exceptions, pin, rf, clk_edge, min_max, group_paths); } if (clk_edge && !first_to_clk_exceptions_.empty()) { const ExceptionPathSet *exceptions = - findExceptions(first_to_clk_exceptions_, clk_edge->clock()); + findKeyValuePtr(first_to_clk_exceptions_, clk_edge->clock()); groupPathsTo(exceptions, pin, rf, clk_edge, min_max, group_paths); } } void Sdc::groupPathsTo(const ExceptionPathSet *to_exceptions, - const Pin *pin, - const RiseFall *rf, - const ClockEdge *clk_edge, - const MinMax *min_max, - // Return value. - ExceptionPathSeq &group_paths) const + const Pin *pin, + const RiseFall *rf, + const ClockEdge *clk_edge, + const MinMax *min_max, + // Return value. + ExceptionPathSeq &group_paths) const { if (to_exceptions) { for (ExceptionPath *exception : *to_exceptions) { if (exception->isGroupPath() - && exceptionMatchesTo(exception, pin, rf, clk_edge, min_max, true, false)) - group_paths.push_back(exception); + && exceptionMatchesTo(exception, pin, rf, clk_edge, min_max, true, false)) + group_paths.push_back(exception); } } } @@ -5609,14 +5618,14 @@ Sdc::groupPathsTo(const ExceptionPathSet *to_exceptions, //////////////////////////////////////////////////////////////// Wireload * -Sdc::wireload(const MinMax *min_max) +Sdc::wireload(const MinMax *min_max) const { return wireload_[min_max->index()]; } void Sdc::setWireload(Wireload *wireload, - const MinMaxAll *min_max) + const MinMaxAll *min_max) { for (auto mm_index : min_max->rangeIndex()) wireload_[mm_index] = wireload; @@ -5628,12 +5637,6 @@ Sdc::setWireloadMode(WireloadMode mode) wireload_mode_ = mode; } -WireloadMode -Sdc::wireloadMode() -{ - return wireload_mode_; -} - const WireloadSelection * Sdc::wireloadSelection(const MinMax *min_max) { @@ -5644,8 +5647,8 @@ Sdc::wireloadSelection(const MinMax *min_max) if (lib) { WireloadSelection *default_sel = lib->defaultWireloadSelection(); if (default_sel) { - sel = default_sel; - setWireloadSelection(default_sel, MinMaxAll::all()); + sel = default_sel; + setWireloadSelection(default_sel, MinMaxAll::all()); } } } @@ -5654,7 +5657,7 @@ Sdc::wireloadSelection(const MinMax *min_max) void Sdc::setWireloadSelection(WireloadSelection *selection, - const MinMaxAll *min_max) + const MinMaxAll *min_max) { for (auto mm_index : min_max->rangeIndex()) wireload_selection_[mm_index] = selection; @@ -5699,12 +5702,12 @@ Sdc::deletePinBefore(const Pin *pin) ExceptionPt *first_pt = exception->firstPt(); ExceptionThruSeq *thrus = exception->thrus(); if (thrus) { - for (ExceptionThru *thru : *exception->thrus()) { + for (ExceptionThru *thru : *exception->thrus()) { thru->deletePinBefore(pin, network_); - if (thru == first_pt) - recordExceptionEdges(exception, thru->edges(), - first_thru_edge_exceptions_); - } + if (thru == first_pt) + recordExceptionEdges(exception, thru->edges(), + first_thru_edge_exceptions_); + } } } first_from_pin_exceptions_.erase(pin); @@ -5712,9 +5715,7 @@ Sdc::deletePinBefore(const Pin *pin) first_to_pin_exceptions_.erase(pin); pin_exceptions_.erase(pin); } - - for (int corner_index = 0; corner_index < corners_->count(); corner_index++) - drvr_pin_wire_cap_maps_[corner_index].erase(pin); + drvr_pin_wire_cap_map_.erase(pin); } void @@ -5732,8 +5733,8 @@ Sdc::clkHpinDisablesChanged(const Pin *pin) // hierarchical output - load pins outside the hierarchical instance void findLeafLoadPins(const Pin *pin, - const Network *network, - PinSet *leaf_pins) + const Network *network, + PinSet *leaf_pins) { if (network->isHierarchical(pin)) { PortDirection *dir = network->direction(pin); @@ -5745,9 +5746,9 @@ findLeafLoadPins(const Pin *pin, const Pin *pin1 = pin_iter->next(); bool is_inside = network->isInside(pin1, hinst); if (((is_input && is_inside) - || (is_output && !is_inside)) - && network->isLoad(pin1)) - leaf_pins->insert(pin1); + || (is_output && !is_inside)) + && network->isLoad(pin1)) + leaf_pins->insert(pin1); } delete pin_iter; } @@ -5761,8 +5762,8 @@ findLeafLoadPins(const Pin *pin, // hierarchical output - driver pins inside the hierarchical instance void findLeafDriverPins(const Pin *pin, - const Network *network, - PinSet *leaf_pins) + const Network *network, + PinSet *leaf_pins) { if (network->isHierarchical(pin)) { PortDirection *dir = network->direction(pin); @@ -5774,9 +5775,9 @@ findLeafDriverPins(const Pin *pin, const Pin *pin1 = pin_iter->next(); bool is_inside = network->isInside(pin1, hinst); if (((is_input && !is_inside) - || (is_output && is_inside)) - && network->isDriver(pin1)) - leaf_pins->insert(pin1); + || (is_output && is_inside)) + && network->isDriver(pin1)) + leaf_pins->insert(pin1); } delete pin_iter; } diff --git a/sdc/Sdc.i b/sdc/Sdc.i index 2c66e43d..e6b95667 100644 --- a/sdc/Sdc.i +++ b/sdc/Sdc.i @@ -23,8 +23,11 @@ // This notice may not be removed or altered from any source distribution. %module sdc +%import %{ +#include + #include "Sdc.hh" #include "Wireload.hh" #include "Clock.hh" @@ -89,18 +92,22 @@ private: void write_sdc_cmd(const char *filename, - bool leaf, - bool compatible, - int digits, + bool leaf, + bool compatible, + int digits, bool gzip, - bool no_timestamp) + bool no_timestamp) { - Sta::sta()->writeSdc(filename, leaf, compatible, digits, gzip, no_timestamp); + Sta *sta = Sta::sta(); + const Sdc *sdc = sta->cmdSdc(); + sta->writeSdc(sdc, filename, leaf, compatible, digits, gzip, no_timestamp); } void set_analysis_type_cmd(const char *analysis_type) { + Sta *sta = Sta::sta(); + Sdc *sdc = sta->cmdSdc(); AnalysisType type; if (stringEq(analysis_type, "single")) type = AnalysisType::single; @@ -109,29 +116,35 @@ set_analysis_type_cmd(const char *analysis_type) else if (stringEq(analysis_type, "on_chip_variation")) type = AnalysisType::ocv; else { - Sta::sta()->report()->warn(2121, "unknown analysis type"); + sta->report()->warn(2121, "unknown analysis type"); type = AnalysisType::single; } - Sta::sta()->setAnalysisType(type); + sta->setAnalysisType(type, sdc); } OperatingConditions * operating_conditions(const MinMax *min_max) { - return Sta::sta()->operatingConditions(min_max); + Sta *sta = Sta::sta(); + const Sdc *sdc = sta->cmdSdc(); + return sta->operatingConditions(min_max, sdc); } void set_operating_conditions_cmd(OperatingConditions *op_cond, - const MinMaxAll *min_max) + const MinMaxAll *min_max) { - Sta::sta()->setOperatingConditions(op_cond, min_max); + Sta *sta = Sta::sta(); + Sdc *sdc = sta->cmdSdc(); + sta->setOperatingConditions(op_cond, min_max, sdc); } const char * operating_condition_analysis_type() { - switch (Sta::sta()->sdc()->analysisType()){ + Sta *sta = Sta::sta(); + const Sdc *sdc = sta->cmdSdc(); + switch (sdc->analysisType()) { case AnalysisType::single: return "single"; case AnalysisType::bc_wc: @@ -145,573 +158,692 @@ operating_condition_analysis_type() void set_instance_pvt(Instance *inst, - const MinMaxAll *min_max, - float process, - float voltage, - float temperature) + const MinMaxAll *min_max, + float process, + float voltage, + float temperature) { + Sta *sta = Sta::sta(); + Sdc *sdc = sta->cmdSdc(); Pvt pvt(process, voltage, temperature); - Sta::sta()->setPvt(inst, min_max, pvt); + sta->setPvt(inst, min_max, pvt, sdc); } float port_ext_pin_cap(const Port *port, - const Corner *corner, - const MinMax *min_max) + const MinMax *min_max) { + Sta *sta = Sta::sta(); + const Sdc *sdc = sta->cmdSdc(); float pin_cap, wire_cap; int fanout; - Sta::sta()->portExtCaps(port, corner, min_max, pin_cap, wire_cap, fanout); + sta->portExtCaps(port, min_max, sdc, pin_cap, wire_cap, fanout); return pin_cap; } void set_port_ext_pin_cap(const Port *port, const RiseFallBoth *rf, - const Corner *corner, const MinMaxAll *min_max, float cap) { - Sta::sta()->setPortExtPinCap(port, rf, corner, min_max, cap); + Sta *sta = Sta::sta(); + Sdc *sdc = sta->cmdSdc(); + sta->setPortExtPinCap(port, rf, min_max, cap, sdc); } float port_ext_wire_cap(const Port *port, - const Corner *corner, const MinMax *min_max) { + Sta *sta = Sta::sta(); + const Sdc *sdc = sta->cmdSdc(); float pin_cap, wire_cap; int fanout; - Sta::sta()->portExtCaps(port, corner, min_max, pin_cap, wire_cap, fanout); + sta->portExtCaps(port, min_max, sdc, pin_cap, wire_cap, fanout); return wire_cap; } void set_port_ext_wire_cap(const Port *port, - bool subtract_pin_cap, const RiseFallBoth *rf, - const Corner *corner, const MinMaxAll *min_max, float cap) { - Sta::sta()->setPortExtWireCap(port, subtract_pin_cap, rf, corner, min_max, cap); + Sta *sta = Sta::sta(); + Sdc *sdc = sta->cmdSdc(); + sta->setPortExtWireCap(port, rf, min_max, cap, sdc); } void set_port_ext_fanout_cmd(const Port *port, - int fanout, - const Corner *corner, - const MinMaxAll *min_max) + int fanout, + const MinMaxAll *min_max) { - Sta::sta()->setPortExtFanout(port, fanout, corner, min_max); + Sta *sta = Sta::sta(); + Sdc *sdc = sta->cmdSdc(); + sta->setPortExtFanout(port, fanout, min_max, sdc); } float port_ext_fanout(const Port *port, - const Corner *corner, const MinMax *min_max) { + Sta *sta = Sta::sta(); + const Sdc *sdc = sta->cmdSdc(); float pin_cap, wire_cap; int fanout; - Sta::sta()->portExtCaps(port, corner, min_max, pin_cap, wire_cap, fanout); + Sta::sta()->portExtCaps(port, min_max, sdc, pin_cap, wire_cap, fanout); return fanout; } void set_net_wire_cap(const Net *net, - bool subtract_pin_cap, - const Corner *corner, - const MinMaxAll *min_max, - float cap) + bool subtract_pin_cap, + const MinMaxAll *min_max, + float cap) { - Sta::sta()->setNetWireCap(net, subtract_pin_cap, corner, min_max, cap); + Sta *sta = Sta::sta(); + Sdc *sdc = sta->cmdSdc(); + sta->setNetWireCap(net, subtract_pin_cap, min_max, cap, sdc); } void set_wire_load_mode_cmd(const char *mode_name) { + Sta *sta = Sta::sta(); + Sdc *sdc = sta->cmdSdc(); WireloadMode mode = stringWireloadMode(mode_name); if (mode == WireloadMode::unknown) - Sta::sta()->report()->warn(2122, "unknown wire load mode"); + sta->report()->warn(2122, "unknown wire load mode"); else - Sta::sta()->setWireloadMode(mode); -} - -void -set_net_resistance(Net *net, - const MinMaxAll *min_max, - float res) -{ - Sta::sta()->setResistance(net, min_max, res); + sta->setWireloadMode(mode, sdc); } void set_wire_load_cmd(Wireload *wireload, - const MinMaxAll *min_max) + const MinMaxAll *min_max) { - Sta::sta()->setWireload(wireload, min_max); + Sta *sta = Sta::sta(); + Sdc *sdc = sta->cmdSdc(); + sta->setWireload(wireload, min_max, sdc); } void set_wire_load_selection_group_cmd(WireloadSelection *selection, - const MinMaxAll *min_max) + const MinMaxAll *min_max) { - Sta::sta()->setWireloadSelection(selection, min_max); + Sta *sta = Sta::sta(); + Sdc *sdc = sta->cmdSdc(); + sta->setWireloadSelection(selection, min_max, sdc); +} + +void +set_net_resistance(Net *net, + const MinMaxAll *min_max, + float res) +{ + Sta *sta = Sta::sta(); + Sdc *sdc = sta->cmdSdc(); + sta->setResistance(net, min_max, res, sdc); } void make_clock(const char *name, - PinSet *pins, - bool add_to_pins, - float period, - FloatSeq *waveform, - char *comment) + PinSet *pins, + bool add_to_pins, + float period, + FloatSeq *waveform, + char *comment) { - Sta::sta()->makeClock(name, pins, add_to_pins, period, waveform, comment); + Sta *sta = Sta::sta(); + const Mode *mode = sta->cmdMode(); + sta->makeClock(name, pins, add_to_pins, period, waveform, comment, mode); } void make_generated_clock(const char *name, - PinSet *pins, - bool add_to_pins, - Pin *src_pin, - Clock *master_clk, - int divide_by, - int multiply_by, - float duty_cycle, - bool invert, - bool combinational, - IntSeq *edges, - FloatSeq *edge_shifts, - char *comment) + PinSet *pins, + bool add_to_pins, + Pin *src_pin, + Clock *master_clk, + int divide_by, + int multiply_by, + float duty_cycle, + bool invert, + bool combinational, + IntSeq *edges, + FloatSeq *edge_shifts, + char *comment) { - Sta::sta()->makeGeneratedClock(name, pins, add_to_pins, - src_pin, master_clk, - divide_by, multiply_by, duty_cycle, invert, - combinational, edges, edge_shifts, - comment); + Sta *sta = Sta::sta(); + const Mode *mode = sta->cmdMode(); + sta->makeGeneratedClock(name, pins, add_to_pins, + src_pin, master_clk, + divide_by, multiply_by, duty_cycle, invert, + combinational, edges, edge_shifts, + comment, mode); } void remove_clock_cmd(Clock *clk) { - Sta::sta()->removeClock(clk); + Sta *sta = Sta::sta(); + Sdc *sdc = sta->cmdSdc(); + sta->removeClock(clk, sdc); } void set_propagated_clock_cmd(Clock *clk) { - Sta::sta()->setPropagatedClock(clk); + Sta *sta = Sta::sta(); + const Mode *mode = sta->cmdMode(); + sta->setPropagatedClock(clk, mode); } void set_propagated_clock_pin_cmd(Pin *pin) { - Sta::sta()->setPropagatedClock(pin); + Sta *sta = Sta::sta(); + const Mode *mode = sta->cmdMode(); + sta->setPropagatedClock(pin, mode); } void unset_propagated_clock_cmd(Clock *clk) { - Sta::sta()->removePropagatedClock(clk); + Sta *sta = Sta::sta(); + const Mode *mode = sta->cmdMode(); + sta->removePropagatedClock(clk, mode); } void unset_propagated_clock_pin_cmd(Pin *pin) { - Sta::sta()->removePropagatedClock(pin); + Sta *sta = Sta::sta(); + const Mode *mode = sta->cmdMode(); + sta->removePropagatedClock(pin, mode); } void set_clock_slew_cmd(Clock *clk, - const RiseFallBoth *rf, - const MinMaxAll *min_max, - float slew) + const RiseFallBoth *rf, + const MinMaxAll *min_max, + float slew) { - Sta::sta()->setClockSlew(clk, rf, min_max, slew); + Sta *sta = Sta::sta(); + Sdc *sdc = sta->cmdSdc(); + sta->setClockSlew(clk, rf, min_max, slew, sdc); } void unset_clock_slew_cmd(Clock *clk) { - Sta::sta()->removeClockSlew(clk); + Sta *sta = Sta::sta(); + Sdc *sdc = sta->cmdSdc(); + sta->removeClockSlew(clk, sdc); } void set_clock_latency_cmd(Clock *clk, - Pin *pin, - const RiseFallBoth *rf, - MinMaxAll *min_max, float delay) + Pin *pin, + const RiseFallBoth *rf, + MinMaxAll *min_max, float delay) { - Sta::sta()->setClockLatency(clk, pin, rf, min_max, delay); + Sta *sta = Sta::sta(); + Sdc *sdc = sta->cmdSdc(); + sta->setClockLatency(clk, pin, rf, min_max, delay, sdc); } void set_clock_insertion_cmd(Clock *clk, - Pin *pin, - const RiseFallBoth *rf, - const MinMaxAll *min_max, - const EarlyLateAll *early_late, - float delay) + Pin *pin, + const RiseFallBoth *rf, + const MinMaxAll *min_max, + const EarlyLateAll *early_late, + float delay) { - Sta::sta()->setClockInsertion(clk, pin, rf, min_max, early_late, delay); + Sta *sta = Sta::sta(); + Sdc *sdc = sta->cmdSdc(); + sta->setClockInsertion(clk, pin, rf, min_max, early_late, delay, sdc); } void unset_clock_latency_cmd(Clock *clk, - Pin *pin) + Pin *pin) { - Sta::sta()->removeClockLatency(clk, pin); + Sta *sta = Sta::sta(); + Sdc *sdc = sta->cmdSdc(); + sta->removeClockLatency(clk, pin, sdc); } void unset_clock_insertion_cmd(Clock *clk, - Pin *pin) + Pin *pin) { - Sta::sta()->removeClockInsertion(clk, pin); + Sta *sta = Sta::sta(); + Sdc *sdc = sta->cmdSdc(); + sta->removeClockInsertion(clk, pin, sdc); } void set_clock_uncertainty_clk(Clock *clk, - const SetupHoldAll *setup_hold, - float uncertainty) + const SetupHoldAll *setup_hold, + float uncertainty) { - Sta::sta()->setClockUncertainty(clk, setup_hold, uncertainty); + Sta *sta = Sta::sta(); + sta->setClockUncertainty(clk, setup_hold, uncertainty); } void unset_clock_uncertainty_clk(Clock *clk, - const SetupHoldAll *setup_hold) + const SetupHoldAll *setup_hold) { - Sta::sta()->removeClockUncertainty(clk, setup_hold); + Sta *sta = Sta::sta(); + sta->removeClockUncertainty(clk, setup_hold); } void set_clock_uncertainty_pin(Pin *pin, - const MinMaxAll *min_max, - float uncertainty) + const MinMaxAll *min_max, + float uncertainty) { - Sta::sta()->setClockUncertainty(pin, min_max, uncertainty); + Sta *sta = Sta::sta(); + Sdc *sdc = sta->cmdSdc(); + sta->setClockUncertainty(pin, min_max, uncertainty, sdc); } void unset_clock_uncertainty_pin(Pin *pin, - const MinMaxAll *min_max) + const MinMaxAll *min_max) { - Sta::sta()->removeClockUncertainty(pin, min_max); + Sta *sta = Sta::sta(); + Sdc *sdc = sta->cmdSdc(); + sta->removeClockUncertainty(pin, min_max, sdc); } void set_inter_clock_uncertainty(Clock *from_clk, - const RiseFallBoth *from_tr, - Clock *to_clk, - const RiseFallBoth *to_tr, - const MinMaxAll *min_max, - float uncertainty) + const RiseFallBoth *from_tr, + Clock *to_clk, + const RiseFallBoth *to_tr, + const MinMaxAll *min_max, + float uncertainty) { - Sta::sta()->setClockUncertainty(from_clk, from_tr, to_clk, to_tr, min_max, - uncertainty); + Sta *sta = Sta::sta(); + Sdc *sdc = sta->cmdSdc(); + sta->setClockUncertainty(from_clk, from_tr, to_clk, to_tr, min_max, + uncertainty, sdc); } void unset_inter_clock_uncertainty(Clock *from_clk, - const RiseFallBoth *from_tr, - Clock *to_clk, - const RiseFallBoth *to_tr, - const MinMaxAll *min_max) + const RiseFallBoth *from_tr, + Clock *to_clk, + const RiseFallBoth *to_tr, + const MinMaxAll *min_max) { - Sta::sta()->removeClockUncertainty(from_clk, from_tr, to_clk, to_tr, min_max); + Sta *sta = Sta::sta(); + Sdc *sdc = sta->cmdSdc(); + sta->removeClockUncertainty(from_clk, from_tr, to_clk, to_tr, min_max, sdc); } void set_clock_gating_check_cmd(const RiseFallBoth *rf, - const SetupHold *setup_hold, - float margin) + const SetupHold *setup_hold, + float margin) { - Sta::sta()->setClockGatingCheck(rf, setup_hold, margin); + Sta *sta = Sta::sta(); + Sdc *sdc = sta->cmdSdc(); + sta->setClockGatingCheck(rf, setup_hold, margin, sdc); } void set_clock_gating_check_clk_cmd(Clock *clk, - const RiseFallBoth *rf, - const SetupHold *setup_hold, - float margin) + const RiseFallBoth *rf, + const SetupHold *setup_hold, + float margin) { - Sta::sta()->setClockGatingCheck(clk, rf, setup_hold, margin); + Sta *sta = Sta::sta(); + Sdc *sdc = sta->cmdSdc(); + sta->setClockGatingCheck(clk, rf, setup_hold, margin, sdc); } void set_clock_gating_check_pin_cmd(Pin *pin, - const RiseFallBoth *rf, - const SetupHold *setup_hold, - float margin, - LogicValue active_value) + const RiseFallBoth *rf, + const SetupHold *setup_hold, + float margin, + LogicValue active_value) { - Sta::sta()->setClockGatingCheck(pin, rf, setup_hold, margin, active_value); + Sta *sta = Sta::sta(); + Sdc *sdc = sta->cmdSdc(); + sta->setClockGatingCheck(pin, rf, setup_hold, margin, active_value, sdc); } void set_clock_gating_check_instance_cmd(Instance *inst, - const RiseFallBoth *rf, - const SetupHold *setup_hold, - float margin, - LogicValue active_value) + const RiseFallBoth *rf, + const SetupHold *setup_hold, + float margin, + LogicValue active_value) { - Sta::sta()->setClockGatingCheck(inst, rf, setup_hold, margin, active_value); + Sta *sta = Sta::sta(); + Sdc *sdc = sta->cmdSdc(); + sta->setClockGatingCheck(inst, rf, setup_hold, margin, active_value, sdc); } void set_data_check_cmd(Pin *from, - const RiseFallBoth *from_rf, - Pin *to, - const RiseFallBoth *to_rf, - Clock *clk, - const SetupHoldAll *setup_hold, - float margin) + const RiseFallBoth *from_rf, + Pin *to, + const RiseFallBoth *to_rf, + Clock *clk, + const SetupHoldAll *setup_hold, + float margin) { - Sta::sta()->setDataCheck(from, from_rf, to, to_rf, clk, setup_hold, margin); + Sta *sta = Sta::sta(); + Sdc *sdc = sta->cmdSdc(); + sta->setDataCheck(from, from_rf, to, to_rf, clk, setup_hold, margin, sdc); } void unset_data_check_cmd(Pin *from, - const RiseFallBoth *from_tr, - Pin *to, - const RiseFallBoth *to_tr, - Clock *clk, - const SetupHoldAll *setup_hold) + const RiseFallBoth *from_tr, + Pin *to, + const RiseFallBoth *to_tr, + Clock *clk, + const SetupHoldAll *setup_hold) { - Sta::sta()->removeDataCheck(from, from_tr, to, to_tr, clk, setup_hold); + Sta *sta = Sta::sta(); + Sdc *sdc = sta->cmdSdc(); + sta->removeDataCheck(from, from_tr, to, to_tr, clk, setup_hold, sdc); } void set_input_delay_cmd(Pin *pin, - RiseFallBoth *rf, - Clock *clk, - RiseFall *clk_rf, - Pin *ref_pin, - bool source_latency_included, - bool network_latency_included, - MinMaxAll *min_max, - bool add, - float delay) + RiseFallBoth *rf, + Clock *clk, + RiseFall *clk_rf, + Pin *ref_pin, + bool source_latency_included, + bool network_latency_included, + MinMaxAll *min_max, + bool add, + float delay) { - Sta::sta()->setInputDelay(pin, rf, clk, clk_rf, ref_pin, - source_latency_included, network_latency_included, - min_max, add, delay); + Sta *sta = Sta::sta(); + Sdc *sdc = sta->cmdSdc(); + sta->setInputDelay(pin, rf, clk, clk_rf, ref_pin, + source_latency_included, network_latency_included, + min_max, add, delay, sdc); } void unset_input_delay_cmd(Pin *pin, - RiseFallBoth *rf, - Clock *clk, - RiseFall *clk_rf, - MinMaxAll *min_max) + RiseFallBoth *rf, + Clock *clk, + RiseFall *clk_rf, + MinMaxAll *min_max) { - Sta::sta()->removeInputDelay(pin, rf, clk, clk_rf, min_max); + Sta *sta = Sta::sta(); + Sdc *sdc = sta->cmdSdc(); + sta->removeInputDelay(pin, rf, clk, clk_rf, min_max, sdc); } void set_output_delay_cmd(Pin *pin, - const RiseFallBoth *rf, - Clock *clk, - const RiseFall *clk_rf, - Pin *ref_pin, - bool source_latency_included, - bool network_latency_included, - const MinMaxAll *min_max, - bool add, - float delay) + const RiseFallBoth *rf, + Clock *clk, + const RiseFall *clk_rf, + Pin *ref_pin, + bool source_latency_included, + bool network_latency_included, + const MinMaxAll *min_max, + bool add, + float delay) { - Sta::sta()->setOutputDelay(pin, rf, clk, clk_rf, ref_pin, - source_latency_included, network_latency_included, - min_max, add, delay); + Sta *sta = Sta::sta(); + Sdc *sdc = sta->cmdSdc(); + sta->setOutputDelay(pin, rf, clk, clk_rf, ref_pin, + source_latency_included, network_latency_included, + min_max, add, delay, sdc); } void unset_output_delay_cmd(Pin *pin, - RiseFallBoth *rf, - Clock *clk, - RiseFall *clk_rf, - MinMaxAll *min_max) + RiseFallBoth *rf, + Clock *clk, + RiseFall *clk_rf, + MinMaxAll *min_max) { - Sta::sta()->removeOutputDelay(pin, rf, clk, clk_rf, min_max); + Sta *sta = Sta::sta(); + Sdc *sdc = sta->cmdSdc(); + sta->removeOutputDelay(pin, rf, clk, clk_rf, min_max, sdc); } void disable_cell(LibertyCell *cell, - LibertyPort *from, - LibertyPort *to) + LibertyPort *from, + LibertyPort *to) { - Sta::sta()->disable(cell, from, to); + Sta *sta = Sta::sta(); + Sdc *sdc = sta->cmdSdc(); + sta->disable(cell, from, to, sdc); } void unset_disable_cell(LibertyCell *cell, - LibertyPort *from, - LibertyPort *to) + LibertyPort *from, + LibertyPort *to) { - Sta::sta()->removeDisable(cell, from, to); + Sta *sta = Sta::sta(); + Sdc *sdc = sta->cmdSdc(); + sta->removeDisable(cell, from, to, sdc); } void disable_lib_port(LibertyPort *port) { - Sta::sta()->disable(port); + Sta *sta = Sta::sta(); + Sdc *sdc = sta->cmdSdc(); + sta->disable(port, sdc); } void unset_disable_lib_port(LibertyPort *port) { - Sta::sta()->removeDisable(port); + Sta *sta = Sta::sta(); + Sdc *sdc = sta->cmdSdc(); + sta->removeDisable(port, sdc); } void disable_port(Port *port) { - Sta::sta()->disable(port); + Sta *sta = Sta::sta(); + Sdc *sdc = sta->cmdSdc(); + sta->disable(port, sdc); } void unset_disable_port(Port *port) { - Sta::sta()->removeDisable(port); + Sta *sta = Sta::sta(); + Sdc *sdc = sta->cmdSdc(); + sta->removeDisable(port, sdc); } void disable_instance(Instance *instance, - LibertyPort *from, - LibertyPort *to) + LibertyPort *from, + LibertyPort *to) { - Sta::sta()->disable(instance, from, to); + Sta *sta = Sta::sta(); + Sdc *sdc = sta->cmdSdc(); + sta->disable(instance, from, to, sdc); } void unset_disable_instance(Instance *instance, - LibertyPort *from, - LibertyPort *to) + LibertyPort *from, + LibertyPort *to) { - Sta::sta()->removeDisable(instance, from, to); + Sta *sta = Sta::sta(); + Sdc *sdc = sta->cmdSdc(); + sta->removeDisable(instance, from, to, sdc); } void disable_pin(Pin *pin) { - Sta::sta()->disable(pin); + Sta *sta = Sta::sta(); + Sdc *sdc = sta->cmdSdc(); + sta->disable(pin, sdc); } void unset_disable_pin(Pin *pin) { - Sta::sta()->removeDisable(pin); + Sta *sta = Sta::sta(); + Sdc *sdc = sta->cmdSdc(); + sta->removeDisable(pin, sdc); } void disable_edge(Edge *edge) { - Sta::sta()->disable(edge); + Sta *sta = Sta::sta(); + Sdc *sdc = sta->cmdSdc(); + sta->disable(edge, sdc); } void unset_disable_edge(Edge *edge) { - Sta::sta()->removeDisable(edge); + Sta *sta = Sta::sta(); + Sdc *sdc = sta->cmdSdc(); + sta->removeDisable(edge, sdc); } void disable_timing_arc_set(TimingArcSet *arc_set) { - Sta::sta()->disable(arc_set); + Sta *sta = Sta::sta(); + Sdc *sdc = sta->cmdSdc(); + sta->disable(arc_set, sdc); } void unset_disable_timing_arc_set(TimingArcSet *arc_set) { - Sta::sta()->removeDisable(arc_set); + Sta *sta = Sta::sta(); + Sdc *sdc = sta->cmdSdc(); + sta->removeDisable(arc_set, sdc); } void disable_clock_gating_check_inst(Instance *inst) { - Sta::sta()->disableClockGatingCheck(inst); + Sta *sta = Sta::sta(); + Sdc *sdc = sta->cmdSdc(); + sta->disableClockGatingCheck(inst, sdc); } void disable_clock_gating_check_pin(Pin *pin) { - Sta::sta()->disableClockGatingCheck(pin); + Sta *sta = Sta::sta(); + Sdc *sdc = sta->cmdSdc(); + sta->disableClockGatingCheck(pin, sdc); } void unset_disable_clock_gating_check_inst(Instance *inst) { - Sta::sta()->removeDisableClockGatingCheck(inst); + Sta *sta = Sta::sta(); + Sdc *sdc = sta->cmdSdc(); + sta->removeDisableClockGatingCheck(inst, sdc); } void unset_disable_clock_gating_check_pin(Pin *pin) { - Sta::sta()->removeDisableClockGatingCheck(pin); + Sta *sta = Sta::sta(); + Sdc *sdc = sta->cmdSdc(); + sta->removeDisableClockGatingCheck(pin, sdc); } EdgeSeq disabled_edges_sorted() { - return Sta::sta()->disabledEdgesSorted(); + Sta *sta = Sta::sta(); + const Mode *mode = sta->cmdMode(); + return sta->disabledEdgesSorted(mode); } bool timing_arc_disabled(Edge *edge, - TimingArc *arc) + TimingArc *arc) { - Graph *graph = Sta::sta()->graph(); - return !searchThru(edge, arc, graph); + Sta *sta = Sta::sta(); + const Mode *mode = sta->cmdMode(); + return !searchThru(edge, arc, mode); } void make_false_path(ExceptionFrom *from, - ExceptionThruSeq *thrus, - ExceptionTo *to, - const MinMaxAll *min_max, - const char *comment) + ExceptionThruSeq *thrus, + ExceptionTo *to, + const MinMaxAll *min_max, + const char *comment) { - Sta::sta()->makeFalsePath(from, thrus, to, min_max, comment); + Sta *sta = Sta::sta(); + Sdc *sdc = sta->cmdSdc(); + sta->makeFalsePath(from, thrus, to, min_max, comment, sdc); } void make_multicycle_path(ExceptionFrom *from, - ExceptionThruSeq *thrus, - ExceptionTo *to, - const MinMaxAll *min_max, - bool use_end_clk, - int path_multiplier, - const char *comment) + ExceptionThruSeq *thrus, + ExceptionTo *to, + const MinMaxAll *min_max, + bool use_end_clk, + int path_multiplier, + const char *comment) { - Sta::sta()->makeMulticyclePath(from, thrus, to, min_max, use_end_clk, - path_multiplier, comment); + Sta *sta = Sta::sta(); + Sdc *sdc = sta->cmdSdc(); + sta->makeMulticyclePath(from, thrus, to, min_max, use_end_clk, + path_multiplier, comment, sdc); } void make_path_delay(ExceptionFrom *from, - ExceptionThruSeq *thrus, - ExceptionTo *to, - const MinMax *min_max, - bool ignore_clk_latency, - bool break_path, - float delay, + ExceptionThruSeq *thrus, + ExceptionTo *to, + const MinMax *min_max, + bool ignore_clk_latency, + bool break_path, + float delay, const char *comment) { - Sta::sta()->makePathDelay(from, thrus, to, min_max, - ignore_clk_latency, break_path, - delay, comment); + Sta *sta = Sta::sta(); + Sdc *sdc = sta->cmdSdc(); + sta->makePathDelay(from, thrus, to, min_max, + ignore_clk_latency, break_path, + delay, comment, sdc); } void reset_path_cmd(ExceptionFrom * - from, ExceptionThruSeq *thrus, - ExceptionTo *to, - const MinMaxAll *min_max) + from, ExceptionThruSeq *thrus, + ExceptionTo *to, + const MinMaxAll *min_max) { - Sta::sta()->resetPath(from, thrus, to, min_max); + Sta *sta = Sta::sta(); + Sdc *sdc = sta->cmdSdc(); + sta->resetPath(from, thrus, to, min_max, sdc); // from/to and thru are owned and deleted by the caller. // ExceptionThruSeq thrus arg is made by TclListSeqExceptionThru // in the swig converter so it is deleted here. @@ -720,404 +852,494 @@ reset_path_cmd(ExceptionFrom * void make_group_path(const char *name, - bool is_default, - ExceptionFrom *from, - ExceptionThruSeq *thrus, - ExceptionTo *to, - const char *comment) + bool is_default, + ExceptionFrom *from, + ExceptionThruSeq *thrus, + ExceptionTo *to, + const char *comment) { + Sta *sta = Sta::sta(); + Sdc *sdc = sta->cmdSdc(); if (name[0] == '\0') name = nullptr; - Sta::sta()->makeGroupPath(name, is_default, from, thrus, to, comment); + sta->makeGroupPath(name, is_default, from, thrus, to, comment, sdc); } bool is_path_group_name(const char *name) { - return Sta::sta()->isPathGroupName(name); + Sta *sta = Sta::sta(); + Sdc *sdc = sta->cmdSdc(); + return Sta::sta()->isPathGroupName(name, sdc); } ExceptionFrom * make_exception_from(PinSet *from_pins, - ClockSet *from_clks, - InstanceSet *from_insts, - const RiseFallBoth *from_tr) + ClockSet *from_clks, + InstanceSet *from_insts, + const RiseFallBoth *from_rf) { - return Sta::sta()->makeExceptionFrom(from_pins, from_clks, from_insts, - from_tr); + Sta *sta = Sta::sta(); + Sdc *sdc = sta->cmdSdc(); + return sta->makeExceptionFrom(from_pins, from_clks, from_insts, + from_rf, sdc); } void delete_exception_from(ExceptionFrom *from) { - Sta::sta()->deleteExceptionFrom(from); + Sta *sta = Sta::sta(); + sta->deleteExceptionFrom(from); } void check_exception_from_pins(ExceptionFrom *from, - const char *file, - int line) + const char *file, + int line) { - Sta::sta()->checkExceptionFromPins(from, file, line); + Sta *sta = Sta::sta(); + const Sdc *sdc = sta->cmdSdc(); + sta->checkExceptionFromPins(from, file, line, sdc); } ExceptionThru * make_exception_thru(PinSet *pins, - NetSet *nets, - InstanceSet *insts, - const RiseFallBoth *rf) + NetSet *nets, + InstanceSet *insts, + const RiseFallBoth *rf) { - return Sta::sta()->makeExceptionThru(pins, nets, insts, rf); + Sta *sta = Sta::sta(); + const Sdc *sdc = sta->cmdSdc(); + return sta->makeExceptionThru(pins, nets, insts, rf, sdc); } void delete_exception_thru(ExceptionThru *thru) { - Sta::sta()->deleteExceptionThru(thru); + Sta *sta = Sta::sta(); + sta->deleteExceptionThru(thru); } ExceptionTo * make_exception_to(PinSet *to_pins, - ClockSet *to_clks, - InstanceSet *to_insts, - const RiseFallBoth *rf, - RiseFallBoth *end_rf) + ClockSet *to_clks, + InstanceSet *to_insts, + const RiseFallBoth *rf, + RiseFallBoth *end_rf) { - return Sta::sta()->makeExceptionTo(to_pins, to_clks, to_insts, rf, end_rf); + Sta *sta = Sta::sta(); + const Sdc *sdc = sta->cmdSdc(); + return sta->makeExceptionTo(to_pins, to_clks, to_insts, rf, end_rf, sdc); } void delete_exception_to(ExceptionTo *to) { - Sta::sta()->deleteExceptionTo(to); + Sta *sta = Sta::sta(); + sta->deleteExceptionTo(to); } void check_exception_to_pins(ExceptionTo *to, - const char *file, - int line) + const char *file, + int line) { - Sta::sta()->checkExceptionToPins(to, file, line); + Sta *sta = Sta::sta(); + const Sdc *sdc = sta->cmdSdc(); + sta->checkExceptionToPins(to, file, line, sdc); } +//////////////////////////////////////////////////////////////// + ClockGroups * make_clock_groups(const char *name, - bool logically_exclusive, - bool physically_exclusive, - bool asynchronous, - bool allow_paths, - const char *comment) + bool logically_exclusive, + bool physically_exclusive, + bool asynchronous, + bool allow_paths, + const char *comment) { - return Sta::sta()->makeClockGroups(name, logically_exclusive, - physically_exclusive, asynchronous, - allow_paths, comment); + Sta *sta = Sta::sta(); + Sdc *sdc = sta->cmdSdc(); + return sta->makeClockGroups(name, logically_exclusive, + physically_exclusive, asynchronous, + allow_paths, comment, sdc); } void clock_groups_make_group(ClockGroups *clk_groups, - ClockSet *clks) + ClockSet *clks) { - Sta::sta()->makeClockGroup(clk_groups, clks); + Sta *sta = Sta::sta(); + Sdc *sdc = sta->cmdSdc(); + sta->makeClockGroup(clk_groups, clks, sdc); } void unset_clock_groups_logically_exclusive(const char *name) { - Sta::sta()->removeClockGroupsLogicallyExclusive(name); + Sta *sta = Sta::sta(); + Sdc *sdc = sta->cmdSdc(); + sta->removeClockGroupsLogicallyExclusive(name, sdc); } void unset_clock_groups_physically_exclusive(const char *name) { - Sta::sta()->removeClockGroupsPhysicallyExclusive(name); + Sta *sta = Sta::sta(); + Sdc *sdc = sta->cmdSdc(); + sta->removeClockGroupsPhysicallyExclusive(name, sdc); } void unset_clock_groups_asynchronous(const char *name) { - Sta::sta()->removeClockGroupsAsynchronous(name); + Sta *sta = Sta::sta(); + Sdc *sdc = sta->cmdSdc(); + sta->removeClockGroupsAsynchronous(name, sdc); } // Debugging function. bool same_clk_group(Clock *clk1, - Clock *clk2) + Clock *clk2) { Sta *sta = Sta::sta(); - Sdc *sdc = sta->sdc(); + Sdc *sdc = sta->cmdSdc(); return sdc->sameClockGroupExplicit(clk1, clk2); } void set_clock_sense_cmd(PinSet *pins, - ClockSet *clks, - bool positive, - bool negative, - bool stop_propagation) + ClockSet *clks, + bool positive, + bool negative, + bool stop_propagation) { Sta *sta = Sta::sta(); + Sdc *sdc = sta->cmdSdc(); if (positive) - sta->setClockSense(pins, clks, ClockSense::positive); + sta->setClockSense(pins, clks, ClockSense::positive, sdc); else if (negative) - sta->setClockSense(pins, clks, ClockSense::negative); + sta->setClockSense(pins, clks, ClockSense::negative, sdc); else if (stop_propagation) - sta->setClockSense(pins, clks, ClockSense::stop); + sta->setClockSense(pins, clks, ClockSense::stop, sdc); else sta->report()->critical(2123, "unknown clock sense"); } void set_input_slew_cmd(Port *port, - const RiseFallBoth *rf, - const MinMaxAll *min_max, - float slew) + const RiseFallBoth *rf, + const MinMaxAll *min_max, + float slew) { - Sta::sta()->setInputSlew(port, rf, min_max, slew); + Sta *sta = Sta::sta(); + Sdc *sdc = sta->cmdSdc(); + sta->setInputSlew(port, rf, min_max, slew, sdc); } void set_drive_cell_cmd(LibertyLibrary *library, - LibertyCell *cell, - Port *port, - LibertyPort *from_port, - float from_slew_rise, - float from_slew_fall, - LibertyPort *to_port, - const RiseFallBoth *rf, - const MinMaxAll *min_max) + LibertyCell *cell, + Port *port, + LibertyPort *from_port, + float from_slew_rise, + float from_slew_fall, + LibertyPort *to_port, + const RiseFallBoth *rf, + const MinMaxAll *min_max) { + Sta *sta = Sta::sta(); + Sdc *sdc = sta->cmdSdc(); float from_slews[RiseFall::index_count]; from_slews[RiseFall::riseIndex()] = from_slew_rise; from_slews[RiseFall::fallIndex()] = from_slew_fall; - Sta::sta()->setDriveCell(library, cell, port, from_port, from_slews, - to_port, rf, min_max); + sta->setDriveCell(library, cell, port, from_port, from_slews, + to_port, rf, min_max, sdc); } void set_drive_resistance_cmd(Port *port, - const RiseFallBoth *rf, - const MinMaxAll *min_max, - float res) + const RiseFallBoth *rf, + const MinMaxAll *min_max, + float res) { - Sta::sta()->setDriveResistance(port, rf, min_max, res); + Sta *sta = Sta::sta(); + Sdc *sdc = sta->cmdSdc(); + sta->setDriveResistance(port, rf, min_max, res, sdc); } void set_slew_limit_clk(Clock *clk, - const RiseFallBoth *rf, - PathClkOrData clk_data, - const MinMax *min_max, - float slew) + const RiseFallBoth *rf, + PathClkOrData clk_data, + const MinMax *min_max, + float slew) { - Sta::sta()->setSlewLimit(clk, rf, clk_data, min_max, slew); + Sta *sta = Sta::sta(); + Sdc *sdc = sta->cmdSdc(); + sta->setSlewLimit(clk, rf, clk_data, min_max, slew, sdc); } void set_slew_limit_port(Port *port, - const MinMax *min_max, - float slew) + const MinMax *min_max, + float slew) { - Sta::sta()->setSlewLimit(port, min_max, slew); + Sta *sta = Sta::sta(); + Sdc *sdc = sta->cmdSdc(); + sta->setSlewLimit(port, min_max, slew, sdc); } void set_slew_limit_cell(Cell *cell, - const MinMax *min_max, - float slew) + const MinMax *min_max, + float slew) { - Sta::sta()->setSlewLimit(cell, min_max, slew); + Sta *sta = Sta::sta(); + Sdc *sdc = sta->cmdSdc(); + sta->setSlewLimit(cell, min_max, slew, sdc); } void set_port_capacitance_limit(Port *port, - const MinMax *min_max, - float cap) + const MinMax *min_max, + float cap) { - Sta::sta()->setCapacitanceLimit(port, min_max, cap); + Sta *sta = Sta::sta(); + Sdc *sdc = sta->cmdSdc(); + sta->setCapacitanceLimit(port, min_max, cap, sdc); } void set_pin_capacitance_limit(Pin *pin, - const MinMax *min_max, - float cap) + const MinMax *min_max, + float cap) { - Sta::sta()->setCapacitanceLimit(pin, min_max, cap); + Sta *sta = Sta::sta(); + Sdc *sdc = sta->cmdSdc(); + sta->setCapacitanceLimit(pin, min_max, cap, sdc); } void set_cell_capacitance_limit(Cell *cell, - const MinMax *min_max, - float cap) + const MinMax *min_max, + float cap) { - Sta::sta()->setCapacitanceLimit(cell, min_max, cap); + Sta *sta = Sta::sta(); + Sdc *sdc = sta->cmdSdc(); + sta->setCapacitanceLimit(cell, min_max, cap, sdc); } void set_latch_borrow_limit_pin(Pin *pin, - float limit) + float limit) { - Sta::sta()->setLatchBorrowLimit(pin, limit); + Sta *sta = Sta::sta(); + Sdc *sdc = sta->cmdSdc(); + sta->setLatchBorrowLimit(pin, limit, sdc); } void set_latch_borrow_limit_inst(Instance *inst, - float limit) + float limit) { - Sta::sta()->setLatchBorrowLimit(inst, limit); + Sta *sta = Sta::sta(); + Sdc *sdc = sta->cmdSdc(); + sta->setLatchBorrowLimit(inst, limit, sdc); } void set_latch_borrow_limit_clk(Clock *clk, float limit) { - Sta::sta()->setLatchBorrowLimit(clk, limit); + Sta *sta = Sta::sta(); + Sdc *sdc = sta->cmdSdc(); + sta->setLatchBorrowLimit(clk, limit, sdc); } void set_min_pulse_width_global(const RiseFallBoth *rf, - float min_width) + float min_width) { - Sta::sta()->setMinPulseWidth(rf, min_width); + Sta *sta = Sta::sta(); + Sdc *sdc = sta->cmdSdc(); + sta->setMinPulseWidth(rf, min_width, sdc); } void set_min_pulse_width_pin(Pin *pin, - const RiseFallBoth *rf, - float min_width) + const RiseFallBoth *rf, + float min_width) { - Sta::sta()->setMinPulseWidth(pin, rf, min_width); + Sta *sta = Sta::sta(); + Sdc *sdc = sta->cmdSdc(); + sta->setMinPulseWidth(pin, rf, min_width, sdc); } void set_min_pulse_width_clk(Clock *clk, - const RiseFallBoth *rf, - float min_width) + const RiseFallBoth *rf, + float min_width) { - Sta::sta()->setMinPulseWidth(clk, rf, min_width); + Sta *sta = Sta::sta(); + Sdc *sdc = sta->cmdSdc(); + sta->setMinPulseWidth(clk, rf, min_width, sdc); } void set_min_pulse_width_inst(Instance *inst, - const RiseFallBoth *rf, - float min_width) + const RiseFallBoth *rf, + float min_width) { - Sta::sta()->setMinPulseWidth(inst, rf, min_width); + Sta *sta = Sta::sta(); + Sdc *sdc = sta->cmdSdc(); + sta->setMinPulseWidth(inst, rf, min_width, sdc); } void set_max_area_cmd(float area) { - Sta::sta()->setMaxArea(area); + Sta *sta = Sta::sta(); + Sdc *sdc = sta->cmdSdc(); + sta->setMaxArea(area, sdc); } void set_port_fanout_limit(Port *port, - const MinMax *min_max, - float fanout) + const MinMax *min_max, + float fanout) { - Sta::sta()->setFanoutLimit(port, min_max, fanout); + Sta *sta = Sta::sta(); + Sdc *sdc = sta->cmdSdc(); + sta->setFanoutLimit(port, min_max, fanout, sdc); } void set_cell_fanout_limit(Cell *cell, - const MinMax *min_max, - float fanout) + const MinMax *min_max, + float fanout) { - Sta::sta()->setFanoutLimit(cell, min_max, fanout); + Sta *sta = Sta::sta(); + Sdc *sdc = sta->cmdSdc(); + sta->setFanoutLimit(cell, min_max, fanout, sdc); } void set_logic_value_cmd(Pin *pin, - LogicValue value) + LogicValue value) { - Sta::sta()->setLogicValue(pin, value); + Sta *sta = Sta::sta(); + Mode *mode = sta->cmdMode(); + sta->setLogicValue(pin, value, mode); } void set_case_analysis_cmd(Pin *pin, - LogicValue value) + LogicValue value) { - Sta::sta()->setCaseAnalysis(pin, value); + Sta *sta = Sta::sta(); + Mode *mode = sta->cmdMode(); + sta->setCaseAnalysis(pin, value, mode); } void unset_case_analysis_cmd(Pin *pin) { - Sta::sta()->removeCaseAnalysis(pin); + Sta *sta = Sta::sta(); + Mode *mode = sta->cmdMode(); + sta->removeCaseAnalysis(pin, mode); } void set_timing_derate_cmd(TimingDerateType type, - PathClkOrData clk_data, - const RiseFallBoth *rf, - const EarlyLate *early_late, - float derate) + PathClkOrData clk_data, + const RiseFallBoth *rf, + const EarlyLate *early_late, + float derate) { - Sta::sta()->setTimingDerate(type, clk_data, rf, early_late, derate); + Sta *sta = Sta::sta(); + Sdc *sdc = sta->cmdSdc(); + sta->setTimingDerate(type, clk_data, rf, early_late, derate, sdc); } void set_timing_derate_net_cmd(const Net *net, - PathClkOrData clk_data, - const RiseFallBoth *rf, - const EarlyLate *early_late, - float derate) + PathClkOrData clk_data, + const RiseFallBoth *rf, + const EarlyLate *early_late, + float derate) { - Sta::sta()->setTimingDerate(net, clk_data, rf, early_late, derate); + Sta *sta = Sta::sta(); + Sdc *sdc = sta->cmdSdc(); + sta->setTimingDerate(net, clk_data, rf, early_late, derate, sdc); } void set_timing_derate_inst_cmd(const Instance *inst, - TimingDerateCellType type, - PathClkOrData clk_data, - const RiseFallBoth *rf, - const EarlyLate *early_late, - float derate) + TimingDerateCellType type, + PathClkOrData clk_data, + const RiseFallBoth *rf, + const EarlyLate *early_late, + float derate) { - Sta::sta()->setTimingDerate(inst, type, clk_data, rf, early_late, derate); + Sta *sta = Sta::sta(); + Sdc *sdc = sta->cmdSdc(); + sta->setTimingDerate(inst, type, clk_data, rf, early_late, derate, sdc); } void set_timing_derate_cell_cmd(const LibertyCell *cell, - TimingDerateCellType type, - PathClkOrData clk_data, - const RiseFallBoth *rf, - const EarlyLate *early_late, - float derate) + TimingDerateCellType type, + PathClkOrData clk_data, + const RiseFallBoth *rf, + const EarlyLate *early_late, + float derate) { - Sta::sta()->setTimingDerate(cell, type, clk_data, rf, early_late, derate); + Sta *sta = Sta::sta(); + Sdc *sdc = sta->cmdSdc(); + sta->setTimingDerate(cell, type, clk_data, rf, early_late, derate, sdc); } void unset_timing_derate_cmd() { - Sta::sta()->unsetTimingDerate(); + Sta *sta = Sta::sta(); + Sdc *sdc = sta->cmdSdc(); + sta->unsetTimingDerate(sdc); } Clock * find_clock(const char *name) { - return Sta::sta()->sdc()->findClock(name); + Sta *sta = Sta::sta(); + Sdc *sdc = sta->cmdSdc(); + return sdc->findClock(name); } bool is_clock_src(const Pin *pin) { - return Sta::sta()->isClockSrc(pin); + Sta *sta = Sta::sta(); + const Sdc *sdc = sta->cmdSdc(); + return sta->isClockSrc(pin, sdc); } Clock * default_arrival_clock() { - return Sta::sta()->sdc()->defaultArrivalClock(); + Sta *sta = Sta::sta(); + const Sdc *sdc = sta->cmdSdc(); + return sdc->defaultArrivalClock(); } ClockSeq find_clocks_matching(const char *pattern, - bool regexp, - bool nocase) + bool regexp, + bool nocase) { Sta *sta = Sta::sta(); - Sdc *sdc = sta->sdc(); + const Sdc *sdc = sta->cmdSdc(); PatternMatch matcher(pattern, regexp, nocase, sta->tclInterp()); return sdc->findClocksMatching(&matcher); } @@ -1130,97 +1352,128 @@ update_generated_clks() bool is_clock(Pin *pin) -{ - return Sta::sta()->isClock(pin); -} - -bool -is_ideal_clock(Pin *pin) -{ - return Sta::sta()->isIdealClock(pin); -} - -bool -is_clock_search(const Pin *pin) { Sta *sta = Sta::sta(); - Graph *graph = sta->graph(); - Search *search = sta->search(); - Vertex *vertex, *bidirect_drvr_vertex; - graph->pinVertices(pin, vertex, bidirect_drvr_vertex); - return search->isClock(vertex); -} - -bool -is_genclk_src(const Pin *pin) -{ - Sta *sta = Sta::sta(); - Graph *graph = sta->graph(); - Search *search = sta->search(); - Vertex *vertex, *bidirect_drvr_vertex; - graph->pinVertices(pin, vertex, bidirect_drvr_vertex); - return search->isGenClkSrc(vertex); -} - -bool -pin_is_constrained(Pin *pin) -{ - return Sta::sta()->sdc()->isConstrained(pin); -} - -bool -instance_is_constrained(Instance *inst) -{ - return Sta::sta()->sdc()->isConstrained(inst); -} - -bool -net_is_constrained(Net *net) -{ - return Sta::sta()->sdc()->isConstrained(net); + Mode *mode = sta->cmdMode(); + return sta->isClock(pin, mode); } +// variable sta_clock_through_tristate_enabled bool clk_thru_tristate_enabled() { return Sta::sta()->clkThruTristateEnabled(); } +// variable sta_clock_through_tristate_enabled void set_clk_thru_tristate_enabled(bool enabled) { Sta::sta()->setClkThruTristateEnabled(enabled); } -void -remove_constraints() -{ - Sta::sta()->removeConstraints(); -} - PortSeq all_inputs_cmd(bool no_clocks) { Sta *sta = Sta::sta(); + const Sdc *sdc = sta->cmdSdc(); sta->ensureLinked(); - return sta->sdc()->allInputs(no_clocks); + return sdc->allInputs(no_clocks); } PortSeq all_outputs_cmd() { Sta *sta = Sta::sta(); + const Sdc *sdc = sta->cmdSdc(); sta->ensureLinked(); - return sta->sdc()->allOutputs(); + return sdc->allOutputs(); } -template Vector -filter_objects(const char *property, - const char *op, - const char *pattern, - Vector *objects) +//////////////////////////////////////////////////////////////// + +// all_register variants + +InstanceSet +find_register_instances(ClockSet *clks, + const RiseFallBoth *clk_tr, + bool edge_triggered, + bool latches) { - Vector filtered_objects; + Sta *sta = Sta::sta(); + Mode *mode = sta->cmdMode(); + InstanceSet insts = sta->findRegisterInstances(clks, clk_tr, + edge_triggered, + latches, mode); + delete clks; + return insts; +} + +PinSet +find_register_data_pins(ClockSet *clks, + const RiseFallBoth *clk_tr, + bool edge_triggered, + bool latches) +{ + Sta *sta = Sta::sta(); + Mode *mode = sta->cmdMode(); + PinSet pins = sta->findRegisterDataPins(clks, clk_tr, edge_triggered, + latches, mode); + delete clks; + return pins; +} + +PinSet +find_register_clk_pins(ClockSet *clks, + const RiseFallBoth *clk_tr, + bool edge_triggered, + bool latches) +{ + Sta *sta = Sta::sta(); + Mode *mode = sta->cmdMode(); + PinSet pins = sta->findRegisterClkPins(clks, clk_tr, edge_triggered, + latches, mode); + delete clks; + return pins; +} + +PinSet +find_register_async_pins(ClockSet *clks, + const RiseFallBoth *clk_tr, + bool edge_triggered, + bool latches) +{ + Sta *sta = Sta::sta(); + Mode *mode = sta->cmdMode(); + PinSet pins = sta->findRegisterAsyncPins(clks, clk_tr, edge_triggered, + latches, mode); + delete clks; + return pins; +} + +PinSet +find_register_output_pins(ClockSet *clks, + const RiseFallBoth *clk_tr, + bool edge_triggered, + bool latches) +{ + Sta *sta = Sta::sta(); + Mode *mode = sta->cmdMode(); + PinSet pins = sta->findRegisterOutputPins(clks, clk_tr, edge_triggered, + latches, mode); + delete clks; + return pins; +} + +//////////////////////////////////////////////////////////////// + +template std::vector +filter_objects(const char *property, + const char *op, + const char *pattern, + std::vector *objects) +{ + std::vector filtered_objects; if (objects) { Sta *sta = Sta::sta(); Properties &properties = sta->properties(); @@ -1230,7 +1483,7 @@ filter_objects(const char *property, bool not_pattern_match = stringEq(op, "!~"); for (T *object : *objects) { PropertyValue value(properties.getProperty(object, property)); - string prop_str = value.to_string(sta->network()); + std::string prop_str = value.to_string(sta->network()); const char *prop = prop_str.c_str(); if (!prop_str.empty() && ((exact_match && stringEq(prop, pattern)) @@ -1246,81 +1499,81 @@ filter_objects(const char *property, PortSeq filter_ports(const char *property, - const char *op, - const char *pattern, - PortSeq *ports) + const char *op, + const char *pattern, + PortSeq *ports) { return filter_objects(property, op, pattern, ports); } InstanceSeq filter_insts(const char *property, - const char *op, - const char *pattern, - InstanceSeq *insts) + const char *op, + const char *pattern, + InstanceSeq *insts) { return filter_objects(property, op, pattern, insts); } PinSeq filter_pins(const char *property, - const char *op, - const char *pattern, - PinSeq *pins) + const char *op, + const char *pattern, + PinSeq *pins) { return filter_objects(property, op, pattern, pins); } ClockSeq filter_clocks(const char *property, - const char *op, - const char *pattern, - ClockSeq *clocks) + const char *op, + const char *pattern, + ClockSeq *clocks) { return filter_objects(property, op, pattern, clocks); } LibertyCellSeq filter_lib_cells(const char *property, - const char *op, - const char *pattern, - LibertyCellSeq *cells) + const char *op, + const char *pattern, + LibertyCellSeq *cells) { return filter_objects(property, op, pattern, cells); } LibertyPortSeq filter_lib_pins(const char *property, - const char *op, - const char *pattern, - LibertyPortSeq *pins) + const char *op, + const char *pattern, + LibertyPortSeq *pins) { return filter_objects(property, op, pattern, pins); } LibertyLibrarySeq filter_liberty_libraries(const char *property, - const char *op, - const char *pattern, - LibertyLibrarySeq *libs) + const char *op, + const char *pattern, + LibertyLibrarySeq *libs) { return filter_objects(property, op, pattern, libs); } NetSeq filter_nets(const char *property, - const char *op, - const char *pattern, - NetSeq *nets) + const char *op, + const char *pattern, + NetSeq *nets) { return filter_objects(property, op, pattern, nets); } EdgeSeq filter_timing_arcs(const char *property, - const char *op, - const char *pattern, - EdgeSeq *edges) + const char *op, + const char *pattern, + EdgeSeq *edges) { return filter_objects(property, op, pattern, edges); } @@ -1330,8 +1583,10 @@ filter_timing_arcs(const char *property, StringSeq group_path_names() { + Sta *sta = Sta::sta(); + Sdc *sdc = sta->cmdSdc(); StringSeq pg_names; - for (auto const& [name, group] : Sta::sta()->sdc()->groupPaths()) + for (auto const& [name, group] : sdc->groupPaths()) pg_names.push_back(name); return pg_names; } @@ -1342,7 +1597,9 @@ void set_voltage_global(const MinMax *min_max, float voltage) { - Sta::sta()->setVoltage(min_max, voltage); + Sta *sta = Sta::sta(); + Sdc *sdc = sta->cmdSdc(); + sta->setVoltage(min_max, voltage, sdc); } void @@ -1350,7 +1607,9 @@ set_voltage_net(const Net *net, const MinMax *min_max, float voltage) { - Sta::sta()->setVoltage(net, min_max, voltage); + Sta *sta = Sta::sta(); + Sdc *sdc = sta->cmdSdc(); + sta->setVoltage(net, min_max, voltage, sdc); } //////////////////////////////////////////////////////////////// @@ -1359,7 +1618,7 @@ char pin_case_logic_value(const Pin *pin) { Sta *sta = Sta::sta(); - Sdc *sdc = sta->sdc(); + const Sdc *sdc = sta->cmdSdc(); LogicValue value = LogicValue::unknown; bool exists; sdc->caseLogicValue(pin, value, exists); @@ -1370,7 +1629,7 @@ char pin_logic_value(const Pin *pin) { Sta *sta = Sta::sta(); - Sdc *sdc = sta->sdc(); + const Sdc *sdc = sta->cmdSdc(); LogicValue value = LogicValue::unknown; bool exists; sdc->logicValue(pin, value, exists); diff --git a/sdc/Sdc.tcl b/sdc/Sdc.tcl index 112ea504..1e59be57 100644 --- a/sdc/Sdc.tcl +++ b/sdc/Sdc.tcl @@ -34,16 +34,27 @@ namespace eval sta { -define_cmd_args "read_sdc" {[-echo] filename} +define_cmd_args "read_sdc" {[-echo] [-mode mode_name] filename} proc_redirect read_sdc { - parse_key_args "read_sdc" args keys {} flags {-echo} + parse_key_args "read_sdc" args keys {-mode} flags {-echo} check_argc_eq1 "read_sdc" $args set echo [info exists flags(-echo)] set filename [file nativename [lindex $args 0]] - set prev_filename [info script] - include_file $filename $echo 0 + set mode_name {} + if { [info exists keys(-mode)] } { + set mode_name $keys(-mode) + } + set prev_mode [cmd_mode_name] + try { + set_mode_cmd $mode_name + include_file $filename $echo 0 + } finally { + if { $prev_mode != "default" } { + set_mode_cmd $prev_mode + } + } } ################################################################ @@ -107,7 +118,7 @@ proc set_hierarchy_separator { separator } { proc check_path_divider { divider } { set sdc_dividers "/@^#.|" if { !([string length $divider] == 1 - && [string first $divider $sdc_dividers] != -1)} { + && [string first $divider $sdc_dividers] != -1)} { sta_error 342 "hierarchy separator must be one of '$sdc_dividers'." } } @@ -237,11 +248,11 @@ proc all_registers { args } { } if {[info exists flags(-edge_triggered)] \ - && ![info exists flags(-level_sensitive)]} { + && ![info exists flags(-level_sensitive)]} { set edge_triggered 1 set level_sensitive 0 } elseif {[info exists flags(-level_sensitive)] \ - && ![info exists flags(-edge_triggered)]} { + && ![info exists flags(-edge_triggered)]} { set level_sensitive 1 set edge_triggered 0 } else { @@ -257,23 +268,23 @@ proc all_registers { args } { } if [info exists flags(-cells)] { return [find_register_instances $clks $clk_rf \ - $edge_triggered $level_sensitive] + $edge_triggered $level_sensitive] } elseif [info exists flags(-data_pins)] { return [find_register_data_pins $clks $clk_rf \ - $edge_triggered $level_sensitive] + $edge_triggered $level_sensitive] } elseif [info exists flags(-clock_pins)] { return [find_register_clk_pins $clks $clk_rf \ - $edge_triggered $level_sensitive] + $edge_triggered $level_sensitive] } elseif [info exists flags(-async_pins)] { return [find_register_async_pins $clks $clk_rf \ - $edge_triggered $level_sensitive] + $edge_triggered $level_sensitive] } elseif [info exists flags(-output_pins)] { return [find_register_output_pins $clks $clk_rf \ - $edge_triggered $level_sensitive] + $edge_triggered $level_sensitive] } else { # -cells is the default. return [find_register_instances $clks $clk_rf \ - $edge_triggered $level_sensitive] + $edge_triggered $level_sensitive] } } @@ -368,19 +379,19 @@ proc get_cells { args } { parse_port_pin_net_arg $keys(-of_objects) pins nets foreach pin $pins { if { [$pin is_top_level_port] } { - set net [get_nets [get_name $pin]] - if { $net != "NULL" } { - lappend nets $net - } + set net [get_nets [get_name $pin]] + if { $net != "NULL" } { + lappend nets $net + } } else { - lappend insts [$pin instance] + lappend insts [$pin instance] } } foreach net $nets { set pin_iter [$net pin_iterator] while { [$pin_iter has_next] } { - set pin [$pin_iter next] - lappend insts [$pin instance] + set pin [$pin_iter next] + lappend insts [$pin instance] } $pin_iter finish } @@ -388,23 +399,23 @@ proc get_cells { args } { check_argc_eq0or1 "get_cells" $args foreach pattern $patterns { if { [is_object $pattern] } { - if { [object_type $pattern] != "Instance" } { - sta_error 326 "object '$pattern' is not an instance." - } - set insts [concat $insts $pattern] + if { [object_type $pattern] != "Instance" } { + sta_error 326 "object '$pattern' is not an instance." + } + set insts [concat $insts $pattern] } else { - if { $divider != $hierarchy_separator } { - regsub $divider $pattern $hierarchy_separator pattern - } - if { $hierarchical } { - set matches [find_instances_hier_matching $pattern $regexp $nocase] - } else { - set matches [find_instances_matching $pattern $regexp $nocase] - } - if { $matches == {} && !$quiet} { - sta_warn 349 "instance '$pattern' not found." - } - set insts [concat $insts $matches] + if { $divider != $hierarchy_separator } { + regsub $divider $pattern $hierarchy_separator pattern + } + if { $hierarchical } { + set matches [find_instances_hier_matching $pattern $regexp $nocase] + } else { + set matches [find_instances_matching $pattern $regexp $nocase] + } + if { $matches == {} && !$quiet} { + sta_warn 349 "instance '$pattern' not found." + } + set insts [concat $insts $matches] } } } @@ -437,17 +448,17 @@ proc get_clocks { args } { foreach pattern $patterns { if { [is_object $pattern] } { if { [object_type $pattern] != "Clock" } { - sta_error 327 "object '$pattern' is not an clock." + sta_error 327 "object '$pattern' is not an clock." } set clocks [concat $clocks $pattern] } else { set matches [find_clocks_matching $pattern $regexp $nocase] if { $matches != {} } { - set clocks [concat $clocks $matches] + set clocks [concat $clocks $matches] } else { - if {![info exists flags(-quiet)]} { - sta_warn 351 "clock '$pattern' not found." - } + if {![info exists flags(-quiet)]} { + sta_warn 351 "clock '$pattern' not found." + } } } } @@ -500,35 +511,35 @@ proc get_lib_cells { args } { set quiet [info exists flags(-quiet)] foreach pattern $patterns { if { [is_object $pattern] } { - if { [object_type $pattern] != "LibertyCell" } { - sta_error 328 "object '$pattern' is not a liberty cell." - } - set cells [concat $cells $pattern] + if { [object_type $pattern] != "LibertyCell" } { + sta_error 328 "object '$pattern' is not a liberty cell." + } + set cells [concat $cells $pattern] } else { - if { ![regexp $cell_regexp $pattern ignore lib_name cell_pattern]} { - set lib_name "*" - set cell_pattern $pattern - } - # Allow wildcards in the library name (incompatible). - set libs [get_libs -quiet $lib_name] - if { $libs == {} } { - if {!$quiet} { - sta_warn 353 "library '$lib_name' not found." - } - } else { - foreach lib $libs { - set matches [$lib find_liberty_cells_matching $cell_pattern \ - $regexp $nocase] - if {$matches != {}} { - set cells [concat $cells $matches] - } - } - if { $cells == {} } { - if {!$quiet} { - sta_warn 354 "cell '$cell_pattern' not found." - } - } - } + if { ![regexp $cell_regexp $pattern ignore lib_name cell_pattern]} { + set lib_name "*" + set cell_pattern $pattern + } + # Allow wildcards in the library name (incompatible). + set libs [get_libs -quiet $lib_name] + if { $libs == {} } { + if {!$quiet} { + sta_warn 353 "library '$lib_name' not found." + } + } else { + foreach lib $libs { + set matches [$lib find_liberty_cells_matching $cell_pattern \ + $regexp $nocase] + if {$matches != {}} { + set cells [concat $cells $matches] + } + } + if { $cells == {} } { + if {!$quiet} { + sta_warn 354 "cell '$cell_pattern' not found." + } + } + } } } } @@ -579,60 +590,60 @@ proc get_lib_pins { args } { set libcells [get_libcells_error "objects" $keys(-of_objects)] foreach libcell $libcells { foreach port [$libcell find_liberty_ports_matching * 0 1] { - # Filter pg ports. - if { ![$port is_pwr_gnd] } { - lappend ports $port - } + # Filter pg ports. + if { ![$port is_pwr_gnd] } { + lappend ports $port + } } } } else { foreach pattern $patterns { if { [is_object $pattern] } { - if { [object_type $pattern] != "LibertyPort" } { - sta_error 329 "object '$pattern' is not a liberty pin." - } - set ports [concat $ports $pattern] + if { [object_type $pattern] != "LibertyPort" } { + sta_error 329 "object '$pattern' is not a liberty pin." + } + set ports [concat $ports $pattern] } else { - # match library/cell/port - set libs {} - if { [regexp $port_regexp1 $pattern ignore lib_name cell_name port_pattern] } { - set libs [get_libs -quiet $lib_name] - # match cell/port - } elseif { [regexp $port_regexp2 $pattern ignore cell_name port_pattern] } { - set libs [get_libs *] - } else { - if { !$quiet } { - sta_warn 355 "library/cell/port '$pattern' not found." - } - return {} - } - if { $libs != {} } { - set found_match 0 - set cells {} - foreach lib $libs { - set cells [$lib find_liberty_cells_matching $cell_name $regexp $nocase] - foreach cell $cells { - set matches [$cell find_liberty_ports_matching $port_pattern \ - $regexp $nocase] - foreach match $matches { - # Filter pg ports. - if { ![$match is_pwr_gnd] } { - lappend ports $match - set found_match 1 - } - } - } - } - if { !$found_match } { - if { !$quiet } { - sta_warn 356 "port '$port_pattern' not found." - } - } - } else { - if { !$quiet } { - sta_warn 357 "library '$lib_name' not found." - } - } + # match library/cell/port + set libs {} + if { [regexp $port_regexp1 $pattern ignore lib_name cell_name port_pattern] } { + set libs [get_libs -quiet $lib_name] + # match cell/port + } elseif { [regexp $port_regexp2 $pattern ignore cell_name port_pattern] } { + set libs [get_libs *] + } else { + if { !$quiet } { + sta_warn 355 "library/cell/port '$pattern' not found." + } + return {} + } + if { $libs != {} } { + set found_match 0 + set cells {} + foreach lib $libs { + set cells [$lib find_liberty_cells_matching $cell_name $regexp $nocase] + foreach cell $cells { + set matches [$cell find_liberty_ports_matching $port_pattern \ + $regexp $nocase] + foreach match $matches { + # Filter pg ports. + if { ![$match is_pwr_gnd] } { + lappend ports $match + set found_match 1 + } + } + } + } + if { !$found_match } { + if { !$quiet } { + sta_warn 356 "port '$port_pattern' not found." + } + } + } else { + if { !$quiet } { + sta_warn 357 "library '$lib_name' not found." + } + } } } } @@ -672,17 +683,17 @@ proc get_libs { args } { foreach pattern $patterns { if { [is_object $pattern] } { if { [object_type $pattern] != "LibertyLibrary" } { - sta_error 330 "object '$pattern' is not a liberty library." + sta_error 330 "object '$pattern' is not a liberty library." } set libs [concat $libs $pattern] } else { set matches [find_liberty_libraries_matching $pattern $regexp $nocase] if {$matches != {}} { - set libs [concat $libs $matches] + set libs [concat $libs $matches] } else { - if {![info exists flags(-quiet)]} { - sta_warn 359 "library '$pattern' not found." - } + if {![info exists flags(-quiet)]} { + sta_warn 359 "library '$pattern' not found." + } } } } @@ -710,8 +721,8 @@ proc find_liberty_libraries_matching { pattern regexp nocase } { set lib [$lib_iter next] set lib_name [get_name $lib] if { (!$regexp && [string match $pattern2 $lib_name]) \ - || ($regexp && $nocase && [regexp -nocase $pattern2 $lib_name]) \ - || ($regexp && !$nocase && [regexp $pattern2 $lib_name]) } { + || ($regexp && $nocase && [regexp -nocase $pattern2 $lib_name]) \ + || ($regexp && !$nocase && [regexp $pattern2 $lib_name]) } { lappend matches $lib } } @@ -758,8 +769,8 @@ proc get_nets { args } { foreach inst $insts { set pin_iter [$inst pin_iterator] while { [$pin_iter has_next] } { - set pin [$pin_iter next] - lappend nets [$pin net] + set pin [$pin_iter next] + lappend nets [$pin net] } $pin_iter finish } @@ -770,20 +781,20 @@ proc get_nets { args } { check_argc_eq0or1 "get_nets" $args foreach pattern $patterns { if { [is_object $pattern] } { - if { [object_type $pattern] != "Net" } { - sta_error 331 "object '$pattern' is not a net." - } - set nets [concat $nets $pattern] + if { [object_type $pattern] != "Net" } { + sta_error 331 "object '$pattern' is not a net." + } + set nets [concat $nets $pattern] } else { - if { $hierarchical } { - set matches [find_nets_hier_matching $pattern $regexp $nocase] - } else { - set matches [find_nets_matching $pattern $regexp $nocase] - } - set nets [concat $nets $matches] - if { $matches == {} && !$quiet } { - sta_warn 361 "net '$pattern' not found." - } + if { $hierarchical } { + set matches [find_nets_hier_matching $pattern $regexp $nocase] + } else { + set matches [find_nets_matching $pattern $regexp $nocase] + } + set nets [concat $nets $matches] + if { $matches == {} && !$quiet } { + sta_warn 361 "net '$pattern' not found." + } } } } @@ -821,22 +832,22 @@ proc get_pins { args } { foreach inst $insts { set pin_iter [$inst pin_iterator] while { [$pin_iter has_next] } { - set pin [$pin_iter next] - # Filter pg ports. - if { ![$pin is_pwr_gnd] } { - lappend pins $pin - } + set pin [$pin_iter next] + # Filter pg ports. + if { ![$pin is_pwr_gnd] } { + lappend pins $pin + } } $pin_iter finish } foreach net $nets { set pin_iter [$net pin_iterator] while { [$pin_iter has_next] } { - set pin [$pin_iter next] - # Filter pg ports. - if { ![$pin is_pwr_gnd] } { - lappend pins $pin - } + set pin [$pin_iter next] + # Filter pg ports. + if { ![$pin is_pwr_gnd] } { + lappend pins $pin + } } $pin_iter finish } @@ -856,25 +867,25 @@ proc get_pins { args } { set patterns [string map {\\ \\\\} $patterns] foreach pattern $patterns { if { [is_object $pattern] } { - if { [object_type $pattern] != "Pin" } { - sta_error 332 "object '$pattern' is not a pin." - } - set pins [concat $pins $pattern] + if { [object_type $pattern] != "Pin" } { + sta_error 332 "object '$pattern' is not a pin." + } + set pins [concat $pins $pattern] } else { - if { $hierarchical } { - set matches [find_pins_hier_matching $pattern $regexp $nocase] - } else { - set matches [find_pins_matching $pattern $regexp $nocase] - } - foreach match $matches { - # Filter pg ports. - if { ![$match is_pwr_gnd] } { - lappend pins $match - } - } - if { $matches == {} && !$quiet } { - sta_warn 363 "pin '$pattern' not found." - } + if { $hierarchical } { + set matches [find_pins_hier_matching $pattern $regexp $nocase] + } else { + set matches [find_pins_matching $pattern $regexp $nocase] + } + foreach match $matches { + # Filter pg ports. + if { ![$match is_pwr_gnd] } { + lappend pins $match + } + } + if { $matches == {} && !$quiet } { + sta_warn 363 "pin '$pattern' not found." + } } } } @@ -918,18 +929,18 @@ proc get_ports { args } { check_argc_eq0or1 "get_ports" $args foreach pattern $patterns { if { [is_object $pattern] } { - if { [object_type $pattern] != "Port" } { - sta_error 333 "object '$pattern' is not a port." - } - set ports [concat $ports $pattern] + if { [object_type $pattern] != "Port" } { + sta_error 333 "object '$pattern' is not a port." + } + set ports [concat $ports $pattern] } else { set matches [find_ports_matching $pattern $regexp $nocase] if { $matches != {} } { - set ports [concat $ports $matches] + set ports [concat $ports $matches] } else { - if {![info exists flags(-quiet)]} { - sta_warn 366 "port '$pattern' not found." - } + if {![info exists flags(-quiet)]} { + sta_warn 366 "port '$pattern' not found." + } } } } @@ -996,10 +1007,10 @@ proc create_clock { args } { check_float "-waveform edge" $edge set edge [time_ui_sta $edge] if { !$first_edge && $edge < $prev_edge } { - sta_error 372 "non-increasing clock -waveform edge times." + sta_error 372 "non-increasing clock -waveform edge times." } if { $edge > [expr $period * 2] } { - sta_error 373 "-waveform time greater than two periods." + sta_error 373 "-waveform time greater than two periods." } lappend waveform $edge set prev_edge $edge @@ -1116,8 +1127,8 @@ proc create_generated_clock { args } { if {[info exists keys(-duty_cycle)]} { set duty_cycle $keys(-duty_cycle) if {![string is double $duty_cycle] \ - || $duty_cycle < 0.0 || $duty_cycle > 100.0} { - sta_error 384 "-duty_cycle is not a float between 0 and 100." + || $duty_cycle < 0.0 || $duty_cycle > 100.0} { + sta_error 384 "-duty_cycle is not a float between 0 and 100." } } } elseif {[info exists keys(-edges)]} { @@ -1129,16 +1140,16 @@ proc create_generated_clock { args } { foreach edge $edges { check_cardinal "-edges" $edge if { $edge <= $prev_edge } { - sta_error 386 "edges times are not monotonically increasing." + sta_error 386 "edges times are not monotonically increasing." } } if [info exists keys(-edge_shift)] { foreach shift $keys(-edge_shift) { - check_float "-edge_shift" $shift - lappend edge_shifts [time_ui_sta $shift] + check_float "-edge_shift" $shift + lappend edge_shifts [time_ui_sta $shift] } if { [llength $edge_shifts] != [llength $edges] } { - sta_error 387 "-edge_shift length does not match -edges length." + sta_error 387 "-edge_shift length does not match -edges length." } } } elseif { $combinational } { @@ -1150,8 +1161,8 @@ proc create_generated_clock { args } { set invert 0 if {[info exists flags(-invert)]} { if {!([info exists keys(-divide_by)] \ - || [info exists keys(-multiply_by)] \ - || [info exists flags(-combinational)])} { + || [info exists keys(-multiply_by)] \ + || [info exists flags(-combinational)])} { sta_error 389 "cannot specify -invert without -multiply_by, -divide_by or -combinational." } set invert 1 @@ -1206,8 +1217,8 @@ define_cmd_args "group_path" \ proc group_path { args } { parse_key_args "group_path" args \ keys {-name -weight -critical_range \ - -from -rise_from -fall_from \ - -to -rise_to -fall_to -comment} \ + -from -rise_from -fall_from \ + -to -rise_to -fall_to -comment} \ flags {-default} 0 set cmd "group_path" @@ -1311,11 +1322,11 @@ proc set_clock_gating_check1 { args rf setup_hold margin active_value } { } foreach pin $pins { set_clock_gating_check_pin_cmd $pin $rf $setup_hold \ - $margin $active_value + $margin $active_value } foreach inst $insts { set_clock_gating_check_instance_cmd $inst $rf $setup_hold \ - $margin $active_value + $margin $active_value } } } @@ -1330,7 +1341,7 @@ proc set_clock_groups { args } { parse_key_args "set_clock_groups" args \ keys {-name -comment} \ flags {-logically_exclusive -physically_exclusive \ - -asynchronous -allow_paths} 0 + -asynchronous -allow_paths} 0 if {[info exists keys(-name)]} { set name $keys(-name) @@ -1352,22 +1363,22 @@ proc set_clock_groups { args } { set comment [parse_comment_key keys] set clk_groups [make_clock_groups $name $logically_exclusive \ - $physically_exclusive $asynchronous $allow_paths \ - $comment] + $physically_exclusive $asynchronous $allow_paths \ + $comment] while { $args != "" } { set arg [lindex $args 0] if {[string match $arg "-group"]} { set group_clks [get_clocks_warn "clocks" [lindex $args 1]] if { $group_clks != {} } { - clock_groups_make_group $clk_groups $group_clks + clock_groups_make_group $clk_groups $group_clks } set args [lrange $args 2 end] } else { if {[is_keyword_arg $arg]} { - sta_warn 402 "unknown keyword argument $arg." + sta_warn 402 "unknown keyword argument $arg." } else { - sta_warn 403 "extra positional argument $arg." + sta_warn 403 "extra positional argument $arg." } set args [lrange $args 1 end] } @@ -1379,7 +1390,7 @@ proc set_clock_groups { args } { define_cmd_args "unset_clock_groups" \ {[-logically_exclusive] [-physically_exclusive]\ [-asynchronous] [-name names] [-all]} - + proc unset_clock_groups { args } { unset_clk_groups_cmd "unset_clock_groups" $args } @@ -1424,11 +1435,11 @@ proc unset_clk_groups_cmd { cmd cmd_args } { } else { foreach name $names { if { $logically_exclusive } { - unset_clock_groups_logically_exclusive $name + unset_clock_groups_logically_exclusive $name } elseif { $physically_exclusive } { - unset_clock_groups_physically_exclusive $name + unset_clock_groups_physically_exclusive $name } elseif { $asynchronous } { - unset_clock_groups_asynchronous $name + unset_clock_groups_asynchronous $name } } } @@ -1474,7 +1485,7 @@ proc set_clock_latency { args } { foreach pin $pins { # Source only allowed on clocks and clock pins. if { ![is_clock_src $pin] } { - sta_error 409 "-source '[get_full_name $pin]' is not a clock pin." + sta_error 409 "-source '[get_full_name $pin]' is not a clock pin." } set_clock_insertion_cmd $pin_clk $pin $rf $min_max $early_late $delay } @@ -1522,7 +1533,7 @@ proc unset_clk_latency_cmd { cmd cmd_args } { foreach pin $pins { # Source only allowed on clocks and clock pins. if { ![is_clock_pin $pin] } { - sta_error 412 "-source '[$pin path_name]' is not a clock pin." + sta_error 412 "-source '[$pin path_name]' is not a clock pin." } unset_clock_insertion_cmd $pin_clk $pin } @@ -1583,8 +1594,8 @@ proc set_clock_sense_cmd1 { cmd cmd_args } { set negative [info exists flags(-negative)] set stop_propagation [info exists flags(-stop_propagation)] if { ($positive && ($negative || $stop_propagation || $pulse)) \ - || ($negative && ($positive || $stop_propagation || $pulse)) \ - || ($stop_propagation && ($positive || $negative || $pulse)) + || ($negative && ($positive || $stop_propagation || $pulse)) \ + || ($stop_propagation && ($positive || $negative || $pulse)) || ($pulse && ($positive || $negative || $stop_propagation)) } { sta_warn 417 "-positive, -negative, -stop_propagation and -pulse are mutually exclusive." } @@ -1703,7 +1714,7 @@ proc set_clock_uncertainty { args } { } if { $from_key != "none" && $to_key == "none" \ - || $from_key == "none" && $to_key != "none" } { + || $from_key == "none" && $to_key != "none" } { sta_error 421 "-from/-to must be used together." } elseif { $from_key != "none" && $to_key != "none" } { # Inter-clock uncertainty. @@ -1715,15 +1726,15 @@ proc set_clock_uncertainty { args } { foreach from_clk $from_clks { foreach to_clk $to_clks { - set_inter_clock_uncertainty $from_clk $from_rf \ - $to_clk $to_rf $min_max $uncertainty + set_inter_clock_uncertainty $from_clk $from_rf \ + $to_clk $to_rf $min_max $uncertainty } } } else { # Single clock uncertainty. check_argc_eq2 "set_clock_uncertainty" $args if { [info exists flags(-rise)] \ - || [info exists flags(-fall)] } { + || [info exists flags(-fall)] } { sta_error 422 "-rise, -fall options not allowed for single clock uncertainty." } set objects [lindex $args 1] @@ -1789,7 +1800,7 @@ proc unset_clk_uncertainty_cmd { cmd cmd_args } { } if { $from_key != "none" && $to_key == "none" \ - || $from_key == "none" && $to_key != "none" } { + || $from_key == "none" && $to_key != "none" } { sta_error 423 "-from/-to must be used together." } elseif { $from_key != "none" && $to_key != "none" } { # Inter-clock uncertainty. @@ -1801,15 +1812,15 @@ proc unset_clk_uncertainty_cmd { cmd cmd_args } { foreach from_clk $from_clks { foreach to_clk $to_clks { - unset_inter_clock_uncertainty $from_clk $from_rf \ - $to_clk $to_rf $min_max + unset_inter_clock_uncertainty $from_clk $from_rf \ + $to_clk $to_rf $min_max } } } else { # Single clock uncertainty. check_argc_eq1 $cmd $cmd_args if { [info exists keys(-rise)] \ - || [info exists keys(-fall)] } { + || [info exists keys(-fall)] } { sta_error 424 "-rise, -fall options not allowed for single clock uncertainty." } set objects [lindex $cmd_args 0] @@ -1964,7 +1975,7 @@ proc set_disable_timing { args } { libcells libports insts ports pins edges timing_arc_sets if { ([info exists keys(-from)] || [info exists keys(-to)]) \ - && ($libports != {} || $pins != {} || $ports != {}) } { + && ($libports != {} || $pins != {} || $ports != {}) } { sta_warn 429 "-from/-to keywords ignored for lib_pin, port and pin arguments." } @@ -2010,7 +2021,7 @@ proc set_disable_timing_instance { inst from to } { } else { foreach from_port $from_ports { foreach to_port $to_ports { - disable_instance $inst $from_port $to_port + disable_instance $inst $from_port $to_port } } } @@ -2770,10 +2781,10 @@ proc set_driving_cell { args } { } else { set library "NULL" if { [is_object $cell_name] } { - if { [object_type $cell_name] != "LibertyCell" } { - sta_error 334 "object '$cell_name' is not a liberty cell." - } - set cell $cell_name + if { [object_type $cell_name] != "LibertyCell" } { + sta_error 334 "object '$cell_name' is not a liberty cell." + } + set cell $cell_name } else { set cell [find_liberty_cell $cell_name] } @@ -2906,11 +2917,11 @@ proc set_input_transition { args } { # set_load port same as -pin_load # set_load net overrides parasitics define_cmd_args "set_load" \ - {[-corner corner] [-rise] [-fall] [-max] [-min] [-subtract_pin_load]\ + {[-rise] [-fall] [-max] [-min] [-subtract_pin_load]\ [-pin_load] [-wire_load] capacitance objects} proc set_load { args } { - parse_key_args "set_load" args keys {-corner} \ + parse_key_args "set_load" args keys {} \ flags {-rise -fall -min -max -subtract_pin_load -pin_load -wire_load}\ check_argc_eq2 "set_load" $args @@ -2918,7 +2929,6 @@ proc set_load { args } { set pin_load [info exists flags(-pin_load)] set wire_load [info exists flags(-wire_load)] set subtract_pin_load [info exists flags(-subtract_pin_load)] - set corner [parse_corner_or_all keys] set min_max [parse_min_max_all_check_flags flags] set rf [parse_rise_fall_flags flags] @@ -2926,7 +2936,6 @@ proc set_load { args } { check_positive_float "capacitance" $cap set cap [capacitance_ui_sta $cap] parse_port_net_args [lindex $args 1] ports nets - if { $ports != {} } { if { $subtract_pin_load } { sta_warn 486 "-subtract_pin_load not allowed for port objects." @@ -2934,11 +2943,11 @@ proc set_load { args } { # -pin_load is the default. if { $pin_load || (!$pin_load && !$wire_load) } { foreach port $ports { - set_port_ext_pin_cap $port $rf $corner $min_max $cap + set_port_ext_pin_cap $port $rf $min_max $cap } } elseif { $wire_load } { foreach port $ports { - set_port_ext_wire_cap $port 0 $rf $corner $min_max $cap + set_port_ext_wire_cap $port $rf $min_max $cap } } } @@ -2953,7 +2962,7 @@ proc set_load { args } { sta_warn 466 "-rise/-fall not allowed for net objects." } foreach net $nets { - set_net_wire_cap $net $subtract_pin_load $corner $min_max $cap + set_net_wire_cap $net $subtract_pin_load $min_max $cap } } } @@ -3103,10 +3112,10 @@ proc set_max_transition { args } { ################################################################ define_cmd_args "set_port_fanout_number" \ - {[-corner corner] [-max] [-min] fanout ports} + {[-max] [-min] fanout ports} proc set_port_fanout_number { args } { - parse_key_args "set_port_fanout_number" args keys {-corner} flags {-max -min} + parse_key_args "set_port_fanout_number" args keys {} flags {-max -min} set min_max [parse_min_max_all_check_flags flags] check_argc_eq2 "set_port_fanout_number" $args @@ -3114,9 +3123,8 @@ proc set_port_fanout_number { args } { set fanout [lindex $args 0] check_positive_integer "fanout" $fanout set ports [get_ports_error "ports" [lindex $args 1]] - set corner [parse_corner_or_all keys] foreach port $ports { - set_port_ext_fanout_cmd $port $fanout $corner $min_max + set_port_ext_fanout_cmd $port $fanout $min_max } } @@ -3628,20 +3636,6 @@ proc set_max_leakage_power { power {unit {}} } { # ################################################################ -define_cmd_args "define_corners" { corner1 [corner2]... } - -proc define_corners { args } { - if { [get_libs -quiet *] != {} } { - sta_error 482 "define_corners must be called before read_liberty." - } - if { [llength $args] == 0 } { - sta_error 577 "define_corners must define at least one corner." - } - define_corners_cmd $args -} - -################################################################ - define_cmd_args "set_pvt"\ {insts [-min] [-max] [-process process] [-voltage voltage]\ [-temperature temperature]} diff --git a/sdc/SdcGraph.cc b/sdc/SdcGraph.cc deleted file mode 100644 index afd14c70..00000000 --- a/sdc/SdcGraph.cc +++ /dev/null @@ -1,396 +0,0 @@ -// OpenSTA, Static Timing Analyzer -// Copyright (c) 2025, Parallax Software, Inc. -// -// This program is free software: you can redistribute it and/or modify -// it under the terms of the GNU General Public License as published by -// the Free Software Foundation, either version 3 of the License, or -// (at your option) any later version. -// -// This program is distributed in the hope that it will be useful, -// but WITHOUT ANY WARRANTY; without even the implied warranty of -// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -// GNU General Public License for more details. -// -// You should have received a copy of the GNU General Public License -// along with this program. If not, see . -// -// The origin of this software must not be misrepresented; you must not -// claim that you wrote the original software. -// -// Altered source versions must be plainly marked as such, and must not be -// misrepresented as being the original software. -// -// This notice may not be removed or altered from any source distribution. - -#include "Stats.hh" -#include "PortDirection.hh" -#include "Network.hh" -#include "Graph.hh" -#include "DisabledPorts.hh" -#include "PortDelay.hh" -#include "ClockLatency.hh" -#include "Sdc.hh" - -namespace sta { - -static void -annotateGraphDisabledWireEdge(const Pin *from_pin, - const Pin *to_pin, - Graph *graph); - -// Annotate constraints to the timing graph. -void -Sdc::annotateGraph() -{ - Stats stats(debug_, report_); - // All output pins are considered constrained because - // they may be downstream from a set_min/max_delay -from that - // does not have a set_output_delay. - annotateGraphConstrainOutputs(); - annotateDisables(); - annotateGraphOutputDelays(); - annotateGraphDataChecks(); - annotateHierClkLatency(); - stats.report("Annotate constraints to graph"); -} - -void -Sdc::annotateGraphConstrainOutputs() -{ - Instance *top_inst = network_->topInstance(); - InstancePinIterator *pin_iter = network_->pinIterator(top_inst); - while (pin_iter->hasNext()) { - Pin *pin = pin_iter->next(); - if (network_->direction(pin)->isAnyOutput()) - annotateGraphConstrained(pin); - } - delete pin_iter; -} - -void -Sdc::annotateDisables() -{ - PinSet::Iterator pin_iter(disabled_pins_); - while (pin_iter.hasNext()) { - const Pin *pin = pin_iter.next(); - annotateGraphDisabled(pin); - } - - if (!disabled_lib_ports_.empty()) { - VertexIterator vertex_iter(graph_); - while (vertex_iter.hasNext()) { - Vertex *vertex = vertex_iter.next(); - Pin *pin = vertex->pin(); - LibertyPort *port = network_->libertyPort(pin); - if (disabled_lib_ports_.hasKey(port)) - annotateGraphDisabled(pin); - } - } - - Instance *top_inst = network_->topInstance(); - PortSet::Iterator port_iter(disabled_ports_); - while (port_iter.hasNext()) { - const Port *port = port_iter.next(); - Pin *pin = network_->findPin(top_inst, port); - annotateGraphDisabled(pin); - } - - for (const PinPair &pair : disabled_wire_edges_) - annotateGraphDisabledWireEdge(pair.first, pair.second, graph_); - - for (Edge *edge : disabled_edges_) - edge->setIsDisabledConstraint(true); - - DisabledInstancePortsMap::Iterator disable_inst_iter(disabled_inst_ports_); - while (disable_inst_iter.hasNext()) { - DisabledInstancePorts *disabled_inst = disable_inst_iter.next(); - setEdgeDisabledInstPorts(disabled_inst); - } -} - -class DisableHpinEdgeVisitor : public HierPinThruVisitor -{ -public: - DisableHpinEdgeVisitor(Graph *graph); - virtual void visit(const Pin *from_pin, - const Pin *to_pin); - -protected: - bool annotate_; - Graph *graph_; -}; - -DisableHpinEdgeVisitor::DisableHpinEdgeVisitor(Graph *graph) : - HierPinThruVisitor(), - graph_(graph) -{ -} - -void -DisableHpinEdgeVisitor::visit(const Pin *from_pin, - const Pin *to_pin) -{ - annotateGraphDisabledWireEdge(from_pin, to_pin, graph_); -} - -static void -annotateGraphDisabledWireEdge(const Pin *from_pin, - const Pin *to_pin, - Graph *graph) -{ - Vertex *from_vertex = graph->pinDrvrVertex(from_pin); - Vertex *to_vertex = graph->pinLoadVertex(to_pin); - if (from_vertex && to_vertex) { - VertexOutEdgeIterator edge_iter(from_vertex, graph); - while (edge_iter.hasNext()) { - Edge *edge = edge_iter.next(); - if (edge->isWire() - && edge->to(graph) == to_vertex) - edge->setIsDisabledConstraint(true); - } - } -} - -void -Sdc::annotateGraphDisabled(const Pin *pin) -{ - Vertex *vertex, *bidirect_drvr_vertex; - graph_->pinVertices(pin, vertex, bidirect_drvr_vertex); - vertex->setIsDisabledConstraint(true); - if (bidirect_drvr_vertex) - bidirect_drvr_vertex->setIsDisabledConstraint(true); -} - -void -Sdc::setEdgeDisabledInstPorts(DisabledInstancePorts *disabled_inst) -{ - setEdgeDisabledInstPorts(disabled_inst, disabled_inst->instance()); -} - -void -Sdc::setEdgeDisabledInstPorts(DisabledPorts *disabled_port, - Instance *inst) -{ - if (disabled_port->all()) { - InstancePinIterator *pin_iter = network_->pinIterator(inst); - while (pin_iter->hasNext()) { - Pin *pin = pin_iter->next(); - // set_disable_timing instance does not disable timing checks. - setEdgeDisabledInstFrom(pin, false); - } - delete pin_iter; - } - - // Disable from pins. - LibertyPortSet::Iterator from_iter(disabled_port->from()); - while (from_iter.hasNext()) { - LibertyPort *from_port = from_iter.next(); - Pin *from_pin = network_->findPin(inst, from_port); - if (from_pin) - setEdgeDisabledInstFrom(from_pin, true); - } - - // Disable to pins. - LibertyPortSet::Iterator to_iter(disabled_port->to()); - while (to_iter.hasNext()) { - LibertyPort *to_port = to_iter.next(); - Pin *to_pin = network_->findPin(inst, to_port); - if (to_pin) { - if (network_->direction(to_pin)->isAnyOutput()) { - Vertex *vertex = graph_->pinDrvrVertex(to_pin); - if (vertex) { - VertexInEdgeIterator edge_iter(vertex, graph_); - while (edge_iter.hasNext()) { - Edge *edge = edge_iter.next(); - edge->setIsDisabledConstraint(true); - } - } - } - } - } - - // Disable from/to pins. - if (disabled_port->fromTo()) { - for (const LibertyPortPair &from_to : *disabled_port->fromTo()) { - const LibertyPort *from_port = from_to.first; - const LibertyPort *to_port = from_to.second; - Pin *from_pin = network_->findPin(inst, from_port); - Pin *to_pin = network_->findPin(inst, to_port); - if (from_pin && network_->direction(from_pin)->isAnyInput() - && to_pin) { - Vertex *from_vertex = graph_->pinLoadVertex(from_pin); - Vertex *to_vertex = graph_->pinDrvrVertex(to_pin); - if (from_vertex && to_vertex) { - VertexOutEdgeIterator edge_iter(from_vertex, graph_); - while (edge_iter.hasNext()) { - Edge *edge = edge_iter.next(); - if (edge->to(graph_) == to_vertex) - edge->setIsDisabledConstraint(true); - } - } - } - } - } -} - -void -Sdc::setEdgeDisabledInstFrom(Pin *from_pin, - bool disable_checks) -{ - if (network_->direction(from_pin)->isAnyInput()) { - Vertex *from_vertex = graph_->pinLoadVertex(from_pin); - if (from_vertex) { - VertexOutEdgeIterator edge_iter(from_vertex, graph_); - while (edge_iter.hasNext()) { - Edge *edge = edge_iter.next(); - if (disable_checks - || !edge->role()->isTimingCheck()) - edge->setIsDisabledConstraint(true); - } - } - } -} - -void -Sdc::annotateGraphOutputDelays() -{ - for (OutputDelay *output_delay : output_delays_) { - for (const Pin *lpin : output_delay->leafPins()) - annotateGraphConstrained(lpin); - } -} - -void -Sdc::annotateGraphDataChecks() -{ - DataChecksMap::Iterator data_checks_iter(data_checks_to_map_); - while (data_checks_iter.hasNext()) { - DataCheckSet *checks = data_checks_iter.next(); - DataCheckSet::Iterator check_iter(checks); - // There may be multiple data checks on a single pin, - // but we only need to mark it as constrained once. - if (check_iter.hasNext()) { - DataCheck *check = check_iter.next(); - annotateGraphConstrained(check->to()); - } - } -} - -void -Sdc::annotateGraphConstrained(const PinSet *pins) -{ - PinSet::ConstIterator pin_iter(pins); - while (pin_iter.hasNext()) { - const Pin *pin = pin_iter.next(); - annotateGraphConstrained(pin); - } -} - -void -Sdc::annotateGraphConstrained(const InstanceSet *insts) -{ - InstanceSet::ConstIterator inst_iter(insts); - while (inst_iter.hasNext()) { - const Instance *inst = inst_iter.next(); - annotateGraphConstrained(inst); - } -} - -void -Sdc::annotateGraphConstrained(const Instance *inst) -{ - InstancePinIterator *pin_iter = network_->pinIterator(inst); - while (pin_iter->hasNext()) { - Pin *pin = pin_iter->next(); - if (network_->direction(pin)->isAnyInput()) - annotateGraphConstrained(pin); - } - delete pin_iter; -} - -void -Sdc::annotateGraphConstrained(const Pin *pin) -{ - Vertex *vertex, *bidirect_drvr_vertex; - graph_->pinVertices(pin, vertex, bidirect_drvr_vertex); - // Pin may be hierarchical and have no vertex. - if (vertex) - vertex->setIsConstrained(true); - if (bidirect_drvr_vertex) - bidirect_drvr_vertex->setIsConstrained(true); -} - -void -Sdc::annotateHierClkLatency() -{ - ClockLatencies::Iterator latency_iter(clk_latencies_); - while (latency_iter.hasNext()) { - ClockLatency *latency = latency_iter.next(); - const Pin *pin = latency->pin(); - if (pin && network_->isHierarchical(pin)) - annotateHierClkLatency(pin, latency); - } -} - -void -Sdc::annotateHierClkLatency(const Pin *hpin, - ClockLatency *latency) -{ - EdgesThruHierPinIterator edge_iter(hpin, network_, graph_); - while (edge_iter.hasNext()) { - Edge *edge = edge_iter.next(); - edge_clk_latency_[edge] = latency; - } -} - -ClockLatency * -Sdc::clockLatency(Edge *edge) const -{ - return edge_clk_latency_.findKey(edge); -} - -void -Sdc::clockLatency(Edge *edge, - const RiseFall *rf, - const MinMax *min_max, - // Return values. - float &latency, - bool &exists) const -{ - ClockLatency *latencies = edge_clk_latency_.findKey(edge); - if (latencies) - latencies->delay(rf, min_max, latency, exists); - else { - latency = 0.0; - exists = false; - } -} - -//////////////////////////////////////////////////////////////// - -void -Sdc::removeGraphAnnotations() -{ - VertexIterator vertex_iter(graph_); - while (vertex_iter.hasNext()) { - Vertex *vertex = vertex_iter.next(); - vertex->setIsDisabledConstraint(false); - vertex->setIsConstrained(false); - - VertexOutEdgeIterator edge_iter(vertex, graph_); - while (edge_iter.hasNext()) { - Edge *edge = edge_iter.next(); - edge->setIsDisabledConstraint(false); - } - } - edge_clk_latency_.clear(); -} - -void -Sdc::searchPreamble() -{ - ensureClkHpinDisables(); - ensureClkGroupExclusions(); -} - -} // namespace diff --git a/sdc/Variables.cc b/sdc/Variables.cc index 1cb10bd0..c97bbba1 100644 --- a/sdc/Variables.cc +++ b/sdc/Variables.cc @@ -32,7 +32,6 @@ Variables::Variables() : propagate_gated_clock_enable_(true), preset_clr_arcs_enabled_(false), cond_default_arcs_enabled_(true), - bidirect_net_paths_enabled_(false), bidirect_inst_paths_enabled_(false), recovery_removal_checks_enabled_(true), gated_clk_checks_enabled_(true), @@ -80,12 +79,6 @@ Variables::setBidirectInstPathsEnabled(bool enabled) bidirect_inst_paths_enabled_ = enabled; } -void -Variables::setBidirectNetPathsEnabled(bool enabled) -{ - bidirect_net_paths_enabled_ = enabled; -} - void Variables::setRecoveryRemovalChecksEnabled(bool enabled) { diff --git a/sdc/WriteSdc.cc b/sdc/WriteSdc.cc index 32c2450c..e317a8a4 100644 --- a/sdc/WriteSdc.cc +++ b/sdc/WriteSdc.cc @@ -27,7 +27,10 @@ #include #include #include +#include +#include +#include "ContainerHelpers.hh" #include "Zlib.hh" #include "Report.hh" #include "Error.hh" @@ -54,7 +57,7 @@ #include "Sdc.hh" #include "Fuzzy.hh" #include "StaState.hh" -#include "Corner.hh" +#include "Scene.hh" #include "Variables.hh" #include "WriteSdcPvt.hh" @@ -62,8 +65,8 @@ namespace sta { using std::string; -typedef Set ClockSenseSet; -typedef Vector ClockSenseSeq; +typedef std::set ClockSenseSet; +typedef std::vector ClockSenseSeq; static const char * transRiseFallFlag(const RiseFall *rf); @@ -94,7 +97,7 @@ class WriteGetPort : public WriteSdcObject { public: WriteGetPort(const Port *port, - const WriteSdc *writer); + const WriteSdc *writer); virtual void write() const; private: @@ -119,9 +122,9 @@ class WriteGetPinAndClkKey : public WriteSdcObject { public: WriteGetPinAndClkKey(const Pin *pin, - bool map_hpin_to_drvr, - const Clock *clk, - const WriteSdc *writer); + bool map_hpin_to_drvr, + const Clock *clk, + const WriteSdc *writer); virtual void write() const; private: @@ -132,9 +135,9 @@ private: }; WriteGetPinAndClkKey::WriteGetPinAndClkKey(const Pin *pin, - bool map_hpin_to_drvr, - const Clock *clk, - const WriteSdc *writer) : + bool map_hpin_to_drvr, + const Clock *clk, + const WriteSdc *writer) : pin_(pin), map_hpin_to_drvr_(map_hpin_to_drvr), clk_(clk), @@ -154,8 +157,8 @@ class WriteGetPin : public WriteSdcObject { public: WriteGetPin(const Pin *pin, - bool map_hpin_to_drvr, - const WriteSdc *writer); + bool map_hpin_to_drvr, + const WriteSdc *writer); virtual void write() const; private: @@ -165,7 +168,7 @@ private: }; WriteGetPin::WriteGetPin(const Pin *pin, - bool map_hpin_to_drvr, + bool map_hpin_to_drvr, const WriteSdc *writer) : pin_(pin), map_hpin_to_drvr_(map_hpin_to_drvr), @@ -183,7 +186,7 @@ class WriteGetNet : public WriteSdcObject { public: WriteGetNet(const Net *net, - const WriteSdc *writer); + const WriteSdc *writer); virtual void write() const; private: @@ -192,7 +195,7 @@ private: }; WriteGetNet::WriteGetNet(const Net *net, - const WriteSdc *writer) : + const WriteSdc *writer) : net_(net), writer_(writer) { @@ -208,7 +211,7 @@ class WriteGetInstance : public WriteSdcObject { public: WriteGetInstance(const Instance *inst, - const WriteSdc *writer); + const WriteSdc *writer); virtual void write() const; private: @@ -217,7 +220,7 @@ private: }; WriteGetInstance::WriteGetInstance(const Instance *inst, - const WriteSdc *writer) : + const WriteSdc *writer) : inst_(inst), writer_(writer) { @@ -233,7 +236,7 @@ class WriteGetLibCell : public WriteSdcObject { public: WriteGetLibCell(const LibertyCell *cell, - const WriteSdc *writer); + const WriteSdc *writer); virtual void write() const; private: @@ -242,7 +245,7 @@ private: }; WriteGetLibCell::WriteGetLibCell(const LibertyCell *cell, - const WriteSdc *writer) : + const WriteSdc *writer) : cell_(cell), writer_(writer) { @@ -258,7 +261,7 @@ class WriteGetClock : public WriteSdcObject { public: WriteGetClock(const Clock *clk, - const WriteSdc *writer); + const WriteSdc *writer); virtual void write() const; private: @@ -267,7 +270,7 @@ private: }; WriteGetClock::WriteGetClock(const Clock *clk, - const WriteSdc *writer) : + const WriteSdc *writer) : clk_(clk), writer_(writer) { @@ -282,29 +285,30 @@ WriteGetClock::write() const //////////////////////////////////////////////////////////////// void -writeSdc(Instance *instance, - const char *filename, - const char *creator, - bool map_hpins, - bool native, - int digits, +writeSdc(const Sdc *sdc, + Instance *instance, + const char *filename, + const char *creator, + bool map_hpins, + bool native, + int digits, bool gzip, - bool no_timestamp, - Sdc *sdc) + bool no_timestamp) { - WriteSdc writer(instance, creator, map_hpins, native, - digits, no_timestamp, sdc); + WriteSdc writer(sdc, instance, creator, map_hpins, native, + digits, no_timestamp); writer.write(filename, gzip); } -WriteSdc::WriteSdc(Instance *instance, - const char *creator, - bool map_hpins, - bool native, - int digits, - bool no_timestamp, - Sdc *sdc) : +WriteSdc::WriteSdc(const Sdc *sdc, + Instance *instance, + const char *creator, + bool map_hpins, + bool native, + int digits, + bool no_timestamp) : StaState(sdc), + sdc_(sdc), instance_(instance), creator_(creator), map_hpins_(map_hpins), @@ -412,7 +416,7 @@ void WriteSdc::writeClock(Clock *clk) const { gzprintf(stream_, "create_clock -name %s", - clk->name()); + clk->name()); if (clk->addToPins()) gzprintf(stream_, " -add"); gzprintf(stream_, " -period "); @@ -435,7 +439,7 @@ void WriteSdc::writeGeneratedClock(Clock *clk) const { gzprintf(stream_, "create_generated_clock -name %s", - clk->name()); + clk->name()); if (clk->addToPins()) gzprintf(stream_, " -add"); gzprintf(stream_, " -source "); @@ -517,8 +521,8 @@ WriteSdc::writeClockUncertainty(const Clock *clk) const void WriteSdc::writeClockUncertainty(const Clock *clk, - const char *setup_hold, - float value) const + const char *setup_hold, + float value) const { gzprintf(stream_, "set_clock_uncertainty %s", setup_hold); writeTime(value); @@ -528,18 +532,13 @@ WriteSdc::writeClockUncertainty(const Clock *clk, void WriteSdc::writeClockUncertaintyPins() const { - PinClockUncertaintyMap::Iterator iter(sdc_->pin_clk_uncertainty_map_); - while (iter.hasNext()) { - const Pin *pin; - ClockUncertainties *uncertainties; - iter.next(pin, uncertainties); + for (const auto [pin, uncertainties] : sdc_->pin_clk_uncertainty_map_) writeClockUncertaintyPin(pin, uncertainties); - } } void WriteSdc::writeClockUncertaintyPin(const Pin *pin, - ClockUncertainties *uncertainties) + ClockUncertainties *uncertainties) const { float setup; @@ -559,8 +558,8 @@ WriteSdc::writeClockUncertaintyPin(const Pin *pin, } void WriteSdc::writeClockUncertaintyPin(const Pin *pin, - const char *setup_hold, - float value) const + const char *setup_hold, + float value) const { gzprintf(stream_, "set_clock_uncertainty %s", setup_hold); writeTime(value); @@ -572,25 +571,23 @@ WriteSdc::writeClockUncertaintyPin(const Pin *pin, void WriteSdc::writeClockLatencies() const { - ClockLatencies::Iterator latency_iter(sdc_->clockLatencies()); - while (latency_iter.hasNext()) { - ClockLatency *latency = latency_iter.next(); + for (ClockLatency *latency : *sdc_->clockLatencies()) { const Pin *pin = latency->pin(); const Clock *clk = latency->clock(); if (pin && clk) { WriteGetPinAndClkKey write_pin(pin, true, clk, this); writeRiseFallMinMaxTimeCmd("set_clock_latency", latency->delays(), - write_pin); + write_pin); } else if (pin) { WriteGetPin write_pin(pin, true, this); writeRiseFallMinMaxTimeCmd("set_clock_latency", latency->delays(), - write_pin); + write_pin); } else if (clk) { WriteGetClock write_clk(clk, this); writeRiseFallMinMaxTimeCmd("set_clock_latency", latency->delays(), - write_clk); + write_clk); } } } @@ -618,27 +615,25 @@ WriteSdc::writeClockInsertions() const void WriteSdc::writeClockInsertion(ClockInsertion *insert, - WriteSdcObject &write_obj) const + WriteSdcObject &write_obj) const { RiseFallMinMax *early_values = insert->delays(EarlyLate::early()); RiseFallMinMax *late_values = insert->delays(EarlyLate::late()); if (early_values->equal(late_values)) writeRiseFallMinMaxTimeCmd("set_clock_latency -source", - late_values, write_obj); + late_values, write_obj); else { writeRiseFallMinMaxTimeCmd("set_clock_latency -source -early", - early_values, write_obj); + early_values, write_obj); writeRiseFallMinMaxTimeCmd("set_clock_latency -source -late", - late_values, write_obj); + late_values, write_obj); } } void WriteSdc::writePropagatedClkPins() const { - PinSet::Iterator pin_iter(sdc_->propagated_clk_pins_); - while (pin_iter.hasNext()) { - const Pin *pin = pin_iter.next(); + for (const Pin *pin : sdc_->propagated_clk_pins_) { gzprintf(stream_, "set_propagated_clock "); writeGetPin(pin, true); gzprintf(stream_, "\n"); @@ -648,12 +643,8 @@ WriteSdc::writePropagatedClkPins() const void WriteSdc::writeInterClockUncertainties() const { - InterClockUncertaintySet::Iterator - uncertainty_iter(sdc_->inter_clk_uncertainties_); - while (uncertainty_iter.hasNext()) { - InterClockUncertainty *uncertainty = uncertainty_iter.next(); + for (InterClockUncertainty *uncertainty : sdc_->inter_clk_uncertainties_) writeInterClockUncertainty(uncertainty); - } } void @@ -680,24 +671,24 @@ writeInterClockUncertainty(InterClockUncertainty *uncertainty) const else { for (auto src_rf : RiseFall::range()) { for (auto tgt_rf : RiseFall::range()) { - for (auto setup_hold : SetupHold::range()) { - float value; - bool exists; - sdc_->clockUncertainty(src_clk, src_rf, tgt_clk, tgt_rf, - setup_hold, value, exists); - if (exists) { - gzprintf(stream_, "set_clock_uncertainty -%s_from ", - src_rf == RiseFall::rise() ? "rise" : "fall"); - writeGetClock(uncertainty->src()); - gzprintf(stream_, " -%s_to ", - tgt_rf == RiseFall::rise() ? "rise" : "fall"); - writeGetClock(uncertainty->target()); - gzprintf(stream_, " %s ", - setupHoldFlag(setup_hold)); - writeTime(value); - gzprintf(stream_, "\n"); - } - } + for (auto setup_hold : SetupHold::range()) { + float value; + bool exists; + sdc_->clockUncertainty(src_clk, src_rf, tgt_clk, tgt_rf, + setup_hold, value, exists); + if (exists) { + gzprintf(stream_, "set_clock_uncertainty -%s_from ", + src_rf == RiseFall::rise() ? "rise" : "fall"); + writeGetClock(uncertainty->src()); + gzprintf(stream_, " -%s_to ", + tgt_rf == RiseFall::rise() ? "rise" : "fall"); + writeGetClock(uncertainty->target()); + gzprintf(stream_, " %s ", + setupHoldFlag(setup_hold)); + writeTime(value); + gzprintf(stream_, "\n"); + } + } } } } @@ -714,11 +705,8 @@ WriteSdc::writeInputDelays() const PortDelayLess port_delay_less(sdc_network_); sort(delays, port_delay_less); - PortDelaySeq::Iterator delay_iter(delays); - while (delay_iter.hasNext()) { - PortDelay *input_delay = delay_iter.next(); + for (PortDelay *input_delay : delays) writePortDelay(input_delay, true, "set_input_delay"); - } } void @@ -737,20 +725,20 @@ WriteSdc::writeOutputDelays() const void WriteSdc::writePortDelay(PortDelay *port_delay, - bool is_input_delay, - const char *sdc_cmd) const + bool is_input_delay, + const char *sdc_cmd) const { RiseFallMinMax *delays = port_delay->delays(); float rise_min, rise_max, fall_min, fall_max; bool rise_min_exists, rise_max_exists, fall_min_exists, fall_max_exists; delays->value(RiseFall::rise(), MinMax::min(), - rise_min, rise_min_exists); + rise_min, rise_min_exists); delays->value(RiseFall::rise(), MinMax::max(), - rise_max, rise_max_exists); + rise_max, rise_max_exists); delays->value(RiseFall::fall(), MinMax::min(), - fall_min, fall_min_exists); + fall_min, fall_min_exists); delays->value(RiseFall::fall(), MinMax::max(), - fall_max, fall_max_exists); + fall_max, fall_max_exists); // Try to compress the four port delays. if (rise_min_exists && rise_max_exists @@ -760,52 +748,52 @@ WriteSdc::writePortDelay(PortDelay *port_delay, && fall_min == rise_min && fall_max == rise_min) writePortDelay(port_delay, is_input_delay, rise_min, - RiseFallBoth::riseFall(), MinMaxAll::all(), sdc_cmd); + RiseFallBoth::riseFall(), MinMaxAll::all(), sdc_cmd); else if (rise_min_exists - && rise_max_exists - && rise_max == rise_min - && fall_min_exists - && fall_max_exists - && fall_min == fall_max) { + && rise_max_exists + && rise_max == rise_min + && fall_min_exists + && fall_max_exists + && fall_min == fall_max) { writePortDelay(port_delay, is_input_delay, rise_min, - RiseFallBoth::rise(), MinMaxAll::all(), sdc_cmd); + RiseFallBoth::rise(), MinMaxAll::all(), sdc_cmd); writePortDelay(port_delay, is_input_delay, fall_min, - RiseFallBoth::fall(), MinMaxAll::all(), sdc_cmd); + RiseFallBoth::fall(), MinMaxAll::all(), sdc_cmd); } else if (rise_min_exists - && fall_min_exists - && rise_min == fall_min - && rise_max_exists - && fall_max_exists - && rise_max == fall_max) { + && fall_min_exists + && rise_min == fall_min + && rise_max_exists + && fall_max_exists + && rise_max == fall_max) { writePortDelay(port_delay, is_input_delay, rise_min, - RiseFallBoth::riseFall(), MinMaxAll::min(), sdc_cmd); + RiseFallBoth::riseFall(), MinMaxAll::min(), sdc_cmd); writePortDelay(port_delay, is_input_delay, rise_max, - RiseFallBoth::riseFall(), MinMaxAll::max(), sdc_cmd); + RiseFallBoth::riseFall(), MinMaxAll::max(), sdc_cmd); } else { if (rise_min_exists) writePortDelay(port_delay, is_input_delay, rise_min, - RiseFallBoth::rise(), MinMaxAll::min(), sdc_cmd); + RiseFallBoth::rise(), MinMaxAll::min(), sdc_cmd); if (rise_max_exists) writePortDelay(port_delay, is_input_delay, rise_max, - RiseFallBoth::rise(), MinMaxAll::max(), sdc_cmd); + RiseFallBoth::rise(), MinMaxAll::max(), sdc_cmd); if (fall_min_exists) writePortDelay(port_delay, is_input_delay, fall_min, - RiseFallBoth::fall(), MinMaxAll::min(), sdc_cmd); + RiseFallBoth::fall(), MinMaxAll::min(), sdc_cmd); if (fall_max_exists) writePortDelay(port_delay, is_input_delay, fall_max, - RiseFallBoth::fall(), MinMaxAll::max(), sdc_cmd); + RiseFallBoth::fall(), MinMaxAll::max(), sdc_cmd); } } void WriteSdc::writePortDelay(PortDelay *port_delay, - bool is_input_delay, - float delay, - const RiseFallBoth *rf, - const MinMaxAll *min_max, - const char *sdc_cmd) const + bool is_input_delay, + float delay, + const RiseFallBoth *rf, + const MinMaxAll *min_max, + const char *sdc_cmd) const { gzprintf(stream_, "%s ", sdc_cmd); writeTime(delay); @@ -816,8 +804,8 @@ WriteSdc::writePortDelay(PortDelay *port_delay, gzprintf(stream_, " -clock_fall"); } gzprintf(stream_, "%s%s -add_delay ", - transRiseFallFlag(rf), - minMaxFlag(min_max)); + transRiseFallFlag(rf), + minMaxFlag(min_max)); const Pin *ref_pin = port_delay->refPin(); if (ref_pin) { gzprintf(stream_, "-reference_pin "); @@ -833,7 +821,7 @@ class PinClockPairNameLess public: PinClockPairNameLess(const Network *network); bool operator()(const PinClockPair &pin_clk1, - const PinClockPair &pin_clk2) const; + const PinClockPair &pin_clk2) const; private: PinPathNameLess pin_less_; @@ -846,7 +834,7 @@ PinClockPairNameLess::PinClockPairNameLess(const Network *network) : bool PinClockPairNameLess::operator()(const PinClockPair &pin_clk1, - const PinClockPair &pin_clk2) const + const PinClockPair &pin_clk2) const { const Pin *pin1 = pin_clk1.first; const Pin *pin2 = pin_clk2.first; @@ -854,15 +842,15 @@ PinClockPairNameLess::operator()(const PinClockPair &pin_clk1, const Clock *clk2 = pin_clk2.second; return pin_less_(pin1, pin2) || (pin1 == pin2 - && ((clk1 == nullptr && clk2) - || (clk1 && clk2 - && clk1->index() < clk2->index()))); + && ((clk1 == nullptr && clk2) + || (clk1 && clk2 + && clk1->index() < clk2->index()))); } void WriteSdc::writeClockSenses() const { - Vector pin_clks; + std::vector pin_clks; for (const auto& [pin_clk, sense] : sdc_->clk_sense_map_) pin_clks.push_back(pin_clk); @@ -872,7 +860,7 @@ WriteSdc::writeClockSenses() const for (auto pin_clk : pin_clks) { ClockSense sense; bool exists; - sdc_->clk_sense_map_.findKey(pin_clk, sense, exists); + findKeyValue(sdc_->clk_sense_map_, pin_clk, sense, exists); if (exists) writeClockSense(pin_clk, sense); } @@ -880,7 +868,7 @@ WriteSdc::writeClockSenses() const void WriteSdc::writeClockSense(PinClockPair &pin_clk, - ClockSense sense) const + ClockSense sense) const { const char *flag = nullptr; if (sense == ClockSense::positive) @@ -904,13 +892,13 @@ class ClockGroupLess { public: bool operator()(const ClockGroup *clk_group1, - const ClockGroup *clk_group2) const; + const ClockGroup *clk_group2) const; }; bool ClockGroupLess::operator()(const ClockGroup *clk_group1, - const ClockGroup *clk_group2) const + const ClockGroup *clk_group2) const { size_t size1 = clk_group1->size(); size_t size2 = clk_group2->size(); @@ -929,17 +917,17 @@ ClockGroupLess::operator()(const ClockGroup *clk_group1, clks2.push_back(clk2); sort(clks2, ClockNameLess()); - ClockSeq::Iterator clk_iter3(clks1); - ClockSeq::Iterator clk_iter4(clks2); - while (clk_iter3.hasNext() - && clk_iter4.hasNext()) { - Clock *clk1 = clk_iter3.next(); - Clock *clk2 = clk_iter4.next(); + ClockSeq::iterator clk_iter3 = clks1.begin(); + ClockSeq::iterator clk_iter4 = clks2.begin(); + while (clk_iter3 != clks1.end() + && clk_iter4 != clks2.end()) { + Clock *clk1 = *clk_iter3++; + Clock *clk2 = *clk_iter4++; int cmp = strcmp(clk1->name(), clk2->name()); if (cmp < 0) - return true; + return true; else if (cmp > 0) - return false; + return false; } return false; } @@ -964,17 +952,12 @@ WriteSdc::writeClockGroups(ClockGroups *clk_groups) const gzprintf(stream_, "-asynchronous \\\n"); if (clk_groups->allowPaths()) gzprintf(stream_, "-allow_paths \\\n"); - Vector groups; - ClockGroupSet::Iterator group_iter1(clk_groups->groups()); - while (group_iter1.hasNext()) { - ClockGroup *clk_group = group_iter1.next(); + std::vector groups; + for (ClockGroup *clk_group : *clk_groups->groups()) groups.push_back(clk_group); - } sort(groups, ClockGroupLess()); bool first = true; - Vector::Iterator group_iter2(groups); - while (group_iter2.hasNext()) { - ClockGroup *clk_group = group_iter2.next(); + for (ClockGroup *clk_group : groups) { if (!first) gzprintf(stream_, "\\\n"); gzprintf(stream_, " -group "); @@ -1012,31 +995,31 @@ WriteSdc::writeDisabledCells() const if (disable->fromTo()) { LibertyPortPairSeq from_tos = sortByName(disable->fromTo()); for (const LibertyPortPair &from_to : from_tos) { - const LibertyPort *from = from_to.first; - const LibertyPort *to = from_to.second; - gzprintf(stream_, "set_disable_timing -from {%s} -to {%s} ", - from->name(), - to->name()); - writeGetLibCell(cell); - gzprintf(stream_, "\n"); + const LibertyPort *from = from_to.first; + const LibertyPort *to = from_to.second; + gzprintf(stream_, "set_disable_timing -from {%s} -to {%s} ", + from->name(), + to->name()); + writeGetLibCell(cell); + gzprintf(stream_, "\n"); } } if (disable->from()) { LibertyPortSeq from = sortByName(disable->from()); for (const LibertyPort *from_port : from) { - gzprintf(stream_, "set_disable_timing -from {%s} ", - from_port->name()); - writeGetLibCell(cell); - gzprintf(stream_, "\n"); + gzprintf(stream_, "set_disable_timing -from {%s} ", + from_port->name()); + writeGetLibCell(cell); + gzprintf(stream_, "\n"); } } if (disable->to()) { LibertyPortSeq to = sortByName(disable->to()); for (const LibertyPort *to_port : to) { - gzprintf(stream_, "set_disable_timing -to {%s} ", - to_port->name()); - writeGetLibCell(cell); - gzprintf(stream_, "\n"); + gzprintf(stream_, "set_disable_timing -to {%s} ", + to_port->name()); + writeGetLibCell(cell); + gzprintf(stream_, "\n"); } } if (disable->timingArcSets()) { @@ -1086,31 +1069,31 @@ WriteSdc::writeDisabledInstances() const else if (disable->fromTo()) { LibertyPortPairSeq from_tos = sortByName(disable->fromTo()); for (LibertyPortPair &from_to : from_tos) { - const LibertyPort *from_port = from_to.first; - const LibertyPort *to_port = from_to.second; - gzprintf(stream_, "set_disable_timing -from {%s} -to {%s} ", - from_port->name(), - to_port->name()); - writeGetInstance(inst); - gzprintf(stream_, "\n"); + const LibertyPort *from_port = from_to.first; + const LibertyPort *to_port = from_to.second; + gzprintf(stream_, "set_disable_timing -from {%s} -to {%s} ", + from_port->name(), + to_port->name()); + writeGetInstance(inst); + gzprintf(stream_, "\n"); } } if (disable->from()) { LibertyPortSeq from = sortByName(disable->from()); for (const LibertyPort *from_port : from) { - gzprintf(stream_, "set_disable_timing -from {%s} ", - from_port->name()); - writeGetInstance(inst); - gzprintf(stream_, "\n"); + gzprintf(stream_, "set_disable_timing -from {%s} ", + from_port->name()); + writeGetInstance(inst); + gzprintf(stream_, "\n"); } } if (disable->to()) { LibertyPortSeq to = sortByName(disable->to()); for (const LibertyPort *to_port : to) { - gzprintf(stream_, "set_disable_timing -to {%s} ", - to_port->name()); - writeGetInstance(inst); - gzprintf(stream_, "\n"); + gzprintf(stream_, "set_disable_timing -to {%s} ", + to_port->name()); + writeGetInstance(inst); + gzprintf(stream_, "\n"); } } } @@ -1146,7 +1129,7 @@ WriteSdc::writeDisabledEdges() const void WriteSdc::findMatchingEdges(Edge *edge, - EdgeSet &matches) const + EdgeSet &matches) const { Vertex *from_vertex = edge->from(graph_); Vertex *to_vertex = edge->to(graph_); @@ -1161,11 +1144,11 @@ WriteSdc::findMatchingEdges(Edge *edge, bool WriteSdc::edgeSenseIsUnique(Edge *edge, - EdgeSet &matches) const + EdgeSet &matches) const { for (Edge *match : matches) { if (match != edge - && match->sense() == edge->sense()) + && match->sense() == edge->sense()) return false; } return true; @@ -1201,7 +1184,7 @@ WriteSdc::writeExceptions() const sort(exceptions, ExceptionPathLess(network_)); for (ExceptionPath *exception : exceptions) { if (!exception->isFilter() - && !exception->isLoop()) + && !exception->isLoop()) writeException(exception); } } @@ -1237,12 +1220,12 @@ WriteSdc::writeExceptionCmd(ExceptionPath *exception) const if (min_max == MinMaxAll::min()) { // For hold MCPs default is -start. if (exception->useEndClk()) - gzprintf(stream_, " -end"); + gzprintf(stream_, " -end"); } else { // For setup MCPs default is -end. if (!exception->useEndClk()) - gzprintf(stream_, " -start"); + gzprintf(stream_, " -start"); } } else if (exception->isPathDelay()) { @@ -1268,7 +1251,7 @@ WriteSdc::writeExceptionValue(ExceptionPath *exception) const { if (exception->isMultiCycle()) gzprintf(stream_, " %d", - exception->pathMultiplier()); + exception->pathMultiplier()); else if (exception->isPathDelay()) { gzprintf(stream_, " "); writeTime(exception->delay()); @@ -1293,8 +1276,8 @@ WriteSdc::writeExceptionTo(ExceptionTo *to) const void WriteSdc::writeExceptionFromTo(ExceptionFromTo *from_to, - const char *from_to_key, - bool map_hpin_to_drvr) const + const char *from_to_key, + bool map_hpin_to_drvr) const { const RiseFallBoth *rf = from_to->transition(); const char *rf_prefix = "-"; @@ -1314,7 +1297,7 @@ WriteSdc::writeExceptionFromTo(ExceptionFromTo *from_to, PinSeq pins = sortByPathName(from_to->pins(), sdc_network_); for (const Pin *pin : pins) { if (multi_objs && !first) - gzprintf(stream_, "\\\n "); + gzprintf(stream_, "\\\n "); writeGetPin(pin, map_hpin_to_drvr); first = false; } @@ -1325,7 +1308,7 @@ WriteSdc::writeExceptionFromTo(ExceptionFromTo *from_to, InstanceSeq insts = sortByPathName(from_to->instances(), sdc_network_); for (const Instance *inst : insts) { if (multi_objs && !first) - gzprintf(stream_, "\\\n "); + gzprintf(stream_, "\\\n "); writeGetInstance(inst); first = false; } @@ -1365,7 +1348,7 @@ WriteSdc::writeExceptionThru(ExceptionThru *thru) const NetSeq nets = sortByPathName(thru->nets(), sdc_network_); for (const Net *net : nets) { if (multi_objs && !first) - gzprintf(stream_, "\\\n "); + gzprintf(stream_, "\\\n "); writeGetNet(net); first = false; } @@ -1374,7 +1357,7 @@ WriteSdc::writeExceptionThru(ExceptionThru *thru) const InstanceSeq insts = sortByPathName(thru->instances(), sdc_network_); for (const Instance *inst : insts) { if (multi_objs && !first) - gzprintf(stream_, "\\\n "); + gzprintf(stream_, "\\\n "); writeGetInstance(inst); first = false; } @@ -1385,28 +1368,28 @@ WriteSdc::writeExceptionThru(ExceptionThru *thru) const void WriteSdc::mapThruHpins(ExceptionThru *thru, - PinSeq &pins) const + PinSeq &pins) const { if (thru->pins()) { for (const Pin *pin : *thru->pins()) { // Map hierarical pins to load pins outside of outputs or inside of inputs. if (network_->isHierarchical(pin)) { - Instance *hinst = network_->instance(pin); - bool hpin_is_output = network_->direction(pin)->isAnyOutput(); - PinConnectedPinIterator *cpin_iter = network_->connectedPinIterator(pin); - while (cpin_iter->hasNext()) { - const Pin *cpin = cpin_iter->next(); - if (network_->isLoad(cpin) - && ((hpin_is_output - && !network_->isInside(network_->instance(cpin), hinst)) - || (!hpin_is_output - && network_->isInside(network_->instance(cpin), hinst)))) - pins.push_back(cpin); - } - delete cpin_iter; + Instance *hinst = network_->instance(pin); + bool hpin_is_output = network_->direction(pin)->isAnyOutput(); + PinConnectedPinIterator *cpin_iter = network_->connectedPinIterator(pin); + while (cpin_iter->hasNext()) { + const Pin *cpin = cpin_iter->next(); + if (network_->isLoad(cpin) + && ((hpin_is_output + && !network_->isInside(network_->instance(cpin), hinst)) + || (!hpin_is_output + && network_->isInside(network_->instance(cpin), hinst)))) + pins.push_back(cpin); + } + delete cpin_iter; } else - pins.push_back(pin); + pins.push_back(pin); } } } @@ -1416,7 +1399,7 @@ WriteSdc::mapThruHpins(ExceptionThru *thru, void WriteSdc::writeDataChecks() const { - Vector checks; + std::vector checks; for (const auto [pin, checks1] : sdc_->data_checks_to_map_) { for (DataCheck *check : *checks1) checks.push_back(check); @@ -1435,18 +1418,18 @@ WriteSdc::writeDataCheck(DataCheck *check) const check->marginIsOneValue(setup_hold, margin, one_value); if (one_value) writeDataCheck(check, RiseFallBoth::riseFall(), - RiseFallBoth::riseFall(), setup_hold, margin); + RiseFallBoth::riseFall(), setup_hold, margin); else { for (auto from_rf : RiseFall::range()) { - for (auto to_rf : RiseFall::range()) { - float margin; - bool margin_exists; - check->margin(from_rf, to_rf, setup_hold, margin, margin_exists); - if (margin_exists) { - writeDataCheck(check, from_rf->asRiseFallBoth(), - to_rf->asRiseFallBoth(), setup_hold, margin); - } - } + for (auto to_rf : RiseFall::range()) { + float margin; + bool margin_exists; + check->margin(from_rf, to_rf, setup_hold, margin, margin_exists); + if (margin_exists) { + writeDataCheck(check, from_rf->asRiseFallBoth(), + to_rf->asRiseFallBoth(), setup_hold, margin); + } + } } } } @@ -1454,10 +1437,10 @@ WriteSdc::writeDataCheck(DataCheck *check) const void WriteSdc::writeDataCheck(DataCheck *check, - const RiseFallBoth *from_rf, - const RiseFallBoth *to_rf, - const SetupHold *setup_hold, - float margin) const + const RiseFallBoth *from_rf, + const RiseFallBoth *to_rf, + const SetupHold *setup_hold, + float margin) const { const char *from_key = "-from"; if (from_rf == RiseFallBoth::rise()) @@ -1474,7 +1457,7 @@ WriteSdc::writeDataCheck(DataCheck *check, gzprintf(stream_, " %s ", to_key); writeGetPin(check->to(), false); gzprintf(stream_, "%s ", - setupHoldFlag(setup_hold)); + setupHoldFlag(setup_hold)); writeTime(margin); gzprintf(stream_, "\n"); } @@ -1513,14 +1496,13 @@ WriteSdc::writeWireload() const WireloadMode wireload_mode = sdc_->wireloadMode(); if (wireload_mode != WireloadMode::unknown) gzprintf(stream_, "set_wire_load_mode \"%s\"\n", - wireloadModeString(wireload_mode)); + wireloadModeString(wireload_mode)); } void WriteSdc::writeNetLoads() const { - int corner_index = 0; // missing corner arg - for (const auto [net, caps] : sdc_->net_wire_cap_maps_[corner_index]) { + for (const auto [net, caps] : sdc_->net_wire_cap_map_) { float min_cap, max_cap; bool min_exists, max_exists; caps.value(MinMax::min(), min_cap, min_exists); @@ -1539,8 +1521,8 @@ WriteSdc::writeNetLoads() const void WriteSdc::writeNetLoad(const Net *net, - const MinMaxAll *min_max, - float cap) const + const MinMaxAll *min_max, + float cap) const { gzprintf(stream_, "set_load "); gzprintf(stream_, "%s ", minMaxFlag(min_max)); @@ -1564,18 +1546,17 @@ WriteSdc::writePortLoads() const void WriteSdc::writePortLoads(const Port *port) const { - const Corner *corner = corners_->findCorner(0); // missing corner arg - PortExtCap *ext_cap = sdc_->portExtCap(port, corner); + const PortExtCap *ext_cap = sdc_->portExtCap(port); if (ext_cap) { WriteGetPort write_port(port, this); writeRiseFallMinMaxCapCmd("set_load -pin_load", - ext_cap->pinCap(), - write_port); + ext_cap->pinCap(), + write_port); writeRiseFallMinMaxCapCmd("set_load -wire_load", - ext_cap->wireCap(), - write_port); + ext_cap->wireCap(), + write_port); writeMinMaxIntValuesCmd("set_port_fanout_number", - ext_cap->fanout(), write_port); + ext_cap->fanout(), write_port); } } @@ -1588,33 +1569,33 @@ WriteSdc::writeDriveResistances() const InputDrive *drive = sdc_->findInputDrive(port); if (drive) { for (auto rf : RiseFall::range()) { - if (drive->driveResistanceMinMaxEqual(rf)) { - float res; - bool exists; - drive->driveResistance(rf, MinMax::max(), res, exists); - gzprintf(stream_, "set_drive %s ", - transRiseFallFlag(rf)); - writeResistance(res); - gzprintf(stream_, " "); - writeGetPort(port); - gzprintf(stream_, "\n"); - } - else { - for (auto min_max : MinMax::range()) { - float res; - bool exists; - drive->driveResistance(rf, min_max, res, exists); - if (exists) { - gzprintf(stream_, "set_drive %s %s ", - transRiseFallFlag(rf), - minMaxFlag(min_max)); - writeResistance(res); - gzprintf(stream_, " "); - writeGetPort(port); - gzprintf(stream_, "\n"); - } - } - } + if (drive->driveResistanceMinMaxEqual(rf)) { + float res; + bool exists; + drive->driveResistance(rf, MinMax::max(), res, exists); + gzprintf(stream_, "set_drive %s ", + transRiseFallFlag(rf)); + writeResistance(res); + gzprintf(stream_, " "); + writeGetPort(port); + gzprintf(stream_, "\n"); + } + else { + for (auto min_max : MinMax::range()) { + float res; + bool exists; + drive->driveResistance(rf, min_max, res, exists); + if (exists) { + gzprintf(stream_, "set_drive %s %s ", + transRiseFallFlag(rf), + minMaxFlag(min_max)); + writeResistance(res); + gzprintf(stream_, " "); + writeGetPort(port); + gzprintf(stream_, "\n"); + } + } + } } } } @@ -1630,47 +1611,47 @@ WriteSdc::writeDrivingCells() const InputDrive *drive = sdc_->findInputDrive(port); if (drive) { InputDriveCell *drive_rise_min = drive->driveCell(RiseFall::rise(), - MinMax::min()); + MinMax::min()); InputDriveCell *drive_rise_max = drive->driveCell(RiseFall::rise(), - MinMax::max()); + MinMax::max()); InputDriveCell *drive_fall_min = drive->driveCell(RiseFall::fall(), - MinMax::min()); + MinMax::min()); InputDriveCell *drive_fall_max = drive->driveCell(RiseFall::fall(), - MinMax::max()); + MinMax::max()); if (drive_rise_min - && drive_rise_max - && drive_fall_min - && drive_fall_max - && drive_rise_min->equal(drive_rise_max) - && drive_rise_min->equal(drive_fall_min) - && drive_rise_min->equal(drive_fall_max)) - // Only write one set_driving_cell if possible. - writeDrivingCell(port, drive_rise_min, nullptr, nullptr); + && drive_rise_max + && drive_fall_min + && drive_fall_max + && drive_rise_min->equal(drive_rise_max) + && drive_rise_min->equal(drive_fall_min) + && drive_rise_min->equal(drive_fall_max)) + // Only write one set_driving_cell if possible. + writeDrivingCell(port, drive_rise_min, nullptr, nullptr); else { - if (drive_rise_min - && drive_rise_max - && drive_rise_min->equal(drive_rise_max)) - writeDrivingCell(port, drive_rise_min, RiseFall::rise(), nullptr); - else { - if (drive_rise_min) - writeDrivingCell(port, drive_rise_min, RiseFall::rise(), - MinMax::min()); - if (drive_rise_max) - writeDrivingCell(port, drive_rise_max, RiseFall::rise(), - MinMax::max()); - } - if (drive_fall_min - && drive_fall_max - && drive_fall_min->equal(drive_fall_max)) - writeDrivingCell(port, drive_fall_min, RiseFall::fall(), nullptr); - else { - if (drive_fall_min) - writeDrivingCell(port, drive_fall_min, RiseFall::fall(), - MinMax::min()); - if (drive_fall_max) - writeDrivingCell(port, drive_fall_max, RiseFall::fall(), - MinMax::max()); - } + if (drive_rise_min + && drive_rise_max + && drive_rise_min->equal(drive_rise_max)) + writeDrivingCell(port, drive_rise_min, RiseFall::rise(), nullptr); + else { + if (drive_rise_min) + writeDrivingCell(port, drive_rise_min, RiseFall::rise(), + MinMax::min()); + if (drive_rise_max) + writeDrivingCell(port, drive_rise_max, RiseFall::rise(), + MinMax::max()); + } + if (drive_fall_min + && drive_fall_max + && drive_fall_min->equal(drive_fall_max)) + writeDrivingCell(port, drive_fall_min, RiseFall::fall(), nullptr); + else { + if (drive_fall_min) + writeDrivingCell(port, drive_fall_min, RiseFall::fall(), + MinMax::min()); + if (drive_fall_max) + writeDrivingCell(port, drive_fall_max, RiseFall::fall(), + MinMax::max()); + } } } } @@ -1679,9 +1660,9 @@ WriteSdc::writeDrivingCells() const void WriteSdc::writeDrivingCell(Port *port, - InputDriveCell *drive_cell, - const RiseFall *rf, - const MinMax *min_max) const + InputDriveCell *drive_cell, + const RiseFall *rf, + const MinMax *min_max) const { const LibertyCell *cell = drive_cell->cell(); const LibertyPort *from_port = drive_cell->fromPort(); @@ -1699,10 +1680,10 @@ WriteSdc::writeDrivingCell(Port *port, gzprintf(stream_, " -lib_cell %s", cell->name()); if (from_port) gzprintf(stream_, " -from_pin {%s}", - from_port->name()); + from_port->name()); gzprintf(stream_, - " -pin {%s} -input_transition_rise ", - to_port->name()); + " -pin {%s} -input_transition_rise ", + to_port->name()); writeTime(from_slews[RiseFall::riseIndex()]); gzprintf(stream_, " -input_transition_fall "); writeTime(from_slews[RiseFall::fallIndex()]); @@ -1740,21 +1721,21 @@ WriteSdc::writeNetResistances() const sdc_->resistance(net, MinMax::min(), min_res, min_exists); sdc_->resistance(net, MinMax::max(), max_res, max_exists); if (min_exists && max_exists - && min_res == max_res) + && min_res == max_res) writeNetResistance(net, MinMaxAll::all(), min_res); else { if (min_exists) - writeNetResistance(net, MinMaxAll::min(), min_res); + writeNetResistance(net, MinMaxAll::min(), min_res); if (max_exists) - writeNetResistance(net, MinMaxAll::max(), max_res); + writeNetResistance(net, MinMaxAll::max(), max_res); } } } void WriteSdc::writeNetResistance(const Net *net, - const MinMaxAll *min_max, - float res) const + const MinMaxAll *min_max, + float res) const { gzprintf(stream_, "set_resistance "); writeResistance(res); @@ -1844,8 +1825,8 @@ WriteSdc::caseAnalysisValueStr(const Pin *pin) const } void -WriteSdc::sortedLogicValuePins(LogicValueMap &value_map, - PinSeq &pins) const +WriteSdc::sortedLogicValuePins(const LogicValueMap &value_map, + PinSeq &pins) const { for (const auto [pin, value] : value_map) pins.push_back(pin); @@ -1866,7 +1847,7 @@ WriteSdc::writeDeratings() const WriteGetNet write_net(net, this); for (auto early_late : EarlyLate::range()) { writeDerating(factors, TimingDerateType::net_delay, early_late, - &write_net); + &write_net); } } @@ -1888,32 +1869,32 @@ WriteSdc::writeDerating(DeratingFactorsGlobal *factors) const bool delay_is_one_value, check_is_one_value, net_is_one_value; float delay_value, check_value, net_value; factors->factors(TimingDerateType::cell_delay)->isOneValue(early_late, - delay_is_one_value, - delay_value); + delay_is_one_value, + delay_value); factors->factors(TimingDerateType::net_delay)->isOneValue(early_late, - net_is_one_value, - net_value); + net_is_one_value, + net_value); DeratingFactors *cell_check_factors = factors->factors(TimingDerateType::cell_check); cell_check_factors->isOneValue(early_late, check_is_one_value, check_value); if (delay_is_one_value - && net_is_one_value - && delay_value == net_value - && (!cell_check_factors->hasValue() - || (check_is_one_value && check_value == 1.0))) { + && net_is_one_value + && delay_value == net_value + && (!cell_check_factors->hasValue() + || (check_is_one_value && check_value == 1.0))) { if (delay_value != 1.0) { - gzprintf(stream_, "set_timing_derate %s ", earlyLateFlag(early_late)); - writeFloat(delay_value); - gzprintf(stream_, "\n"); + gzprintf(stream_, "set_timing_derate %s ", earlyLateFlag(early_late)); + writeFloat(delay_value); + gzprintf(stream_, "\n"); } } else { for (int type_index = 0; - type_index < timing_derate_type_count; - type_index++) { - TimingDerateType type = static_cast(type_index); - DeratingFactors *type_factors = factors->factors(type); - writeDerating(type_factors, type, early_late, nullptr); + type_index < timing_derate_type_count; + type_index++) { + TimingDerateType type = static_cast(type_index); + DeratingFactors *type_factors = factors->factors(type); + writeDerating(type_factors, type, early_late, nullptr); } } } @@ -1921,7 +1902,7 @@ WriteSdc::writeDerating(DeratingFactorsGlobal *factors) const void WriteSdc::writeDerating(DeratingFactorsCell *factors, - WriteSdcObject *write_obj) const + WriteSdcObject *write_obj) const { for (auto early_late : EarlyLate::range()) { DeratingFactors *delay_factors=factors->factors(TimingDerateCellType::cell_delay); @@ -1933,9 +1914,9 @@ WriteSdc::writeDerating(DeratingFactorsCell *factors, void WriteSdc::writeDerating(DeratingFactors *factors, - TimingDerateType type, - const MinMax *early_late, - WriteSdcObject *write_obj) const + TimingDerateType type, + const MinMax *early_late, + WriteSdcObject *write_obj) const { const char *type_key = timingDerateTypeKeyword(type); bool is_one_value; @@ -1944,57 +1925,57 @@ WriteSdc::writeDerating(DeratingFactors *factors, if (is_one_value) { if (value != 1.0) { gzprintf(stream_, "set_timing_derate %s %s ", - type_key, - earlyLateFlag(early_late)); + type_key, + earlyLateFlag(early_late)); writeFloat(value); if (write_obj) { - gzprintf(stream_, " "); - write_obj->write(); + gzprintf(stream_, " "); + write_obj->write(); } gzprintf(stream_, "\n"); } } else { for (int clk_data_index = 0; - clk_data_index < path_clk_or_data_count; - clk_data_index++) { + clk_data_index < path_clk_or_data_count; + clk_data_index++) { PathClkOrData clk_data = static_cast(clk_data_index); static const char *clk_data_keys[] = {"-clock", "-data"}; const char *clk_data_key = clk_data_keys[clk_data_index]; factors->isOneValue(clk_data, early_late, is_one_value, value); if (is_one_value) { - if (value != 1.0) { - gzprintf(stream_, "set_timing_derate %s %s %s ", - type_key, - earlyLateFlag(early_late), - clk_data_key); - writeFloat(value); - if (write_obj) { - gzprintf(stream_, " "); - write_obj->write(); - } - gzprintf(stream_, "\n"); - } + if (value != 1.0) { + gzprintf(stream_, "set_timing_derate %s %s %s ", + type_key, + earlyLateFlag(early_late), + clk_data_key); + writeFloat(value); + if (write_obj) { + gzprintf(stream_, " "); + write_obj->write(); + } + gzprintf(stream_, "\n"); + } } else { - for (auto rf : RiseFall::range()) { - float factor; - bool exists; - factors->factor(clk_data, rf, early_late, factor, exists); - if (exists) { - gzprintf(stream_, "set_timing_derate %s %s %s %s ", - type_key, - clk_data_key, - transRiseFallFlag(rf), - earlyLateFlag(early_late)); - writeFloat(factor); - if (write_obj) { - gzprintf(stream_, " "); - write_obj->write(); - } - gzprintf(stream_, "\n"); - } - } + for (auto rf : RiseFall::range()) { + float factor; + bool exists; + factors->factor(clk_data, rf, early_late, factor, exists); + if (exists) { + gzprintf(stream_, "set_timing_derate %s %s %s %s ", + type_key, + clk_data_key, + transRiseFallFlag(rf), + earlyLateFlag(early_late)); + writeFloat(factor); + if (write_obj) { + gzprintf(stream_, " "); + write_obj->write(); + } + gzprintf(stream_, "\n"); + } + } } } } @@ -2077,7 +2058,7 @@ WriteSdc::writeMinPulseWidths() const void WriteSdc::writeMinPulseWidths(RiseFallValues *min_widths, - WriteSdcObject &write_obj) const + WriteSdcObject &write_obj) const { bool hi_exists, low_exists; float hi, low; @@ -2096,8 +2077,8 @@ WriteSdc::writeMinPulseWidths(RiseFallValues *min_widths, void WriteSdc::writeMinPulseWidth(const char *hi_low, - float value, - WriteSdcObject &write_obj) const + float value, + WriteSdcObject &write_obj) const { gzprintf(stream_, "set_min_pulse_width %s", hi_low); writeTime(value); @@ -2172,44 +2153,43 @@ void WriteSdc::writeClkSlewLimits() const { const MinMax *min_max = MinMax::max(); - ClockSeq clks; - sdc_->sortedClocks(clks); + ClockSeq clks = sdc_->sortedClocks(); for (const Clock *clk : clks) { float rise_clk_limit, fall_clk_limit, rise_data_limit, fall_data_limit; bool rise_clk_exists, fall_clk_exists, rise_data_exists, fall_data_exists; clk->slewLimit(RiseFall::rise(), PathClkOrData::clk, min_max, - rise_clk_limit, rise_clk_exists); + rise_clk_limit, rise_clk_exists); clk->slewLimit(RiseFall::fall(), PathClkOrData::clk, min_max, - fall_clk_limit, fall_clk_exists); + fall_clk_limit, fall_clk_exists); clk->slewLimit(RiseFall::rise(), PathClkOrData::data, min_max, - rise_data_limit, rise_data_exists); + rise_data_limit, rise_data_exists); clk->slewLimit(RiseFall::fall(), PathClkOrData::data, min_max, - fall_data_limit, fall_data_exists); + fall_data_limit, fall_data_exists); if (rise_clk_exists && fall_clk_exists - && rise_data_exists && fall_data_exists - && fall_clk_limit == rise_clk_limit - && rise_data_limit == rise_clk_limit - && fall_data_limit == rise_clk_limit) + && rise_data_exists && fall_data_exists + && fall_clk_limit == rise_clk_limit + && rise_data_limit == rise_clk_limit + && fall_data_limit == rise_clk_limit) writeClkSlewLimit("", "", clk, rise_clk_limit); else { if (rise_clk_exists && fall_clk_exists - && fall_clk_limit == rise_clk_limit) - writeClkSlewLimit("-clock_path ", "", clk, rise_clk_limit); + && fall_clk_limit == rise_clk_limit) + writeClkSlewLimit("-clock_path ", "", clk, rise_clk_limit); else { - if (rise_clk_exists) - writeClkSlewLimit("-clock_path ", "-rise ", clk, rise_clk_limit); - if (fall_clk_exists) - writeClkSlewLimit("-clock_path ", "-fall ", clk, fall_clk_limit); + if (rise_clk_exists) + writeClkSlewLimit("-clock_path ", "-rise ", clk, rise_clk_limit); + if (fall_clk_exists) + writeClkSlewLimit("-clock_path ", "-fall ", clk, fall_clk_limit); } if (rise_data_exists && fall_data_exists - && fall_data_limit == rise_data_limit) - writeClkSlewLimit("-data_path ", "", clk, rise_data_limit); + && fall_data_limit == rise_data_limit) + writeClkSlewLimit("-data_path ", "", clk, rise_data_limit); else { - if (rise_data_exists) - writeClkSlewLimit("-data_path ", "-rise ", clk, rise_data_limit); - if (fall_data_exists) { - writeClkSlewLimit("-data_path ", "-fall ", clk, fall_data_limit); - } + if (rise_data_exists) + writeClkSlewLimit("-data_path ", "-rise ", clk, rise_data_limit); + if (fall_data_exists) { + writeClkSlewLimit("-data_path ", "-fall ", clk, fall_data_limit); + } } } } @@ -2217,9 +2197,9 @@ WriteSdc::writeClkSlewLimits() const void WriteSdc::writeClkSlewLimit(const char *clk_data, - const char *rise_fall, - const Clock *clk, - float limit) const + const char *rise_fall, + const Clock *clk, + float limit) const { gzprintf(stream_, "set_max_transition %s%s", clk_data, rise_fall); writeTime(limit); @@ -2237,7 +2217,7 @@ WriteSdc::writeCapLimits() const void WriteSdc::writeCapLimits(const MinMax *min_max, - const char *cmd) const + const char *cmd) const { float cap; bool exists; @@ -2295,7 +2275,7 @@ WriteSdc::writeFanoutLimits() const void WriteSdc::writeFanoutLimits(const MinMax *min_max, - const char *cmd) const + const char *cmd) const { float fanout; bool exists; @@ -2311,11 +2291,11 @@ WriteSdc::writeFanoutLimits(const MinMax *min_max, Port *port = port_iter->next(); sdc_->fanoutLimit(port, min_max, fanout, exists); if (exists) { - gzprintf(stream_, "%s ", cmd); - writeFloat(fanout); - gzprintf(stream_, " "); - writeGetPort(port); - gzprintf(stream_, "\n"); + gzprintf(stream_, "%s ", cmd); + writeFloat(fanout); + gzprintf(stream_, " "); + writeGetPort(port); + gzprintf(stream_, "\n"); } } delete port_iter; @@ -2359,7 +2339,7 @@ WriteSdc::writeGetTimingArcs(Edge *edge) const void WriteSdc::writeGetTimingArcs(Edge *edge, - const char *filter) const + const char *filter) const { gzprintf(stream_, "[%s -from ", getTimingArcsCmd()); Vertex *from_vertex = edge->from(graph_); @@ -2384,8 +2364,8 @@ void WriteSdc::writeGetLibCell(const LibertyCell *cell) const { gzprintf(stream_, "[get_lib_cells {%s/%s}]", - cell->libertyLibrary()->name(), - cell->name()); + cell->libertyLibrary()->name(), + cell->name()); } void @@ -2394,9 +2374,9 @@ WriteSdc::writeGetLibPin(const LibertyPort *port) const LibertyCell *cell = port->libertyCell(); LibertyLibrary *lib = cell->libertyLibrary(); gzprintf(stream_, "[get_lib_pins {%s/%s/%s}]", - lib->name(), - cell->name(), - port->name()); + lib->name(), + cell->name(), + port->name()); } void @@ -2413,8 +2393,8 @@ WriteSdc::writeGetClocks(ClockSet *clks) const void WriteSdc::writeGetClocks(ClockSet *clks, - bool multiple, - bool &first) const + bool multiple, + bool &first) const { ClockSeq clks1 = sortByName(clks); for (const Clock *clk : clks1) { @@ -2429,7 +2409,7 @@ void WriteSdc::writeGetClock(const Clock *clk) const { gzprintf(stream_, "[get_clocks {%s}]", - clk->name()); + clk->name()); } void @@ -2440,19 +2420,19 @@ WriteSdc::writeGetPort(const Port *port) const void WriteSdc::writeGetPins(const PinSet *pins, - bool map_hpin_to_drvr) const + bool map_hpin_to_drvr) const { if (map_hpins_) { PinSet leaf_pins(network_);; for (const Pin *pin : *pins) { if (network_->isHierarchical(pin)) { - if (map_hpin_to_drvr) - findLeafDriverPins(const_cast(pin), network_, &leaf_pins); - else - findLeafLoadPins(const_cast(pin), network_, &leaf_pins); + if (map_hpin_to_drvr) + findLeafDriverPins(const_cast(pin), network_, &leaf_pins); + else + findLeafLoadPins(const_cast(pin), network_, &leaf_pins); } else - leaf_pins.insert(pin); + leaf_pins.insert(pin); } PinSeq pins1 = sortByPathName(&leaf_pins, sdc_network_); writeGetPins1(&pins1); @@ -2491,7 +2471,7 @@ WriteSdc::writeGetPin(const Pin *pin) const void WriteSdc::writeGetPin(const Pin *pin, - bool map_hpin_to_drvr) const + bool map_hpin_to_drvr) const { if (map_hpins_ && network_->isHierarchical(pin)) { PinSet pins(network_); @@ -2562,101 +2542,101 @@ WriteSdc::writeCommentSeparator() const void WriteSdc::writeRiseFallMinMaxTimeCmd(const char *sdc_cmd, - const RiseFallMinMax *values, - WriteSdcObject &write_object) const + const RiseFallMinMax *values, + WriteSdcObject &write_object) const { writeRiseFallMinMaxCmd(sdc_cmd, values, units_->timeUnit()->scale(), - write_object); + write_object); } void WriteSdc::writeRiseFallMinMaxCapCmd(const char *sdc_cmd, - const RiseFallMinMax *values, - WriteSdcObject &write_object) const + const RiseFallMinMax *values, + WriteSdcObject &write_object) const { writeRiseFallMinMaxCmd(sdc_cmd, values, units_->capacitanceUnit()->scale(), - write_object); + write_object); } void WriteSdc::writeRiseFallMinMaxCmd(const char *sdc_cmd, - const RiseFallMinMax *values, - float scale, - WriteSdcObject &write_object) const + const RiseFallMinMax *values, + float scale, + WriteSdcObject &write_object) const { float fall_min, fall_max, rise_min, rise_max; bool fall_min_exists, fall_max_exists, rise_min_exists, rise_max_exists; values->value(RiseFall::fall(), MinMax::min(), - fall_min, fall_min_exists); + fall_min, fall_min_exists); values->value(RiseFall::fall(), MinMax::max(), - fall_max, fall_max_exists); + fall_max, fall_max_exists); values->value(RiseFall::rise(), MinMax::min(), - rise_min, rise_min_exists); + rise_min, rise_min_exists); values->value(RiseFall::rise(), MinMax::max(), - rise_max, rise_max_exists); + rise_max, rise_max_exists); if (fall_min_exists && fall_max_exists && rise_min_exists && rise_max_exists) { if (fall_min == rise_min - && rise_max == rise_min - && fall_max == rise_min) { + && rise_max == rise_min + && fall_max == rise_min) { // rise/fall/min/max match. writeRiseFallMinMaxCmd(sdc_cmd, rise_min, scale, - RiseFallBoth::riseFall(), MinMaxAll::all(), - write_object); + RiseFallBoth::riseFall(), MinMaxAll::all(), + write_object); } else if (rise_min == fall_min - && rise_max == fall_max) { + && rise_max == fall_max) { // rise/fall match. writeRiseFallMinMaxCmd(sdc_cmd, rise_min, scale, - RiseFallBoth::riseFall(), MinMaxAll::min(), - write_object); + RiseFallBoth::riseFall(), MinMaxAll::min(), + write_object); writeRiseFallMinMaxCmd(sdc_cmd, rise_max, scale, - RiseFallBoth::riseFall(), MinMaxAll::max(), - write_object); + RiseFallBoth::riseFall(), MinMaxAll::max(), + write_object); } else if (rise_min == rise_max - && fall_min == fall_max) { + && fall_min == fall_max) { // min/max match. writeRiseFallMinMaxCmd(sdc_cmd, rise_min, scale, - RiseFallBoth::rise(), MinMaxAll::all(), - write_object); + RiseFallBoth::rise(), MinMaxAll::all(), + write_object); writeRiseFallMinMaxCmd(sdc_cmd, fall_min, scale, - RiseFallBoth::fall(), MinMaxAll::all(), - write_object); + RiseFallBoth::fall(), MinMaxAll::all(), + write_object); } } else { if (rise_min_exists) writeRiseFallMinMaxCmd(sdc_cmd, rise_min, scale, - RiseFallBoth::rise(), MinMaxAll::min(), - write_object); + RiseFallBoth::rise(), MinMaxAll::min(), + write_object); if (rise_max_exists) writeRiseFallMinMaxCmd(sdc_cmd, rise_max, scale, - RiseFallBoth::rise(), MinMaxAll::max(), - write_object); + RiseFallBoth::rise(), MinMaxAll::max(), + write_object); if (fall_min_exists) writeRiseFallMinMaxCmd(sdc_cmd, fall_min, scale, - RiseFallBoth::fall(), MinMaxAll::min(), - write_object); + RiseFallBoth::fall(), MinMaxAll::min(), + write_object); if (fall_max_exists) writeRiseFallMinMaxCmd(sdc_cmd, fall_max, scale, - RiseFallBoth::fall(), MinMaxAll::max(), - write_object); + RiseFallBoth::fall(), MinMaxAll::max(), + write_object); } } void WriteSdc::writeRiseFallMinMaxCmd(const char *sdc_cmd, - float value, - float scale, - const RiseFallBoth *rf, - const MinMaxAll *min_max, - WriteSdcObject &write_object) const + float value, + float scale, + const RiseFallBoth *rf, + const MinMaxAll *min_max, + WriteSdcObject &write_object) const { gzprintf(stream_, "%s%s%s ", - sdc_cmd, - transRiseFallFlag(rf), - minMaxFlag(min_max)); + sdc_cmd, + transRiseFallFlag(rf), + minMaxFlag(min_max)); writeFloat(value / scale); gzprintf(stream_, " "); write_object.write(); @@ -2674,9 +2654,9 @@ WriteSdc::writeClockKey(const Clock *clk) const void WriteSdc::writeMinMaxFloatValuesCmd(const char *sdc_cmd, - MinMaxFloatValues *values, - float scale, - WriteSdcObject &write_object) const + const MinMaxFloatValues *values, + float scale, + WriteSdcObject &write_object) const { float min, max; bool min_exists, max_exists; @@ -2697,14 +2677,14 @@ WriteSdc::writeMinMaxFloatValuesCmd(const char *sdc_cmd, void WriteSdc::writeMinMaxFloatCmd(const char *sdc_cmd, - float value, - float scale, - const MinMaxAll *min_max, - WriteSdcObject &write_object) const + float value, + float scale, + const MinMaxAll *min_max, + WriteSdcObject &write_object) const { gzprintf(stream_, "%s%s ", - sdc_cmd, - minMaxFlag(min_max)); + sdc_cmd, + minMaxFlag(min_max)); writeFloat(value / scale); gzprintf(stream_, " "); write_object.write(); @@ -2713,8 +2693,8 @@ WriteSdc::writeMinMaxFloatCmd(const char *sdc_cmd, void WriteSdc::writeMinMaxIntValuesCmd(const char *sdc_cmd, - MinMaxIntValues *values, - WriteSdcObject &write_object) const + const MinMaxIntValues *values, + WriteSdcObject &write_object) const { int min, max; bool min_exists, max_exists; @@ -2735,13 +2715,13 @@ WriteSdc::writeMinMaxIntValuesCmd(const char *sdc_cmd, void WriteSdc::writeMinMaxIntCmd(const char *sdc_cmd, - int value, - const MinMaxAll *min_max, - WriteSdcObject &write_object) const + int value, + const MinMaxAll *min_max, + WriteSdcObject &write_object) const { gzprintf(stream_, "%s%s ", - sdc_cmd, - minMaxFlag(min_max)); + sdc_cmd, + minMaxFlag(min_max)); gzprintf(stream_, "%d ", value); write_object.write(); gzprintf(stream_, "\n"); @@ -2793,7 +2773,7 @@ WriteSdc::writeResistance(float res) const void WriteSdc::writeFloatSeq(FloatSeq *floats, - float scale) const + float scale) const { gzprintf(stream_, "{"); bool first = true; diff --git a/sdc/WriteSdcPvt.hh b/sdc/WriteSdcPvt.hh index 90392d9c..7fd42340 100644 --- a/sdc/WriteSdcPvt.hh +++ b/sdc/WriteSdcPvt.hh @@ -36,13 +36,13 @@ class WriteSdcObject; class WriteSdc : public StaState { public: - WriteSdc(Instance *instance, - const char *creator, - bool map_hpins, - bool native, - int digits, - bool no_timestamp, - Sdc *sdc); + WriteSdc(const Sdc *sdc, + Instance *instance, + const char *creator, + bool map_hpins, + bool native, + int digits, + bool no_timestamp); virtual ~WriteSdc(); void write(const char *filename, bool gzip); @@ -61,49 +61,49 @@ public: void writeDisabledEdges() const; void writeDisabledEdge(Edge *edge) const; void findMatchingEdges(Edge *edge, - EdgeSet &matches) const; + EdgeSet &matches) const; bool edgeSenseIsUnique(Edge *edge, - EdgeSet &matches) const; + EdgeSet &matches) const; void writeDisabledEdgeSense(Edge *edge) const; void writeClocks() const; void writeClock(Clock *clk) const; void writeGeneratedClock(Clock *clk) const; void writeClockPins(const Clock *clk) const; void writeFloatSeq(FloatSeq *floats, - float scale) const; + float scale) const; void writeIntSeq(IntSeq *ints) const; void writeClockSlews(const Clock *clk) const; void writeClockUncertainty(const Clock *clk) const; void writeClockUncertainty(const Clock *clk, - const char *setup_hold, - float value) const; + const char *setup_hold, + float value) const; void writeClockUncertaintyPins() const; void writeClockUncertaintyPin(const Pin *pin, - ClockUncertainties *uncertainties) const; + ClockUncertainties *uncertainties) const; void writeClockUncertaintyPin(const Pin *pin, - const char *setup_hold, - float value) const; + const char *setup_hold, + float value) const; void writeClockLatencies() const; void writeClockInsertions() const; void writeClockInsertion(ClockInsertion *insert, - WriteSdcObject &write_obj) const; + WriteSdcObject &write_obj) const; void writeInterClockUncertainties() const; void writeInterClockUncertainty(InterClockUncertainty *uncertainty) const; void writePropagatedClkPins() const; void writeInputDelays() const; void writeOutputDelays() const; void writePortDelay(PortDelay *port_delay, - bool is_input_delay, - const char *sdc_cmd) const; + bool is_input_delay, + const char *sdc_cmd) const; void writePortDelay(PortDelay *port_delay, - bool is_input_delay, - float delay, - const RiseFallBoth *rf, - const MinMaxAll *min_max, - const char *sdc_cmd) const; + bool is_input_delay, + float delay, + const RiseFallBoth *rf, + const MinMaxAll *min_max, + const char *sdc_cmd) const; void writeClockSenses() const; void writeClockSense(PinClockPair &pin_clk, - ClockSense sense) const; + ClockSense sense) const; void writeClockGroups() const; void writeClockGroups(ClockGroups *clk_groups) const; void writeExceptions() const; @@ -113,25 +113,25 @@ public: void writeExceptionFrom(ExceptionFrom *from) const; void writeExceptionTo(ExceptionTo *to) const; void writeExceptionFromTo(ExceptionFromTo *from_to, - const char *from_to_key, - bool map_hpin_to_drvr) const; + const char *from_to_key, + bool map_hpin_to_drvr) const; void writeExceptionThru(ExceptionThru *thru) const; void mapThruHpins(ExceptionThru *thru, - PinSeq &pins) const; + PinSeq &pins) const; void writeDataChecks() const; void writeDataCheck(DataCheck *check) const; void writeDataCheck(DataCheck *check, - const RiseFallBoth *from_rf, - const RiseFallBoth *to_rf, - const SetupHold *setup_hold, - float margin) const; + const RiseFallBoth *from_rf, + const RiseFallBoth *to_rf, + const SetupHold *setup_hold, + float margin) const; void writeEnvironment() const; void writeOperatingConditions() const; void writeWireload() const; virtual void writeNetLoads() const; void writeNetLoad(const Net *net, - const MinMaxAll *min_max, - float cap) const; + const MinMaxAll *min_max, + float cap) const; void writePortLoads() const; void writePortLoads(const Port *port) const; void writePortFanout(const Port *port) const; @@ -139,45 +139,45 @@ public: void writeDrivingCells() const; void writeInputTransitions() const; void writeDrivingCell(Port *port, - InputDriveCell *drive_cell, - const RiseFall *rf, - const MinMax *min_max) const; + InputDriveCell *drive_cell, + const RiseFall *rf, + const MinMax *min_max) const; void writeConstants() const; virtual void writeConstant(const Pin *pin) const; const char *setConstantCmd(const Pin *pin) const; void writeCaseAnalysis() const; virtual void writeCaseAnalysis(const Pin *pin) const; const char *caseAnalysisValueStr(const Pin *pin) const; - void sortedLogicValuePins(LogicValueMap &value_map, - PinSeq &pins) const; + void sortedLogicValuePins(const LogicValueMap &value_map, + PinSeq &pins) const; void writeNetResistances() const; void writeNetResistance(const Net *net, - const MinMaxAll *min_max, - float res) const; + const MinMaxAll *min_max, + float res) const; void writeDesignRules() const; void writeMinPulseWidths() const; void writeMinPulseWidths(RiseFallValues *min_widths, - WriteSdcObject &write_obj) const; + WriteSdcObject &write_obj) const; void writeMinPulseWidth(const char *hi_low, - float value, - WriteSdcObject &write_obj) const; + float value, + WriteSdcObject &write_obj) const; void writeSlewLimits() const; void writeCapLimits() const; void writeCapLimits(const MinMax *min_max, - const char *cmd) const; + const char *cmd) const; void writeMaxArea() const; void writeFanoutLimits() const; void writeFanoutLimits(const MinMax *min_max, - const char *cmd) const; + const char *cmd) const; void writeLatchBorowLimits() const; void writeDeratings() const; void writeDerating(DeratingFactorsGlobal *factors) const; void writeDerating(DeratingFactorsCell *factors, - WriteSdcObject *write_obj) const; + WriteSdcObject *write_obj) const; void writeDerating(DeratingFactors *factors, - TimingDerateType type, - const MinMax *early_late, - WriteSdcObject *write_obj) const; + TimingDerateType type, + const MinMax *early_late, + WriteSdcObject *write_obj) const; void writeVoltages() const; const char *pathName(const Pin *pin) const; @@ -189,23 +189,23 @@ public: void writeGetTimingArcsOfOjbects(const LibertyCell *cell) const; void writeGetTimingArcs(Edge *edge) const; void writeGetTimingArcs(Edge *edge, - const char *filter) const; + const char *filter) const; const char *getTimingArcsCmd() const; void writeGetLibCell(const LibertyCell *cell) const; void writeGetLibPin(const LibertyPort *port) const; void writeGetClock(const Clock *clk) const; void writeGetClocks(ClockSet *clks) const; void writeGetClocks(ClockSet *clks, - bool multiple, - bool &first) const; + bool multiple, + bool &first) const; virtual void writeGetPort(const Port *port) const; virtual void writeGetNet(const Net *net) const; virtual void writeGetInstance(const Instance *inst) const; virtual void writeGetPin(const Pin *pin) const; void writeGetPin(const Pin *pin, - bool map_hpin_to_drvr) const; + bool map_hpin_to_drvr) const; void writeGetPins(const PinSet *pins, - bool map_hpin_to_drvr) const; + bool map_hpin_to_drvr) const; void writeGetPins1(PinSeq *pins) const; void writeClockKey(const Clock *clk) const; float scaleTime(float time) const; @@ -218,41 +218,41 @@ public: void writeClkSlewLimits() const; void writeClkSlewLimit(const char *clk_data, - const char *rise_fall, - const Clock *clk, - float limit) const; + const char *rise_fall, + const Clock *clk, + float limit) const; void writeRiseFallMinMaxTimeCmd(const char *sdc_cmd, - const RiseFallMinMax *values, - WriteSdcObject &write_object) const; + const RiseFallMinMax *values, + WriteSdcObject &write_object) const; void writeRiseFallMinMaxCapCmd(const char *sdc_cmd, - const RiseFallMinMax *values, - WriteSdcObject &write_object) const; + const RiseFallMinMax *values, + WriteSdcObject &write_object) const; void writeRiseFallMinMaxCmd(const char *sdc_cmd, - const RiseFallMinMax *values, - float scale, - WriteSdcObject &write_object) const; + const RiseFallMinMax *values, + float scale, + WriteSdcObject &write_object) const; void writeRiseFallMinMaxCmd(const char *sdc_cmd, - float value, - float scale, - const RiseFallBoth *rf, - const MinMaxAll *min_max, - WriteSdcObject &write_object) const; + float value, + float scale, + const RiseFallBoth *rf, + const MinMaxAll *min_max, + WriteSdcObject &write_object) const; void writeMinMaxFloatValuesCmd(const char *sdc_cmd, - MinMaxFloatValues *values, - float scale, - WriteSdcObject &write_object) const; + const MinMaxFloatValues *values, + float scale, + WriteSdcObject &write_object) const; void writeMinMaxFloatCmd(const char *sdc_cmd, - float value, - float scale, - const MinMaxAll *min_max, - WriteSdcObject &write_object) const; + float value, + float scale, + const MinMaxAll *min_max, + WriteSdcObject &write_object) const; void writeMinMaxIntValuesCmd(const char *sdc_cmd, - MinMaxIntValues *values, - WriteSdcObject &write_object) const; + const MinMaxIntValues *values, + WriteSdcObject &write_object) const; void writeMinMaxIntCmd(const char *sdc_cmd, - int value, - const MinMaxAll *min_max, - WriteSdcObject &write_object) const; + int value, + const MinMaxAll *min_max, + WriteSdcObject &write_object) const; void writeSetupHoldFlag(const MinMaxAll *min_max) const; void writeVariables() const; void writeCmdComment(SdcCmdComment *cmd) const; @@ -260,6 +260,7 @@ public: gzFile stream() const { return stream_; } protected: + const Sdc *sdc_; Instance *instance_; const char *creator_; bool map_hpins_; diff --git a/sdf/ReportAnnotation.cc b/sdf/ReportAnnotation.cc index 649853e9..63ecbcc6 100644 --- a/sdf/ReportAnnotation.cc +++ b/sdf/ReportAnnotation.cc @@ -33,45 +33,46 @@ #include "Graph.hh" #include "GraphCmp.hh" #include "Sdc.hh" -#include "DcalcAnalysisPt.hh" namespace sta { class ReportAnnotated : public StaState { public: - ReportAnnotated(bool report_cells, - bool report_nets, - bool report_in_ports, - bool report_out_ports, - int max_lines, - bool list_annotated, - bool list_unannotated, - bool constant_arcs, - StaState *sta); - ReportAnnotated(bool report_setup, - bool report_hold, - bool report_recovery, - bool report_removal, - bool report_nochange, - bool report_width, - bool report_period, - bool report_max_skew, - int max_lines, - bool list_annotated, - bool list_unannotated, - bool constant_arcs, - StaState *sta); + ReportAnnotated(const Scene *scene, + bool report_cells, + bool report_nets, + bool report_in_ports, + bool report_out_ports, + int max_lines, + bool report_annotated, + bool report_unannotated, + bool constant_arcs, + StaState *sta); + ReportAnnotated(const Scene *scene, + bool report_setup, + bool report_hold, + bool report_recovery, + bool report_removal, + bool report_nochange, + bool report_width, + bool report_period, + bool report_max_skew, + int max_lines, + bool report_annotated, + bool report_unannotated, + bool constant_arcs, + StaState *sta); void reportDelayAnnotation(); void reportCheckAnnotation(); protected: - enum CountIndex { + enum class CountIndex { count_internal_net = TimingRole::index_max, count_input_net, count_output_net, - count_index_max }; + static const int count_index_max = static_cast(CountIndex::count_output_net) + 1; static int count_delay; void init(); @@ -81,28 +82,30 @@ protected: void reportCheckCounts(); void reportArcs(); void reportArcs(const char *header, - bool report_annotated, - PinSet &pins); + bool report_annotated, + PinSet &pins); void reportArcs(Vertex *vertex, - bool report_annotated, - int &i); + bool report_annotated, + int &i); void reportPeriodArcs(const Pin *pin, bool report_annotated, int &i); void reportCount(const char *title, - int index, - int &total, - int &annotated_total); + int index, + int &total, + int &annotated_total); void reportCheckCount(const TimingRole *role, - int &total, - int &annotated_total); + int &total, + int &annotated_total); int roleIndex(const TimingRole *role, - const Pin *from_pin, - const Pin *to_pin); + const Pin *from_pin, + const Pin *to_pin); + bool delayAnnotated(Edge *edge); + const Scene *scene_; int max_lines_; - bool list_annotated_; - bool list_unannotated_; + bool report_annotated_; + bool report_unannotated_; bool report_constant_arcs_; int edge_count_[count_index_max]; @@ -118,45 +121,48 @@ protected: int ReportAnnotated::count_delay; void -reportAnnotatedDelay(bool report_cells, - bool report_nets, - bool from_in_ports, - bool to_out_ports, - int max_lines, - bool list_annotated, - bool list_unannotated, - bool report_constant_arcs, - StaState *sta) +reportAnnotatedDelay(const Scene *scene, + bool report_cells, + bool report_nets, + bool from_in_ports, + bool to_out_ports, + int max_lines, + bool report_annotated, + bool report_unannotated, + bool report_constant_arcs, + StaState *sta) { - ReportAnnotated report_annotated(report_cells, report_nets, - from_in_ports, to_out_ports, - max_lines, list_annotated, list_unannotated, - report_constant_arcs, sta); - report_annotated.reportDelayAnnotation(); + ReportAnnotated report(scene, report_cells, report_nets, + from_in_ports, to_out_ports, + max_lines, report_annotated, report_unannotated, + report_constant_arcs, sta); + report.reportDelayAnnotation(); } -ReportAnnotated::ReportAnnotated(bool report_cells, - bool report_nets, - bool report_in_ports, - bool report_out_ports, - int max_lines, - bool list_annotated, - bool list_unannotated, - bool report_constant_arcs, - StaState *sta) : +ReportAnnotated::ReportAnnotated(const Scene *scene, + bool report_cells, + bool report_nets, + bool report_in_ports, + bool report_out_ports, + int max_lines, + bool report_annotated, + bool report_unannotated, + bool report_constant_arcs, + StaState *sta) : StaState(sta), + scene_(scene), max_lines_(max_lines), - list_annotated_(list_annotated), - list_unannotated_(list_unannotated), + report_annotated_(report_annotated), + report_unannotated_(report_unannotated), report_constant_arcs_(report_constant_arcs), unannotated_pins_(sta->network()), annotated_pins_(sta->network()) { init(); report_role_[TimingRole::sdfIopath()->index()] = report_cells; - report_role_[count_internal_net] = report_nets; - report_role_[count_input_net] = report_in_ports; - report_role_[count_output_net] = report_out_ports; + report_role_[static_cast(CountIndex::count_internal_net)] = report_nets; + report_role_[static_cast(CountIndex::count_input_net)] = report_in_ports; + report_role_[static_cast(CountIndex::count_output_net)] = report_out_ports; } void @@ -177,11 +183,11 @@ ReportAnnotated::reportDelayCounts() int total = 0; int annotated_total = 0; reportCount("cell arcs", count_delay, total, annotated_total); - reportCount("internal net arcs", count_internal_net, total, annotated_total); - reportCount("net arcs from primary inputs", count_input_net, - total, annotated_total); - reportCount("net arcs to primary outputs", count_output_net, - total, annotated_total); + reportCount("internal net arcs", static_cast(CountIndex::count_internal_net), total, annotated_total); + reportCount("net arcs from primary inputs", static_cast(CountIndex::count_input_net), + total, annotated_total); + reportCount("net arcs to primary outputs", static_cast(CountIndex::count_output_net), + total, annotated_total); report_->reportLine("----------------------------------------------------------------"); report_->reportLine("%-28s %10u %10u %10u", " ", @@ -193,47 +199,50 @@ ReportAnnotated::reportDelayCounts() //////////////////////////////////////////////////////////////// void -reportAnnotatedCheck(bool report_setup, - bool report_hold, - bool report_recovery, - bool report_removal, - bool report_nochange, - bool report_width, - bool report_period, - bool report_max_skew, - int max_lines, - bool list_annotated, - bool list_unannotated, - bool report_constant_arcs, - StaState *sta) +reportAnnotatedCheck(const Scene *scene, + bool report_setup, + bool report_hold, + bool report_recovery, + bool report_removal, + bool report_nochange, + bool report_width, + bool report_period, + bool report_max_skew, + int max_lines, + bool report_annotated, + bool report_unannotated, + bool report_constant_arcs, + StaState *sta) { - ReportAnnotated report_annotated(report_setup, report_hold, - report_recovery, report_removal, - report_nochange, report_width, - report_period, report_max_skew, - max_lines, list_annotated, list_unannotated, - report_constant_arcs, sta); - report_annotated.reportCheckAnnotation(); + ReportAnnotated report(scene, report_setup, report_hold, + report_recovery, report_removal, + report_nochange, report_width, + report_period, report_max_skew, + max_lines, report_annotated, report_unannotated, + report_constant_arcs, sta); + report.reportCheckAnnotation(); } -ReportAnnotated::ReportAnnotated(bool report_setup, - bool report_hold, - bool report_recovery, - bool report_removal, - bool report_nochange, - bool report_width, - bool report_period, - bool report_max_skew, - int max_lines, - bool list_annotated, - bool list_unannotated, - bool report_constant_arcs, - StaState *sta) : +ReportAnnotated::ReportAnnotated(const Scene *scene, + bool report_setup, + bool report_hold, + bool report_recovery, + bool report_removal, + bool report_nochange, + bool report_width, + bool report_period, + bool report_max_skew, + int max_lines, + bool report_annotated, + bool report_unannotated, + bool report_constant_arcs, + StaState *sta) : StaState(sta), + scene_(scene), max_lines_(max_lines), - list_annotated_(list_annotated), - list_unannotated_(list_unannotated), + report_annotated_(report_annotated), + report_unannotated_(report_unannotated), report_constant_arcs_(report_constant_arcs), unannotated_pins_(sta->network()), annotated_pins_(sta->network()) @@ -285,8 +294,8 @@ ReportAnnotated::reportCheckCounts() void ReportAnnotated::reportCheckCount(const TimingRole *role, - int &total, - int &annotated_total) + int &total, + int &annotated_total) { int index = role->index(); if (edge_count_[index] > 0) { @@ -314,14 +323,15 @@ ReportAnnotated::init() void ReportAnnotated::findCounts() { + const Sdc *sdc = scene_->sdc(); VertexIterator vertex_iter(graph_); while (vertex_iter.hasNext()) { Vertex *from_vertex = vertex_iter.next(); Pin *from_pin = from_vertex->pin(); LogicValue from_logic_value; bool from_logic_value_exists; - sdc_->logicValue(from_pin, from_logic_value, - from_logic_value_exists); + sdc->logicValue(from_pin, from_logic_value, + from_logic_value_exists); VertexOutEdgeIterator edge_iter(from_vertex, graph_); while (edge_iter.hasNext()) { Edge *edge = edge_iter.next(); @@ -331,50 +341,64 @@ ReportAnnotated::findCounts() int index = roleIndex(role, from_pin, to_pin); LogicValue to_logic_value; bool to_logic_value_exists; - sdc_->logicValue(to_pin, to_logic_value, - to_logic_value_exists); + sdc->logicValue(to_pin, to_logic_value, + to_logic_value_exists); edge_count_[index]++; if (from_logic_value_exists || to_logic_value_exists) - edge_constant_count_[index]++; + edge_constant_count_[index]++; if (report_role_[index]) { - if (graph_->delayAnnotated(edge)) { - edge_annotated_count_[index]++; - if (from_logic_value_exists || to_logic_value_exists) - edge_constant_annotated_count_[index]++; - if (list_annotated_) - annotated_pins_.insert(from_pin); - } - else { - if (list_unannotated_) - unannotated_pins_.insert(from_pin); - } + if (delayAnnotated(edge)) { + edge_annotated_count_[index]++; + if (from_logic_value_exists || to_logic_value_exists) + edge_constant_annotated_count_[index]++; + if (report_annotated_) + annotated_pins_.insert(from_pin); + } + else { + if (report_unannotated_) + unannotated_pins_.insert(from_pin); + } } } findPeriodCount(from_pin); } } +bool +ReportAnnotated::delayAnnotated(Edge *edge) +{ + TimingArcSet *arc_set = edge->timingArcSet(); + for (TimingArc *arc : arc_set->arcs()) { + for (const MinMax *min_max : MinMax::range()) { + DcalcAPIndex ap_index = scene_->dcalcAnalysisPtIndex(min_max); + if (!graph_->arcDelayAnnotated(edge, arc, ap_index)) + return false; + } + } + return true; +} + int ReportAnnotated::roleIndex(const TimingRole *role, - const Pin *from_pin, - const Pin *to_pin) + const Pin *from_pin, + const Pin *to_pin) { if (role == TimingRole::wire()) { if (network_->isTopLevelPort(from_pin)) - return count_input_net; + return static_cast(CountIndex::count_input_net); else if (network_->isTopLevelPort(to_pin)) - return count_output_net; + return static_cast(CountIndex::count_output_net); else - return count_internal_net; + return static_cast(CountIndex::count_internal_net); } else if (role->sdfRole() == TimingRole::sdfIopath()) return count_delay; else { if (role->isTimingCheck() - && (role == TimingRole::latchSetup() - || role == TimingRole::latchHold())) + && (role == TimingRole::latchSetup() + || role == TimingRole::latchHold())) role = role->genericRole(); return role->index(); } @@ -394,17 +418,17 @@ ReportAnnotated::findPeriodCount(Pin *pin) if (report_role_[period_index]) { port->minPeriod(value, exists); if (exists) { - edge_count_[period_index]++; - graph_->periodCheckAnnotation(pin, ap_index, value, annotated); - if (annotated) { - edge_annotated_count_[period_index]++; - if (list_annotated_) - annotated_pins_.insert(pin); - } - else { - if (list_unannotated_) - unannotated_pins_.insert(pin); - } + edge_count_[period_index]++; + graph_->periodCheckAnnotation(pin, ap_index, value, annotated); + if (annotated) { + edge_annotated_count_[period_index]++; + if (report_annotated_) + annotated_pins_.insert(pin); + } + else { + if (report_unannotated_) + unannotated_pins_.insert(pin); + } } } } @@ -412,9 +436,9 @@ ReportAnnotated::findPeriodCount(Pin *pin) void ReportAnnotated::reportCount(const char *title, - int index, - int &total, - int &annotated_total) + int index, + int &total, + int &annotated_total) { if (report_role_[index]) { int count = edge_count_[index]; @@ -441,16 +465,16 @@ ReportAnnotated::reportCount(const char *title, void ReportAnnotated::reportArcs() { - if (list_annotated_) + if (report_annotated_) reportArcs("Annotated Arcs", true, annotated_pins_); - if (list_unannotated_) + if (report_unannotated_) reportArcs("Unannotated Arcs", false, unannotated_pins_); } void ReportAnnotated::reportArcs(const char *header, - bool report_annotated, - PinSet &pins) + bool report_annotated, + PinSet &pins) { report_->reportBlankLine(); report_->reportLineString(header); @@ -470,31 +494,31 @@ ReportAnnotated::reportArcs(const char *header, void ReportAnnotated::reportArcs(Vertex *vertex, - bool report_annotated, - int &i) + bool report_annotated, + int &i) { const Pin *from_pin = vertex->pin(); VertexOutEdgeIterator edge_iter(vertex, graph_); while (edge_iter.hasNext() - && (max_lines_ == 0 || i < max_lines_)) { + && (max_lines_ == 0 || i < max_lines_)) { Edge *edge = edge_iter.next(); const TimingRole *role = edge->role(); const Pin *to_pin = edge->to(graph_)->pin(); - if (graph_->delayAnnotated(edge) == report_annotated - && report_role_[roleIndex(role, from_pin, to_pin)]) { + if (delayAnnotated(edge) == report_annotated + && report_role_[roleIndex(role, from_pin, to_pin)]) { const char *role_name; if (role->isTimingCheck()) - role_name = role->to_string().c_str(); + role_name = role->to_string().c_str(); else if (role->isWire()) { - if (network_->isTopLevelPort(from_pin)) - role_name = "primary input net"; - else if (network_->isTopLevelPort(to_pin)) - role_name = "primary output net"; - else - role_name = "internal net"; + if (network_->isTopLevelPort(from_pin)) + role_name = "primary input net"; + else if (network_->isTopLevelPort(to_pin)) + role_name = "primary output net"; + else + role_name = "internal net"; } else - role_name = "delay"; + role_name = "delay"; const char *cond = edge->timingArcSet()->sdfCond(); report_->reportLine(" %-18s %s -> %s %s", role_name, @@ -516,19 +540,19 @@ ReportAnnotated::reportPeriodArcs(const Pin *pin, DcalcAPIndex ap_index = 0; int period_index = TimingRole::period()->index(); if (report_role_[period_index] - && (max_lines_ == 0 || i < max_lines_)) { + && (max_lines_ == 0 || i < max_lines_)) { float value; bool exists, annotated; port->minPeriod(value, exists); if (exists) { - edge_count_[period_index]++; - graph_->periodCheckAnnotation(pin, ap_index, value, annotated); - if (annotated == report_annotated) { - report_->reportLine(" %-18s %s", + edge_count_[period_index]++; + graph_->periodCheckAnnotation(pin, ap_index, value, annotated); + if (annotated == report_annotated) { + report_->reportLine(" %-18s %s", "period", network_->pathName(pin)); - i++; - } + i++; + } } } } diff --git a/sdf/ReportAnnotation.hh b/sdf/ReportAnnotation.hh index eb1b5ff5..1973fe74 100644 --- a/sdf/ReportAnnotation.hh +++ b/sdf/ReportAnnotation.hh @@ -27,30 +27,33 @@ namespace sta { class StaState; +class Scene; void -reportAnnotatedDelay(bool report_cells, - bool report_nets, - bool report_in_ports, - bool report_out_ports, - int max_lines, - bool list_annotated, - bool list_unannotated, - bool report_constant_arcs, - StaState *sta); +reportAnnotatedDelay(const Scene *scene, + bool report_cells, + bool report_nets, + bool report_in_ports, + bool report_out_ports, + int max_lines, + bool report_annotated, + bool report_unannotated, + bool report_constant_arcs, + StaState *sta); void -reportAnnotatedCheck(bool report_setup, - bool report_hold, - bool report_recovery, - bool report_removal, - bool report_nochange, - bool report_width, - bool report_period, - bool report_max_skew, - int max_lines, - bool list_annotated, - bool list_unannotated, - bool report_constant_arcs, - StaState *sta); +reportAnnotatedCheck(const Scene *scene, + bool report_setup, + bool report_hold, + bool report_recovery, + bool report_removal, + bool report_nochange, + bool report_width, + bool report_period, + bool report_max_skew, + int max_lines, + bool report_annotated, + bool report_unannotated, + bool report_constant_arcs, + StaState *sta); } // namespace diff --git a/sdf/Sdf.i b/sdf/Sdf.i index 8e35fd0e..395e0f7e 100644 --- a/sdf/Sdf.i +++ b/sdf/Sdf.i @@ -53,7 +53,7 @@ using sta::reportAnnotatedCheck; bool read_sdf_file(const char *filename, const char *path, - Corner *corner, + Scene *scene, bool unescaped_dividers, bool incremental_only, MinMaxAllNull *cond_use) @@ -63,70 +63,74 @@ read_sdf_file(const char *filename, sta->ensureGraph(); if (stringEq(path, "")) path = NULL; - bool success = readSdf(filename, path, corner, unescaped_dividers, incremental_only, - cond_use, sta); + bool success = readSdf(filename, path, scene, unescaped_dividers, + incremental_only, cond_use, sta); sta->search()->arrivalsInvalid(); return success; } void -report_annotated_delay_cmd(bool report_cells, - bool report_nets, - bool report_in_ports, - bool report_out_ports, - unsigned max_lines, - bool list_annotated, - bool list_not_annotated, - bool report_constant_arcs) +report_annotated_delay_cmd(const Scene *scene, + bool report_cells, + bool report_nets, + bool report_in_ports, + bool report_out_ports, + unsigned max_lines, + bool report_annotated, + bool report_not_annotated, + bool report_constant_arcs) { Sta *sta = Sta::sta(); sta->ensureLibLinked(); sta->ensureGraph(); - reportAnnotatedDelay(report_cells, report_nets, - report_in_ports, report_out_ports, - max_lines, list_annotated, list_not_annotated, - report_constant_arcs, sta); + reportAnnotatedDelay(scene, report_cells, report_nets, + report_in_ports, report_out_ports, + max_lines, report_annotated, + report_not_annotated, + report_constant_arcs, sta); } void -report_annotated_check_cmd(bool report_setup, - bool report_hold, - bool report_recovery, - bool report_removal, - bool report_nochange, - bool report_width, - bool report_period, - bool report_max_skew, - unsigned max_lines, - bool list_annotated, - bool list_not_annotated, - bool report_constant_arcs) +report_annotated_check_cmd(const Scene *scene, + bool report_setup, + bool report_hold, + bool report_recovery, + bool report_removal, + bool report_nochange, + bool report_width, + bool report_period, + bool report_max_skew, + unsigned max_lines, + bool report_annotated, + bool report_not_annotated, + bool report_constant_arcs) { Sta *sta = Sta::sta(); sta->ensureLibLinked(); sta->ensureGraph(); - reportAnnotatedCheck(report_setup, report_hold, - report_recovery, report_removal, - report_nochange, report_width, - report_period, report_max_skew, - max_lines, list_annotated, list_not_annotated, - report_constant_arcs, sta); + reportAnnotatedCheck(scene, report_setup, report_hold, + report_recovery, report_removal, + report_nochange, report_width, + report_period, report_max_skew, + max_lines, report_annotated, + report_not_annotated, + report_constant_arcs, sta); } void write_sdf_cmd(char *filename, - Corner *corner, - char divider, - bool include_typ, + Scene *scene, + char divider, + bool include_typ, int digits, - bool gzip, - bool no_timestamp, - bool no_version) + bool gzip, + bool no_timestamp, + bool no_version) { Sta *sta = Sta::sta(); sta->ensureLibLinked(); - sta->writeSdf(filename, corner, divider, include_typ, digits, gzip, - no_timestamp, no_version); + sta->writeSdf(filename, scene, divider, include_typ, digits, gzip, + no_timestamp, no_version); } %} // inline diff --git a/sdf/Sdf.tcl b/sdf/Sdf.tcl index 32ce32d3..ab6572c2 100644 --- a/sdf/Sdf.tcl +++ b/sdf/Sdf.tcl @@ -25,13 +25,13 @@ namespace eval sta { define_cmd_args "read_sdf" \ - {[-path path] [-corner corner]\ + {[-path path] [-scene scene]\ [-cond_use min|max|min_max]\ [-unescaped_dividers] filename} proc_redirect read_sdf { parse_key_args "read_sdf" args \ - keys {-path -corner -cond_use -analysis_type} \ + keys {-path -corner -scene -cond_use -analysis_type} \ flags {-unescaped_dividers -incremental_only} check_argc_eq1 "read_sdf" $args @@ -40,7 +40,7 @@ proc_redirect read_sdf { if [info exists keys(-path)] { set path $keys(-path) } - set corner [parse_corner keys] + set scene [parse_scene keys] set cond_use "NULL" if [info exists keys(-cond_use)] { @@ -50,31 +50,32 @@ proc_redirect read_sdf { set cond_use "NULL" } if { $cond_use == "min_max" \ - && { [operating_condition_analysis_type] == "single" }} { + && { [operating_condition_analysis_type] == "single" }} { sta_error 621 "-cond_use min_max cannot be used with analysis type single." } } set unescaped_dividers [info exists flags(-unescaped_dividers)] set incremental_only [info exists flags(-incremental_only)] - read_sdf_file $filename $path $corner $unescaped_dividers \ + read_sdf_file $filename $path $scene $unescaped_dividers \ $incremental_only $cond_use } ################################################################ define_cmd_args "report_annotated_delay" \ - {[-cell] [-net] [-from_in_ports] [-to_out_ports] [-max_lines lines]\ + {[-cell] [-net] [-from_in_ports] [-to_out_ports]\ + [-scene scene] [-max_lines lines]\ [-report_annotated] [-report_unannotated] [-constant_arcs]} proc_redirect report_annotated_delay { - parse_key_args "report_annotated_delay" args keys {-max_lines} \ + parse_key_args "report_annotated_delay" args keys {-scene -corner -max_lines} \ flags {-cell -net -from_in_ports -to_out_ports \ -report_annotated -report_unannotated -constant_arcs \ -list_not_annotated -list_annotated} if { [info exists flags(-cell)] || [info exists flags(-net)] \ - || [info exists flags(-from_in_ports)] \ - || [info exists flags(-to_out_ports)] } { + || [info exists flags(-from_in_ports)] \ + || [info exists flags(-to_out_ports)] } { set report_cells [info exists flags(-cell)] set report_nets [info exists flags(-net)] set report_in_nets [info exists flags(-from_in_ports)] @@ -86,6 +87,7 @@ proc_redirect report_annotated_delay { set report_out_nets 1 } + set scene [parse_scene keys] set max_lines 0 if { [info exists keys(-max_lines)] } { set max_lines $keys(-max_lines) @@ -105,26 +107,27 @@ proc_redirect report_annotated_delay { set report_unannotated 1 } - report_annotated_delay_cmd $report_cells $report_nets \ + report_annotated_delay_cmd $scene $report_cells $report_nets \ $report_in_nets $report_out_nets \ $max_lines $report_annotated $report_unannotated \ [info exists flags(-constant_arcs)] } define_cmd_args "report_annotated_check" \ - {[-setup] [-hold] [-recovery] [-removal] [-nochange] [-width] [-period]\ - [-max_skew] [-max_lines lines] [-report_annotated] [-report_unannotated]\ - [-constant_arcs]} + {[-setup] [-hold] [-recovery] [-removal] [-nochange]\ + [-width] [-period] [-max_skew]\ + [-scene scene] [-max_lines lines]\ + [-report_annotated] [-report_unannotated] [-constant_arcs]} proc_redirect report_annotated_check { - parse_key_args "report_annotated_check" args keys {-max_lines} \ + parse_key_args "report_annotated_check" args keys {-scene -max_lines} \ flags {-setup -hold -recovery -removal -nochange -width -period \ - -max_skew -report_annotated -report_unannotated -constant_arcs \ + -max_skew -report_annotated -report_unannotated -constant_arcs \ -list_annotated -list_not_annotated} if { [info exists flags(-setup)] || [info exists flags(-hold)] \ - || [info exists flags(-recovery)] || [info exists flags(-removal)] \ - || [info exists flags(-nochange)] || [info exists flags(-width)] \ - || [info exists flags(-period)] || [info exists flags(-max_skew)] } { + || [info exists flags(-recovery)] || [info exists flags(-removal)] \ + || [info exists flags(-nochange)] || [info exists flags(-width)] \ + || [info exists flags(-period)] || [info exists flags(-max_skew)] } { set report_setup [info exists flags(-setup)] set report_hold [info exists flags(-hold)] set report_recovery [info exists flags(-recovery)] @@ -144,6 +147,7 @@ proc_redirect report_annotated_check { set report_max_skew 1 } + set scene [parse_scene keys] set max_lines 0 if { [info exists keys(-max_lines)] } { set max_lines $keys(-max_lines) @@ -163,7 +167,7 @@ proc_redirect report_annotated_check { set report_unannotated 1 } - report_annotated_check_cmd $report_setup $report_hold \ + report_annotated_check_cmd $scene $report_setup $report_hold \ $report_recovery $report_removal $report_nochange \ $report_width $report_period $report_max_skew \ $max_lines $report_annotated $report_unannotated \ @@ -171,15 +175,15 @@ proc_redirect report_annotated_check { } define_cmd_args "write_sdf" \ - {[-corner corner] [-divider /|.] [-include_typ]\ + {[-scene scene] [-divider /|.] [-include_typ]\ [-digits digits] [-gzip] [-no_timestamp] [-no_version] filename} proc_redirect write_sdf { parse_key_args "write_sdf" args \ - keys {-corner -divider -digits -significant_digits} \ + keys {-corner -scene -divider -digits -significant_digits} \ flags {-include_typ -gzip -no_timestamp -no_version} check_argc_eq1 "write_sdf" $args - set corner [parse_corner keys] + set scene [parse_scene keys] set filename [file nativename [lindex $args 0]] set divider "/" if [info exists keys(-divider)] { @@ -198,7 +202,7 @@ proc_redirect write_sdf { set no_timestamp [info exists flags(-no_timestamp)] set no_version [info exists flags(-no_version)] set gzip [info exists flags(-gzip)] - write_sdf_cmd $filename $corner $divider $include_typ $digits $gzip \ + write_sdf_cmd $filename $scene $divider $include_typ $digits $gzip \ $no_timestamp $no_version } diff --git a/sdf/SdfReader.cc b/sdf/SdfReader.cc index 00279e49..8f695296 100644 --- a/sdf/SdfReader.cc +++ b/sdf/SdfReader.cc @@ -27,6 +27,7 @@ #include #include +#include "ContainerHelpers.hh" #include "Zlib.hh" #include "Error.hh" #include "Debug.hh" @@ -37,8 +38,7 @@ #include "Network.hh" #include "SdcNetwork.hh" #include "Graph.hh" -#include "Corner.hh" -#include "DcalcAnalysisPt.hh" +#include "Scene.hh" #include "Sdc.hh" #include "sdf/SdfReaderPvt.hh" #include "sdf/SdfScanner.hh" @@ -52,8 +52,8 @@ class SdfTriple { public: SdfTriple(float *min, - float *typ, - float *max); + float *typ, + float *max); ~SdfTriple(); float **values() { return values_; } bool hasValue() const; @@ -66,8 +66,8 @@ class SdfPortSpec { public: SdfPortSpec(const Transition *tr, - const std::string *port, - const std::string *cond); + const std::string *port, + const std::string *cond); ~SdfPortSpec(); const string *port() const { return port_; } const Transition *transition() const { return tr_; } @@ -82,32 +82,32 @@ private: bool readSdf(const char *filename, const char *path, - Corner *corner, + Scene *scene, bool unescaped_dividers, bool incremental_only, MinMaxAll *cond_use, StaState *sta) { - int arc_min_index = corner->findDcalcAnalysisPt(MinMax::min())->index(); - int arc_max_index = corner->findDcalcAnalysisPt(MinMax::max())->index(); + int arc_min_index = scene->dcalcAnalysisPtIndex(MinMax::min()); + int arc_max_index = scene->dcalcAnalysisPtIndex(MinMax::max()); SdfReader reader(filename, path, - arc_min_index, arc_max_index, - sta->sdc()->analysisType(), + arc_min_index, arc_max_index, + scene->sdc()->analysisType(), unescaped_dividers, incremental_only, - cond_use, sta); + cond_use, sta); bool success = reader.read(); return success; } SdfReader::SdfReader(const char *filename, - const char *path, + const char *path, int arc_min_index, - int arc_max_index, - AnalysisType analysis_type, - bool unescaped_dividers, - bool is_incremental_only, + int arc_max_index, + AnalysisType analysis_type, + bool unescaped_dividers, + bool is_incremental_only, MinMaxAll *cond_use, - StaState *sta) : + StaState *sta) : StaState(sta), filename_(filename), path_(path), @@ -125,7 +125,7 @@ SdfReader::SdfReader(const char *filename, cell_name_(nullptr), in_timing_check_(false), in_incremental_(false), - timescale_(1.0E-9F) // default units of ns + timescale_(1.0E-9F) // default units of ns { if (unescaped_dividers) network_ = makeSdcNetwork(network_); @@ -162,7 +162,7 @@ SdfReader::setDivider(char divider) void SdfReader::setTimescale(float multiplier, - const string *units) + const string *units) { if (multiplier == 1.0 || multiplier == 10.0 @@ -183,8 +183,8 @@ SdfReader::setTimescale(float multiplier, void SdfReader::interconnect(const string *from_pin_name, - const string *to_pin_name, - SdfTripleSeq *triples) + const string *to_pin_name, + SdfTripleSeq *triples) { // Ignore non-incremental annotations in incremental only mode. if (!(is_incremental_only_ && !in_incremental_)) { @@ -194,29 +194,29 @@ SdfReader::interconnect(const string *from_pin_name, // Assume the pins are non-hierarchical and on the same net. Edge *edge = findWireEdge(from_pin, to_pin); if (edge) - setEdgeDelays(edge, triples, "INTERCONNECT"); + setEdgeDelays(edge, triples, "INTERCONNECT"); else { - bool from_is_hier = network_->isHierarchical(from_pin); - bool to_is_hier = network_->isHierarchical(to_pin); - if (from_is_hier || to_is_hier) { - if (from_is_hier) - sdfError(182, "pin %s is a hierarchical pin.", + bool from_is_hier = network_->isHierarchical(from_pin); + bool to_is_hier = network_->isHierarchical(to_pin); + if (from_is_hier || to_is_hier) { + if (from_is_hier) + sdfError(182, "pin %s is a hierarchical pin.", from_pin_name->c_str()); - if (to_is_hier) - sdfError(183, "pin %s is a hierarchical pin.", + if (to_is_hier) + sdfError(183, "pin %s is a hierarchical pin.", to_pin_name->c_str()); - } - else - sdfWarn(184, "INTERCONNECT from %s to %s not found.", + } + else + sdfWarn(184, "INTERCONNECT from %s to %s not found.", from_pin_name->c_str(), to_pin_name->c_str()); } } else { if (from_pin == nullptr) - sdfWarn(185, "pin %s not found.", from_pin_name->c_str()); + sdfWarn(185, "pin %s not found.", from_pin_name->c_str()); if (to_pin == nullptr) - sdfWarn(186, "pin %s not found.", to_pin_name->c_str()); + sdfWarn(186, "pin %s not found.", to_pin_name->c_str()); } } delete from_pin_name; @@ -226,7 +226,7 @@ SdfReader::interconnect(const string *from_pin_name, void SdfReader::port(const string *to_pin_name, - SdfTripleSeq *triples) + SdfTripleSeq *triples) { // Ignore non-incremental annotations in incremental only mode. if (!(is_incremental_only_ && !in_incremental_)) { @@ -239,9 +239,9 @@ SdfReader::port(const string *to_pin_name, Vertex *vertex = graph_->pinLoadVertex(to_pin); VertexInEdgeIterator edge_iter(vertex, graph_); while (edge_iter.hasNext()) { - Edge *edge = edge_iter.next(); - if (edge->role()->sdfRole()->isWire()) - setEdgeDelays(edge, triples, "PORT"); + Edge *edge = edge_iter.next(); + if (edge->role()->sdfRole()->isWire()) + setEdgeDelays(edge, triples, "PORT"); } } } @@ -251,7 +251,7 @@ SdfReader::port(const string *to_pin_name, Edge * SdfReader::findWireEdge(Pin *from_pin, - Pin *to_pin) + Pin *to_pin) { Vertex *to_vertex, *to_vertex_bidirect_drvr; graph_->pinVertices(to_pin, to_vertex, to_vertex_bidirect_drvr); @@ -271,8 +271,8 @@ SdfReader::findWireEdge(Pin *from_pin, void SdfReader::setEdgeDelays(Edge *edge, - SdfTripleSeq *triples, - const char *sdf_cmd) + SdfTripleSeq *triples, + const char *sdf_cmd) { // Rise/fall triples. size_t triple_count = triples->size(); @@ -282,9 +282,9 @@ SdfReader::setEdgeDelays(Edge *edge, for (TimingArc *arc : arc_set->arcs()) { size_t triple_index; if (triple_count == 1) - triple_index = 0; + triple_index = 0; else - triple_index = arc->toEdge()->sdfTripleIndex(); + triple_index = arc->toEdge()->sdfTripleIndex(); SdfTriple *triple = (*triples)[triple_index]; setEdgeArcDelays(edge, arc, triple); } @@ -312,10 +312,10 @@ SdfReader::setInstance(const string *instance_name) else { instance_ = findInstance(instance_name); if (instance_) { - Cell *inst_cell = network_->cell(instance_); - const char *inst_cell_name = network_->name(inst_cell); - if (cell_name_ && !stringEq(inst_cell_name, cell_name_->c_str())) - sdfWarn(190, "instance %s cell %s does not match enclosing cell %s.", + Cell *inst_cell = network_->cell(instance_); + const char *inst_cell_name = network_->name(inst_cell); + if (cell_name_ && !stringEq(inst_cell_name, cell_name_->c_str())) + sdfWarn(190, "instance %s cell %s does not match enclosing cell %s.", instance_name->c_str(), inst_cell_name, cell_name_->c_str()); @@ -344,10 +344,10 @@ SdfReader::cellFinish() void SdfReader::iopath(SdfPortSpec *from_edge, - const string *to_port_name, - SdfTripleSeq *triples, - const string *cond, - bool condelse) + const string *to_port_name, + SdfTripleSeq *triples, + const string *cond, + bool condelse) { if (instance_) { const string *from_port_name = from_edge->port(); @@ -360,8 +360,8 @@ SdfReader::iopath(SdfPortSpec *from_edge, // Do not report an error if the pin is not found because the // instance may not have the pin. if (from_pin && to_pin) { - Vertex *to_vertex = graph_->pinDrvrVertex(to_pin); - if (to_vertex) { + Vertex *to_vertex = graph_->pinDrvrVertex(to_pin); + if (to_vertex) { size_t triple_count = triples->size(); bool matched = false; // Fanin < fanout, so search for driver from load. @@ -433,7 +433,7 @@ SdfReader::findPort(const Cell *cell, void SdfReader::timingCheck(const TimingRole *role, SdfPortSpec *data_edge, - SdfPortSpec *clk_edge, + SdfPortSpec *clk_edge, SdfTriple *triple) { if (instance_) { @@ -453,10 +453,10 @@ SdfReader::timingCheck(const TimingRole *role, void SdfReader::timingCheck1(const TimingRole *role, Port *data_port, - SdfPortSpec *data_edge, + SdfPortSpec *data_edge, Port *clk_port, - SdfPortSpec *clk_edge, - SdfTriple *triple) + SdfPortSpec *clk_edge, + SdfTriple *triple) { // Ignore non-incremental annotations in incremental only mode. if (!(is_incremental_only_ && !in_incremental_) @@ -507,12 +507,12 @@ SdfReader::timingCheck1(const TimingRole *role, // Return true if matched. bool SdfReader::annotateCheckEdges(Pin *data_pin, - SdfPortSpec *data_edge, - Pin *clk_pin, - SdfPortSpec *clk_edge, - const TimingRole *sdf_role, - SdfTriple *triple, - bool match_generic) + SdfPortSpec *data_edge, + Pin *clk_pin, + SdfPortSpec *clk_edge, + const TimingRole *sdf_role, + SdfTriple *triple, + bool match_generic) { bool matched = false; const string *cond_start = data_edge->cond(); @@ -529,21 +529,21 @@ SdfReader::annotateCheckEdges(Pin *data_pin, const char *lib_cond_start = arc_set->sdfCondStart(); const char *lib_cond_end = arc_set->sdfCondEnd(); bool cond_matches = condMatch(cond_start, lib_cond_start) - && condMatch(cond_end, lib_cond_end); + && condMatch(cond_end, lib_cond_end); if (((!match_generic && edge_role->sdfRole() == sdf_role) - || (match_generic - && edge_role->genericRole() == sdf_role->genericRole())) - && cond_matches) { - TimingArcSet *arc_set = edge->timingArcSet(); + || (match_generic + && edge_role->genericRole() == sdf_role->genericRole())) + && cond_matches) { + TimingArcSet *arc_set = edge->timingArcSet(); for (TimingArc *arc : arc_set->arcs()) { - if (((data_edge->transition() == Transition::riseFall()) - || (arc->toEdge() == data_edge->transition())) - && ((clk_edge->transition() == Transition::riseFall()) - || (arc->fromEdge() == clk_edge->transition()))) { - setEdgeArcDelays(edge, arc, triple); - } - } - matched = true; + if (((data_edge->transition() == Transition::riseFall()) + || (arc->toEdge() == data_edge->transition())) + && ((clk_edge->transition() == Transition::riseFall()) + || (arc->fromEdge() == clk_edge->transition()))) { + setEdgeArcDelays(edge, arc, triple); + } + } + matched = true; } } } @@ -552,7 +552,7 @@ SdfReader::annotateCheckEdges(Pin *data_pin, void SdfReader::timingCheckWidth(SdfPortSpec *edge, - SdfTriple *triple) + SdfTriple *triple) { // Ignore non-incremental annotations in incremental only mode. if (!(is_incremental_only_ && !in_incremental_) @@ -578,9 +578,9 @@ SdfReader::timingCheckWidth(SdfPortSpec *edge, void SdfReader::timingCheckSetupHold(SdfPortSpec *data_edge, - SdfPortSpec *clk_edge, - SdfTriple *setup_triple, - SdfTriple *hold_triple) + SdfPortSpec *clk_edge, + SdfTriple *setup_triple, + SdfTriple *hold_triple) { timingCheckSetupHold1(data_edge, clk_edge, setup_triple, hold_triple, TimingRole::setup(), TimingRole::hold()); @@ -588,9 +588,9 @@ SdfReader::timingCheckSetupHold(SdfPortSpec *data_edge, void SdfReader::timingCheckRecRem(SdfPortSpec *data_edge, - SdfPortSpec *clk_edge, - SdfTriple *rec_triple, - SdfTriple *rem_triple) + SdfPortSpec *clk_edge, + SdfTriple *rec_triple, + SdfTriple *rem_triple) { timingCheckSetupHold1(data_edge, clk_edge, rec_triple, rem_triple, TimingRole::recovery(), TimingRole::removal()); @@ -621,7 +621,7 @@ SdfReader::timingCheckSetupHold1(SdfPortSpec *data_edge, void SdfReader::timingCheckPeriod(SdfPortSpec *edge, - SdfTriple *triple) + SdfTriple *triple) { // Ignore non-incremental annotations in incremental only mode. if (!(is_incremental_only_ && !in_incremental_) @@ -633,19 +633,19 @@ SdfReader::timingCheckPeriod(SdfPortSpec *edge, // Edge specifier is ignored for period checks. Pin *pin = network_->findPin(instance_, port_name->c_str()); if (pin) { - float **values = triple->values(); - float *value_ptr = values[triple_min_index_]; - if (value_ptr) { - float value = *value_ptr; - graph_->setPeriodCheckAnnotation(pin, arc_delay_min_index_, value); - } - if (triple_max_index_ != null_index_) { - value_ptr = values[triple_max_index_]; - if (value_ptr) { - float value = *value_ptr; - graph_->setPeriodCheckAnnotation(pin, arc_delay_max_index_, value); - } - } + float **values = triple->values(); + float *value_ptr = values[triple_min_index_]; + if (value_ptr) { + float value = *value_ptr; + graph_->setPeriodCheckAnnotation(pin, arc_delay_min_index_, value); + } + if (triple_max_index_ != null_index_) { + value_ptr = values[triple_max_index_]; + if (value_ptr) { + float value = *value_ptr; + graph_->setPeriodCheckAnnotation(pin, arc_delay_max_index_, value); + } + } } } } @@ -655,9 +655,9 @@ SdfReader::timingCheckPeriod(SdfPortSpec *edge, void SdfReader::timingCheckNochange(SdfPortSpec *data_edge, - SdfPortSpec *clk_edge, - SdfTriple *before_triple, - SdfTriple *after_triple) + SdfPortSpec *clk_edge, + SdfTriple *before_triple, + SdfTriple *after_triple) { notSupported("NOCHANGE"); delete data_edge; @@ -684,7 +684,7 @@ SdfReader::device(SdfTripleSeq *triples) void SdfReader::device(const string *to_port_name, - SdfTripleSeq *triples) + SdfTripleSeq *triples) { // Ignore non-incremental annotations in incremental only mode. if (!(is_incremental_only_ && !in_incremental_) @@ -702,7 +702,7 @@ SdfReader::device(const string *to_port_name, void SdfReader::setDevicePinDelays(Pin *to_pin, - SdfTripleSeq *triples) + SdfTripleSeq *triples) { Vertex *vertex = graph_->pinDrvrVertex(to_pin); if (vertex) { @@ -717,8 +717,8 @@ SdfReader::setDevicePinDelays(Pin *to_pin, void SdfReader::setEdgeArcDelays(Edge *edge, - TimingArc *arc, - SdfTriple *triple) + TimingArc *arc, + SdfTriple *triple) { setEdgeArcDelays(edge, arc, triple, triple_min_index_, arc_delay_min_index_); setEdgeArcDelays(edge, arc, triple, triple_max_index_, arc_delay_max_index_); @@ -726,10 +726,10 @@ SdfReader::setEdgeArcDelays(Edge *edge, void SdfReader::setEdgeArcDelays(Edge *edge, - TimingArc *arc, - SdfTriple *triple, - int triple_index, - int arc_delay_index) + TimingArc *arc, + SdfTriple *triple, + int triple_index, + int arc_delay_index) { if (triple_index != null_index_) { float **values = triple->values(); @@ -737,9 +737,9 @@ SdfReader::setEdgeArcDelays(Edge *edge, if (value_ptr) { ArcDelay delay; if (in_incremental_) - delay = *value_ptr + graph_->arcDelay(edge, arc, arc_delay_index); + delay = *value_ptr + graph_->arcDelay(edge, arc, arc_delay_index); else - delay = *value_ptr; + delay = *value_ptr; graph_->setArcDelay(edge, arc, arc_delay_index, delay); graph_->setArcDelayAnnotated(edge, arc, arc_delay_index, true); edge->setDelayAnnotationIsIncremental(is_incremental_only_); @@ -749,8 +749,8 @@ SdfReader::setEdgeArcDelays(Edge *edge, void SdfReader::setEdgeArcDelaysCondUse(Edge *edge, - TimingArc *arc, - SdfTriple *triple) + TimingArc *arc, + SdfTriple *triple) { float **values = triple->values(); float *value_min = values[triple_min_index_]; @@ -769,18 +769,18 @@ SdfReader::setEdgeArcDelaysCondUse(Edge *edge, max = MinMax::max(); } setEdgeArcDelaysCondUse(edge, arc, value_min, triple_min_index_, - arc_delay_min_index_, min); + arc_delay_min_index_, min); setEdgeArcDelaysCondUse(edge, arc, value_max, triple_max_index_, - arc_delay_max_index_, max); + arc_delay_max_index_, max); } void SdfReader::setEdgeArcDelaysCondUse(Edge *edge, - TimingArc *arc, - float *value, - int triple_index, - int arc_delay_index, - const MinMax *min_max) + TimingArc *arc, + float *value, + int triple_index, + int arc_delay_index, + const MinMax *min_max) { if (value && triple_index != null_index_) { @@ -790,7 +790,7 @@ SdfReader::setEdgeArcDelaysCondUse(Edge *edge, else if (graph_->arcDelayAnnotated(edge, arc, arc_delay_index)) { ArcDelay prev_value = graph_->arcDelay(edge, arc, arc_delay_index); if (delayGreater(prev_value, delay, min_max, this)) - delay = prev_value; + delay = prev_value; } graph_->setArcDelay(edge, arc, arc_delay_index, delay); graph_->setArcDelayAnnotated(edge, arc, arc_delay_index, true); @@ -800,7 +800,7 @@ SdfReader::setEdgeArcDelaysCondUse(Edge *edge, bool SdfReader::condMatch(const string *sdf_cond, - const char *lib_cond) + const char *lib_cond) { // If the sdf is not conditional it matches any library condition. if (sdf_cond == nullptr) @@ -814,11 +814,11 @@ SdfReader::condMatch(const string *sdf_cond, ch1 = *c1++; ch2 = *c2++; while (ch1 && isspace(ch1)) - ch1 = *c1++; + ch1 = *c1++; while (ch2 && isspace(ch2)) - ch2 = *c2++; + ch2 = *c2++; if (ch1 != ch2) - return false; + return false; } while (ch1 && ch2); return (ch1 == '\0' && ch2 == '\0'); } @@ -828,8 +828,8 @@ SdfReader::condMatch(const string *sdf_cond, SdfPortSpec * SdfReader::makePortSpec(const Transition *tr, - const string *port, - const string *cond) + const string *port, + const string *cond) { return new SdfPortSpec(tr, port, cond); } @@ -866,11 +866,7 @@ SdfReader::makeTripleSeq() void SdfReader::deleteTripleSeq(SdfTripleSeq *triples) { - SdfTripleSeq::Iterator iter(triples); - while (iter.hasNext()) { - SdfTriple *triple = iter.next(); - delete triple; - } + deleteContents(triples); delete triples; } @@ -890,8 +886,8 @@ SdfReader::makeTriple(float value) SdfTriple * SdfReader::makeTriple(float *min, - float *typ, - float *max) + float *typ, + float *max) { if (min) *min *= timescale_; if (typ) *typ *= timescale_; @@ -930,18 +926,18 @@ SdfReader::unescaped(const string *token) char next_ch = (*token)[i + 1]; if (next_ch == divider_) { // Escaped divider. - // Translate sdf escape to network escape. - *unescaped += path_escape; - // Translate sdf divider to network divider. - *unescaped += path_divider; + // Translate sdf escape to network escape. + *unescaped += path_escape; + // Translate sdf divider to network divider. + *unescaped += path_divider; } else if (next_ch == '[' - || next_ch == ']' - || next_ch == escape_) { - // Escaped bus bracket or escape. - // Translate sdf escape to network escape. - *unescaped += path_escape; - *unescaped += next_ch; + || next_ch == ']' + || next_ch == escape_) { + // Escaped bus bracket or escape. + // Translate sdf escape to network escape. + *unescaped += path_escape; + *unescaped += next_ch; } else // Escaped non-divider character. @@ -1060,8 +1056,8 @@ SdfPortSpec::~SdfPortSpec() //////////////////////////////////////////////////////////////// SdfTriple::SdfTriple(float *min, - float *typ, - float *max) + float *typ, + float *max) { values_[0] = min; values_[1] = typ; diff --git a/sdf/SdfReader.hh b/sdf/SdfReader.hh index a2b4e064..fd17bb84 100644 --- a/sdf/SdfReader.hh +++ b/sdf/SdfReader.hh @@ -27,7 +27,7 @@ namespace sta { class MinMaxAll; -class Corner; +class Scene; class StaState; // If unescaped_dividers is true, path names in the SDF do not have to @@ -54,7 +54,7 @@ class StaState; bool readSdf(const char *filename, const char *path, - Corner *corner, + Scene *scene, bool unescaped_dividers, bool incremental_only, MinMaxAll *cond_use, diff --git a/sdf/SdfReaderPvt.hh b/sdf/SdfReaderPvt.hh index 06749391..52bc1cf3 100644 --- a/sdf/SdfReaderPvt.hh +++ b/sdf/SdfReaderPvt.hh @@ -24,7 +24,8 @@ #pragma once -#include "Vector.hh" +#include + #include "TimingRole.hh" #include "Transition.hh" #include "LibertyClass.hh" @@ -40,20 +41,20 @@ class SdfTriple; class SdfPortSpec; class SdfScanner; -typedef Vector SdfTripleSeq; +using SdfTripleSeq = std::vector; class SdfReader : public StaState { public: SdfReader(const char *filename, - const char *path, - int arc_min_index, - int arc_max_index, - AnalysisType analysis_type, - bool unescaped_dividers, - bool is_incremental_only, + const char *path, + int arc_min_index, + int arc_max_index, + AnalysisType analysis_type, + bool unescaped_dividers, + bool is_incremental_only, MinMaxAll *cond_use, - StaState *sta); + StaState *sta); ~SdfReader(); bool read(); @@ -61,53 +62,53 @@ public: void setTimescale(float multiplier, const std::string *units); void setPortDeviceDelay(Edge *edge, - SdfTripleSeq *triples, - bool from_trans); + SdfTripleSeq *triples, + bool from_trans); void setEdgeArcDelays(Edge *edge, - TimingArc *arc, - SdfTriple *triple); + TimingArc *arc, + SdfTriple *triple); void setEdgeArcDelays(Edge *edge, - TimingArc *arc, - SdfTriple *triple, - int triple_index, - int arc_delay_index); + TimingArc *arc, + SdfTriple *triple, + int triple_index, + int arc_delay_index); void setEdgeArcDelaysCondUse(Edge *edge, - TimingArc *arc, - SdfTriple *triple); + TimingArc *arc, + SdfTriple *triple); void setEdgeArcDelaysCondUse(Edge *edge, - TimingArc *arc, - float *value, - int triple_index, - int arc_delay_index, - const MinMax *min_max); + TimingArc *arc, + float *value, + int triple_index, + int arc_delay_index, + const MinMax *min_max); void setInstance(const std::string *instance_name); void setInstanceWildcard(); void cellFinish(); void setCell(const std::string *cell_name); void interconnect(const std::string *from_pin_name, - const std::string *to_pin_name, - SdfTripleSeq *triples); + const std::string *to_pin_name, + SdfTripleSeq *triples); void iopath(SdfPortSpec *from_edge, - const std::string *to_port_name, - SdfTripleSeq *triples, - const std::string *cond, - bool condelse); + const std::string *to_port_name, + SdfTripleSeq *triples, + const std::string *cond, + bool condelse); void timingCheck(const TimingRole *role, - SdfPortSpec *data_edge, - SdfPortSpec *clk_edge, - SdfTriple *triple); + SdfPortSpec *data_edge, + SdfPortSpec *clk_edge, + SdfTriple *triple); void timingCheckWidth(SdfPortSpec *edge, - SdfTriple *triple); + SdfTriple *triple); void timingCheckPeriod(SdfPortSpec *edge, - SdfTriple *triple); + SdfTriple *triple); void timingCheckSetupHold(SdfPortSpec *data_edge, - SdfPortSpec *clk_edge, - SdfTriple *setup_triple, - SdfTriple *hold_triple); + SdfPortSpec *clk_edge, + SdfTriple *setup_triple, + SdfTriple *hold_triple); void timingCheckRecRem(SdfPortSpec *data_edge, - SdfPortSpec *clk_edge, - SdfTriple *rec_triple, - SdfTriple *rem_triple); + SdfPortSpec *clk_edge, + SdfTriple *rec_triple, + SdfTriple *rem_triple); void timingCheckSetupHold1(SdfPortSpec *data_edge, SdfPortSpec *clk_edge, SdfTriple *setup_triple, @@ -115,26 +116,26 @@ public: const TimingRole *setup_role, const TimingRole *hold_role); void timingCheckNochange(SdfPortSpec *data_edge, - SdfPortSpec *clk_edge, - SdfTriple *before_triple, - SdfTriple *after_triple); + SdfPortSpec *clk_edge, + SdfTriple *before_triple, + SdfTriple *after_triple); void port(const std::string *to_pin_name, - SdfTripleSeq *triples); + SdfTripleSeq *triples); void device(SdfTripleSeq *triples); void device(const std::string *to_pin_name, - SdfTripleSeq *triples); + SdfTripleSeq *triples); SdfTriple *makeTriple(); SdfTriple *makeTriple(float value); SdfTriple *makeTriple(float *min, - float *typ, - float *max); + float *typ, + float *max); void deleteTriple(SdfTriple *triple); SdfTripleSeq *makeTripleSeq(); void deleteTripleSeq(SdfTripleSeq *triples); SdfPortSpec *makePortSpec(const Transition *tr, - const std::string *port, - const std::string *cond); + const std::string *port, + const std::string *cond); SdfPortSpec *makeCondPortSpec(const std::string *cond_port); std::string *unescaped(const std::string *token); std::string *makePath(const std::string *head, @@ -156,17 +157,17 @@ public: private: int readSdfFile1(Network *network, - Graph *graph, - const char *filename); + Graph *graph, + const char *filename); Edge *findCheckEdge(Pin *from_pin, - Pin *to_pin, - const TimingRole *sdf_role, - const std::string *cond_start, - const std::string *cond_end); + Pin *to_pin, + const TimingRole *sdf_role, + const std::string *cond_start, + const std::string *cond_end); Edge *findWireEdge(Pin *from_pin, - Pin *to_pin); + Pin *to_pin); bool condMatch(const std::string *sdf_cond, - const char *lib_cond); + const char *lib_cond); void timingCheck1(const TimingRole *role, Port *data_port, SdfPortSpec *data_edge, @@ -174,19 +175,19 @@ private: SdfPortSpec *clk_edge, SdfTriple *triple); bool annotateCheckEdges(Pin *data_pin, - SdfPortSpec *data_edge, - Pin *clk_pin, - SdfPortSpec *clk_edge, - const TimingRole *sdf_role, - SdfTriple *triple, - bool match_generic); + SdfPortSpec *data_edge, + Pin *clk_pin, + SdfPortSpec *clk_edge, + const TimingRole *sdf_role, + SdfTriple *triple, + bool match_generic); Pin *findPin(const std::string *name); Instance *findInstance(const std::string *name); void setEdgeDelays(Edge *edge, - SdfTripleSeq *triples, - const char *sdf_cmd); + SdfTripleSeq *triples, + const char *sdf_cmd); void setDevicePinDelays(Pin *to_pin, - SdfTripleSeq *triples); + SdfTripleSeq *triples); Port *findPort(const Cell *cell, const std::string *port_name); diff --git a/sdf/SdfWriter.cc b/sdf/SdfWriter.cc index 2c2bfa82..23b055cb 100644 --- a/sdf/SdfWriter.cc +++ b/sdf/SdfWriter.cc @@ -39,11 +39,9 @@ #include "MinMaxValues.hh" #include "Network.hh" #include "Graph.hh" -#include "DcalcAnalysisPt.hh" #include "GraphDelayCalc.hh" #include "StaState.hh" -#include "Corner.hh" -#include "PathAnalysisPt.hh" +#include "Scene.hh" namespace sta { @@ -55,18 +53,18 @@ public: SdfWriter(StaState *sta); ~SdfWriter(); void write(const char *filename, - const Corner *corner, - char sdf_divider, - bool include_typ, + const Scene *scene, + char sdf_divider, + bool include_typ, int digits, - bool gzip, - bool no_timestamp, - bool no_version); + bool gzip, + bool no_timestamp, + bool no_version); protected: void writeHeader(LibertyLibrary *default_lib, - bool no_timestamp, - bool no_version); + bool no_timestamp, + bool no_version); void writeTrailer(); void writeInterconnects(); void writeInstInterconnects(Instance *inst); @@ -76,33 +74,33 @@ protected: void writeInstHeader(const Instance *inst); void writeInstTrailer(); void writeIopaths(const Instance *inst, - bool &inst_header); + bool &inst_header); void writeIopathHeader(); void writeIopathTrailer(); void writeTimingChecks(const Instance *inst, - bool &inst_header); + bool &inst_header); void ensureTimingCheckheaders(bool &check_header, - const Instance *inst, - bool &inst_header); + const Instance *inst, + bool &inst_header); void writeCheck(Edge *edge, - const char *sdf_check); + const char *sdf_check); void writeCheck(Edge *edge, - TimingArc *arc, - const char *sdf_check, - bool use_data_edge, - bool use_clk_edge); + TimingArc *arc, + const char *sdf_check, + bool use_data_edge, + bool use_clk_edge); void writeEdgeCheck(Edge *edge, - const char *sdf_check, - int clk_rf_index, - TimingArc *arcs[RiseFall::index_count][RiseFall::index_count]); + const char *sdf_check, + int clk_rf_index, + TimingArc *arcs[RiseFall::index_count][RiseFall::index_count]); void writeTimingCheckHeader(); void writeTimingCheckTrailer(); void writeWidthCheck(const Pin *pin, - const RiseFall *hi_low, - float min_width, - float max_width); + const RiseFall *hi_low, + float min_width, + float max_width); void writePeriodCheck(const Pin *pin, - float min_period); + float min_period); const char *sdfEdge(const Transition *tr); void writeArcDelays(Edge *edge); void writeSdfTriple(RiseFallMinMax &delays, @@ -125,25 +123,25 @@ private: char *delay_format_; gzFile stream_; - const Corner *corner_; + const Scene *scene_; int arc_delay_min_index_; int arc_delay_max_index_; }; void writeSdf(const char *filename, - const Corner *corner, - char sdf_divider, + const Scene *scene, + char sdf_divider, bool include_typ, - int digits, - bool gzip, - bool no_timestamp, - bool no_version, - StaState *sta) + int digits, + bool gzip, + bool no_timestamp, + bool no_version, + StaState *sta) { SdfWriter writer(sta); - writer.write(filename, corner, sdf_divider, include_typ, digits, gzip, - no_timestamp, no_version); + writer.write(filename, scene, sdf_divider, include_typ, digits, gzip, + no_timestamp, no_version); } SdfWriter::SdfWriter(StaState *sta) : @@ -161,13 +159,13 @@ SdfWriter::~SdfWriter() void SdfWriter::write(const char *filename, - const Corner *corner, - char sdf_divider, + const Scene *scene, + char sdf_divider, bool include_typ, - int digits, - bool gzip, - bool no_timestamp, - bool no_version) + int digits, + bool gzip, + bool no_timestamp, + bool no_version) { sdf_divider_ = sdf_divider; include_typ_ = include_typ; @@ -177,17 +175,9 @@ SdfWriter::write(const char *filename, LibertyLibrary *default_lib = network_->defaultLibertyLibrary(); timescale_ = default_lib->units()->timeUnit()->scale(); - corner_ = corner; - const MinMax *min_max; - const DcalcAnalysisPt *dcalc_ap; - - min_max = MinMax::min(); - dcalc_ap = corner_->findDcalcAnalysisPt(min_max); - arc_delay_min_index_ = dcalc_ap->index(); - - min_max = MinMax::max(); - dcalc_ap = corner_->findDcalcAnalysisPt(min_max); - arc_delay_max_index_ = dcalc_ap->index(); + scene_ = scene; + arc_delay_min_index_ = scene->dcalcAnalysisPtIndex(MinMax::min()); + arc_delay_max_index_ = scene->dcalcAnalysisPtIndex(MinMax::max()); stream_ = gzopen(filename, gzip ? "wb" : "wT"); if (stream_ == nullptr) @@ -204,13 +194,13 @@ SdfWriter::write(const char *filename, void SdfWriter::writeHeader(LibertyLibrary *default_lib, - bool no_timestamp, - bool no_version) + bool no_timestamp, + bool no_version) { gzprintf(stream_, "(DELAYFILE\n"); gzprintf(stream_, " (SDFVERSION \"3.0\")\n"); gzprintf(stream_, " (DESIGN \"%s\")\n", - network_->cellName(network_->topInstance())); + network_->cellName(network_->topInstance())); if (!no_timestamp) { time_t now; @@ -228,11 +218,11 @@ SdfWriter::writeHeader(LibertyLibrary *default_lib, gzprintf(stream_, " (DIVIDER %c)\n", sdf_divider_); LibertyLibrary *lib_min = default_lib; - const LibertySeq &libs_min = corner_->libertyLibraries(MinMax::min()); + const LibertySeq &libs_min = scene_->libertyLibraries(MinMax::min()); if (!libs_min.empty()) lib_min = libs_min[0]; LibertyLibrary *lib_max = default_lib; - const LibertySeq &libs_max = corner_->libertyLibraries(MinMax::max()); + const LibertySeq &libs_max = scene_->libertyLibraries(MinMax::max()); if (!libs_max.empty()) lib_max = libs_max[0]; @@ -284,7 +274,7 @@ SdfWriter::writeInterconnects() { gzprintf(stream_, " (CELL\n"); gzprintf(stream_, " (CELLTYPE \"%s\")\n", - network_->cellName(network_->topInstance())); + network_->cellName(network_->topInstance())); gzprintf(stream_, " (INSTANCE)\n"); gzprintf(stream_, " (DELAY\n"); gzprintf(stream_, " (ABSOLUTE\n"); @@ -369,7 +359,7 @@ SdfWriter::writeInstTrailer() void SdfWriter::writeIopaths(const Instance *inst, - bool &inst_header) + bool &inst_header) { bool iopath_header = false; InstancePinIterator *pin_iter = network_->pinIterator(inst); @@ -379,39 +369,39 @@ SdfWriter::writeIopaths(const Instance *inst, Vertex *from_vertex = graph_->pinLoadVertex(from_pin); VertexOutEdgeIterator edge_iter(from_vertex, graph_); while (edge_iter.hasNext()) { - Edge *edge = edge_iter.next(); - const TimingRole *role = edge->role(); - if (role == TimingRole::combinational() - || role == TimingRole::tristateEnable() - || role == TimingRole::regClkToQ() - || role == TimingRole::regSetClr() - || role == TimingRole::latchEnToQ() - || role == TimingRole::latchDtoQ()) { - Vertex *to_vertex = edge->to(graph_); - Pin *to_pin = to_vertex->pin(); - if (!inst_header) { - writeInstHeader(inst); - inst_header = true; - } - if (!iopath_header) { - writeIopathHeader(); - iopath_header = true; - } - const char *sdf_cond = edge->timingArcSet()->sdfCond(); - if (sdf_cond) { - gzprintf(stream_, " (COND %s\n", sdf_cond); - gzprintf(stream_, " "); - } - string from_pin_name = sdfPortName(from_pin); - string to_pin_name = sdfPortName(to_pin); + Edge *edge = edge_iter.next(); + const TimingRole *role = edge->role(); + if (role == TimingRole::combinational() + || role == TimingRole::tristateEnable() + || role == TimingRole::regClkToQ() + || role == TimingRole::regSetClr() + || role == TimingRole::latchEnToQ() + || role == TimingRole::latchDtoQ()) { + Vertex *to_vertex = edge->to(graph_); + Pin *to_pin = to_vertex->pin(); + if (!inst_header) { + writeInstHeader(inst); + inst_header = true; + } + if (!iopath_header) { + writeIopathHeader(); + iopath_header = true; + } + const char *sdf_cond = edge->timingArcSet()->sdfCond(); + if (sdf_cond) { + gzprintf(stream_, " (COND %s\n", sdf_cond); + gzprintf(stream_, " "); + } + string from_pin_name = sdfPortName(from_pin); + string to_pin_name = sdfPortName(to_pin); gzprintf(stream_, " (IOPATH %s %s ", - from_pin_name.c_str(), - to_pin_name.c_str()); - writeArcDelays(edge); - if (sdf_cond) - gzprintf(stream_, ")"); - gzprintf(stream_, ")\n"); - } + from_pin_name.c_str(), + to_pin_name.c_str()); + writeArcDelays(edge); + if (sdf_cond) + gzprintf(stream_, ")"); + gzprintf(stream_, ")\n"); + } } } } @@ -455,9 +445,9 @@ SdfWriter::writeArcDelays(Edge *edge) writeSdfTriple(delays, RiseFall::rise()); // Merge rise/fall values if they are the same. if (!(fuzzyEqual(delays.value(RiseFall::rise(), MinMax::min()), - delays.value(RiseFall::fall(), MinMax::min())) - && fuzzyEqual(delays.value(RiseFall::rise(), MinMax::max()), - delays.value(RiseFall::fall(),MinMax::max())))) { + delays.value(RiseFall::fall(), MinMax::min())) + && fuzzyEqual(delays.value(RiseFall::rise(), MinMax::max()), + delays.value(RiseFall::fall(),MinMax::max())))) { gzprintf(stream_, " "); writeSdfTriple(delays, RiseFall::fall()); } @@ -506,7 +496,7 @@ SdfWriter::writeSdfDelay(double delay) void SdfWriter::writeTimingChecks(const Instance *inst, - bool &inst_header) + bool &inst_header) { bool check_header = false; @@ -517,40 +507,40 @@ SdfWriter::writeTimingChecks(const Instance *inst, if (vertex) { VertexOutEdgeIterator edge_iter(vertex, graph_); while (edge_iter.hasNext()) { - Edge *edge = edge_iter.next(); - const TimingRole *role = edge->role(); - const char *sdf_check = nullptr; - if (role == TimingRole::setup()) - sdf_check = "SETUP"; - else if (role == TimingRole::hold()) - sdf_check = "HOLD"; - else if (role == TimingRole::recovery()) - sdf_check = "RECOVERY"; - else if (role == TimingRole::removal()) - sdf_check = "REMOVAL"; - if (sdf_check) { - ensureTimingCheckheaders(check_header, inst, inst_header); - writeCheck(edge, sdf_check); - } + Edge *edge = edge_iter.next(); + const TimingRole *role = edge->role(); + const char *sdf_check = nullptr; + if (role == TimingRole::setup()) + sdf_check = "SETUP"; + else if (role == TimingRole::hold()) + sdf_check = "HOLD"; + else if (role == TimingRole::recovery()) + sdf_check = "RECOVERY"; + else if (role == TimingRole::removal()) + sdf_check = "REMOVAL"; + if (sdf_check) { + ensureTimingCheckheaders(check_header, inst, inst_header); + writeCheck(edge, sdf_check); + } } for (auto hi_low : RiseFall::range()) { - float min_width, max_width; - Edge *edge; - TimingArc *arc; - graph_->minPulseWidthArc(vertex, hi_low, edge, arc); - if (edge) { - min_width = delayAsFloat(graph_->arcDelay(edge, arc, arc_delay_min_index_)); - max_width = delayAsFloat(graph_->arcDelay(edge, arc, arc_delay_max_index_)); - ensureTimingCheckheaders(check_header, inst, inst_header); - writeWidthCheck(pin, hi_low, min_width, max_width); - } + float min_width, max_width; + Edge *edge; + TimingArc *arc; + graph_->minPulseWidthArc(vertex, hi_low, edge, arc); + if (edge) { + min_width = delayAsFloat(graph_->arcDelay(edge, arc, arc_delay_min_index_)); + max_width = delayAsFloat(graph_->arcDelay(edge, arc, arc_delay_max_index_)); + ensureTimingCheckheaders(check_header, inst, inst_header); + writeWidthCheck(pin, hi_low, min_width, max_width); + } } float min_period; bool exists; - graph_delay_calc_->minPeriod(pin, corner_, min_period, exists); + graph_delay_calc_->minPeriod(pin, scene_, min_period, exists); if (exists) { - ensureTimingCheckheaders(check_header, inst, inst_header); - writePeriodCheck(pin, min_period); + ensureTimingCheckheaders(check_header, inst, inst_header); + writePeriodCheck(pin, min_period); } } } @@ -562,8 +552,8 @@ SdfWriter::writeTimingChecks(const Instance *inst, void SdfWriter::ensureTimingCheckheaders(bool &check_header, - const Instance *inst, - bool &inst_header) + const Instance *inst, + bool &inst_header) { if (!inst_header) { writeInstHeader(inst); @@ -589,7 +579,7 @@ SdfWriter::writeTimingCheckTrailer() void SdfWriter::writeCheck(Edge *edge, - const char *sdf_check) + const char *sdf_check) { TimingArcSet *arc_set = edge->timingArcSet(); // Examine the arcs to see if the check requires clk or data edge specifiers. @@ -605,7 +595,7 @@ SdfWriter::writeCheck(Edge *edge, && arcs[RiseFall::fallIndex()][RiseFall::fallIndex()] == nullptr) writeEdgeCheck(edge, sdf_check, RiseFall::riseIndex(), arcs); else if (arcs[RiseFall::riseIndex()][RiseFall::riseIndex()] == nullptr - && arcs[RiseFall::riseIndex()][RiseFall::fallIndex()] == nullptr) + && arcs[RiseFall::riseIndex()][RiseFall::fallIndex()] == nullptr) writeEdgeCheck(edge, sdf_check, RiseFall::fallIndex(), arcs); else { // No special case; write all the checks with data and clock edge specifiers. @@ -616,9 +606,9 @@ SdfWriter::writeCheck(Edge *edge, void SdfWriter::writeEdgeCheck(Edge *edge, - const char *sdf_check, - int clk_rf_index, - TimingArc *arcs[RiseFall::index_count][RiseFall::index_count]) + const char *sdf_check, + int clk_rf_index, + TimingArc *arcs[RiseFall::index_count][RiseFall::index_count]) { // SDF requires edge specifiers on the data port to define separate // rise/fall check values. @@ -629,36 +619,36 @@ SdfWriter::writeEdgeCheck(Edge *edge, && arcs[clk_rf_index][RiseFall::riseIndex()] && arcs[clk_rf_index][RiseFall::fallIndex()] && delayEqual(graph_->arcDelay(edge, - arcs[clk_rf_index][RiseFall::riseIndex()], - arc_delay_min_index_), - graph_->arcDelay(edge, - arcs[clk_rf_index][RiseFall::fallIndex()], - arc_delay_min_index_)) + arcs[clk_rf_index][RiseFall::riseIndex()], + arc_delay_min_index_), + graph_->arcDelay(edge, + arcs[clk_rf_index][RiseFall::fallIndex()], + arc_delay_min_index_)) && delayEqual(graph_->arcDelay(edge, - arcs[clk_rf_index][RiseFall::riseIndex()], - arc_delay_max_index_), - graph_->arcDelay(edge, - arcs[clk_rf_index][RiseFall::fallIndex()], - arc_delay_max_index_))) + arcs[clk_rf_index][RiseFall::riseIndex()], + arc_delay_max_index_), + graph_->arcDelay(edge, + arcs[clk_rf_index][RiseFall::fallIndex()], + arc_delay_max_index_))) // Rise/fall margins are the same, so no data edge specifier is required. writeCheck(edge, arcs[clk_rf_index][RiseFall::riseIndex()], - sdf_check, false, true); + sdf_check, false, true); else { if (arcs[clk_rf_index][RiseFall::riseIndex()]) writeCheck(edge, arcs[clk_rf_index][RiseFall::riseIndex()], - sdf_check, true, true); + sdf_check, true, true); if (arcs[clk_rf_index][RiseFall::fallIndex()]) writeCheck(edge, arcs[clk_rf_index][RiseFall::fallIndex()], - sdf_check, true, true); + sdf_check, true, true); } } void SdfWriter::writeCheck(Edge *edge, - TimingArc *arc, - const char *sdf_check, - bool use_data_edge, - bool use_clk_edge) + TimingArc *arc, + const char *sdf_check, + bool use_data_edge, + bool use_clk_edge) { TimingArcSet *arc_set = edge->timingArcSet(); Pin *from_pin = edge->from(graph_)->pin(); @@ -674,8 +664,8 @@ SdfWriter::writeCheck(Edge *edge, string to_pin_name = sdfPortName(to_pin); if (use_data_edge) { gzprintf(stream_, "(%s %s)", - sdfEdge(arc->toEdge()), - to_pin_name.c_str()); + sdfEdge(arc->toEdge()), + to_pin_name.c_str()); } else gzprintf(stream_, "%s", to_pin_name.c_str()); @@ -691,8 +681,8 @@ SdfWriter::writeCheck(Edge *edge, string from_pin_name = sdfPortName(from_pin); if (use_clk_edge) gzprintf(stream_, "(%s %s)", - sdfEdge(arc->fromEdge()), - from_pin_name.c_str()); + sdfEdge(arc->fromEdge()), + from_pin_name.c_str()); else gzprintf(stream_, "%s", from_pin_name.c_str()); @@ -710,21 +700,21 @@ SdfWriter::writeCheck(Edge *edge, void SdfWriter::writeWidthCheck(const Pin *pin, - const RiseFall *hi_low, - float min_width, - float max_width) + const RiseFall *hi_low, + float min_width, + float max_width) { string pin_name = sdfPortName(pin); gzprintf(stream_, " (WIDTH (%s %s) ", - sdfEdge(hi_low->asTransition()), - pin_name.c_str()); + sdfEdge(hi_low->asTransition()), + pin_name.c_str()); writeSdfTriple(min_width, max_width); gzprintf(stream_, ")\n"); } void SdfWriter::writePeriodCheck(const Pin *pin, - float min_period) + float min_period) { string pin_name = sdfPortName(pin); gzprintf(stream_, " (PERIOD %s ", pin_name.c_str()); @@ -766,7 +756,6 @@ SdfWriter::sdfPathName(const Instance *instance) { InstanceSeq inst_path; network_->path(instance, inst_path); - InstanceSeq::Iterator path_iter1(inst_path); string path_name; while (!inst_path.empty()) { const Instance *inst = inst_path.back(); @@ -791,8 +780,8 @@ SdfWriter::sdfName(const Instance *inst) // Ignore sta escapes. if (ch != network_escape_) { if (!(isalnum(ch) || ch == '_')) - // Insert escape. - sdf_name += sdf_escape_; + // Insert escape. + sdf_name += sdf_escape_; sdf_name += ch; } p++; diff --git a/sdf/SdfWriter.hh b/sdf/SdfWriter.hh index 382faa71..3c992366 100644 --- a/sdf/SdfWriter.hh +++ b/sdf/SdfWriter.hh @@ -27,17 +27,17 @@ namespace sta { class StaState; -class Corner; +class Scene; void writeSdf(const char *filename, - const Corner *corner, - char divider, + const Scene *scene, + char divider, bool include_typ, - int digits, - bool gzip, - bool no_timestamp, - bool no_version, - StaState *sta); + int digits, + bool gzip, + bool no_timestamp, + bool no_version, + StaState *sta); } // namespace diff --git a/search/Bdd.cc b/search/Bdd.cc index 0845c24c..89d77655 100644 --- a/search/Bdd.cc +++ b/search/Bdd.cc @@ -49,17 +49,17 @@ Bdd::funcBdd(const FuncExpr *expr) DdNode *right = nullptr; DdNode *result = nullptr; switch (expr->op()) { - case FuncExpr::op_port: { + case FuncExpr::Op::port: { LibertyPort *port = expr->port(); result = ensureNode(port); break; } - case FuncExpr::op_not: + case FuncExpr::Op::not_: left = funcBdd(expr->left()); if (left) result = Cudd_Not(left); break; - case FuncExpr::op_or: + case FuncExpr::Op::or_: left = funcBdd(expr->left()); right = funcBdd(expr->right()); if (left && right) @@ -69,7 +69,7 @@ Bdd::funcBdd(const FuncExpr *expr) else if (right) result = right; break; - case FuncExpr::op_and: + case FuncExpr::Op::and_: left = funcBdd(expr->left()); right = funcBdd(expr->right()); if (left && right) @@ -79,7 +79,7 @@ Bdd::funcBdd(const FuncExpr *expr) else if (right) result = right; break; - case FuncExpr::op_xor: + case FuncExpr::Op::xor_: left = funcBdd(expr->left()); right = funcBdd(expr->right()); if (left && right) @@ -89,10 +89,10 @@ Bdd::funcBdd(const FuncExpr *expr) else if (right) result = right; break; - case FuncExpr::op_one: + case FuncExpr::Op::one: result = Cudd_ReadOne(cudd_mgr_); break; - case FuncExpr::op_zero: + case FuncExpr::Op::zero: result = Cudd_ReadLogicZero(cudd_mgr_); break; default: diff --git a/search/Bfs.cc b/search/Bfs.cc index ebea9fdb..5ea3d470 100644 --- a/search/Bfs.cc +++ b/search/Bfs.cc @@ -122,21 +122,14 @@ BfsIterator::empty() const void BfsIterator::enqueueAdjacentVertices(Vertex *vertex) { - enqueueAdjacentVertices(vertex, search_pred_, level_max_); + enqueueAdjacentVertices(vertex, search_pred_); } void BfsIterator::enqueueAdjacentVertices(Vertex *vertex, - SearchPred *search_pred) + const Mode *mode) { - enqueueAdjacentVertices(vertex, search_pred, level_max_); -} - -void -BfsIterator::enqueueAdjacentVertices(Vertex *vertex, - Level to_level) -{ - enqueueAdjacentVertices(vertex, search_pred_, to_level); + enqueueAdjacentVertices(vertex, search_pred_, mode); } int @@ -395,22 +388,37 @@ BfsFwdIterator::levelLess(Level level1, void BfsFwdIterator::enqueueAdjacentVertices(Vertex *vertex, - SearchPred *search_pred, - Level to_level) + SearchPred *search_pred) { if (search_pred->searchFrom(vertex)) { VertexOutEdgeIterator edge_iter(vertex, graph_); while (edge_iter.hasNext()) { Edge *edge = edge_iter.next(); Vertex *to_vertex = edge->to(graph_); - if (to_vertex->level() <= to_level - && search_pred->searchThru(edge) + if (search_pred->searchThru(edge) && search_pred->searchTo(to_vertex)) enqueue(to_vertex); } } } +void +BfsFwdIterator::enqueueAdjacentVertices(Vertex *vertex, + SearchPred *search_pred, + const Mode *mode) +{ + if (search_pred->searchFrom(vertex, mode)) { + VertexOutEdgeIterator edge_iter(vertex, graph_); + while (edge_iter.hasNext()) { + Edge *edge = edge_iter.next(); + Vertex *to_vertex = edge->to(graph_); + if (search_pred->searchThru(edge, mode) + && search_pred->searchTo(to_vertex, mode)) + enqueue(to_vertex); + } + } +} + //////////////////////////////////////////////////////////////// BfsBkwdIterator::BfsBkwdIterator(BfsIndex bfs_index, @@ -449,20 +457,35 @@ BfsBkwdIterator::levelLess(Level level1, void BfsBkwdIterator::enqueueAdjacentVertices(Vertex *vertex, - SearchPred *search_pred, - Level to_level) + SearchPred *search_pred) { if (search_pred->searchTo(vertex)) { VertexInEdgeIterator edge_iter(vertex, graph_); while (edge_iter.hasNext()) { Edge *edge = edge_iter.next(); Vertex *from_vertex = edge->from(graph_); - if (from_vertex->level() >= to_level - && search_pred->searchFrom(from_vertex) + if (search_pred->searchFrom(from_vertex) && search_pred->searchThru(edge)) enqueue(from_vertex); } } } +void +BfsBkwdIterator::enqueueAdjacentVertices(Vertex *vertex, + SearchPred *search_pred, + const Mode *mode) +{ + if (search_pred->searchTo(vertex, mode)) { + VertexInEdgeIterator edge_iter(vertex, graph_); + while (edge_iter.hasNext()) { + Edge *edge = edge_iter.next(); + Vertex *from_vertex = edge->from(graph_); + if (search_pred->searchFrom(from_vertex, mode) + && search_pred->searchThru(edge, mode)) + enqueue(from_vertex); + } + } +} + } // namespace diff --git a/search/CheckCapacitanceLimits.cc b/search/CheckCapacitanceLimits.cc deleted file mode 100644 index 391ecda1..00000000 --- a/search/CheckCapacitanceLimits.cc +++ /dev/null @@ -1,356 +0,0 @@ -// OpenSTA, Static Timing Analyzer -// Copyright (c) 2025, Parallax Software, Inc. -// -// This program is free software: you can redistribute it and/or modify -// it under the terms of the GNU General Public License as published by -// the Free Software Foundation, either version 3 of the License, or -// (at your option) any later version. -// -// This program is distributed in the hope that it will be useful, -// but WITHOUT ANY WARRANTY; without even the implied warranty of -// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -// GNU General Public License for more details. -// -// You should have received a copy of the GNU General Public License -// along with this program. If not, see . -// -// The origin of this software must not be misrepresented; you must not -// claim that you wrote the original software. -// -// Altered source versions must be plainly marked as such, and must not be -// misrepresented as being the original software. -// -// This notice may not be removed or altered from any source distribution. - -#include "CheckCapacitanceLimits.hh" - -#include "Fuzzy.hh" -#include "Liberty.hh" -#include "Network.hh" -#include "Sdc.hh" -#include "InputDrive.hh" -#include "DcalcAnalysisPt.hh" -#include "GraphDelayCalc.hh" -#include "StaState.hh" -#include "Corner.hh" -#include "PortDirection.hh" -#include "Sim.hh" -#include "Graph.hh" -#include "GraphDelayCalc.hh" - -namespace sta { - -class PinCapacitanceLimitSlackLess -{ -public: - PinCapacitanceLimitSlackLess(const Corner *corner, - const MinMax *min_max, - CheckCapacitanceLimits *check_capacitance_limit, - const StaState *sta); - bool operator()(const Pin *pin1, - const Pin *pin2) const; - -private: - const Corner *corner_; - const MinMax *min_max_; - CheckCapacitanceLimits *check_capacitance_limit_; - const StaState *sta_; - -}; - -PinCapacitanceLimitSlackLess::PinCapacitanceLimitSlackLess(const Corner *corner, - const MinMax *min_max, - CheckCapacitanceLimits *check_capacitance_limit, - const StaState *sta) : - corner_(corner), - min_max_(min_max), - check_capacitance_limit_(check_capacitance_limit), - sta_(sta) -{ -} - -bool -PinCapacitanceLimitSlackLess::operator()(const Pin *pin1, - const Pin *pin2) const -{ - const Corner *corner1, *corner2; - const RiseFall *rf1, *rf2; - float capacitance1, capacitance2; - float limit1, limit2, slack1, slack2; - check_capacitance_limit_->checkCapacitance(pin1, corner_, min_max_, - corner1, rf1, capacitance1, - limit1, slack1); - check_capacitance_limit_->checkCapacitance(pin2, corner_, min_max_, - corner2, rf2, capacitance2, - limit2, slack2); - return fuzzyLess(slack1, slack2) - || (fuzzyEqual(slack1, slack2) - // Break ties for the sake of regression stability. - && sta_->network()->pinLess(pin1, pin2)); -} - -//////////////////////////////////////////////////////////////// - -CheckCapacitanceLimits::CheckCapacitanceLimits(const Sta *sta) : - sta_(sta) -{ -} - -void -CheckCapacitanceLimits::checkCapacitance(const Pin *pin, - const Corner *corner, - const MinMax *min_max, - // Return values. - const Corner *&corner1, - const RiseFall *&rf1, - float &capacitance1, - float &limit1, - float &slack1) const -{ - corner1 = nullptr; - rf1 = nullptr; - capacitance1 = 0.0; - limit1 = 0.0; - slack1 = MinMax::min()->initValue(); - if (corner) - checkCapacitance1(pin, corner, min_max, - corner1, rf1, capacitance1, limit1, slack1); - else { - for (auto corner : *sta_->corners()) { - checkCapacitance1(pin, corner, min_max, - corner1, rf1, capacitance1, limit1, slack1); - } - } -} - -void -CheckCapacitanceLimits::checkCapacitance1(const Pin *pin, - const Corner *corner, - const MinMax *min_max, - // Return values. - const Corner *&corner1, - const RiseFall *&rf1, - float &capacitance1, - float &limit1, - float &slack1) const -{ - float limit; - bool limit_exists; - findLimit(pin, corner, min_max, limit, limit_exists); - if (limit_exists) { - for (auto rf : RiseFall::range()) { - checkCapacitance(pin, corner, min_max, rf, limit, - corner1, rf1, capacitance1, slack1, limit1); - } - } -} - -// Return the tightest limit. -void -CheckCapacitanceLimits::findLimit(const Pin *pin, - const Corner *corner, - const MinMax *min_max, - // Return values. - float &limit, - bool &exists) const -{ - const Network *network = sta_->network(); - Sdc *sdc = sta_->sdc(); - - // Default to top ("design") limit. - Cell *top_cell = network->cell(network->topInstance()); - sdc->capacitanceLimit(top_cell, min_max, - limit, exists); - - float limit1; - bool exists1; - if (network->isTopLevelPort(pin)) { - Port *port = network->port(pin); - sdc->capacitanceLimit(port, min_max, limit1, exists1); - if (exists1 - && (!exists - || min_max->compare(limit, limit1))) { - limit = limit1; - exists = true; - } - InputDrive *drive = sdc->findInputDrive(port); - if (drive) { - for (auto rf : RiseFall::range()) { - const LibertyCell *cell; - const LibertyPort *from_port; - float *from_slews; - const LibertyPort *to_port; - drive->driveCell(rf, min_max, cell, from_port, from_slews, to_port); - if (to_port) { - const LibertyPort *corner_port = to_port->cornerPort(corner, min_max); - corner_port->capacitanceLimit(min_max, limit1, exists1); - if (!exists1 - && corner_port->direction()->isAnyOutput() - && min_max == MinMax::max()) - corner_port->libertyLibrary()->defaultMaxCapacitance(limit1, exists1); - if (exists1 - && (!exists - || min_max->compare(limit, limit1))) { - limit = limit1; - exists = true; - } - } - } - } - } - else { - Cell *cell = network->cell(network->instance(pin)); - sdc->capacitanceLimit(cell, min_max, - limit1, exists1); - if (exists1 - && (!exists - || min_max->compare(limit, limit1))) { - limit = limit1; - exists = true; - } - LibertyPort *port = network->libertyPort(pin); - if (port) { - LibertyPort *corner_port = port->cornerPort(corner, min_max); - corner_port->capacitanceLimit(min_max, limit1, exists1); - if (!exists1 - && port->direction()->isAnyOutput()) - corner_port->libertyLibrary()->defaultMaxCapacitance(limit1, exists1); - if (exists1 - && (!exists - || min_max->compare(limit, limit1))) { - limit = limit1; - exists = true; - } - } - } -} - -void -CheckCapacitanceLimits::checkCapacitance(const Pin *pin, - const Corner *corner, - const MinMax *min_max, - const RiseFall *rf, - float limit, - // Return values. - const Corner *&corner1, - const RiseFall *&rf1, - float &capacitance1, - float &slack1, - float &limit1) const -{ - const DcalcAnalysisPt *dcalc_ap = corner->findDcalcAnalysisPt(min_max); - GraphDelayCalc *dcalc = sta_->graphDelayCalc(); - float cap = dcalc->loadCap(pin, dcalc_ap); - - float slack = (min_max == MinMax::max()) - ? limit - cap : cap - limit; - if (slack < slack1 - // Break ties for the sake of regression stability. - || (fuzzyEqual(slack, slack1) - && rf->index() < rf1->index())) { - corner1 = corner; - rf1 = rf; - capacitance1 = cap; - slack1 = slack; - limit1 = limit; - } -} - -//////////////////////////////////////////////////////////////// - -PinSeq -CheckCapacitanceLimits::checkCapacitanceLimits(const Net *net, - bool violators, - const Corner *corner, - const MinMax *min_max) -{ - const Network *network = sta_->network(); - PinSeq cap_pins; - float min_slack = MinMax::min()->initValue(); - if (net) { - NetPinIterator *pin_iter = network->pinIterator(net); - while (pin_iter->hasNext()) { - const Pin *pin = pin_iter->next(); - checkCapLimits(pin, violators, corner, min_max, cap_pins, min_slack); - } - delete pin_iter; - } - else { - LeafInstanceIterator *inst_iter = network->leafInstanceIterator(); - while (inst_iter->hasNext()) { - Instance *inst = inst_iter->next(); - checkCapLimits(inst, violators, corner, min_max, cap_pins, min_slack); - } - delete inst_iter; - // Check top level ports. - checkCapLimits(network->topInstance(), violators, corner, min_max, - cap_pins, min_slack); - } - sort(cap_pins, PinCapacitanceLimitSlackLess(corner, min_max, this, sta_)); - // Keep the min slack pin unless all violators or net pins. - if (!cap_pins.empty() && !violators && net == nullptr) - cap_pins.resize(1); - return cap_pins; -} - -void -CheckCapacitanceLimits::checkCapLimits(const Instance *inst, - bool violators, - const Corner *corner, - const MinMax *min_max, - PinSeq &cap_pins, - float &min_slack) -{ - const Network *network = sta_->network(); - InstancePinIterator *pin_iter = network->pinIterator(inst); - while (pin_iter->hasNext()) { - Pin *pin = pin_iter->next(); - checkCapLimits(pin, violators, corner, min_max, cap_pins, min_slack); - } - delete pin_iter; -} - -void -CheckCapacitanceLimits::checkCapLimits(const Pin *pin, - bool violators, - const Corner *corner, - const MinMax *min_max, - PinSeq &cap_pins, - float &min_slack) -{ - if (checkPin(pin)) { - const Corner *corner1; - const RiseFall *rf; - float capacitance, limit, slack; - checkCapacitance(pin, corner, min_max, corner1, rf, capacitance, limit, slack); - if (!fuzzyInf(slack)) { - if (violators) { - if (slack < 0.0) - cap_pins.push_back(pin); - } - else { - if (cap_pins.empty() - || slack < min_slack) { - cap_pins.push_back(pin); - min_slack = slack; - } - } - } - } -} - -bool -CheckCapacitanceLimits::checkPin(const Pin *pin) -{ - const Network *network = sta_->network(); - const Sim *sim = sta_->sim(); - const Sdc *sdc = sta_->sdc(); - const Graph *graph = sta_->graph(); - Vertex *vertex = graph->pinLoadVertex(pin); - return network->isDriver(pin) - && !sim->logicZeroOne(pin) - && !sdc->isDisabled(pin) - && !(vertex && sta_->isIdealClock(pin)); -} - -} // namespace diff --git a/search/CheckCapacitanceLimits.hh b/search/CheckCapacitanceLimits.hh deleted file mode 100644 index cae73774..00000000 --- a/search/CheckCapacitanceLimits.hh +++ /dev/null @@ -1,105 +0,0 @@ -// OpenSTA, Static Timing Analyzer -// Copyright (c) 2025, Parallax Software, Inc. -// -// This program is free software: you can redistribute it and/or modify -// it under the terms of the GNU General Public License as published by -// the Free Software Foundation, either version 3 of the License, or -// (at your option) any later version. -// -// This program is distributed in the hope that it will be useful, -// but WITHOUT ANY WARRANTY; without even the implied warranty of -// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -// GNU General Public License for more details. -// -// You should have received a copy of the GNU General Public License -// along with this program. If not, see . -// -// The origin of this software must not be misrepresented; you must not -// claim that you wrote the original software. -// -// Altered source versions must be plainly marked as such, and must not be -// misrepresented as being the original software. -// -// This notice may not be removed or altered from any source distribution. - -#pragma once - -#include "MinMax.hh" -#include "Transition.hh" -#include "NetworkClass.hh" -#include "SdcClass.hh" -#include "Sta.hh" - -namespace sta { - -class StaState; -class Corner; - -class CheckCapacitanceLimits -{ -public: - CheckCapacitanceLimits(const Sta *sta); - // corner=nullptr checks all corners. - void checkCapacitance(const Pin *pin, - const Corner *corner1, - const MinMax *min_max, - // Return values. - // Corner is nullptr for no capacitance limit. - const Corner *&corner, - const RiseFall *&rf, - float &capacitance, - float &limit, - float &slack) const; - // Return pins with the min/max cap limit slack. - // net=null check all nets - // corner=nullptr checks all corners. - PinSeq checkCapacitanceLimits(const Net *net, - bool violators, - const Corner *corner, - const MinMax *min_max); - -protected: - void checkCapacitance(const Pin *pin, - const Corner *corner, - const MinMax *min_max, - const RiseFall *rf, - float limit, - // Return values. - const Corner *&corner1, - const RiseFall *&rf1, - float &capacitance1, - float &slack1, - float &limit1) const; - void checkCapacitance1(const Pin *pin, - const Corner *corner, - const MinMax *min_max, - // Return values. - const Corner *&corner1, - const RiseFall *&rf1, - float &capacitance1, - float &limit1, - float &slack1) const; - void findLimit(const Pin *pin, - const Corner *corner, - const MinMax *min_max, - // Return values. - float &limit, - bool &limit_exists) const; - void checkCapLimits(const Instance *inst, - bool violators, - const Corner *corner, - const MinMax *min_max, - PinSeq &cap_pins, - float &min_slack); - void checkCapLimits(const Pin *pin, - bool violators, - const Corner *corner, - const MinMax *min_max, - PinSeq &cap_pins, - float &min_slack); - bool checkPin(const Pin *pin); - - const Sta *sta_; -}; - -} // namespace diff --git a/search/CheckCapacitances.cc b/search/CheckCapacitances.cc new file mode 100644 index 00000000..c084ca8c --- /dev/null +++ b/search/CheckCapacitances.cc @@ -0,0 +1,369 @@ +// OpenSTA, Static Timing Analyzer +// Copyright (c) 2025, Parallax Software, Inc. +// +// This program is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see . +// +// The origin of this software must not be misrepresented; you must not +// claim that you wrote the original software. +// +// Altered source versions must be plainly marked as such, and must not be +// misrepresented as being the original software. +// +// This notice may not be removed or altered from any source distribution. + +#include "CheckCapacitances.hh" + +#include "ContainerHelpers.hh" +#include "Fuzzy.hh" +#include "Liberty.hh" +#include "Network.hh" +#include "Sdc.hh" +#include "Mode.hh" +#include "InputDrive.hh" +#include "GraphDelayCalc.hh" +#include "StaState.hh" +#include "Scene.hh" +#include "PortDirection.hh" +#include "Sim.hh" +#include "Graph.hh" +#include "GraphDelayCalc.hh" +#include "ClkNetwork.hh" +#include "Transition.hh" +#include "BoundedHeap.hh" + +namespace sta { + +class CapacitanceCheckSlackLess +{ +public: + CapacitanceCheckSlackLess(const StaState *sta); + bool operator()(const CapacitanceCheck &check1, + const CapacitanceCheck &check2) const; + +private: + const StaState *sta_; +}; + +CapacitanceCheckSlackLess::CapacitanceCheckSlackLess(const StaState *sta) : + sta_(sta) +{ +} + +bool +CapacitanceCheckSlackLess::operator()(const CapacitanceCheck &check1, + const CapacitanceCheck &check2) const +{ + return fuzzyLess(check1.slack(), check2.slack()) + || (fuzzyEqual(check1.slack(), check2.slack()) + // Break ties for the sake of regression stability. + && sta_->network()->pinLess(check1.pin(), check2.pin())); +} + +//////////////////////////////////////////////////////////////// + +CheckCapacitances::CheckCapacitances(const StaState *sta) : + sta_(sta) +{ +} + +void +CheckCapacitances::clear() +{ + checks_.clear(); +} + +CapacitanceCheck +CheckCapacitances::check(const Pin *pin, + const SceneSeq &scenes, + const MinMax *min_max) const +{ + return check(pin, false, scenes, min_max); +} + +CapacitanceCheck +CheckCapacitances::check(const Pin *pin, + bool violators, + const SceneSeq &scenes, + const MinMax *min_max) const +{ + CapacitanceCheck min_slack_check(nullptr, 0.0, min_max->initValue(), + MinMax::min()->initValue(), nullptr, nullptr); + GraphDelayCalc *dcalc = sta_->graphDelayCalc(); + + for (const Scene *scene : scenes) { + if (checkPin(pin, scene)) { + float limit; + bool limit_exists; + findLimit(pin, scene, min_max, limit, limit_exists); + if (limit_exists) { + for (const RiseFall *rf : RiseFall::range()) { + float cap = dcalc->loadCap(pin, scene, min_max); + float slack = (min_max == MinMax::max()) + ? limit - cap : cap - limit; + if ((!violators || fuzzyLess(slack, 0.0)) + && (min_slack_check.pin() == nullptr + || fuzzyLess(slack, min_slack_check.slack()) + // Break ties for the sake of regression stability. + || (fuzzyEqual(slack, min_slack_check.slack()) + && rf->index() < min_slack_check.rf()->index()))) + min_slack_check = CapacitanceCheck(pin, cap, limit, slack, scene, rf); + } + } + } + } + return min_slack_check; +} + +// Return the tightest limit. +void +CheckCapacitances::findLimit(const Pin *pin, + const Scene *scene, + const MinMax *min_max, + // Return values. + float &limit, + bool &exists) const +{ + const Network *network = sta_->network(); + Sdc *sdc = scene->sdc(); + + // Default to top ("design") limit. + Cell *top_cell = network->cell(network->topInstance()); + sdc->capacitanceLimit(top_cell, min_max, + limit, exists); + + float limit1; + bool exists1; + if (network->isTopLevelPort(pin)) { + Port *port = network->port(pin); + sdc->capacitanceLimit(port, min_max, limit1, exists1); + if (exists1 + && (!exists + || min_max->compare(limit, limit1))) { + limit = limit1; + exists = true; + } + InputDrive *drive = sdc->findInputDrive(port); + if (drive) { + for (auto rf : RiseFall::range()) { + const LibertyCell *cell; + const LibertyPort *from_port; + float *from_slews; + const LibertyPort *to_port; + drive->driveCell(rf, min_max, cell, from_port, from_slews, to_port); + if (to_port) { + const LibertyPort *scene_port = to_port->scenePort(scene, min_max); + scene_port->capacitanceLimit(min_max, limit1, exists1); + if (!exists1 + && scene_port->direction()->isAnyOutput() + && min_max == MinMax::max()) + scene_port->libertyLibrary()->defaultMaxCapacitance(limit1, exists1); + if (exists1 + && (!exists + || min_max->compare(limit, limit1))) { + limit = limit1; + exists = true; + } + } + } + } + } + else { + Cell *cell = network->cell(network->instance(pin)); + sdc->capacitanceLimit(cell, min_max, + limit1, exists1); + if (exists1 + && (!exists + || min_max->compare(limit, limit1))) { + limit = limit1; + exists = true; + } + LibertyPort *port = network->libertyPort(pin); + if (port) { + LibertyPort *scene_port = port->scenePort(scene, min_max); + scene_port->capacitanceLimit(min_max, limit1, exists1); + if (!exists1 + && port->direction()->isAnyOutput()) + scene_port->libertyLibrary()->defaultMaxCapacitance(limit1, exists1); + if (exists1 + && (!exists + || min_max->compare(limit, limit1))) { + limit = limit1; + exists = true; + } + } + } +} + +//////////////////////////////////////////////////////////////// + +CapacitanceCheckSeq & +CheckCapacitances::check(const Net *net, + size_t max_count, + bool violations, + const SceneSeq &scenes, + const MinMax *min_max) +{ + clear(); + if (violations) + return checkViolations(net, scenes, min_max); + else + return checkMaxCount(net, max_count, scenes, min_max); +} + +CapacitanceCheckSeq & +CheckCapacitances::checkViolations(const Net *net, + const SceneSeq &scenes, + const MinMax *min_max) +{ + const Network *network = sta_->network(); + if (net) { + NetPinIterator *pin_iter = network->pinIterator(net); + while (pin_iter->hasNext()) { + const Pin *pin = pin_iter->next(); + CapacitanceCheck cap_check = check(pin, true, scenes, min_max); + if (!cap_check.isNull()) + checks_.push_back(cap_check); + } + delete pin_iter; + } + else { + LeafInstanceIterator *inst_iter = network->leafInstanceIterator(); + while (inst_iter->hasNext()) { + Instance *inst = inst_iter->next(); + checkCapLimits(inst, true, scenes, min_max); + } + delete inst_iter; + // Check top level ports. + checkCapLimits(network->topInstance(), true, scenes, min_max); + } + + sort(checks_, CapacitanceCheckSlackLess(sta_)); + return checks_; +} + +CapacitanceCheckSeq & +CheckCapacitances::checkMaxCount(const Net *net, + size_t max_count, + const SceneSeq &scenes, + const MinMax *min_max) +{ + const Network *network = sta_->network(); + CapacitanceCheckHeap heap(max_count, CapacitanceCheckSlackLess(sta_)); + + if (net) { + NetPinIterator *pin_iter = network->pinIterator(net); + while (pin_iter->hasNext()) { + const Pin *pin = pin_iter->next(); + check(pin, scenes, min_max, heap); + } + delete pin_iter; + } + else { + LeafInstanceIterator *inst_iter = network->leafInstanceIterator(); + while (inst_iter->hasNext()) { + Instance *inst = inst_iter->next(); + checkCapLimits(inst, scenes, min_max, heap); + } + delete inst_iter; + // Check top level ports. + checkCapLimits(network->topInstance(), scenes, min_max, heap); + } + + checks_ = heap.extract(); + return checks_; +} + +void +CheckCapacitances::checkCapLimits(const Instance *inst, + bool violators, + const SceneSeq &scenes, + const MinMax *min_max) +{ + const Network *network = sta_->network(); + InstancePinIterator *pin_iter = network->pinIterator(inst); + while (pin_iter->hasNext()) { + Pin *pin = pin_iter->next(); + CapacitanceCheck cap_check = check(pin, violators, scenes, min_max); + if (!cap_check.isNull()) + checks_.push_back(cap_check); + } + delete pin_iter; +} + +void +CheckCapacitances::checkCapLimits(const Instance *inst, + const SceneSeq &scenes, + const MinMax *min_max, + CapacitanceCheckHeap &heap) +{ + const Network *network = sta_->network(); + InstancePinIterator *pin_iter = network->pinIterator(inst); + while (pin_iter->hasNext()) { + Pin *pin = pin_iter->next(); + check(pin, scenes, min_max, heap); + } + delete pin_iter; +} + +void +CheckCapacitances::check(const Pin *pin, + const SceneSeq &scenes, + const MinMax *min_max, + CapacitanceCheckHeap &heap) +{ + CapacitanceCheck cap_check = check(pin, false, scenes, min_max); + if (!cap_check.isNull()) + heap.insert(cap_check); +} + +bool +CheckCapacitances::checkPin(const Pin *pin, + const Scene *scene) const +{ + const Network *network = sta_->network(); + const Mode *mode = scene->mode(); + return network->isDriver(pin) + && !mode->sim()->isConstant(pin) + && !mode->sdc()->isDisabledConstraint(pin) + && !mode->clkNetwork()->isIdealClock(pin); +} + +//////////////////////////////////////////////////////////////// + +CapacitanceCheck::CapacitanceCheck() : + pin_(nullptr), + capacitance_(0.0), + limit_(INF), + slack_(-INF), + scene_(nullptr), + rf_(nullptr) +{ +} + +CapacitanceCheck::CapacitanceCheck(const Pin *pin, + float capacitance, + float limit, + float slack, + const Scene *scene, + const RiseFall *rf) : + pin_(pin), + capacitance_(capacitance), + limit_(limit), + slack_(slack), + scene_(scene), + rf_(rf) +{ +} + +} // namespace diff --git a/search/CheckCapacitances.hh b/search/CheckCapacitances.hh new file mode 100644 index 00000000..4d395cf5 --- /dev/null +++ b/search/CheckCapacitances.hh @@ -0,0 +1,128 @@ +// OpenSTA, Static Timing Analyzer +// Copyright (c) 2025, Parallax Software, Inc. +// +// This program is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see . +// +// The origin of this software must not be misrepresented; you must not +// claim that you wrote the original software. +// +// Altered source versions must be plainly marked as such, and must not be +// misrepresented as being the original software. +// +// This notice may not be removed or altered from any source distribution. + +#pragma once + +#include + +#include "MinMax.hh" +#include "Transition.hh" +#include "NetworkClass.hh" +#include "SdcClass.hh" +#include "StaState.hh" +#include "BoundedHeap.hh" + +namespace sta { + +class StaState; +class Scene; +class RiseFall; +class CapacitanceCheckSlackLess; + +class CapacitanceCheck +{ +public: + CapacitanceCheck(); + CapacitanceCheck(const Pin *pin, + float capacitance, + float limit, + float slack, + const Scene *scene, + const RiseFall *rf); + bool isNull() { return pin_ == nullptr; } + const Pin *pin() const { return pin_; } + float capacitance() const { return capacitance_; } + float limit() const { return limit_; } + float slack() const { return slack_; } + const Scene *scene() const { return scene_; } + const RiseFall *rf() const { return rf_; } + +private: + const Pin *pin_; + float capacitance_; + float limit_; + float slack_; + const Scene *scene_; + const RiseFall *rf_; +}; + +using CapacitanceCheckSeq = std::vector; +using CapacitanceCheckHeap = BoundedHeap; + +class CheckCapacitances +{ +public: + CheckCapacitances(const StaState *sta); + void clear(); + // Return pins with the min/max cap limit slack. + // net=null check all nets + CapacitanceCheckSeq &check(const Net *net, + size_t max_count, + bool violators, + const SceneSeq &scenes, + const MinMax *min_max); + // Return min slack check across scenes. + CapacitanceCheck check(const Pin *pin, + const SceneSeq &scenes, + const MinMax *min_max) const; + +protected: + CapacitanceCheck check(const Pin *pin, + bool violators, + const SceneSeq &scenes, + const MinMax *min_max) const; + void findLimit(const Pin *pin, + const Scene *scene, + const MinMax *min_max, + // Return values. + float &limit, + bool &limit_exists) const; + void checkCapLimits(const Instance *inst, + bool violators, + const SceneSeq &scenes, + const MinMax *min_max); + void checkCapLimits(const Instance *inst, + const SceneSeq &scenes, + const MinMax *min_max, + CapacitanceCheckHeap &heap); + void check(const Pin *pin, + const SceneSeq &scenes, + const MinMax *min_max, + CapacitanceCheckHeap &heap); + CapacitanceCheckSeq &checkViolations(const Net *net, + const SceneSeq &scenes, + const MinMax *min_max); + CapacitanceCheckSeq &checkMaxCount(const Net *net, + size_t max_count, + const SceneSeq &scenes, + const MinMax *min_max); + bool checkPin(const Pin *pin, + const Scene *scene) const; + + const StaState *sta_; + CapacitanceCheckSeq checks_; +}; + +} // namespace + diff --git a/search/CheckFanoutLimits.cc b/search/CheckFanoutLimits.cc deleted file mode 100644 index 726fbc31..00000000 --- a/search/CheckFanoutLimits.cc +++ /dev/null @@ -1,332 +0,0 @@ -// OpenSTA, Static Timing Analyzer -// Copyright (c) 2025, Parallax Software, Inc. -// -// This program is free software: you can redistribute it and/or modify -// it under the terms of the GNU General Public License as published by -// the Free Software Foundation, either version 3 of the License, or -// (at your option) any later version. -// -// This program is distributed in the hope that it will be useful, -// but WITHOUT ANY WARRANTY; without even the implied warranty of -// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -// GNU General Public License for more details. -// -// You should have received a copy of the GNU General Public License -// along with this program. If not, see . -// -// The origin of this software must not be misrepresented; you must not -// claim that you wrote the original software. -// -// Altered source versions must be plainly marked as such, and must not be -// misrepresented as being the original software. -// -// This notice may not be removed or altered from any source distribution. - -#include "CheckFanoutLimits.hh" - -#include "Fuzzy.hh" -#include "Liberty.hh" -#include "Network.hh" -#include "Sdc.hh" -#include "InputDrive.hh" -#include "Sim.hh" -#include "PortDirection.hh" -#include "Graph.hh" -#include "Search.hh" - -namespace sta { - -class PinFanoutLimitSlackLess -{ -public: - PinFanoutLimitSlackLess(const MinMax *min_max, - CheckFanoutLimits *check_fanout_limit, - const StaState *sta); - bool operator()(const Pin *pin1, - const Pin *pin2) const; - -private: - const MinMax *min_max_; - CheckFanoutLimits *check_fanout_limit_; - const StaState *sta_; - -}; - -PinFanoutLimitSlackLess::PinFanoutLimitSlackLess(const MinMax *min_max, - CheckFanoutLimits *check_fanout_limit, - const StaState *sta) : - min_max_(min_max), - check_fanout_limit_(check_fanout_limit), - sta_(sta) -{ -} - -bool -PinFanoutLimitSlackLess::operator()(const Pin *pin1, - const Pin *pin2) const -{ - float fanout1, fanout2; - float limit1, limit2, slack1, slack2; - check_fanout_limit_->checkFanout(pin1, min_max_, - fanout1, limit1, slack1); - check_fanout_limit_->checkFanout(pin2, min_max_, - fanout2, limit2, slack2); - return fuzzyLess(slack1, slack2) - || (fuzzyEqual(slack1, slack2) - // Break ties for the sake of regression stability. - && sta_->network()->pinLess(pin1, pin2)); -} - -//////////////////////////////////////////////////////////////// - -CheckFanoutLimits::CheckFanoutLimits(const Sta *sta) : - sta_(sta) -{ -} - -void -CheckFanoutLimits::checkFanout(const Pin *pin, - const MinMax *min_max, - // Return values. - float &fanout, - float &limit, - float &slack) const -{ - fanout = 0.0; - limit = min_max->initValue(); - slack = MinMax::min()->initValue(); - - float limit1; - bool limit1_exists; - findLimit(pin, min_max, limit1, limit1_exists); - if (limit1_exists) - checkFanout(pin, min_max, limit1, - fanout, limit, slack); -} - -// return the tightest limit. -void -CheckFanoutLimits::findLimit(const Pin *pin, - const MinMax *min_max, - // Return values. - float &limit, - bool &exists) const -{ - const Network *network = sta_->network(); - Sdc *sdc = sta_->sdc(); - - limit = min_max->initValue(); - exists = false; - - // Default to top ("design") limit. - // Applies to input ports as well as instance outputs. - Cell *top_cell = network->cell(network->topInstance()); - sdc->fanoutLimit(top_cell, min_max, - limit, exists); - - float limit1; - bool exists1; - if (network->isTopLevelPort(pin)) { - Port *port = network->port(pin); - sdc->fanoutLimit(port, min_max, limit1, exists1); - if (exists1 - && (!exists - || min_max->compare(limit, limit1))) { - limit = limit1; - exists = true; - } - InputDrive *drive = sdc->findInputDrive(port); - if (drive) { - for (auto rf : RiseFall::range()) { - const LibertyCell *cell; - const LibertyPort *from_port; - float *from_slews; - const LibertyPort *to_port; - drive->driveCell(rf, min_max, cell, from_port, from_slews, to_port); - if (to_port) { - to_port->fanoutLimit(min_max, limit1, exists1); - if (!exists1 - && min_max == MinMax::max() - && to_port->direction()->isAnyOutput()) - to_port->libertyLibrary()->defaultMaxFanout(limit1, exists1); - if (exists1 - && (!exists - || min_max->compare(limit, limit1))) { - limit = limit1; - exists = true; - } - } - } - } - } - else { - Cell *cell = network->cell(network->instance(pin)); - sdc->fanoutLimit(cell, min_max, - limit1, exists1); - if (exists1 - && (!exists - || min_max->compare(limit, limit1))) { - limit = limit1; - exists = true; - } - LibertyPort *port = network->libertyPort(pin); - if (port) { - port->fanoutLimit(min_max, limit1, exists1); - if (!exists1 - && min_max == MinMax::max() - && port->direction()->isAnyOutput()) - port->libertyLibrary()->defaultMaxFanout(limit1, exists1); - if (exists1 - && (!exists - || min_max->compare(limit, limit1))) { - limit = limit1; - exists = true; - } - } - } -} - -void -CheckFanoutLimits::checkFanout(const Pin *pin, - const MinMax *min_max, - float limit1, - // Return values. - float &fanout, - float &limit, - float &slack) const -{ - float fanout1 = fanoutLoad(pin); - float slack1 = (min_max == MinMax::max()) - ? limit1 - fanout1 - : fanout1 - limit1; - if (fuzzyLessEqual(slack1, slack)) { - fanout = fanout1; - slack = slack1; - limit = limit1; - } -} - -float -CheckFanoutLimits::fanoutLoad(const Pin *pin) const -{ - float fanout = 0; - const Network *network = sta_->network(); - NetConnectedPinIterator *pin_iter = network->connectedPinIterator(pin); - while (pin_iter->hasNext()) { - const Pin *fanout_pin = pin_iter->next(); - if (network->isLoad(fanout_pin) - && !network->isTopLevelPort(fanout_pin)) { - LibertyPort *port = network->libertyPort(fanout_pin); - if (port) { - float fanout_load; - bool exists; - port->fanoutLoad(fanout_load, exists); - if (!exists) { - LibertyLibrary *lib = port->libertyLibrary(); - lib->defaultFanoutLoad(fanout_load, exists); - } - if (exists) - fanout += fanout_load; - } - else - fanout += 1; - } - } - delete pin_iter; - return fanout; -} - -//////////////////////////////////////////////////////////////// - -PinSeq -CheckFanoutLimits::checkFanoutLimits(const Net *net, - bool violators, - const MinMax *min_max) -{ - const Network *network = sta_->network(); - PinSeq fanout_pins; - float min_slack = MinMax::min()->initValue(); - if (net) { - NetPinIterator *pin_iter = network->pinIterator(net); - while (pin_iter->hasNext()) { - const Pin *pin = pin_iter->next(); - checkFanoutLimits(pin, violators, min_max, fanout_pins, min_slack); - } - delete pin_iter; - } - else { - LeafInstanceIterator *inst_iter = network->leafInstanceIterator(); - while (inst_iter->hasNext()) { - const Instance *inst = inst_iter->next(); - checkFanoutLimits(inst, violators, min_max, fanout_pins, min_slack); - } - delete inst_iter; - // Check top level ports. - checkFanoutLimits(network->topInstance(), violators, min_max, - fanout_pins, min_slack); - } - sort(fanout_pins, PinFanoutLimitSlackLess(min_max, this, sta_)); - // Keep the min slack pin unless all violators or net pins. - if (!fanout_pins.empty() && !violators && net == nullptr) - fanout_pins.resize(1); - return fanout_pins; -} - -void -CheckFanoutLimits::checkFanoutLimits(const Instance *inst, - bool violators, - const MinMax *min_max, - PinSeq &fanout_pins, - float &min_slack) -{ - const Network *network = sta_->network(); - InstancePinIterator *pin_iter = network->pinIterator(inst); - while (pin_iter->hasNext()) { - const Pin *pin = pin_iter->next(); - checkFanoutLimits(pin, violators, min_max, fanout_pins, min_slack); - } - delete pin_iter; -} - -void -CheckFanoutLimits::checkFanoutLimits(const Pin *pin, - bool violators, - const MinMax *min_max, - PinSeq &fanout_pins, - float &min_slack) -{ - if (checkPin(pin)) { - float fanout; - float limit, slack; - checkFanout(pin, min_max, fanout, limit, slack); - if (!fuzzyInf(slack)) { - if (violators) { - if (slack < 0.0) - fanout_pins.push_back(pin); - } - else { - if (fanout_pins.empty() - || slack < min_slack) { - fanout_pins.push_back(pin); - min_slack = slack; - } - } - } - } -} - -bool -CheckFanoutLimits::checkPin(const Pin *pin) -{ - const Network *network = sta_->network(); - const Sim *sim = sta_->sim(); - const Sdc *sdc = sta_->sdc(); - const Graph *graph = sta_->graph(); - Vertex *vertex = graph->pinDrvrVertex(pin); - return network->isDriver(pin) - && !sim->logicZeroOne(pin) - && !sdc->isDisabled(pin) - && !(vertex && sta_->isIdealClock(pin)); -} - -} // namespace diff --git a/search/CheckFanoutLimits.hh b/search/CheckFanoutLimits.hh deleted file mode 100644 index 0af63f3e..00000000 --- a/search/CheckFanoutLimits.hh +++ /dev/null @@ -1,82 +0,0 @@ -// OpenSTA, Static Timing Analyzer -// Copyright (c) 2025, Parallax Software, Inc. -// -// This program is free software: you can redistribute it and/or modify -// it under the terms of the GNU General Public License as published by -// the Free Software Foundation, either version 3 of the License, or -// (at your option) any later version. -// -// This program is distributed in the hope that it will be useful, -// but WITHOUT ANY WARRANTY; without even the implied warranty of -// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -// GNU General Public License for more details. -// -// You should have received a copy of the GNU General Public License -// along with this program. If not, see . -// -// The origin of this software must not be misrepresented; you must not -// claim that you wrote the original software. -// -// Altered source versions must be plainly marked as such, and must not be -// misrepresented as being the original software. -// -// This notice may not be removed or altered from any source distribution. - -#pragma once - -#include "MinMax.hh" -#include "NetworkClass.hh" -#include "SdcClass.hh" -#include "Sta.hh" - -namespace sta { - -class StaState; - -class CheckFanoutLimits -{ -public: - CheckFanoutLimits(const Sta *sta); - void checkFanout(const Pin *pin, - const MinMax *min_max, - // Return values. - float &fanout, - float &limit, - float &slack) const; - // Return pins with the min/max fanout limit slack. - // net=null check all nets - // corner=nullptr checks all corners. - PinSeq checkFanoutLimits(const Net *net, - bool violators, - const MinMax *min_max); - -protected: - void checkFanout(const Pin *pin, - const MinMax *min_max, - float limit1, - // Return values. - float &fanout, - float &limit, - float &slack) const; - void findLimit(const Pin *pin, - const MinMax *min_max, - // Return values. - float &limit, - bool &limit_exists) const; - float fanoutLoad(const Pin *pin) const; - void checkFanoutLimits(const Instance *inst, - bool violators, - const MinMax *min_max, - PinSeq &fanout_pins, - float &min_slack); - void checkFanoutLimits(const Pin *pin, - bool violators, - const MinMax *min_max, - PinSeq &fanout_pins, - float &min_slack); - bool checkPin(const Pin *pin); - - const Sta *sta_; -}; - -} // namespace diff --git a/search/CheckFanouts.cc b/search/CheckFanouts.cc new file mode 100644 index 00000000..7b5a03d0 --- /dev/null +++ b/search/CheckFanouts.cc @@ -0,0 +1,334 @@ +// OpenSTA, Static Timing Analyzer +// Copyright (c) 2025, Parallax Software, Inc. +// +// This program is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see . +// +// The origin of this software must not be misrepresented; you must not +// claim that you wrote the original software. +// +// Altered source versions must be plainly marked as such, and must not be +// misrepresented as being the original software. +// +// This notice may not be removed or altered from any source distribution. + +#include "CheckFanouts.hh" + +#include "ContainerHelpers.hh" +#include "Fuzzy.hh" +#include "Liberty.hh" +#include "Network.hh" +#include "Sdc.hh" +#include "Mode.hh" +#include "InputDrive.hh" +#include "Sim.hh" +#include "PortDirection.hh" +#include "Graph.hh" +#include "Search.hh" +#include "ClkNetwork.hh" + +namespace sta { + +CheckFanouts::CheckFanouts(const Sta *sta) : + sta_(sta), + heap_(0, FanoutCheckSlackLess(sta)) +{ +} + +void +CheckFanouts::clear() +{ + checks_.clear(); + heap_.clear(); +} + +FanoutCheck +CheckFanouts::check(const Pin *pin, + const Mode *mode, + const MinMax *min_max) const +{ + FanoutCheck min_slack_check; + float fanout = fanoutLoad(pin); + if (checkPin(pin, mode)) { + float limit; + bool limit_exists; + findLimit(pin, mode->sdc(), min_max, limit, limit_exists); + if (limit_exists) { + float slack = (min_max == MinMax::max()) + ? limit - fanout + : fanout - limit; + return FanoutCheck(pin, fanout, limit, slack, mode); + } + } + return FanoutCheck(); +} + +// return the tightest limit. +void +CheckFanouts::findLimit(const Pin *pin, + const Sdc *sdc, + const MinMax *min_max, + // Return values. + float &limit, + bool &exists) const +{ + const Network *network = sta_->network(); + + limit = min_max->initValue(); + exists = false; + + // Default to top ("design") limit. + // Applies to input ports as well as instance outputs. + Cell *top_cell = network->cell(network->topInstance()); + sdc->fanoutLimit(top_cell, min_max, + limit, exists); + + float limit1; + bool exists1; + if (network->isTopLevelPort(pin)) { + Port *port = network->port(pin); + sdc->fanoutLimit(port, min_max, limit1, exists1); + if (exists1 + && (!exists + || min_max->compare(limit, limit1))) { + limit = limit1; + exists = true; + } + InputDrive *drive = sdc->findInputDrive(port); + if (drive) { + for (auto rf : RiseFall::range()) { + const LibertyCell *cell; + const LibertyPort *from_port; + float *from_slews; + const LibertyPort *to_port; + drive->driveCell(rf, min_max, cell, from_port, from_slews, to_port); + if (to_port) { + to_port->fanoutLimit(min_max, limit1, exists1); + if (!exists1 + && min_max == MinMax::max() + && to_port->direction()->isAnyOutput()) + to_port->libertyLibrary()->defaultMaxFanout(limit1, exists1); + if (exists1 + && (!exists + || min_max->compare(limit, limit1))) { + limit = limit1; + exists = true; + } + } + } + } + } + else { + Cell *cell = network->cell(network->instance(pin)); + sdc->fanoutLimit(cell, min_max, + limit1, exists1); + if (exists1 + && (!exists + || min_max->compare(limit, limit1))) { + limit = limit1; + exists = true; + } + LibertyPort *port = network->libertyPort(pin); + if (port) { + port->fanoutLimit(min_max, limit1, exists1); + if (!exists1 + && min_max == MinMax::max() + && port->direction()->isAnyOutput()) + port->libertyLibrary()->defaultMaxFanout(limit1, exists1); + if (exists1 + && (!exists + || min_max->compare(limit, limit1))) { + limit = limit1; + exists = true; + } + } + } +} + +float +CheckFanouts::fanoutLoad(const Pin *pin) const +{ + float fanout = 0; + const Network *network = sta_->network(); + NetConnectedPinIterator *pin_iter = network->connectedPinIterator(pin); + while (pin_iter->hasNext()) { + const Pin *fanout_pin = pin_iter->next(); + if (network->isLoad(fanout_pin) + && !network->isTopLevelPort(fanout_pin)) { + LibertyPort *port = network->libertyPort(fanout_pin); + if (port) { + float fanout_load; + bool exists; + port->fanoutLoad(fanout_load, exists); + if (!exists) { + LibertyLibrary *lib = port->libertyLibrary(); + lib->defaultFanoutLoad(fanout_load, exists); + } + if (exists) + fanout += fanout_load; + } + else + fanout += 1; + } + } + delete pin_iter; + return fanout; +} + +//////////////////////////////////////////////////////////////// + +FanoutCheckSeq & +CheckFanouts::check(const Net *net, + size_t max_count, + bool violators, + const ModeSeq &modes, + const MinMax *min_max) +{ + clear(); + if (!violators) + heap_.setMaxSize(max_count); + + if (net) + checkNet(net, violators, modes, min_max); + else + checkAll(violators, modes, min_max); + + if (violators) + sort(checks_, FanoutCheckSlackLess(sta_)); + else + checks_ = heap_.extract(); + return checks_; +} + +void +CheckFanouts::checkNet(const Net *net, + bool violators, + const ModeSeq &modes, + const MinMax *min_max) +{ + const Network *network = sta_->network(); + if (net) { + NetPinIterator *pin_iter = network->pinIterator(net); + while (pin_iter->hasNext()) { + const Pin *pin = pin_iter->next(); + checkPin(pin, violators, modes, min_max); + } + delete pin_iter; + } +} + +void +CheckFanouts::checkAll(bool violators, + const ModeSeq &modes, + const MinMax *min_max) +{ + const Network *network = sta_->network(); + LeafInstanceIterator *inst_iter = network->leafInstanceIterator(); + while (inst_iter->hasNext()) { + const Instance *inst = inst_iter->next(); + checkInst(inst, violators, modes, min_max); + } + delete inst_iter; + // Check top level ports. + checkInst(network->topInstance(), violators, modes, min_max); +} + +void +CheckFanouts::checkInst(const Instance *inst, + bool violators, + const ModeSeq &modes, + const MinMax *min_max) +{ + const Network *network = sta_->network(); + InstancePinIterator *pin_iter = network->pinIterator(inst); + while (pin_iter->hasNext()) { + const Pin *pin = pin_iter->next(); + checkPin(pin, violators, modes, min_max); + } + delete pin_iter; +} + +void +CheckFanouts::checkPin(const Pin *pin, + bool violators, + const ModeSeq &modes, + const MinMax *min_max) +{ + for (const Mode *mode : modes) { + if (checkPin(pin, mode)) { + FanoutCheck fanout_check = check(pin, mode, min_max); + if (!fanout_check.isNull()) { + if (violators) { + if (fanout_check.slack() < 0.0) + checks_.push_back(fanout_check); + } + else + heap_.insert(fanout_check); + } + } + } +} + +bool +CheckFanouts::checkPin(const Pin *pin, + const Mode *mode) const +{ + const Network *network = sta_->network(); + return network->isDriver(pin) + && !mode->sim()->isConstant(pin) + && !mode->sdc()->isDisabledConstraint(pin) + && !mode->clkNetwork()->isIdealClock(pin); +} + +//////////////////////////////////////////////////////////////// + +FanoutCheck::FanoutCheck() : + pin_(nullptr), + fanout_(0.0), + limit_(INF), + slack_(INF), + mode_(nullptr) +{ +} + +FanoutCheck::FanoutCheck(const Pin *pin, + float fanout, + float limit, + float slack, + const Mode *mode) : + pin_(pin), + fanout_(fanout), + limit_(limit), + slack_(slack), + mode_(mode) +{ +} + +//////////////////////////////////////////////////////////////// + +FanoutCheckSlackLess::FanoutCheckSlackLess(const StaState *sta) : + sta_(sta) +{ +} + +bool +FanoutCheckSlackLess::operator()(const FanoutCheck &check1, + const FanoutCheck &check2) const +{ + return fuzzyLess(check1.slack(), check2.slack()) + || (fuzzyEqual(check1.slack(), check2.slack()) + // Break ties for the sake of regression stability. + && sta_->network()->pinLess(check1.pin(), check2.pin())); +} + +} // namespace diff --git a/search/CheckFanouts.hh b/search/CheckFanouts.hh new file mode 100644 index 00000000..0cd3d1c3 --- /dev/null +++ b/search/CheckFanouts.hh @@ -0,0 +1,126 @@ +// OpenSTA, Static Timing Analyzer +// Copyright (c) 2025, Parallax Software, Inc. +// +// This program is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see . +// +// The origin of this software must not be misrepresented; you must not +// claim that you wrote the original software. +// +// Altered source versions must be plainly marked as such, and must not be +// misrepresented as being the original software. +// +// This notice may not be removed or altered from any source distribution. + +#pragma once + +#include + +#include "MinMax.hh" +#include "NetworkClass.hh" +#include "SdcClass.hh" +#include "Sta.hh" +#include "BoundedHeap.hh" + +namespace sta { + +class StaState; + +class FanoutCheck +{ +public: + FanoutCheck(); + FanoutCheck(const Pin *pin, + float fanout, + float limit, + float slack, + const Mode *mode); + bool isNull() { return pin_ == nullptr; } + const Pin *pin() const { return pin_; } + float fanout() const { return fanout_; } + float limit() const { return limit_; } + float slack() const { return slack_; } + const Mode *mode() const { return mode_; } + +private: + const Pin *pin_; + float fanout_; + float limit_; + float slack_; + const Mode *mode_; +}; + +class FanoutCheckSlackLess +{ +public: + FanoutCheckSlackLess(const StaState *sta); + bool operator()(const FanoutCheck &check1, + const FanoutCheck &check2) const; + +private: + const StaState *sta_; +}; + +using FanoutCheckSeq = std::vector; +using FanoutCheckHeap = BoundedHeap; + +class CheckFanouts +{ +public: + CheckFanouts(const Sta *sta); + void clear(); + // Return pins with the min/max fanout limit slack. + // net=null check all nets + FanoutCheckSeq &check(const Net *net, + size_t max_count, + bool violators, + const ModeSeq &modes, + const MinMax *min_max); + FanoutCheck check(const Pin *pin, + const Mode*mode, + const MinMax *min_max) const; + +protected: + void checkNet(const Net *net, + bool violators, + const ModeSeq &modes, + const MinMax *min_max); + void checkAll(bool violators, + const ModeSeq &modes, + const MinMax *min_max); + void checkInst(const Instance *inst, + bool violators, + const ModeSeq &modes, + const MinMax *min_max); + void checkPin(const Pin *pin, + bool violators, + const ModeSeq &modes, + const MinMax *min_max); + bool checkPin(const Pin *pin, + const Mode *mode) const; + + void findLimit(const Pin *pin, + const Sdc *sdc, + const MinMax *min_max, + // Return values. + float &limit, + bool &limit_exists) const; + float fanoutLoad(const Pin *pin) const; + + const Sta *sta_; + FanoutCheckSeq checks_; + FanoutCheckHeap heap_; +}; + +} // namespace + diff --git a/search/CheckMaxSkews.cc b/search/CheckMaxSkews.cc index 3496fb0c..8e71b8a5 100644 --- a/search/CheckMaxSkews.cc +++ b/search/CheckMaxSkews.cc @@ -31,21 +31,10 @@ #include "Graph.hh" #include "Clock.hh" #include "Path.hh" -#include "PathAnalysisPt.hh" #include "Search.hh" namespace sta { -// Abstract base class. -class MaxSkewCheckVisitor -{ -public: - MaxSkewCheckVisitor() {} - virtual ~MaxSkewCheckVisitor() {} - virtual void visit(MaxSkewCheck &check, - const StaState *sta) = 0; -}; - CheckMaxSkews::CheckMaxSkews(StaState *sta) : sta_(sta) { @@ -53,141 +42,57 @@ CheckMaxSkews::CheckMaxSkews(StaState *sta) : CheckMaxSkews::~CheckMaxSkews() { - checks_.deleteContents(); } void CheckMaxSkews::clear() { - checks_.deleteContentsClear(); -} - -class MaxSkewChecksVisitor : public MaxSkewCheckVisitor -{ -public: - explicit MaxSkewChecksVisitor(MaxSkewCheckSeq &checks); - virtual void visit(MaxSkewCheck &check, - const StaState *sta); - -private: - MaxSkewCheckSeq &checks_; -}; - -MaxSkewChecksVisitor::MaxSkewChecksVisitor(MaxSkewCheckSeq &checks) : - MaxSkewCheckVisitor(), - checks_(checks) -{ -} - -void -MaxSkewChecksVisitor::visit(MaxSkewCheck &check, - const StaState *) -{ - checks_.push_back(new MaxSkewCheck(check)); -} - -class MaxSkewViolatorsVisititor : public MaxSkewCheckVisitor -{ -public: - explicit MaxSkewViolatorsVisititor(MaxSkewCheckSeq &checks); - virtual void visit(MaxSkewCheck &check, - const StaState *sta); - -private: - MaxSkewCheckSeq &checks_; -}; - -MaxSkewViolatorsVisititor:: -MaxSkewViolatorsVisititor(MaxSkewCheckSeq &checks) : - MaxSkewCheckVisitor(), - checks_(checks) -{ -} - -void -MaxSkewViolatorsVisititor::visit(MaxSkewCheck &check, - const StaState *sta) -{ - if (delayLess(check.slack(sta), 0.0, sta)) - checks_.push_back(new MaxSkewCheck(check)); + checks_.clear(); } MaxSkewCheckSeq & -CheckMaxSkews::violations() +CheckMaxSkews::check(const Net *net, + size_t max_count, + bool violators, + const SceneSeq &scenes) { clear(); - MaxSkewViolatorsVisititor visitor(checks_); - visitMaxSkewChecks(&visitor); + scenes_ = Scene::sceneSet(scenes); + + Graph *graph = sta_->graph(); + const Network *network = sta_->network(); + if (net) { + NetPinIterator *pin_iter = network->pinIterator(net); + while (pin_iter->hasNext()) { + const Pin *pin = pin_iter->next(); + Vertex *vertex = graph->pinLoadVertex(pin); + check(vertex, violators); + } + delete pin_iter; + } + else { + VertexIterator vertex_iter(graph); + while (vertex_iter.hasNext()) { + Vertex *vertex = vertex_iter.next(); + check(vertex, violators); + } + } + + // Sort checks by slack sort(checks_, MaxSkewSlackLess(sta_)); + if (!violators && checks_.size() > max_count) + checks_.resize(max_count); return checks_; } -class MaxSkewSlackVisitor : public MaxSkewCheckVisitor -{ -public: - MaxSkewSlackVisitor(); - virtual void visit(MaxSkewCheck &check, - const StaState *sta); - MaxSkewCheck *minSlackCheck(); - -private: - MaxSkewCheck *min_slack_check_; -}; - -MaxSkewSlackVisitor::MaxSkewSlackVisitor() : - MaxSkewCheckVisitor(), - min_slack_check_(nullptr) -{ -} - void -MaxSkewSlackVisitor::visit(MaxSkewCheck &check, - const StaState *sta) -{ - MaxSkewSlackLess slack_less(sta); - if (min_slack_check_ == nullptr - || slack_less(&check, min_slack_check_)) { - delete min_slack_check_; - min_slack_check_ = new MaxSkewCheck(check); - } -} - -MaxSkewCheck * -MaxSkewSlackVisitor::minSlackCheck() -{ - return min_slack_check_; -} - -MaxSkewCheck * -CheckMaxSkews::minSlackCheck() -{ - clear(); - MaxSkewSlackVisitor visitor; - visitMaxSkewChecks(&visitor); - MaxSkewCheck *check = visitor.minSlackCheck(); - // Save check for cleanup. - checks_.push_back(check); - return check; -} - -void -CheckMaxSkews::visitMaxSkewChecks(MaxSkewCheckVisitor *visitor) -{ - Graph *graph = sta_->graph(); - VertexIterator vertex_iter(graph); - while (vertex_iter.hasNext()) { - Vertex *vertex = vertex_iter.next(); - visitMaxSkewChecks(vertex, visitor); - } -} - -void -CheckMaxSkews:: visitMaxSkewChecks(Vertex *vertex, - MaxSkewCheckVisitor *visitor) +CheckMaxSkews::check(Vertex *vertex, + bool violators) { Graph *graph = sta_->graph(); Search *search = sta_->search(); const MinMax *clk_min_max = MinMax::max(); + MaxSkewCheck min_slack_check; VertexInEdgeIterator edge_iter(vertex, graph); while (edge_iter.hasNext()) { Edge *edge = edge_iter.next(); @@ -195,35 +100,53 @@ CheckMaxSkews:: visitMaxSkewChecks(Vertex *vertex, Vertex *ref_vertex = edge->from(graph); TimingArcSet *arc_set = edge->timingArcSet(); for (TimingArc *arc : arc_set->arcs()) { - const RiseFall *clk_rf = arc->fromEdge()->asRiseFall(); - const RiseFall *ref_rf = arc->toEdge()->asRiseFall(); - VertexPathIterator clk_path_iter(vertex, clk_rf, clk_min_max, search); - while (clk_path_iter.hasNext()) { - Path *clk_path = clk_path_iter.next(); - if (clk_path->isClock(search)) { - const PathAnalysisPt *clk_ap = clk_path->pathAnalysisPt(sta_); - PathAnalysisPt *ref_ap = clk_ap->tgtClkAnalysisPt(); - VertexPathIterator ref_path_iter(ref_vertex, ref_rf, ref_ap, sta_); - while (ref_path_iter.hasNext()) { - Path *ref_path = ref_path_iter.next(); - if (ref_path->isClock(search)) { - MaxSkewCheck check(clk_path, ref_path, arc, edge); - visitor->visit(check, sta_); - } - } - } - } + const RiseFall *clk_rf = arc->fromEdge()->asRiseFall(); + const RiseFall *ref_rf = arc->toEdge()->asRiseFall(); + VertexPathIterator clk_path_iter(vertex, clk_rf, clk_min_max, search); + while (clk_path_iter.hasNext()) { + Path *clk_path = clk_path_iter.next(); + if (clk_path->isClock(search)) { + const Scene *scene = clk_path->scene(sta_); + if (scenes_.contains(scene)) { + const MinMax *ref_min_max = clk_path->tgtClkMinMax(sta_); + VertexPathIterator ref_path_iter(ref_vertex, scene, ref_min_max, + ref_rf, sta_); + while (ref_path_iter.hasNext()) { + Path *ref_path = ref_path_iter.next(); + if (ref_path->isClock(search)) { + MaxSkewCheck skew_check(clk_path, ref_path, arc, edge); + Slack slack = skew_check.slack(sta_); + if ((min_slack_check.isNull() + || delayLess(slack, min_slack_check.slack(sta_), sta_)) + && (!violators || + delayLess(slack, 0.0, sta_))) + min_slack_check = skew_check; + } + } + } + } + } } } } + if (!min_slack_check.isNull()) + checks_.push_back(min_slack_check); } //////////////////////////////////////////////////////////////// +MaxSkewCheck::MaxSkewCheck() : + clk_path_(nullptr), + ref_path_(nullptr), + check_arc_(nullptr), + check_edge_(nullptr) +{ +} + MaxSkewCheck::MaxSkewCheck(Path *clk_path, - Path *ref_path, - TimingArc *check_arc, - Edge *check_edge) : + Path *ref_path, + TimingArc *check_arc, + Edge *check_edge) : clk_path_(clk_path), ref_path_(ref_path), check_arc_(check_arc), @@ -248,8 +171,10 @@ MaxSkewCheck::maxSkew(const StaState *sta) const { Search *search = sta->search(); return search->deratedDelay(ref_path_->vertex(sta), - check_arc_, check_edge_, false, - clk_path_->pathAnalysisPt(sta)); + check_arc_, check_edge_, false, + clk_path_->minMax(sta), + clk_path_->dcalcAnalysisPtIndex(sta), + ref_path_->scene(sta)->sdc()); } Delay @@ -272,15 +197,15 @@ MaxSkewSlackLess::MaxSkewSlackLess(const StaState *sta) : } bool -MaxSkewSlackLess::operator()(const MaxSkewCheck *check1, - const MaxSkewCheck *check2) const +MaxSkewSlackLess::operator()(const MaxSkewCheck &check1, + const MaxSkewCheck &check2) const { - Slack slack1 = check1->slack(sta_); - Slack slack2 = check2->slack(sta_); + Slack slack1 = check1.slack(sta_); + Slack slack2 = check2.slack(sta_); return delayLess(slack1, slack2, sta_) || (delayEqual(slack1, slack2) - // Break ties based on constrained pin names. - && sta_->network()->pinLess(check1->clkPin(sta_),check2->clkPin(sta_))); + // Break ties based on constrained pin names. + && sta_->network()->pinLess(check1.clkPin(sta_), check2.clkPin(sta_))); } } // namespace diff --git a/search/CheckMaxSkews.hh b/search/CheckMaxSkews.hh index 4f40ffbb..0c7a5882 100644 --- a/search/CheckMaxSkews.hh +++ b/search/CheckMaxSkews.hh @@ -24,43 +24,26 @@ #pragma once +#include + #include "GraphClass.hh" #include "Delay.hh" #include "StaState.hh" #include "SearchClass.hh" #include "Path.hh" +#include "MinMax.hh" namespace sta { -class MaxSkewCheckVisitor; - -class CheckMaxSkews -{ -public: - explicit CheckMaxSkews(StaState *sta); - ~CheckMaxSkews(); - void clear(); - // All violating max skew checks. - MaxSkewCheckSeq &violations(); - // Max skew check with the least slack. - MaxSkewCheck *minSlackCheck(); - -protected: - void visitMaxSkewChecks(MaxSkewCheckVisitor *visitor); - void visitMaxSkewChecks(Vertex *vertex, - MaxSkewCheckVisitor *visitor); - - MaxSkewCheckSeq checks_; - StaState *sta_; -}; - class MaxSkewCheck { public: + MaxSkewCheck(); MaxSkewCheck(Path *clk_path, - Path *ref_path, - TimingArc *check_arc, - Edge *check_edge); + Path *ref_path, + TimingArc *check_arc, + Edge *check_edge); + bool isNull() const { return clk_path_ == nullptr; } const Path *clkPath() const { return clk_path_; } Pin *clkPin(const StaState *sta) const; const Path *refPath() const { return ref_path_; } @@ -77,12 +60,36 @@ private: Edge *check_edge_; }; +using MaxSkewCheckSeq = std::vector; + +class CheckMaxSkews +{ +public: + CheckMaxSkews(StaState *sta); + ~CheckMaxSkews(); + void clear(); + // Return max skew checks. + // net=null check all nets + MaxSkewCheckSeq &check(const Net *net, + size_t max_count, + bool violators, + const SceneSeq &scenes); + +protected: + void check(Vertex *vertex, + bool violators); + + SceneSet scenes_; + MaxSkewCheckSeq checks_; + StaState *sta_; +}; + class MaxSkewSlackLess { public: - explicit MaxSkewSlackLess(const StaState *sta); - bool operator()(const MaxSkewCheck *check1, - const MaxSkewCheck *check2) const; + MaxSkewSlackLess(const StaState *sta); + bool operator()(const MaxSkewCheck &check1, + const MaxSkewCheck &check2) const; protected: const StaState *sta_; diff --git a/search/CheckMinPeriods.cc b/search/CheckMinPeriods.cc index 06358382..7008d413 100644 --- a/search/CheckMinPeriods.cc +++ b/search/CheckMinPeriods.cc @@ -29,184 +29,134 @@ #include "Sdc.hh" #include "Clock.hh" #include "Graph.hh" -#include "DcalcAnalysisPt.hh" #include "GraphDelayCalc.hh" #include "Search.hh" namespace sta { -// Abstract base class. -class MinPeriodCheckVisitor -{ -public: - MinPeriodCheckVisitor(const Corner *corner); - virtual ~MinPeriodCheckVisitor() {} - virtual void visit(MinPeriodCheck &check, - StaState *sta) = 0; - const Corner *corner() { return corner_; } - -protected: - const Corner *corner_; -}; - -MinPeriodCheckVisitor::MinPeriodCheckVisitor(const Corner *corner) : - corner_(corner) -{ -} - CheckMinPeriods::CheckMinPeriods(StaState *sta) : + heap_(0, MinPeriodSlackLess(sta)), sta_(sta) { } -CheckMinPeriods::~CheckMinPeriods() -{ - checks_.deleteContents(); -} - void CheckMinPeriods::clear() { - checks_.deleteContentsClear(); -} - -class MinPeriodViolatorsVisitor : public MinPeriodCheckVisitor -{ -public: - MinPeriodViolatorsVisitor(const Corner *corner, - MinPeriodCheckSeq &checks); - virtual void visit(MinPeriodCheck &check, - StaState *sta); - -private: - MinPeriodCheckSeq &checks_; -}; - -MinPeriodViolatorsVisitor::MinPeriodViolatorsVisitor(const Corner *corner, - MinPeriodCheckSeq &checks): - MinPeriodCheckVisitor(corner), - checks_(checks) -{ -} - -void -MinPeriodViolatorsVisitor::visit(MinPeriodCheck &check, - StaState *sta) -{ - if (delayLess(check.slack(sta), 0.0, sta)) - checks_.push_back(check.copy()); + checks_.clear(); + heap_.clear(); } MinPeriodCheckSeq & -CheckMinPeriods::violations(const Corner *corner) +CheckMinPeriods::check(const Net *net, + size_t max_count, + bool violators, + const SceneSeq &scenes) { clear(); - MinPeriodViolatorsVisitor visitor(corner, checks_); - visitMinPeriodChecks(&visitor); - sort(checks_, MinPeriodSlackLess(sta_)); + if (!violators) + heap_.setMaxSize(max_count); + + if (net) + checkNet(net, violators, scenes); + else + checkAll(violators, scenes); + + if (violators) + sort(checks_, MinPeriodSlackLess(sta_)); + else + checks_ = heap_.extract(); return checks_; } void -CheckMinPeriods::visitMinPeriodChecks(MinPeriodCheckVisitor *visitor) +CheckMinPeriods::checkNet(const Net *net, + bool violators, + const SceneSeq &scenes) +{ + Graph *graph = sta_->graph(); + NetPinIterator *pin_iter = sta_->network()->pinIterator(net); + while (pin_iter->hasNext()) { + const Pin *pin = pin_iter->next(); + Vertex *vertex = graph->pinLoadVertex(pin); + checkVertex(vertex, violators, scenes); + } + delete pin_iter; +} + +void +CheckMinPeriods::checkAll(bool violators, + const SceneSeq &scenes) { Graph *graph = sta_->graph(); VertexIterator vertex_iter(graph); while (vertex_iter.hasNext()) { Vertex *vertex = vertex_iter.next(); - if (isClkEnd(vertex, graph)) - visitMinPeriodChecks(vertex, visitor); + checkVertex(vertex, violators, scenes); } } void -CheckMinPeriods::visitMinPeriodChecks(Vertex *vertex, - MinPeriodCheckVisitor *visitor) +CheckMinPeriods::checkVertex(Vertex *vertex, + bool violators, + const SceneSeq &scenes) +{ + MinPeriodCheck min_check = check(vertex, scenes); + if (!min_check.isNull()) { + if (violators) { + if (delayLess(min_check.slack(sta_), 0.0, sta_)) + checks_.push_back(min_check); + } + else + heap_.insert(min_check); + } +} + +MinPeriodCheck +CheckMinPeriods::check(Vertex *vertex, + const SceneSeq &scenes) { Search *search = sta_->search(); GraphDelayCalc *graph_dcalc = sta_->graphDelayCalc(); - const Corner *corner = visitor->corner(); + MinPeriodCheck min_slack_check; Pin *pin = vertex->pin(); - float min_period; - bool exists; - graph_dcalc->minPeriod(pin, corner, min_period, exists); - if (exists) { - const ClockSet clks = search->clocks(vertex); - ClockSet::ConstIterator clk_iter(clks); - while (clk_iter.hasNext()) { - Clock *clk = clk_iter.next(); - MinPeriodCheck check(pin, clk, corner); - visitor->visit(check, sta_); + for (const Scene *scene : scenes) { + const Mode *mode = scene->mode(); + if (isClkEnd(vertex, mode)) { + float min_period; + bool exists; + graph_dcalc->minPeriod(pin, scene, min_period, exists); + if (exists) { + const ClockSet clks = search->clocks(vertex, mode); + for (Clock *clk : clks) { + MinPeriodCheck check(pin, clk, scene); + Slack slack = check.slack(sta_); + if (min_slack_check.isNull() + || delayLess(slack, min_slack_check.slack(sta_), sta_)) + min_slack_check = check; + } + } } } -} - -//////////////////////////////////////////////////////////////// - -class MinPeriodSlackVisitor : public MinPeriodCheckVisitor -{ -public: - MinPeriodSlackVisitor(const Corner *corner); - void visit(MinPeriodCheck &check, - StaState *sta) override; - MinPeriodCheck *minSlackCheck(); - -private: - MinPeriodCheck *min_slack_check_; -}; - -MinPeriodSlackVisitor::MinPeriodSlackVisitor(const Corner *corner) : - MinPeriodCheckVisitor(corner), - min_slack_check_(nullptr) -{ -} - -void -MinPeriodSlackVisitor::visit(MinPeriodCheck &check, - StaState *sta) -{ - MinPeriodSlackLess slack_less(sta); - if (min_slack_check_ == nullptr) - min_slack_check_ = check.copy(); - else if (slack_less(&check, min_slack_check_)) { - delete min_slack_check_; - min_slack_check_ = check.copy(); - } -} - -MinPeriodCheck * -MinPeriodSlackVisitor::minSlackCheck() -{ - return min_slack_check_; -} - -MinPeriodCheck * -CheckMinPeriods::minSlackCheck(const Corner *corner) -{ - clear(); - MinPeriodSlackVisitor visitor(corner); - visitMinPeriodChecks(&visitor); - MinPeriodCheck *check = visitor.minSlackCheck(); - // Save check for cleanup. - checks_.push_back(check); - return check; + return min_slack_check; } //////////////////////////////////////////////////////////////// MinPeriodCheck::MinPeriodCheck(Pin *pin, - Clock *clk, - const Corner *corner) : + Clock *clk, + const Scene *scene) : pin_(pin), clk_(clk), - corner_(corner) + scene_(scene) { } -MinPeriodCheck * -MinPeriodCheck::copy() +MinPeriodCheck::MinPeriodCheck() : + pin_(nullptr), + clk_(nullptr), + scene_(nullptr) { - return new MinPeriodCheck(pin_, clk_, corner_); } float @@ -221,7 +171,7 @@ MinPeriodCheck::minPeriod(const StaState *sta) const GraphDelayCalc *graph_dcalc = sta->graphDelayCalc(); float min_period; bool exists; - graph_dcalc->minPeriod(pin_, corner_, min_period, exists); + graph_dcalc->minPeriod(pin_, scene_, min_period, exists); return min_period; } @@ -233,26 +183,26 @@ MinPeriodCheck::slack(const StaState *sta) const //////////////////////////////////////////////////////////////// -MinPeriodSlackLess::MinPeriodSlackLess(StaState *sta) : +MinPeriodSlackLess::MinPeriodSlackLess(const StaState *sta) : sta_(sta) { } bool -MinPeriodSlackLess::operator()(const MinPeriodCheck *check1, - const MinPeriodCheck *check2) const +MinPeriodSlackLess::operator()(const MinPeriodCheck &check1, + const MinPeriodCheck &check2) const { - Slack slack1 = check1->slack(sta_); - Slack slack2 = check2->slack(sta_); - const Pin *pin1 = check1->pin(); - const Pin *pin2 = check2->pin(); + Slack slack1 = check1.slack(sta_); + Slack slack2 = check2.slack(sta_); + const Pin *pin1 = check1.pin(); + const Pin *pin2 = check2.pin(); return delayLess(slack1, slack2, sta_) // Break ties based on pin and clock names. || (delayEqual(slack1, slack2) - && (sta_->network()->pinLess(pin1, pin2) - || (pin1 == pin2 - && ClockNameLess()(check1->clk(), - check2->clk())))); + && (sta_->network()->pinLess(pin1, pin2) + || (pin1 == pin2 + && ClockNameLess()(check1.clk(), + check2.clk())))); } } // namespace diff --git a/search/CheckMinPeriods.hh b/search/CheckMinPeriods.hh index bcba3218..a8e0b918 100644 --- a/search/CheckMinPeriods.hh +++ b/search/CheckMinPeriods.hh @@ -30,37 +30,31 @@ #include "SdcClass.hh" #include "SearchClass.hh" #include "StaState.hh" +#include "BoundedHeap.hh" namespace sta { -class MinPeriodCheckVisitor; - -class CheckMinPeriods +class MinPeriodSlackLess { public: - CheckMinPeriods(StaState *sta); - ~CheckMinPeriods(); - void clear(); - MinPeriodCheckSeq &violations(const Corner *corner); - // Min period check with the least slack. - MinPeriodCheck *minSlackCheck(const Corner *corner); + MinPeriodSlackLess(const StaState *sta); + bool operator()(const MinPeriodCheck &check1, + const MinPeriodCheck &check2) const; -protected: - void visitMinPeriodChecks(MinPeriodCheckVisitor *visitor); - void visitMinPeriodChecks(Vertex *vertex, - MinPeriodCheckVisitor *visitor); - - MinPeriodCheckSeq checks_; - StaState *sta_; +private: + const StaState *sta_; }; +using MinPeriodHeap = BoundedHeap; + class MinPeriodCheck { public: + MinPeriodCheck(); MinPeriodCheck(Pin *pin, - Clock *clk, - const Corner *corner); - MinPeriodCheck *copy(); + Clock *clk, + const Scene *scene); + bool isNull() { return pin_ == nullptr; } Pin *pin() const { return pin_; } Clock *clk() const { return clk_; } float period() const; @@ -70,18 +64,36 @@ public: private: Pin *pin_; Clock *clk_; - const Corner *corner_; + const Scene *scene_; }; -class MinPeriodSlackLess +using MinPeriodCheckSeq = std::vector; + +class CheckMinPeriods { public: - MinPeriodSlackLess(StaState *sta); - bool operator()(const MinPeriodCheck *check1, - const MinPeriodCheck *check2) const; + CheckMinPeriods(StaState *sta); + void clear(); + MinPeriodCheckSeq &check(const Net *net, + size_t max_count, + bool violators, + const SceneSeq &scenes); -private: - const StaState *sta_; +protected: + void checkNet(const Net *net, + bool violators, + const SceneSeq &scenes); + void checkAll(bool violators, + const SceneSeq &scenes); + void checkVertex(Vertex *vertex, + bool violators, + const SceneSeq &scenes); + MinPeriodCheck check(Vertex *vertex, + const SceneSeq &scenes); + + MinPeriodCheckSeq checks_; + MinPeriodHeap heap_; + StaState *sta_; }; } // namespace diff --git a/search/CheckMinPulseWidths.cc b/search/CheckMinPulseWidths.cc index 395327ea..b13de4e3 100644 --- a/search/CheckMinPulseWidths.cc +++ b/search/CheckMinPulseWidths.cc @@ -24,6 +24,7 @@ #include "CheckMinPulseWidths.hh" +#include "ContainerHelpers.hh" #include "Debug.hh" #include "TimingRole.hh" #include "Liberty.hh" @@ -31,13 +32,11 @@ #include "Graph.hh" #include "Clock.hh" #include "Sdc.hh" -#include "DcalcAnalysisPt.hh" #include "GraphDelayCalc.hh" #include "ClkInfo.hh" #include "Tag.hh" #include "Path.hh" -#include "Corner.hh" -#include "PathAnalysisPt.hh" +#include "Scene.hh" #include "SearchPred.hh" #include "PathEnd.hh" #include "Search.hh" @@ -47,238 +46,111 @@ namespace sta { static void minPulseWidth(const Path *path, - const StaState *sta, - // Return values. - float &min_width, - bool &exists); - -// Abstract base class. -class MinPulseWidthCheckVisitor -{ -public: - MinPulseWidthCheckVisitor() {} - virtual ~MinPulseWidthCheckVisitor() {} - virtual void visit(MinPulseWidthCheck &check, - const StaState *sta) = 0; -}; + const StaState *sta, + // Return values. + float &min_width, + bool &exists); CheckMinPulseWidths::CheckMinPulseWidths(StaState *sta) : + heap_(0, MinPulseWidthSlackLess(sta)), sta_(sta) { } -CheckMinPulseWidths::~CheckMinPulseWidths() -{ - checks_.deleteContents(); -} - void CheckMinPulseWidths::clear() { - checks_.deleteContentsClear(); -} - -//////////////////////////////////////////////////////////////// - -class MinPulseWidthChecksVisitor : public MinPulseWidthCheckVisitor -{ -public: - explicit MinPulseWidthChecksVisitor(const Corner *corner, - MinPulseWidthCheckSeq &checks); - virtual void visit(MinPulseWidthCheck &check, - const StaState *sta); - -private: - const Corner *corner_; - MinPulseWidthCheckSeq &checks_; -}; - -MinPulseWidthChecksVisitor:: -MinPulseWidthChecksVisitor(const Corner *corner, - MinPulseWidthCheckSeq &checks) : - corner_(corner), - checks_(checks) -{ -} - -void -MinPulseWidthChecksVisitor::visit(MinPulseWidthCheck &check, - const StaState *sta) -{ - if (corner_ == nullptr - || check.corner(sta) == corner_) { - MinPulseWidthCheck *copy = new MinPulseWidthCheck(check.openPath()); - checks_.push_back(copy); - } + checks_.clear(); + heap_.clear(); } MinPulseWidthCheckSeq & -CheckMinPulseWidths::check(const Corner *corner) +CheckMinPulseWidths::check(const Net *net, + size_t max_count, + bool violators, + const SceneSeq &scenes) { clear(); - MinPulseWidthChecksVisitor visitor(corner, checks_); - visitMinPulseWidthChecks(&visitor); - sort(checks_, MinPulseWidthSlackLess(sta_)); + if (!violators) + heap_.setMaxSize(max_count); + + if (net) + checkNet(net, violators, scenes); + else + checkAll(violators, scenes); + + if (violators) + sort(checks_, MinPulseWidthSlackLess(sta_)); + else + checks_ = heap_.extract(); return checks_; } -MinPulseWidthCheckSeq & -CheckMinPulseWidths::check(PinSeq *pins, - const Corner *corner) +void +CheckMinPulseWidths::checkNet(const Net *net, + bool violators, + const SceneSeq &scenes) { - clear(); Graph *graph = sta_->graph(); - MinPulseWidthChecksVisitor visitor(corner, checks_); - PinSeq::Iterator pin_iter(pins); - while (pin_iter.hasNext()) { - const Pin *pin = pin_iter.next(); + NetPinIterator *pin_iter = sta_->network()->pinIterator(net); + while (pin_iter->hasNext()) { + const Pin *pin = pin_iter->next(); Vertex *vertex = graph->pinLoadVertex(pin); - visitMinPulseWidthChecks(vertex, &visitor); + checkVertex(vertex, violators, scenes); } - sort(checks_, MinPulseWidthSlackLess(sta_)); - return checks_; -} - -//////////////////////////////////////////////////////////////// - -class MinPulseWidthViolatorsVisitor : public MinPulseWidthCheckVisitor -{ -public: - explicit MinPulseWidthViolatorsVisitor(const Corner *corner, - MinPulseWidthCheckSeq &checks); - virtual void visit(MinPulseWidthCheck &check, - const StaState *sta); - -private: - const Corner *corner_; - MinPulseWidthCheckSeq &checks_; -}; - -MinPulseWidthViolatorsVisitor:: -MinPulseWidthViolatorsVisitor(const Corner *corner, - MinPulseWidthCheckSeq &checks) : - corner_(corner), - checks_(checks) -{ + delete pin_iter; } void -MinPulseWidthViolatorsVisitor::visit(MinPulseWidthCheck &check, - const StaState *sta) -{ - if (delayLess(check.slack(sta), 0.0, sta) - && (corner_ == nullptr - || check.corner(sta) == corner_)) { - MinPulseWidthCheck *copy = new MinPulseWidthCheck(check.openPath()); - checks_.push_back(copy); - } -} - -MinPulseWidthCheckSeq & -CheckMinPulseWidths::violations(const Corner *corner) -{ - clear(); - MinPulseWidthViolatorsVisitor visitor(corner, checks_); - visitMinPulseWidthChecks(&visitor); - sort(checks_, MinPulseWidthSlackLess(sta_)); - return checks_; -} - -//////////////////////////////////////////////////////////////// - -class MinPulseWidthSlackVisitor : public MinPulseWidthCheckVisitor -{ -public: - MinPulseWidthSlackVisitor(const Corner *corner); - virtual void visit(MinPulseWidthCheck &check, - const StaState *sta); - MinPulseWidthCheck *minSlackCheck(); - -private: - const Corner *corner_; - MinPulseWidthCheck *min_slack_check_; -}; - -MinPulseWidthSlackVisitor::MinPulseWidthSlackVisitor(const Corner *corner) : - corner_(corner), - min_slack_check_(nullptr) -{ -} - -void -MinPulseWidthSlackVisitor::visit(MinPulseWidthCheck &check, - const StaState *sta) -{ - MinPulseWidthSlackLess slack_less(sta); - if (corner_ == nullptr - || check.corner(sta) == corner_) { - if (min_slack_check_ == nullptr) - min_slack_check_ = check.copy(); - else if (slack_less(&check, min_slack_check_)) { - delete min_slack_check_; - min_slack_check_ = check.copy(); - } - } -} - -MinPulseWidthCheck * -MinPulseWidthSlackVisitor::minSlackCheck() -{ - return min_slack_check_; -} - -MinPulseWidthCheck * -CheckMinPulseWidths::minSlackCheck(const Corner *corner) -{ - clear(); - MinPulseWidthSlackVisitor visitor(corner); - visitMinPulseWidthChecks(&visitor); - MinPulseWidthCheck *check = visitor.minSlackCheck(); - // Save check for cleanup. - checks_.push_back(check); - return check; -} - -void -CheckMinPulseWidths:: -visitMinPulseWidthChecks(MinPulseWidthCheckVisitor *visitor) +CheckMinPulseWidths::checkAll(bool violators, + const SceneSeq &scenes) { Graph *graph = sta_->graph(); - Debug *debug = sta_->debug(); VertexIterator vertex_iter(graph); while (vertex_iter.hasNext()) { Vertex *vertex = vertex_iter.next(); - if (isClkEnd(vertex, graph)) { - debugPrint(debug, "mpw", 1, "check mpw %s", - vertex->to_string(sta_).c_str()); - visitMinPulseWidthChecks(vertex, visitor); - } + checkVertex(vertex, violators, scenes); } } void -CheckMinPulseWidths:: -visitMinPulseWidthChecks(Vertex *vertex, - MinPulseWidthCheckVisitor *visitor) +CheckMinPulseWidths::checkVertex(Vertex *vertex, + bool violators, + const SceneSeq &scenes) { Search *search = sta_->search(); + Debug *debug = sta_->debug(); const MinMax *min_max = MinMax::max(); + SceneSet scene_set = Scene::sceneSet(scenes); VertexPathIterator path_iter(vertex, search); while (path_iter.hasNext()) { Path *path = path_iter.next(); - if (path->isClock(search) - && !path->tag(sta_)->clkInfo()->isGenClkSrcPath()) { - if (path->minMax(sta_) == min_max) { - float min_width; - bool exists; - minPulseWidth(path, sta_, min_width, exists); - if (exists) { - MinPulseWidthCheck check(path); - Path *close_path = check.closePath(sta_); - // Don't bother visiting if nobody is home. - if (close_path) - visitor->visit(check, sta_); - } + Vertex *path_vertex = path->vertex(sta_); + const Mode *mode = path->mode(sta_); + if (isClkEnd(path_vertex, mode) + && path->isClock(search) + && !path->tag(sta_)->clkInfo()->isGenClkSrcPath() + && scene_set.find(path->scene(sta_)) != scene_set.end() + && path->minMax(sta_) == min_max) { + float min_width; + bool exists; + minPulseWidth(path, sta_, min_width, exists); + if (exists) { + MinPulseWidthCheck check(path); + Path *close_path = check.closePath(sta_); + // Don't bother visiting if nobody is home. + if (close_path) { + debugPrint(debug, "mpw", 2, "%s %s %s", + path_vertex->to_string(sta_).c_str(), + path->transition(sta_) == RiseFall::rise() ? "(high)" : "(low)", + delayAsString(check.slack(sta_), sta_)); + if (violators) { + if (delayLess(check.slack(sta_), 0.0, sta_)) + checks_.push_back(check); + } + else + heap_.insert(check); + } } } } @@ -296,10 +168,13 @@ MinPulseWidthCheck::MinPulseWidthCheck(Path *open_path) : { } -MinPulseWidthCheck * -MinPulseWidthCheck::copy() +std::string +MinPulseWidthCheck::to_string(const StaState *sta) { - return new MinPulseWidthCheck(open_path_); + std::string result = sta->network()->pathName(pin(sta)); + result += " "; + result += (openTransition(sta) == RiseFall::rise()) ? "(high)" : "(low)"; + return result; } Pin * @@ -317,37 +192,39 @@ MinPulseWidthCheck::openTransition(const StaState *sta) const Path * MinPulseWidthCheck::closePath(const StaState *sta) const { - PathAnalysisPt *open_ap = open_path_->pathAnalysisPt(sta); - PathAnalysisPt *close_ap = open_ap->tgtClkAnalysisPt(); + Scene *scene = open_path_->scene(sta); + const MinMax *close_min_max = open_path_->tgtClkMinMax(sta); const RiseFall *open_rf = open_path_->transition(sta); const RiseFall *close_rf = open_rf->opposite(); Tag *open_tag = open_path_->tag(sta); const ClkInfo *open_clk_info = open_tag->clkInfo(); - const ClkInfo close_clk_info(open_clk_info->clkEdge()->opposite(), - open_clk_info->clkSrc(), - open_clk_info->isPropagated(), - open_clk_info->genClkSrc(), - open_clk_info->isGenClkSrcPath(), - open_clk_info->pulseClkSense(), - delay_zero, 0.0, nullptr, - open_clk_info->pathAPIndex(), - open_clk_info->crprClkPath(sta), - sta); - Tag close_tag(0, - close_rf->index(), - close_ap->index(), - &close_clk_info, - open_tag->isClock(), - open_tag->inputDelay(), - open_tag->isSegmentStart(), - open_tag->states(), - false, sta); + const ClkInfo close_clk_info(scene, + open_clk_info->clkEdge()->opposite(), + open_clk_info->clkSrc(), + open_clk_info->isPropagated(), + open_clk_info->genClkSrc(), + open_clk_info->isGenClkSrcPath(), + open_clk_info->pulseClkSense(), + delay_zero, 0.0, nullptr, + open_clk_info->minMax(), + open_clk_info->crprClkPath(sta), + sta); + Tag close_tag(scene, + 0, + close_rf, + close_min_max, + &close_clk_info, + open_tag->isClock(), + open_tag->inputDelay(), + open_tag->isSegmentStart(), + open_tag->states(), + false); debugPrint(sta->debug(), "mpw", 3, " open %s", open_tag->to_string(sta).c_str()); debugPrint(sta->debug(), "mpw", 3, " close %s", close_tag.to_string(sta).c_str()); - VertexPathIterator close_iter(open_path_->vertex(sta), close_rf, - close_ap, sta); + VertexPathIterator close_iter(open_path_->vertex(sta), scene, close_min_max, + close_rf, sta); while (close_iter.hasNext()) { Path *close_path = close_iter.next(); if (Tag::matchNoPathAp(close_path->tag(sta), &close_tag)) { @@ -434,27 +311,26 @@ MinPulseWidthCheck::minWidth(const StaState *sta) const // min_pulse_width timing group static void minPulseWidth(const Path *path, - const StaState *sta, - // Return values. - float &min_width, - bool &exists) + const StaState *sta, + // Return values. + float &min_width, + bool &exists) { Pin *pin = path->pin(sta); const Clock *clk = path->clock(sta); const RiseFall *rf = path->transition(sta); - Sdc *sdc = sta->sdc(); + const Sdc *sdc = path->sdc(sta); // set_min_pulse_width command. sdc->minPulseWidth(pin, clk, rf, min_width, exists); if (!exists) { - const PathAnalysisPt *path_ap = path->pathAnalysisPt(sta); - const DcalcAnalysisPt *dcalc_ap = path_ap->dcalcAnalysisPt(); + DcalcAPIndex dcalc_ap = path->dcalcAnalysisPtIndex(sta); Vertex *vertex = path->vertex(sta); Graph *graph = sta->graph(); Edge *edge; TimingArc *arc; graph->minPulseWidthArc(vertex, rf, edge, arc); if (edge) { - min_width = delayAsFloat(graph->arcDelay(edge, arc, dcalc_ap->index())); + min_width = delayAsFloat(graph->arcDelay(edge, arc, dcalc_ap)); exists = true; } } @@ -477,10 +353,10 @@ MinPulseWidthCheck::slack(const StaState *sta) const return width(sta) - minWidth(sta); } -Corner * -MinPulseWidthCheck::corner(const StaState *sta) const +Scene * +MinPulseWidthCheck::scene(const StaState *sta) const { - return open_path_->pathAnalysisPt(sta)->corner(); + return open_path_->scene(sta); } //////////////////////////////////////////////////////////////// @@ -491,20 +367,20 @@ MinPulseWidthSlackLess::MinPulseWidthSlackLess(const StaState *sta) : } bool -MinPulseWidthSlackLess::operator()(const MinPulseWidthCheck *check1, - const MinPulseWidthCheck *check2) const +MinPulseWidthSlackLess::operator()(const MinPulseWidthCheck &check1, + const MinPulseWidthCheck &check2) const { - Slack slack1 = check1->slack(sta_); - Slack slack2 = check2->slack(sta_); - const Pin *pin1 = check1->pin(sta_); - const Pin *pin2 = check2->pin(sta_); + Slack slack1 = check1.slack(sta_); + Slack slack2 = check2.slack(sta_); + const Pin *pin1 = check1.pin(sta_); + const Pin *pin2 = check2.pin(sta_); return delayLess(slack1, slack2, sta_) || (delayEqual(slack1, slack2) - // Break ties for the sake of regression stability. - && (sta_->network()->pinLess(pin1, pin2) - || (pin1 == pin2 - && check1->openPath()->rfIndex(sta_) - < check2->openPath()->rfIndex(sta_)))); + // Break ties for the sake of regression stability. + && (sta_->network()->pinLess(pin1, pin2) + || (pin1 == pin2 + && check1.openPath()->rfIndex(sta_) + < check2.openPath()->rfIndex(sta_)))); } } // namespace diff --git a/search/CheckMinPulseWidths.hh b/search/CheckMinPulseWidths.hh index d250cc20..0acda273 100644 --- a/search/CheckMinPulseWidths.hh +++ b/search/CheckMinPulseWidths.hh @@ -24,59 +24,45 @@ #pragma once +#include +#include +#include + #include "SdcClass.hh" #include "SearchClass.hh" #include "StaState.hh" #include "Path.hh" +#include "BoundedHeap.hh" namespace sta { class RiseFall; -class MinPulseWidthCheck; -class MinPulseWidthCheckVisitor; -class CheckMinPulseWidths +class MinPulseWidthSlackLess { public: - CheckMinPulseWidths(StaState *sta); - ~CheckMinPulseWidths(); - void clear(); - // Min pulse width checks for pins. - // corner=nullptr checks all corners. - MinPulseWidthCheckSeq &check(PinSeq *pins, - const Corner *corner); - // All min pulse width checks. - // corner=nullptr checks all corners. - MinPulseWidthCheckSeq &check(const Corner *corner); - // All violating min pulse width checks. - // corner=nullptr checks all corners. - MinPulseWidthCheckSeq &violations(const Corner *corner); - // Min pulse width check with the least slack. - // corner=nullptr checks all corners. - MinPulseWidthCheck *minSlackCheck(const Corner *corner); + MinPulseWidthSlackLess(const StaState *sta); + bool operator()(const MinPulseWidthCheck &check1, + const MinPulseWidthCheck &check2) const; -protected: - void visitMinPulseWidthChecks(MinPulseWidthCheckVisitor *visitor); - void visitMinPulseWidthChecks(Vertex *vertex, - MinPulseWidthCheckVisitor *visitor); - - MinPulseWidthCheckSeq checks_; - StaState *sta_; +private: + const StaState *sta_; }; class MinPulseWidthCheck { public: - explicit MinPulseWidthCheck(); + MinPulseWidthCheck(); MinPulseWidthCheck(Path *open_path); - MinPulseWidthCheck *copy(); + std::string to_string(const StaState *sta); + bool isNull() const { return open_path_ == nullptr; } Pin *pin(const StaState *sta) const; const RiseFall *openTransition(const StaState *sta) const; Arrival width(const StaState *sta) const; float minWidth(const StaState *sta) const; Slack slack(const StaState *sta) const; Path *openPath() { return open_path_; } - Corner *corner(const StaState *sta) const; + Scene *scene(const StaState *sta) const; const Path *openPath() const { return open_path_; } Arrival openArrival(const StaState *sta) const; Path *closePath(const StaState *sta) const; @@ -93,15 +79,32 @@ protected: Path *open_path_; }; -class MinPulseWidthSlackLess +using MinPulseWidthCheckSeq = std::vector; +using MinPulseWidthCheckHeap = BoundedHeap; + +class CheckMinPulseWidths { public: - MinPulseWidthSlackLess(const StaState *sta); - bool operator()(const MinPulseWidthCheck *check1, - const MinPulseWidthCheck *check2) const; + CheckMinPulseWidths(StaState *sta); + void clear(); + MinPulseWidthCheckSeq &check(const Net *net, + size_t max_count, + bool violators, + const SceneSeq &scenes); -private: - const StaState *sta_; +protected: + void checkNet(const Net *net, + bool violators, + const SceneSeq &scenes); + void checkAll(bool violators, + const SceneSeq &scenes); + void checkVertex(Vertex *vertex, + bool violators, + const SceneSeq &scenes); + + MinPulseWidthCheckSeq checks_; + MinPulseWidthCheckHeap heap_; + StaState *sta_; }; } // namespace diff --git a/search/CheckSlewLimits.cc b/search/CheckSlewLimits.cc deleted file mode 100644 index 2cc392ca..00000000 --- a/search/CheckSlewLimits.cc +++ /dev/null @@ -1,422 +0,0 @@ -// OpenSTA, Static Timing Analyzer -// Copyright (c) 2025, Parallax Software, Inc. -// -// This program is free software: you can redistribute it and/or modify -// it under the terms of the GNU General Public License as published by -// the Free Software Foundation, either version 3 of the License, or -// (at your option) any later version. -// -// This program is distributed in the hope that it will be useful, -// but WITHOUT ANY WARRANTY; without even the implied warranty of -// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -// GNU General Public License for more details. -// -// You should have received a copy of the GNU General Public License -// along with this program. If not, see . -// -// The origin of this software must not be misrepresented; you must not -// claim that you wrote the original software. -// -// Altered source versions must be plainly marked as such, and must not be -// misrepresented as being the original software. -// -// This notice may not be removed or altered from any source distribution. - -#include "CheckSlewLimits.hh" - -#include "Fuzzy.hh" -#include "Liberty.hh" -#include "Network.hh" -#include "Sdc.hh" -#include "InputDrive.hh" -#include "Graph.hh" -#include "DcalcAnalysisPt.hh" -#include "GraphDelayCalc.hh" -#include "StaState.hh" -#include "Corner.hh" -#include "Path.hh" -#include "PortDirection.hh" -#include "Search.hh" -#include "ClkNetwork.hh" - -namespace sta { - -class PinSlewLimitSlackLess -{ -public: - PinSlewLimitSlackLess(const Corner *corner, - const MinMax *min_max, - CheckSlewLimits *check_slew_limit, - const StaState *sta); - bool operator()(const Pin *pin1, - const Pin *pin2) const; - -private: - const Corner *corner_; - const MinMax *min_max_; - CheckSlewLimits *check_slew_limit_; - const StaState *sta_; - -}; - -PinSlewLimitSlackLess::PinSlewLimitSlackLess(const Corner *corner, - const MinMax *min_max, - CheckSlewLimits *check_slew_limit, - const StaState *sta) : - corner_(corner), - min_max_(min_max), - check_slew_limit_(check_slew_limit), - sta_(sta) -{ -} - -bool -PinSlewLimitSlackLess::operator()(const Pin *pin1, - const Pin *pin2) const -{ - const Corner *corner1, *corner2; - const RiseFall *rf1, *rf2; - Slew slew1, slew2; - float limit1, limit2, slack1, slack2; - check_slew_limit_->checkSlew(pin1, corner_, min_max_, true, - corner1, rf1, slew1, limit1, slack1); - check_slew_limit_->checkSlew(pin2, corner_, min_max_, true, - corner2, rf2, slew2, limit2, slack2); - return fuzzyLess(slack1, slack2) - || (fuzzyEqual(slack1, slack2) - // Break ties for the sake of regression stability. - && sta_->network()->pinLess(pin1, pin2)); -} - -//////////////////////////////////////////////////////////////// - -CheckSlewLimits::CheckSlewLimits(const StaState *sta) : - sta_(sta) -{ -} - -void -CheckSlewLimits::checkSlewLimits(const Pin *pin, - bool violators, - const Corner *corner, - const MinMax *min_max, - PinSeq &slew_pins, - float &min_slack) -{ - const Corner *corner1; - const RiseFall *rf; - Slew slew; - float limit, slack; - checkSlew(pin, corner, min_max, true, corner1, rf, slew, limit, slack); - if (!fuzzyInf(slack)) { - if (violators) { - if (slack < 0.0) - slew_pins.push_back(pin); - } - else { - if (slew_pins.empty() - || slack < min_slack) { - slew_pins.push_back(pin); - min_slack = slack; - } - } - } -} - -void -CheckSlewLimits::checkSlew(const Pin *pin, - const Corner *corner, - const MinMax *min_max, - bool check_clks, - // Return values. - const Corner *&corner1, - const RiseFall *&rf1, - Slew &slew1, - float &limit1, - float &slack1) const -{ - corner1 = nullptr; - rf1 = nullptr; - slew1 = 0.0; - limit1 = 0.0; - slack1 = MinMax::min()->initValue(); - - Vertex *vertex, *bidirect_drvr_vertex; - sta_->graph()->pinVertices(pin, vertex, bidirect_drvr_vertex); - if (vertex) - checkSlew1(pin, vertex, corner, min_max, check_clks, - corner1, rf1, slew1, limit1, slack1); - if (bidirect_drvr_vertex) - checkSlew1(pin, bidirect_drvr_vertex, corner, min_max, check_clks, - corner1, rf1, slew1, limit1, slack1); -} - -void -CheckSlewLimits::checkSlew1(const Pin *pin, - const Vertex *vertex, - const Corner *corner, - const MinMax *min_max, - bool check_clks, - // Return values. - const Corner *&corner1, - const RiseFall *&rf1, - Slew &slew1, - float &limit1, - float &slack1) const -{ - if (!vertex->isDisabledConstraint() - && !vertex->isConstant() - && !sta_->clkNetwork()->isIdealClock(pin)) { - ClockSet clks; - if (check_clks) - clks = clockDomains(vertex); - if (corner) - checkSlew2(pin, vertex, corner, min_max, clks, - corner1, rf1, slew1, limit1, slack1); - else { - for (auto corner : *sta_->corners()) { - checkSlew2(pin, vertex, corner, min_max, clks, - corner1, rf1, slew1, limit1, slack1); - } - } - } -} - -void -CheckSlewLimits::checkSlew2(const Pin *pin, - const Vertex *vertex, - const Corner *corner, - const MinMax *min_max, - const ClockSet &clks, - // Return values. - const Corner *&corner1, - const RiseFall *&rf1, - Slew &slew1, - float &limit1, - float &slack1) const -{ - for (const RiseFall *rf : RiseFall::range()) { - float limit; - bool exists; - findLimit(pin, corner, rf, min_max, clks, - limit, exists); - if (exists) { - checkSlew3(vertex, corner, rf, min_max, limit, - corner1, rf1, slew1, slack1, limit1); - } - } -} - -void -CheckSlewLimits::checkSlew3(const Vertex *vertex, - const Corner *corner, - const RiseFall *rf, - const MinMax *min_max, - float limit, - // Return values. - const Corner *&corner1, - const RiseFall *&rf1, - Slew &slew1, - float &slack1, - float &limit1) const -{ - const DcalcAnalysisPt *dcalc_ap = corner->findDcalcAnalysisPt(min_max); - Slew slew = sta_->graph()->slew(vertex, rf, dcalc_ap->index()); - float slew2 = delayAsFloat(slew); - float slack = (min_max == MinMax::max()) - ? limit - slew2 : slew2 - limit; - if (corner1 == nullptr - || (slack < slack1 - // Break ties for the sake of regression stability. - || (fuzzyEqual(slack, slack1) - && rf->index() < rf1->index()))) { - corner1 = corner; - rf1 = rf; - slew1 = slew; - slack1 = slack; - limit1 = limit; - } -} - -// Return the tightest limit. -void -CheckSlewLimits::findLimit(const Pin *pin, - const Corner *corner, - const RiseFall *rf, - const MinMax *min_max, - const ClockSet &clks, - // Return values. - float &limit, - bool &exists) const -{ - const Network *network = sta_->network(); - Sdc *sdc = sta_->sdc(); - LibertyPort *port = network->libertyPort(pin); - findLimit(port, corner, min_max, - limit, exists); - - float limit1; - bool exists1; - if (!clks.empty()) { - // Look for clock slew limits. - bool is_clk = sta_->clkNetwork()->isIdealClock(pin); - for (Clock *clk : clks) { - PathClkOrData clk_data = is_clk ? PathClkOrData::clk : PathClkOrData::data; - sdc->slewLimit(clk, rf, clk_data, min_max, - limit1, exists1); - if (exists1 - && (!exists - || min_max->compare(limit, limit1))) { - limit = limit1; - exists = true; - } - } - } - - if (network->isTopLevelPort(pin)) { - Port *port = network->port(pin); - sdc->slewLimit(port, min_max, limit1, exists1); - if (exists1 - && (!exists - || min_max->compare(limit, limit1))) { - limit = limit1; - exists = true; - } - InputDrive *drive = sdc->findInputDrive(port); - if (drive) { - for (auto rf : RiseFall::range()) { - const LibertyCell *cell; - const LibertyPort *from_port; - float *from_slews; - const LibertyPort *to_port; - drive->driveCell(rf, min_max, cell, from_port, from_slews, to_port); - if (to_port) { - const LibertyPort *corner_port = to_port->cornerPort(corner, min_max); - corner_port->slewLimit(min_max, limit1, exists1); - if (!exists1 - && corner_port->direction()->isAnyOutput() - && min_max == MinMax::max()) - corner_port->libertyLibrary()->defaultMaxSlew(limit1, exists1); - if (exists1 - && (!exists - || min_max->compare(limit, limit1))) { - limit = limit1; - exists = true; - } - } - } - } - } -} - -void -CheckSlewLimits::findLimit(const LibertyPort *port, - const Corner *corner, - const MinMax *min_max, - // Return values. - float &limit, - bool &exists) const -{ - limit = INF; - exists = false; - - const Network *network = sta_->network(); - Sdc *sdc = sta_->sdc(); - float limit1; - bool exists1; - - // Default to top ("design") limit. - Cell *top_cell = network->cell(network->topInstance()); - sdc->slewLimit(top_cell, min_max, - limit1, exists1); - if (exists1) { - limit = limit1; - exists = true; - } - - if (port) { - const LibertyPort *corner_port = port->cornerPort(corner, min_max); - corner_port->slewLimit(min_max, limit1, exists1); - if (!exists1 - // default_max_transition only applies to outputs. - && corner_port->direction()->isAnyOutput() - && min_max == MinMax::max()) - corner_port->libertyLibrary()->defaultMaxSlew(limit1, exists1); - if (exists1 - && (!exists - || min_max->compare(limit, limit1))) { - limit = limit1; - exists = true; - } - } -} - -ClockSet -CheckSlewLimits::clockDomains(const Vertex *vertex) const -{ - ClockSet clks; - VertexPathIterator path_iter(const_cast(vertex), sta_); - while (path_iter.hasNext()) { - Path *path = path_iter.next(); - const Clock *clk = path->clock(sta_); - if (clk) - clks.insert(const_cast(clk)); - } - return clks; -} - -//////////////////////////////////////////////////////////////// - -PinSeq -CheckSlewLimits::checkSlewLimits(const Net *net, - bool violators, - const Corner *corner, - const MinMax *min_max) -{ - const Network *network = sta_->network(); - PinSeq slew_pins; - float min_slack = MinMax::min()->initValue(); - if (net) { - NetPinIterator *pin_iter = network->pinIterator(net); - while (pin_iter->hasNext()) { - const Pin *pin = pin_iter->next(); - checkSlewLimits(pin, violators, corner, min_max, slew_pins, min_slack); - } - delete pin_iter; - } - else { - LeafInstanceIterator *inst_iter = network->leafInstanceIterator(); - while (inst_iter->hasNext()) { - const Instance *inst = inst_iter->next(); - checkSlewLimits(inst, violators,corner, min_max, slew_pins, min_slack); - } - delete inst_iter; - // Check top level ports. - checkSlewLimits(network->topInstance(), violators, corner, min_max, - slew_pins, min_slack); - } - sort(slew_pins, PinSlewLimitSlackLess(corner, min_max, this, sta_)); - // Keep the min slack pin unless all violators or net pins. - if (!slew_pins.empty() && !violators && net == nullptr) - slew_pins.resize(1); - return slew_pins; -} - -void -CheckSlewLimits::checkSlewLimits(const Instance *inst, - bool violators, - const Corner *corner, - const MinMax *min_max, - PinSeq &slew_pins, - float &min_slack) -{ - const Network *network = sta_->network(); - InstancePinIterator *pin_iter = network->pinIterator(inst); - while (pin_iter->hasNext()) { - Pin *pin = pin_iter->next(); - checkSlewLimits(pin, violators, corner, min_max, slew_pins, min_slack); - } - delete pin_iter; -} - -} // namespace diff --git a/search/CheckSlewLimits.hh b/search/CheckSlewLimits.hh deleted file mode 100644 index ba907103..00000000 --- a/search/CheckSlewLimits.hh +++ /dev/null @@ -1,129 +0,0 @@ -// OpenSTA, Static Timing Analyzer -// Copyright (c) 2025, Parallax Software, Inc. -// -// This program is free software: you can redistribute it and/or modify -// it under the terms of the GNU General Public License as published by -// the Free Software Foundation, either version 3 of the License, or -// (at your option) any later version. -// -// This program is distributed in the hope that it will be useful, -// but WITHOUT ANY WARRANTY; without even the implied warranty of -// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -// GNU General Public License for more details. -// -// You should have received a copy of the GNU General Public License -// along with this program. If not, see . -// -// The origin of this software must not be misrepresented; you must not -// claim that you wrote the original software. -// -// Altered source versions must be plainly marked as such, and must not be -// misrepresented as being the original software. -// -// This notice may not be removed or altered from any source distribution. - -#pragma once - -#include "MinMax.hh" -#include "Transition.hh" -#include "NetworkClass.hh" -#include "GraphClass.hh" -#include "Delay.hh" -#include "SdcClass.hh" - -namespace sta { - -class StaState; -class DcalcAnalysisPt; -class Corner; - -class CheckSlewLimits -{ -public: - CheckSlewLimits(const StaState *sta); - // Return pins with the min/max slew limit slack. - // net=null check all nets - // corner=nullptr checks all corners. - PinSeq checkSlewLimits(const Net *net, - bool violators, - const Corner *corner, - const MinMax *min_max); - // corner=nullptr checks all corners. - void checkSlew(const Pin *pin, - const Corner *corner, - const MinMax *min_max, - bool check_clks, - // Return values. - // Corner is nullptr for no slew limit. - const Corner *&corner1, - const RiseFall *&rf, - Slew &slew, - float &limit, - float &slack) const; - void findLimit(const LibertyPort *port, - const Corner *corner, - const MinMax *min_max, - // Return values. - float &limit, - bool &exists) const; - -protected: - void checkSlew1(const Pin *pin, - const Vertex *vertex, - const Corner *corner, - const MinMax *min_max, - bool check_clks, - // Return values. - const Corner *&corner1, - const RiseFall *&rf1, - Slew &slew1, - float &limit1, - float &slack1) const; - void checkSlew2(const Pin *pin, - const Vertex *vertex, - const Corner *corner, - const MinMax *min_max, - const ClockSet &clks, - // Return values. - const Corner *&corner1, - const RiseFall *&rf1, - Slew &slew1, - float &limit1, - float &slack1) const; - void checkSlew3(const Vertex *vertex, - const Corner *corner1, - const RiseFall *rf1, - const MinMax *min_max, - float limit1, - // Return values. - const Corner *&corner, - const RiseFall *&rf, - Slew &slew, - float &slack, - float &limit) const; - void findLimit(const Pin *pin, - const Corner *corner, - const RiseFall *rf, - const MinMax *min_max, - const ClockSet &clks, - // Return values. - float &limit, - bool &limit_exists) const; - void checkSlewLimits(const Instance *inst, - bool violators, - const Corner *corner, - const MinMax *min_max, - PinSeq &slew_pins, - float &min_slack); - void checkSlewLimits(const Pin *pin, - bool violators, - const Corner *corner, - const MinMax *min_max, - PinSeq &slew_pins, - float &min_slack); - ClockSet clockDomains(const Vertex *vertex) const; - - const StaState *sta_; -}; - -} // namespace diff --git a/search/CheckSlews.cc b/search/CheckSlews.cc new file mode 100644 index 00000000..faa3a77c --- /dev/null +++ b/search/CheckSlews.cc @@ -0,0 +1,420 @@ +// OpenSTA, Static Timing Analyzer +// Copyright (c) 2025, Parallax Software, Inc. +// +// This program is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see . +// +// The origin of this software must not be misrepresented; you must not +// claim that you wrote the original software. +// +// Altered source versions must be plainly marked as such, and must not be +// misrepresented as being the original software. +// +// This notice may not be removed or altered from any source distribution. + +#include "CheckSlews.hh" + +#include "Fuzzy.hh" +#include "Liberty.hh" +#include "Network.hh" +#include "Sdc.hh" +#include "Mode.hh" +#include "InputDrive.hh" +#include "Graph.hh" +#include "GraphDelayCalc.hh" +#include "StaState.hh" +#include "Scene.hh" +#include "Path.hh" +#include "PortDirection.hh" +#include "Sim.hh" +#include "Search.hh" +#include "ClkNetwork.hh" + +namespace sta { + +CheckSlews::CheckSlews(const StaState *sta) : + heap_(0, SlewCheckSlackLess(sta)), + sta_(sta) +{ +} + +void +CheckSlews::clear() +{ + checks_.clear(); + heap_.clear(); +} + +SlewCheckSeq & +CheckSlews::check(const Net *net, + size_t max_count, + bool violators, + const SceneSeq &scenes, + const MinMax *min_max) +{ + clear(); + if (!violators) + heap_.setMaxSize(max_count); + + if (net) + checkNet(net, violators, scenes, min_max); + else + checkAll(violators, scenes, min_max); + + if (violators) + sort(checks_, SlewCheckSlackLess(sta_)); + else + checks_ = heap_.extract(); + return checks_; +} + +void +CheckSlews::checkNet(const Net *net, + bool violators, + const SceneSeq &scenes, + const MinMax *min_max) +{ + const Network *network = sta_->network(); + NetPinIterator *pin_iter = network->pinIterator(net); + while (pin_iter->hasNext()) { + const Pin *pin = pin_iter->next(); + checkPin(pin, violators, scenes, min_max); + } + delete pin_iter; +} + +void +CheckSlews::checkAll(bool violators, + const SceneSeq &scenes, + const MinMax *min_max) +{ + const Network *network = sta_->network(); + LeafInstanceIterator *inst_iter = network->leafInstanceIterator(); + while (inst_iter->hasNext()) { + const Instance *inst = inst_iter->next(); + checkInst(inst, violators, scenes, min_max); + } + delete inst_iter; + // Check top level ports. + checkInst(network->topInstance(), violators, scenes, min_max); +} + +void +CheckSlews::checkInst(const Instance *inst, + bool violators, + const SceneSeq &scenes, + const MinMax *min_max) +{ + const Network *network = sta_->network(); + InstancePinIterator *pin_iter = network->pinIterator(inst); + while (pin_iter->hasNext()) { + Pin *pin = pin_iter->next(); + checkPin(pin, violators, scenes, min_max); + } + delete pin_iter; +} + +void +CheckSlews::checkPin(const Pin *pin, + bool violators, + const SceneSeq &scenes, + const MinMax *min_max) +{ + const Scene *scene; + const RiseFall *rf; + Slew slew; + float limit, slack; + check(pin, scenes, min_max, true, slew, limit, slack, rf, scene); + if (scene) { + if (violators) { + if (slack < 0.0) + checks_.emplace_back(pin, rf, slew, limit, slack, scene); + } + else + heap_.insert(SlewCheck(pin, rf, slew, limit, slack, scene)); + } +} + +void +CheckSlews::check(const Pin *pin, + const SceneSeq &scenes, + const MinMax *min_max, + bool check_clks, + // Return values. + Slew &slew, + float &limit, + float &slack, + const RiseFall *&rf, + const Scene *&scene) const +{ + scene = nullptr; + rf = nullptr; + slew = 0.0; + limit = 0.0; + slack = MinMax::min()->initValue(); + + for (const Scene *scene1 : scenes) { + Vertex *vertex, *bidirect_drvr_vertex; + sta_->graph()->pinVertices(pin, vertex, bidirect_drvr_vertex); + if (vertex) + check2(vertex, scene1, min_max, check_clks, + scene, rf, slew, limit, slack); + if (bidirect_drvr_vertex) + check2(bidirect_drvr_vertex, scene1, min_max, check_clks, + scene, rf, slew, limit, slack); + } +} + +void +CheckSlews::check2(const Vertex *vertex, + const Scene *scene, + const MinMax *min_max, + bool check_clks, + // Return values. + const Scene *&scene1, + const RiseFall *&rf1, + Slew &slew1, + float &limit1, + float &slack1) const +{ + const Mode *mode = scene->mode(); + const Sdc *sdc = mode->sdc(); + const ClkNetwork *clk_network = mode->clkNetwork(); + const Pin *pin = vertex->pin(); + if (!sdc->isDisabledConstraint(pin) + && !clk_network->isIdealClock(pin)) { + ConstClockSet clks; + if (check_clks) + clks = clockDomains(vertex, scene); + for (const RiseFall *rf : RiseFall::range()) { + float limit; + bool exists; + findLimit(pin, scene, rf, min_max, clks, + limit, exists); + if (exists) { + check3(vertex, scene, rf, min_max, limit, + scene1, rf1, slew1, slack1, limit1); + } + } + } +} + +void +CheckSlews::check3(const Vertex *vertex, + const Scene *scene, + const RiseFall *rf, + const MinMax *min_max, + float limit, + // Return values. + const Scene *&scene1, + const RiseFall *&rf1, + Slew &slew1, + float &slack1, + float &limit1) const +{ + DcalcAPIndex ap_index = scene->dcalcAnalysisPtIndex(min_max); + Slew slew = sta_->graph()->slew(vertex, rf, ap_index); + float slew2 = delayAsFloat(slew); + float slack = (min_max == MinMax::max()) + ? limit - slew2 : slew2 - limit; + if (scene1 == nullptr + || (slack < slack1 + // Break ties for the sake of regression stability. + || (fuzzyEqual(slack, slack1) + && rf->index() < rf1->index()))) { + scene1 = scene; + rf1 = rf; + slew1 = slew; + slack1 = slack; + limit1 = limit; + } +} + +// Return the tightest limit. +void +CheckSlews::findLimit(const Pin *pin, + const Scene *scene, + const RiseFall *rf, + const MinMax *min_max, + const ConstClockSet &clks, + // Return values. + float &limit, + bool &exists) const +{ + const Network *network = sta_->network(); + const Sdc *sdc = scene->sdc(); + LibertyPort *port = network->libertyPort(pin); + findLimit(port, scene, min_max, + limit, exists); + + float limit1; + bool exists1; + if (!clks.empty()) { + // Look for clock slew limits. + const ClkNetwork *clk_network = scene->mode()->clkNetwork(); + bool is_clk = clk_network->isIdealClock(pin); + for (const Clock *clk : clks) { + PathClkOrData clk_data = is_clk ? PathClkOrData::clk : PathClkOrData::data; + sdc->slewLimit(clk, rf, clk_data, min_max, + limit1, exists1); + if (exists1 + && (!exists + || min_max->compare(limit, limit1))) { + limit = limit1; + exists = true; + } + } + } + + if (network->isTopLevelPort(pin)) { + Port *port = network->port(pin); + sdc->slewLimit(port, min_max, limit1, exists1); + if (exists1 + && (!exists + || min_max->compare(limit, limit1))) { + limit = limit1; + exists = true; + } + InputDrive *drive = sdc->findInputDrive(port); + if (drive) { + for (auto rf : RiseFall::range()) { + const LibertyCell *cell; + const LibertyPort *from_port; + float *from_slews; + const LibertyPort *to_port; + drive->driveCell(rf, min_max, cell, from_port, from_slews, to_port); + if (to_port) { + const LibertyPort *scene_port = to_port->scenePort(scene, min_max); + scene_port->slewLimit(min_max, limit1, exists1); + if (!exists1 + && scene_port->direction()->isAnyOutput() + && min_max == MinMax::max()) + scene_port->libertyLibrary()->defaultMaxSlew(limit1, exists1); + if (exists1 + && (!exists + || min_max->compare(limit, limit1))) { + limit = limit1; + exists = true; + } + } + } + } + } +} + +void +CheckSlews::findLimit(const LibertyPort *port, + const Scene *scene, + const MinMax *min_max, + // Return values. + float &limit, + bool &exists) const +{ + limit = INF; + exists = false; + + const Network *network = sta_->network(); + const Sdc *sdc = scene->sdc(); + float limit1; + bool exists1; + + // Default to top ("design") limit. + Cell *top_cell = network->cell(network->topInstance()); + sdc->slewLimit(top_cell, min_max, + limit1, exists1); + if (exists1) { + limit = limit1; + exists = true; + } + + if (port) { + const LibertyPort *scene_port = port->scenePort(scene, min_max); + scene_port->slewLimit(min_max, limit1, exists1); + if (!exists1 + // default_max_transition only applies to outputs. + && scene_port->direction()->isAnyOutput() + && min_max == MinMax::max()) + scene_port->libertyLibrary()->defaultMaxSlew(limit1, exists1); + if (exists1 + && (!exists + || min_max->compare(limit, limit1))) { + limit = limit1; + exists = true; + } + } +} + +ConstClockSet +CheckSlews::clockDomains(const Vertex *vertex, + const Scene *scene) const +{ + ConstClockSet clks; + VertexPathIterator path_iter(const_cast(vertex), sta_); + while (path_iter.hasNext()) { + Path *path = path_iter.next(); + if (path->scene(sta_) == scene) { + const Clock *clk = path->clock(sta_); + if (clk) + clks.insert(clk); + } + } + return clks; +} + +//////////////////////////////////////////////////////////////// + +SlewCheck::SlewCheck() : + pin_(nullptr), + rf_(nullptr), + slew_(0.0), + limit_(0.0), + slack_(0.0), + scene_(nullptr) +{ +} + +SlewCheck::SlewCheck(const Pin *pin, + const RiseFall *rf, + Slew &slew, + float limit, + float slack, + const Scene *scene) : + pin_(pin), + rf_(rf), + slew_(slew), + limit_(limit), + slack_(slack), + scene_(scene) +{ +} + +//////////////////////////////////////////////////////////////// + +SlewCheckSlackLess::SlewCheckSlackLess(const StaState *sta) : + sta_(sta) +{ +} + +bool +SlewCheckSlackLess::operator()(const SlewCheck &check1, + const SlewCheck &check2) const +{ + float slack1 = check1.slack(); + float slack2 = check2.slack(); + return fuzzyLess(slack1, slack2) + || (fuzzyEqual(slack1, slack2) + // Break ties for the sake of regression stability. + && sta_->network()->pinLess(check1.pin(), check2.pin())); +} + +} // namespace diff --git a/search/CheckSlews.hh b/search/CheckSlews.hh new file mode 100644 index 00000000..60a167db --- /dev/null +++ b/search/CheckSlews.hh @@ -0,0 +1,168 @@ +// OpenSTA, Static Timing Analyzer +// Copyright (c) 2025, Parallax Software, Inc. +// +// This program is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see . +// +// The origin of this software must not be misrepresented; you must not +// claim that you wrote the original software. +// +// Altered source versions must be plainly marked as such, and must not be +// misrepresented as being the original software. +// +// This notice may not be removed or altered from any source distribution. + +#pragma once + +#include "MinMax.hh" +#include "Transition.hh" +#include "NetworkClass.hh" +#include "GraphClass.hh" +#include "Delay.hh" +#include "SdcClass.hh" +#include "StaState.hh" +#include "BoundedHeap.hh" +#include "Network.hh" + +namespace sta { + +class Scene; +class Mode; +class SlewCheckSlackLess; + +class SlewCheck +{ +public: + SlewCheck(); + SlewCheck(const Pin *pin, + const RiseFall *rf, + Slew &slew, + float limit, + float slack, + const Scene *scene); + bool isNull() { return pin_ == nullptr; } + const Pin *pin() const { return pin_; } + Slew slew() const { return slew_; } + const RiseFall *edge() const { return rf_; } + float limit() const { return limit_; } + float slack() const { return slack_; } + const Scene *scene() const { return scene_; } + +private: + const Pin *pin_; + const RiseFall *rf_; + Slew slew_; + float limit_; + float slack_; + const Scene *scene_; +}; + +class SlewCheckSlackLess +{ +public: + SlewCheckSlackLess(const StaState *sta); + bool operator()(const SlewCheck &check1, + const SlewCheck &check2) const; + +private: + const StaState *sta_; + +}; + +using SlewCheckHeap = BoundedHeap; +using SlewCheckSeq = std::vector; + +class CheckSlews +{ +public: + CheckSlews(const StaState *sta); + void clear(); + // net=null check all nets + SlewCheckSeq &check(const Net *net, + size_t max_count, + bool violators, + const SceneSeq &scenes, + const MinMax *min_max); + void check(const Pin *pin, + const SceneSeq &scenes, + const MinMax *min_max, + bool check_clks, + // Return values. + // Scene is nullptr for no slew limit. + Slew &slew, + float &limit, + float &slack, + const RiseFall *&rf, + const Scene *&scene) const; + void findLimit(const LibertyPort *port, + const Scene *scene, + const MinMax *min_max, + // Return values. + float &limit, + bool &exists) const; + +protected: + void checkNet(const Net *net, + bool violators, + const SceneSeq &scenes, + const MinMax *min_max); + void checkAll(bool violators, + const SceneSeq &scenes, + const MinMax *min_max); + void checkInst(const Instance *inst, + bool violators, + const SceneSeq &scenes, + const MinMax *min_max); + void checkPin(const Pin *pin, + bool violators, + const SceneSeq &scenes, + const MinMax *min_max); + void check2(const Vertex *vertex, + const Scene *scene, + const MinMax *min_max, + bool check_clks, + // Return values. + const Scene *&scene1, + const RiseFall *&rf, + Slew &slew1, + float &limit1, + float &slack1) const; + void check3(const Vertex *vertex, + const Scene *scene, + const RiseFall *rf, + const MinMax *min_max, + float limit, + // Return values. + const Scene *&scene1, + const RiseFall *&rf1, + Slew &slew1, + float &slack1, + float &limit1) const; + void findLimit(const Pin *pin, + const Scene *scene, + const RiseFall *rf, + const MinMax *min_max, + const ConstClockSet &clks, + // Return values. + float &limit, + bool &limit_exists) const; + ConstClockSet clockDomains(const Vertex *vertex, + const Scene *scene) const; + + SlewCheckSeq checks_; + SlewCheckHeap heap_; + const StaState *sta_; +}; + +} // namespace + diff --git a/search/CheckTiming.cc b/search/CheckTiming.cc index 76e11698..9c692fba 100644 --- a/search/CheckTiming.cc +++ b/search/CheckTiming.cc @@ -24,6 +24,7 @@ #include "CheckTiming.hh" +#include "ContainerHelpers.hh" #include "Error.hh" #include "TimingRole.hh" #include "Network.hh" @@ -33,6 +34,7 @@ #include "PortDelay.hh" #include "ExceptionPath.hh" #include "Sdc.hh" +#include "Mode.hh" #include "SearchPred.hh" #include "Levelize.hh" #include "Bfs.hh" @@ -40,13 +42,18 @@ #include "Genclks.hh" #include "Path.hh" #include "Sim.hh" +#include "ClkNetwork.hh" namespace sta { using std::string; CheckTiming::CheckTiming(StaState *sta) : - StaState(sta) + StaState(sta), + mode_(nullptr), + sdc_(nullptr), + sim_(nullptr), + clk_network_(nullptr) { } @@ -58,9 +65,7 @@ CheckTiming::~CheckTiming() void CheckTiming::deleteErrors() { - CheckErrorSeq::Iterator error_iter(errors_); - while (error_iter.hasNext()) { - CheckError *error = error_iter.next(); + for (CheckError *error : errors_) { deleteContents(error); delete error; } @@ -74,15 +79,21 @@ CheckTiming::clear() } CheckErrorSeq & -CheckTiming::check(bool no_input_delay, - bool no_output_delay, - bool reg_multiple_clks, - bool reg_no_clks, - bool unconstrained_endpoints, - bool loops, - bool generated_clks) +CheckTiming::check(const Mode *mode, + bool no_input_delay, + bool no_output_delay, + bool reg_multiple_clks, + bool reg_no_clks, + bool unconstrained_endpoints, + bool loops, + bool generated_clks) { clear(); + mode_ = mode; + sdc_ = mode->sdc(); + sim_ = mode->sim(); + clk_network_ = mode->clkNetwork(); + if (no_input_delay) checkNoInputDelay(); if (no_output_delay) @@ -110,14 +121,14 @@ CheckTiming::checkNoInputDelay() if (!sdc_->isClock(pin)) { PortDirection *dir = network_->direction(pin); if (dir->isAnyInput() - && !sdc_->hasInputDelay(pin) - && !sim_->logicZeroOne(pin)) - no_arrival.insert(pin); + && !sdc_->hasInputDelay(pin) + && !sim_->isConstant(pin)) + no_arrival.insert(pin); } } delete pin_iter; pushPinErrors("Warning: There %is %d input port%s missing set_input_delay.", - no_arrival); + no_arrival); } void @@ -126,7 +137,7 @@ CheckTiming::checkNoOutputDelay() PinSet no_departure(network_); checkNoOutputDelay(no_departure); pushPinErrors("Warning: There %is %d output port%s missing set_output_delay.", - no_departure); + no_departure); } void @@ -138,8 +149,8 @@ CheckTiming::checkNoOutputDelay(PinSet &no_departure) const Pin *pin = pin_iter->next(); PortDirection *dir = network_->direction(pin); if (dir->isAnyOutput() - && !sdc_->hasOutputDelay(pin) - && !sim_->logicZeroOne(pin)) + && !sdc_->hasOutputDelay(pin) + && !sim_->isConstant(pin)) no_departure.insert(pin); } delete pin_iter; @@ -152,31 +163,30 @@ CheckTiming::hasClkedCheck(Vertex *vertex) while (edge_iter.hasNext()) { Edge *edge = edge_iter.next(); if (edge->role() == TimingRole::setup() - && search_->isClock(edge->from(graph_))) + && clk_network_->isClock(edge->from(graph_))) return true; } return false; } -// Search incrementally maintains register/latch clock pins, so use it. void CheckTiming::checkRegClks(bool reg_multiple_clks, - bool reg_no_clks) + bool reg_no_clks) { PinSet no_clk_pins(network_); PinSet multiple_clk_pins(network_); - for (Vertex *vertex : *graph_->regClkVertices()) { + for (Vertex *vertex : graph_->regClkVertices()) { const Pin *pin = vertex->pin(); - ClockSet clks = search_->clocks(vertex); - if (reg_no_clks && clks.empty()) + const ClockSet *clks = clk_network_->clocks(pin); + if (reg_no_clks && clks == nullptr) no_clk_pins.insert(pin); - if (reg_multiple_clks && clks.size() > 1) + if (reg_multiple_clks && clks && clks->size() > 1) multiple_clk_pins.insert(pin); } pushPinErrors("Warning: There %is %d unclocked register/latch pin%s.", - no_clk_pins); + no_clk_pins); pushPinErrors("Warning: There %is %d register/latch pin%s with multiple clocks.", - multiple_clk_pins); + multiple_clk_pins); } void @@ -194,23 +204,19 @@ CheckTiming::checkLoops() if (loop_count > 0) { string error_msg; errorMsgSubst("Warning: There %is %d combinational loop%s in the design.", - loop_count, error_msg); + loop_count, error_msg); CheckError *error = new CheckError; error->push_back(stringCopy(error_msg.c_str())); - GraphLoopSeq::Iterator loop_iter2(loops); - while (loop_iter2.hasNext()) { - GraphLoop *loop = loop_iter2.next(); + for (GraphLoop *loop : loops) { if (loop->isCombinational()) { - EdgeSeq::Iterator edge_iter(loop->edges()); - Edge *last_edge = nullptr; - while (edge_iter.hasNext()) { - Edge *edge = edge_iter.next(); - Pin *pin = edge->from(graph_)->pin(); - const char *pin_name = stringCopy(sdc_network_->pathName(pin)); - error->push_back(pin_name); - last_edge = edge; - } + Edge *last_edge = nullptr; + for (Edge *edge : *loop->edges()) { + Pin *pin = edge->from(graph_)->pin(); + const char *pin_name = stringCopy(sdc_network_->pathName(pin)); + error->push_back(pin_name); + last_edge = edge; + } if (last_edge) { error->push_back(stringCopy("| loop cut point")); const Pin *pin = last_edge->to(graph_)->pin(); @@ -233,7 +239,7 @@ CheckTiming::checkUnconstrainedEndpoints() checkUnconstrainedOutputs(unconstrained_ends); checkUnconstrainedSetups(unconstrained_ends); pushPinErrors("Warning: There %is %d unconstrained endpoint%s.", - unconstrained_ends); + unconstrained_ends); } void @@ -246,10 +252,10 @@ CheckTiming::checkUnconstrainedOutputs(PinSet &unconstrained_ends) PortDirection *dir = network_->direction(pin); Vertex *vertex = graph_->pinLoadVertex(pin); if (dir->isAnyOutput() - && !vertex->isConstant() + && !sim_->isConstant(pin) && !((hasClkedDepature(pin) - && hasClkedArrival(vertex)) - || hasMaxDelay(pin))) + && hasClkedArrival(vertex)) + || hasMaxDelay(pin))) unconstrained_ends.insert(pin); } delete pin_iter; @@ -262,8 +268,8 @@ CheckTiming::hasClkedDepature(Pin *pin) if (output_delays) { for (OutputDelay *output_delay : *output_delays) { if (output_delay->clkEdge() != nullptr - || output_delay->refPin() != nullptr) - return true; + || output_delay->refPin() != nullptr) + return true; } } return false; @@ -273,13 +279,13 @@ CheckTiming::hasClkedDepature(Pin *pin) bool CheckTiming::hasMaxDelay(Pin *pin) { - for (ExceptionPath *exception : sdc_->exceptions()) { + for (const ExceptionPath *exception : sdc_->exceptions()) { ExceptionTo *to = exception->to(); if (exception->isPathDelay() - && exception->minMax() == MinMaxAll::max() - && to - && to->hasPins() - && to->pins()->hasKey(pin)) + && exception->minMax() == MinMaxAll::max() + && to + && to->hasPins() + && to->pins()->contains(pin)) return true; } return false; @@ -291,12 +297,12 @@ CheckTiming::checkUnconstrainedSetups(PinSet &unconstrained_ends) VertexIterator vertex_iter(graph_); while (vertex_iter.hasNext()) { Vertex *vertex = vertex_iter.next(); - if (!vertex->isConstant()) { + if (!sim_->isConstant(vertex)) { VertexInEdgeIterator edge_iter(vertex, graph_); while (edge_iter.hasNext()) { Edge *edge = edge_iter.next(); if (edge->role() == TimingRole::setup() - && (!search_->isClock(edge->from(graph_)) + && (!clk_network_->isClock(edge->from(graph_)) || !hasClkedArrival(edge->to(graph_)))) { unconstrained_ends.insert(vertex->pin()); break; @@ -322,26 +328,24 @@ void CheckTiming::checkGeneratedClocks() { ClockSet gen_clk_errors; - for (auto clk : sdc_->clks()) { + for (auto clk : sdc_->clocks()) { if (clk->isGenerated()) { - search_->genclks()->checkMaster(clk); + mode_->genclks()->checkMaster(clk, sdc_); bool found_clk = false; - VertexSet src_vertices(graph_); + VertexSet src_vertices = makeVertexSet(this); clk->srcPinVertices(src_vertices, network_, graph_); - VertexSet::Iterator vertex_iter(src_vertices); - while (vertex_iter.hasNext()) { - Vertex *vertex = vertex_iter.next(); - if (search_->isClock(vertex)) { - found_clk = true; - break; - } + for (Vertex *vertex : src_vertices) { + if (clk_network_->isClock(vertex)) { + found_clk = true; + break; + } } if (!found_clk) - gen_clk_errors.insert(clk); + gen_clk_errors.insert(clk); } } pushClkErrors("Warning: There %is %d generated clock%s that %is not connected to a clock source.", - gen_clk_errors); + gen_clk_errors); } // Report the "msg" error for each pin in "pins". @@ -354,7 +358,7 @@ CheckTiming::checkGeneratedClocks() // %a - a/"" void CheckTiming::pushPinErrors(const char *msg, - PinSet &pins) + PinSet &pins) { if (!pins.empty()) { CheckError *error = new CheckError; @@ -376,7 +380,7 @@ CheckTiming::pushPinErrors(const char *msg, void CheckTiming::pushClkErrors(const char *msg, - ClockSet &clks) + ClockSet &clks) { if (!clks.empty()) { CheckError *error = new CheckError; @@ -399,40 +403,40 @@ CheckTiming::pushClkErrors(const char *msg, // Copy msg making substitutions for singular/plurals. void CheckTiming::errorMsgSubst(const char *msg, - int obj_count, - string &error_msg) + int obj_count, + string &error_msg) { for (const char *s = msg; *s; s++) { char ch = *s; if (ch == '%') { char flag = s[1]; if (flag == 'i') { - if (obj_count > 1) - error_msg += "are"; - else - error_msg += "is"; - s += 2; + if (obj_count > 1) + error_msg += "are"; + else + error_msg += "is"; + s += 2; } else if (flag == 'a') { - if (obj_count == 1) { - error_msg += 'a'; - s++; - } - else - // Skip space after %a. - s += 2; + if (obj_count == 1) { + error_msg += 'a'; + s++; + } + else + // Skip space after %a. + s += 2; } else if (flag == 's') { - if (obj_count > 1) - error_msg += 's'; - s++; + if (obj_count > 1) + error_msg += 's'; + s++; } else if (flag == 'd') { - error_msg += std::to_string(obj_count); - s++; + error_msg += std::to_string(obj_count); + s++; } else - criticalError(245, "unknown print flag"); + criticalError(245, "unknown print flag"); } else error_msg += ch; diff --git a/search/CheckTiming.hh b/search/CheckTiming.hh index 1bbc6dd1..26edc150 100644 --- a/search/CheckTiming.hh +++ b/search/CheckTiming.hh @@ -24,7 +24,8 @@ #pragma once -#include "Vector.hh" +#include + #include "StringSeq.hh" #include "NetworkClass.hh" #include "GraphClass.hh" @@ -33,21 +34,24 @@ namespace sta { -typedef StringSeq CheckError; -typedef Vector CheckErrorSeq; +class ClkNetwork; + +using CheckError = StringSeq; +using CheckErrorSeq = std::vector; class CheckTiming : public StaState { public: - explicit CheckTiming(StaState *sta); + CheckTiming(StaState *sta); ~CheckTiming(); - CheckErrorSeq &check(bool no_input_delay, - bool no_output_delay, - bool reg_multiple_clks, - bool reg_no_clks, - bool unconstrained_endpoints, - bool loops, - bool generated_clks); + CheckErrorSeq &check(const Mode *sdc, + bool no_input_delay, + bool no_output_delay, + bool reg_multiple_clks, + bool reg_no_clks, + bool unconstrained_endpoints, + bool loops, + bool generated_clks); protected: void clear(); @@ -55,7 +59,7 @@ protected: void checkNoInputDelay(); void checkNoOutputDelay(); void checkRegClks(bool reg_multiple_clks, - bool reg_no_clks); + bool reg_no_clks); void checkUnconstrainedEndpoints(); bool hasClkedArrival(Vertex *vertex); void checkNoOutputDelay(PinSet &ends); @@ -67,14 +71,18 @@ protected: bool hasMaxDelay(Pin *pin); void checkGeneratedClocks(); void pushPinErrors(const char *msg, - PinSet &pins); + PinSet &pins); void pushClkErrors(const char *msg, - ClockSet &clks); + ClockSet &clks); void errorMsgSubst(const char *msg, - int count, - std::string &error_msg); + int count, + std::string &error_msg); CheckErrorSeq errors_; + const Mode *mode_; + const Sdc *sdc_; + const Sim *sim_; + const ClkNetwork *clk_network_; }; } // namespace diff --git a/search/ClkInfo.cc b/search/ClkInfo.cc index a8679101..ac8e1bf9 100644 --- a/search/ClkInfo.cc +++ b/search/ClkInfo.cc @@ -30,25 +30,26 @@ #include "Network.hh" #include "Graph.hh" #include "Sdc.hh" -#include "Corner.hh" +#include "Scene.hh" #include "Search.hh" #include "Tag.hh" -#include "PathAnalysisPt.hh" namespace sta { -ClkInfo::ClkInfo(const ClockEdge *clk_edge, - const Pin *clk_src, - bool is_propagated, +ClkInfo::ClkInfo(Scene *scene, + const ClockEdge *clk_edge, + const Pin *clk_src, + bool is_propagated, const Pin *gen_clk_src, - bool is_gen_clk_src_path, - const RiseFall *pulse_clk_sense, - Arrival insertion, - float latency, - ClockUncertainties *uncertainties, - PathAPIndex path_ap_index, - const Path *crpr_clk_path, - const StaState *sta) : + bool is_gen_clk_src_path, + const RiseFall *pulse_clk_sense, + Arrival insertion, + float latency, + const ClockUncertainties *uncertainties, + const MinMax *min_max, + const Path *crpr_clk_path, + const StaState *sta) : + scene_(scene), clk_edge_(clk_edge), clk_src_(clk_src), gen_clk_src_(gen_clk_src), @@ -61,7 +62,7 @@ ClkInfo::ClkInfo(const ClockEdge *clk_edge, crpr_path_refs_filter_(crpr_clk_path ? crpr_clk_path->tag(sta)->isFilter() : false), is_pulse_clk_(pulse_clk_sense != nullptr), pulse_clk_sense_(pulse_clk_sense ? pulse_clk_sense->index() : 0), - path_ap_index_(path_ap_index) + min_max_index_(min_max->index()) { findHash(sta); } @@ -106,7 +107,13 @@ ClkInfo::findHash(const StaState *sta) hashIncr(hash_, is_gen_clk_src_path_); hashIncr(hash_, is_pulse_clk_); hashIncr(hash_, pulse_clk_sense_); - hashIncr(hash_, path_ap_index_); + hashIncr(hash_, min_max_index_); +} + +const MinMax * +ClkInfo::minMax() const +{ + return MinMax::find(min_max_index_); } VertexId @@ -143,15 +150,13 @@ std::string ClkInfo::to_string(const StaState *sta) const { Network *network = sta->network(); - Corners *corners = sta->corners(); std::string result; - PathAnalysisPt *path_ap = corners->findPathAnalysisPt(path_ap_index_); - result += path_ap->pathMinMax()->to_string(); + result += scene_->name(); result += "/"; - result += std::to_string(path_ap_index_); - + result += minMax()->to_string(); result += " "; + if (clk_edge_) result += clk_edge_->name(); else @@ -235,15 +240,15 @@ ClkInfoEqual::ClkInfoEqual(const StaState *sta) : bool ClkInfoEqual::operator()(const ClkInfo *clk_info1, - const ClkInfo *clk_info2) const + const ClkInfo *clk_info2) const { return ClkInfo::equal(clk_info1, clk_info2, sta_); } bool ClkInfo::equal(const ClkInfo *clk_info1, - const ClkInfo *clk_info2, - const StaState *sta) + const ClkInfo *clk_info2, + const StaState *sta) { return ClkInfo::cmp(clk_info1, clk_info2, sta) == 0; } @@ -257,16 +262,23 @@ ClkInfoLess::ClkInfoLess(const StaState *sta) : bool ClkInfoLess::operator()(const ClkInfo *clk_info1, - const ClkInfo *clk_info2) const + const ClkInfo *clk_info2) const { return ClkInfo::cmp(clk_info1, clk_info2, sta_) < 0; } int ClkInfo::cmp(const ClkInfo *clk_info1, - const ClkInfo *clk_info2, - const StaState *sta) + const ClkInfo *clk_info2, + const StaState *sta) { + size_t scene_index1 = clk_info1->scene()->index(); + size_t scene_index2 = clk_info2->scene()->index(); + if (scene_index1 < scene_index2) + return -1; + if (scene_index1 > scene_index2) + return 1; + const ClockEdge *clk_edge1 = clk_info1->clkEdge(); const ClockEdge *clk_edge2 = clk_info2->clkEdge(); int edge_index1 = clk_edge1 ? clk_edge1->index() : -1; @@ -276,11 +288,11 @@ ClkInfo::cmp(const ClkInfo *clk_info1, if (edge_index1 > edge_index2) return 1; - PathAPIndex path_ap_index1 = clk_info1->pathAPIndex(); - PathAPIndex path_ap_index2 = clk_info2->pathAPIndex(); - if (path_ap_index1 < path_ap_index2) + int mm_index1 = clk_info1->minMaxIndex(); + int mm_index2 = clk_info2->minMaxIndex(); + if (mm_index1 < mm_index2) return -1; - if (path_ap_index1 > path_ap_index2) + if (mm_index1 > mm_index2) return 1; const Network *network = sta->network(); @@ -302,14 +314,11 @@ ClkInfo::cmp(const ClkInfo *clk_info1, if (gen_clk_src_id1 > gen_clk_src_id2) return 1; - bool crpr_on = sta->crprActive(); - if (crpr_on) { - const Path *crpr_path1 = clk_info1->crprClkPathRaw(); - const Path *crpr_path2 = clk_info2->crprClkPathRaw(); - int path_cmp = Path::cmp(crpr_path1, crpr_path2, sta); - if (path_cmp != 0) - return path_cmp; - } + const Path *crpr_path1 = clk_info1->crprClkPathRaw(); + const Path *crpr_path2 = clk_info2->crprClkPathRaw(); + int path_cmp = Path::cmp(crpr_path1, crpr_path2, sta); + if (path_cmp != 0) + return path_cmp; const ClockUncertainties *uncertainties1 = clk_info1->uncertainties(); const ClockUncertainties *uncertainties2 = clk_info2->uncertainties(); diff --git a/search/ClkInfo.hh b/search/ClkInfo.hh index 09d2c0e0..8b0432bf 100644 --- a/search/ClkInfo.hh +++ b/search/ClkInfo.hh @@ -36,20 +36,24 @@ class Path; class ClkInfo { public: - ClkInfo(const ClockEdge *clk_edge, - const Pin *clk_src, - bool is_propagated, - const Pin *gen_clk_src, - bool is_gen_clk_src_path, - const RiseFall *pulse_clk_sense, - Arrival insertion, - float latency, - ClockUncertainties *uncertainties, - PathAPIndex path_ap_index, - const Path *crpr_clk_path, - const StaState *sta); + ClkInfo(Scene *scene, + const ClockEdge *clk_edge, + const Pin *clk_src, + bool is_propagated, + const Pin *gen_clk_src, + bool is_gen_clk_src_path, + const RiseFall *pulse_clk_sense, + Arrival insertion, + float latency, + const ClockUncertainties *uncertainties, + const MinMax *min_max, + const Path *crpr_clk_path, + const StaState *sta); ~ClkInfo(); std::string to_string(const StaState *sta) const; + Scene *scene() const { return scene_; } + const MinMax *minMax() const; + int minMaxIndex() const { return min_max_index_; } const ClockEdge *clkEdge() const { return clk_edge_; } const Clock *clock() const; const Pin *clkSrc() const { return clk_src_; } @@ -61,8 +65,7 @@ public: float latency() const { return latency_; } Arrival &insertion() { return insertion_; } const Arrival &insertion() const { return insertion_; } - ClockUncertainties *uncertainties() const { return uncertainties_; } - PathAPIndex pathAPIndex() const { return path_ap_index_; } + const ClockUncertainties *uncertainties() const { return uncertainties_; } // Clock path used for crpr resolution. // Null for clocks because the path cannot point to itself. Path *crprClkPath(const StaState *sta); @@ -76,20 +79,21 @@ public: const Path *crprClkPathRaw() const; static int cmp(const ClkInfo *clk_info1, - const ClkInfo *clk_info2, - const StaState *sta); + const ClkInfo *clk_info2, + const StaState *sta); static bool equal(const ClkInfo *clk_info1, - const ClkInfo *clk_info2, - const StaState *sta); + const ClkInfo *clk_info2, + const StaState *sta); protected: void findHash(const StaState *sta); private: + Scene *scene_; const ClockEdge *clk_edge_; const Pin *clk_src_; const Pin *gen_clk_src_; Path crpr_clk_path_; - ClockUncertainties *uncertainties_; + const ClockUncertainties *uncertainties_; Arrival insertion_; float latency_; size_t hash_; @@ -100,16 +104,16 @@ private: bool crpr_path_refs_filter_:1; bool is_pulse_clk_:1; unsigned int pulse_clk_sense_:RiseFall::index_bit_count; - unsigned int path_ap_index_:path_ap_index_bit_count; + unsigned int min_max_index_:MinMax::index_bit_count; }; class ClkInfoLess { public: - explicit ClkInfoLess(const StaState *sta); + ClkInfoLess(const StaState *sta); ~ClkInfoLess() {} bool operator()(const ClkInfo *clk_info1, - const ClkInfo *clk_info2) const; + const ClkInfo *clk_info2) const; protected: const StaState *sta_; @@ -126,7 +130,7 @@ class ClkInfoEqual public: ClkInfoEqual(const StaState *sta); bool operator()(const ClkInfo *clk_info1, - const ClkInfo *clk_info2) const; + const ClkInfo *clk_info2) const; protected: const StaState *sta_; diff --git a/search/ClkLatency.cc b/search/ClkLatency.cc index d9b4a68f..5fc244e8 100644 --- a/search/ClkLatency.cc +++ b/search/ClkLatency.cc @@ -26,6 +26,7 @@ #include +#include "ContainerHelpers.hh" #include "Report.hh" #include "Debug.hh" #include "Units.hh" @@ -36,7 +37,6 @@ #include "Path.hh" #include "StaState.hh" #include "Search.hh" -#include "PathAnalysisPt.hh" #include "ClkInfo.hh" namespace sta { @@ -48,29 +48,32 @@ ClkLatency::ClkLatency(StaState *sta) : ClkDelays ClkLatency::findClkDelays(const Clock *clk, - const Corner *corner, + const Scene *scene, bool include_internal_latency) { ConstClockSeq clks; clks.push_back(clk); - ClkDelayMap clk_delay_map = findClkDelays(clks, corner, + SceneSet scenes; + scenes.insert(scene); + ClkDelayMap clk_delay_map = findClkDelays(clks, scenes, include_internal_latency); return clk_delay_map[clk]; } void ClkLatency::reportClkLatency(ConstClockSeq &clks, - const Corner *corner, + const SceneSeq &scenes, bool include_internal_latency, int digits) { - ClkDelayMap clk_delay_map = findClkDelays(clks, corner, include_internal_latency); + const SceneSet scenes1 = Scene::sceneSet(scenes); + ClkDelayMap clk_delay_map = findClkDelays(clks, scenes1, include_internal_latency); // Sort the clocks to report in a stable order. ConstClockSeq sorted_clks; for (const Clock *clk : clks) sorted_clks.push_back(clk); - std::sort(sorted_clks.begin(), sorted_clks.end(), ClkNameLess()); + sort(sorted_clks, ClkNameLess()); for (const Clock *clk : sorted_clks) { ClkDelays clk_delays = clk_delay_map[clk]; @@ -143,23 +146,28 @@ ClkLatency::reportClkLatency(const Clock *clk, ClkDelayMap ClkLatency::findClkDelays(ConstClockSeq &clks, - const Corner *corner, + const SceneSet &scenes, bool include_internal_latency) { + ConstClockSet clk_set; + for (const Clock *clk : clks) + clk_set.insert(clk); + ClkDelayMap clk_delay_map; // Make entries for the relevant clocks to filter path clocks. for (const Clock *clk : clks) clk_delay_map[clk]; - for (Vertex *clk_vertex : *graph_->regClkVertices()) { + + for (Vertex *clk_vertex : graph_->regClkVertices()) { VertexPathIterator path_iter(clk_vertex, this); while (path_iter.hasNext()) { Path *path = path_iter.next(); const ClockEdge *path_clk_edge = path->clkEdge(this); - const PathAnalysisPt *path_ap = path->pathAnalysisPt(this); + const Scene *path_scene = path->scene(this); + const Clock *path_clk = path_clk_edge->clock(); if (path_clk_edge - && (corner == nullptr - || path_ap->corner() == corner)) { - const Clock *path_clk = path_clk_edge->clock(); + && scenes.contains(path_scene) + && clk_set.contains(path_clk)) { auto delays_itr = clk_delay_map.find(path_clk); if (delays_itr != clk_delay_map.end()) { ClkDelays &clk_delays = delays_itr->second; @@ -295,10 +303,10 @@ ClkDelays::insertionDelay(Path *clk_path, const RiseFall *clk_rf = clk_edge->transition(); const ClkInfo *clk_info = clk_path->clkInfo(sta); const Pin *src_pin = clk_info->clkSrc(); - const PathAnalysisPt *path_ap = clk_path->pathAnalysisPt(sta); const MinMax *min_max = clk_path->minMax(sta); + const Mode *mode = clk_path->mode(sta); return delayAsFloat(sta->search()->clockInsertion(clk, src_pin, clk_rf, min_max, - min_max, path_ap)); + min_max, mode)); } float diff --git a/search/ClkLatency.hh b/search/ClkLatency.hh index 3a7d0385..c8fbd49b 100644 --- a/search/ClkLatency.hh +++ b/search/ClkLatency.hh @@ -35,7 +35,7 @@ namespace sta { -typedef std::map ClkDelayMap; +using ClkDelayMap = std::map; // Find and report clock skews between source/target registers. class ClkLatency : public StaState @@ -44,16 +44,16 @@ public: ClkLatency(StaState *sta); // Report clk latency for clks. void reportClkLatency(ConstClockSeq &clks, - const Corner *corner, + const SceneSeq &scenes, bool include_internal_latency, int digits); ClkDelays findClkDelays(const Clock *clk, - const Corner *corner, + const Scene *scene, bool include_internal_latency); protected: ClkDelayMap findClkDelays(ConstClockSeq &clks, - const Corner *corner, + const SceneSet &scenes, bool include_internal_latency); void reportClkLatency(const Clock *clk, ClkDelays &clk_delays, diff --git a/search/ClkNetwork.cc b/search/ClkNetwork.cc index 663c350c..a27ad610 100644 --- a/search/ClkNetwork.cc +++ b/search/ClkNetwork.cc @@ -29,20 +29,23 @@ #include "Graph.hh" #include "Bfs.hh" #include "Sdc.hh" +#include "Mode.hh" #include "SearchPred.hh" #include "Search.hh" namespace sta { -ClkNetwork::ClkNetwork(StaState *sta) : +ClkNetwork::ClkNetwork(Mode *mode, + StaState *sta) : StaState(sta), + mode_(mode), clk_pins_valid_(false) { } ClkNetwork::~ClkNetwork() { - clk_pins_map_.deleteContentsClear(); + deleteContents(clk_pins_map_); } void @@ -57,7 +60,7 @@ ClkNetwork::clear() { clk_pins_valid_ = false; pin_clks_map_.clear(); - clk_pins_map_.deleteContentsClear(); + deleteContents(clk_pins_map_); pin_ideal_clks_map_.clear(); } @@ -85,7 +88,7 @@ ClkNetwork::disconnectPinBefore(const Pin *pin) void ClkNetwork::connectPinAfter(const Pin *pin) { - if (isClock(pin)) + if (network_->isRegClkPin(pin)) clkPinsInvalid(); } @@ -93,7 +96,8 @@ class ClkSearchPred : public ClkTreeSearchPred { public: ClkSearchPred(const StaState *sta); - virtual bool searchTo(const Vertex *to); + bool searchTo(const Vertex *to, + const Mode *mode) const override; }; ClkSearchPred::ClkSearchPred(const StaState *sta) : @@ -102,10 +106,10 @@ ClkSearchPred::ClkSearchPred(const StaState *sta) : } bool -ClkSearchPred::searchTo(const Vertex *to) +ClkSearchPred::searchTo(const Vertex *to, + const Mode *mode) const { - const Sdc *sdc = sta_->sdc(); - return !sdc->isLeafPinClock(to->pin()); + return !mode->sdc()->isLeafPinClock(to->pin()); } void @@ -120,38 +124,39 @@ ClkNetwork::findClkPins() void ClkNetwork::findClkPins(bool ideal_only, - PinClksMap &pin_clks_map) + PinClksMap &pin_clks_map) { + const Sdc *sdc = mode_->sdc(); ClkSearchPred srch_pred(this); BfsFwdIterator bfs(BfsIndex::other, &srch_pred, this); - for (Clock *clk : sdc_->clks()) { + for (Clock *clk : sdc->clocks()) { if (!ideal_only - || !clk->isPropagated()) { + || !clk->isPropagated()) { PinSet *clk_pins = clk_pins_map_[clk]; if (clk_pins == nullptr) { clk_pins = new PinSet(network_); clk_pins_map_[clk] = clk_pins; } for (const Pin *pin : clk->leafPins()) { - if (!ideal_only - || !sdc_->isPropagatedClock(pin)) { - Vertex *vertex, *bidirect_drvr_vertex; - graph_->pinVertices(pin, vertex, bidirect_drvr_vertex); - bfs.enqueue(vertex); - if (bidirect_drvr_vertex) - bfs.enqueue(bidirect_drvr_vertex); - } + if (!ideal_only + || !sdc->isPropagatedClock(pin)) { + Vertex *vertex, *bidirect_drvr_vertex; + graph_->pinVertices(pin, vertex, bidirect_drvr_vertex); + bfs.enqueue(vertex); + if (bidirect_drvr_vertex) + bfs.enqueue(bidirect_drvr_vertex); + } } while (bfs.hasNext()) { - Vertex *vertex = bfs.next(); - const Pin *pin = vertex->pin(); - if (!ideal_only - || !sdc_->isPropagatedClock(pin)) { - clk_pins->insert(pin); - ClockSet &pin_clks = pin_clks_map[pin]; + Vertex *vertex = bfs.next(); + const Pin *pin = vertex->pin(); + if (!ideal_only + || !sdc->isPropagatedClock(pin)) { + clk_pins->insert(pin); + ClockSet &pin_clks = pin_clks_map[pin]; pin_clks.insert(clk); - bfs.enqueueAdjacentVertices(vertex); - } + bfs.enqueueAdjacentVertices(vertex); + } } } } @@ -160,8 +165,13 @@ ClkNetwork::findClkPins(bool ideal_only, bool ClkNetwork::isClock(const Pin *pin) const { - return network_->isRegClkPin(pin) - || pin_clks_map_.hasKey(pin); + return pin_clks_map_.contains(pin); +} + +bool +ClkNetwork::isClock(const Vertex *vertex) const +{ + return isClock(vertex->pin()); } bool @@ -183,30 +193,45 @@ ClkNetwork::isClock(const Net *net) const bool ClkNetwork::isIdealClock(const Pin *pin) const { - return pin_ideal_clks_map_.hasKey(pin); + return pin_ideal_clks_map_.contains(pin); +} + +bool +ClkNetwork::isIdealClock(const Vertex *vertex) const +{ + return isIdealClock(vertex->pin()); } bool ClkNetwork::isPropagatedClock(const Pin *pin) const { - return pin_clks_map_.hasKey(pin) - && !pin_ideal_clks_map_.hasKey(pin); + return pin_clks_map_.contains(pin) + && !pin_ideal_clks_map_.contains(pin); } const ClockSet * -ClkNetwork::clocks(const Pin *pin) +ClkNetwork::clocks(const Pin *pin) const { - if (pin_clks_map_.hasKey(pin)) - return &pin_clks_map_[pin]; + auto itr = pin_clks_map_.find(pin); + if (itr != pin_clks_map_.end()) + return &itr->second; else return nullptr; } + const ClockSet * -ClkNetwork::idealClocks(const Pin *pin) +ClkNetwork::clocks(const Vertex *vertex) const { - if (pin_ideal_clks_map_.hasKey(pin)) - return &pin_ideal_clks_map_[pin]; + return clocks(vertex->pin()); +} + +const ClockSet * +ClkNetwork::idealClocks(const Pin *pin) const +{ + auto itr = pin_ideal_clks_map_.find(pin); + if (itr != pin_ideal_clks_map_.end()) + return &itr->second; else return nullptr; } @@ -214,7 +239,7 @@ ClkNetwork::idealClocks(const Pin *pin) const PinSet * ClkNetwork::pins(const Clock *clk) { - if (clk_pins_map_.hasKey(clk)) + if (clk_pins_map_.contains(clk)) return clk_pins_map_[clk]; else return nullptr; @@ -223,14 +248,12 @@ ClkNetwork::pins(const Clock *clk) float ClkNetwork::idealClkSlew(const Pin *pin, const RiseFall *rf, - const MinMax *min_max) + const MinMax *min_max) const { - const ClockSet *clks = clk_network_->idealClocks(pin); + const ClockSet *clks = idealClocks(pin); if (clks && !clks->empty()) { float slew = min_max->initValue(); - ClockSet::ConstIterator clk_iter(clks); - while (clk_iter.hasNext()) { - Clock *clk = clk_iter.next(); + for (Clock *clk : *clks) { float clk_slew = clk->slew(rf, min_max); if (min_max->compare(clk_slew, slew)) slew = clk_slew; diff --git a/search/ClkSkew.cc b/search/ClkSkew.cc index 33df2af6..9a34fe5e 100644 --- a/search/ClkSkew.cc +++ b/search/ClkSkew.cc @@ -26,6 +26,8 @@ #include // abs #include +#include +#include #include "Fuzzy.hh" #include "Report.hh" @@ -40,7 +42,6 @@ #include "Bfs.hh" #include "Path.hh" #include "StaState.hh" -#include "PathAnalysisPt.hh" #include "SearchPred.hh" #include "Search.hh" #include "Crpr.hh" @@ -50,6 +51,321 @@ namespace sta { using std::abs; +ClkSkews::ClkSkews(StaState *sta) : + StaState(sta), + include_internal_latency_(true), + fanout_pred_(this) +{ +} + +void +ClkSkews::clear() +{ + skews_.clear(); +} + +void +ClkSkews::reportClkSkew(ConstClockSeq &clks, + const SceneSeq &scenes, + const SetupHold *setup_hold, + bool include_internal_latency, + int digits) +{ + findClkSkew(clks, scenes, include_internal_latency); + + // Sort the clocks to report in a stable order. + ConstClockSeq sorted_clks; + for (const Clock *clk : clks) + sorted_clks.push_back(clk); + sort(sorted_clks, ClkNameLess()); + + for (const Clock *clk : sorted_clks) { + report_->reportLine("Clock %s", clk->name()); + auto skew_itr = skews_.find(clk); + if (skew_itr != skews_.end()) + reportClkSkew(skew_itr->second[setup_hold->index()], digits); + else + report_->reportLine("No launch/capture paths found."); + report_->reportBlankLine(); + } +} + +void +ClkSkews::reportClkSkew(ClkSkew &clk_skew, + int digits) +{ + Unit *time_unit = units_->timeUnit(); + Path *src_path = clk_skew.srcPath(); + Path *tgt_path = clk_skew.tgtPath(); + float src_latency = clk_skew.srcLatency(this); + float tgt_latency = clk_skew.tgtLatency(this); + float src_internal_clk_latency = clk_skew.srcInternalClkLatency(this); + float tgt_internal_clk_latency = clk_skew.tgtInternalClkLatency(this); + float uncertainty = clk_skew.uncertainty(this); + + if (src_internal_clk_latency != 0.0) + src_latency -= src_internal_clk_latency; + report_->reportLine("%7s source latency %s %s", + time_unit->asString(src_latency, digits), + sdc_network_->pathName(src_path->pin(this)), + src_path->transition(this)->to_string().c_str()); + if (src_internal_clk_latency != 0.0) + report_->reportLine("%7s source internal clock delay", + time_unit->asString(src_internal_clk_latency, digits)); + + if (tgt_internal_clk_latency != 0.0) + tgt_latency -= tgt_internal_clk_latency; + report_->reportLine("%7s target latency %s %s", + time_unit->asString(-tgt_latency, digits), + sdc_network_->pathName(tgt_path->pin(this)), + tgt_path->transition(this)->to_string().c_str()); + if (tgt_internal_clk_latency != 0.0) + report_->reportLine("%7s target internal clock delay", + time_unit->asString(-tgt_internal_clk_latency, digits)); + if (uncertainty != 0.0) + report_->reportLine("%7s clock uncertainty", + time_unit->asString(uncertainty, digits)); + report_->reportLine("%7s CRPR", + time_unit->asString(delayAsFloat(-clk_skew.crpr(this)), + digits)); + report_->reportLine("--------------"); + report_->reportLine("%7s %s skew", + time_unit->asString(clk_skew.skew(), digits), + src_path->minMax(this) == MinMax::max() ? "setup" : "hold"); +} + +float +ClkSkews::findWorstClkSkew(const SceneSeq &scenes, + const SetupHold *setup_hold, + bool include_internal_latency) +{ + ConstClockSeq clks; + for (const Scene *scene : scenes_) { + for (const Clock *clk : scene->sdc()->clocks()) + clks.push_back(clk); + } + findClkSkew(clks, scenes, include_internal_latency); + float worst_skew = 0.0; + for (const auto& [clk, clk_skews] : skews_) { + float skew = clk_skews[setup_hold->index()].skew(); + if (abs(skew) > abs(worst_skew)) + worst_skew = skew; + } + return worst_skew; +} + +void +ClkSkews::findClkSkew(ConstClockSeq &clks, + const SceneSeq &scenes, + bool include_internal_latency) +{ + if (scenes == scenes_ + && include_internal_latency == include_internal_latency_ + && clks == clks_ + && !skews_.empty()) + return; + + skews_.clear(); + clks_ = clks; + scenes_ = scenes; + include_internal_latency_ = include_internal_latency; + + clk_set_.clear(); + for (const Clock *clk : clks) + clk_set_.insert(clk); + scenes_set_ = Scene::sceneSet(scenes); + // This sets modes_ for fanout_pred_ also. + modes_ = Scene::modes(scenes_); + + if (thread_count_ > 1) { + std::vector partial_skews(thread_count_); + for (Vertex *src_vertex : graph_->regClkVertices()) { + if (hasClkPaths(src_vertex)) { + dispatch_queue_->dispatch([this, src_vertex, &partial_skews](int i) { + findClkSkewFrom(src_vertex, partial_skews[i]); + }); + } + } + dispatch_queue_->finishTasks(); + + // Reduce skews from each register source. + for (size_t i = 0; i < partial_skews.size(); i++) { + for (auto& [clk, partial_skew] : partial_skews[i]) { + auto itr = skews_.find(clk); + if (itr == skews_.end()) { + // Insert new entry using emplace with piecewise_construct + // This will default-construct the array, then we copy the elements + auto result = skews_.emplace(std::piecewise_construct, + std::forward_as_tuple(clk), + std::make_tuple()); + itr = result.first; + // Copy array elements + for (int setup_hold_idx : SetupHold::rangeIndex()) + itr->second[setup_hold_idx] = partial_skew[setup_hold_idx]; + } + else { + // Update existing entry + for (int setup_hold_idx : SetupHold::rangeIndex()) { + ClkSkew &final_skew = itr->second[setup_hold_idx]; + ClkSkew &partial_skew_val = partial_skew[setup_hold_idx]; + float partial_skew1 = partial_skew_val.skew(); + float final_skew1 = final_skew.skew(); + if (abs(partial_skew1) > abs(final_skew1) + || (fuzzyEqual(abs(partial_skew1), abs(final_skew1)) + // Break ties based on source/target path names. + && ClkSkew::srcTgtPathNameLess(partial_skew_val, final_skew, this))) + final_skew = partial_skew_val; + } + } + } + } + } + else { + for (Vertex *src_vertex : graph_->regClkVertices()) { + if (hasClkPaths(src_vertex)) + findClkSkewFrom(src_vertex, skews_); + } + } +} + +bool +ClkSkews::hasClkPaths(Vertex *vertex) +{ + VertexPathIterator path_iter(vertex, this); + while (path_iter.hasNext()) { + Path *path = path_iter.next(); + const Clock *path_clk = path->clock(this); + if (clk_set_.contains(path_clk)) + return true; + } + return false; +} + +void +ClkSkews::findClkSkewFrom(Vertex *src_vertex, + ClkSkewMap &skews) +{ + VertexOutEdgeIterator edge_iter(src_vertex, graph_); + while (edge_iter.hasNext()) { + Edge *edge = edge_iter.next(); + if (edge->role()->genericRole() == TimingRole::regClkToQ()) { + Vertex *q_vertex = edge->to(graph_); + const RiseFall *rf = edge->timingArcSet()->isRisingFallingEdge(); + const RiseFallBoth *src_rf = rf + ? rf->asRiseFallBoth() + : RiseFallBoth::riseFall(); + findClkSkewFrom(src_vertex, q_vertex, src_rf, skews); + } + } +} + +void +ClkSkews::findClkSkewFrom(Vertex *src_vertex, + Vertex *q_vertex, + const RiseFallBoth *src_rf, + ClkSkewMap &skews) +{ + VertexSet endpoints = findFanout(q_vertex); + for (Vertex *end : endpoints) { + VertexInEdgeIterator edge_iter(end, graph_); + while (edge_iter.hasNext()) { + Edge *edge = edge_iter.next(); + const TimingRole *role = edge->role(); + if (role->genericRole() == TimingRole::setup() + || role->genericRole() == TimingRole::hold()) { + Vertex *tgt_vertex = edge->from(graph_); + const RiseFall *tgt_rf1 = edge->timingArcSet()->isRisingFallingEdge(); + const RiseFallBoth *tgt_rf = tgt_rf1 + ? tgt_rf1->asRiseFallBoth() + : RiseFallBoth::riseFall(); + findClkSkew(src_vertex, src_rf, tgt_vertex, tgt_rf, skews); + } + } + } +} + +void +ClkSkews::findClkSkew(Vertex *src_vertex, + const RiseFallBoth *src_rf, + Vertex *tgt_vertex, + const RiseFallBoth *tgt_rf, + ClkSkewMap &skews) +{ + Unit *time_unit = units_->timeUnit(); + VertexPathIterator src_iter(src_vertex, this); + while (src_iter.hasNext()) { + Path *src_path = src_iter.next(); + Scene *src_scene = src_path->scene(this); + const Clock *src_clk = src_path->clock(this); + if (src_path->isClock(this) + && src_rf->matches(src_path->transition(this)) + && clk_set_.contains(src_clk) + && scenes_set_.contains(src_scene)) { + const MinMax *tgt_min_max = src_path->minMax(this)->opposite(); + VertexPathIterator tgt_iter(tgt_vertex, this); + while (tgt_iter.hasNext()) { + Path *tgt_path = tgt_iter.next(); + const Clock *tgt_clk = tgt_path->clock(this); + if (tgt_clk == src_clk + && tgt_path->isClock(this) + && tgt_rf->matches(tgt_path->transition(this)) + && tgt_path->minMax(this) == tgt_min_max + && tgt_path->scene(this) == src_scene) { + ClkSkew probe(src_path, tgt_path, include_internal_latency_, this); + const SetupHold *setup_hold = src_path->minMax(this); + ClkSkew &clk_skew = skews[src_clk][setup_hold->index()]; + debugPrint(debug_, "clk_skew", 2, + "%s %s %s -> %s %s %s crpr = %s skew = %s", + network_->pathName(src_path->pin(this)), + src_path->transition(this)->to_string().c_str(), + time_unit->asString(probe.srcLatency(this)), + network_->pathName(tgt_path->pin(this)), + tgt_path->transition(this)->to_string().c_str(), + time_unit->asString(probe.tgtLatency(this)), + delayAsString(probe.crpr(this), this), + time_unit->asString(probe.skew())); + if (clk_skew.srcPath() == nullptr + || abs(probe.skew()) > abs(clk_skew.skew())) + clk_skew = probe; + } + } + } + } +} + +VertexSet +ClkSkews::findFanout(Vertex *from) +{ + VertexSet endpoints = makeVertexSet(this); + std::unordered_set visited; + findFanout1(from, visited, endpoints); + return endpoints; +} + +void +ClkSkews::findFanout1(Vertex *from, + std::unordered_set &visited, + VertexSet &endpoints) +{ + visited.insert(from); + if (from->hasChecks()) + endpoints.insert(from); + if (fanout_pred_.searchFrom(from)) { + VertexOutEdgeIterator edge_iter(from, graph_); + while (edge_iter.hasNext()) { + Edge *edge = edge_iter.next(); + Vertex *to = edge->to(graph_); + if (fanout_pred_.searchThru(edge) + && fanout_pred_.searchTo(to) + // Do not revisit downstream fanout cones. + && visited.insert(to).second) + findFanout1(to, visited, endpoints); + } + } +} + +//////////////////////////////////////////////////////////////// + ClkSkew::ClkSkew() : src_path_(nullptr), tgt_path_(nullptr), @@ -59,9 +375,9 @@ ClkSkew::ClkSkew() : } ClkSkew::ClkSkew(Path *src_path, - Path *tgt_path, + Path *tgt_path, bool include_internal_latency, - StaState *sta) : + StaState *sta) : src_path_(src_path), tgt_path_(tgt_path), include_internal_latency_(include_internal_latency) @@ -167,319 +483,6 @@ ClkSkew::srcTgtPathNameLess(ClkSkew &clk_skew1, && stringEqual(tgt_path1, tgt_path2)); } - -//////////////////////////////////////////////////////////////// - -ClkSkews::ClkSkews(StaState *sta) : - StaState(sta), - corner_(nullptr), - include_internal_latency_(true), - fanout_pred_(sta) -{ -} - -void -ClkSkews::clear() -{ - skews_.clear(); -} - -void -ClkSkews::reportClkSkew(ConstClockSeq &clks, - const Corner *corner, - const SetupHold *setup_hold, - bool include_internal_latency, - int digits) -{ - findClkSkew(clks, corner, include_internal_latency); - - // Sort the clocks to report in a stable order. - ConstClockSeq sorted_clks; - for (const Clock *clk : clks) - sorted_clks.push_back(clk); - std::sort(sorted_clks.begin(), sorted_clks.end(), ClkNameLess()); - - for (const Clock *clk : sorted_clks) { - report_->reportLine("Clock %s", clk->name()); - auto skew_itr = skews_.find(clk); - if (skew_itr != skews_.end()) - reportClkSkew(skew_itr->second[setup_hold->index()], digits); - else - report_->reportLine("No launch/capture paths found."); - report_->reportBlankLine(); - } -} - -void -ClkSkews::reportClkSkew(ClkSkew &clk_skew, - int digits) -{ - Unit *time_unit = units_->timeUnit(); - Path *src_path = clk_skew.srcPath(); - Path *tgt_path = clk_skew.tgtPath(); - float src_latency = clk_skew.srcLatency(this); - float tgt_latency = clk_skew.tgtLatency(this); - float src_internal_clk_latency = clk_skew.srcInternalClkLatency(this); - float tgt_internal_clk_latency = clk_skew.tgtInternalClkLatency(this); - float uncertainty = clk_skew.uncertainty(this); - - if (src_internal_clk_latency != 0.0) - src_latency -= src_internal_clk_latency; - report_->reportLine("%7s source latency %s %s", - time_unit->asString(src_latency, digits), - sdc_network_->pathName(src_path->pin(this)), - src_path->transition(this)->to_string().c_str()); - if (src_internal_clk_latency != 0.0) - report_->reportLine("%7s source internal clock delay", - time_unit->asString(src_internal_clk_latency, digits)); - - if (tgt_internal_clk_latency != 0.0) - tgt_latency -= tgt_internal_clk_latency; - report_->reportLine("%7s target latency %s %s", - time_unit->asString(-tgt_latency, digits), - sdc_network_->pathName(tgt_path->pin(this)), - tgt_path->transition(this)->to_string().c_str()); - if (tgt_internal_clk_latency != 0.0) - report_->reportLine("%7s target internal clock delay", - time_unit->asString(-tgt_internal_clk_latency, digits)); - if (uncertainty != 0.0) - report_->reportLine("%7s clock uncertainty", - time_unit->asString(uncertainty, digits)); - report_->reportLine("%7s CRPR", - time_unit->asString(delayAsFloat(-clk_skew.crpr(this)), - digits)); - report_->reportLine("--------------"); - report_->reportLine("%7s %s skew", - time_unit->asString(clk_skew.skew(), digits), - src_path->minMax(this) == MinMax::max() ? "setup" : "hold"); -} - -float -ClkSkews::findWorstClkSkew(const Corner *corner, - const SetupHold *setup_hold, - bool include_internal_latency) -{ - ConstClockSeq clks; - for (const Clock *clk : *sdc_->clocks()) - clks.push_back(clk); - findClkSkew(clks, corner, include_internal_latency); - float worst_skew = 0.0; - for (const auto& [clk, clk_skews] : skews_) { - float skew = clk_skews[setup_hold->index()].skew(); - if (abs(skew) > abs(worst_skew)) - worst_skew = skew; - } - return worst_skew; -} - -void -ClkSkews::findClkSkew(ConstClockSeq &clks, - const Corner *corner, - bool include_internal_latency) -{ - if (corner == corner_ - && include_internal_latency == include_internal_latency_ - && clks == clks_ - && !skews_.empty()) - return; - - skews_.clear(); - clks_ = clks; - corner_ = corner; - include_internal_latency_ = include_internal_latency; - - clk_set_.clear(); - for (const Clock *clk : clks) - clk_set_.insert(clk); - - if (thread_count_ > 1) { - std::vector partial_skews(thread_count_); - for (Vertex *src_vertex : *graph_->regClkVertices()) { - if (hasClkPaths(src_vertex)) { - dispatch_queue_->dispatch([this, src_vertex, &partial_skews](int i) { - findClkSkewFrom(src_vertex, partial_skews[i]); - }); - } - } - dispatch_queue_->finishTasks(); - - // Reduce skews from each register source. - for (size_t i = 0; i < partial_skews.size(); i++) { - for (auto& [clk, partial_skew] : partial_skews[i]) { - auto itr = skews_.find(clk); - if (itr == skews_.end()) { - // Insert new entry using emplace with piecewise_construct - // This will default-construct the array, then we copy the elements - auto result = skews_.emplace(std::piecewise_construct, - std::forward_as_tuple(clk), - std::make_tuple()); - itr = result.first; - // Copy array elements - for (int setup_hold_idx : SetupHold::rangeIndex()) - itr->second[setup_hold_idx] = partial_skew[setup_hold_idx]; - } else { - // Update existing entry - for (int setup_hold_idx : SetupHold::rangeIndex()) { - ClkSkew &final_skew = itr->second[setup_hold_idx]; - ClkSkew &partial_skew_val = partial_skew[setup_hold_idx]; - float partial_skew1 = partial_skew_val.skew(); - float final_skew1 = final_skew.skew(); - if (abs(partial_skew1) > abs(final_skew1) - || (fuzzyEqual(abs(partial_skew1), abs(final_skew1)) - // Break ties based on source/target path names. - && ClkSkew::srcTgtPathNameLess(partial_skew_val, final_skew, this))) - final_skew = partial_skew_val; - } - } - } - } - } - else { - for (Vertex *src_vertex : *graph_->regClkVertices()) { - if (hasClkPaths(src_vertex)) - findClkSkewFrom(src_vertex, skews_); - } - } -} - -bool -ClkSkews::hasClkPaths(Vertex *vertex) -{ - VertexPathIterator path_iter(vertex, this); - while (path_iter.hasNext()) { - Path *path = path_iter.next(); - const Clock *path_clk = path->clock(this); - if (clk_set_.find(path_clk) != clk_set_.end()) - return true; - } - return false; -} - -void -ClkSkews::findClkSkewFrom(Vertex *src_vertex, - ClkSkewMap &skews) -{ - VertexOutEdgeIterator edge_iter(src_vertex, graph_); - while (edge_iter.hasNext()) { - Edge *edge = edge_iter.next(); - if (edge->role()->genericRole() == TimingRole::regClkToQ()) { - Vertex *q_vertex = edge->to(graph_); - const RiseFall *rf = edge->timingArcSet()->isRisingFallingEdge(); - const RiseFallBoth *src_rf = rf - ? rf->asRiseFallBoth() - : RiseFallBoth::riseFall(); - findClkSkewFrom(src_vertex, q_vertex, src_rf, skews); - } - } -} - -void -ClkSkews::findClkSkewFrom(Vertex *src_vertex, - Vertex *q_vertex, - const RiseFallBoth *src_rf, - ClkSkewMap &skews) -{ - VertexSet endpoints = findFanout(q_vertex); - for (Vertex *end : endpoints) { - VertexInEdgeIterator edge_iter(end, graph_); - while (edge_iter.hasNext()) { - Edge *edge = edge_iter.next(); - const TimingRole *role = edge->role(); - if (role->genericRole() == TimingRole::setup() - || role->genericRole() == TimingRole::hold()) { - Vertex *tgt_vertex = edge->from(graph_); - const RiseFall *tgt_rf1 = edge->timingArcSet()->isRisingFallingEdge(); - const RiseFallBoth *tgt_rf = tgt_rf1 - ? tgt_rf1->asRiseFallBoth() - : RiseFallBoth::riseFall(); - findClkSkew(src_vertex, src_rf, tgt_vertex, tgt_rf, skews); - } - } - } -} - -void -ClkSkews::findClkSkew(Vertex *src_vertex, - const RiseFallBoth *src_rf, - Vertex *tgt_vertex, - const RiseFallBoth *tgt_rf, - ClkSkewMap &skews) -{ - Unit *time_unit = units_->timeUnit(); - VertexPathIterator src_iter(src_vertex, this); - while (src_iter.hasNext()) { - Path *src_path = src_iter.next(); - const Clock *src_clk = src_path->clock(this); - if (src_path->isClock(this) - && src_rf->matches(src_path->transition(this)) - && clk_set_.find(src_clk) != clk_set_.end()) { - Corner *src_corner = src_path->pathAnalysisPt(this)->corner(); - const MinMax *tgt_min_max = src_path->minMax(this)->opposite(); - if (corner_ == nullptr - || src_corner == corner_) { - VertexPathIterator tgt_iter(tgt_vertex, this); - while (tgt_iter.hasNext()) { - Path *tgt_path = tgt_iter.next(); - const Clock *tgt_clk = tgt_path->clock(this); - if (tgt_clk == src_clk - && tgt_path->isClock(this) - && tgt_rf->matches(tgt_path->transition(this)) - && tgt_path->minMax(this) == tgt_min_max - && tgt_path->pathAnalysisPt(this)->corner() == src_corner) { - ClkSkew probe(src_path, tgt_path, include_internal_latency_, this); - const SetupHold *setup_hold = src_path->minMax(this); - ClkSkew &clk_skew = skews[src_clk][setup_hold->index()]; - debugPrint(debug_, "clk_skew", 2, - "%s %s %s -> %s %s %s crpr = %s skew = %s", - network_->pathName(src_path->pin(this)), - src_path->transition(this)->to_string().c_str(), - time_unit->asString(probe.srcLatency(this)), - network_->pathName(tgt_path->pin(this)), - tgt_path->transition(this)->to_string().c_str(), - time_unit->asString(probe.tgtLatency(this)), - delayAsString(probe.crpr(this), this), - time_unit->asString(probe.skew())); - if (clk_skew.srcPath() == nullptr - || abs(probe.skew()) > abs(clk_skew.skew())) - clk_skew = probe; - } - } - } - } - } -} - -VertexSet -ClkSkews::findFanout(Vertex *from) -{ - VertexSet endpoints(graph_); - UnorderedSet visited; - findFanout1(from, visited, endpoints); - return endpoints; -} - -void -ClkSkews::findFanout1(Vertex *from, - UnorderedSet &visited, - VertexSet &endpoints) -{ - visited.insert(from); - if (from->hasChecks()) - endpoints.insert(from); - if (fanout_pred_.searchFrom(from)) { - VertexOutEdgeIterator edge_iter(from, graph_); - while (edge_iter.hasNext()) { - Edge *edge = edge_iter.next(); - Vertex *to = edge->to(graph_); - if (fanout_pred_.searchThru(edge) - && fanout_pred_.searchTo(to) - // Do not revisit downstream fanout cones. - && visited.insert(to).second) - findFanout1(to, visited, endpoints); - } - } -} - //////////////////////////////////////////////////////////////// FanOutSrchPred::FanOutSrchPred(const StaState *sta) : @@ -488,10 +491,11 @@ FanOutSrchPred::FanOutSrchPred(const StaState *sta) : } bool -FanOutSrchPred::searchThru(Edge *edge) +FanOutSrchPred::searchThru(Edge *edge, + const Mode *mode) const { const TimingRole *role = edge->role(); - return SearchPred1::searchThru(edge) + return SearchPred1::searchThru(edge, mode) && (role == TimingRole::wire() || role == TimingRole::combinational() || role == TimingRole::tristateEnable() diff --git a/search/ClkSkew.hh b/search/ClkSkew.hh index f59d03dc..cedefa8a 100644 --- a/search/ClkSkew.hh +++ b/search/ClkSkew.hh @@ -26,7 +26,8 @@ #include -#include "UnorderedSet.hh" +#include + #include "SdcClass.hh" #include "StaState.hh" #include "Transition.hh" @@ -72,13 +73,15 @@ private: float skew_; }; -typedef std::map ClkSkewMap; +using ClkSkewMap = std::map; class FanOutSrchPred : public SearchPred1 { public: FanOutSrchPred(const StaState *sta); - virtual bool searchThru(Edge *edge); + bool searchThru(Edge *edge, + const Mode *mode) const override; + using SearchPred1::searchThru; }; // Find and report clock skews between source/target registers. @@ -89,41 +92,42 @@ public: void clear(); // Report clk skews for clks. void reportClkSkew(ConstClockSeq &clks, - const Corner *corner, - const SetupHold *setup_hold, + const SceneSeq &scenes, + const SetupHold *setup_hold, bool include_internal_latency, - int digits); + int digits); // Find worst clock skew between src/target registers. - float findWorstClkSkew(const Corner *corner, + float findWorstClkSkew(const SceneSeq &scenes, const SetupHold *setup_hold, bool include_internal_latency); protected: void findClkSkew(ConstClockSeq &clks, - const Corner *corner, + const SceneSeq &scenes, bool include_internal_latency); bool hasClkPaths(Vertex *vertex); void findClkSkewFrom(Vertex *src_vertex, - ClkSkewMap &skews); + ClkSkewMap &skews); void findClkSkewFrom(Vertex *src_vertex, - Vertex *q_vertex, - const RiseFallBoth *src_rf, - ClkSkewMap &skews); + Vertex *q_vertex, + const RiseFallBoth *src_rf, + ClkSkewMap &skews); void findClkSkew(Vertex *src_vertex, - const RiseFallBoth *src_rf, - Vertex *tgt_vertex, - const RiseFallBoth *tgt_rf, - ClkSkewMap &skews); + const RiseFallBoth *src_rf, + Vertex *tgt_vertex, + const RiseFallBoth *tgt_rf, + ClkSkewMap &skews); VertexSet findFanout(Vertex *from); void findFanout1(Vertex *from, - UnorderedSet &visited, + std::unordered_set &visited, VertexSet &endpoints); void reportClkSkew(ClkSkew &clk_skew, int digits); + // Node StaState scenes_ and modes_ are reused there. ConstClockSeq clks_; ConstClockSet clk_set_; - const Corner *corner_; + SceneSet scenes_set_; bool include_internal_latency_; FanOutSrchPred fanout_pred_; ClkSkewMap skews_; diff --git a/search/Corner.cc b/search/Corner.cc index 19a7e5df..e69de29b 100644 --- a/search/Corner.cc +++ b/search/Corner.cc @@ -1,461 +0,0 @@ -// OpenSTA, Static Timing Analyzer -// Copyright (c) 2025, Parallax Software, Inc. -// -// This program is free software: you can redistribute it and/or modify -// it under the terms of the GNU General Public License as published by -// the Free Software Foundation, either version 3 of the License, or -// (at your option) any later version. -// -// This program is distributed in the hope that it will be useful, -// but WITHOUT ANY WARRANTY; without even the implied warranty of -// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -// GNU General Public License for more details. -// -// You should have received a copy of the GNU General Public License -// along with this program. If not, see . -// -// The origin of this software must not be misrepresented; you must not -// claim that you wrote the original software. -// -// Altered source versions must be plainly marked as such, and must not be -// misrepresented as being the original software. -// -// This notice may not be removed or altered from any source distribution. - -#include "Corner.hh" - -#include "Sdc.hh" -#include "Parasitics.hh" -#include "DcalcAnalysisPt.hh" -#include "PathAnalysisPt.hh" - -namespace sta { - -Corners::Corners(StaState *sta) : - StaState(sta) -{ -} - -Corners::~Corners() -{ - clear(); -} - -void -Corners::clear() -{ - corners_.deleteContentsClear(); - corner_map_.clear(); - dcalc_analysis_pts_.deleteContentsClear(); - path_analysis_pts_.deleteContentsClear(); - parasitic_analysis_pts_.deleteContentsClear(); -} - -int -Corners::count() const -{ - return corners_.size(); -} - -bool -Corners::multiCorner() const -{ - return corners_.size() > 1; -} - -Corner * -Corners::findCorner(const char *corner_name) -{ - return corner_map_.findKey(corner_name); -} - -Corner * -Corners::findCorner(int corner_index) -{ - return corners_[corner_index]; -} - -void -Corners::analysisTypeChanged() -{ - makeAnalysisPts(); -} - -void -Corners::operatingConditionsChanged() -{ - for (DcalcAnalysisPt *dcalc_ap : dcalc_analysis_pts_) { - const MinMax *min_max = dcalc_ap->constraintMinMax(); - const OperatingConditions *op_cond = - sdc_->operatingConditions(min_max); - dcalc_ap->setOperatingConditions(op_cond); - } -} - -void -Corners::makeCorners(StringSet *corner_names) -{ - clear(); - int index = 0; - for (const char *name : *corner_names) { - Corner *corner = new Corner(name, index); - corners_.push_back(corner); - // Use the copied name in the map. - corner_map_[corner->name()] = corner; - index++; - } - makeAnalysisPts(); -} - -void -Corners::copy(Corners *corners) -{ - clear(); - int index = 0; - for (Corner *orig : corners->corners_) { - Corner *corner = new Corner(orig->name(), index); - corners_.push_back(corner); - // Use the copied name in the map. - corner_map_[corner->name()] = corner; - index++; - } - makeAnalysisPts(); - - for (ParasiticAnalysisPt *orig_ap : corners->parasitic_analysis_pts_) { - ParasiticAnalysisPt *ap = new ParasiticAnalysisPt(orig_ap->name(), - orig_ap->index(), - orig_ap->indexMax()); - parasitic_analysis_pts_.push_back(ap); - } - - for (size_t i = 0; i < corners->corners_.size(); i++) { - Corner *orig = corners->corners_[i]; - Corner *corner = corners_[i]; - corner->parasitic_analysis_pts_ = orig->parasitic_analysis_pts_; - } -} - -void -Corners::makeParasiticAnalysisPts(bool per_corner) -{ - parasitic_analysis_pts_.deleteContentsClear(); - if (per_corner) { - // per corner, per min/max - parasitic_analysis_pts_.resize(corners_.size() * MinMax::index_count); - for (Corner *corner : corners_) { - corner->setParasiticAnalysisPtcount(MinMax::index_count); - for (const MinMax *min_max : MinMax::range()) { - int mm_index = min_max->index(); - int ap_index = corner->index() * MinMax::index_count + mm_index; - int ap_index_max = corner->index() * MinMax::index_count - + MinMax::max()->index(); - std::string ap_name = corner->name(); - ap_name += "_"; - ap_name += min_max->to_string(); - ParasiticAnalysisPt *ap = new ParasiticAnalysisPt(ap_name.c_str(), - ap_index, ap_index_max); - parasitic_analysis_pts_[ap_index] = ap; - corner->setParasiticAP(ap, mm_index); - } - } - } - else { - // shared corner, per min/max - parasitic_analysis_pts_.resize(MinMax::index_count); - int ap_index_max = MinMax::max()->index(); - for (const MinMax *min_max : MinMax::range()) { - int mm_index = min_max->index(); - int ap_index = mm_index; - ParasiticAnalysisPt *ap = new ParasiticAnalysisPt(min_max->to_string().c_str(), - ap_index, - ap_index_max); - parasitic_analysis_pts_[ap_index] = ap; - for (Corner *corner : corners_) { - corner->setParasiticAnalysisPtcount(MinMax::index_count); - corner->setParasiticAP(ap, mm_index); - } - } - } -} - -void -Corners::makeAnalysisPts() -{ - dcalc_analysis_pts_.deleteContentsClear(); - path_analysis_pts_.deleteContentsClear(); - - for (Corner *corner : corners_) { - makeDcalcAnalysisPts(corner); - makePathAnalysisPts(corner); - } -} - -void -Corners::makeDcalcAnalysisPts(Corner *corner) -{ - DcalcAnalysisPt *min_ap, *max_ap; - switch (sdc_->analysisType()) { - case AnalysisType::single: - corner->setDcalcAnalysisPtcount(1); - max_ap = makeDcalcAnalysisPt(corner, MinMax::max(), MinMax::min()); - max_ap->setCheckClkSlewIndex(max_ap->index()); - break; - case AnalysisType::bc_wc: - corner->setDcalcAnalysisPtcount(2); - min_ap = makeDcalcAnalysisPt(corner, MinMax::min(), MinMax::min()); - max_ap = makeDcalcAnalysisPt(corner, MinMax::max(), MinMax::max()); - min_ap->setCheckClkSlewIndex(min_ap->index()); - max_ap->setCheckClkSlewIndex(max_ap->index()); - break; - case AnalysisType::ocv: - corner->setDcalcAnalysisPtcount(2); - min_ap = makeDcalcAnalysisPt(corner, MinMax::min(), MinMax::max()); - max_ap = makeDcalcAnalysisPt(corner, MinMax::max(), MinMax::min()); - min_ap->setCheckClkSlewIndex(max_ap->index()); - max_ap->setCheckClkSlewIndex(min_ap->index()); - break; - } -} - -DcalcAnalysisPt * -Corners::makeDcalcAnalysisPt(Corner *corner, - const MinMax *min_max, - const MinMax *check_clk_slew_min_max) -{ - OperatingConditions *op_cond = sdc_->operatingConditions(min_max); - DcalcAnalysisPt *dcalc_ap = new DcalcAnalysisPt(corner, - dcalc_analysis_pts_.size(), - op_cond, min_max, - check_clk_slew_min_max); - dcalc_analysis_pts_.push_back(dcalc_ap); - corner->addDcalcAP(dcalc_ap); - return dcalc_ap; -} - -// The clock insertion delay (source latency) required for setup and -// hold checks is: -// -// hold check -// report_timing -delay_type min -// path insertion pll_delay -// src clk min early max -// tgt clk max late min -// -// setup check -// report_timing -delay_type max -// path insertion pll_delay -// src clk max late min -// tgt clk min early max -// -// For analysis type single or bc_wc only one path is required, but as -// shown above both early and late insertion delays are required. -// To find propagated generated clock insertion delays both early and -// late clock network paths are required. Thus, analysis type single -// makes min and max analysis points. -// Only one of them is enabled to "report paths". -void -Corners::makePathAnalysisPts(Corner *corner) -{ - DcalcAnalysisPt *dcalc_ap_min = corner->findDcalcAnalysisPt(MinMax::min()); - DcalcAnalysisPt *dcalc_ap_max = corner->findDcalcAnalysisPt(MinMax::max()); - switch (sdc_->analysisType()) { - case AnalysisType::single: - case AnalysisType::bc_wc: - makePathAnalysisPts(corner, false, dcalc_ap_min, dcalc_ap_max); - break; - case AnalysisType::ocv: - makePathAnalysisPts(corner, true, dcalc_ap_min, dcalc_ap_max); - break; - } -} - - -void -Corners::makePathAnalysisPts(Corner *corner, - bool swap_clk_min_max, - DcalcAnalysisPt *dcalc_ap_min, - DcalcAnalysisPt *dcalc_ap_max) -{ - PathAnalysisPt *min_ap = new PathAnalysisPt(corner, - path_analysis_pts_.size(), - MinMax::min(), dcalc_ap_min); - path_analysis_pts_.push_back(min_ap); - corner->addPathAP(min_ap); - - PathAnalysisPt *max_ap = new PathAnalysisPt(corner, - path_analysis_pts_.size(), - MinMax::max(), dcalc_ap_max); - path_analysis_pts_.push_back(max_ap); - corner->addPathAP(max_ap); - - if (swap_clk_min_max) { - min_ap->setTgtClkAnalysisPt(max_ap); - max_ap->setTgtClkAnalysisPt(min_ap); - } - else { - min_ap->setTgtClkAnalysisPt(min_ap); - max_ap->setTgtClkAnalysisPt(max_ap); - } - - min_ap->setInsertionAnalysisPt(MinMax::min(), min_ap); - min_ap->setInsertionAnalysisPt(MinMax::max(), max_ap); - max_ap->setInsertionAnalysisPt(MinMax::min(), min_ap); - max_ap->setInsertionAnalysisPt(MinMax::max(), max_ap); -} - -int -Corners::parasiticAnalysisPtCount() const -{ - return parasitic_analysis_pts_.size(); -} - -ParasiticAnalysisPtSeq & -Corners::parasiticAnalysisPts() -{ - return parasitic_analysis_pts_; -} - -DcalcAPIndex -Corners::dcalcAnalysisPtCount() const -{ - return dcalc_analysis_pts_.size(); -} - -DcalcAnalysisPtSeq & -Corners::dcalcAnalysisPts() -{ - return dcalc_analysis_pts_; -} - -const DcalcAnalysisPtSeq & -Corners::dcalcAnalysisPts() const -{ - return dcalc_analysis_pts_; -} - -PathAPIndex -Corners::pathAnalysisPtCount() const -{ - return path_analysis_pts_.size(); -} - -PathAnalysisPtSeq & -Corners::pathAnalysisPts() -{ - return path_analysis_pts_; -} - -const PathAnalysisPtSeq & -Corners::pathAnalysisPts() const -{ - return path_analysis_pts_; -} - -PathAnalysisPt * -Corners::findPathAnalysisPt(PathAPIndex path_index) const -{ - return path_analysis_pts_[path_index]; -} - -//////////////////////////////////////////////////////////////// - -Corner::Corner(const char *name, - int index) : - name_(name), - index_(index), - path_analysis_pts_(MinMax::index_count) -{ -} - -ParasiticAnalysisPt * -Corner::findParasiticAnalysisPt(const MinMax *min_max) const -{ - int ap_count = parasitic_analysis_pts_.size(); - if (ap_count == 0) - return nullptr; - else if (ap_count == 1) - return parasitic_analysis_pts_[0]; - else if (ap_count == 2) - return parasitic_analysis_pts_[min_max->index()]; - else { - criticalError(246, "unknown parasitic analysis point count"); - return nullptr; - } -} - -void -Corner::setParasiticAnalysisPtcount(int ap_count) -{ - parasitic_analysis_pts_.resize(ap_count); -} - -void -Corner::setParasiticAP(ParasiticAnalysisPt *ap, - int mm_index) -{ - parasitic_analysis_pts_[mm_index] = ap; -} - -void -Corner::setDcalcAnalysisPtcount(DcalcAPIndex ap_count) -{ - dcalc_analysis_pts_.resize(ap_count); -} - -void -Corner::addDcalcAP(DcalcAnalysisPt *dcalc_ap) -{ - if (dcalc_analysis_pts_.size() == 1) - dcalc_analysis_pts_[0] = dcalc_ap; - else - dcalc_analysis_pts_[dcalc_ap->constraintMinMax()->index()] = dcalc_ap; -} - -DcalcAnalysisPt * -Corner::findDcalcAnalysisPt(const MinMax *min_max) const -{ - int ap_count = dcalc_analysis_pts_.size(); - if (ap_count == 0) - return nullptr; - else if (ap_count == 1) - return dcalc_analysis_pts_[0]; - else if (ap_count == 2) - return dcalc_analysis_pts_[min_max->index()]; - else { - criticalError(247, "unknown analysis point count"); - return nullptr; - } -} - -PathAnalysisPt * -Corner::findPathAnalysisPt(const MinMax *min_max) const -{ - return path_analysis_pts_[min_max->index()]; -} - -void -Corner::addPathAP(PathAnalysisPt *path_ap) -{ - path_analysis_pts_[path_ap->pathMinMax()->index()] = path_ap; -} - -void -Corner::addLiberty(LibertyLibrary *lib, - const MinMax *min_max) -{ - liberty_[min_max->index()].push_back(lib); -} - -const LibertySeq & -Corner::libertyLibraries(const MinMax *min_max) const -{ - return liberty_[min_max->index()]; -} - -int -Corner::libertyIndex(const MinMax *min_max) const -{ - return index_ * MinMax::index_count + min_max->index(); -} - -} // namespace diff --git a/search/Crpr.cc b/search/Crpr.cc index 5420f720..c2226541 100644 --- a/search/Crpr.cc +++ b/search/Crpr.cc @@ -28,12 +28,10 @@ #include #include "Debug.hh" -#include "Vector.hh" #include "Network.hh" #include "Graph.hh" #include "Sdc.hh" #include "Path.hh" -#include "PathAnalysisPt.hh" #include "ClkInfo.hh" #include "Tag.hh" #include "TagGroup.hh" @@ -42,6 +40,7 @@ #include "Search.hh" #include "Genclks.hh" #include "Variables.hh" +#include "Mode.hh" namespace sta { @@ -74,11 +73,12 @@ CheckCrpr::maxCrpr(const ClkInfo *clk_info) Arrival CheckCrpr::otherMinMaxArrival(const Path *path) { - PathAnalysisPt *other_ap = path->pathAnalysisPt(this)->tgtClkAnalysisPt(); + const MinMax *tgt_min_max = path->tgtClkMinMax(this); Tag *tag = path->tag(this); VertexPathIterator other_iter(path->vertex(this), - path->transition(this), - other_ap, this); + path->scene(this), tgt_min_max, + path->transition(this), + this); while (other_iter.hasNext()) { Path *other = other_iter.next(); if (Tag::matchCrpr(other->tag(this), tag)) @@ -91,7 +91,7 @@ CheckCrpr::otherMinMaxArrival(const Path *path) Crpr CheckCrpr::checkCrpr(const Path *src_path, - const Path *tgt_clk_path) + const Path *tgt_clk_path) { Crpr crpr; Pin *crpr_pin; @@ -101,15 +101,15 @@ CheckCrpr::checkCrpr(const Path *src_path, void CheckCrpr::checkCrpr(const Path *src_path, - const Path *tgt_clk_path, - // Return values. - Crpr &crpr, - Pin *&crpr_pin) + const Path *tgt_clk_path, + // Return values. + Crpr &crpr, + Pin *&crpr_pin) { crpr = 0.0; crpr_pin = nullptr; - if (crprActive() - && src_path && tgt_clk_path) { + if (src_path && tgt_clk_path + && crprActive(src_path->mode(this))) { bool same_pin = (variables_->crprMode() == CrprMode::same_pin); checkCrpr1(src_path, tgt_clk_path, same_pin, crpr, crpr_pin); } @@ -117,11 +117,11 @@ CheckCrpr::checkCrpr(const Path *src_path, void CheckCrpr::checkCrpr1(const Path *src_path, - const Path *tgt_clk_path, - bool same_pin, - // Return values. - Crpr &crpr, - Pin *&crpr_pin) + const Path *tgt_clk_path, + bool same_pin, + // Return values. + Crpr &crpr, + Pin *&crpr_pin) { crpr = 0.0; crpr_pin = nullptr; @@ -146,12 +146,13 @@ CheckCrpr::checkCrpr1(const Path *src_path, // is from the opposite min/max of the data. && src_clk_min_max != tgt_clk_path->minMax(this) && (src_clk_path - || src_clk->isGenerated())) { + || src_clk->isGenerated())) { // Src path from input port clk path can only be from generated clk path. if (src_clk_path == nullptr) { src_clk_path = portClkPath(src_clk_info->clkEdge(), src_clk_info->clkSrc(), - src_path->pathAnalysisPt(this)); + src_path->scene(this), + src_path->minMax(this)); } findCrpr(src_clk_path, tgt_clk_path, same_pin, crpr, crpr_pin); } @@ -160,16 +161,17 @@ CheckCrpr::checkCrpr1(const Path *src_path, // Find the clk path for an input/output port. Path * CheckCrpr::portClkPath(const ClockEdge *clk_edge, - const Pin *clk_src_pin, - const PathAnalysisPt *path_ap) + const Pin *clk_src_pin, + const Scene *scene, + const MinMax *min_max) { Vertex *clk_vertex = graph_->pinDrvrVertex(clk_src_pin); - VertexPathIterator path_iter(clk_vertex, clk_edge->transition(), - path_ap, this); + VertexPathIterator path_iter(clk_vertex, scene, min_max, + clk_edge->transition(), this); while (path_iter.hasNext()) { Path *path = path_iter.next(); if (path->clkEdge(this) == clk_edge - && path->isClock(this)) { + && path->isClock(this)) { return path; } } @@ -178,11 +180,11 @@ CheckCrpr::portClkPath(const ClockEdge *clk_edge, void CheckCrpr::findCrpr(const Path *src_clk_path, - const Path *tgt_clk_path, - bool same_pin, - // Return values. - Crpr &crpr, - Pin *&crpr_pin) + const Path *tgt_clk_path, + bool same_pin, + // Return values. + Crpr &crpr, + Pin *&crpr_pin) { crpr = 0.0; crpr_pin = nullptr; @@ -202,12 +204,12 @@ CheckCrpr::findCrpr(const Path *src_clk_path, const Path *src_path = src_gclk_paths[i]; const Path *tgt_path = tgt_gclk_paths[j]; if (src_path->clkInfo(this)->clkSrc() - == tgt_path->clkInfo(this)->clkSrc()) { - src_clk_path1 = src_gclk_paths[i]; - tgt_clk_path1 = tgt_gclk_paths[j]; + == tgt_path->clkInfo(this)->clkSrc()) { + src_clk_path1 = src_gclk_paths[i]; + tgt_clk_path1 = tgt_gclk_paths[j]; } else - break; + break; } } const Path *src_clk_path2 = src_clk_path1; @@ -222,14 +224,14 @@ CheckCrpr::findCrpr(const Path *src_clk_path, if (level_diff >= 0) { src_clk_path2 = src_clk_path2->prevPath(); if (src_clk_path2 == nullptr - || src_clk_path2->isNull()) + || src_clk_path2->isNull()) break; src_level = src_clk_path2->vertex(this)->level(); } if (level_diff <= 0) { tgt_clk_path2 = tgt_clk_path2->prevPath(); if (tgt_clk_path2 == nullptr - || tgt_clk_path2->isNull()) + || tgt_clk_path2->isNull()) break; tgt_level = tgt_clk_path2->vertex(this)->level(); } @@ -237,7 +239,7 @@ CheckCrpr::findCrpr(const Path *src_clk_path, if (src_clk_path2 && !src_clk_path2->isNull() && tgt_clk_path2 && !tgt_clk_path2->isNull() && (src_clk_path2->transition(this) == tgt_clk_path2->transition(this) - || same_pin)) { + || same_pin)) { debugPrint(debug_, "crpr", 2, "crpr pin %s", network_->pathName(src_clk_path2->pin(this))); crpr = findCrpr1(src_clk_path2, tgt_clk_path2); @@ -252,11 +254,12 @@ CheckCrpr::genClkSrcPaths(const Path *path) const ClkInfo *clk_info = path->clkInfo(this); const ClockEdge *clk_edge = clk_info->clkEdge(); const Pin *clk_src = clk_info->clkSrc(); - PathAnalysisPt *path_ap = path->pathAnalysisPt(this); + const Mode *mode = path->mode(this); + const MinMax *min_max = path->minMax(this); gclk_paths.push_back(path); - Genclks *genclks = search_->genclks(); + Genclks *genclks = mode->genclks(); while (clk_edge->clock()->isGenerated()) { - const Path *genclk_path = genclks->srcPath(clk_edge, clk_src, path_ap); + const Path *genclk_path = genclks->srcPath(clk_edge, clk_src, min_max); if (genclk_path == nullptr) break; clk_info = genclk_path->clkInfo(this); @@ -269,7 +272,7 @@ CheckCrpr::genClkSrcPaths(const Path *path) Crpr CheckCrpr::findCrpr1(const Path *src_clk_path, - const Path *tgt_clk_path) + const Path *tgt_clk_path) { if (variables_->pocvEnabled()) { // Remove variation on the common path. @@ -282,7 +285,7 @@ CheckCrpr::findCrpr1(const Path *src_clk_path, float src_clk_time = src_clk_path->clkEdge(this)->time(); float tgt_clk_time = tgt_clk_path->clkEdge(this)->time(); float crpr_mean = abs(delayAsFloat(src_arrival) - src_clk_time - - (delayAsFloat(tgt_arrival) - tgt_clk_time)); + - (delayAsFloat(tgt_arrival) - tgt_clk_time)); // Remove the sigma from both source and target path arrivals. float crpr_sigma2 = delaySigma2(src_arrival, src_el) + delaySigma2(tgt_arrival, tgt_el); @@ -310,13 +313,13 @@ CheckCrpr::crprArrivalDiff(const Path *path) { Arrival other_arrival = otherMinMaxArrival(path); float crpr_diff = abs(delayAsFloat(path->arrival()) - - delayAsFloat(other_arrival)); + - delayAsFloat(other_arrival)); return crpr_diff; } Crpr CheckCrpr::outputDelayCrpr(const Path *src_clk_path, - const ClockEdge *tgt_clk_edge) + const ClockEdge *tgt_clk_edge) { Crpr crpr; Pin *crpr_pin; @@ -326,30 +329,32 @@ CheckCrpr::outputDelayCrpr(const Path *src_clk_path, void CheckCrpr::outputDelayCrpr(const Path *src_path, - const ClockEdge *tgt_clk_edge, - // Return values. - Crpr &crpr, - Pin *&crpr_pin) + const ClockEdge *tgt_clk_edge, + // Return values. + Crpr &crpr, + Pin *&crpr_pin) { crpr = 0.0; crpr_pin = nullptr; - if (crprActive()) { - const PathAnalysisPt *path_ap = src_path->pathAnalysisPt(this); - const PathAnalysisPt *tgt_path_ap = path_ap->tgtClkAnalysisPt(); + const Scene *scene = src_path->scene(this); + const Mode *mode = scene->mode(); + if (crprActive(mode)) { + const MinMax *tgt_min_max = src_path->tgtClkMinMax(this); bool same_pin = (variables_->crprMode() == CrprMode::same_pin); - outputDelayCrpr1(src_path,tgt_clk_edge,tgt_path_ap, same_pin, - crpr, crpr_pin); + outputDelayCrpr1(src_path, tgt_clk_edge, scene, tgt_min_max, + same_pin, crpr, crpr_pin); } } void CheckCrpr::outputDelayCrpr1(const Path *src_path, - const ClockEdge *tgt_clk_edge, - const PathAnalysisPt *tgt_path_ap, - bool same_pin, - // Return values. - Crpr &crpr, - Pin *&crpr_pin) + const ClockEdge *tgt_clk_edge, + const Scene *scene, + const MinMax *min_max, + bool same_pin, + // Return values. + Crpr &crpr, + Pin *&crpr_pin) { crpr = 0.0; crpr_pin = nullptr; @@ -363,7 +368,7 @@ CheckCrpr::outputDelayCrpr1(const Path *src_path, && crprPossible(src_clk, tgt_clk)) { Path *tgt_genclk_path = portClkPath(tgt_clk_edge, tgt_clk_edge->clock()->defaultPin(), - tgt_path_ap); + scene, min_max); const Path *src_clk_path = src_path->clkInfo(this)->crprClkPath(this); if (src_clk_path) findCrpr(src_clk_path, tgt_genclk_path, same_pin, crpr, crpr_pin); @@ -372,17 +377,17 @@ CheckCrpr::outputDelayCrpr1(const Path *src_path, bool CheckCrpr::crprPossible(const Clock *clk1, - const Clock *clk2) + const Clock *clk2) { return clk1 && clk2 && !clk1->isVirtual() && !clk2->isVirtual() // Generated clocks can have crpr in the source path. && (clk1 == clk2 - || clk1->isGenerated() - || clk2->isGenerated() - // Different non-generated clocks with the same source pins (using -add). - || PinSet::intersects(&clk1->pins(), &clk2->pins(), network_)); + || clk1->isGenerated() + || clk2->isGenerated() + // Different non-generated clocks with the same source pins (using -add). + || intersects(&clk1->pins(), &clk2->pins(), network_)); } } // namespace diff --git a/search/Crpr.hh b/search/Crpr.hh index e26353aa..379608c1 100644 --- a/search/Crpr.hh +++ b/search/Crpr.hh @@ -36,58 +36,60 @@ class CrprPaths; class CheckCrpr : public StaState { public: - explicit CheckCrpr(StaState *sta); + CheckCrpr(StaState *sta); // Find the maximum possible crpr (clock min/max delta delay) for path. Arrival maxCrpr(const ClkInfo *clk_info); // Timing check CRPR. Crpr checkCrpr(const Path *src_clk_path, - const Path *tgt_clk_path); + const Path *tgt_clk_path); void checkCrpr(const Path *src_path, - const Path *tgt_clk_path, - // Return values. - Crpr &crpr, - Pin *&crpr_pin); + const Path *tgt_clk_path, + // Return values. + Crpr &crpr, + Pin *&crpr_pin); // Output delay CRPR. Crpr outputDelayCrpr(const Path *src_clk_path, - const ClockEdge *tgt_clk_edge); + const ClockEdge *tgt_clk_edge); void outputDelayCrpr(const Path *src_clk_path, - const ClockEdge *tgt_clk_edge, - // Return values. - Crpr &crpr, - Pin *&crpr_pin); + const ClockEdge *tgt_clk_edge, + // Return values. + Crpr &crpr, + Pin *&crpr_pin); private: void clkPathPrev(const Path *path, Path &prev); Arrival otherMinMaxArrival(const Path *path); void checkCrpr1(const Path *src_path, - const Path *tgt_clk_path, - bool same_pin, - // Return values. - Crpr &crpr, - Pin *&crpr_pin); + const Path *tgt_clk_path, + bool same_pin, + // Return values. + Crpr &crpr, + Pin *&crpr_pin); void outputDelayCrpr1(const Path *src_path, - const ClockEdge *tgt_clk_edge, - const PathAnalysisPt *tgt_path_ap, - bool same_pin, - // Return values. - Crpr &crpr, - Pin *&crpr_pin); + const ClockEdge *tgt_clk_edge, + const Scene *scene, + const MinMax *min_max, + bool same_pin, + // Return values. + Crpr &crpr, + Pin *&crpr_pin); bool crprPossible(const Clock *clk1, - const Clock *clk2); + const Clock *clk2); ConstPathSeq genClkSrcPaths(const Path *path); void findCrpr(const Path *src_clk_path, - const Path *tgt_clk_path, - bool same_pin, - // Return values. - Crpr &crpr, - Pin *&common_pin); + const Path *tgt_clk_path, + bool same_pin, + // Return values. + Crpr &crpr, + Pin *&common_pin); Path *portClkPath(const ClockEdge *clk_edge, const Pin *clk_src_pin, - const PathAnalysisPt *path_ap); + const Scene *scene, + const MinMax *min_max); Crpr findCrpr1(const Path *src_clk_path, - const Path *tgt_clk_path); + const Path *tgt_clk_path); float crprArrivalDiff(const Path *path); }; diff --git a/search/FindRegister.cc b/search/FindRegister.cc index 66f9b553..f45f2391 100644 --- a/search/FindRegister.cc +++ b/search/FindRegister.cc @@ -32,6 +32,7 @@ #include "Network.hh" #include "Graph.hh" #include "Sdc.hh" +#include "Mode.hh" #include "Clock.hh" #include "SearchPred.hh" #include "Search.hh" @@ -40,151 +41,147 @@ namespace sta { static TimingSense pathSenseThru(TimingSense from_sense, - TimingSense thru_sense); + TimingSense thru_sense); static bool hasMinPulseWidthCheck(LibertyPort *port); // Predicate used for searching from clocks to find registers. -class FindRegClkPred : public SearchPred1 +class FindRegClkPred : public ClkTreeSearchPred { public: FindRegClkPred(Clock *clk, - const StaState *sta); - virtual bool searchThru(Edge *edge); - virtual bool searchFrom(const Vertex *from_vertex); + const StaState *sta); + bool searchFrom(const Vertex *from_vertex, + const Mode *mode) const override; private: Clock *clk_; }; FindRegClkPred::FindRegClkPred(Clock *clk, - const StaState *sta) : - SearchPred1(sta), + const StaState *sta) : + ClkTreeSearchPred(sta), clk_(clk) { } bool -FindRegClkPred::searchFrom(const Vertex *from_vertex) +FindRegClkPred::searchFrom(const Vertex *from_vertex, + const Mode *mode) const { - const Sdc *sdc = sta_->sdc(); const Pin *from_pin = from_vertex->pin(); - return !sdc->clkStopPropagation(from_pin, clk_) - && SearchPred1::searchFrom(from_vertex); + return !mode->sdc()->clkStopPropagation(from_pin, clk_) + && ClkTreeSearchPred::searchFrom(from_vertex, mode); } -bool -FindRegClkPred::searchThru(Edge *edge) -{ - const TimingRole *role = edge->role(); - return (role->isWire() - || role == TimingRole::combinational()) - && SearchPred1::searchThru(edge); -} +//////////////////////////////////////////////////////////////// // Helper for "all_registers". // Visit all register instances. class FindRegVisitor : public StaState { public: - FindRegVisitor(StaState *sta); + FindRegVisitor(const StaState *sta); virtual ~FindRegVisitor() {} void visitRegs(ClockSet *clks, - const RiseFallBoth *clk_rf, - bool edge_triggered, - bool latches); + const RiseFallBoth *clk_rf, + bool edge_triggered, + bool latches, + const Mode *mode); private: void visitRegs(const Pin *clk_pin, - TimingSense clk_sense, - const RiseFallBoth *clk_rf, - bool edge_triggered, - bool latches); + TimingSense clk_sense, + const RiseFallBoth *clk_rf, + bool edge_triggered, + bool latches); virtual void visitReg(Instance *inst) = 0; virtual void visitSequential(Instance *inst, - Sequential *seq) = 0; + Sequential *seq) = 0; void visitFanoutRegs(Vertex *from_vertex, - TimingSense from_sense, - const RiseFallBoth *clk_rf, - bool edge_triggered, - bool latches, - SearchPred &clk_pred, - VertexSet &visited_vertices); + TimingSense from_sense, + const RiseFallBoth *clk_rf, + bool edge_triggered, + bool latches, + SearchPred &clk_pred, + VertexSet &visited_vertices, + const Mode *mode); void findSequential(const Pin *clk_pin, - Instance *inst, - LibertyCell *cell, - TimingSense clk_sense, - const RiseFallBoth *clk_rf, - bool edge_triggered, - bool latches, - bool &has_seqs, - bool &matches); + Instance *inst, + LibertyCell *cell, + TimingSense clk_sense, + const RiseFallBoth *clk_rf, + bool edge_triggered, + bool latches, + // Return values. + bool &has_seqs, + bool &matches); bool findInferedSequential(LibertyCell *cell, - TimingSense clk_sense, - const RiseFallBoth *clk_rf, - bool edge_triggered, - bool latches); + TimingSense clk_sense, + const RiseFallBoth *clk_rf, + bool edge_triggered, + bool latches); bool hasTimingCheck(LibertyCell *cell, - LibertyPort *clk, - LibertyPort *d); + LibertyPort *clk, + LibertyPort *d); }; -FindRegVisitor::FindRegVisitor(StaState *sta) : +FindRegVisitor::FindRegVisitor(const StaState *sta) : StaState(sta) { } void FindRegVisitor::visitRegs(ClockSet *clks, - const RiseFallBoth *clk_rf, - bool edge_triggered, - bool latches) + const RiseFallBoth *clk_rf, + bool edge_triggered, + bool latches, + const Mode *mode) { if (clks && !clks->empty()) { // Use DFS search to find all registers downstream of the clocks. - ClockSet::Iterator clk_iter(clks); - while (clk_iter.hasNext()) { - Clock *clk = clk_iter.next(); + for (Clock *clk : *clks) { FindRegClkPred clk_pred(clk, this); - VertexSet visited_vertices(graph_); + VertexSet visited_vertices = makeVertexSet(this); for (const Pin *pin : clk->leafPins()) { - Vertex *vertex, *bidirect_drvr_vertex; - graph_->pinVertices(pin, vertex, bidirect_drvr_vertex); - visitFanoutRegs(vertex, TimingSense::positive_unate, - clk_rf, edge_triggered, - latches, clk_pred, - visited_vertices); - // Clocks defined on bidirect pins blow it out both ends. - if (bidirect_drvr_vertex) - visitFanoutRegs(bidirect_drvr_vertex, - TimingSense::positive_unate, - clk_rf, edge_triggered, - latches, clk_pred, - visited_vertices); + Vertex *vertex, *bidirect_drvr_vertex; + graph_->pinVertices(pin, vertex, bidirect_drvr_vertex); + visitFanoutRegs(vertex, TimingSense::positive_unate, + clk_rf, edge_triggered, + latches, clk_pred, + visited_vertices, mode); + // Clocks defined on bidirect pins blow it out both ends. + if (bidirect_drvr_vertex) + visitFanoutRegs(bidirect_drvr_vertex, + TimingSense::positive_unate, + clk_rf, edge_triggered, + latches, clk_pred, + visited_vertices, mode); } } } else { - for (Vertex *vertex : *graph_->regClkVertices()) { + for (Vertex *vertex : graph_->regClkVertices()) { visitRegs(vertex->pin(), TimingSense::positive_unate, - RiseFallBoth::riseFall(), - edge_triggered, latches); + RiseFallBoth::riseFall(), + edge_triggered, latches); } } } void FindRegVisitor::visitFanoutRegs(Vertex *from_vertex, - TimingSense from_sense, - const RiseFallBoth *clk_rf, - bool edge_triggered, - bool latches, - SearchPred &clk_pred, - VertexSet &visited_vertices) + TimingSense from_sense, + const RiseFallBoth *clk_rf, + bool edge_triggered, + bool latches, + SearchPred &clk_pred, + VertexSet &visited_vertices, + const Mode *mode) { - if (!visited_vertices.hasKey(from_vertex) - && clk_pred.searchFrom(from_vertex)) { + if (!visited_vertices.contains(from_vertex) + && clk_pred.searchFrom(from_vertex, mode)) { visited_vertices.insert(from_vertex); VertexOutEdgeIterator edge_iter(from_vertex, graph_); while (edge_iter.hasNext()) { @@ -193,22 +190,22 @@ FindRegVisitor::visitFanoutRegs(Vertex *from_vertex, const Pin *to_pin = to_vertex->pin(); TimingSense to_sense = pathSenseThru(from_sense, edge->sense()); if (to_vertex->isRegClk()) - visitRegs(to_pin, to_sense, clk_rf, edge_triggered, latches); + visitRegs(to_pin, to_sense, clk_rf, edge_triggered, latches); // Even register clock pins can have combinational fanout arcs. - if (clk_pred.searchThru(edge) - && clk_pred.searchTo(to_vertex)) - visitFanoutRegs(to_vertex, to_sense, clk_rf, edge_triggered, latches, - clk_pred, visited_vertices); + if (clk_pred.searchThru(edge, mode) + && clk_pred.searchTo(to_vertex, mode)) + visitFanoutRegs(to_vertex, to_sense, clk_rf, edge_triggered, latches, + clk_pred, visited_vertices, mode); } } } void FindRegVisitor::visitRegs(const Pin *clk_pin, - TimingSense clk_sense, - const RiseFallBoth *clk_rf, - bool edge_triggered, - bool latches) + TimingSense clk_sense, + const RiseFallBoth *clk_rf, + bool edge_triggered, + bool latches) { Instance *inst = network_->instance(clk_pin); LibertyCell *cell = network_->libertyCell(inst); @@ -216,11 +213,11 @@ FindRegVisitor::visitRegs(const Pin *clk_pin, || clk_rf != RiseFallBoth::riseFall()) { bool matches, has_seqs; findSequential(clk_pin, inst, cell, clk_sense, clk_rf, - edge_triggered, latches, - has_seqs, matches); + edge_triggered, latches, + has_seqs, matches); if (!has_seqs) matches = findInferedSequential(cell, clk_sense, clk_rf, - edge_triggered, latches); + edge_triggered, latches); if (matches) visitReg(inst); } @@ -232,39 +229,40 @@ FindRegVisitor::visitRegs(const Pin *clk_pin, void FindRegVisitor::findSequential(const Pin *clk_pin, - Instance *inst, - LibertyCell *cell, - TimingSense clk_sense, - const RiseFallBoth *clk_rf, - bool edge_triggered, - bool latches, - bool &has_seqs, - bool &matches) + Instance *inst, + LibertyCell *cell, + TimingSense clk_sense, + const RiseFallBoth *clk_rf, + bool edge_triggered, + bool latches, + // Return values. + bool &has_seqs, + bool &matches) { has_seqs = false; matches = false; for (Sequential *seq : cell->sequentials()) { has_seqs = true; if ((seq->isRegister() && edge_triggered) - || (seq->isLatch() && latches)) { + || (seq->isLatch() && latches)) { if (clk_rf == RiseFallBoth::riseFall()) { - visitSequential(inst, seq); - matches = true; - break; + visitSequential(inst, seq); + matches = true; + break; } else { - FuncExpr *clk_func = seq->clock(); - LibertyPort *port = network_->libertyPort(clk_pin); - TimingSense port_sense = clk_func->portTimingSense(port); - TimingSense path_sense = pathSenseThru(clk_sense, port_sense); - if ((path_sense == TimingSense::positive_unate - && clk_rf == RiseFallBoth::rise()) - || (path_sense == TimingSense::negative_unate - && clk_rf == RiseFallBoth::fall())) { - visitSequential(inst, seq); - matches = true; - break; - } + FuncExpr *clk_func = seq->clock(); + LibertyPort *port = network_->libertyPort(clk_pin); + TimingSense port_sense = clk_func->portTimingSense(port); + TimingSense path_sense = pathSenseThru(clk_sense, port_sense); + if ((path_sense == TimingSense::positive_unate + && clk_rf == RiseFallBoth::rise()) + || (path_sense == TimingSense::negative_unate + && clk_rf == RiseFallBoth::fall())) { + visitSequential(inst, seq); + matches = true; + break; + } } } } @@ -272,10 +270,10 @@ FindRegVisitor::findSequential(const Pin *clk_pin, bool FindRegVisitor::findInferedSequential(LibertyCell *cell, - TimingSense clk_sense, - const RiseFallBoth *clk_rf, - bool edge_triggered, - bool latches) + TimingSense clk_sense, + const RiseFallBoth *clk_rf, + bool edge_triggered, + bool latches) { bool matches = false; const RiseFall *clk_rf1 = clk_rf->asRiseFall(); @@ -283,16 +281,16 @@ FindRegVisitor::findInferedSequential(LibertyCell *cell, TimingArc *arc = *arc_set->arcs().begin(); const RiseFall *arc_clk_rf = arc->fromEdge()->asRiseFall(); bool tr_matches = (clk_rf == RiseFallBoth::riseFall() - || (arc_clk_rf == clk_rf1 - && clk_sense == TimingSense::positive_unate) - || (arc_clk_rf == clk_rf1->opposite() - && clk_sense == TimingSense::negative_unate)); + || (arc_clk_rf == clk_rf1 + && clk_sense == TimingSense::positive_unate) + || (arc_clk_rf == clk_rf1->opposite() + && clk_sense == TimingSense::negative_unate)); const TimingRole *role = arc_set->role(); if (tr_matches - && ((role == TimingRole::regClkToQ() - && edge_triggered) - || (role == TimingRole::latchEnToQ() - && latches))) { + && ((role == TimingRole::regClkToQ() + && edge_triggered) + || (role == TimingRole::latchEnToQ() + && latches))) { matches = true; break; } @@ -302,8 +300,8 @@ FindRegVisitor::findInferedSequential(LibertyCell *cell, bool FindRegVisitor::hasTimingCheck(LibertyCell *cell, - LibertyPort *clk, - LibertyPort *d) + LibertyPort *clk, + LibertyPort *d) { for (TimingArcSet *arc_set : cell->timingArcSets(clk, d)) { const TimingRole *role = arc_set->role(); @@ -316,21 +314,22 @@ FindRegVisitor::hasTimingCheck(LibertyCell *cell, class FindRegInstances : public FindRegVisitor { public: - explicit FindRegInstances(StaState *sta); + FindRegInstances(const StaState *sta); InstanceSet findRegs(ClockSet *clks, const RiseFallBoth *clk_rf, bool edge_triggered, - bool latches); + bool latches, + const Mode *mode); private: virtual void visitReg(Instance *inst); virtual void visitSequential(Instance *inst, - Sequential *seq); + Sequential *seq); InstanceSet regs_; }; -FindRegInstances::FindRegInstances(StaState *sta) : +FindRegInstances::FindRegInstances(const StaState *sta) : FindRegVisitor(sta), regs_(network_) { @@ -338,17 +337,18 @@ FindRegInstances::FindRegInstances(StaState *sta) : InstanceSet FindRegInstances::findRegs(ClockSet *clks, - const RiseFallBoth *clk_rf, - bool edge_triggered, - bool latches) + const RiseFallBoth *clk_rf, + bool edge_triggered, + bool latches, + const Mode *mode) { - visitRegs(clks, clk_rf, edge_triggered, latches); + visitRegs(clks, clk_rf, edge_triggered, latches, mode); return regs_; } void FindRegInstances::visitSequential(Instance *, - Sequential *) + Sequential *) { } @@ -360,13 +360,14 @@ FindRegInstances::visitReg(Instance *inst) InstanceSet findRegInstances(ClockSet *clks, - const RiseFallBoth *clk_rf, - bool edge_triggered, - bool latches, - StaState *sta) + const RiseFallBoth *clk_rf, + bool edge_triggered, + bool latches, + const Mode *mode, + const StaState *sta) { FindRegInstances find_regs(sta); - return find_regs.findRegs(clks, clk_rf, edge_triggered, latches); + return find_regs.findRegs(clks, clk_rf, edge_triggered, latches, mode); } //////////////////////////////////////////////////////////////// @@ -374,20 +375,21 @@ findRegInstances(ClockSet *clks, class FindRegPins : public FindRegVisitor { public: - FindRegPins(StaState *sta); + FindRegPins(const StaState *sta); PinSet findPins(ClockSet *clks, const RiseFallBoth *clk_rf, bool edge_triggered, - bool latches); + bool latches, + const Mode *mode); protected: virtual void visitReg(Instance *inst); virtual void visitSequential(Instance *inst, - Sequential *seq); + Sequential *seq); virtual bool matchPin(Pin *pin); void visitExpr(FuncExpr *expr, - Instance *inst, - Sequential *seq); + Instance *inst, + Sequential *seq); // Sequential expressions to find instance pins. virtual FuncExpr *seqExpr1(Sequential *seq) = 0; virtual FuncExpr *seqExpr2(Sequential *seq) = 0; @@ -395,7 +397,7 @@ protected: PinSet pins_; }; -FindRegPins::FindRegPins(StaState *sta) : +FindRegPins::FindRegPins(const StaState *sta) : FindRegVisitor(sta), pins_(network_) { @@ -403,17 +405,18 @@ FindRegPins::FindRegPins(StaState *sta) : PinSet FindRegPins::findPins(ClockSet *clks, - const RiseFallBoth *clk_rf, - bool edge_triggered, - bool latches) + const RiseFallBoth *clk_rf, + bool edge_triggered, + bool latches, + const Mode *mode) { - visitRegs(clks, clk_rf, edge_triggered, latches); + visitRegs(clks, clk_rf, edge_triggered, latches, mode); return pins_; } void FindRegPins::visitSequential(Instance *inst, - Sequential *seq) + Sequential *seq) { visitExpr(seqExpr1(seq), inst, seq); visitExpr(seqExpr2(seq), inst, seq); @@ -421,16 +424,15 @@ FindRegPins::visitSequential(Instance *inst, void FindRegPins::visitExpr(FuncExpr *expr, - Instance *inst, - Sequential *) + Instance *inst, + Sequential *) { if (expr) { - FuncExprPortIterator port_iter(expr); - while (port_iter.hasNext()) { - LibertyPort *port = port_iter.next(); + LibertyPortSet ports = expr->ports(); + for (LibertyPort *port : ports) { Pin *pin = network_->findPin(inst, port); if (pin) - pins_.insert(pin); + pins_.insert(pin); } } } @@ -456,7 +458,7 @@ FindRegPins::matchPin(Pin *) class FindRegDataPins : public FindRegPins { public: - explicit FindRegDataPins(StaState *sta); + FindRegDataPins(const StaState *sta); private: virtual bool matchPin(Pin *pin); @@ -464,7 +466,7 @@ private: virtual FuncExpr *seqExpr2(Sequential *seq); }; -FindRegDataPins::FindRegDataPins(StaState *sta) : +FindRegDataPins::FindRegDataPins(const StaState *sta) : FindRegPins(sta) { } @@ -508,13 +510,14 @@ hasMinPulseWidthCheck(LibertyPort *port) PinSet findRegDataPins(ClockSet *clks, - const RiseFallBoth *clk_rf, - bool edge_triggered, - bool latches, - StaState *sta) + const RiseFallBoth *clk_rf, + bool edge_triggered, + bool latches, + const Mode *mode, + const StaState *sta) { FindRegDataPins find_regs(sta); - return find_regs.findPins(clks, clk_rf, edge_triggered, latches); + return find_regs.findPins(clks, clk_rf, edge_triggered, latches, mode); } //////////////////////////////////////////////////////////////// @@ -522,7 +525,7 @@ findRegDataPins(ClockSet *clks, class FindRegClkPins : public FindRegPins { public: - explicit FindRegClkPins(StaState *sta); + FindRegClkPins(const StaState *sta); private: virtual bool matchPin(Pin *pin); @@ -530,7 +533,7 @@ private: virtual FuncExpr *seqExpr2(Sequential *seq); }; -FindRegClkPins::FindRegClkPins(StaState *sta) : +FindRegClkPins::FindRegClkPins(const StaState *sta) : FindRegPins(sta) { } @@ -565,13 +568,14 @@ FindRegClkPins::seqExpr2(Sequential *) PinSet findRegClkPins(ClockSet *clks, - const RiseFallBoth *clk_rf, - bool edge_triggered, - bool latches, - StaState *sta) + const RiseFallBoth *clk_rf, + bool edge_triggered, + bool latches, + const Mode *mode, + const StaState *sta) { FindRegClkPins find_regs(sta); - return find_regs.findPins(clks, clk_rf, edge_triggered, latches); + return find_regs.findPins(clks, clk_rf, edge_triggered, latches, mode); } //////////////////////////////////////////////////////////////// @@ -579,7 +583,7 @@ findRegClkPins(ClockSet *clks, class FindRegAsyncPins : public FindRegPins { public: - explicit FindRegAsyncPins(StaState *sta); + FindRegAsyncPins(const StaState *sta); private: virtual bool matchPin(Pin *pin); @@ -587,7 +591,7 @@ private: virtual FuncExpr *seqExpr2(Sequential *seq) { return seq->preset(); } }; -FindRegAsyncPins::FindRegAsyncPins(StaState *sta) : +FindRegAsyncPins::FindRegAsyncPins(const StaState *sta) : FindRegPins(sta) { } @@ -607,13 +611,14 @@ FindRegAsyncPins::matchPin(Pin *pin) PinSet findRegAsyncPins(ClockSet *clks, - const RiseFallBoth *clk_rf, - bool edge_triggered, - bool latches, - StaState *sta) + const RiseFallBoth *clk_rf, + bool edge_triggered, + bool latches, + const Mode *mode, + const StaState *sta) { FindRegAsyncPins find_regs(sta); - return find_regs.findPins(clks, clk_rf, edge_triggered, latches); + return find_regs.findPins(clks, clk_rf, edge_triggered, latches, mode); } //////////////////////////////////////////////////////////////// @@ -621,20 +626,20 @@ findRegAsyncPins(ClockSet *clks, class FindRegOutputPins : public FindRegPins { public: - explicit FindRegOutputPins(StaState *sta); + FindRegOutputPins(const StaState *sta); private: virtual bool matchPin(Pin *pin); virtual void visitSequential(Instance *inst, - Sequential *seq); + Sequential *seq); void visitOutput(LibertyPort *port, - Instance *inst); + Instance *inst); // Unused. virtual FuncExpr *seqExpr1(Sequential *seq); virtual FuncExpr *seqExpr2(Sequential *seq); }; -FindRegOutputPins::FindRegOutputPins(StaState *sta) : +FindRegOutputPins::FindRegOutputPins(const StaState *sta) : FindRegPins(sta) { } @@ -647,8 +652,8 @@ FindRegOutputPins::matchPin(Pin *pin) for (TimingArcSet *arc_set : cell->timingArcSets(nullptr, port)) { const TimingRole *role = arc_set->role(); if (role == TimingRole::regClkToQ() - || role == TimingRole::latchEnToQ() - || role == TimingRole::latchDtoQ()) + || role == TimingRole::latchEnToQ() + || role == TimingRole::latchDtoQ()) return true; } return false; @@ -656,7 +661,7 @@ FindRegOutputPins::matchPin(Pin *pin) void FindRegOutputPins::visitSequential(Instance *inst, - Sequential *seq) + Sequential *seq) { visitOutput(seq->output(), inst); visitOutput(seq->outputInv(), inst); @@ -664,7 +669,7 @@ FindRegOutputPins::visitSequential(Instance *inst, void FindRegOutputPins::visitOutput(LibertyPort *port, - Instance *inst) + Instance *inst) { if (port) { // Sequential outputs are internal ports. @@ -676,9 +681,9 @@ FindRegOutputPins::visitOutput(LibertyPort *port, LibertyPort *pin_port = network_->libertyPort(pin); FuncExpr *func = pin_port->function(); if (func - && func->port() - && func->port() == port) - pins_.insert(pin); + && func->port() + && func->port() == port) + pins_.insert(pin); } delete pin_iter; } @@ -698,13 +703,14 @@ FindRegOutputPins::seqExpr2(Sequential *) PinSet findRegOutputPins(ClockSet *clks, - const RiseFallBoth *clk_rf, - bool edge_triggered, - bool latches, - StaState *sta) + const RiseFallBoth *clk_rf, + bool edge_triggered, + bool latches, + const Mode *mode, + const StaState *sta) { FindRegOutputPins find_regs(sta); - return find_regs.findPins(clks, clk_rf, edge_triggered, latches); + return find_regs.findPins(clks, clk_rf, edge_triggered, latches, mode); } //////////////////////////////////////////////////////////////// @@ -713,8 +719,8 @@ static TimingSense path_sense_thru[timing_sense_count][timing_sense_count]; static void initPathSenseThru1(TimingSense from, - TimingSense thru, - TimingSense to) + TimingSense thru, + TimingSense to) { path_sense_thru[int(from)][int(thru)] = to; } @@ -723,63 +729,63 @@ void initPathSenseThru() { initPathSenseThru1(TimingSense::positive_unate, TimingSense::positive_unate, - TimingSense::positive_unate); + TimingSense::positive_unate); initPathSenseThru1(TimingSense::positive_unate, TimingSense::negative_unate, - TimingSense::negative_unate); + TimingSense::negative_unate); initPathSenseThru1(TimingSense::positive_unate, TimingSense::non_unate, - TimingSense::non_unate); + TimingSense::non_unate); initPathSenseThru1(TimingSense::positive_unate, TimingSense::none, - TimingSense::none); + TimingSense::none); initPathSenseThru1(TimingSense::positive_unate, TimingSense::unknown, - TimingSense::unknown); + TimingSense::unknown); initPathSenseThru1(TimingSense::negative_unate, TimingSense::positive_unate, - TimingSense::negative_unate); + TimingSense::negative_unate); initPathSenseThru1(TimingSense::negative_unate, TimingSense::negative_unate, - TimingSense::positive_unate); + TimingSense::positive_unate); initPathSenseThru1(TimingSense::negative_unate, TimingSense::non_unate, - TimingSense::non_unate); + TimingSense::non_unate); initPathSenseThru1(TimingSense::negative_unate, TimingSense::none, - TimingSense::none); + TimingSense::none); initPathSenseThru1(TimingSense::negative_unate, TimingSense::unknown, - TimingSense::unknown); + TimingSense::unknown); initPathSenseThru1(TimingSense::non_unate, TimingSense::positive_unate, - TimingSense::non_unate); + TimingSense::non_unate); initPathSenseThru1(TimingSense::non_unate, TimingSense::negative_unate, - TimingSense::non_unate); + TimingSense::non_unate); initPathSenseThru1(TimingSense::non_unate, TimingSense::non_unate, - TimingSense::non_unate); + TimingSense::non_unate); initPathSenseThru1(TimingSense::non_unate, TimingSense::none, - TimingSense::none); + TimingSense::none); initPathSenseThru1(TimingSense::non_unate, TimingSense::unknown, - TimingSense::unknown); + TimingSense::unknown); initPathSenseThru1(TimingSense::none, TimingSense::positive_unate, - TimingSense::none); + TimingSense::none); initPathSenseThru1(TimingSense::none, TimingSense::negative_unate, - TimingSense::none); + TimingSense::none); initPathSenseThru1(TimingSense::none, TimingSense::non_unate, - TimingSense::none); + TimingSense::none); initPathSenseThru1(TimingSense::none, TimingSense::none, - TimingSense::none); + TimingSense::none); initPathSenseThru1(TimingSense::none, TimingSense::unknown, - TimingSense::unknown); + TimingSense::unknown); initPathSenseThru1(TimingSense::unknown, TimingSense::positive_unate, - TimingSense::unknown); + TimingSense::unknown); initPathSenseThru1(TimingSense::unknown, TimingSense::negative_unate, - TimingSense::unknown); + TimingSense::unknown); initPathSenseThru1(TimingSense::unknown, TimingSense::non_unate, - TimingSense::unknown); + TimingSense::unknown); initPathSenseThru1(TimingSense::unknown, TimingSense::none, - TimingSense::unknown); + TimingSense::unknown); initPathSenseThru1(TimingSense::unknown, TimingSense::unknown, - TimingSense::unknown); + TimingSense::unknown); } static TimingSense pathSenseThru(TimingSense from_sense, - TimingSense thru_sense) + TimingSense thru_sense) { return path_sense_thru[int(from_sense)][int(thru_sense)]; } diff --git a/search/FindRegister.hh b/search/FindRegister.hh index f9820f9c..96cd5062 100644 --- a/search/FindRegister.hh +++ b/search/FindRegister.hh @@ -32,20 +32,40 @@ namespace sta { InstanceSet -findRegInstances(ClockSet *clks, const RiseFallBoth *clk_rf, - bool edge_triggered, bool latches, StaState *sta); +findRegInstances(ClockSet *clks, + const RiseFallBoth *clk_rf, + bool edge_triggered, + bool latches, + const Mode *mode, + const StaState *sta); PinSet -findRegDataPins(ClockSet *clks, const RiseFallBoth *clk_rf, - bool edge_triggered, bool latches, StaState *sta); +findRegDataPins(ClockSet *clks, + const RiseFallBoth *clk_rf, + bool edge_triggered, + bool latches, + const Mode *mode, + const StaState *sta); PinSet -findRegClkPins(ClockSet *clks, const RiseFallBoth *clk_rf, - bool edge_triggered, bool latches, StaState *sta); +findRegClkPins(ClockSet *clks, + const RiseFallBoth *clk_rf, + bool edge_triggered, + bool latches, + const Mode *mode, + const StaState *sta); PinSet -findRegAsyncPins(ClockSet *clks, const RiseFallBoth *clk_rf, - bool edge_triggered, bool latches, StaState *sta); +findRegAsyncPins(ClockSet *clks, + const RiseFallBoth *clk_rf, + bool edge_triggered, + bool latches, + const Mode *mode, + const StaState *sta); PinSet -findRegOutputPins(ClockSet *clks, const RiseFallBoth *clk_rf, - bool edge_triggered, bool latches, StaState *sta); +findRegOutputPins(ClockSet *clks, + const RiseFallBoth *clk_rf, + bool edge_triggered, + bool latches, + const Mode *mode, + const StaState *sta); void initPathSenseThru(); diff --git a/search/GatedClk.cc b/search/GatedClk.cc index 804cee9d..e7fa73fc 100644 --- a/search/GatedClk.cc +++ b/search/GatedClk.cc @@ -29,8 +29,10 @@ #include "PortDirection.hh" #include "Network.hh" #include "Graph.hh" +#include "Mode.hh" #include "Sdc.hh" #include "Search.hh" +#include "ClkNetwork.hh" namespace sta { @@ -40,88 +42,87 @@ GatedClk::GatedClk(const StaState *sta) : } bool -GatedClk::isGatedClkEnable(Vertex *vertex) const +GatedClk::isGatedClkEnable(Vertex *vertex, + const Mode *mode) const { bool is_gated_clk_enable; const Pin *clk_pin; LogicValue logic_active_value; - isGatedClkEnable(vertex, - is_gated_clk_enable, clk_pin, logic_active_value); + isGatedClkEnable(vertex, mode, + is_gated_clk_enable, clk_pin, logic_active_value); return is_gated_clk_enable; } void GatedClk::isGatedClkEnable(Vertex *enable_vertex, - bool &is_gated_clk_enable, - const Pin *&clk_pin, - LogicValue &logic_active_value) const + const Mode *mode, + // Return values. + bool &is_gated_clk_enable, + const Pin *&clk_pin, + LogicValue &logic_active_value) const { is_gated_clk_enable = false; const Pin *enable_pin = enable_vertex->pin(); const Instance *inst = network_->instance(enable_pin); LibertyPort *enable_port = network_->libertyPort(enable_pin); EvalPred *eval_pred = search_->evalPred(); + ClkNetwork *clk_network = mode->clkNetwork(); if (enable_port + && !clk_network->isClock(enable_vertex) && enable_port->direction()->isInput() - && !sdc_->isDisableClockGatingCheck(enable_pin) - && !sdc_->isDisableClockGatingCheck(inst) - && eval_pred->searchFrom(enable_vertex)) { + && eval_pred->searchFrom(enable_vertex, mode)) { + const Sdc *sdc = mode->sdc(); FuncExpr *func = nullptr; Vertex *gclk_vertex = nullptr; VertexOutEdgeIterator edge_iter(enable_vertex, graph_); while (edge_iter.hasNext()) { Edge *edge = edge_iter.next(); gclk_vertex = edge->to(graph_); + const Pin *gclk_pin = gclk_vertex->pin(); if (edge->role() == TimingRole::combinational() - && eval_pred->searchTo(gclk_vertex) - && eval_pred->searchThru(edge)) { - const Pin *gclk_pin = gclk_vertex->pin(); - LibertyPort *gclk_port = network_->libertyPort(gclk_pin); - if (gclk_port) { - func = gclk_port->function(); - if (func) - break; - } - } - } - if (func - && search_->isClock(gclk_vertex) - && !search_->isClock(enable_vertex)) { - FuncExprPortIterator clk_port_iter(func); - while (clk_port_iter.hasNext()) { - LibertyPort *clk_port = clk_port_iter.next(); - if (clk_port != enable_port) { - bool is_clk_gate = false; - isClkGatingFunc(func, enable_port, clk_port, - is_clk_gate, logic_active_value); - if (is_clk_gate) { - clk_pin = network_->findPin(inst, clk_port); - if (clk_pin - && !sdc_->isDisableClockGatingCheck(clk_pin) - && search_->isClock(graph_->pinLoadVertex(clk_pin))) { - is_gated_clk_enable = true; - break; - } - } - } + && eval_pred->searchTo(gclk_vertex, mode) + && eval_pred->searchThru(edge, mode)) { + LibertyPort *gclk_port = network_->libertyPort(gclk_pin); + func = gclk_port->function(); + if (gclk_port + && func + && clk_network->isClock(gclk_vertex)) { + LibertyPortSet clk_ports = func->ports(); + for (LibertyPort *clk_port : clk_ports) { + if (clk_port != enable_port) { + bool is_clk_gate = false; + isClkGatingFunc(func, enable_port, clk_port, + is_clk_gate, logic_active_value); + if (is_clk_gate) { + clk_pin = network_->findPin(inst, clk_port); + if (clk_pin + && !sdc->isDisableClockGatingCheck(clk_pin) + && clk_network->isClock(graph_->pinLoadVertex(clk_pin))) { + is_gated_clk_enable = true; + return; + } + } + } + } + } } } + } } -void +PinSet GatedClk::gatedClkEnables(Vertex *clk_vertex, - // Return value. - PinSet &enable_pins) + const Mode *mode) { + PinSet enable_pins(network_); const Pin *clk_pin = clk_vertex->pin(); const Instance *inst = network_->instance(clk_pin); LibertyPort *clk_port = network_->libertyPort(clk_pin); EvalPred *eval_pred = search_->evalPred(); if (clk_port - && !sdc_->isDisableClockGatingCheck(clk_pin) - && !sdc_->isDisableClockGatingCheck(inst) - && eval_pred->searchFrom(clk_vertex)) { + && eval_pred->searchFrom(clk_vertex, mode)) { + ClkNetwork *clk_network = mode->clkNetwork(); FuncExpr *func = nullptr; Vertex *gclk_vertex = nullptr; VertexOutEdgeIterator edge_iter(clk_vertex, graph_); @@ -129,56 +130,55 @@ GatedClk::gatedClkEnables(Vertex *clk_vertex, Edge *edge = edge_iter.next(); gclk_vertex = edge->to(graph_); if (edge->role() == TimingRole::combinational() - && eval_pred->searchTo(gclk_vertex) - && eval_pred->searchThru(edge)) { - const Pin *gclk_pin = gclk_vertex->pin(); - LibertyPort *gclk_port = network_->libertyPort(gclk_pin); - if (gclk_port) { - func = gclk_port->function(); - if (func) { - if (search_->isClock(gclk_vertex)) { - FuncExprPortIterator enable_port_iter(func); - while (enable_port_iter.hasNext()) { - LibertyPort *enable_port = enable_port_iter.next(); - if (enable_port != clk_port) { - bool is_clk_gate; - LogicValue logic_value; - isClkGatingFunc(func, enable_port, clk_port, - is_clk_gate, logic_value); - if (is_clk_gate) { - Pin *enable_pin = network_->findPin(inst, enable_port); - if (enable_pin - && !sdc_->isDisableClockGatingCheck(enable_pin) - && !search_->isClock(graph_->pinLoadVertex(enable_pin))) { - enable_pins.insert(enable_pin); - } - } - } - } - } - break; - } - } + && eval_pred->searchTo(gclk_vertex, mode) + && eval_pred->searchThru(edge, mode)) { + const Pin *gclk_pin = gclk_vertex->pin(); + LibertyPort *gclk_port = network_->libertyPort(gclk_pin); + if (gclk_port) { + func = gclk_port->function(); + if (func) { + if (clk_network->isClock(gclk_vertex)) { + LibertyPortSet enable_ports = func->ports(); + for (LibertyPort *enable_port : enable_ports) { + if (enable_port != clk_port) { + bool is_clk_gate; + LogicValue logic_value; + isClkGatingFunc(func, enable_port, clk_port, + is_clk_gate, logic_value); + if (is_clk_gate) { + Pin *enable_pin = network_->findPin(inst, enable_port); + if (enable_pin + && !clk_network->isClock(graph_->pinLoadVertex(enable_pin))) { + enable_pins.insert(enable_pin); + } + } + } + } + } + break; + } + } } } } + return enable_pins; } void GatedClk::isClkGatingFunc(FuncExpr *func, - LibertyPort *enable_port, - LibertyPort *clk_port, - bool &is_clk_gate, - LogicValue &logic_value) const + LibertyPort *enable_port, + LibertyPort *clk_port, + bool &is_clk_gate, + LogicValue &logic_value) const { // The function should be in two-level SOP or POS form depending on "cost". // We need to apply literal cofactor if any input port is constant and // do "simple" logic minimization based on SOP and POS. - while (func->op() == FuncExpr::op_not) + while (func->op() == FuncExpr::Op::not_) func = func->left(); - if (func->op() == FuncExpr::op_and) + if (func->op() == FuncExpr::Op::and_) logic_value = LogicValue::one; - else if (func->op() == FuncExpr::op_or) + else if (func->op() == FuncExpr::Op::or_) logic_value = LogicValue::zero; else { is_clk_gate = false; @@ -190,35 +190,32 @@ GatedClk::isClkGatingFunc(FuncExpr *func, functionClkOperands(func, func->right(), funcs); bool need_gating_check = false; - FuncExprSet::Iterator expr_iter(funcs); - while (expr_iter.hasNext()) { - FuncExpr *expr = expr_iter.next(); - if (expr->op() == FuncExpr::op_not) { - if (expr->left()->op() == FuncExpr::op_port - && expr->left()->port() == clk_port) { - need_gating_check = true; - logic_value = (logic_value == LogicValue::one) ? LogicValue::zero : LogicValue::one; + for (FuncExpr *expr : funcs) { + if (expr->op() == FuncExpr::Op::not_) { + if (expr->left()->op() == FuncExpr::Op::port + && expr->left()->port() == clk_port) { + need_gating_check = true; + logic_value = (logic_value == LogicValue::one) + ? LogicValue::zero + : LogicValue::one; } } else { - if (expr->op() == FuncExpr::op_port - && expr->port() == clk_port) { - need_gating_check = true; + if (expr->op() == FuncExpr::Op::port + && expr->port() == clk_port) { + need_gating_check = true; } } } if (need_gating_check) { - FuncExprSet::Iterator expr_iter2(funcs); - while (expr_iter2.hasNext()) { - FuncExpr *expr = expr_iter2.next(); - FuncExprPortIterator en_port_iter(expr); - while (en_port_iter.hasNext()) { - LibertyPort *port = en_port_iter.next(); - if (port == enable_port) { - is_clk_gate = true; - return; - } + for (FuncExpr *expr : funcs) { + LibertyPortSet ports = expr->ports(); + for (LibertyPort *port : ports) { + if (port == enable_port) { + is_clk_gate = true; + return; + } } } } @@ -227,8 +224,8 @@ GatedClk::isClkGatingFunc(FuncExpr *func, void GatedClk::functionClkOperands(FuncExpr *root_expr, - FuncExpr *expr, - FuncExprSet &funcs) const + FuncExpr *expr, + FuncExprSet &funcs) const { if (expr->op() != root_expr->op()) funcs.insert(expr); @@ -240,7 +237,7 @@ GatedClk::functionClkOperands(FuncExpr *root_expr, const RiseFall * GatedClk::gatedClkActiveTrans(LogicValue active_value, - const MinMax *min_max) const + const MinMax *min_max) const { const RiseFall *leading_rf; switch (active_value) { diff --git a/search/GatedClk.hh b/search/GatedClk.hh index 8f63307d..6cec6bc4 100644 --- a/search/GatedClk.hh +++ b/search/GatedClk.hh @@ -24,6 +24,8 @@ #pragma once +#include + #include "SdcClass.hh" #include "GraphClass.hh" #include "SearchClass.hh" @@ -31,33 +33,35 @@ namespace sta { -typedef Set FuncExprSet; +using FuncExprSet = std::set; class GatedClk : public StaState { public: GatedClk(const StaState *sta); - bool isGatedClkEnable(Vertex *vertex) const; + bool isGatedClkEnable(Vertex *vertexm, + const Mode *mode) const; void isGatedClkEnable(Vertex *enable_vertex, - bool &is_gated_clk_enable, - const Pin *&clk_pin, - LogicValue &logic_active_value) const; - void gatedClkEnables(Vertex *clk_vertex, - // Return value. - PinSet &enable_pins); + const Mode *mode, + // Return values. + bool &is_gated_clk_enable, + const Pin *&clk_pin, + LogicValue &logic_active_value) const; + PinSet gatedClkEnables(Vertex *clk_vertex, + const Mode *mode); const RiseFall *gatedClkActiveTrans(LogicValue active_value, const MinMax *min_max) const; protected: void isClkGatingFunc(FuncExpr *func, - LibertyPort *enable_port, - LibertyPort *clk_port, - bool &is_clk_gate, - LogicValue &logic_value) const; + LibertyPort *enable_port, + LibertyPort *clk_port, + bool &is_clk_gate, + LogicValue &logic_value) const; void functionClkOperands(FuncExpr *root_expr, - FuncExpr *curr_expr, - FuncExprSet &funcs) const; + FuncExpr *curr_expr, + FuncExprSet &funcs) const; }; } // namespace diff --git a/search/Genclks.cc b/search/Genclks.cc index e002c4c7..66b8cd14 100644 --- a/search/Genclks.cc +++ b/search/Genclks.cc @@ -24,6 +24,7 @@ #include "Genclks.hh" +#include "ContainerHelpers.hh" #include "Stats.hh" #include "Debug.hh" #include "Report.hh" @@ -31,14 +32,14 @@ #include "PortDirection.hh" #include "Graph.hh" #include "Sdc.hh" +#include "Mode.hh" #include "ExceptionPath.hh" #include "Clock.hh" #include "StaState.hh" #include "SearchPred.hh" #include "Bfs.hh" #include "TagGroup.hh" -#include "Corner.hh" -#include "PathAnalysisPt.hh" +#include "Scene.hh" #include "Levelize.hh" #include "Path.hh" #include "Search.hh" @@ -52,35 +53,33 @@ class GenclkInfo { public: GenclkInfo(Clock *gclk, - Level gclk_level, - VertexSet *fanins, - FilterPath *src_filter); + Level gclk_level, + FilterPath *src_filter, + const StaState *sta); ~GenclkInfo(); - EdgeSet *fdbkEdges() const { return fdbk_edges_; } - VertexSet *fanins() const { return fanins_; } + EdgeSet &fdbkEdges() { return fdbk_edges_; } + VertexSet &fanins() { return fanins_; } Level gclkLevel() const { return gclk_level_; } FilterPath *srcFilter() const { return src_filter_; } - void setLatchFdbkEdges(EdgeSet *fdbk_edges); bool foundLatchFdbkEdges() const { return found_latch_fdbk_edges_; } void setFoundLatchFdbkEdges(bool found); protected: Clock *gclk_; Level gclk_level_; - VertexSet *fanins_; - EdgeSet *fdbk_edges_; + VertexSet fanins_; + EdgeSet fdbk_edges_; bool found_latch_fdbk_edges_; FilterPath *src_filter_; }; GenclkInfo::GenclkInfo(Clock *gclk, - Level gclk_level, - VertexSet *fanins, - FilterPath *src_filter) : + Level gclk_level, + FilterPath *src_filter, + const StaState *sta) : gclk_(gclk), gclk_level_(gclk_level), - fanins_(fanins), - fdbk_edges_(nullptr), + fanins_(makeVertexSet(sta->graph())), found_latch_fdbk_edges_(false), src_filter_(src_filter) { @@ -88,17 +87,9 @@ GenclkInfo::GenclkInfo(Clock *gclk, GenclkInfo::~GenclkInfo() { - delete fanins_; - delete fdbk_edges_; delete src_filter_; } -void -GenclkInfo::setLatchFdbkEdges(EdgeSet *fdbk_edges) -{ - fdbk_edges_ = fdbk_edges; -} - void GenclkInfo::setFoundLatchFdbkEdges(bool found) { @@ -107,8 +98,10 @@ GenclkInfo::setFoundLatchFdbkEdges(bool found) //////////////////////////////////////////////////////////////// -Genclks::Genclks(StaState *sta) : +Genclks::Genclks(const Mode *mode, + StaState *sta) : StaState(sta), + mode_(mode), found_insertion_delays_(false), vertex_src_paths_map_(graph_) { @@ -116,7 +109,7 @@ Genclks::Genclks(StaState *sta) : Genclks::~Genclks() { - genclk_info_map_.deleteContentsClear(); + deleteContents(genclk_info_map_); clearSrcPaths(); } @@ -124,8 +117,7 @@ void Genclks::clear() { found_insertion_delays_ = false; - genclk_info_map_.deleteContentsClear(); - vertex_src_paths_map_.clear(); + deleteContents(genclk_info_map_); clearSrcPaths(); } @@ -134,7 +126,7 @@ Genclks::fanins(const Clock *clk) { GenclkInfo *genclk_info = genclkInfo(clk); if (genclk_info) - return genclk_info->fanins(); + return &genclk_info->fanins(); else return nullptr; } @@ -167,9 +159,9 @@ Genclks::clkPinMaxLevel(const Clock *clk) const class ClockPinMaxLevelLess { public: - explicit ClockPinMaxLevelLess(const Genclks *genclks); + ClockPinMaxLevelLess(const Genclks *genclks); bool operator()(Clock *clk1, - Clock *clk2) const; + Clock *clk2) const; protected: const Genclks *genclks_; @@ -182,7 +174,7 @@ ClockPinMaxLevelLess::ClockPinMaxLevelLess(const Genclks *genclks) : bool ClockPinMaxLevelLess::operator()(Clock *clk1, - Clock *clk2) const + Clock *clk2) const { return genclks_->clkPinMaxLevel(clk1) < genclks_->clkPinMaxLevel(clk2); } @@ -198,106 +190,79 @@ Genclks::ensureInsertionDelays() Stats stats(debug_, report_); debugPrint(debug_, "genclk", 1, "find generated clk insertion delays"); + clearSrcPaths(); + Sdc *sdc = mode_->sdc(); ClockSeq gclks; - for (auto clk : sdc_->clks()) { + for (Clock *clk : sdc->clocks()) { if (clk->isGenerated()) { - checkMaster(clk); - gclks.push_back(clk); + checkMaster(clk, sdc); + gclks.push_back(clk); } } - clearSrcPaths(); - // Generated clocks derived from a generated clock inherit its // insertion delay, so sort the clocks by source pin level. - sort(gclks, ClockPinMaxLevelLess(this)); + sort(gclks , ClockPinMaxLevelLess(this)); for (Clock *gclk : gclks) { if (gclk->masterClk()) { - findInsertionDelays(gclk); - recordSrcPaths(gclk); + findInsertionDelays(gclk); + recordSrcPaths(gclk); } } - stats.report("Find generated clk insertion delays"); found_insertion_delays_ = true; } } -// Similar to ClkTreeSearchPred but ignore constants. -class GenClkMasterSearchPred : public SearchPred +//////////////////////////////////////////////////////////////// + +class GenClkMasterSearchPred : public ClkTreeSearchPred { public: - explicit GenClkMasterSearchPred(const StaState *sta); - virtual bool searchFrom(const Vertex *from_vertex); - virtual bool searchThru(Edge *edge); - virtual bool searchTo(const Vertex *to_vertex); - -protected: - const StaState *sta_; + GenClkMasterSearchPred(const StaState *sta); + bool searchThruAllow(const TimingRole *role) const override; }; GenClkMasterSearchPred::GenClkMasterSearchPred(const StaState *sta) : - SearchPred(), - sta_(sta) + ClkTreeSearchPred(sta) { } bool -GenClkMasterSearchPred::searchFrom(const Vertex *from_vertex) +GenClkMasterSearchPred::searchThruAllow(const TimingRole *role) const { - return !from_vertex->isDisabledConstraint(); + return (role->isWire() + || role == TimingRole::combinational() + || role->regClkToQ()); } -bool -GenClkMasterSearchPred::searchThru(Edge *edge) -{ - const Variables *variables = sta_->variables(); - const TimingRole *role = edge->role(); - // Propagate clocks through constants. - return !(edge->role()->isTimingCheck() - || edge->isDisabledLoop() - || edge->isDisabledConstraint() - // Constants disable edge cond expression. - || edge->isDisabledCond() - || sta_->isDisabledCondDefault(edge) - // Register/latch preset/clr edges are disabled by default. - || (!variables->presetClrArcsEnabled() - && role == TimingRole::regSetClr()) - || (edge->isBidirectInstPath() - && !variables->bidirectInstPathsEnabled()) - || (edge->isBidirectNetPath() - && !variables->bidirectNetPathsEnabled())); -} - -bool -GenClkMasterSearchPred::searchTo(const Vertex *) -{ - return true; -} +//////////////////////////////////////////////////////////////// void -Genclks::checkMaster(Clock *gclk) +Genclks::checkMaster(Clock *gclk, + const Sdc *sdc) { - ensureMaster(gclk); + ensureMaster(gclk, sdc); if (gclk->masterClk() == nullptr) report_->warn(1060, "no master clock found for generated clock %s.", - gclk->name()); + gclk->name()); } void -Genclks::ensureMaster(Clock *gclk) +Genclks::ensureMaster(Clock *gclk, + const Sdc *sdc) { Clock *master_clk = gclk->masterClk(); if (master_clk == nullptr) { int master_clk_count = 0; bool found_master = false; Pin *src_pin = gclk->srcPin(); - ClockSet *master_clks = sdc_->findClocks(src_pin); - ClockSet::Iterator master_iter(master_clks); - if (master_iter.hasNext()) { - while (master_iter.hasNext()) { - master_clk = master_iter.next(); + ClockSet *master_clks = sdc->findClocks(src_pin); + if (master_clks) { + ClockSet::iterator master_iter = master_clks->begin(); + while (master_iter != master_clks->end()) { + master_clk = *master_iter++; // Master source pin can actually be a clock source pin. if (master_clk != gclk) { gclk->setInferedMasterClk(master_clk); @@ -317,12 +282,12 @@ Genclks::ensureMaster(Clock *gclk) while (iter.hasNext()) { Vertex *vertex = iter.next(); Pin *pin = vertex->pin(); - if (sdc_->isLeafPinClock(pin)) { - ClockSet *master_clks = sdc_->findLeafPinClocks(pin); + if (sdc->isLeafPinClock(pin)) { + ClockSet *master_clks = sdc->findLeafPinClocks(pin); if (master_clks) { - ClockSet::Iterator master_iter(master_clks); - if (master_iter.hasNext()) { - master_clk = master_iter.next(); + ClockSet::iterator master_iter = master_clks->begin(); + if (master_iter != master_clks->end()) { + master_clk = *master_iter++; // Master source pin can actually be a clock source pin. if (master_clk != gclk) { gclk->setInferedMasterClk(master_clk); @@ -335,7 +300,7 @@ Genclks::ensureMaster(Clock *gclk) } } } - iter.enqueueAdjacentVertices(vertex); + iter.enqueueAdjacentVertices(vertex, mode_); } } if (master_clk_count > 1) @@ -348,9 +313,9 @@ Genclks::ensureMaster(Clock *gclk) void Genclks::seedSrcPins(Clock *clk, - BfsBkwdIterator &iter) + BfsBkwdIterator &iter) { - VertexSet src_vertices(graph_); + VertexSet src_vertices = makeVertexSet(this); clk->srcPinVertices(src_vertices, network_, graph_); for (Vertex *vertex : src_vertices) iter.enqueue(vertex); @@ -359,55 +324,36 @@ Genclks::seedSrcPins(Clock *clk, //////////////////////////////////////////////////////////////// // Similar to ClkTreeSearchPred but -// search thru constants // respect generated clock combinational attribute -// search thru disabled loop arcs class GenClkFaninSrchPred : public GenClkMasterSearchPred { public: - explicit GenClkFaninSrchPred(Clock *gclk, - const StaState *sta); - virtual bool searchFrom(const Vertex *from_vertex); - virtual bool searchThru(Edge *edge); - virtual bool searchTo(const Vertex *to_vertex); + GenClkFaninSrchPred(Clock *gclk, + const StaState *sta); + bool searchThruAllow(const TimingRole *role) const override; private: bool combinational_; }; GenClkFaninSrchPred::GenClkFaninSrchPred(Clock *gclk, - const StaState *sta) : + const StaState *sta) : GenClkMasterSearchPred(sta), combinational_(gclk->combinational()) { } bool -GenClkFaninSrchPred::searchFrom(const Vertex *from_vertex) +GenClkFaninSrchPred::searchThruAllow(const TimingRole *role) const { - return !from_vertex->isDisabledConstraint(); -} - -bool -GenClkFaninSrchPred::searchThru(Edge *edge) -{ - const TimingRole *role = edge->role(); - return GenClkMasterSearchPred::searchThru(edge) - && (role == TimingRole::combinational() - || role == TimingRole::wire() - || !combinational_); -} - -bool -GenClkFaninSrchPred::searchTo(const Vertex *) -{ - return true; + return (role == TimingRole::combinational() + || role == TimingRole::wire() + || !combinational_); } void Genclks::findFanin(Clock *gclk, - // Return value. - VertexSet *fanins) + VertexSet &fanins) { // Search backward from generated clock source pin to a clock pin. GenClkFaninSrchPred srch_pred(gclk, this); @@ -415,102 +361,98 @@ Genclks::findFanin(Clock *gclk, seedClkVertices(gclk, iter, fanins); while (iter.hasNext()) { Vertex *vertex = iter.next(); - if (!fanins->hasKey(vertex)) { - fanins->insert(vertex); + if (!fanins.contains(vertex)) { + fanins.insert(vertex); debugPrint(debug_, "genclk", 2, "gen clk %s fanin %s", gclk->name(), vertex->to_string(this).c_str()); - iter.enqueueAdjacentVertices(vertex); + iter.enqueueAdjacentVertices(vertex, mode_); } } } void Genclks::seedClkVertices(Clock *clk, - BfsBkwdIterator &iter, - VertexSet *fanins) + BfsBkwdIterator &iter, + VertexSet &fanins) { for (const Pin *pin : clk->leafPins()) { Vertex *vertex, *bidirect_drvr_vertex; graph_->pinVertices(pin, vertex, bidirect_drvr_vertex); - fanins->insert(vertex); - iter.enqueueAdjacentVertices(vertex); + fanins.insert(vertex); + iter.enqueueAdjacentVertices(vertex, mode_); if (bidirect_drvr_vertex) { - fanins->insert(bidirect_drvr_vertex); - iter.enqueueAdjacentVertices(bidirect_drvr_vertex); + fanins.insert(bidirect_drvr_vertex); + iter.enqueueAdjacentVertices(bidirect_drvr_vertex, mode_); } } } //////////////////////////////////////////////////////////////// -class GenClkInsertionSearchPred : public SearchPred0, public DynLoopSrchPred +class GenClkInsertionSearchPred : public SearchPred0 { public: GenClkInsertionSearchPred(Clock *gclk, - TagGroupBldr *tag_bldr, - GenclkInfo *genclk_info, - const StaState *sta); - virtual bool searchThru(Edge *edge); - virtual bool searchTo(const Vertex *to_vertex); + GenclkInfo *genclk_info, + const StaState *sta); + bool searchThru(Edge *edge, + const Mode *mode) const override; + bool searchTo(const Vertex *to_vertex, + const Mode *mode) const override; private: - bool isNonGeneratedClkPin(const Pin *pin) const; + bool isNonGeneratedClkPin(const Pin *pin, + const Sdc *sdc) const; Clock *gclk_; GenclkInfo *genclk_info_; }; GenClkInsertionSearchPred::GenClkInsertionSearchPred(Clock *gclk, - TagGroupBldr *tag_bldr, - GenclkInfo *genclk_info, - const StaState *sta) : + GenclkInfo *genclk_info, + const StaState *sta) : SearchPred0(sta), - DynLoopSrchPred(tag_bldr), gclk_(gclk), genclk_info_(genclk_info) { } bool -GenClkInsertionSearchPred::searchThru(Edge *edge) +GenClkInsertionSearchPred::searchThru(Edge *edge, + const Mode *mode) const { - const Graph *graph = sta_->graph(); - const Sdc *sdc = sta_->sdc(); - Search *search = sta_->search(); const TimingRole *role = edge->role(); - EdgeSet *fdbk_edges = genclk_info_->fdbkEdges(); - return SearchPred0::searchThru(edge) + EdgeSet &fdbk_edges = genclk_info_->fdbkEdges(); + return SearchPred0::searchThru(edge, mode) && !role->isTimingCheck() && (sta_->variables()->clkThruTristateEnabled() - || !(role == TimingRole::tristateEnable() - || role == TimingRole::tristateDisable())) - && !(fdbk_edges && fdbk_edges->hasKey(edge)) - && loopEnabled(edge, sdc, graph, search); + || !(role == TimingRole::tristateEnable() + || role == TimingRole::tristateDisable())) + && !fdbk_edges.contains(edge); } bool -GenClkInsertionSearchPred::searchTo(const Vertex *to_vertex) +GenClkInsertionSearchPred::searchTo(const Vertex *to_vertex, + const Mode *mode) const { Pin *to_pin = to_vertex->pin(); - return SearchPred0::searchTo(to_vertex) + return SearchPred0::searchTo(to_vertex, mode) // Propagate through other generated clock roots but not regular // clock roots. - && !(!gclk_->leafPins().hasKey(to_pin) - && isNonGeneratedClkPin(to_pin)) - && genclk_info_->fanins()->hasKey(const_cast(to_vertex)); + && !(!gclk_->leafPins().contains(to_pin) + && isNonGeneratedClkPin(to_pin, mode->sdc())) + && genclk_info_->fanins().contains(const_cast(to_vertex)); } bool -GenClkInsertionSearchPred::isNonGeneratedClkPin(const Pin *pin) const +GenClkInsertionSearchPred::isNonGeneratedClkPin(const Pin *pin, + const Sdc *sdc) const { - const Sdc *sdc = sta_->sdc(); ClockSet *clks = sdc->findLeafPinClocks(pin); if (clks) { - ClockSet::Iterator clk_iter(clks); - while (clk_iter.hasNext()) { - const Clock *clk = clk_iter.next(); + for (const Clock *clk : *clks) { if (!clk->isGenerated()) - return true; + return true; } } return false; @@ -525,7 +467,7 @@ Genclks::findInsertionDelays(Clock *gclk) gclk->name()); GenclkInfo *genclk_info = makeGenclkInfo(gclk); FilterPath *src_filter = genclk_info->srcFilter(); - GenClkInsertionSearchPred srch_pred(gclk, nullptr, genclk_info, this); + GenClkInsertionSearchPred srch_pred(gclk, genclk_info, this); BfsFwdIterator insert_iter(BfsIndex::other, &srch_pred, this); seedSrcPins(gclk, src_filter, insert_iter); // Propagate arrivals to generated clk root pin level. @@ -533,46 +475,41 @@ Genclks::findInsertionDelays(Clock *gclk) // Unregister the filter so that it is not triggered by other searches. // The exception itself has to stick around because the source path // tags reference it. - sdc_->unrecordException(src_filter); + mode_->sdc()->unrecordException(src_filter); } GenclkInfo * Genclks::makeGenclkInfo(Clock *gclk) { - FilterPath *src_filter = makeSrcFilter(gclk); + FilterPath *src_filter = makeSrcFilter(gclk, mode_->sdc()); Level gclk_level = clkPinMaxLevel(gclk); - VertexSet *fanins = new VertexSet(graph_); - findFanin(gclk, fanins); - GenclkInfo *genclk_info = new GenclkInfo(gclk, gclk_level, fanins, - src_filter); - genclk_info_map_.insert(gclk, genclk_info); + GenclkInfo *genclk_info = new GenclkInfo(gclk, gclk_level, src_filter, this); + findFanin(gclk, genclk_info->fanins()); + genclk_info_map_[gclk] = genclk_info; return genclk_info; } GenclkInfo * Genclks::genclkInfo(const Clock *gclk) const { - return genclk_info_map_.findKey(const_cast(gclk)); + return findKey(genclk_info_map_, const_cast(gclk)); } FilterPath * Genclks::srcFilter(Clock *gclk) { - GenclkInfo *genclk_info = genclk_info_map_.findKey(gclk); + GenclkInfo *genclk_info = findKey(genclk_info_map_, gclk); if (genclk_info) return genclk_info->srcFilter(); else return nullptr; } -EdgeSet * +EdgeSet & Genclks::latchFdbkEdges(const Clock *clk) { GenclkInfo *genclk_info = genclkInfo(clk); - if (genclk_info) - return genclk_info->fdbkEdges(); - else - return nullptr; + return genclk_info->fdbkEdges(); } void @@ -595,79 +532,77 @@ Genclks::findLatchFdbkEdges(const Clock *clk) // D to Q edge is encountered in the BFS arrival search. void Genclks::findLatchFdbkEdges(const Clock *gclk, - GenclkInfo *genclk_info) + GenclkInfo *genclk_info) { Level gclk_level = genclk_info->gclkLevel(); - EdgeSet *fdbk_edges = nullptr; + EdgeSet &fdbk_edges = genclk_info->fdbkEdges(); for (const Pin *pin : gclk->masterClk()->leafPins()) { Vertex *vertex = graph_->pinDrvrVertex(pin); - VertexSet path_vertices(graph_); - VertexSet visited_vertices(graph_); + VertexSet path_vertices = makeVertexSet(this); + VertexSet visited_vertices = makeVertexSet(this); SearchPred1 srch_pred(this); findLatchFdbkEdges(vertex, gclk_level, srch_pred, path_vertices, - visited_vertices, fdbk_edges); + visited_vertices, fdbk_edges); } - genclk_info->setLatchFdbkEdges(fdbk_edges); genclk_info->setFoundLatchFdbkEdges(true); } void Genclks::findLatchFdbkEdges(Vertex *from_vertex, - Level gclk_level, - SearchPred &srch_pred, - VertexSet &path_vertices, - VertexSet &visited_vertices, - EdgeSet *&fdbk_edges) + Level gclk_level, + SearchPred &srch_pred, + VertexSet &path_vertices, + VertexSet &visited_vertices, + EdgeSet &fdbk_edges) { - if (!visited_vertices.hasKey(from_vertex)) { + if (!visited_vertices.contains(from_vertex)) { visited_vertices.insert(from_vertex); path_vertices.insert(from_vertex); VertexOutEdgeIterator edge_iter(from_vertex, graph_); while (edge_iter.hasNext()) { Edge *edge = edge_iter.next(); Vertex *to_vertex = edge->to(graph_); - if (path_vertices.hasKey(to_vertex)) { - debugPrint(debug_, "genclk", 2, " found feedback edge %s", + if (path_vertices.contains(to_vertex)) { + debugPrint(debug_, "genclk", 2, " found feedback edge %s", edge->to_string(this).c_str()); - if (fdbk_edges == nullptr) - fdbk_edges = new EdgeSet; - fdbk_edges->insert(edge); + fdbk_edges.insert(edge); } - else if (srch_pred.searchThru(edge) - && srch_pred.searchTo(to_vertex) - && to_vertex->level() <= gclk_level) - findLatchFdbkEdges(to_vertex, gclk_level, srch_pred, - path_vertices, visited_vertices, fdbk_edges); + else if (srch_pred.searchThru(edge, mode_) + && srch_pred.searchTo(to_vertex, mode_) + && to_vertex->level() <= gclk_level) + findLatchFdbkEdges(to_vertex, gclk_level, srch_pred, + path_vertices, visited_vertices, fdbk_edges); } path_vertices.erase(from_vertex); } } FilterPath * -Genclks::makeSrcFilter(Clock *gclk) +Genclks::makeSrcFilter(Clock *gclk, + Sdc *sdc) { ClockSet *from_clks = new ClockSet; from_clks->insert(gclk->masterClk()); const RiseFallBoth *rf = RiseFallBoth::riseFall(); - ExceptionFrom *from = sdc_->makeExceptionFrom(nullptr,from_clks,nullptr,rf); + ExceptionFrom *from = sdc->makeExceptionFrom(nullptr,from_clks,nullptr,rf); PinSet *thru_pins = new PinSet(network_); thru_pins->insert(gclk->srcPin()); - ExceptionThru *thru = sdc_->makeExceptionThru(thru_pins,nullptr,nullptr,rf); + ExceptionThru *thru = sdc->makeExceptionThru(thru_pins,nullptr,nullptr,rf); ExceptionThruSeq *thrus = new ExceptionThruSeq; thrus->push_back(thru); ClockSet *to_clks = new ClockSet; to_clks->insert(gclk); - ExceptionTo *to = sdc_->makeExceptionTo(nullptr, to_clks, nullptr, rf, rf); + ExceptionTo *to = sdc->makeExceptionTo(nullptr, to_clks, nullptr, rf, rf); - return sdc_->makeFilterPath(from, thrus, to); + return sdc->makeFilterPath(from, thrus, to); } void Genclks::seedSrcPins(Clock *gclk, - FilterPath *src_filter, - BfsFwdIterator &insert_iter) + FilterPath *src_filter, + BfsFwdIterator &insert_iter) { Clock *master_clk = gclk->masterClk(); for (const Pin *master_pin : master_clk->leafPins()) { @@ -678,31 +613,33 @@ Genclks::seedSrcPins(Clock *gclk, TagGroupBldr tag_bldr(true, this); tag_bldr.init(vertex); copyGenClkSrcPaths(vertex, &tag_bldr); - for (auto path_ap : corners_->pathAnalysisPts()) { - const MinMax *min_max = path_ap->pathMinMax(); - const EarlyLate *early_late = min_max; - for (const RiseFall *rf : RiseFall::range()) { - Arrival insert = search_->clockInsertion(master_clk, master_pin, rf, - min_max, early_late, path_ap); - Tag *tag = makeTag(gclk, master_clk, master_pin, rf, - src_filter, insert, path_ap); - tag_bldr.setArrival(tag, insert); + for (Scene *scene : mode_->scenes()) { + for (const MinMax *min_max : MinMax::range()) { + const EarlyLate *early_late = min_max; + for (const RiseFall *rf : RiseFall::range()) { + Arrival insert = search_->clockInsertion(master_clk, master_pin, rf, + min_max, early_late, mode_); + Tag *tag = makeTag(gclk, master_clk, master_pin, rf, + src_filter, insert, scene, min_max); + tag_bldr.setArrival(tag, insert); + } } + search_->setVertexArrivals(vertex, &tag_bldr); + insert_iter.enqueueAdjacentVertices(vertex, mode_); } - search_->setVertexArrivals(vertex, &tag_bldr); - insert_iter.enqueueAdjacentVertices(vertex); } } } Tag * Genclks::makeTag(const Clock *gclk, - const Clock *master_clk, - const Pin *master_pin, - const RiseFall *master_rf, - FilterPath *src_filter, + const Clock *master_clk, + const Pin *master_pin, + const RiseFall *master_rf, + FilterPath *src_filter, Arrival insert, - const PathAnalysisPt *path_ap) + Scene *scene, + const MinMax *min_max) { ExceptionState *state = src_filter->firstState(); // If the src pin is one of the master pins the filter is active @@ -711,101 +648,115 @@ Genclks::makeTag(const Clock *gclk, state = state->nextState(); ExceptionStateSet *states = new ExceptionStateSet(); states->insert(state); - const ClkInfo *clk_info = search_->findClkInfo(master_clk->edge(master_rf), - master_pin, true, nullptr, true, - nullptr, insert, 0.0, nullptr, - path_ap, nullptr); - return search_->findTag(master_rf, path_ap, clk_info, false, - nullptr, false, states, true, nullptr); + const ClkInfo *clk_info = search_->findClkInfo(scene, + master_clk->edge(master_rf), + master_pin, true, nullptr, true, + nullptr, insert, 0.0, nullptr, + min_max, nullptr); + return search_->findTag(scene, master_rf, min_max, clk_info, + false, nullptr, false, states, true, nullptr); } class GenClkArrivalSearchPred : public EvalPred { public: GenClkArrivalSearchPred(Clock *gclk, - const StaState *sta); - bool searchThru(Edge *edge); - virtual bool searchTo(const Vertex *to_vertex); + const StaState *sta); + bool searchThru(Edge *edge, + const Mode *mode) const override; + bool searchTo(const Vertex *to_vertex, + const Mode *mode) const override; private: bool combinational_; }; GenClkArrivalSearchPred::GenClkArrivalSearchPred(Clock *gclk, - const StaState *sta) : + const StaState *sta) : EvalPred(sta), combinational_(gclk->combinational()) { } bool -GenClkArrivalSearchPred::searchThru(Edge *edge) +GenClkArrivalSearchPred::searchThru(Edge *edge, + const Mode *mode) const { const TimingRole *role = edge->role(); - return EvalPred::searchThru(edge) + return EvalPred::searchThru(edge, mode) && (role == TimingRole::combinational() - || role->isWire() - || !combinational_) + || role->isWire() + || !combinational_) && (sta_->variables()->clkThruTristateEnabled() - || !(role == TimingRole::tristateEnable() - || role == TimingRole::tristateDisable())); + || !(role == TimingRole::tristateEnable() + || role == TimingRole::tristateDisable())); } // Override EvalPred::searchTo to search to generated clock pin. bool -GenClkArrivalSearchPred::searchTo(const Vertex *to_vertex) +GenClkArrivalSearchPred::searchTo(const Vertex *to_vertex, + const Mode *mode) const { - return SearchPred0::searchTo(to_vertex); + return SearchPred0::searchTo(to_vertex, mode); } class GenclkSrcArrivalVisitor : public ArrivalVisitor { public: GenclkSrcArrivalVisitor(Clock *gclk, - BfsFwdIterator *insert_iter, - GenclkInfo *genclk_info, - const StaState *sta); + BfsFwdIterator *insert_iter, + GenclkInfo *genclk_info, + const Mode *mode); virtual VertexVisitor *copy() const; virtual void visit(Vertex *vertex); protected: GenclkSrcArrivalVisitor(Clock *gclk, - BfsFwdIterator *insert_iter, - GenclkInfo *genclk_info, - bool always_to_endpoints, - SearchPred *pred, - const StaState *sta); + BfsFwdIterator *insert_iter, + GenclkInfo *genclk_info, + bool always_to_endpoints, + SearchPred *pred, + const Mode *mode); Clock *gclk_; BfsFwdIterator *insert_iter_; GenclkInfo *genclk_info_; GenClkInsertionSearchPred srch_pred_; + const Mode *mode_; + const Sdc *sdc_; + Genclks *genclks_; }; GenclkSrcArrivalVisitor::GenclkSrcArrivalVisitor(Clock *gclk, - BfsFwdIterator *insert_iter, - GenclkInfo *genclk_info, - const StaState *sta): - ArrivalVisitor(sta), + BfsFwdIterator *insert_iter, + GenclkInfo *genclk_info, + const Mode *mode): + ArrivalVisitor(mode), gclk_(gclk), insert_iter_(insert_iter), genclk_info_(genclk_info), - srch_pred_(gclk_, tag_bldr_, genclk_info, sta) + srch_pred_(gclk_, genclk_info, mode), + mode_(mode), + sdc_(mode->sdc()), + genclks_(mode->genclks()) { } // Copy constructor. GenclkSrcArrivalVisitor::GenclkSrcArrivalVisitor(Clock *gclk, - BfsFwdIterator *insert_iter, - GenclkInfo *genclk_info, - bool always_to_endpoints, - SearchPred *pred, - const StaState *sta) : - ArrivalVisitor(always_to_endpoints, pred, sta), + BfsFwdIterator *insert_iter, + GenclkInfo *genclk_info, + bool always_to_endpoints, + SearchPred *pred, + const Mode *mode) : + ArrivalVisitor(always_to_endpoints, pred, mode), gclk_(gclk), insert_iter_(insert_iter), genclk_info_(genclk_info), - srch_pred_(gclk, tag_bldr_, genclk_info, sta) + srch_pred_(gclk, genclk_info, mode), + mode_(mode), + sdc_(mode->sdc()), + genclks_(mode->genclks()) { } @@ -813,33 +764,32 @@ VertexVisitor * GenclkSrcArrivalVisitor::copy() const { return new GenclkSrcArrivalVisitor(gclk_, insert_iter_, genclk_info_, - always_to_endpoints_, pred_, this); + always_to_endpoints_, pred_, mode_); } void GenclkSrcArrivalVisitor::visit(Vertex *vertex) { - Genclks *genclks = search_->genclks(); debugPrint(debug_, "genclk", 2, "find gen clk insert arrival %s", vertex->to_string(this).c_str()); tag_bldr_->init(vertex); has_fanin_one_ = graph_->hasFaninOne(vertex); - genclks->copyGenClkSrcPaths(vertex, tag_bldr_); + genclks_->copyGenClkSrcPaths(vertex, tag_bldr_); visitFaninPaths(vertex); // Propagate beyond the clock tree to reach generated clk roots. - insert_iter_->enqueueAdjacentVertices(vertex, &srch_pred_); + insert_iter_->enqueueAdjacentVertices(vertex, &srch_pred_, mode_); search_->setVertexArrivals(vertex, tag_bldr_); } void Genclks::findSrcArrivals(Clock *gclk, - BfsFwdIterator &insert_iter, - GenclkInfo *genclk_info) + BfsFwdIterator &insert_iter, + GenclkInfo *genclk_info) { GenClkArrivalSearchPred eval_pred(gclk, this); GenclkSrcArrivalVisitor arrival_visitor(gclk, &insert_iter, - genclk_info, this); - arrival_visitor.init(true, &eval_pred); + genclk_info, mode_); + arrival_visitor.init(true, false, &eval_pred); // This cannot restrict the search level because loops in the clock tree // can circle back to the generated clock src pin. // Parallel visit is slightly slower (at last check). @@ -849,7 +799,7 @@ Genclks::findSrcArrivals(Clock *gclk, // Copy generated clock source paths to tag_bldr. void Genclks::copyGenClkSrcPaths(Vertex *vertex, - TagGroupBldr *tag_bldr) + TagGroupBldr *tag_bldr) { auto itr = vertex_src_paths_map_.find(vertex); if (itr != vertex_src_paths_map_.end()) { @@ -863,8 +813,8 @@ Genclks::copyGenClkSrcPaths(Vertex *vertex, } debugPrint(debug_, "genclk", 3, "vertex %s insert genclk %s src path %s %ss", src_path.vertex(this)->to_string(this).c_str(), - src_path.tag(this)->genClkSrcPathClk(this)->name(), - src_path.tag(this)->pathAnalysisPt(this)->pathMinMax()->to_string().c_str(), + src_path.tag(this)->genClkSrcPathClk()->name(), + src_path.tag(this)->minMax()->to_string().c_str(), src_path.tag(this)->to_string(true, false, this).c_str()); tag_bldr->insertPath(src_path); } @@ -876,25 +826,25 @@ Genclks::copyGenClkSrcPaths(Vertex *vertex, void Genclks::clearSrcPaths() { - for (auto const & [clk_pin, src_paths] : genclk_src_paths_) { - for (const Path &src_path : src_paths) - delete src_path.prevPath(); + for (auto [vertex, paths] : vertex_src_paths_map_) { + for (const Path *path : paths) + delete path; } + vertex_src_paths_map_.clear(); genclk_src_paths_.clear(); } size_t Genclks::srcPathIndex(const RiseFall *clk_rf, - const PathAnalysisPt *path_ap) const + const MinMax *min_max) const { - return path_ap->index() * RiseFall::index_count + clk_rf->index(); + return min_max->index() * RiseFall::index_count + clk_rf->index(); } void Genclks::recordSrcPaths(Clock *gclk) { - int path_count = RiseFall::index_count - * corners_->pathAnalysisPtCount(); + size_t path_count = RiseFall::index_count * MinMax::index_count; bool divide_by_1 = gclk->isDivideByOneCombinational(); bool invert = gclk->invert(); @@ -904,70 +854,64 @@ Genclks::recordSrcPaths(Clock *gclk) std::vector &src_paths = genclk_src_paths_[ClockPinPair(gclk, gclk_pin)]; src_paths.resize(path_count); Vertex *gclk_vertex = srcPath(gclk_pin); - bool found_src_paths = false; VertexPathIterator path_iter(gclk_vertex, this); while (path_iter.hasNext()) { Path *path = path_iter.next(); const ClockEdge *src_clk_edge = path->clkEdge(this); if (src_clk_edge - && matchesSrcFilter(path, gclk)) { - const EarlyLate *early_late = path->minMax(this); - const RiseFall *src_clk_rf = src_clk_edge->transition(); - const RiseFall *rf = path->transition(this); - bool inverting_path = (rf != src_clk_rf); - const PathAnalysisPt *path_ap = path->pathAnalysisPt(this); - size_t path_index = srcPathIndex(rf, path_ap); - Path &src_path = src_paths[path_index]; - if ((!divide_by_1 + && matchesSrcFilter(path, gclk)) { + const EarlyLate *early_late = path->minMax(this); + const RiseFall *src_clk_rf = src_clk_edge->transition(); + const RiseFall *rf = path->transition(this); + bool inverting_path = (rf != src_clk_rf); + size_t path_index = srcPathIndex(rf, path->minMax(this)); + Path &src_path = src_paths[path_index]; + if ((!divide_by_1 || (inverting_path == invert)) - && (!has_edges - || src_clk_rf == gclk->masterClkEdgeTr(rf)) - && (src_path.isNull() - || delayGreater(path->arrival(), - src_path.arrival(), - early_late, - this))) { - debugPrint(debug_, "genclk", 2, " %s insertion %s %s %s", + && (!has_edges + || src_clk_rf == gclk->masterClkEdgeTr(rf)) + && (src_path.isNull() + || delayGreater(path->arrival(), + src_path.arrival(), + early_late, + this))) { + debugPrint(debug_, "genclk", 2, " %s insertion %s %s %s", network_->pathName(gclk_pin), early_late->to_string().c_str(), rf->to_string().c_str(), delayAsString(path->arrival(), this)); - // If this path is replacing another one delete the previous one. - delete src_path.prevPath(); src_path = *path; - Path *prev_copy = &src_path; - Path *p = path->prevPath(); - while (p) { - Path *copy = new Path(p); - copy->setIsEnum(true); - prev_copy->setPrevPath(copy); - prev_copy = copy; - p = p->prevPath(); - } - found_src_paths = true; - } - } - } - if (found_src_paths) { - // Record vertex->genclk src paths. - for (const Path &path : src_paths) { - if (!path.isNull()) { - const Path *p = &path; - while (p && !p->isNull()) { - Vertex *vertex = p->vertex(this); - vertex_src_paths_map_[vertex].push_back(p); - p = p->prevPath(); - } } } } + // Record vertex->genclk src paths. + bool found_src_paths = false; + for (size_t path_index = 0; path_index < path_count; path_index++) { + Path &src_path = src_paths[path_index]; + if (!src_path.isNull()) { + Path *prev_copy = &src_path; + const Path *p = src_path.prevPath(); + while (p) { + Path *copy = new Path(p); + copy->setIsEnum(true); + prev_copy->setPrevPath(copy); + prev_copy = copy; + + Vertex *vertex = p->vertex(this); + vertex_src_paths_map_[vertex].push_back(copy); + p = p->prevPath(); + } + found_src_paths = true; + } + } // Don't warn if the master clock is ideal. - else if (gclk->masterClk() - && gclk->masterClk()->isPropagated()) + if (!found_src_paths + && gclk->masterClk() + && gclk->masterClk()->isPropagated()) report_->warn(1062, "generated clock %s source pin %s missing paths from master clock %s.", - gclk->name(), - network_->pathName(gclk_pin), - gclk->masterClk()->name()); + gclk->name(), + network_->pathName(gclk_pin), + gclk->masterClk()->name()); } deleteGenclkSrcPaths(gclk); } @@ -976,7 +920,7 @@ void Genclks:: deleteGenclkSrcPaths(Clock *gclk) { GenclkInfo *genclk_info = genclkInfo(gclk); - GenClkInsertionSearchPred srch_pred(gclk, nullptr, genclk_info, this); + GenClkInsertionSearchPred srch_pred(gclk, genclk_info, mode_); BfsFwdIterator insert_iter(BfsIndex::other, &srch_pred, this); FilterPath *src_filter = genclk_info->srcFilter(); seedSrcPins(gclk, src_filter, insert_iter); @@ -984,27 +928,25 @@ Genclks:: deleteGenclkSrcPaths(Clock *gclk) while (insert_iter.hasNext()) { Vertex *vertex = insert_iter.next(); search_->deletePaths(vertex); - insert_iter.enqueueAdjacentVertices(vertex, &srch_pred); + insert_iter.enqueueAdjacentVertices(vertex, &srch_pred, mode_); } } bool Genclks::matchesSrcFilter(Path *path, - const Clock *gclk) const + const Clock *gclk) const { Tag *tag = path->tag(this); const ExceptionStateSet *states = tag->states(); if (tag->isGenClkSrcPath() && states) { - ExceptionStateSet::ConstIterator state_iter(states); - while (state_iter.hasNext()) { - ExceptionState *state = state_iter.next(); + for (ExceptionState *state : *states) { ExceptionPath *except = state->exception(); if (except->isFilter() - && state->nextThru() == nullptr - && except->to() - && except->to()->matches(gclk)) - return true; + && state->nextThru() == nullptr + && except->to() + && except->to()->matches(gclk)) + return true; } } return false; @@ -1015,32 +957,31 @@ Genclks::srcPath(const Path *clk_path) const { const Pin *src_pin = clk_path->pin(this); const ClockEdge *clk_edge = clk_path->clkEdge(this); - const PathAnalysisPt *path_ap = clk_path->pathAnalysisPt(this); const EarlyLate *early_late = clk_path->minMax(this); - PathAnalysisPt *insert_ap = path_ap->insertionAnalysisPt(early_late); - return srcPath(clk_edge->clock(), src_pin, clk_edge->transition(), - insert_ap); + return srcPath(clk_edge->clock(), src_pin, + clk_edge->transition(), early_late); } const Path * Genclks::srcPath(const ClockEdge *clk_edge, - const Pin *src_pin, - const PathAnalysisPt *path_ap) const + const Pin *src_pin, + const MinMax *min_max) const { - return srcPath(clk_edge->clock(), src_pin, clk_edge->transition(), path_ap); + return srcPath(clk_edge->clock(), src_pin, + clk_edge->transition(), min_max); } const Path * Genclks::srcPath(const Clock *gclk, - const Pin *src_pin, - const RiseFall *rf, - const PathAnalysisPt *path_ap) const + const Pin *src_pin, + const RiseFall *rf, + const MinMax *min_max) const { auto itr = genclk_src_paths_.find(ClockPinPair(gclk, src_pin)); if (itr != genclk_src_paths_.end()) { const std::vector &src_paths = itr->second; if (!src_paths.empty()) { - size_t path_index = srcPathIndex(rf, path_ap); + size_t path_index = srcPathIndex(rf, min_max); const Path *src_path = &src_paths[path_index]; if (!src_path->isNull()) return src_path; @@ -1051,13 +992,11 @@ Genclks::srcPath(const Clock *gclk, Arrival Genclks::insertionDelay(const Clock *clk, - const Pin *pin, - const RiseFall *rf, - const EarlyLate *early_late, - const PathAnalysisPt *path_ap) const + const Pin *pin, + const RiseFall *rf, + const EarlyLate *early_late) const { - PathAnalysisPt *insert_ap = path_ap->insertionAnalysisPt(early_late); - const Path *src_path = srcPath(clk, pin, rf, insert_ap); + const Path *src_path = srcPath(clk, pin, rf, early_late); if (src_path) return src_path->arrival(); else @@ -1068,7 +1007,7 @@ Genclks::insertionDelay(const Clock *clk, bool ClockPinPairLess::operator()(const ClockPinPair &pair1, - const ClockPinPair &pair2) const + const ClockPinPair &pair2) const { const Clock *clk1 = pair1.first; @@ -1078,8 +1017,8 @@ ClockPinPairLess::operator()(const ClockPinPair &pair1, const Pin *pin1 = pair1.second; const Pin *pin2 = pair2.second; return (clk_index1 < clk_index2 - || (clk_index1 == clk_index2 - && pin1 < pin2)); + || (clk_index1 == clk_index2 + && pin1 < pin2)); } class ClockPinPairHash @@ -1107,12 +1046,12 @@ class ClockPinPairEqual { public: bool operator()(const ClockPinPair &pair1, - const ClockPinPair &pair2) const; + const ClockPinPair &pair2) const; }; bool ClockPinPairEqual::operator()(const ClockPinPair &pair1, - const ClockPinPair &pair2) const + const ClockPinPair &pair2) const { return pair1.first == pair2.first diff --git a/search/Genclks.hh b/search/Genclks.hh index 0f69f5f0..b3da5bbd 100644 --- a/search/Genclks.hh +++ b/search/Genclks.hh @@ -24,7 +24,8 @@ #pragma once -#include "Map.hh" +#include + #include "Transition.hh" #include "NetworkClass.hh" #include "Graph.hh" @@ -40,51 +41,53 @@ class BfsBkwdIterator; class SearchPred; class TagGroupBldr; -typedef std::pair ClockPinPair; +using ClockPinPair = std::pair; class ClockPinPairLess { public: bool operator()(const ClockPinPair &pair1, - const ClockPinPair &pair2) const; + const ClockPinPair &pair2) const; }; -typedef Map GenclkInfoMap; -typedef Map, ClockPinPairLess> GenclkSrcPathMap; -typedef std::map, VertexIdLess> VertexGenclkSrcPathsMap; +using GenclkInfoMap = std::map; +using GenclkSrcPathMap = std::map, ClockPinPairLess>; +using VertexGenclkSrcPathsMap = std::map, VertexIdLess>; class Genclks : public StaState { public: - Genclks(StaState *sta); - ~Genclks(); + Genclks(const Mode *mode, + StaState *sta); + virtual ~Genclks(); void clear(); void ensureInsertionDelays(); VertexSet *fanins(const Clock *clk); void findLatchFdbkEdges(const Clock *clk); - EdgeSet *latchFdbkEdges(const Clock *clk); - void checkMaster(Clock *gclk); - void ensureMaster(Clock *gclk); + EdgeSet &latchFdbkEdges(const Clock *clk); + void checkMaster(Clock *gclk, + const Sdc *sdc); + void ensureMaster(Clock *gclk, + const Sdc *sdc); // Generated clock insertion delay. Arrival insertionDelay(const Clock *clk, - const Pin *pin, - const RiseFall *rf, - const EarlyLate *early_late, - const PathAnalysisPt *path_ap) const; + const Pin *pin, + const RiseFall *rf, + const EarlyLate *early_late) const; // Generated clock source path for a clock path root. const Path *srcPath(const Path *clk_path) const; // Generated clock source path. const Path *srcPath(const ClockEdge *clk_edge, const Pin *src_pin, - const PathAnalysisPt *path_ap) const; + const MinMax *min_max) const; const Path *srcPath(const Clock *clk, const Pin *src_pin, const RiseFall *rf, - const PathAnalysisPt *path_ap) const; + const MinMax *min_max) const; Vertex *srcPath(const Pin *pin) const; Level clkPinMaxLevel(const Clock *clk) const; void copyGenClkSrcPaths(Vertex *vertex, - TagGroupBldr *tag_bldr); + TagGroupBldr *tag_bldr); private: void findInsertionDelays(); @@ -93,45 +96,47 @@ private: void recordSrcPaths(Clock *gclk); void findInsertionDelays(Clock *gclk); void seedClkVertices(Clock *clk, - BfsBkwdIterator &iter, - VertexSet *fanins); + BfsBkwdIterator &iter, + VertexSet &dfanins); size_t srcPathIndex(const RiseFall *clk_rf, - const PathAnalysisPt *path_ap) const; + const MinMax *min_max) const; bool matchesSrcFilter(Path *path, - const Clock *gclk) const; + const Clock *gclk) const; void seedSrcPins(Clock *gclk, - FilterPath *src_filter, - BfsFwdIterator &insert_iter); + FilterPath *src_filter, + BfsFwdIterator &insert_iter); void findSrcArrivals(Clock *gclk, - BfsFwdIterator &insert_iter, - GenclkInfo *genclk_info); - virtual FilterPath *makeSrcFilter(Clock *gclk); + BfsFwdIterator &insert_iter, + GenclkInfo *genclk_info); + FilterPath *makeSrcFilter(Clock *gclk, + Sdc *sdc); void deleteGenClkInfo(); virtual Tag *makeTag(const Clock *gclk, - const Clock *master_clk, - const Pin *master_pin, - const RiseFall *rf, - FilterPath *src_filter, + const Clock *master_clk, + const Pin *master_pin, + const RiseFall *rf, + FilterPath *src_filter, Arrival insert, - const PathAnalysisPt *path_ap); + Scene *scene, + const MinMax *min_max); void seedSrcPins(Clock *clk, - BfsBkwdIterator &iter); + BfsBkwdIterator &iter); void findInsertionDelay(Clock *gclk); GenclkInfo *makeGenclkInfo(Clock *gclk); FilterPath *srcFilter(Clock *gclk); void findFanin(Clock *gclk, - // Return value. - VertexSet *fanins); + VertexSet &fanins); void findLatchFdbkEdges(const Clock *clk, - GenclkInfo *genclk_info); + GenclkInfo *genclk_info); void findLatchFdbkEdges(Vertex *vertex, - Level gclk_level, - SearchPred &srch_pred, - VertexSet &path_vertices, - VertexSet &visited_vertices, - EdgeSet *&fdbk_edges); + Level gclk_level, + SearchPred &srch_pred, + VertexSet &path_vertices, + VertexSet &visited_vertices, + EdgeSet &fdbk_edges); void deleteGenclkSrcPaths(Clock *gclk); + const Mode *mode_; bool found_insertion_delays_; GenclkSrcPathMap genclk_src_paths_; GenclkInfoMap genclk_info_map_; diff --git a/search/Latches.cc b/search/Latches.cc index 73ffa95c..3c113c51 100644 --- a/search/Latches.cc +++ b/search/Latches.cc @@ -32,11 +32,11 @@ #include "Graph.hh" #include "ExceptionPath.hh" #include "Sdc.hh" +#include "Mode.hh" #include "ClkInfo.hh" #include "Tag.hh" #include "Sim.hh" #include "PathEnd.hh" -#include "PathAnalysisPt.hh" #include "Search.hh" #include "Crpr.hh" @@ -49,18 +49,19 @@ Latches::Latches(StaState *sta) : void Latches::latchRequired(const Path *data_path, - const Path *enable_path, - const Path *disable_path, - const MultiCyclePath *mcp, - const PathDelay *path_delay, - Arrival src_clk_latency, - const ArcDelay &margin, - // Return values. - Required &required, - Arrival &borrow, - Arrival &adjusted_data_arrival, - Delay &time_given_to_startpoint) const + const Path *enable_path, + const Path *disable_path, + const MultiCyclePath *mcp, + const PathDelay *path_delay, + Arrival src_clk_latency, + const ArcDelay &margin, + // Return values. + Required &required, + Arrival &borrow, + Arrival &adjusted_data_arrival, + Delay &time_given_to_startpoint) const { + Sdc *sdc = data_path->sdc(this); const Arrival data_arrival = data_path->arrival(); float max_delay = 0.0; bool ignore_clk_latency = false; @@ -82,18 +83,18 @@ Latches::latchRequired(const Path *data_path, Crpr open_crpr, crpr_diff; bool borrow_limit_exists; latchBorrowInfo(data_path, enable_path, disable_path, margin, - ignore_clk_latency, - nom_pulse_width, open_latency, latency_diff, - open_uncertainty, open_crpr, crpr_diff, max_borrow, - borrow_limit_exists); + ignore_clk_latency, + nom_pulse_width, open_latency, latency_diff, + open_uncertainty, open_crpr, crpr_diff, max_borrow, + borrow_limit_exists); const ClockEdge *data_clk_edge = data_path->clkEdge(this); const ClockEdge *enable_clk_edge = enable_path->clkEdge(this); const TimingRole *check_role = enable_path->clkInfo(this)->isPulseClk() ? TimingRole::setup() : TimingRole::latchSetup(); - CycleAccting *acct = sdc_->cycleAccting(data_clk_edge, - enable_clk_edge); + CycleAccting *acct = sdc->cycleAccting(data_clk_edge, + enable_clk_edge); // checkTgtClkTime float tgt_clk_time = path_delay ? 0.0 : acct->requiredTime(check_role); // checkTgtClkArrival broken down into components. @@ -102,7 +103,7 @@ Latches::latchRequired(const Path *data_path, + open_latency + open_uncertainty + PathEnd::checkSetupMcpAdjustment(data_clk_edge, enable_clk_edge, mcp, - 1, sdc_) + 1, sdc) + open_crpr; debugPrint(debug_, "latch", 1, "data %s enable %s", delayAsString(data_arrival, this), @@ -118,10 +119,10 @@ Latches::latchRequired(const Path *data_path, // Data arrives while latch is transparent. borrow = data_arrival - enable_arrival; if (delayLessEqual(borrow, max_borrow, this)) - required = data_arrival; + required = data_arrival; else { - borrow = max_borrow; - required = enable_arrival + max_borrow; + borrow = max_borrow; + required = enable_arrival + max_borrow; } time_given_to_startpoint = borrow + open_uncertainty + open_crpr; @@ -129,7 +130,7 @@ Latches::latchRequired(const Path *data_path, // data clock zeroth cycle. The data departs the latch // with respect to the enable clock zeroth cycle. float data_shift_to_enable_clk = acct->sourceTimeOffset(check_role) - - acct->targetTimeOffset(check_role); + - acct->targetTimeOffset(check_role); adjusted_data_arrival = required + data_shift_to_enable_clk; } } @@ -147,29 +148,30 @@ Latches::latchRequired(const Path *data_path, time_given_to_startpoint = 0.0; } debugPrint(debug_, "latch", 2, "req %s borrow %s time_given %s adj_arrival %s", - delayAsString(required, this), - delayAsString(borrow, this), - delayAsString(time_given_to_startpoint, this), - delayAsString(adjusted_data_arrival, this)); + delayAsString(required, this), + delayAsString(borrow, this), + delayAsString(time_given_to_startpoint, this), + delayAsString(adjusted_data_arrival, this)); } void Latches::latchBorrowInfo(const Path *data_path, - const Path *enable_path, - const Path *disable_path, - const ArcDelay &margin, - bool ignore_clk_latency, - // Return values. - float &nom_pulse_width, - Delay &open_latency, - Delay &latency_diff, - float &open_uncertainty, - Crpr &open_crpr, - Crpr &crpr_diff, - Delay &max_borrow, - bool &borrow_limit_exists) const + const Path *enable_path, + const Path *disable_path, + const ArcDelay &margin, + bool ignore_clk_latency, + // Return values. + float &nom_pulse_width, + Delay &open_latency, + Delay &latency_diff, + float &open_uncertainty, + Crpr &open_crpr, + Crpr &crpr_diff, + Delay &max_borrow, + bool &borrow_limit_exists) const { if (data_path && enable_path && disable_path) { + Sdc *sdc = data_path->sdc(this); const ClockEdge *data_clk_edge = data_path->clkEdge(this); const ClockEdge *enable_clk_edge = enable_path->clkEdge(this); const ClockEdge *disable_clk_edge = disable_path->clkEdge(this); @@ -177,7 +179,7 @@ Latches::latchBorrowInfo(const Path *data_path, nom_pulse_width = is_pulse_clk ? 0.0F : enable_clk_edge->pulseWidth(); open_uncertainty = PathEnd::checkClkUncertainty(data_clk_edge, enable_clk_edge, enable_path, - TimingRole::latchSetup(), this); + TimingRole::latchSetup(), sdc); if (ignore_clk_latency) { open_latency = 0.0; latency_diff = 0.0; @@ -198,9 +200,9 @@ Latches::latchBorrowInfo(const Path *data_path, latency_diff = open_latency - close_latency; } float borrow_limit; - sdc_->latchBorrowLimit(data_path->pin(this), disable_path->pin(this), - enable_clk_edge->clock(), - borrow_limit, borrow_limit_exists); + sdc->latchBorrowLimit(data_path->pin(this), disable_path->pin(this), + enable_clk_edge->clock(), + borrow_limit, borrow_limit_exists); if (borrow_limit_exists) max_borrow = borrow_limit; else @@ -216,63 +218,64 @@ Latches::latchBorrowInfo(const Path *data_path, crpr_diff = 0.0; } debugPrint(debug_, "latch", 2, "nom_width %s open_lat %s lat_diff %s open_uncert %s", - delayAsString(nom_pulse_width, this), - delayAsString(open_latency, this), - delayAsString(latency_diff, this), - delayAsString(open_uncertainty, this)); + delayAsString(nom_pulse_width, this), + delayAsString(open_latency, this), + delayAsString(latency_diff, this), + delayAsString(open_uncertainty, this)); debugPrint(debug_, "latch", 2, "open_crpr %s crpr_diff %s open_uncert %s max_borrow %s", - delayAsString(open_crpr, this), - delayAsString(crpr_diff, this), - delayAsString(open_uncertainty, this), - borrow_limit_exists ? delayAsString(max_borrow, this) : "none"); + delayAsString(open_crpr, this), + delayAsString(crpr_diff, this), + delayAsString(open_uncertainty, this), + borrow_limit_exists ? delayAsString(max_borrow, this) : "none"); } void Latches::latchRequired(const Path *data_path, - const Path *enable_path, - const Path *disable_path, - const PathAnalysisPt *path_ap, - // Return values. - Required &required, - Arrival &borrow, - Arrival &adjusted_data_arrival, - Delay &time_given_to_startpoint) const + const Path *enable_path, + const Path *disable_path, + // Return values. + Required &required, + Arrival &borrow, + Arrival &adjusted_data_arrival, + Delay &time_given_to_startpoint) const { + Sdc *sdc = data_path->sdc(this); Vertex *data_vertex = data_path->vertex(this); const RiseFall *data_rf = data_path->transition(this); - ArcDelay setup = latchSetupMargin(data_vertex,data_rf,disable_path,path_ap); + ArcDelay setup = latchSetupMargin(data_vertex,data_rf,disable_path); ExceptionPath *excpt = search_->exceptionTo(ExceptionPathType::any, - data_path, data_vertex->pin(), - data_rf, - enable_path->clkEdge(this), - path_ap->pathMinMax(), false, - false); + data_path, data_vertex->pin(), + data_rf, + enable_path->clkEdge(this), + data_path->minMax(this), + false, false, sdc); MultiCyclePath *mcp = dynamic_cast(excpt); PathDelay *path_delay = dynamic_cast(excpt); Arrival src_clk_latency = 0.0; if (path_delay && path_delay->ignoreClkLatency()) src_clk_latency = search_->pathClkPathArrival(data_path); latchRequired(data_path, enable_path, disable_path, mcp, - path_delay, src_clk_latency, setup, - required, borrow, adjusted_data_arrival, - time_given_to_startpoint); + path_delay, src_clk_latency, setup, + required, borrow, adjusted_data_arrival, + time_given_to_startpoint); } // Find the latch enable open/close path from the close/open path. Path * -Latches::latchEnableOtherPath(const Path *path, - const PathAnalysisPt *tgt_clk_path_ap) const +Latches::latchEnableOtherPath(const Path *path) const { Vertex *vertex = path->vertex(this); const ClockEdge *clk_edge = path->clkEdge(this); const ClockEdge *other_clk_edge = path->clkInfo(this)->isPulseClk() ? clk_edge:clk_edge->opposite(); const RiseFall *other_rf = path->transition(this)->opposite(); - VertexPathIterator path_iter(vertex, other_rf, tgt_clk_path_ap, this); + VertexPathIterator path_iter(vertex, path->scene(this), + path->minMax(this), + other_rf, this); while (path_iter.hasNext()) { Path *path = path_iter.next(); if (path->isClock(this) - && path->clkEdge(this) == other_clk_edge) { + && path->clkEdge(this) == other_clk_edge) { return path; } } @@ -281,25 +284,26 @@ Latches::latchEnableOtherPath(const Path *path, Path * Latches::latchEnablePath(const Path *q_path, - const Edge *d_q_edge) const + const Edge *d_q_edge) const { const ClockEdge *en_clk_edge = q_path->clkEdge(this); - PathAnalysisPt *path_ap = q_path->pathAnalysisPt(this); - const PathAnalysisPt *tgt_clk_path_ap = path_ap->tgtClkAnalysisPt(); + const Scene *scene = q_path->scene(this); + const Mode *mode = scene->mode(); + const MinMax *tgt_min_max = q_path->tgtClkMinMax(this); const Instance *latch = network_->instance(q_path->pin(this)); Vertex *en_vertex; const RiseFall *en_rf; LatchEnableState state; - latchDtoQEnable(d_q_edge, latch, en_vertex, en_rf, state); + latchDtoQEnable(d_q_edge, latch, mode, en_vertex, en_rf, state); if (state == LatchEnableState::enabled) { - VertexPathIterator path_iter(en_vertex, en_rf, tgt_clk_path_ap, this); + VertexPathIterator path_iter(en_vertex, scene, tgt_min_max, en_rf, this); while (path_iter.hasNext()) { Path *path = path_iter.next(); const ClockEdge *clk_edge = path->clkEdge(this); if (path->isClock(this) - && clk_edge == en_clk_edge) { - return path; + && clk_edge == en_clk_edge) { + return path; } } } @@ -312,20 +316,24 @@ Latches::latchEnablePath(const Path *q_path, // the enable open edge. void Latches::latchOutArrival(const Path *data_path, - const TimingArc *d_q_arc, - const Edge *d_q_edge, - const PathAnalysisPt *path_ap, - // Return values. - Tag *&q_tag, - ArcDelay &arc_delay, - Arrival &q_arrival) + const TimingArc *d_q_arc, + const Edge *d_q_edge, + // Return values. + Tag *&q_tag, + ArcDelay &arc_delay, + Arrival &q_arrival) { + Scene *scene = data_path->scene(this); + Sdc *sdc = scene->sdc(); + const Mode *mode = scene->mode(); Vertex *data_vertex = d_q_edge->from(graph_); const Instance *inst = network_->instance(data_vertex->pin()); + const MinMax *min_max = data_path->minMax(this); + DcalcAPIndex dcalc_ap = data_path->dcalcAnalysisPtIndex(this); Vertex *enable_vertex; const RiseFall *enable_rf; LatchEnableState state; - latchDtoQEnable(d_q_edge, inst, enable_vertex, enable_rf, state); + latchDtoQEnable(d_q_edge, inst, mode, enable_vertex, enable_rf, state); // Latch enable may be missing if library is malformed. switch (state) { case LatchEnableState::closed: @@ -335,70 +343,71 @@ Latches::latchOutArrival(const Path *data_path, ExceptionPath *excpt = exceptionTo(data_path, nullptr); if (!(excpt && excpt->isFalse())) { arc_delay = search_->deratedDelay(data_vertex, d_q_arc, d_q_edge, - false, path_ap); + false, min_max, dcalc_ap, sdc); q_arrival = data_path->arrival() + arc_delay; q_tag = data_path->tag(this); } } break; case LatchEnableState::enabled: { - const PathAnalysisPt *tgt_clk_path_ap = path_ap->tgtClkAnalysisPt(); - VertexPathIterator enable_iter(enable_vertex, enable_rf, - tgt_clk_path_ap, this); + const MinMax *tgt_min_max = data_path->tgtClkMinMax(this); + VertexPathIterator enable_iter(enable_vertex, scene, tgt_min_max, + enable_rf, this); while (enable_iter.hasNext()) { Path *enable_path = enable_iter.next(); const ClkInfo *en_clk_info = enable_path->clkInfo(this); const ClockEdge *en_clk_edge = en_clk_info->clkEdge(); if (enable_path->isClock(this)) { - ExceptionPath *excpt = exceptionTo(data_path, en_clk_edge); - // D->Q is disabled when if there is a path delay -to D or EN clk. - if (!(excpt && (excpt->isFalse() - || excpt->isPathDelay()))) { - Path *disable_path = latchEnableOtherPath(enable_path, tgt_clk_path_ap); - Delay borrow, time_given_to_startpoint; - Arrival adjusted_data_arrival; - Required required; - latchRequired(data_path, enable_path, disable_path, path_ap, - required, borrow, adjusted_data_arrival, - time_given_to_startpoint); - if (delayGreater(borrow, 0.0, this)) { - // Latch is transparent when data arrives. - arc_delay = search_->deratedDelay(data_vertex, d_q_arc, d_q_edge, - false, path_ap); - q_arrival = adjusted_data_arrival + arc_delay; - // Tag switcheroo - data passing thru gets latch enable tag. - // States and path ap come from Q, everything else from enable. - Path *crpr_clk_path = crprActive() ? enable_path : nullptr; - const ClkInfo *q_clk_info = - search_->findClkInfo(en_clk_edge, - en_clk_info->clkSrc(), - en_clk_info->isPropagated(), - en_clk_info->genClkSrc(), - en_clk_info->isGenClkSrcPath(), - en_clk_info->pulseClkSense(), - en_clk_info->insertion(), - en_clk_info->latency(), - en_clk_info->uncertainties(), - path_ap, - crpr_clk_path); - const RiseFall *q_rf = d_q_arc->toEdge()->asRiseFall(); - ExceptionStateSet *states = nullptr; - // Latch data pin is a valid exception -from pin. - if (sdc_->exceptionFromStates(data_path->pin(this), - data_path->transition(this), - nullptr, nullptr, // clk below - MinMax::max(), states) - // -from enable non-filter exceptions apply. - && sdc_->exceptionFromStates(enable_vertex->pin(), - enable_rf, - en_clk_edge->clock(), - en_clk_edge->transition(), - MinMax::max(), false, states)) - q_tag = search_->findTag(q_rf, path_ap, q_clk_info, false, - nullptr, false, states, true, nullptr); - } - return; - } + ExceptionPath *excpt = exceptionTo(data_path, en_clk_edge); + // D->Q is disabled when if there is a path delay -to D or EN clk. + if (!(excpt && (excpt->isFalse() + || excpt->isPathDelay()))) { + Path *disable_path = latchEnableOtherPath(enable_path); + Delay borrow, time_given_to_startpoint; + Arrival adjusted_data_arrival; + Required required; + latchRequired(data_path, enable_path, disable_path, + required, borrow, adjusted_data_arrival, + time_given_to_startpoint); + if (delayGreater(borrow, 0.0, this)) { + // Latch is transparent when data arrives. + arc_delay = search_->deratedDelay(data_vertex, d_q_arc, d_q_edge, + false, min_max, dcalc_ap, sdc); + q_arrival = adjusted_data_arrival + arc_delay; + // Tag switcheroo - data passing thru gets latch enable tag. + // States and path ap come from Q, everything else from enable. + Path *crpr_clk_path = crprActive(mode) ? enable_path : nullptr; + const ClkInfo *q_clk_info = + search_->findClkInfo(en_clk_info->scene(), + en_clk_edge, + en_clk_info->clkSrc(), + en_clk_info->isPropagated(), + en_clk_info->genClkSrc(), + en_clk_info->isGenClkSrcPath(), + en_clk_info->pulseClkSense(), + en_clk_info->insertion(), + en_clk_info->latency(), + en_clk_info->uncertainties(), + min_max, crpr_clk_path); + const RiseFall *q_rf = d_q_arc->toEdge()->asRiseFall(); + ExceptionStateSet *states = nullptr; + // Latch data pin is a valid exception -from pin. + if (sdc->exceptionFromStates(data_path->pin(this), + data_path->transition(this), + nullptr, nullptr, // clk below + MinMax::max(), states) + // -from enable non-filter exceptions apply. + && sdc->exceptionFromStates(enable_vertex->pin(), + enable_rf, + en_clk_edge->clock(), + en_clk_edge->transition(), + MinMax::max(), false, states)) + q_tag = search_->findTag(enable_path->tag(this)->scene(), + q_rf, MinMax::max(), q_clk_info, false, + nullptr, false, states, true, nullptr); + } + return; + } } } // No enable path found. @@ -409,26 +418,30 @@ Latches::latchOutArrival(const Path *data_path, ExceptionPath * Latches::exceptionTo(const Path *data_path, - const ClockEdge *en_clk_edge) + const ClockEdge *en_clk_edge) { + Sdc *sdc = data_path->sdc(this); // Look for exceptions -to data or -to enable clk. return search_->exceptionTo(ExceptionPathType::any, - data_path, - data_path->pin(this), - data_path->transition(this), - en_clk_edge, - data_path->minMax(this), - false, false); + data_path, + data_path->pin(this), + data_path->transition(this), + en_clk_edge, + data_path->minMax(this), + false, false, sdc); } ArcDelay Latches::latchSetupMargin(Vertex *data_vertex, - const RiseFall *data_rf, - const Path *disable_path, - const PathAnalysisPt *path_ap) const + const RiseFall *data_rf, + const Path *disable_path) const { if (disable_path) { + const Mode *mode = disable_path->mode(this); + const Sdc *sdc = mode->sdc(); Vertex *enable_vertex = disable_path->vertex(this); + const MinMax *min_max = disable_path->minMax(this); + DcalcAPIndex dcalc_ap = disable_path->dcalcAnalysisPtIndex(this); const RiseFall *disable_rf = disable_path->transition(this); VertexInEdgeIterator edge_iter(data_vertex, graph_); while (edge_iter.hasNext()) { @@ -436,16 +449,16 @@ Latches::latchSetupMargin(Vertex *data_vertex, const TimingRole *role = edge->role(); Vertex *from_vertex = edge->from(graph_); if (role == TimingRole::setup() - && from_vertex == enable_vertex - && !edge->isDisabledCond() - && !sdc_->isDisabledCondDefault(edge)) { - TimingArcSet *arc_set = edge->timingArcSet(); + && from_vertex == enable_vertex + && !mode->sim()->isDisabledCond(edge) + && !sdc->isDisabledCondDefault(edge)) { + TimingArcSet *arc_set = edge->timingArcSet(); for (TimingArc *check_arc : arc_set->arcs()) { - if (check_arc->toEdge()->asRiseFall() == data_rf - && check_arc->fromEdge()->asRiseFall() == disable_rf) - return search_->deratedDelay(from_vertex, check_arc, edge, - false, path_ap); - } + if (check_arc->toEdge()->asRiseFall() == data_rf + && check_arc->fromEdge()->asRiseFall() == disable_rf) + return search_->deratedDelay(from_vertex, check_arc, edge, + false, min_max, dcalc_ap, sdc); + } } } } @@ -454,23 +467,21 @@ Latches::latchSetupMargin(Vertex *data_vertex, void Latches::latchTimeGivenToStartpoint(const Path *d_path, - const Path *q_path, - const Edge *d_q_edge, - // Return values. - Arrival &time_given, - Path *&enable_path) const + const Path *q_path, + const Edge *d_q_edge, + // Return values. + Arrival &time_given, + Path *&enable_path) const { enable_path = latchEnablePath(q_path, d_q_edge); if (enable_path && enable_path->isClock(this)) { - const PathAnalysisPt *path_ap = q_path->pathAnalysisPt(this); - const PathAnalysisPt *tgt_clk_path_ap = path_ap->tgtClkAnalysisPt(); - Path *disable_path = latchEnableOtherPath(enable_path, tgt_clk_path_ap); + Path *disable_path = latchEnableOtherPath(enable_path); Delay borrow; Required required; Arrival adjusted_data_arrival; - latchRequired(d_path, enable_path, disable_path, path_ap, - required, borrow, adjusted_data_arrival, time_given); + latchRequired(d_path, enable_path, disable_path, + required, borrow, adjusted_data_arrival, time_given); } else { time_given = 0.0; @@ -480,11 +491,12 @@ Latches::latchTimeGivenToStartpoint(const Path *d_path, void Latches::latchDtoQEnable(const Edge *d_q_edge, - const Instance *inst, - // Return values. - Vertex *&enable_vertex, - const RiseFall *&enable_rf, - LatchEnableState &state) const + const Instance *inst, + const Mode *mode, + // Return values. + Vertex *&enable_vertex, + const RiseFall *&enable_rf, + LatchEnableState &state) const { enable_vertex = nullptr; state = LatchEnableState::open; @@ -495,38 +507,41 @@ Latches::latchDtoQEnable(const Edge *d_q_edge, const FuncExpr *enable_func; cell->latchEnable(d_q_set, enable_port, enable_func, enable_rf); if (enable_port) { + const Sdc *sdc = mode->sdc(); + Sim *sim = mode->sim(); Pin *enable_pin = network_->findPin(inst, enable_port); if (enable_pin) { - enable_vertex = graph_->pinLoadVertex(enable_pin); - if (enable_vertex->isDisabledConstraint()) - state = LatchEnableState::open; - else { - // See if constant values in the latch enable expression force - // it to be continuously open or closed. - LogicValue enable_value = enable_func - ? sim_->evalExpr(enable_func, inst) - : sim_->logicValue(enable_pin); - switch (enable_value) { - case LogicValue::zero: - case LogicValue::fall: - state = LatchEnableState::closed; - break; - case LogicValue::one: - case LogicValue::rise: - state = LatchEnableState::open; - break; - case LogicValue::unknown: - state = LatchEnableState::enabled; - break; - } - } + enable_vertex = graph_->pinLoadVertex(enable_pin); + if (sdc->isDisabledConstraint(enable_pin)) + state = LatchEnableState::open; + else { + // See if constant values in the latch enable expression force + // it to be continuously open or closed. + LogicValue enable_value = enable_func + ? sim->evalExpr(enable_func, inst) + : sim->simValue(enable_pin); + switch (enable_value) { + case LogicValue::zero: + case LogicValue::fall: + state = LatchEnableState::closed; + break; + case LogicValue::one: + case LogicValue::rise: + state = LatchEnableState::open; + break; + case LogicValue::unknown: + state = LatchEnableState::enabled; + break; + } + } } } } } LatchEnableState -Latches::latchDtoQState(const Edge *edge) const +Latches::latchDtoQState(const Edge *edge, + const Mode *mode) const { const Vertex *from_vertex = edge->from(graph_); const Pin *from_pin = from_vertex->pin(); @@ -534,17 +549,18 @@ Latches::latchDtoQState(const Edge *edge) const Vertex *enable_vertex; const RiseFall *enable_rf; LatchEnableState state; - latchDtoQEnable(edge, inst, enable_vertex, enable_rf, state); + latchDtoQEnable(edge, inst, mode, enable_vertex, enable_rf, state); return state; } // Latch D->Q arc looks combinational when the enable pin is disabled // or constant. bool -Latches::isLatchDtoQ(const Edge *edge) const +Latches::isLatchDtoQ(const Edge *edge, + const Mode *mode) const { return edge->role() == TimingRole::latchDtoQ() - && latchDtoQState(edge) == LatchEnableState::enabled; + && latchDtoQState(edge, mode) == LatchEnableState::enabled; } } // namespace diff --git a/search/Latches.hh b/search/Latches.hh index 689e1685..864904e5 100644 --- a/search/Latches.hh +++ b/search/Latches.hh @@ -39,74 +39,73 @@ class Latches : public StaState public: Latches(StaState *sta); void latchTimeGivenToStartpoint(const Path *d_path, - const Path *q_path, - const Edge *d_q_edge, - // Return values. - Arrival &time_given, - Path *&enable_path) const; + const Path *q_path, + const Edge *d_q_edge, + // Return values. + Arrival &time_given, + Path *&enable_path) const; void latchRequired(const Path *data_path, - const Path *enable_path, - const Path *disable_path, - const MultiCyclePath *mcp, - const PathDelay *path_delay, - Arrival src_clk_latency, - const ArcDelay &margin, - // Return values. - Required &required, - Delay &borrow, - Arrival &adjusted_data_arrival, - Delay &time_given_to_startpoint) const; - void latchRequired(const Path *data_path, - const Path *enable_path, - const Path *disable_path, - const PathAnalysisPt *path_ap, - // Return values. - Required &required, - Delay &borrow, - Arrival &adjusted_data_arrival, - Delay &time_given_to_startpoint) const; + const Path *enable_path, + const Path *disable_path, + const MultiCyclePath *mcp, + const PathDelay *path_delay, + Arrival src_clk_latency, + const ArcDelay &margin, + // Return values. + Required &required, + Delay &borrow, + Arrival &adjusted_data_arrival, + Delay &time_given_to_startpoint) const; void latchBorrowInfo(const Path *data_path, - const Path *enable_path, - const Path *disable_path, - const ArcDelay &margin, - bool ignore_clk_latency, - // Return values. - float &nom_pulse_width, - Delay &open_latency, - Delay &latency_diff, - float &open_uncertainty, - Crpr &open_crpr, - Crpr &crpr_diff, - Delay &max_borrow, - bool &borrow_limit_exists) const; - bool isLatchDtoQ(const Edge *edge) const; + const Path *enable_path, + const Path *disable_path, + const ArcDelay &margin, + bool ignore_clk_latency, + // Return values. + float &nom_pulse_width, + Delay &open_latency, + Delay &latency_diff, + float &open_uncertainty, + Crpr &open_crpr, + Crpr &crpr_diff, + Delay &max_borrow, + bool &borrow_limit_exists) const; + bool isLatchDtoQ(const Edge *edge, + const Mode *mode) const; // Find the latch EN->Q edge for a D->Q edge. void latchDtoQEnable(const Edge *d_q_edge, - const Instance *inst, - // Return values. - Vertex *&enable_vertex, - const RiseFall *&enable_rf, - LatchEnableState &state) const; - LatchEnableState latchDtoQState(const Edge *d_q_edge) const; - Path *latchEnableOtherPath(const Path *path, - const PathAnalysisPt *tgt_clk_path_ap) const; + const Instance *inst, + const Mode *mode, + // Return values. + Vertex *&enable_vertex, + const RiseFall *&enable_rf, + LatchEnableState &state) const; + LatchEnableState latchDtoQState(const Edge *d_q_edge, + const Mode *mode) const; + Path *latchEnableOtherPath(const Path *path) const; Path *latchEnablePath(const Path *q_path, const Edge *d_q_edge) const; void latchOutArrival(const Path *data_path, - const TimingArc *d_q_arc, - const Edge *d_q_edge, - const PathAnalysisPt *path_ap, - Tag *&q_tag, - ArcDelay &arc_delay, - Arrival &q_arrival); + const TimingArc *d_q_arc, + const Edge *d_q_edge, + Tag *&q_tag, + ArcDelay &arc_delay, + Arrival &q_arrival); protected: + void latchRequired(const Path *data_path, + const Path *enable_path, + const Path *disable_path, + // Return values. + Required &required, + Delay &borrow, + Arrival &adjusted_data_arrival, + Delay &time_given_to_startpoint) const; ArcDelay latchSetupMargin(Vertex *data_vertex, - const RiseFall *data_rf, - const Path *disable_path, - const PathAnalysisPt *path_ap) const; + const RiseFall *data_rf, + const Path *disable_path) const; ExceptionPath *exceptionTo(const Path *data_path, - const ClockEdge *en_clk_edge); + const ClockEdge *en_clk_edge); }; } // namespace diff --git a/search/Levelize.cc b/search/Levelize.cc index 69273479..02ef86e5 100644 --- a/search/Levelize.cc +++ b/search/Levelize.cc @@ -27,6 +27,7 @@ #include #include +#include "ContainerHelpers.hh" #include "Report.hh" #include "Debug.hh" #include "Stats.hh" @@ -34,9 +35,9 @@ #include "PortDirection.hh" #include "Network.hh" #include "Sdc.hh" +#include "Mode.hh" #include "Graph.hh" #include "GraphCmp.hh" -#include "SearchPred.hh" #include "Variables.hh" #include "GraphDelayCalc.hh" @@ -46,13 +47,12 @@ using std::max; Levelize::Levelize(StaState *sta) : StaState(sta), - search_pred_(sta), levelized_(false), levels_valid_(false), max_level_(0), level_space_(10), - roots_(graph_), - relevelize_from_(graph_), + roots_(makeVertexSet(sta)), + relevelize_from_(makeVertexSet(sta)), observer_(nullptr) { } @@ -60,7 +60,8 @@ Levelize::Levelize(StaState *sta) : Levelize::~Levelize() { delete observer_; - loops_.deleteContents(); + for (auto loop : loops_) + delete loop; } void @@ -84,7 +85,9 @@ Levelize::clear() roots_.clear(); relevelize_from_.clear(); clearLoopEdges(); - loops_.deleteContentsClear(); + for (auto loop : loops_) + delete loop; + loops_.clear(); loop_edges_.clear(); max_level_ = 0; } @@ -92,11 +95,8 @@ Levelize::clear() void Levelize::clearLoopEdges() { - EdgeSet::Iterator edge_iter(disabled_loop_edges_); - while (edge_iter.hasNext()) { - Edge *edge = edge_iter.next(); + for (Edge *edge : disabled_loop_edges_) edge->setIsDisabledLoop(false); - } disabled_loop_edges_.clear(); } @@ -173,7 +173,7 @@ Levelize::findRoots() size_t fanout_roots = 0; for (Vertex *root : roots_) { if (hasFanout(root)) - fanout_roots++; + fanout_roots++; } debugPrint(debug_, "levelize", 1, "Found %zu roots %zu with fanout", roots_.size(), @@ -186,43 +186,47 @@ Levelize::findRoots() bool Levelize::isRoot(Vertex *vertex) { - if (search_pred_.searchTo(vertex)) { - VertexInEdgeIterator edge_iter1(vertex, graph_); - while (edge_iter1.hasNext()) { - Edge *edge = edge_iter1.next(); - Vertex *from_vertex = edge->from(graph_); - if (search_pred_.searchFrom(from_vertex) - && search_pred_.searchThru(edge)) - return false; - } - // Levelize bidirect driver as if it was a fanout of the bidirect load. - return !(graph_delay_calc_->bidirectDrvrSlewFromLoad(vertex->pin()) - && vertex->isBidirectDriver()); + VertexInEdgeIterator edge_iter1(vertex, graph_); + while (edge_iter1.hasNext()) { + Edge *edge = edge_iter1.next(); + if (searchThru(edge)) + return false; } - else - return false; + // Levelize bidirect driver as if it was a fanout of the bidirect load. + return !(graph_delay_calc_->bidirectDrvrSlewFromLoad(vertex->pin()) + && vertex->isBidirectDriver()); +} + +bool +Levelize::searchThru(Edge *edge) +{ + const TimingRole *role = edge->role(); + return !role->isTimingCheck() + && role != TimingRole::latchDtoQ() + && !edge->isDisabledLoop() + // Register/latch preset/clr edges are disabled by default. + && !(role == TimingRole::regSetClr() + && !variables_->presetClrArcsEnabled()) + && !(edge->isBidirectInstPath() + && !variables_->bidirectInstPathsEnabled()); } bool Levelize::hasFanout(Vertex *vertex) { bool has_fanout = false; - if (search_pred_.searchFrom(vertex)) { - VertexOutEdgeIterator edge_iter2(vertex, graph_); - while (edge_iter2.hasNext()) { - Edge *edge = edge_iter2.next(); - Vertex *to_vertex = edge->from(graph_); - if (search_pred_.searchTo(to_vertex) - && search_pred_.searchThru(edge)) { - has_fanout = true; - break; - } - } - // Levelize bidirect driver as if it was a fanout of the bidirect load. - if (graph_delay_calc_->bidirectDrvrSlewFromLoad(vertex->pin()) - && !vertex->isBidirectDriver()) + VertexOutEdgeIterator edge_iter2(vertex, graph_); + while (edge_iter2.hasNext()) { + Edge *edge = edge_iter2.next(); + if (searchThru(edge)) { has_fanout = true; + break; + } } + // Levelize bidirect driver as if it was a fanout of the bidirect load. + if (graph_delay_calc_->bidirectDrvrSlewFromLoad(vertex->pin()) + && !vertex->isBidirectDriver()) + has_fanout = true; return has_fanout; } @@ -268,11 +272,10 @@ Levelize::findBackEdges(EdgeSeq &path, EdgeSet back_edges; while (!stack.empty()) { VertexEdgeIterPair vertex_iter = stack.top(); - Vertex *vertex = vertex_iter.first; - VertexOutEdgeIterator *edge_iter = vertex_iter.second; + const auto& [vertex, edge_iter] = vertex_iter; if (edge_iter->hasNext()) { Edge *edge = edge_iter->next(); - if (search_pred_.searchThru(edge)) { + if (searchThru(edge)) { Vertex *to_vertex = edge->to(graph_); if (!to_vertex->visited()) { to_vertex->setVisited(true); @@ -310,10 +313,10 @@ Levelize::findCycleBackEdges() if (unvisited.size() < 100) sort(unvisited, VertexNameLess(network_)); size_t back_edge_count = 0; - VertexSet visited(graph_); + VertexSet visited = makeVertexSet(this); for (Vertex *vertex : unvisited) { - if (visited.find(vertex) == visited.end()) { - VertexSet path_vertices(graph_); + if (!visited.contains(vertex)) { + VertexSet path_vertices = makeVertexSet(this); EdgeSeq path; FindBackEdgesStack stack; visited.insert(vertex); @@ -336,8 +339,7 @@ Levelize::findUnvisitedVertices() VertexIterator vertex_iter(graph_); while (vertex_iter.hasNext()) { Vertex *vertex = vertex_iter.next(); - if (!vertex->visited() - && search_pred_.searchFrom(vertex)) + if (!vertex->visited()) unvisited.push_back(vertex); } return unvisited; @@ -354,25 +356,21 @@ Levelize::findTopologicalOrder() VertexIterator vertex_iter(graph_); while (vertex_iter.hasNext()) { Vertex *vertex = vertex_iter.next(); - if (search_pred_.searchFrom(vertex)) { - VertexOutEdgeIterator edge_iter(vertex, graph_); - while (edge_iter.hasNext()) { - Edge *edge = edge_iter.next(); - Vertex *to_vertex = edge->to(graph_); - if (search_pred_.searchThru(edge) - && search_pred_.searchTo(to_vertex)) - in_degree[to_vertex] += 1; - if (edge->role() == TimingRole::latchDtoQ()) - latch_d_to_q_edges_.insert(edge); - } - // Levelize bidirect driver as if it was a fanout of the bidirect load. - const Pin *pin = vertex->pin(); - if (graph_delay_calc_->bidirectDrvrSlewFromLoad(pin) - && !vertex->isBidirectDriver()) { - Vertex *to_vertex = graph_->pinDrvrVertex(pin);; - if (search_pred_.searchTo(to_vertex)) - in_degree[to_vertex] += 1; - } + VertexOutEdgeIterator edge_iter(vertex, graph_); + while (edge_iter.hasNext()) { + Edge *edge = edge_iter.next(); + Vertex *to_vertex = edge->to(graph_); + if (searchThru(edge)) + in_degree[to_vertex] += 1; + if (edge->role() == TimingRole::latchDtoQ()) + latch_d_to_q_edges_.insert(edge); + } + // Levelize bidirect driver as if it was a fanout of the bidirect load. + const Pin *pin = vertex->pin(); + if (graph_delay_calc_->bidirectDrvrSlewFromLoad(pin) + && !vertex->isBidirectDriver()) { + Vertex *to_vertex = graph_->pinDrvrVertex(pin);; + in_degree[to_vertex] += 1; } } @@ -385,19 +383,16 @@ Levelize::findTopologicalOrder() Vertex *vertex = queue.front(); queue.pop_front(); topo_order.push_back(vertex); - if (search_pred_.searchFrom(vertex)) { - VertexOutEdgeIterator edge_iter(vertex, graph_); - while (edge_iter.hasNext()) { - Edge *edge = edge_iter.next(); - Vertex *to_vertex = edge->to(graph_); - if (search_pred_.searchThru(edge) - && search_pred_.searchTo(to_vertex)) { - const auto &to_degree_itr = in_degree.find(to_vertex); - int &to_in_degree = to_degree_itr->second; - to_in_degree -= 1; - if (to_in_degree == 0) - queue.push_back(to_vertex); - } + VertexOutEdgeIterator edge_iter(vertex, graph_); + while (edge_iter.hasNext()) { + Edge *edge = edge_iter.next(); + Vertex *to_vertex = edge->to(graph_); + if (searchThru(edge)) { + const auto &to_degree_itr = in_degree.find(to_vertex); + int &to_in_degree = to_degree_itr->second; + to_in_degree -= 1; + if (to_in_degree == 0) + queue.push_back(to_vertex); } } // Levelize bidirect driver as if it was a fanout of the bidirect load. @@ -405,13 +400,11 @@ Levelize::findTopologicalOrder() if (graph_delay_calc_->bidirectDrvrSlewFromLoad(pin) && !vertex->isBidirectDriver()) { Vertex *to_vertex = graph_->pinDrvrVertex(pin); - if (search_pred_.searchTo(to_vertex)) { - const auto °ree_itr = in_degree.find(to_vertex); - int &in_degree = degree_itr->second; - in_degree -= 1; - if (in_degree == 0) - queue.push_back(to_vertex); - } + const auto °ree_itr = in_degree.find(to_vertex); + int &in_degree = degree_itr->second; + in_degree -= 1; + if (in_degree == 0) + queue.push_back(to_vertex); } } @@ -435,7 +428,7 @@ Levelize::findTopologicalOrder() void Levelize::recordLoop(Edge *edge, - EdgeSeq &path) + EdgeSeq &path) { debugPrint(debug_, "levelize", 2, "Loop edge %s (%s)", edge->to_string(this).c_str(), @@ -443,8 +436,10 @@ Levelize::recordLoop(Edge *edge, EdgeSeq *loop_edges = loopEdges(path, edge); GraphLoop *loop = new GraphLoop(loop_edges); loops_.push_back(loop); - if (variables_->dynamicLoopBreaking()) - sdc_->makeLoopExceptions(loop); + if (variables_->dynamicLoopBreaking()) { + for (Mode *mode : modes_) + mode->sdc()->makeLoopExceptions(loop); + } // Record disabled loop edges so they can be cleared without // traversing the entire graph to find them. @@ -454,16 +449,14 @@ Levelize::recordLoop(Edge *edge, EdgeSeq * Levelize::loopEdges(EdgeSeq &path, - Edge *closing_edge) + Edge *closing_edge) { debugPrint(debug_, "loop", 2, "Loop"); EdgeSeq *loop_edges = new EdgeSeq; // Skip the "head" of the path up to where closing_edge closes the loop. Pin *loop_pin = closing_edge->to(graph_)->pin(); bool copy = false; - EdgeSeq::Iterator edge_iter(path); - while (edge_iter.hasNext()) { - Edge *edge = edge_iter.next(); + for (Edge *edge : path) { Pin *from_pin = edge->from(graph_)->pin(); if (from_pin == loop_pin) copy = true; @@ -485,9 +478,7 @@ void Levelize::reportPath(EdgeSeq &path) const { bool first_edge = true; - EdgeSeq::Iterator edge_iter(path); - while (edge_iter.hasNext()) { - Edge *edge = edge_iter.next(); + for (Edge *edge : path) { if (first_edge) report_->reportLine(" %s", edge->from(graph_)->to_string(this).c_str()); report_->reportLine(" %s", edge->to(graph_)->to_string(this).c_str()); @@ -503,14 +494,12 @@ Levelize::assignLevels(VertexSeq &topo_sorted) for (Vertex *root : roots_) setLevel(root, 0); for (Vertex *vertex : topo_sorted) { - if (vertex->level() != -1 - && search_pred_.searchFrom(vertex)) { + if (vertex->level() != -1) { VertexOutEdgeIterator edge_iter(vertex, graph_); while (edge_iter.hasNext()) { Edge *edge = edge_iter.next(); Vertex *to_vertex = edge->to(graph_); - if (search_pred_.searchThru(edge) - && search_pred_.searchTo(to_vertex)) + if (searchThru(edge)) setLevel(to_vertex, max(to_vertex->level(), vertex->level() + level_space_)); } @@ -519,9 +508,8 @@ Levelize::assignLevels(VertexSeq &topo_sorted) if (graph_delay_calc_->bidirectDrvrSlewFromLoad(pin) && !vertex->isBidirectDriver()) { Vertex *to_vertex = graph_->pinDrvrVertex(pin); - if (search_pred_.searchTo(to_vertex)) - setLevel(to_vertex, max(to_vertex->level(), - vertex->level() + level_space_)); + setLevel(to_vertex, max(to_vertex->level(), + vertex->level() + level_space_)); } } } @@ -536,9 +524,7 @@ Levelize::assignLevels(VertexSeq &topo_sorted) void Levelize::ensureLatchLevels() { - EdgeSet::Iterator latch_edge_iter(latch_d_to_q_edges_); - while (latch_edge_iter.hasNext()) { - Edge *edge = latch_edge_iter.next(); + for (Edge *edge : latch_d_to_q_edges_) { Vertex *from = edge->from(graph_); Vertex *to = edge->to(graph_); if (from->level() == to->level()) @@ -549,7 +535,7 @@ Levelize::ensureLatchLevels() void Levelize::setLevel(Vertex *vertex, - Level level) + Level level) { debugPrint(debug_, "levelize", 2, "set level %s %d", vertex->to_string(this).c_str(), @@ -570,23 +556,6 @@ Levelize::invalid() } } -void -Levelize::invalidFrom(Vertex *vertex) -{ - if (levelized_) { - debugPrint(debug_, "levelize", 1, "level invalid from %s", - vertex->to_string(this).c_str()); - VertexInEdgeIterator edge_iter(vertex, graph_); - while (edge_iter.hasNext()) { - Edge *edge = edge_iter.next(); - Vertex *from_vertex = edge->from(graph_); - relevelize_from_.insert(from_vertex); - } - relevelize_from_.insert(vertex); - levels_valid_ = false; - } -} - void Levelize::deleteVertexBefore(Vertex *vertex) { @@ -611,7 +580,7 @@ void Levelize::deleteEdgeBefore(Edge *edge) { if (levelized_ - && loop_edges_.hasKey(edge)) { + && loop_edges_.contains(edge)) { debugPrint(debug_, "levelize", 2, "delete loop edge %s", edge->to_string(this).c_str()); disabled_loop_edges_.erase(edge); @@ -636,13 +605,11 @@ Levelize::relevelize() for (Vertex *vertex : relevelize_from_) { debugPrint(debug_, "levelize", 1, "relevelize from %s", vertex->to_string(this).c_str()); - if (search_pred_.searchFrom(vertex)) { - if (isRoot(vertex)) - roots_.insert(vertex); - VertexSet path_vertices(graph_); - EdgeSeq path; - visit(vertex, nullptr, vertex->level(), 1, path_vertices, path); - } + if (isRoot(vertex)) + roots_.insert(vertex); + VertexSet path_vertices = makeVertexSet(this); + EdgeSeq path; + visit(vertex, nullptr, vertex->level(), 1, path_vertices, path); } ensureLatchLevels(); levels_valid_ = true; @@ -651,11 +618,11 @@ Levelize::relevelize() void Levelize::visit(Vertex *vertex, - Edge *from, + Edge *from, Level level, - Level level_space, + Level level_space, VertexSet &path_vertices, - EdgeSeq &path) + EdgeSeq &path) { Pin *from_pin = vertex->pin(); setLevelIncr(vertex, level); @@ -663,32 +630,28 @@ Levelize::visit(Vertex *vertex, if (from) path.push_back(from); - if (search_pred_.searchFrom(vertex)) { - VertexOutEdgeIterator edge_iter(vertex, graph_); - while (edge_iter.hasNext()) { - Edge *edge = edge_iter.next(); - Vertex *to_vertex = edge->to(graph_); - if (search_pred_.searchThru(edge) - && search_pred_.searchTo(to_vertex)) { - if (path_vertices.find(to_vertex) != path_vertices.end()) - // Back edges form feedback loops. - recordLoop(edge, path); - else if (to_vertex->level() <= level) - visit(to_vertex, edge, level+level_space, level_space, - path_vertices, path); - } - if (edge->role() == TimingRole::latchDtoQ()) - latch_d_to_q_edges_.insert(edge); - } - // Levelize bidirect driver as if it was a fanout of the bidirect load. - if (graph_delay_calc_->bidirectDrvrSlewFromLoad(from_pin) - && !vertex->isBidirectDriver()) { - Vertex *to_vertex = graph_->pinDrvrVertex(from_pin); - if (search_pred_.searchTo(to_vertex) - && (to_vertex->level() <= level)) - visit(to_vertex, nullptr, level+level_space, level_space, - path_vertices, path); + VertexOutEdgeIterator edge_iter(vertex, graph_); + while (edge_iter.hasNext()) { + Edge *edge = edge_iter.next(); + Vertex *to_vertex = edge->to(graph_); + if (searchThru(edge)) { + if (path_vertices.contains(to_vertex)) + // Back edges form feedback loops. + recordLoop(edge, path); + else if (to_vertex->level() <= level) + visit(to_vertex, edge, level+level_space, level_space, + path_vertices, path); } + if (edge->role() == TimingRole::latchDtoQ()) + latch_d_to_q_edges_.insert(edge); + } + // Levelize bidirect driver as if it was a fanout of the bidirect load. + if (graph_delay_calc_->bidirectDrvrSlewFromLoad(from_pin) + && !vertex->isBidirectDriver()) { + Vertex *to_vertex = graph_->pinDrvrVertex(from_pin); + if (to_vertex->level() <= level) + visit(to_vertex, nullptr, level+level_space, level_space, + path_vertices, path); } path_vertices.erase(vertex); if (from) @@ -698,7 +661,7 @@ Levelize::visit(Vertex *vertex, bool Levelize::isDisabledLoop(Edge *edge) const { - return disabled_loop_edges_.hasKey(edge); + return disabled_loop_edges_.contains(edge); } void @@ -724,24 +687,21 @@ Levelize::checkLevels() VertexIterator vertex_iter(graph_); while (vertex_iter.hasNext()) { Vertex *vertex = vertex_iter.next(); - if (search_pred_.searchTo(vertex)) { - Level level = vertex->level(); - VertexInEdgeIterator edge_iter1(vertex, graph_); - while (edge_iter1.hasNext()) { - Edge *edge = edge_iter1.next(); - Vertex *from_vertex = edge->from(graph_); - Level from_level = from_vertex->level(); - if (search_pred_.searchFrom(from_vertex) - && search_pred_.searchThru(edge) - && from_level >= level - // Loops with no entry edges are all level zero. - && !(from_level == 0 && level == 0)) - report_->warn(617, "level check failed %s %d -> %s %d", - from_vertex->name(network_), - from_vertex->level(), - vertex->name(network_), - level); - } + Level level = vertex->level(); + VertexInEdgeIterator edge_iter1(vertex, graph_); + while (edge_iter1.hasNext()) { + Edge *edge = edge_iter1.next(); + Vertex *from_vertex = edge->from(graph_); + Level from_level = from_vertex->level(); + if (searchThru(edge) + && from_level >= level + // Loops with no entry edges are all level zero. + && !(from_level == 0 && level == 0)) + report_->warn(617, "level check failed %s %d -> %s %d", + from_vertex->name(network_), + from_vertex->level(), + vertex->name(network_), + level); } } } @@ -761,14 +721,12 @@ GraphLoop::~GraphLoop() bool GraphLoop::isCombinational() const { - EdgeSeq::Iterator edge_iter(edges_); - while (edge_iter.hasNext()) { - Edge *edge = edge_iter.next(); + for (Edge *edge : *edges_) { const TimingRole *role = edge->role(); if (!(role == TimingRole::wire() - || role == TimingRole::combinational() - || role == TimingRole::tristateEnable() - || role == TimingRole::tristateDisable())) + || role == TimingRole::combinational() + || role == TimingRole::tristateEnable() + || role == TimingRole::tristateDisable())) return false; } return true; @@ -780,9 +738,7 @@ GraphLoop::report(const StaState *sta) const Graph *graph = sta->graph(); Report *report = sta->report(); bool first_edge = true; - EdgeSeq::Iterator loop_edge_iter(edges_); - while (loop_edge_iter.hasNext()) { - Edge *edge = loop_edge_iter.next(); + for (Edge *edge : *edges_) { if (first_edge) report->reportLine(" %s", edge->from(graph)->to_string(sta).c_str()); report->reportLine(" %s", edge->to(graph)->to_string(graph).c_str()); diff --git a/search/Levelize.hh b/search/Levelize.hh index fb9c1af9..aab99a00 100644 --- a/search/Levelize.hh +++ b/search/Levelize.hh @@ -36,9 +36,11 @@ namespace sta { class SearchPred; class LevelizeObserver; +class GraphLoop; -typedef std::pair VertexEdgeIterPair; -typedef std::stack FindBackEdgesStack; +using VertexEdgeIterPair = std::pair; +using FindBackEdgesStack = std::stack; +using GraphLoopSeq = std::vector; class Levelize : public StaState { @@ -52,7 +54,6 @@ public: void ensureLevelized(); void invalid(); // Levels downstream from vertex are invalid. - void invalidFrom(Vertex *vertex); void relevelizeFrom(Vertex *vertex); void deleteVertexBefore(Vertex *vertex); void deleteEdgeBefore(Edge *edge); @@ -61,6 +62,7 @@ public: VertexSet &roots() { return roots_; } bool isRoot(Vertex *vertex); bool hasFanout(Vertex *vertex); + bool searchThru(Edge *edge); // Reset to virgin state. void clear(); // Edge is disabled to break combinational loops. @@ -96,14 +98,13 @@ protected: VertexSet &path_vertices, EdgeSeq &path); void setLevel(Vertex *vertex, - Level level); + Level level); void setLevelIncr(Vertex *vertex, Level level); void clearLoopEdges(); void deleteLoops(); void reportPath(EdgeSeq &path) const; - SearchPredNonLatch2 search_pred_; bool levelized_; bool levels_valid_; Level max_level_; @@ -123,7 +124,7 @@ protected: class GraphLoop { public: - explicit GraphLoop(EdgeSeq *edges); + GraphLoop(EdgeSeq *edges); ~GraphLoop(); EdgeSeq *edges() { return edges_; } bool isCombinational() const; diff --git a/search/MakeTimingModel.cc b/search/MakeTimingModel.cc index e20cf407..40e27ae2 100644 --- a/search/MakeTimingModel.cc +++ b/search/MakeTimingModel.cc @@ -37,8 +37,7 @@ #include "liberty/LibertyBuilder.hh" #include "Network.hh" #include "PortDirection.hh" -#include "Corner.hh" -#include "DcalcAnalysisPt.hh" +#include "Scene.hh" #include "GraphDelayCalc.hh" #include "Sdc.hh" #include "StaState.hh" @@ -61,30 +60,32 @@ LibertyLibrary * makeTimingModel(const char *lib_name, const char *cell_name, const char *filename, - const Corner *corner, + const Scene *scene, Sta *sta) { - MakeTimingModel maker(lib_name, cell_name, filename, corner, sta); + MakeTimingModel maker(lib_name, cell_name, filename, scene, sta); return maker.makeTimingModel(); } MakeTimingModel::MakeTimingModel(const char *lib_name, const char *cell_name, const char *filename, - const Corner *corner, + const Scene *scene, Sta *sta) : StaState(sta), lib_name_(lib_name), cell_name_(cell_name), filename_(filename), - corner_(corner), + scene_(scene), cell_(nullptr), min_max_(MinMax::max()), lib_builder_(new LibertyBuilder), tbl_template_index_(1), + sdc_(scene->sdc()), sdc_backup_(nullptr), sta_(sta) { + scenes_.insert(scene_); } MakeTimingModel::~MakeTimingModel() @@ -118,7 +119,7 @@ MakeTimingModel::makeTimingModel() void MakeTimingModel::saveSdc() { - sdc_backup_ = new Sdc(this); + sdc_backup_ = new Sdc(sdc_->mode(), this); swapSdcWithBackup(); sta_->delaysInvalid(); } @@ -186,7 +187,6 @@ MakeTimingModel::findArea() void MakeTimingModel::makePorts() { - const DcalcAnalysisPt *dcalc_ap = corner_->findDcalcAnalysisPt(min_max_); Instance *top_inst = network_->topInstance(); Cell *top_cell = network_->cell(top_inst); CellPortIterator *port_iter = network_->portIterator(top_cell); @@ -207,7 +207,7 @@ MakeTimingModel::makePorts() Port *bit_port = member_iter->next(); Pin *pin = network_->findPin(top_inst, bit_port); LibertyPort *lib_bit_port = modelPort(pin); - float load_cap = graph_delay_calc_->loadCap(pin, dcalc_ap); + float load_cap = graph_delay_calc_->loadCap(pin, scene_, min_max_); lib_bit_port->setCapacitance(load_cap); } delete member_iter; @@ -216,7 +216,7 @@ MakeTimingModel::makePorts() LibertyPort *lib_port = lib_builder_->makePort(cell_, port_name); lib_port->setDirection(network_->direction(port)); Pin *pin = network_->findPin(top_inst, port); - float load_cap = graph_delay_calc_->loadCap(pin, dcalc_ap); + float load_cap = graph_delay_calc_->loadCap(pin, scene_, min_max_); lib_port->setCapacitance(load_cap); } } @@ -275,9 +275,10 @@ void MakeEndTimingArcs::visit(PathEnd *path_end) { Path *src_path = path_end->path(); + const Sdc *sdc = src_path->sdc(sta_); const Clock *src_clk = src_path->clock(sta_); const ClockEdge *tgt_clk_edge = path_end->targetClkEdge(sta_); - if (src_clk == sta_->sdc()->defaultArrivalClock() + if (src_clk == sdc->defaultArrivalClock() && tgt_clk_edge) { Network *network = sta_->network(); Debug *debug = sta_->debug(); @@ -334,7 +335,7 @@ MakeTimingModel::findTimingFromInput(Port *input_port) { Instance *top_inst = network_->topInstance(); Pin *input_pin = network_->findPin(top_inst, input_port); - if (!sta_->isClockSrc(input_pin)) { + if (!sdc_->isClock(input_pin)) { MakeEndTimingArcs end_visitor(sta_); OutputPinDelays output_delays; for (const RiseFall *input_rf : RiseFall::range()) { @@ -342,26 +343,26 @@ MakeTimingModel::findTimingFromInput(Port *input_port) sta_->setInputDelay(input_pin, input_rf1, sdc_->defaultArrivalClock(), sdc_->defaultArrivalClockEdge()->transition(), - nullptr, false, false, MinMaxAll::all(), true, 0.0); + nullptr, false, false, MinMaxAll::all(), true, 0.0, sdc_); PinSet *from_pins = new PinSet(network_); from_pins->insert(input_pin); ExceptionFrom *from = sta_->makeExceptionFrom(from_pins, nullptr, nullptr, - input_rf1); + input_rf1, sdc_); search_->findFilteredArrivals(from, nullptr, nullptr, false, false); end_visitor.setInputRf(input_rf); VertexSeq endpoints = search_->filteredEndpoints(); VisitPathEnds visit_ends(sta_); for (Vertex *end : endpoints) - visit_ends.visitPathEnds(end, corner_, MinMaxAll::all(), true, &end_visitor); + visit_ends.visitPathEnds(end, scenes_, MinMaxAll::all(), true, &end_visitor); findOutputDelays(input_rf, output_delays); search_->deleteFilteredArrivals(); sta_->removeInputDelay(input_pin, input_rf1, sdc_->defaultArrivalClock(), sdc_->defaultArrivalClockEdge()->transition(), - MinMaxAll::all()); + MinMaxAll::all(), sdc_); } makeSetupHoldTimingArcs(input_pin, end_visitor.margins()); makeInputOutputTimingArcs(input_pin, output_delays); @@ -547,7 +548,7 @@ MakeTimingModel::findClkTreeDelays() ClockSet *clks = sdc_->findClocks(pin); if (clks->size() == 1) { for (const Clock *clk : *clks) { - ClkDelays delays = sta_->findClkDelays(clk, true); + ClkDelays delays = sta_->findClkDelays(clk, scene_, true); for (const MinMax *min_max : MinMax::range()) { makeClkTreePaths(lib_port, min_max, TimingSense::positive_unate, delays); makeClkTreePaths(lib_port, min_max, TimingSense::negative_unate, delays); @@ -656,9 +657,9 @@ MakeTimingModel::makeGateModelTable(const Pin *output_pin, Delay delay, const RiseFall *rf) { - const DcalcAnalysisPt *dcalc_ap = corner_->findDcalcAnalysisPt(min_max_); - const Pvt *pvt = dcalc_ap->operatingConditions(); + const Pvt *pvt = sdc_->operatingConditions(min_max_); PinSet *drvrs = network_->drivers(network_->net(network_->term(output_pin))); + DcalcAPIndex ap_index = scene_->dcalcAnalysisPtIndex(min_max_); const Pin *drvr_pin = *drvrs->begin(); const LibertyPort *drvr_port = network_->libertyPort(drvr_pin); if (drvr_port) { @@ -674,11 +675,14 @@ MakeTimingModel::makeGateModelTable(const Pin *output_pin, Vertex *gate_in_vertex = graph_->pinLoadVertex(gate_in_pin); Slew in_slew = graph_->slew(gate_in_vertex, drvr_arc->fromEdge()->asRiseFall(), - dcalc_ap->index()); + ap_index); float in_slew1 = delayAsFloat(in_slew); - GateTableModel *drvr_gate_model = drvr_arc->gateTableModel(dcalc_ap); + GateTableModel *drvr_gate_model = drvr_arc->gateTableModel(scene_, + min_max_); if (drvr_gate_model) { - float output_load_cap = graph_delay_calc_->loadCap(output_pin, dcalc_ap); + float output_load_cap = graph_delay_calc_->loadCap(output_pin, + scene_, + min_max_); ArcDelay drvr_self_delay; Slew drvr_self_slew; drvr_gate_model->gateDelay(pvt, in_slew1, output_load_cap, false, @@ -731,7 +735,7 @@ MakeTimingModel::makeGateModelTable(const Pin *output_pin, } } Vertex *output_vertex = graph_->pinLoadVertex(output_pin); - Slew slew = graph_->slew(output_vertex, rf, dcalc_ap->index()); + Slew slew = graph_->slew(output_vertex, rf, ap_index); return makeGateModelScalar(delay, slew, rf); } @@ -739,7 +743,7 @@ TableTemplate * MakeTimingModel::ensureTableTemplate(const TableTemplate *drvr_template, TableAxisPtr load_axis) { - TableTemplate *model_template = template_map_.findKey(drvr_template); + TableTemplate *model_template = findKey(template_map_, drvr_template); if (model_template == nullptr) { string template_name = "template_"; template_name += std::to_string(tbl_template_index_++); diff --git a/search/MakeTimingModel.hh b/search/MakeTimingModel.hh index 0f9c8ea9..bf929526 100644 --- a/search/MakeTimingModel.hh +++ b/search/MakeTimingModel.hh @@ -27,14 +27,14 @@ namespace sta { class LibertyLibrary; -class Corner; +class Scene; class Sta; LibertyLibrary * makeTimingModel(const char *lib_name, const char *cell_name, const char *filename, - const Corner *corner, + const Scene *scene, Sta *sta); } // namespace diff --git a/search/MakeTimingModelPvt.hh b/search/MakeTimingModelPvt.hh index babd247a..8184c46e 100644 --- a/search/MakeTimingModelPvt.hh +++ b/search/MakeTimingModelPvt.hh @@ -48,8 +48,8 @@ public: bool rf_path_exists[RiseFall::index_count][RiseFall::index_count]; }; -typedef std::map ClockEdgeDelays; -typedef std::map OutputPinDelays; +using ClockEdgeDelays = std::map; +using OutputPinDelays = std::map; class MakeTimingModel : public StaState { @@ -57,7 +57,7 @@ public: MakeTimingModel(const char *lib_name, const char *cell_name, const char *filename, - const Corner *corner, + const Scene *scene, Sta *sta); ~MakeTimingModel(); LibertyLibrary *makeTimingModel(); @@ -105,14 +105,16 @@ private: const char *lib_name_; const char *cell_name_; const char *filename_; - const Corner *corner_; + const Scene *scene_; + SceneSet scenes_; LibertyLibrary *library_; LibertyCell *cell_; const MinMax *min_max_; LibertyBuilder *lib_builder_; // Output driver table model template to model template. - Map template_map_; + std::map template_map_; int tbl_template_index_; + Sdc *sdc_; Sdc *sdc_backup_; Sta *sta_; }; diff --git a/search/Mode.cc b/search/Mode.cc new file mode 100644 index 00000000..80e5b5fd --- /dev/null +++ b/search/Mode.cc @@ -0,0 +1,146 @@ +// OpenSTA, Static Timing Analyzer +// Copyright (c) 2025, Parallax Software, Inc. +// +// This program is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see . +// +// The origin of this software must not be misrepresented; you must not +// claim that you wrote the original software. +// +// Altered source versions must be plainly marked as such, and must not be +// misrepresented as being the original software. +// +// This notice may not be removed or altered from any source distribution. + +#include "Mode.hh" + +#include "Sdc.hh" +#include "Sim.hh" +#include "ClkNetwork.hh" +#include "Genclks.hh" +#include "PathGroup.hh" + +namespace sta { + +Mode::Mode(const std::string &name, + size_t mode_index, + StaState *sta) : + StaState(sta), + name_(name), + mode_index_(mode_index), + sdc_(new Sdc(this, sta)), + sim_(new Sim(sta)), + clk_network_(new ClkNetwork(this, sta)), + genclks_(new Genclks(this, sta)), + path_groups_(nullptr) +{ +} + +Mode::~Mode() +{ + delete sdc_; + delete sim_; + delete clk_network_; + delete genclks_; + delete path_groups_; +} + +void +Mode::copyState(const StaState *sta) +{ + StaState::copyState(sta); + sdc_->copyState(sta); + sim_->copyState(sta); + clk_network_->copyState(sta); + genclks_->copyState(sta); +} + +void +Mode::clear() +{ + scenes_.clear(); + sim_->clear(); + clk_network_->clear(); + genclks_->clear(); +} + +void +Mode::addScene(Scene *scene) +{ + scenes_.push_back(scene); +} + +void +Mode::removeScene(Scene *scene) +{ + // std iterators just plain suck + scenes_.erase(std::remove(scenes_.begin(), scenes_.end(), scene), scenes_.end()); +} + +const SceneSet +Mode::sceneSet() const +{ + SceneSet scenes; + for (Scene *scene : scenes_) + scenes.insert(scene); + return scenes; +} + +//////////////////////////////////////////////////////////////// + +PathGroups * +Mode::makePathGroups(int group_path_count, + int endpoint_path_count, + bool unique_pins, + bool unique_edges, + float slack_min, + float slack_max, + StdStringSeq &group_names, + bool setup, + bool hold, + bool recovery, + bool removal, + bool clk_gating_setup, + bool clk_gating_hold, + bool unconstrained_paths) +{ + path_groups_ = new PathGroups(group_path_count, + endpoint_path_count, + unique_pins, unique_edges, + slack_min, slack_max, + group_names, + setup, hold, + recovery, removal, + clk_gating_setup, clk_gating_hold, + unconstrained_paths, + this); + return path_groups_; +} + +void +Mode::deletePathGroups() +{ + delete path_groups_; + path_groups_ = nullptr; +} + +PathGroupSeq +Mode::pathGroups(const PathEnd *path_end) const +{ + if (path_groups_) + return path_groups_->pathGroups(path_end); + else + return PathGroupSeq(); +} + +} // namespace diff --git a/search/Path.cc b/search/Path.cc index bf8fc2de..40d96baf 100644 --- a/search/Path.cc +++ b/search/Path.cc @@ -29,11 +29,10 @@ #include "Network.hh" #include "Graph.hh" #include "Clock.hh" -#include "DcalcAnalysisPt.hh" -#include "Corner.hh" -#include "PathAnalysisPt.hh" #include "Tag.hh" #include "TagGroup.hh" +#include "Sdc.hh" +#include "Mode.hh" #include "Search.hh" namespace sta { @@ -123,12 +122,6 @@ Path::Path(Vertex *vertex, } } -Path:: ~Path() -{ - if (is_enum_ && prev_path_ && prev_path_->is_enum_) - delete prev_path_; -} - void Path::init(Vertex *vertex, Arrival arrival, @@ -205,15 +198,13 @@ Path::to_string(const StaState *sta) const { if (isNull()) return "null path"; - else { - const PathAnalysisPt *path_ap = pathAnalysisPt(sta); - return stringPrintTmp("%s %s %s/%d %d", + else + return stringPrintTmp("%s %s %s/%s %d", vertex(sta)->to_string(sta).c_str(), transition(sta)->to_string().c_str(), - path_ap->pathMinMax()->to_string().c_str(), - path_ap->index(), + scene(sta)->name().c_str(), + minMax(sta)->to_string().c_str(), tagIndex(sta)); - } } bool @@ -259,6 +250,24 @@ Path::tag(const StaState *sta) const return search->tag(tag_index_); } +Scene * +Path::scene(const StaState *sta) const +{ + return tag(sta)->scene(); +} + +Mode * +Path::mode(const StaState *sta) const +{ + return tag(sta)->scene()->mode(); +} + +Sdc * +Path::sdc(const StaState *sta) const +{ + return tag(sta)->scene()->sdc(); +} + void Path::setTag(Tag *tag) { @@ -306,26 +315,26 @@ Path::isClock(const StaState *sta) const const MinMax * Path::minMax(const StaState *sta) const { - return tag(sta)->minMax(sta); + return tag(sta)->minMax(); +} + +DcalcAPIndex +Path::dcalcAnalysisPtIndex(const StaState *sta) const +{ + return scene(sta)->dcalcAnalysisPtIndex(minMax(sta)); } PathAPIndex Path::pathAnalysisPtIndex(const StaState *sta) const { - return pathAnalysisPt(sta)->index(); -} - -DcalcAnalysisPt * -Path::dcalcAnalysisPt(const StaState *sta) const -{ - return pathAnalysisPt(sta)->dcalcAnalysisPt(); + return scene(sta)->pathIndex(minMax(sta)); } Slew Path::slew(const StaState *sta) const { - return sta->graph()->slew(vertex(sta), transition(sta), - dcalcAnalysisPt(sta)->index()); + DcalcAPIndex slew_index = scene(sta)->dcalcAnalysisPtIndex(minMax(sta)); + return sta->graph()->slew(vertex(sta), transition(sta), slew_index); } const RiseFall * @@ -340,12 +349,6 @@ Path::rfIndex(const StaState *sta) const return transition(sta)->index(); } -PathAnalysisPt * -Path::pathAnalysisPt(const StaState *sta) const -{ - return tag(sta)->pathAnalysisPt(sta); -} - void Path::setArrival(Arrival arrival) { @@ -470,6 +473,23 @@ Path::setIsEnum(bool is_enum) //////////////////////////////////////////////////////////////// +const MinMax * +Path::tgtClkMinMax(const StaState *sta) const +{ + const MinMax *min_max = minMax(sta); + switch (mode(sta)->sdc()->analysisType()) { + case AnalysisType::single: + case AnalysisType::bc_wc: + return min_max; + case AnalysisType::ocv: + return min_max->opposite(); + default: + // suppress gcc warning + return min_max; + } +} +//////////////////////////////////////////////////////////////// + Path * Path::vertexPath(const Path *path, const StaState *sta) @@ -512,8 +532,8 @@ Path::vertexPath(const Vertex *vertex, int Path::cmpPinTrClk(const Path *path1, - const Path *path2, - const StaState *sta) + const Path *path2, + const StaState *sta) { if (path1 && path2) { const Pin *pin1 = path1->pin(sta); @@ -523,11 +543,11 @@ Path::cmpPinTrClk(const Path *path1, int tr_index1 = path1->rfIndex(sta); int tr_index2 = path2->rfIndex(sta); if (tr_index1 == tr_index2) - return cmpClk(path1, path2, sta); + return cmpClk(path1, path2, sta); else if (tr_index1 < tr_index2) - return -1; + return -1; else - return 1; + return 1; } else if (network->pathNameLess(pin1, pin2)) return -1; @@ -544,8 +564,8 @@ Path::cmpPinTrClk(const Path *path1, int Path::cmpClk(const Path *path1, - const Path *path2, - const StaState *sta) + const Path *path2, + const StaState *sta) { const ClockEdge *clk_edge1 = path1->clkEdge(sta); const ClockEdge *clk_edge2 = path2->clkEdge(sta); @@ -560,7 +580,7 @@ Path::cmpClk(const Path *path1, return 1; } else if (clk_edge1 == nullptr - && clk_edge2 == nullptr) + && clk_edge2 == nullptr) return 0; else if (clk_edge2) return -1; @@ -570,15 +590,15 @@ Path::cmpClk(const Path *path1, bool Path::equal(const Path *path1, - const Path *path2, - const StaState *sta) + const Path *path2, + const StaState *sta) { return (path1 == nullptr && path2 == nullptr) || (path1 - && path2 - && path1->vertexId(sta) == path2->vertexId(sta) - // Tag equal implies transition and path ap equal. - && path1->tagIndex(sta) == path2->tagIndex(sta)); + && path2 + && path1->vertexId(sta) == path2->vertexId(sta) + // Tag equal implies transition and path ap equal. + && path1->tagIndex(sta) == path2->tagIndex(sta)); } //////////////////////////////////////////////////////////////// @@ -590,23 +610,23 @@ PathLess::PathLess(const StaState *sta) : bool PathLess::operator()(const Path *path1, - const Path *path2) const + const Path *path2) const { return Path::less(path1, path2, sta_); } bool Path::less(const Path *path1, - const Path *path2, - const StaState *sta) + const Path *path2, + const StaState *sta) { return cmp(path1, path2, sta) < 0; } int Path::cmp(const Path *path1, - const Path *path2, - const StaState *sta) + const Path *path2, + const StaState *sta) { if (path1 == path2) return 0; @@ -625,19 +645,19 @@ Path::cmp(const Path *path1, TagIndex tag_index1 = path1->tagIndex(sta); TagIndex tag_index2 = path2->tagIndex(sta); if (tag_index1 == tag_index2) - return 0; + return 0; else if (tag_index1 < tag_index2) - return -1; + return -1; else - return 1; + return 1; } } } int Path::cmpNoCrpr(const Path *path1, - const Path *path2, - const StaState *sta) + const Path *path2, + const StaState *sta) { VertexId vertex_id1 = path1->vertexId(sta); VertexId vertex_id2 = path2->vertexId(sta); @@ -651,8 +671,8 @@ Path::cmpNoCrpr(const Path *path1, int Path::cmpAll(const Path *path1, - const Path *path2, - const StaState *sta) + const Path *path2, + const StaState *sta) { const Path *p1 = path1; const Path *p2 = path2; @@ -682,8 +702,8 @@ Path::cmpAll(const Path *path1, bool Path::lessAll(const Path *path1, - const Path *path2, - const StaState *sta) + const Path *path2, + const StaState *sta) { return cmpAll(path1, path2, sta) < 0; } @@ -691,35 +711,12 @@ Path::lessAll(const Path *path1, //////////////////////////////////////////////////////////////// VertexPathIterator::VertexPathIterator(Vertex *vertex, - const StaState *sta) : + const StaState *sta) : search_(sta->search()), - filtered_(false), + scene_(nullptr), + min_max_(nullptr), rf_(nullptr), - path_ap_(nullptr), - min_max_(nullptr), - paths_(vertex->paths()), - path_count_(0), - path_index_(0), - next_(nullptr) -{ - TagGroup *tag_group = search_->tagGroup(vertex); - if (tag_group) { - path_count_ = tag_group->pathCount(); - findNext(); - } -} - -// Iterate over vertex paths with the same transition and -// analysis pt but different but different tags. -VertexPathIterator::VertexPathIterator(Vertex *vertex, - const RiseFall *rf, - const PathAnalysisPt *path_ap, - const StaState *sta) : - search_(sta->search()), - filtered_(true), - rf_(rf), - path_ap_(path_ap), - min_max_(nullptr), + filtered_(false), paths_(vertex->paths()), path_count_(0), path_index_(0), @@ -733,14 +730,15 @@ VertexPathIterator::VertexPathIterator(Vertex *vertex, } VertexPathIterator::VertexPathIterator(Vertex *vertex, - const RiseFall *rf, - const MinMax *min_max, - const StaState *sta) : + const Scene *scene, + const MinMax *min_max, + const RiseFall *rf, + const StaState *sta) : search_(sta->search()), - filtered_(true), - rf_(rf), - path_ap_(nullptr), + scene_(scene), min_max_(min_max), + rf_(rf), + filtered_(true), paths_(vertex->paths()), path_count_(0), path_index_(0), @@ -754,15 +752,14 @@ VertexPathIterator::VertexPathIterator(Vertex *vertex, } VertexPathIterator::VertexPathIterator(Vertex *vertex, - const RiseFall *rf, - const PathAnalysisPt *path_ap, - const MinMax *min_max, - const StaState *sta) : + const RiseFall *rf, + const MinMax *min_max, + const StaState *sta) : search_(sta->search()), - filtered_(true), - rf_(rf), - path_ap_(path_ap), + scene_(nullptr), min_max_(min_max), + rf_(rf), + filtered_(true), paths_(vertex->paths()), path_count_(0), path_index_(0), @@ -782,12 +779,12 @@ VertexPathIterator::findNext() Path *path = &paths_[path_index_++]; if (filtered_) { const Tag *tag = path->tag(search_); - if ((rf_ == nullptr + if ((scene_ == nullptr + || path->scene(search_) == scene_) + && (rf_ == nullptr || tag->rfIndex() == rf_->index()) - && (path_ap_ == nullptr - || tag->pathAPIndex() == path_ap_->index()) && (min_max_ == nullptr - || tag->pathAnalysisPt(search_)->pathMinMax() == min_max_)) { + || path->minMax(search_) == min_max_)) { next_ = path; return; } diff --git a/search/PathAnalysisPt.cc b/search/PathAnalysisPt.cc index 476a8649..e69de29b 100644 --- a/search/PathAnalysisPt.cc +++ b/search/PathAnalysisPt.cc @@ -1,73 +0,0 @@ -// OpenSTA, Static Timing Analyzer -// Copyright (c) 2025, Parallax Software, Inc. -// -// This program is free software: you can redistribute it and/or modify -// it under the terms of the GNU General Public License as published by -// the Free Software Foundation, either version 3 of the License, or -// (at your option) any later version. -// -// This program is distributed in the hope that it will be useful, -// but WITHOUT ANY WARRANTY; without even the implied warranty of -// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -// GNU General Public License for more details. -// -// You should have received a copy of the GNU General Public License -// along with this program. If not, see . -// -// The origin of this software must not be misrepresented; you must not -// claim that you wrote the original software. -// -// Altered source versions must be plainly marked as such, and must not be -// misrepresented as being the original software. -// -// This notice may not be removed or altered from any source distribution. - -#include "PathAnalysisPt.hh" - -#include "StringUtil.hh" -#include "Corner.hh" -#include "Search.hh" - -namespace sta { - -PathAnalysisPt::PathAnalysisPt(Corner *corner, - PathAPIndex index, - const MinMax *path_min_max, - DcalcAnalysisPt *dcalc_ap) : - corner_(corner), - index_(index), - path_min_max_(path_min_max), - tgt_clk_ap_(nullptr), - dcalc_ap_(dcalc_ap) -{ -} - -std::string -PathAnalysisPt::to_string() const -{ - std::string name = corner_->name(); - name += '/'; - name += path_min_max_->to_string(); - return name; -} - -void -PathAnalysisPt::setTgtClkAnalysisPt(PathAnalysisPt *path_ap) -{ - tgt_clk_ap_ = path_ap; -} - -PathAnalysisPt * -PathAnalysisPt::insertionAnalysisPt(const EarlyLate *early_late) const -{ - return insertion_aps_[early_late->index()]; -} - -void -PathAnalysisPt::setInsertionAnalysisPt(const EarlyLate *early_late, - PathAnalysisPt *ap) -{ - insertion_aps_[early_late->index()] = ap; -} - -} // namespace diff --git a/search/PathEnd.cc b/search/PathEnd.cc index 12b539d4..2a7af024 100644 --- a/search/PathEnd.cc +++ b/search/PathEnd.cc @@ -34,10 +34,10 @@ #include "PortDelay.hh" #include "DataCheck.hh" #include "Sdc.hh" +#include "Mode.hh" #include "ExceptionPath.hh" #include "ClkInfo.hh" #include "Tag.hh" -#include "PathAnalysisPt.hh" #include "Search.hh" #include "ReportPath.hh" #include "Sim.hh" @@ -75,13 +75,13 @@ PathEnd::vertex(const StaState *sta) const const MinMax * PathEnd::minMax(const StaState *sta) const { - return path_->pathAnalysisPt(sta)->pathMinMax(); + return path_->minMax(sta); } const EarlyLate * PathEnd::pathEarlyLate(const StaState *sta) const { - return path_->pathAnalysisPt(sta)->pathMinMax(); + return path_->minMax(sta); } const EarlyLate * @@ -96,18 +96,6 @@ PathEnd::transition(const StaState *sta) const return path_->transition(sta); } -PathAPIndex -PathEnd::pathIndex(const StaState *sta) const -{ - return path_->pathAnalysisPtIndex(sta); -} - -PathAnalysisPt * -PathEnd::pathAnalysisPt(const StaState *sta) const -{ - return path_->pathAnalysisPt(sta); -} - const ClockEdge * PathEnd::sourceClkEdge(const StaState *sta) const { @@ -290,7 +278,7 @@ PathEnd::multiCyclePath() const int PathEnd::exceptPathCmp(const PathEnd *path_end, - const StaState *) const + const StaState *) const { Type type1 = type(); Type type2 = path_end->type(); @@ -306,46 +294,46 @@ PathEnd::exceptPathCmp(const PathEnd *path_end, Delay PathEnd::checkTgtClkDelay(const Path *tgt_clk_path, - const ClockEdge *tgt_clk_edge, - const TimingRole *check_role, - const StaState *sta) + const ClockEdge *tgt_clk_edge, + const TimingRole *check_role, + const StaState *sta) { Delay insertion, latency; checkTgtClkDelay(tgt_clk_path, tgt_clk_edge, check_role, sta, - insertion, latency); + insertion, latency); return Delay(insertion + latency); } void PathEnd::checkTgtClkDelay(const Path *tgt_clk_path, - const ClockEdge *tgt_clk_edge, - const TimingRole *check_role, - const StaState *sta, - // Return values. - Delay &insertion, - Delay &latency) + const ClockEdge *tgt_clk_edge, + const TimingRole *check_role, + const StaState *sta, + // Return values. + Delay &insertion, + Delay &latency) { if (tgt_clk_path) { Search *search = sta->search(); // If propagated clk, adjust required time for target clk network delay. const MinMax *min_max = tgt_clk_path->minMax(sta); const EarlyLate *early_late = check_role->tgtClkEarlyLate(); - const PathAnalysisPt *tgt_path_ap = tgt_clk_path->pathAnalysisPt(sta); const ClkInfo *clk_info = tgt_clk_path->clkInfo(sta); const Pin *tgt_src_pin = clk_info->clkSrc(); const Clock *tgt_clk = tgt_clk_edge->clock(); const RiseFall *tgt_clk_rf = tgt_clk_edge->transition(); + const Mode *mode = tgt_clk_path->mode(sta); insertion = search->clockInsertion(tgt_clk, tgt_src_pin, tgt_clk_rf, - min_max, early_late, tgt_path_ap); + min_max, early_late, mode); if (clk_info->isPropagated() - // Data check target clock is always propagated. - || check_role->isDataCheck()) { + // Data check target clock is always propagated. + || check_role->isDataCheck()) { // Propagated clock. Propagated arrival is seeded with // early_late==path_min_max insertion delay. Arrival clk_arrival = tgt_clk_path->arrival(); Delay path_insertion = search->clockInsertion(tgt_clk, tgt_src_pin, - tgt_clk_rf, min_max, - min_max, tgt_path_ap); + tgt_clk_rf, min_max, + min_max, mode); latency = delayRemove(clk_arrival - tgt_clk_edge->time(), path_insertion); } else @@ -360,20 +348,20 @@ PathEnd::checkTgtClkDelay(const Path *tgt_clk_path, float PathEnd::checkClkUncertainty(const ClockEdge *src_clk_edge, - const ClockEdge *tgt_clk_edge, - const Path *tgt_clk_path, - const TimingRole *check_role, - const StaState *sta) + const ClockEdge *tgt_clk_edge, + const Path *tgt_clk_path, + const TimingRole *check_role, + const Sdc *sdc) { float inter_clk; bool inter_exists; - checkInterClkUncertainty(src_clk_edge, tgt_clk_edge, check_role, sta, - inter_clk, inter_exists); + checkInterClkUncertainty(src_clk_edge, tgt_clk_edge, check_role, sdc, + inter_clk, inter_exists); if (inter_exists) return inter_clk; else - return checkTgtClkUncertainty(tgt_clk_path, tgt_clk_edge, check_role, sta); + return checkTgtClkUncertainty(tgt_clk_path, tgt_clk_edge, check_role, sdc); } float @@ -383,7 +371,7 @@ PathEnd::checkTgtClkUncertainty(const Path *tgt_clk_path, const StaState *sta) { const MinMax *min_max = check_role->pathMinMax(); - ClockUncertainties *uncertainties = nullptr; + const ClockUncertainties *uncertainties = nullptr; if (tgt_clk_path && tgt_clk_path->isClock(sta)) uncertainties = tgt_clk_path->clkInfo(sta)->uncertainties(); else if (tgt_clk_edge) @@ -403,13 +391,12 @@ PathEnd::checkTgtClkUncertainty(const Path *tgt_clk_path, void PathEnd::checkInterClkUncertainty(const ClockEdge *src_clk_edge, - const ClockEdge *tgt_clk_edge, - const TimingRole *check_role, - const StaState *sta, - float &uncertainty, - bool &exists) + const ClockEdge *tgt_clk_edge, + const TimingRole *check_role, + const Sdc *sdc, + float &uncertainty, + bool &exists) { - Sdc *sdc = sta->sdc(); if (src_clk_edge && src_clk_edge != sdc->defaultArrivalClockEdge() && tgt_clk_edge) { @@ -420,7 +407,7 @@ PathEnd::checkInterClkUncertainty(const ClockEdge *src_clk_edge, check_role->pathMinMax(), uncertainty, exists); if (exists - && check_role->genericRole() == TimingRole::setup()) + && check_role->genericRole() == TimingRole::setup()) uncertainty = -uncertainty; } else @@ -512,7 +499,7 @@ PathEndUnconstrained::typeName() const //////////////////////////////////////////////////////////////// PathEndClkConstrained::PathEndClkConstrained(Path *path, - Path *clk_path) : + Path *clk_path) : PathEnd(path), clk_path_(clk_path), crpr_(0.0), @@ -521,9 +508,9 @@ PathEndClkConstrained::PathEndClkConstrained(Path *path, } PathEndClkConstrained::PathEndClkConstrained(Path *path, - Path *clk_path, - Crpr crpr, - bool crpr_valid) : + Path *clk_path, + Crpr crpr, + bool crpr_valid) : PathEnd(path), clk_path_(clk_path), crpr_(crpr), @@ -542,18 +529,18 @@ float PathEndClkConstrained::sourceClkOffset(const StaState *sta) const { return sourceClkOffset(sourceClkEdge(sta), - targetClkEdge(sta), - checkRole(sta), - sta); + targetClkEdge(sta), + checkRole(sta), + sta); } float PathEndClkConstrained::sourceClkOffset(const ClockEdge *src_clk_edge, - const ClockEdge *tgt_clk_edge, - const TimingRole *check_role, - const StaState *sta) const + const ClockEdge *tgt_clk_edge, + const TimingRole *check_role, + const StaState *sta) const { - Sdc *sdc = sta->sdc(); + Sdc *sdc = path_->sdc(sta); CycleAccting *acct = sdc->cycleAccting(src_clk_edge, tgt_clk_edge); return acct->sourceTimeOffset(check_role); } @@ -590,7 +577,7 @@ PathEndClkConstrained::targetClkOffset(const StaState *sta) const const ClockEdge *src_clk_edge = sourceClkEdge(sta); const ClockEdge *tgt_clk_edge = targetClkEdge(sta); const TimingRole *check_role = checkRole(sta); - Sdc *sdc = sta->sdc(); + Sdc *sdc = path_->sdc(sta); CycleAccting *acct = sdc->cycleAccting(src_clk_edge, tgt_clk_edge); return acct->targetTimeOffset(check_role); } @@ -620,7 +607,7 @@ PathEndClkConstrained::targetClkTime(const StaState *sta) const const ClockEdge *src_clk_edge = sourceClkEdge(sta); const ClockEdge *tgt_clk_edge = targetClkEdge(sta); const TimingRole *check_role = checkRole(sta); - Sdc *sdc = sta->sdc(); + Sdc *sdc = path_->sdc(sta); CycleAccting *acct = sdc->cycleAccting(src_clk_edge, tgt_clk_edge); return acct->requiredTime(check_role); } @@ -635,12 +622,13 @@ PathEndClkConstrained::targetClkArrival(const StaState *sta) const Arrival PathEndClkConstrained::targetClkArrivalNoCrpr(const StaState *sta) const { + Sdc *sdc = path_->sdc(sta); return targetClkTime(sta) + targetClkDelay(sta) + checkClkUncertainty(sourceClkEdge(sta), - targetClkEdge(sta), - targetClkPath(), - checkRole(sta), sta) + targetClkEdge(sta), + targetClkPath(), + checkRole(sta), sdc) + targetClkMcpAdjustment(sta); } @@ -655,8 +643,8 @@ PathEndClkConstrained::targetClkInsertionDelay(const StaState *sta) const { Arrival insertion, latency; checkTgtClkDelay(targetClkPath(), targetClkEdge(sta), - checkRole(sta), sta, - insertion, latency); + checkRole(sta), sta, + insertion, latency); return insertion; } @@ -667,10 +655,11 @@ PathEndClkConstrained::targetNonInterClkUncertainty(const StaState *sta) const const ClockEdge *tgt_clk_edge = targetClkEdge(sta); const TimingRole *check_role = checkRole(sta); + Sdc *sdc = path_->sdc(sta); float inter_clk; bool inter_exists; checkInterClkUncertainty(src_clk_edge, tgt_clk_edge, check_role, - sta, inter_clk, inter_exists); + sdc, inter_clk, inter_exists); if (inter_exists) // This returns non inter-clock uncertainty. return 0.0; @@ -681,11 +670,12 @@ PathEndClkConstrained::targetNonInterClkUncertainty(const StaState *sta) const float PathEndClkConstrained::interClkUncertainty(const StaState *sta) const { + Sdc *sdc = path_->sdc(sta); float uncertainty; bool exists; checkInterClkUncertainty(sourceClkEdge(sta), targetClkEdge(sta), - checkRole(sta), sta, - uncertainty, exists); + checkRole(sta), sdc, + uncertainty, exists); if (exists) return uncertainty; else @@ -695,8 +685,9 @@ PathEndClkConstrained::interClkUncertainty(const StaState *sta) const float PathEndClkConstrained::targetClkUncertainty(const StaState *sta) const { + Sdc *sdc = path_->sdc(sta); return checkClkUncertainty(sourceClkEdge(sta), targetClkEdge(sta), - targetClkPath(), checkRole(sta), sta); + targetClkPath(), checkRole(sta), sdc); } Crpr @@ -741,7 +732,7 @@ PathEndClkConstrained::slack(const StaState *sta) const int PathEndClkConstrained::exceptPathCmp(const PathEnd *path_end, - const StaState *sta) const + const StaState *sta) const { int cmp = PathEnd::exceptPathCmp(path_end, sta); if (cmp == 0) { @@ -757,18 +748,18 @@ PathEndClkConstrained::exceptPathCmp(const PathEnd *path_end, //////////////////////////////////////////////////////////////// PathEndClkConstrainedMcp::PathEndClkConstrainedMcp(Path *path, - Path *clk_path, - MultiCyclePath *mcp) : + Path *clk_path, + MultiCyclePath *mcp) : PathEndClkConstrained(path, clk_path), mcp_(mcp) { } PathEndClkConstrainedMcp::PathEndClkConstrainedMcp(Path *path, - Path *clk_path, - MultiCyclePath *mcp, - Crpr crpr, - bool crpr_valid) : + Path *clk_path, + MultiCyclePath *mcp, + Crpr crpr, + bool crpr_valid) : PathEndClkConstrained(path, clk_path, crpr, crpr_valid), mcp_(mcp) { @@ -782,56 +773,56 @@ PathEndClkConstrainedMcp::targetClkMcpAdjustment(const StaState *sta) const float PathEndClkConstrainedMcp::checkMcpAdjustment(const Path *path, - const ClockEdge *tgt_clk_edge, - const StaState *sta) const + const ClockEdge *tgt_clk_edge, + const StaState *sta) const { if (mcp_) { const TimingRole *check_role = checkRole(sta); const MinMax *min_max = check_role->pathMinMax(); const ClockEdge *src_clk_edge = path->clkEdge(sta); - Sdc *sdc = sta->sdc(); + Sdc *sdc = path_->sdc(sta); if (min_max == MinMax::max()) return PathEnd::checkSetupMcpAdjustment(src_clk_edge, tgt_clk_edge, - mcp_, setupDefaultCycles(), sdc); + mcp_, setupDefaultCycles(), sdc); else { // Hold check. // Default arrival clock is a proxy for the target clock. if (src_clk_edge == nullptr) - src_clk_edge = tgt_clk_edge; + src_clk_edge = tgt_clk_edge; else if (src_clk_edge->clock() == sdc->defaultArrivalClock()) - src_clk_edge = tgt_clk_edge->clock()->edge(src_clk_edge->transition()); + src_clk_edge = tgt_clk_edge->clock()->edge(src_clk_edge->transition()); const MultiCyclePath *setup_mcp; const MultiCyclePath *hold_mcp; // Hold checks also need the setup mcp for cycle accounting. findHoldMcps(tgt_clk_edge, setup_mcp, hold_mcp, sta); if (setup_mcp && hold_mcp) { - int setup_mult = setup_mcp->pathMultiplier(MinMax::max()); - int hold_mult = hold_mcp->pathMultiplier(MinMax::min()); - const ClockEdge *setup_clk_edge = - setup_mcp->useEndClk() ? tgt_clk_edge : src_clk_edge; - float setup_period = setup_clk_edge->clock()->period(); - const ClockEdge *hold_clk_edge = - hold_mcp->useEndClk() ? tgt_clk_edge : src_clk_edge; - float hold_period = hold_clk_edge->clock()->period(); - return (setup_mult - 1) * setup_period - hold_mult * hold_period; + int setup_mult = setup_mcp->pathMultiplier(MinMax::max()); + int hold_mult = hold_mcp->pathMultiplier(MinMax::min()); + const ClockEdge *setup_clk_edge = + setup_mcp->useEndClk() ? tgt_clk_edge : src_clk_edge; + float setup_period = setup_clk_edge->clock()->period(); + const ClockEdge *hold_clk_edge = + hold_mcp->useEndClk() ? tgt_clk_edge : src_clk_edge; + float hold_period = hold_clk_edge->clock()->period(); + return (setup_mult - 1) * setup_period - hold_mult * hold_period; } else if (hold_mcp) { - int mult = hold_mcp->pathMultiplier(min_max); - const ClockEdge *clk_edge = - hold_mcp->useEndClk() ? tgt_clk_edge : src_clk_edge; - float period = clk_edge->clock()->period(); - return -mult * period; + int mult = hold_mcp->pathMultiplier(min_max); + const ClockEdge *clk_edge = + hold_mcp->useEndClk() ? tgt_clk_edge : src_clk_edge; + float period = clk_edge->clock()->period(); + return -mult * period; } else if (setup_mcp) { - int mult = setup_mcp->pathMultiplier(min_max); - const ClockEdge *clk_edge = - setup_mcp->useEndClk() ? tgt_clk_edge : src_clk_edge; - float period = clk_edge->clock()->period(); - return (mult - 1) * period; + int mult = setup_mcp->pathMultiplier(min_max); + const ClockEdge *clk_edge = + setup_mcp->useEndClk() ? tgt_clk_edge : src_clk_edge; + float period = clk_edge->clock()->period(); + return (mult - 1) * period; } else - return 0.0; + return 0.0; } } else @@ -840,10 +831,10 @@ PathEndClkConstrainedMcp::checkMcpAdjustment(const Path *path, float PathEnd::checkSetupMcpAdjustment(const ClockEdge *src_clk_edge, - const ClockEdge *tgt_clk_edge, - const MultiCyclePath *mcp, - int default_cycles, - Sdc *sdc) + const ClockEdge *tgt_clk_edge, + const MultiCyclePath *mcp, + int default_cycles, + Sdc *sdc) { if (mcp) { // Default arrival clock is a proxy for the target clock. @@ -854,7 +845,7 @@ PathEnd::checkSetupMcpAdjustment(const ClockEdge *src_clk_edge, if (mcp->minMax()->matches(MinMax::max())) { int mult = mcp->pathMultiplier(MinMax::max()); const ClockEdge *clk_edge = - mcp->useEndClk() ? tgt_clk_edge : src_clk_edge; + mcp->useEndClk() ? tgt_clk_edge : src_clk_edge; float period = clk_edge->clock()->period(); return (mult - default_cycles) * period; } @@ -878,9 +869,9 @@ PathEndClkConstrained::slackNoCrpr(const StaState *sta) const void PathEndClkConstrainedMcp::findHoldMcps(const ClockEdge *tgt_clk_edge, - const MultiCyclePath *&setup_mcp, - const MultiCyclePath *&hold_mcp, - const StaState *sta) const + const MultiCyclePath *&setup_mcp, + const MultiCyclePath *&hold_mcp, + const StaState *sta) const { Pin *pin = path_->pin(sta); @@ -892,25 +883,27 @@ PathEndClkConstrainedMcp::findHoldMcps(const ClockEdge *tgt_clk_edge, hold_mcp = mcp_; setup_mcp = dynamic_cast(search->exceptionTo(ExceptionPathType::multi_cycle, - path_, pin, rf, - tgt_clk_edge, - MinMax::max(), true, - false)); + path_, pin, rf, + tgt_clk_edge, + MinMax::max(), true, + false, + path_->sdc(sta))); } else { setup_mcp = mcp_; hold_mcp = dynamic_cast(search->exceptionTo(ExceptionPathType::multi_cycle, - path_, pin, rf, - tgt_clk_edge, - MinMax::min(), true, - false)); + path_, pin, rf, + tgt_clk_edge, + MinMax::min(), true, + false, + path_->sdc(sta))); } } int PathEndClkConstrainedMcp::exceptPathCmp(const PathEnd *path_end, - const StaState *sta) const + const StaState *sta) const { int cmp = PathEndClkConstrained::exceptPathCmp(path_end, sta); if (cmp == 0) { @@ -931,11 +924,11 @@ PathEndClkConstrainedMcp::exceptPathCmp(const PathEnd *path_end, //////////////////////////////////////////////////////////////// PathEndCheck::PathEndCheck(Path *path, - TimingArc *check_arc, - Edge *check_edge, - Path *clk_path, - MultiCyclePath *mcp, - const StaState *) : + TimingArc *check_arc, + Edge *check_edge, + Path *clk_path, + MultiCyclePath *mcp, + const StaState *) : PathEndClkConstrainedMcp(path, clk_path, mcp), check_arc_(check_arc), check_edge_(check_edge) @@ -943,12 +936,12 @@ PathEndCheck::PathEndCheck(Path *path, } PathEndCheck::PathEndCheck(Path *path, - TimingArc *check_arc, - Edge *check_edge, - Path *clk_path, - MultiCyclePath *mcp, - Crpr crpr, - bool crpr_valid) : + TimingArc *check_arc, + Edge *check_edge, + Path *clk_path, + MultiCyclePath *mcp, + Crpr crpr, + bool crpr_valid) : PathEndClkConstrainedMcp(path, clk_path, mcp, crpr, crpr_valid), check_arc_(check_arc), check_edge_(check_edge) @@ -959,7 +952,7 @@ PathEnd * PathEndCheck::copy() const { return new PathEndCheck(path_, check_arc_, check_edge_, - clk_path_, mcp_, crpr_, crpr_valid_); + clk_path_, mcp_, crpr_, crpr_valid_); } PathEnd::Type @@ -996,13 +989,15 @@ ArcDelay PathEndCheck::margin(const StaState *sta) const { return sta->search()->deratedDelay(clk_path_->vertex(sta), - check_arc_, check_edge_, false, - pathAnalysisPt(sta)); + check_arc_, check_edge_, false, + path_->minMax(sta), + path_->dcalcAnalysisPtIndex(sta), + path_->sdc(sta)); } int PathEndCheck::exceptPathCmp(const PathEnd *path_end, - const StaState *sta) const + const StaState *sta) const { int cmp = PathEndClkConstrainedMcp::exceptPathCmp(path_end, sta); if (cmp == 0) { @@ -1087,21 +1082,19 @@ PathEndCheck::macroClkTreeDelay(const StaState *sta) const //////////////////////////////////////////////////////////////// PathEndLatchCheck::PathEndLatchCheck(Path *path, - TimingArc *check_arc, - Edge *check_edge, - Path *disable_path, - MultiCyclePath *mcp, - PathDelay *path_delay, - const StaState *sta) : + TimingArc *check_arc, + Edge *check_edge, + Path *disable_path, + MultiCyclePath *mcp, + PathDelay *path_delay, + const StaState *sta) : PathEndCheck(path, check_arc, check_edge, nullptr, mcp, sta), disable_path_(disable_path), path_delay_(path_delay), src_clk_arrival_(0.0) { Latches *latches = sta->latches(); - Path *enable_path = - latches->latchEnableOtherPath(disable_path, - disable_path->pathAnalysisPt(sta)); + Path *enable_path = latches->latchEnableOtherPath(disable_path); clk_path_ = enable_path; Search *search = sta->search(); // Same as PathEndPathDelay::findRequired. @@ -1110,15 +1103,15 @@ PathEndLatchCheck::PathEndLatchCheck(Path *path, } PathEndLatchCheck::PathEndLatchCheck(Path *path, - TimingArc *check_arc, - Edge *check_edge, - Path *clk_path, - Path *disable_path, - MultiCyclePath *mcp, - PathDelay *path_delay, - Delay src_clk_arrival, - Crpr crpr, - bool crpr_valid) : + TimingArc *check_arc, + Edge *check_edge, + Path *clk_path, + Path *disable_path, + MultiCyclePath *mcp, + PathDelay *path_delay, + Delay src_clk_arrival, + Crpr crpr, + bool crpr_valid) : PathEndCheck(path, check_arc, check_edge, clk_path, mcp, crpr, crpr_valid), disable_path_(disable_path), path_delay_(path_delay), @@ -1130,8 +1123,8 @@ PathEnd * PathEndLatchCheck::copy() const { return new PathEndLatchCheck(path_, check_arc_, check_edge_, - clk_path_, disable_path_, mcp_, path_delay_, - src_clk_arrival_, crpr_, crpr_valid_); + clk_path_, disable_path_, mcp_, path_delay_, + src_clk_arrival_, crpr_, crpr_valid_); } PathEnd::Type @@ -1177,9 +1170,9 @@ PathEndLatchCheck::sourceClkOffset(const StaState *sta) const return pathDelaySrcClkOffset(path_, path_delay_, src_clk_arrival_, sta); else return PathEndClkConstrained::sourceClkOffset(sourceClkEdge(sta), - disable_path_->clkEdge(sta), - TimingRole::setup(), - sta); + disable_path_->clkEdge(sta), + TimingRole::setup(), + sta); } const TimingRole * @@ -1219,9 +1212,9 @@ PathEndLatchCheck::requiredTime(const StaState *sta) const Arrival borrow, adjusted_data_arrival, time_given_to_startpoint; Latches *latches = sta->latches(); latches->latchRequired(path_, targetClkPath(), latchDisable(), - mcp_, path_delay_, src_clk_arrival_, margin(sta), - required, borrow, adjusted_data_arrival, - time_given_to_startpoint); + mcp_, path_delay_, src_clk_arrival_, margin(sta), + required, borrow, adjusted_data_arrival, + time_given_to_startpoint); return required; } @@ -1232,47 +1225,47 @@ PathEndLatchCheck::borrow(const StaState *sta) const Required required; Arrival borrow, adjusted_data_arrival, time_given_to_startpoint; latches->latchRequired(path_, targetClkPath(), latchDisable(), - mcp_, path_delay_, src_clk_arrival_, margin(sta), - required, borrow, adjusted_data_arrival, - time_given_to_startpoint); + mcp_, path_delay_, src_clk_arrival_, margin(sta), + required, borrow, adjusted_data_arrival, + time_given_to_startpoint); return borrow; } void PathEndLatchCheck::latchRequired(const StaState *sta, - // Return values. - Required &required, - Delay &borrow, - Arrival &adjusted_data_arrival, - Delay &time_given_to_startpoint) const + // Return values. + Required &required, + Delay &borrow, + Arrival &adjusted_data_arrival, + Delay &time_given_to_startpoint) const { Latches *latches = sta->latches(); latches->latchRequired(path_, targetClkPath(), latchDisable(), - mcp_, path_delay_, src_clk_arrival_, margin(sta), - required, borrow, adjusted_data_arrival, - time_given_to_startpoint); + mcp_, path_delay_, src_clk_arrival_, margin(sta), + required, borrow, adjusted_data_arrival, + time_given_to_startpoint); } void PathEndLatchCheck::latchBorrowInfo(const StaState *sta, - // Return values. - float &nom_pulse_width, - Delay &open_latency, - Delay &latency_diff, - float &open_uncertainty, - Crpr &open_crpr, - Crpr &crpr_diff, - Delay &max_borrow, - bool &borrow_limit_exists) const + // Return values. + float &nom_pulse_width, + Delay &open_latency, + Delay &latency_diff, + float &open_uncertainty, + Crpr &open_crpr, + Crpr &crpr_diff, + Delay &max_borrow, + bool &borrow_limit_exists) const { Latches *latches = sta->latches(); latches->latchBorrowInfo(path_, targetClkPath(), latchDisable(), - margin(sta), - path_delay_ && ignoreClkLatency(sta), - nom_pulse_width, open_latency, - latency_diff, open_uncertainty, - open_crpr, crpr_diff, max_borrow, - borrow_limit_exists); + margin(sta), + path_delay_ && ignoreClkLatency(sta), + nom_pulse_width, open_latency, + latency_diff, open_uncertainty, + open_crpr, crpr_diff, max_borrow, + borrow_limit_exists); } Arrival @@ -1296,7 +1289,7 @@ PathEndLatchCheck::targetClkWidth(const StaState *sta) const int PathEndLatchCheck::exceptPathCmp(const PathEnd *path_end, - const StaState *sta) const + const StaState *sta) const { int cmp = PathEndClkConstrainedMcp::exceptPathCmp(path_end, sta); if (cmp == 0) { @@ -1325,10 +1318,10 @@ PathEndLatchCheck::ignoreClkLatency(const StaState *sta) const /////////////////////////////////////////////////////////////// PathEndOutputDelay::PathEndOutputDelay(OutputDelay *output_delay, - Path *path, - Path *clk_path, - MultiCyclePath *mcp, - const StaState *) : + Path *path, + Path *clk_path, + MultiCyclePath *mcp, + const StaState *) : // No target clk_path_ for output delays. PathEndClkConstrainedMcp(path, clk_path, mcp), output_delay_(output_delay) @@ -1336,11 +1329,11 @@ PathEndOutputDelay::PathEndOutputDelay(OutputDelay *output_delay, } PathEndOutputDelay::PathEndOutputDelay(OutputDelay *output_delay, - Path *path, - Path *clk_path, - MultiCyclePath *mcp, - Crpr crpr, - bool crpr_valid) : + Path *path, + Path *clk_path, + MultiCyclePath *mcp, + Crpr crpr, + bool crpr_valid) : PathEndClkConstrainedMcp(path, clk_path, mcp, crpr, crpr_valid), output_delay_(output_delay) { @@ -1350,7 +1343,7 @@ PathEnd * PathEndOutputDelay::copy() const { return new PathEndOutputDelay(output_delay_, path_, clk_path_, - mcp_, crpr_, crpr_valid_); + mcp_, crpr_, crpr_valid_); } PathEnd::Type @@ -1385,8 +1378,8 @@ PathEndOutputDelay::margin(const StaState *sta) const float PathEnd::outputDelayMargin(OutputDelay *output_delay, - const Path *path, - const StaState *sta) + const Path *path, + const StaState *sta) { const RiseFall *rf = path->transition(sta); const MinMax *min_max = path->minMax(sta); @@ -1452,42 +1445,41 @@ PathEndOutputDelay::targetClkDelay(const StaState *sta) const Arrival PathEndOutputDelay::tgtClkDelay(const ClockEdge *tgt_clk_edge, - const TimingRole *check_role, - const StaState *sta) const + const TimingRole *check_role, + const StaState *sta) const { Arrival insertion, latency; tgtClkDelay(tgt_clk_edge, check_role, sta, - insertion, latency); + insertion, latency); return insertion + latency; } void PathEndOutputDelay::tgtClkDelay(const ClockEdge *tgt_clk_edge, - const TimingRole *check_role, - const StaState *sta, - // Return values. - Arrival &insertion, - Arrival &latency) const + const TimingRole *check_role, + const StaState *sta, + // Return values. + Arrival &insertion, + Arrival &latency) const { // Early late: setup early, hold late. const EarlyLate *early_late = check_role->tgtClkEarlyLate(); // Latency min_max depends on bc_wc or ocv. - const PathAnalysisPt *path_ap = path_->pathAnalysisPt(sta); - const MinMax *latency_min_max = path_ap->tgtClkAnalysisPt()->pathMinMax(); + const MinMax *latency_min_max = path_->tgtClkMinMax(sta); Clock *tgt_clk = tgt_clk_edge->clock(); const RiseFall *tgt_clk_rf = tgt_clk_edge->transition(); + const Mode *mode = path_->mode(sta); if (!output_delay_->sourceLatencyIncluded()) insertion = sta->search()->clockInsertion(tgt_clk, - tgt_clk->defaultPin(), - tgt_clk_rf, - latency_min_max, - early_late, path_ap); + tgt_clk->defaultPin(), + tgt_clk_rf, + latency_min_max, + early_late, mode); else insertion = 0.0; - const Sdc *sdc = sta->sdc(); if (!tgt_clk->isPropagated() && !output_delay_->networkLatencyIncluded()) - latency = sdc->clockLatency(tgt_clk, tgt_clk_rf, latency_min_max); + latency = mode->sdc()->clockLatency(tgt_clk, tgt_clk_rf, latency_min_max); else latency = 0.0; } @@ -1500,14 +1492,14 @@ PathEndOutputDelay::targetClkInsertionDelay(const StaState *sta) const else { Arrival insertion, latency; tgtClkDelay(targetClkEdge(sta), checkRole(sta), sta, - insertion, latency); + insertion, latency); return insertion; } } int PathEndOutputDelay::exceptPathCmp(const PathEnd *path_end, - const StaState *sta) const + const StaState *sta) const { int cmp = PathEndClkConstrainedMcp::exceptPathCmp(path_end, sta); if (cmp == 0) { @@ -1528,11 +1520,11 @@ PathEndOutputDelay::exceptPathCmp(const PathEnd *path_end, //////////////////////////////////////////////////////////////// PathEndGatedClock::PathEndGatedClock(Path *gating_ref, - Path *clk_path, - const TimingRole *check_role, - MultiCyclePath *mcp, - ArcDelay margin, - const StaState *) : + Path *clk_path, + const TimingRole *check_role, + MultiCyclePath *mcp, + ArcDelay margin, + const StaState *) : PathEndClkConstrainedMcp(gating_ref, clk_path, mcp), check_role_(check_role), margin_(margin) @@ -1540,12 +1532,12 @@ PathEndGatedClock::PathEndGatedClock(Path *gating_ref, } PathEndGatedClock::PathEndGatedClock(Path *gating_ref, - Path *clk_path, - const TimingRole *check_role, - MultiCyclePath *mcp, - ArcDelay margin, - Crpr crpr, - bool crpr_valid) : + Path *clk_path, + const TimingRole *check_role, + MultiCyclePath *mcp, + ArcDelay margin, + Crpr crpr, + bool crpr_valid) : PathEndClkConstrainedMcp(gating_ref, clk_path, mcp, crpr, crpr_valid), check_role_(check_role), margin_(margin) @@ -1556,7 +1548,7 @@ PathEnd * PathEndGatedClock::copy() const { return new PathEndGatedClock(path_, clk_path_, check_role_, - mcp_, margin_, crpr_, crpr_valid_); + mcp_, margin_, crpr_, crpr_valid_); } PathEnd::Type @@ -1591,7 +1583,7 @@ PathEndGatedClock::reportShort(const ReportPath *report) const int PathEndGatedClock::exceptPathCmp(const PathEnd *path_end, - const StaState *sta) const + const StaState *sta) const { int cmp = PathEndClkConstrainedMcp::exceptPathCmp(path_end, sta); if (cmp == 0) { @@ -1612,10 +1604,10 @@ PathEndGatedClock::exceptPathCmp(const PathEnd *path_end, //////////////////////////////////////////////////////////////// PathEndDataCheck::PathEndDataCheck(DataCheck *check, - Path *data_path, - Path *data_clk_path, - MultiCyclePath *mcp, - const StaState *sta) : + Path *data_path, + Path *data_clk_path, + MultiCyclePath *mcp, + const StaState *sta) : PathEndClkConstrainedMcp(data_path, nullptr, mcp), data_clk_path_(data_clk_path), check_(check) @@ -1639,15 +1631,15 @@ PathEndDataCheck::clkPath(Path *path, if (prev_arc) { const TimingRole *prev_role = prev_arc->role(); if (prev_role == TimingRole::regClkToQ() - || prev_role == TimingRole::latchEnToQ()) { + || prev_role == TimingRole::latchEnToQ()) { prev_path = p->prevPath(); - return prev_path; + return prev_path; } else if (prev_role == TimingRole::latchDtoQ()) { - const Latches *latches = sta->latches(); - Edge *prev_edge = p->prevEdge(sta); - Path *enable_path = latches->latchEnablePath(p, prev_edge); - return enable_path; + const Latches *latches = sta->latches(); + Edge *prev_edge = p->prevEdge(sta); + Path *enable_path = latches->latchEnablePath(p, prev_edge); + return enable_path; } } p = prev_path; @@ -1656,12 +1648,12 @@ PathEndDataCheck::clkPath(Path *path, } PathEndDataCheck::PathEndDataCheck(DataCheck *check, - Path *data_path, - Path *data_clk_path, - Path *clk_path, - MultiCyclePath *mcp, - Crpr crpr, - bool crpr_valid) : + Path *data_path, + Path *data_clk_path, + Path *clk_path, + MultiCyclePath *mcp, + Crpr crpr, + bool crpr_valid) : PathEndClkConstrainedMcp(data_path, clk_path, mcp, crpr, crpr_valid), data_clk_path_(data_clk_path), check_(check) @@ -1672,7 +1664,7 @@ PathEnd * PathEndDataCheck::copy() const { return new PathEndDataCheck(check_, path_, data_clk_path_, - clk_path_, mcp_, crpr_, crpr_valid_); + clk_path_, mcp_, crpr_, crpr_valid_); } PathEnd::Type @@ -1718,9 +1710,9 @@ PathEndDataCheck::margin(const StaState *sta) const float margin; bool margin_exists; check_->margin(data_clk_path_->transition(sta), - path_->transition(sta), - path_->minMax(sta), - margin, margin_exists); + path_->transition(sta), + path_->minMax(sta), + margin, margin_exists); return margin; } @@ -1747,7 +1739,7 @@ PathEndDataCheck::reportShort(const ReportPath *report) const int PathEndDataCheck::exceptPathCmp(const PathEnd *path_end, - const StaState *sta) const + const StaState *sta) const { int cmp = PathEndClkConstrainedMcp::exceptPathCmp(path_end, sta); if (cmp == 0) { @@ -1768,8 +1760,8 @@ PathEndDataCheck::exceptPathCmp(const PathEnd *path_end, //////////////////////////////////////////////////////////////// PathEndPathDelay::PathEndPathDelay(PathDelay *path_delay, - Path *path, - const StaState *sta): + Path *path, + const StaState *sta): PathEndClkConstrained(path, nullptr), path_delay_(path_delay), check_arc_(nullptr), @@ -1780,9 +1772,9 @@ PathEndPathDelay::PathEndPathDelay(PathDelay *path_delay, } PathEndPathDelay::PathEndPathDelay(PathDelay *path_delay, - Path *path, - OutputDelay *output_delay, - const StaState *sta): + Path *path, + OutputDelay *output_delay, + const StaState *sta): PathEndClkConstrained(path, nullptr), path_delay_(path_delay), check_arc_(nullptr), @@ -1793,11 +1785,11 @@ PathEndPathDelay::PathEndPathDelay(PathDelay *path_delay, } PathEndPathDelay::PathEndPathDelay(PathDelay *path_delay, - Path *path, - Path *clk_path, - TimingArc *check_arc, - Edge *check_edge, - const StaState *sta) : + Path *path, + Path *clk_path, + TimingArc *check_arc, + Edge *check_edge, + const StaState *sta) : PathEndClkConstrained(path, clk_path), path_delay_(path_delay), check_arc_(check_arc), @@ -1808,14 +1800,14 @@ PathEndPathDelay::PathEndPathDelay(PathDelay *path_delay, } PathEndPathDelay::PathEndPathDelay(PathDelay *path_delay, - Path *path, - Path *clk_path, - TimingArc *check_arc, - Edge *check_edge, - OutputDelay *output_delay, - Arrival src_clk_arrival, - Crpr crpr, - bool crpr_valid) : + Path *path, + Path *clk_path, + TimingArc *check_arc, + Edge *check_edge, + OutputDelay *output_delay, + Arrival src_clk_arrival, + Crpr crpr, + bool crpr_valid) : PathEndClkConstrained(path, clk_path, crpr, crpr_valid), path_delay_(path_delay), check_arc_(check_arc), @@ -1829,8 +1821,8 @@ PathEnd * PathEndPathDelay::copy() const { return new PathEndPathDelay(path_delay_, path_, clk_path_, - check_arc_, check_edge_, output_delay_, - src_clk_arrival_, crpr_, crpr_valid_); + check_arc_, check_edge_, output_delay_, + src_clk_arrival_, crpr_, crpr_valid_); } PathEnd::Type @@ -1891,8 +1883,10 @@ PathEndPathDelay::margin(const StaState *sta) const { if (check_arc_) { return sta->search()->deratedDelay(check_edge_->from(sta->graph()), - check_arc_, check_edge_, false, - pathAnalysisPt(sta)); + check_arc_, check_edge_, false, + path_->minMax(sta), + path_->dcalcAnalysisPtIndex(sta), + path_->sdc(sta)); } else if (output_delay_) return outputDelayMargin(output_delay_, path_, sta); @@ -1915,9 +1909,9 @@ PathEnd::clkSkew(const StaState *) // Helper shared by PathEndLatchCheck. float PathEnd::pathDelaySrcClkOffset(const Path *path, - PathDelay *path_delay, - Arrival src_clk_arrival, - const StaState *sta) + PathDelay *path_delay, + Arrival src_clk_arrival, + const StaState *sta) { float offset = 0.0; const ClockEdge *clk_edge = path->clkEdge(sta); @@ -2009,7 +2003,7 @@ PathEndPathDelay::ignoreClkLatency(const StaState *sta) const int PathEndPathDelay::exceptPathCmp(const PathEnd *path_end, - const StaState *sta) const + const StaState *sta) const { int cmp = PathEndClkConstrained::exceptPathCmp(path_end, sta); if (cmp == 0) { @@ -2019,11 +2013,11 @@ PathEndPathDelay::exceptPathCmp(const PathEnd *path_end, if (path_delay_ == path_delay2) { const TimingArc *check_arc2 = path_end2->check_arc_; if (check_arc_ == check_arc2) - return 0; + return 0; else if (check_arc_ < check_arc2) - return -1; + return -1; else - return 1; + return 1; } else if (path_delay_ < path_delay2) return -1; @@ -2043,23 +2037,23 @@ PathEndLess::PathEndLess(const StaState *sta) : bool PathEndLess::operator()(const PathEnd *path_end1, - const PathEnd *path_end2) const + const PathEnd *path_end2) const { return PathEnd::less(path_end1, path_end2, sta_); } bool PathEnd::less(const PathEnd *path_end1, - const PathEnd *path_end2, - const StaState *sta) + const PathEnd *path_end2, + const StaState *sta) { return cmp(path_end1, path_end2, sta) < 0; } int PathEnd::cmp(const PathEnd *path_end1, - const PathEnd *path_end2, - const StaState *sta) + const PathEnd *path_end2, + const StaState *sta) { int cmp = path_end1->isUnconstrained() ? -cmpArrival(path_end1, path_end2, sta) @@ -2073,9 +2067,9 @@ PathEnd::cmp(const PathEnd *path_end1, const Path *clk_path2 = path_end2->targetClkPath(); cmp = Path::cmpPinTrClk(clk_path1, clk_path2, sta); if (cmp == 0) { - cmp = Path::cmpAll(path1, path2, sta); - if (cmp == 0) - cmp = Path::cmpAll(clk_path1, clk_path2, sta); + cmp = Path::cmpAll(path1, path2, sta); + if (cmp == 0) + cmp = Path::cmpAll(clk_path1, clk_path2, sta); } } } @@ -2084,8 +2078,8 @@ PathEnd::cmp(const PathEnd *path_end1, int PathEnd::cmpSlack(const PathEnd *path_end1, - const PathEnd *path_end2, - const StaState *sta) + const PathEnd *path_end2, + const StaState *sta) { Slack slack1 = path_end1->slack(sta); Slack slack2 = path_end2->slack(sta); @@ -2114,8 +2108,8 @@ PathEnd::cmpSlack(const PathEnd *path_end1, int PathEnd::cmpArrival(const PathEnd *path_end1, - const PathEnd *path_end2, - const StaState *sta) + const PathEnd *path_end2, + const StaState *sta) { Arrival arrival1 = path_end1->dataArrivalTime(sta); Arrival arrival2 = path_end2->dataArrivalTime(sta); @@ -2130,8 +2124,8 @@ PathEnd::cmpArrival(const PathEnd *path_end1, int PathEnd::cmpNoCrpr(const PathEnd *path_end1, - const PathEnd *path_end2, - const StaState *sta) + const PathEnd *path_end2, + const StaState *sta) { int cmp = path_end1->exceptPathCmp(path_end2, sta); if (cmp == 0) { @@ -2152,7 +2146,7 @@ PathEndSlackLess::PathEndSlackLess(const StaState *sta) : bool PathEndSlackLess::operator()(const PathEnd *path_end1, - const PathEnd *path_end2) const + const PathEnd *path_end2) const { int cmp = path_end1->isUnconstrained() ? -PathEnd::cmpArrival(path_end1, path_end2, sta_) @@ -2169,7 +2163,7 @@ PathEndNoCrprLess::PathEndNoCrprLess(const StaState *sta) : bool PathEndNoCrprLess::operator()(const PathEnd *path_end1, - const PathEnd *path_end2) const + const PathEnd *path_end2) const { int cmp = path_end1->exceptPathCmp(path_end2, sta_); if (cmp == 0) { diff --git a/search/PathEnum.cc b/search/PathEnum.cc index c3a1189a..7411b7d2 100644 --- a/search/PathEnum.cc +++ b/search/PathEnum.cc @@ -31,8 +31,8 @@ #include "TimingArc.hh" #include "Network.hh" #include "Sdc.hh" +#include "Mode.hh" #include "Graph.hh" -#include "PathAnalysisPt.hh" #include "Tag.hh" #include "Search.hh" #include "Latches.hh" @@ -53,7 +53,7 @@ class Diversion { public: Diversion(PathEnd *path_end, - Path *after_div); + Path *after_div); PathEnd *pathEnd() const { return path_end_; } Path *divPath() const { return after_div_; } @@ -63,7 +63,7 @@ private: }; Diversion::Diversion(PathEnd *path_end, - Path *after_div) : + Path *after_div) : path_end_(path_end), after_div_(after_div) { @@ -87,7 +87,7 @@ DiversionGreater::DiversionGreater(const StaState *sta) : // the same delay is kept in the queue. bool DiversionGreater::operator()(Diversion *div1, - Diversion *div2) const + Diversion *div2) const { PathEnd *path_end1 = div1->pathEnd(); PathEnd *path_end2 = div2->pathEnd(); @@ -98,9 +98,8 @@ static void deleteDiversionPathEnd(Diversion *div) { PathEnd *div_end = div->pathEnd(); - Path *div_path = div_end->path(); - if (div_path->isEnum()) - delete div_path; + // This does NOT delete the div_end->path() even if it is enum. + // Search::deletePathss takes care of that. delete div_end; delete div; } @@ -108,11 +107,11 @@ deleteDiversionPathEnd(Diversion *div) //////////////////////////////////////////////////////////////// PathEnum::PathEnum(size_t group_path_count, - size_t endpoint_path_count, - bool unique_pins, - bool unique_edges, - bool cmp_slack, - const StaState *sta) : + size_t endpoint_path_count, + bool unique_pins, + bool unique_edges, + bool cmp_slack, + const StaState *sta) : StaState(sta), cmp_slack_(cmp_slack), group_path_count_(group_path_count), @@ -183,10 +182,10 @@ PathEnum::findNext() Diversion *div = div_queue_.top(); div_queue_.pop(); PathEnd *path_end = div->pathEnd(); + Path *path = path_end->path(); Vertex *vertex = path_end->vertex(this); path_counts_[vertex]++; if (debug_->check("path_enum", 2)) { - Path *path = path_end->path(); report_->reportLine("path_enum: next path %zu %s delay %s slack %s", path_counts_[vertex], path->to_string(this).c_str(), @@ -201,7 +200,6 @@ PathEnum::findNext() makeDiversions(path_end, div->divPath()); // Caller owns the path end now, so don't delete it. next_ = path_end; - //search_->saveEnumPath(path_end->path()); delete div; break; } @@ -209,7 +207,7 @@ PathEnum::findNext() // We have endpoint_path_count paths for this endpoint, // so we are done with it. debugPrint(debug_, "path_enum", 1, - "endpoint_path_count reached for %s", + "endpoint_path_count reached for %s", vertex->to_string(this).c_str()); deleteDiversionPathEnd(div); } @@ -237,44 +235,43 @@ PathEnum::reportDiversionPath(Diversion *div) //////////////////////////////////////////////////////////////// -typedef std::set> VisitedFanins; -typedef std::pair VertexEdge; +using VisitedFanins = std::set>; +using VertexEdge = std::pair; class PathEnumFaninVisitor : public PathVisitor { public: PathEnumFaninVisitor(PathEnd *path_end, - Path *before_div, - bool unique_pins, - bool unique_edges, - PathEnum *path_enum); + Path *before_div, + bool unique_pins, + bool unique_edges, + PathEnum *path_enum); virtual VertexVisitor *copy() const override; void visitFaninPathsThru(Path *before_div, - Vertex *prev_vertex, - TimingArc *prev_arc); + Vertex *prev_vertex, + TimingArc *prev_arc); virtual bool visitFromToPath(const Pin *from_pin, - Vertex *from_vertex, - const RiseFall *from_rf, - Tag *from_tag, - Path *from_path, + Vertex *from_vertex, + const RiseFall *from_rf, + Tag *from_tag, + Path *from_path, const Arrival &from_arrival, - Edge *edge, - TimingArc *arc, - ArcDelay arc_delay, - Vertex *to_vertex, - const RiseFall *to_rf, - Tag *to_tag, - Arrival &to_arrival, - const MinMax *min_max, - const PathAnalysisPt *path_ap) override; + Edge *edge, + TimingArc *arc, + ArcDelay arc_delay, + Vertex *to_vertex, + const RiseFall *to_rf, + Tag *to_tag, + Arrival &to_arrival, + const MinMax *min_max) override; private: void makeDivertedPathEnd(Path *after_div, Edge *div_edge, - TimingArc *div_arc, - // Return values. - PathEnd *&div_end, - Path *&after_div_copy); + TimingArc *div_arc, + // Return values. + PathEnd *&div_end, + Path *&after_div_copy); bool visitEdge(const Pin *from_pin, Vertex *from_vertex, Edge *edge, @@ -284,7 +281,7 @@ private: void insertUniqueEdgeDiv(Diversion *div); void reportDiversion(const Edge *edge, const TimingArc *div_arc, - Path *after_div); + Path *after_div); PathEnd *path_end_; Path *before_div_; @@ -295,7 +292,8 @@ private: Slack path_end_slack_; Tag *before_div_tag_; int before_div_rf_index_; - PathAPIndex before_div_ap_index_; + Scene *scene_; + const MinMax *min_max_; Arrival before_div_arrival_; TimingArc *prev_arc_; Vertex *prev_vertex_; @@ -305,10 +303,10 @@ private: }; PathEnumFaninVisitor::PathEnumFaninVisitor(PathEnd *path_end, - Path *before_div, - bool unique_pins, - bool unique_edges, - PathEnum *path_enum) : + Path *before_div, + bool unique_pins, + bool unique_edges, + PathEnum *path_enum) : PathVisitor(path_enum), path_end_(path_end), before_div_(before_div), @@ -319,9 +317,10 @@ PathEnumFaninVisitor::PathEnumFaninVisitor(PathEnd *path_end, path_end_slack_(path_end->slack(this)), before_div_tag_(before_div_->tag(this)), before_div_rf_index_(before_div_tag_->rfIndex()), - before_div_ap_index_(before_div_tag_->pathAPIndex()), + scene_(before_div_->scene(this)), + min_max_(before_div_->minMax(this)), before_div_arrival_(before_div_->arrival()), - crpr_active_(crprActive()) + crpr_active_(crprActive(path_end->path()->mode(this))) { } @@ -329,19 +328,20 @@ VertexVisitor * PathEnumFaninVisitor::copy() const { return new PathEnumFaninVisitor(path_end_, before_div_, unique_pins_, - unique_edges_, path_enum_); + unique_edges_, path_enum_); } void PathEnumFaninVisitor::visitFaninPathsThru(Path *before_div, - Vertex *prev_vertex, - TimingArc *prev_arc) + Vertex *prev_vertex, + TimingArc *prev_arc) { before_div_ = before_div; before_div_tag_ = before_div_->tag(this); before_div_arrival_ = before_div_->arrival(); before_div_rf_index_ = before_div_tag_->rfIndex(); - before_div_ap_index_ = before_div_tag_->pathAPIndex(); + scene_ = before_div->scene(this); + min_max_ = before_div->minMax(this); prev_arc_ = prev_arc; prev_vertex_ = prev_vertex; @@ -367,27 +367,28 @@ PathEnumFaninVisitor::visitEdge(const Pin *from_pin, TagGroup *from_tag_group = search_->tagGroup(from_vertex); if (from_tag_group) { TimingArcSet *arc_set = edge->timingArcSet(); - VertexPathIterator from_iter(from_vertex, search_); + VertexPathIterator from_iter(from_vertex, scene_, min_max_, nullptr, search_); while (from_iter.hasNext()) { Path *from_path = from_iter.next(); - // Filter paths by path ap. - PathAnalysisPt *path_ap = from_path->pathAnalysisPt(this); - if (path_ap->index() == before_div_ap_index_) { - const MinMax *min_max = path_ap->pathMinMax(); + const Mode *mode = from_path->mode(this); + const Sdc *sdc = mode->sdc(); + if (pred_->searchFrom(from_vertex, mode) + && pred_->searchThru(edge, mode) + && pred_->searchTo(to_vertex, mode) + // Fanin paths are broken by path delay internal pin startpoints. + && !sdc->isPathDelayInternalFromBreak(to_pin)) { const RiseFall *from_rf = from_path->transition(this); TimingArc *arc1, *arc2; arc_set->arcsFrom(from_rf, arc1, arc2); // Filter arcs by to edge. - if (arc1 && arc1->toEdge()->asRiseFall()->index() == before_div_rf_index_) { + if (arc1 && arc1->toEdge()->asRiseFall()->index() == before_div_rf_index_) { if (!visitArc(from_pin, from_vertex, from_rf, from_path, - edge, arc1, to_pin, to_vertex, - min_max, path_ap)) + edge, arc1, to_pin, to_vertex, min_max_, mode)) return false; } if (arc2 && arc2->toEdge()->asRiseFall()->index() == before_div_rf_index_) { if (!visitArc(from_pin, from_vertex, from_rf, from_path, - edge, arc2, to_pin, to_vertex, - min_max, path_ap)) + edge, arc2, to_pin, to_vertex, min_max_, mode)) return false; } } @@ -398,20 +399,19 @@ PathEnumFaninVisitor::visitEdge(const Pin *from_pin, bool PathEnumFaninVisitor::visitFromToPath(const Pin *, - Vertex *from_vertex, - const RiseFall *from_rf, - Tag *, - Path *from_path, + Vertex *from_vertex, + const RiseFall *from_rf, + Tag *, + Path *from_path, const Arrival &, - Edge *edge, - TimingArc *arc, - ArcDelay, - Vertex *to_vertex, - const RiseFall *to_rf, - Tag *to_tag, - Arrival & /* to_arrival */, - const MinMax * /* min_max */, - const PathAnalysisPt *path_ap) + Edge *edge, + TimingArc *arc, + ArcDelay, + Vertex *to_vertex, + const RiseFall *to_rf, + Tag *to_tag, + Arrival & /* to_arrival */, + const MinMax *) { // These paths fanin to before_div_ so we know to_vertex matches. if ((!unique_pins_ || from_vertex != prev_vertex_) @@ -420,13 +420,16 @@ PathEnumFaninVisitor::visitFromToPath(const Pin *, && Tag::matchNoCrpr(to_tag, before_div_tag_) // Ignore paths that only differ by crpr from same vertex/edge. && (!crpr_active_ - || visited_fanins_.find({from_vertex, arc}) == visited_fanins_.end())) { + || !visited_fanins_.contains({from_vertex, arc}))) { debugPrint(debug_, "path_enum", 3, "visit fanin %s -> %s %s %s", from_path->to_string(this).c_str(), to_vertex->to_string(this).c_str(), to_rf->to_string().c_str(), delayAsString(search_->deratedDelay(from_vertex, arc, edge, - false,path_ap), this)); + false, from_path->minMax(this), + from_path->dcalcAnalysisPtIndex(this), + from_path->sdc(this)), + this)); PathEnd *div_end; Path *after_div_copy; // Make the diverted path end to check slack with from_path crpr. @@ -442,8 +445,8 @@ PathEnumFaninVisitor::visitFromToPath(const Pin *, } else debugPrint(debug_, "path_enum", 3, " pruned %s %s", - edge->to_string(this).c_str(), - arc->to_string().c_str()); + edge->to_string(this).c_str(), + arc->to_string().c_str()); return true; } @@ -468,14 +471,14 @@ PathEnumFaninVisitor::insertUniqueEdgeDiv(Diversion *div) void PathEnumFaninVisitor::makeDivertedPathEnd(Path *after_div, Edge *div_edge, - TimingArc *div_arc, - // Return values. - PathEnd *&div_end, - Path *&after_div_copy) + TimingArc *div_arc, + // Return values. + PathEnd *&div_end, + Path *&after_div_copy) { Path *div_path; path_enum_->makeDivertedPath(path_end_->path(), before_div_, after_div, - div_edge, div_arc, div_path, after_div_copy); + div_edge, div_arc, div_path, after_div_copy); div_end = path_end_->copy(); div_end->setPath(div_path); } @@ -483,17 +486,16 @@ PathEnumFaninVisitor::makeDivertedPathEnd(Path *after_div, void PathEnumFaninVisitor::reportDiversion(const Edge *div_edge, const TimingArc *div_arc, - Path *after_div) -{ + Path *after_div) +{ if (debug_->check("path_enum", 3)) { Path *path = path_end_->path(); - const PathAnalysisPt *path_ap = path->pathAnalysisPt(this); Arrival path_delay = path_enum_->cmp_slack_ ? path_end_->slack(this) : path_end_->dataArrivalTime(this); Arrival div_delay = path_delay - path_enum_->divSlack(before_div_, - after_div, div_edge, - div_arc, path_ap); + after_div, div_edge, + div_arc); Path *div_prev = before_div_->prevPath(); report_->reportLine("path_enum: diversion %s %s %s -> %s", path->to_string(this).c_str(), @@ -530,8 +532,8 @@ PathEnum::pruneDiversionQueue() Diversion *div = div_queue_.top(); Vertex *vertex = div->pathEnd()->vertex(this); if (end_count < group_path_count_ - && ((unique_pins_ && path_counts[vertex] == 0) - || (!unique_pins_ && path_counts[vertex] < endpoint_path_count_))) { + && ((unique_pins_ && path_counts[vertex] == 0) + || (!unique_pins_ && path_counts[vertex] < endpoint_path_count_))) { divs.push_back(div); path_counts[vertex]++; end_count++; @@ -548,10 +550,9 @@ PathEnum::pruneDiversionQueue() Arrival PathEnum::divSlack(Path *before_div, - Path *after_div, + Path *after_div, const Edge *div_edge, - const TimingArc *div_arc, - const PathAnalysisPt *path_ap) + const TimingArc *div_arc) { Arrival before_div_arrival = before_div->arrival(); if (div_edge) { @@ -559,14 +560,17 @@ PathEnum::divSlack(Path *before_div, Arrival div_arrival; ArcDelay div_delay; Tag *q_tag; - latches_->latchOutArrival(after_div, div_arc, div_edge, path_ap, - q_tag, div_delay, div_arrival); + latches_->latchOutArrival(after_div, div_arc, div_edge, + q_tag, div_delay, div_arrival); return div_arrival - before_div_arrival; } else { + DcalcAPIndex dcalc_ap = before_div->dcalcAnalysisPtIndex(this); ArcDelay div_delay = search_->deratedDelay(div_edge->from(graph_), - div_arc, div_edge, - false, path_ap); + div_arc, div_edge, + false, before_div->minMax(this), + dcalc_ap, + before_div->sdc(this)); Arrival div_arrival = search_->clkPathArrival(after_div) + div_delay; return div_arrival - before_div_arrival; } @@ -581,13 +585,13 @@ PathEnum::divSlack(Path *before_div, // starting at "before" to the beginning of the path. void PathEnum::makeDiversions(PathEnd *path_end, - Path *before) + Path *before) { Path *path = before; Path *prev_path = path->prevPath(); TimingArc *prev_arc = path->prevArc(this); PathEnumFaninVisitor fanin_visitor(path_end, path, unique_pins_, - unique_edges_, this); + unique_edges_, this); while (prev_path) { // Fanin visitor does all the work. // While visiting the fanins the fanin_visitor finds the @@ -607,13 +611,13 @@ PathEnum::makeDiversions(PathEnd *path_end, void PathEnum::makeDivertedPath(Path *path, - Path *before_div, - Path *after_div, + Path *before_div, + Path *after_div, Edge *div_edge, - TimingArc *div_arc, - // Returned values. - Path *&div_path, - Path *&after_div_copy) + TimingArc *div_arc, + // Returned values. + Path *&div_path, + Path *&after_div_copy) { div_path = nullptr; after_div_copy = nullptr; @@ -633,6 +637,7 @@ PathEnum::makeDivertedPath(Path *path, p->prevEdge(this), p->prevArc(this), true, this); + search_->saveEnumPath(copy); if (prev_copy) prev_copy->setPrevPath(copy); copies.push_back(copy); @@ -665,7 +670,7 @@ PathEnum::makeDivertedPath(Path *path, void PathEnum::updatePathHeadDelays(PathSeq &paths, - Path *after_div) + Path *after_div) { Tag *prev_tag = after_div->tag(this); const ClkInfo *prev_clk_info = prev_tag->clkInfo(); @@ -678,46 +683,49 @@ PathEnum::updatePathHeadDelays(PathSeq &paths, Edge *edge = path->prevEdge(this); if (edge) { Arrival arrival; - PathAnalysisPt *path_ap = path->pathAnalysisPt(this); const MinMax *min_max = path->minMax(this); if (i == path_idx_max - && edge->role()->isLatchDtoQ() - && min_max == MinMax::max()) { - ArcDelay arc_delay; - Tag *q_tag; - latches_->latchOutArrival(after_div, arc, edge, path_ap, - q_tag, arc_delay, arrival); - path->setArrival(arrival); - path->setTag(q_tag); - prev_clk_info = q_tag->clkInfo(); + && edge->role()->isLatchDtoQ() + && min_max == MinMax::max()) { + ArcDelay arc_delay; + Tag *q_tag; + latches_->latchOutArrival(after_div, arc, edge, + q_tag, arc_delay, arrival); + path->setArrival(arrival); + path->setTag(q_tag); + prev_clk_info = q_tag->clkInfo(); } else { - ArcDelay arc_delay = search_->deratedDelay(edge->from(graph_), - arc, edge, false, path_ap); - arrival = prev_arrival + arc_delay; - path->setArrival(arrival); - const Tag *tag = path->tag(this); - const ClkInfo *clk_info = tag->clkInfo(); - if (crprActive() - && clk_info != prev_clk_info - // D->Q paths use the EN->Q clk info so no need to update. - && arc->role() != TimingRole::latchDtoQ()) { - // When crpr is enabled the diverion may be from another crpr clk pin, - // so update the tags to use the corresponding ClkInfo. - Tag *updated_tag = search_->findTag(path->transition(this), - path_ap, - prev_clk_info, - tag->isClock(), - tag->inputDelay(), - tag->isSegmentStart(), - tag->states(), false, nullptr); - path->setTag(updated_tag); - } - debugPrint(debug_, "path_enum", 5, "update arrival %s %s %s -> %s", - path->vertex(this)->to_string(this).c_str(), - path->tag(this)->to_string(this).c_str(), - delayAsString(path->arrival(), this), - delayAsString(arrival, this)); + ArcDelay arc_delay = search_->deratedDelay(edge->from(graph_), + arc, edge, false, + path->minMax(this), + path->dcalcAnalysisPtIndex(this), + path->sdc(this)); + arrival = prev_arrival + arc_delay; + path->setArrival(arrival); + const Tag *tag = path->tag(this); + const ClkInfo *clk_info = tag->clkInfo(); + if (crprActive(path->mode(this)) + && clk_info != prev_clk_info + // D->Q paths use the EN->Q clk info so no need to update. + && arc->role() != TimingRole::latchDtoQ()) { + // When crpr is enabled the diverion may be from another crpr clk pin, + // so update the tags to use the corresponding ClkInfo. + Tag *updated_tag = search_->findTag(path->scene(this), + path->transition(this), + path->minMax(this), + prev_clk_info, + tag->isClock(), + tag->inputDelay(), + tag->isSegmentStart(), + tag->states(), false, nullptr); + path->setTag(updated_tag); + } + debugPrint(debug_, "path_enum", 5, "update arrival %s %s %s -> %s", + path->vertex(this)->to_string(this).c_str(), + path->tag(this)->to_string(this).c_str(), + delayAsString(path->arrival(), this), + delayAsString(arrival, this)); } prev_arrival = arrival; } diff --git a/search/PathEnum.hh b/search/PathEnum.hh index 1f13f1e9..f2f68cd8 100644 --- a/search/PathEnum.hh +++ b/search/PathEnum.hh @@ -25,9 +25,10 @@ #pragma once #include +#include +#include "ContainerHelpers.hh" #include "Iterator.hh" -#include "Vector.hh" #include "StaState.hh" #include "SearchClass.hh" #include "Path.hh" @@ -38,9 +39,9 @@ class Diversion; class PathEnumFaninVisitor; class DiversionGreater; -typedef Vector DiversionSeq; -typedef std::priority_queue DiversionQueue; +using DiversionSeq = std::vector; +using DiversionQueue = std::priority_queue; class DiversionGreater { @@ -48,7 +49,7 @@ public: DiversionGreater(); DiversionGreater(const StaState *sta); bool operator()(Diversion *div1, - Diversion *div2) const; + Diversion *div2) const; private: const StaState *sta_; @@ -59,11 +60,11 @@ class PathEnum : public Iterator, StaState { public: PathEnum(size_t group_path_count, - size_t endpoint_path_count, - bool unique_pins, - bool unique_edges, - bool cmp_slack, - const StaState *sta); + size_t endpoint_path_count, + bool unique_pins, + bool unique_edges, + bool cmp_slack, + const StaState *sta); // Insert path ends that are enumerated in slack/arrival order. void insert(PathEnd *path_end); virtual ~PathEnum(); @@ -72,23 +73,22 @@ public: private: void makeDiversions(PathEnd *path_end, - Path *before); + Path *before); void insert(Diversion *div); void makeDivertedPath(Path *path, - Path *before_div, - Path *after_div, + Path *before_div, + Path *after_div, Edge *div_edge, - TimingArc *div_arc, - // Returned values. - Path *&div_path, - Path *&after_div_copy); + TimingArc *div_arc, + // Returned values. + Path *&div_path, + Path *&after_div_copy); void updatePathHeadDelays(PathSeq &path, - Path *after_div); + Path *after_div); Arrival divSlack(Path *path, - Path *after_div, + Path *after_div, const Edge *div_edge, - const TimingArc *div_arc, - const PathAnalysisPt *path_ap); + const TimingArc *div_arc); void reportDiversionPath(Diversion *div); void pruneDiversionQueue(); void findNext(); diff --git a/search/PathExpanded.cc b/search/PathExpanded.cc index 170c280a..6f77a595 100644 --- a/search/PathExpanded.cc +++ b/search/PathExpanded.cc @@ -32,6 +32,7 @@ #include "Path.hh" #include "Latches.hh" #include "Genclks.hh" +#include "Mode.hh" namespace sta { @@ -41,16 +42,16 @@ PathExpanded::PathExpanded(const StaState *sta) : } PathExpanded::PathExpanded(const Path *path, - // Expand generated clk source paths. - bool expand_genclks, - const StaState *sta) : + // Expand generated clk source paths. + bool expand_genclks, + const StaState *sta) : sta_(sta) { expand(path, expand_genclks); } PathExpanded::PathExpanded(const Path *path, - const StaState *sta) : + const StaState *sta) : sta_(sta) { expand(path, false); @@ -58,9 +59,10 @@ PathExpanded::PathExpanded(const Path *path, void PathExpanded::expand(const Path *path, - bool expand_genclks) + bool expand_genclks) { const Latches *latches = sta_->latches(); + const Mode *mode = path->mode(sta_); // Push the paths from the end into an array of Paths. const Path *p = path; const Path *last_path = nullptr; @@ -71,25 +73,25 @@ PathExpanded::expand(const Path *path, if (!found_start) { if (prev_path) { const TimingArc *prev_arc = p->prevArc(sta_); - const TimingRole *prev_role = prev_arc->role(); - if (prev_role == TimingRole::regClkToQ() - || prev_role == TimingRole::latchEnToQ()) { - start_index_ = i; - found_start = true; - } - else if (prev_role == TimingRole::latchDtoQ()) { - const Edge *prev_edge = p->prevEdge(sta_); - if (prev_edge && latches->isLatchDtoQ(prev_edge)) { - start_index_ = i; - found_start = true; + const TimingRole *prev_role = prev_arc->role(); + if (prev_role == TimingRole::regClkToQ() + || prev_role == TimingRole::latchEnToQ()) { + start_index_ = i; + found_start = true; + } + else if (prev_role->isLatchDtoQ()) { + const Edge *prev_edge = p->prevEdge(sta_); + if (prev_edge && latches->isLatchDtoQ(prev_edge, mode)) { + start_index_ = i; + found_start = true; - paths_.push_back(p); - // Push latch D path. - paths_.push_back(prev_path); - // This breaks latch loop paths. - break; - } - } + paths_.push_back(p); + // Push latch D path. + paths_.push_back(prev_path); + // This breaks latch loop paths. + break; + } + } } } paths_.push_back(p); @@ -110,20 +112,21 @@ PathExpanded::expandGenclk(const Path *clk_path) if (clk_path) { const Clock *src_clk = clk_path->clock(sta_); if (src_clk && src_clk->isGenerated()) { - const Path *src_path = sta_->search()->genclks()->srcPath(clk_path); + const Mode *mode = clk_path->mode(sta_); + const Path *src_path = mode->genclks()->srcPath(clk_path); if (src_path) { - // The head of the genclk src path is already in paths_, - // so skip past it. - Path *prev_path = src_path->prevPath(); - Path *p = prev_path; - Path *last_path = nullptr; - while (p) { - prev_path = p->prevPath(); - paths_.push_back(p); - last_path = p; - p = prev_path; - } - expandGenclk(last_path); + // The head of the genclk src path is already in paths_, + // so skip past it. + Path *prev_path = src_path->prevPath(); + Path *p = prev_path; + Path *last_path = nullptr; + while (p) { + prev_path = p->prevPath(); + paths_.push_back(p); + last_path = p; + p = prev_path; + } + expandGenclk(last_path); } } } @@ -188,14 +191,15 @@ PathExpanded::clkPath() const const TimingArc *prev_arc = startPrevArc(); if (start && prev_arc) { const TimingRole *role = prev_arc->role(); - if (role == TimingRole::latchDtoQ()) { + if (role->isLatchDtoQ()) { Edge *prev_edge = start->prevEdge(sta_); - if (prev_edge && latches->isLatchDtoQ(prev_edge)) { - return latches->latchEnablePath(start, prev_edge); + const Mode *mode = start->mode(sta_); + if (prev_edge && latches->isLatchDtoQ(prev_edge, mode)) { + return latches->latchEnablePath(start, prev_edge); } } else if (role == TimingRole::regClkToQ() - || role == TimingRole::latchEnToQ()) { + || role == TimingRole::latchEnToQ()) { const Path *start_prev = startPrevPath(); if (start_prev) return start_prev; @@ -208,9 +212,9 @@ PathExpanded::clkPath() const void PathExpanded::latchPaths(// Return values. - const Path *&d_path, - const Path *&q_path, - Edge *&d_q_edge) const + const Path *&d_path, + const Path *&q_path, + Edge *&d_q_edge) const { d_path = nullptr; q_path = nullptr; @@ -221,9 +225,10 @@ PathExpanded::latchPaths(// Return values. && prev_arc && prev_arc->role() == TimingRole::latchDtoQ()) { Edge *prev_edge = start->prevEdge(sta_); + const Mode *mode = start->mode(sta_); // This breaks latch loop paths. if (prev_edge - && sta_->latches()->isLatchDtoQ(prev_edge)) { + && sta_->latches()->isLatchDtoQ(prev_edge, mode)) { d_path = startPrevPath(); q_path = start; d_q_edge = prev_edge; diff --git a/search/PathGroup.cc b/search/PathGroup.cc index 3ce7443a..6ac127f0 100644 --- a/search/PathGroup.cc +++ b/search/PathGroup.cc @@ -26,7 +26,11 @@ #include #include +#include +#include +#include "ContainerHelpers.hh" +#include "StringUtil.hh" #include "Stats.hh" #include "Debug.hh" #include "Mutex.hh" @@ -35,11 +39,11 @@ #include "DispatchQueue.hh" #include "ExceptionPath.hh" #include "Sdc.hh" +#include "Mode.hh" #include "Graph.hh" #include "PathEnd.hh" -#include "PathAnalysisPt.hh" #include "Tag.hh" -#include "Corner.hh" +#include "Scene.hh" #include "Search.hh" #include "VisitPathEnds.hh" #include "PathEnum.hh" @@ -50,43 +54,43 @@ size_t PathGroup::group_path_count_max = std::numeric_limits::max(); PathGroup * PathGroup::makePathGroupSlack(const char *name, - int group_path_count, - int endpoint_path_count, - bool unique_pins, - bool unique_edges, - float slack_min, - float slack_max, - const StaState *sta) + int group_path_count, + int endpoint_path_count, + bool unique_pins, + bool unique_edges, + float slack_min, + float slack_max, + const StaState *sta) { return new PathGroup(name, group_path_count, endpoint_path_count, - unique_pins, unique_edges, slack_min, slack_max, - true, MinMax::min(), sta); + unique_pins, unique_edges, slack_min, slack_max, + true, MinMax::min(), sta); } PathGroup * PathGroup::makePathGroupArrival(const char *name, - int group_path_count, - int endpoint_path_count, - bool unique_pins, - bool unique_edges, - const MinMax *min_max, - const StaState *sta) + int group_path_count, + int endpoint_path_count, + bool unique_pins, + bool unique_edges, + const MinMax *min_max, + const StaState *sta) { return new PathGroup(name, group_path_count, endpoint_path_count, - unique_pins, unique_edges, 0.0, 0.0, - false, min_max, sta); + unique_pins, unique_edges, 0.0, 0.0, + false, min_max, sta); } PathGroup::PathGroup(const char *name, - size_t group_path_count, - size_t endpoint_path_count, - bool unique_pins, - bool unique_edges, - float slack_min, - float slack_max, - bool cmp_slack, - const MinMax *min_max, - const StaState *sta) : + size_t group_path_count, + size_t endpoint_path_count, + bool unique_pins, + bool unique_edges, + float slack_min, + float slack_max, + bool cmp_slack, + const MinMax *min_max, + const StaState *sta) : name_(name), group_path_count_(group_path_count), endpoint_path_count_(endpoint_path_count), @@ -103,7 +107,7 @@ PathGroup::PathGroup(const char *name, PathGroup::~PathGroup() { - path_ends_.deleteContents(); + deleteContents(path_ends_); } bool @@ -119,13 +123,13 @@ PathGroup::saveable(PathEnd *path_end) // without crpr first because it is expensive to find. Slack slack = path_end->slackNoCrpr(sta_); if (!delayIsInitValue(slack, min_max_) - && delayLessEqual(slack, threshold, sta_) - && delayLessEqual(slack, slack_max_, sta_)) { + && delayLessEqual(slack, threshold, sta_) + && delayLessEqual(slack, slack_max_, sta_)) { // Now check with crpr. slack = path_end->slack(sta_); return delayLessEqual(slack, threshold, sta_) - && delayLessEqual(slack, slack_max_, sta_) - && delayGreaterEqual(slack, slack_min_, sta_); + && delayLessEqual(slack, slack_max_, sta_) + && delayGreaterEqual(slack, slack_min_, sta_); } } else { @@ -148,11 +152,11 @@ PathGroup::enumMinSlackUnderMin(PathEnd *path_end) && endpoint_path_count_ > 1 && slack_min_ > -INF) { const Path *path = path_end->path(); - PathAnalysisPt *other_ap = path->pathAnalysisPt(sta_)->tgtClkAnalysisPt(); const Tag *tag = path->tag(sta_); VertexPathIterator other_iter(path->vertex(sta_), - path->transition(sta_), - other_ap, sta_); + path->scene(sta_), + path->tgtClkMinMax(sta_), + path->transition(sta_), sta_); while (other_iter.hasNext()) { Path *other = other_iter.next(); if (Tag::matchCrpr(other->tag(sta_), tag)) { @@ -192,7 +196,7 @@ PathGroup::prune() // Squish up to endpoint_path_count path ends per vertex // up to the front of path_ends_. if (end_count < group_path_count_ - && path_counts[vertex] < endpoint_path_count_) { + && path_counts[vertex] < endpoint_path_count_) { path_ends_[end_count++] = path_end; path_counts[vertex]++; } @@ -218,13 +222,6 @@ PathGroup::pushEnds(PathEndSeq &path_ends) path_ends.push_back(path_end); } -PathGroupIterator * -PathGroup::iterator() -{ - ensureSortedMaxPaths(); - return new PathGroupIterator(path_ends_); -} - void PathGroup::ensureSortedMaxPaths() { @@ -256,21 +253,22 @@ const char *PathGroups::async_group_name_ = "asynchronous"; const char *PathGroups::unconstrained_group_name_ = "unconstrained"; PathGroups::PathGroups(int group_path_count, - int endpoint_path_count, - bool unique_pins, - bool unique_edges, - float slack_min, - float slack_max, - PathGroupNameSet *group_names, - bool setup, - bool hold, - bool recovery, - bool removal, - bool clk_gating_setup, - bool clk_gating_hold, - bool unconstrained, - const StaState *sta) : - StaState(sta), + int endpoint_path_count, + bool unique_pins, + bool unique_edges, + float slack_min, + float slack_max, + StdStringSeq &group_names, + bool setup, + bool hold, + bool recovery, + bool removal, + bool clk_gating_setup, + bool clk_gating_hold, + bool unconstrained, + const Mode *mode) : + StaState(mode), + mode_(mode), group_path_count_(group_path_count), endpoint_path_count_(endpoint_path_count), unique_pins_(unique_pins), @@ -278,56 +276,61 @@ PathGroups::PathGroups(int group_path_count, slack_min_(slack_min), slack_max_(slack_max) { + StdStringSet groups; + for (std::string &group_name : group_names) + groups.insert(group_name); + makeGroups(group_path_count, endpoint_path_count, unique_pins, unique_edges, - slack_min, slack_max, group_names, - setup, recovery, clk_gating_setup, unconstrained, - MinMax::max()); + slack_min, slack_max, groups, + setup, recovery, clk_gating_setup, unconstrained, + MinMax::max()); makeGroups(group_path_count, endpoint_path_count, unique_pins, unique_edges, - slack_min, slack_max, group_names, - hold, removal, clk_gating_hold, unconstrained, - MinMax::min()); + slack_min, slack_max, groups, + hold, removal, clk_gating_hold, unconstrained, + MinMax::min()); } void PathGroups::makeGroups(int group_path_count, - int endpoint_path_count, - bool unique_pins, - bool unique_edges, - float slack_min, - float slack_max, - PathGroupNameSet *group_names, - bool setup_hold, - bool async, - bool gated_clk, - bool unconstrained, - const MinMax *min_max) + int endpoint_path_count, + bool unique_pins, + bool unique_edges, + float slack_min, + float slack_max, + StdStringSet &group_names, + bool setup_hold, + bool async, + bool gated_clk, + bool unconstrained, + const MinMax *min_max) { int mm_index = min_max->index(); if (setup_hold) { - for (const auto [name, group] : sdc_->groupPaths()) { + const Sdc *sdc = mode_->sdc(); + for (const auto& [name, group] : sdc->groupPaths()) { if (reportGroup(name, group_names)) { - PathGroup *group = PathGroup::makePathGroupSlack(name, - group_path_count, - endpoint_path_count, - unique_pins, - unique_edges, - slack_min, slack_max, - this); - named_map_[mm_index][name] = group; + PathGroup *group = PathGroup::makePathGroupSlack(name, + group_path_count, + endpoint_path_count, + unique_pins, + unique_edges, + slack_min, slack_max, + this); + named_map_[mm_index][name] = group; } } - for (auto clk : sdc_->clks()) { + for (Clock *clk : sdc->clocks()) { const char *clk_name = clk->name(); if (reportGroup(clk_name, group_names)) { - PathGroup *group = PathGroup::makePathGroupSlack(clk_name, - group_path_count, - endpoint_path_count, - unique_pins, - unique_edges, - slack_min, slack_max, - this); - clk_map_[mm_index][clk] = group; + PathGroup *group = PathGroup::makePathGroupSlack(clk_name, + group_path_count, + endpoint_path_count, + unique_pins, + unique_edges, + slack_min, slack_max, + this); + clk_map_[mm_index][clk] = group; } } } @@ -335,36 +338,36 @@ PathGroups::makeGroups(int group_path_count, if (setup_hold && reportGroup(path_delay_group_name_, group_names)) path_delay_[mm_index] = PathGroup::makePathGroupSlack(path_delay_group_name_, - group_path_count, - endpoint_path_count, - unique_pins, - unique_edges, - slack_min, slack_max, - this); + group_path_count, + endpoint_path_count, + unique_pins, + unique_edges, + slack_min, slack_max, + this); else path_delay_[mm_index] = nullptr; if (gated_clk && reportGroup(gated_clk_group_name_, group_names)) gated_clk_[mm_index] = PathGroup::makePathGroupSlack(gated_clk_group_name_, - group_path_count, - endpoint_path_count, - unique_pins, - unique_edges, - slack_min, slack_max, - this); + group_path_count, + endpoint_path_count, + unique_pins, + unique_edges, + slack_min, slack_max, + this); else gated_clk_[mm_index] = nullptr; if (async && reportGroup(async_group_name_, group_names)) async_[mm_index] = PathGroup::makePathGroupSlack(async_group_name_, - group_path_count, - endpoint_path_count, - unique_pins, - unique_edges, - slack_min, slack_max, - this); + group_path_count, + endpoint_path_count, + unique_pins, + unique_edges, + slack_min, slack_max, + this); else async_[mm_index] = nullptr; @@ -372,8 +375,8 @@ PathGroups::makeGroups(int group_path_count, && reportGroup(unconstrained_group_name_, group_names)) unconstrained_[mm_index] = PathGroup::makePathGroupArrival(unconstrained_group_name_, - group_path_count, endpoint_path_count, - unique_pins, unique_edges, min_max, this); + group_path_count, endpoint_path_count, + unique_pins, unique_edges, min_max, this); else unconstrained_[mm_index] = nullptr; } @@ -381,8 +384,8 @@ PathGroups::makeGroups(int group_path_count, PathGroups::~PathGroups() { for (auto mm_index : MinMax::rangeIndex()) { - named_map_[mm_index].deleteContents(); - clk_map_[mm_index].deleteContents(); + deleteContents(named_map_[mm_index]); + deleteContents(clk_map_[mm_index]); delete path_delay_[mm_index]; delete gated_clk_[mm_index]; delete async_[mm_index]; @@ -392,25 +395,32 @@ PathGroups::~PathGroups() PathGroup * PathGroups::findPathGroup(const char *name, - const MinMax *min_max) const + const MinMax *min_max) const { - return named_map_[min_max->index()].findKey(name); + auto itr = named_map_[min_max->index()].find(name); + if (itr != named_map_[min_max->index()].end()) + return itr->second; + else + return nullptr; } PathGroup * PathGroups::findPathGroup(const Clock *clock, - const MinMax *min_max) const + const MinMax *min_max) const { - return clk_map_[min_max->index()].findKey(clock); + auto itr = clk_map_[min_max->index()].find(clock); + if (itr != clk_map_[min_max->index()].end()) + return itr->second; + else + return nullptr; } bool PathGroups::reportGroup(const char *group_name, - PathGroupNameSet *group_names) const + StdStringSet &group_names) const { - return group_names == nullptr - || group_names->empty() - || group_names->hasKey(group_name); + return group_names.empty() + || group_names.contains(group_name); } PathGroupSeq @@ -427,12 +437,12 @@ PathGroups::pathGroups(const PathEnd *path_end) const else if (!group_paths.empty()) { for (ExceptionPath *group_path : group_paths) { if (group_path->isDefault()) - path_groups.push_back(path_delay_[mm_index]); + path_groups.push_back(path_delay_[mm_index]); else { - const char *group_name = group_path->name(); - PathGroup *group = findPathGroup(group_name, min_max); - if (group) - path_groups.push_back(group); + const char *group_name = group_path->name(); + PathGroup *group = findPathGroup(group_name, min_max); + if (group) + path_groups.push_back(group); } } } @@ -440,7 +450,7 @@ PathGroups::pathGroups(const PathEnd *path_end) const const TimingRole *check_role = path_end->checkRole(this); const Clock *tgt_clk = path_end->targetClk(this); if (check_role == TimingRole::removal() - || check_role == TimingRole::recovery()) + || check_role == TimingRole::recovery()) path_group = async_[mm_index]; else path_group = findPathGroup(tgt_clk, min_max); @@ -456,7 +466,7 @@ PathGroups::pathGroups(const PathEnd *path_end) const PathDelay *path_delay = path_end->pathDelay(); const Clock *tgt_clk = path_end->targetClk(this); if (tgt_clk - && !path_delay->ignoreClkLatency()) + && !path_delay->ignoreClkLatency()) path_group = findPathGroup(tgt_clk, min_max); else path_group = path_delay_[mm_index]; @@ -469,7 +479,7 @@ PathGroups::pathGroups(const PathEnd *path_end) const // Mirrors PathGroups::pathGroup. StdStringSeq PathGroups::pathGroupNames(const PathEnd *path_end, - const StaState *sta) + const StaState *sta) { StdStringSeq group_names; const char *group_name = nullptr; @@ -481,22 +491,22 @@ PathGroups::pathGroupNames(const PathEnd *path_end, // GroupPaths have precedence. for (ExceptionPath *group_path : group_paths) { if (group_path->isDefault()) - group_names.push_back(path_delay_group_name_); + group_names.push_back(path_delay_group_name_); else - group_names.push_back(group_path->name()); + group_names.push_back(group_path->name()); } } else if (path_end->isCheck() || path_end->isLatchCheck()) { const TimingRole *check_role = path_end->checkRole(sta); const Clock *tgt_clk = path_end->targetClk(sta); if (check_role == TimingRole::removal() - || check_role == TimingRole::recovery()) + || check_role == TimingRole::recovery()) group_name = async_group_name_; else group_name = tgt_clk->name(); } else if (path_end->isOutputDelay() - || path_end->isDataCheck()) { + || path_end->isDataCheck()) { const Clock *tgt_clk = path_end->targetClk(sta); if (tgt_clk) group_name = tgt_clk->name(); @@ -509,7 +519,7 @@ PathGroups::pathGroupNames(const PathEnd *path_end, PathDelay *path_delay = path_end->pathDelay(); const Clock *tgt_clk = path_end->targetClk(sta); if (tgt_clk - && !path_delay->ignoreClkLatency()) + && !path_delay->ignoreClkLatency()) group_name = tgt_clk->name(); else group_name = path_delay_group_name_; @@ -519,16 +529,30 @@ PathGroups::pathGroupNames(const PathEnd *path_end, return group_names; } -void -PathGroups::pushGroupPathEnds(PathEndSeq &path_ends) +GroupPath * +PathGroups::groupPathTo(const PathEnd *path_end, + const StaState *sta) { - for (auto min_max : MinMax::range()) { + const Path *path = path_end->path(); + const Pin *pin = path->pin(sta); + ExceptionPath *exception = + sta->search()->exceptionTo(ExceptionPathType::group_path, path, + pin, path->transition(sta), + path_end->targetClkEdge(sta), + path->minMax(sta), false, false, + path->sdc(sta)); + return dynamic_cast(exception); +} + +void +PathGroups::pushEnds(PathEndSeq &path_ends) +{ + for (const MinMax *min_max : MinMax::range()) { int mm_index = min_max->index(); - for (auto name_group : sdc_->groupPaths()) { - const char *name = name_group.first; - PathGroup *path_group = findPathGroup(name, min_max); + for (std::string &group_name : pathGroupNames()) { + PathGroup *path_group = findPathGroup(group_name.c_str(), min_max); if (path_group) - path_group->pushEnds(path_ends); + path_group->pushEnds(path_ends); } if (async_[mm_index]) @@ -540,61 +564,72 @@ PathGroups::pushGroupPathEnds(PathEndSeq &path_ends) if (path_delay_[mm_index]) path_delay_[mm_index]->pushEnds(path_ends); - ClockSeq clks; - sdc_->sortedClocks(clks); - ClockSeq::Iterator clk_iter(clks); - while (clk_iter.hasNext()) { - Clock *clk = clk_iter.next(); + const Sdc *sdc = mode_->sdc(); + ClockSeq clks = sdc->sortedClocks(); + for (Clock *clk : clks) { PathGroup *path_group = findPathGroup(clk, min_max); if (path_group) - path_group->pushEnds(path_ends); + path_group->pushEnds(path_ends); } } } +StdStringSeq +PathGroups::pathGroupNames() +{ + std::set group_names1; + const Sdc *sdc = mode_->sdc(); + for (const auto& [name, group] : sdc->groupPaths()) + group_names1.insert(name); + StdStringSeq group_names2; + for (const std::string &name : group_names1) + group_names2.push_back(name); + sort(group_names2); + return group_names2; +} + + void PathGroups::pushUnconstrainedPathEnds(PathEndSeq &path_ends, - const MinMaxAll *min_max) + const MinMaxAll *min_max) { - Set groups; - for (auto path_ap : corners_->pathAnalysisPts()) { - const MinMax *path_min_max = path_ap->pathMinMax(); - if (min_max->matches(path_min_max)) { - int mm_index = path_min_max->index(); - PathGroup *group = unconstrained_[mm_index]; - if (group - // For multiple corner path APs use the same group. - // Only report it once. - && !groups.findKey(group)) { - group->pushEnds(path_ends); - groups.insert(group); - } + std::set groups; + for (const MinMax *mm : min_max->range()) { + int mm_index = mm->index(); + PathGroup *group = unconstrained_[mm_index]; + if (group + // For multiple scene path APs use the same group. + // Only report it once. + && !groups.contains(group)) { + group->pushEnds(path_ends); + groups.insert(group); } } } //////////////////////////////////////////////////////////////// -typedef Map PathGroupEndMap; -typedef Map PathGroupEndsMap; -typedef Set PathEndNoCrprSet; +using PathGroupEndMap = std::map; +using PathGroupEndsMap = std::map; +using PathEndNoCrprSet = std::set; static bool exceptionToEmpty(ExceptionTo *to); -PathEndSeq +void PathGroups::makePathEnds(ExceptionTo *to, - bool unconstrained_paths, - const Corner *corner, - const MinMaxAll *min_max, - bool sort_by_slack) + const SceneSeq &scenes, + const MinMaxAll *min_max, + bool sort_by_slack, + bool unconstrained_paths, + // Return value. + PathEndSeq &path_ends) { Stats stats(debug_, report_); makeGroupPathEnds(to, group_path_count_, endpoint_path_count_, - unique_pins_, unique_edges_, corner, min_max); + unique_pins_, unique_edges_, scenes, min_max); - PathEndSeq path_ends; - pushGroupPathEnds(path_ends); + pushEnds(path_ends); if (sort_by_slack) { sort(path_ends, PathEndLess(this)); } @@ -605,7 +640,6 @@ PathGroups::makePathEnds(ExceptionTo *to, pushUnconstrainedPathEnds(path_ends, min_max); stats.report("Make path ends"); - return path_ends; } //////////////////////////////////////////////////////////////// @@ -623,7 +657,7 @@ public: private: void visitPathEnd(PathEnd *path_end, - PathGroup *group); + PathGroup *group); PathGroups *path_groups_; PathGroupEndMap ends_; @@ -651,15 +685,15 @@ MakePathEnds1::visit(PathEnd *path_end) void MakePathEnds1::visitPathEnd(PathEnd *path_end, - PathGroup *group) + PathGroup *group) { if (group->saveable(path_end)) { // Only keep the path end with the smallest slack/latest arrival. - PathEnd *worst_end = ends_.findKey(group); + PathEnd *worst_end = findKey(ends_, group); if (worst_end) { if (cmp_(path_end, worst_end)) { - ends_[group] = path_end->copy(); - delete worst_end; + ends_[group] = path_end->copy(); + delete worst_end; } } else @@ -671,11 +705,7 @@ MakePathEnds1::visitPathEnd(PathEnd *path_end, void MakePathEnds1::vertexEnd(Vertex *) { - PathGroupEndMap::Iterator group_iter(ends_); - while (group_iter.hasNext()) { - PathGroup *group; - PathEnd *end; - group_iter.next(group, end); + for (auto [group, end] : ends_) { // visitPathEnd already confirmed slack is saveable. if (end) { group->insert(end); @@ -703,7 +733,7 @@ public: private: void visitPathEnd(PathEnd *path_end, - PathGroup *group); + PathGroup *group); int endpoint_path_count_; PathGroups *path_groups_; @@ -714,7 +744,7 @@ private: }; MakePathEndsAll::MakePathEndsAll(int endpoint_path_count, - PathGroups *path_groups) : + PathGroups *path_groups) : endpoint_path_count_(endpoint_path_count), path_groups_(path_groups), sta_(path_groups), @@ -732,13 +762,7 @@ MakePathEndsAll::copy() const MakePathEndsAll::~MakePathEndsAll() { - PathGroupEndsMap::Iterator group_iter(ends_); - while (group_iter.hasNext()) { - PathGroup *group; - PathEndSeq *ends; - group_iter.next(group, ends); - delete ends; - } + deleteContents(ends_); } void @@ -750,9 +774,9 @@ MakePathEndsAll::visit(PathEnd *path_end) void MakePathEndsAll::visitPathEnd(PathEnd *path_end, - PathGroup *group) + PathGroup *group) { - PathEndSeq *ends = ends_.findKey(group); + PathEndSeq *ends = findKey(ends_, group); if (ends == nullptr) { ends = new PathEndSeq; ends_[group] = ends; @@ -764,50 +788,41 @@ void MakePathEndsAll::vertexEnd(Vertex *) { Debug *debug = sta_->debug(); - PathGroupEndsMap::Iterator group_iter(ends_); - while (group_iter.hasNext()) { - PathGroup *group; - PathEndSeq *ends; - group_iter.next(group, ends); + for (auto [group, ends] : ends_) { if (ends) { sort(ends, slack_cmp_); PathEndNoCrprSet unique_ends(path_no_crpr_cmp_); - PathEndSeq::Iterator end_iter(ends); + auto end_iter = ends->begin(); int n = 0; - while (end_iter.hasNext() - && n < endpoint_path_count_) { - PathEnd *path_end = end_iter.next(); - // Only save the worst path end for each crpr tag. - // PathEnum will peel the others. - if (!unique_ends.hasKey(path_end)) { - debugPrint(debug, "path_group", 2, "insert %s %s %s %d", + while (end_iter != ends->end() + && n < endpoint_path_count_) { + PathEnd *path_end = *end_iter++; + // Only save the worst path end for each crpr tag. + // PathEnum will peel the others. + if (!unique_ends.contains(path_end)) { + debugPrint(debug, "path_group", 2, "insert %s %s %s %d", path_end->vertex(sta_)->to_string(sta_).c_str(), path_end->typeName(), path_end->transition(sta_)->to_string().c_str(), path_end->path()->tag(sta_)->index()); - // Give the group a copy of the path end because - // it may delete it during pruning. - if (group->saveable(path_end) + // Give the group a copy of the path end because + // it may delete it during pruning. + if (group->saveable(path_end) || group->enumMinSlackUnderMin(path_end)) { - group->insert(path_end->copy()); - unique_ends.insert(path_end); - n++; - } - } - else - debugPrint(debug, "path_group", 3, "prune %s %s %s %d", + group->insert(path_end->copy()); + unique_ends.insert(path_end); + n++; + } + } + else + debugPrint(debug, "path_group", 3, "prune %s %s %s %d", path_end->vertex(sta_)->to_string(sta_).c_str(), path_end->typeName(), path_end->transition(sta_)->to_string().c_str(), path_end->path()->tag(sta_)->index()); } // Clear ends for next vertex. - PathEndSeq::Iterator end_iter2(ends); - while (end_iter2.hasNext()) { - PathEnd *path_end = end_iter2.next(); - delete path_end; - } - ends->clear(); + deleteContents(*ends); } } } @@ -816,78 +831,76 @@ MakePathEndsAll::vertexEnd(Vertex *) void PathGroups::makeGroupPathEnds(ExceptionTo *to, - int group_path_count, - int endpoint_path_count, - bool unique_pins, - bool unique_edges, - const Corner *corner, - const MinMaxAll *min_max) + int group_path_count, + int endpoint_path_count, + bool unique_pins, + bool unique_edges, + const SceneSeq &scenes, + const MinMaxAll *min_max) { if (endpoint_path_count == 1) { MakePathEnds1 make_path_ends(this); - makeGroupPathEnds(to, corner, min_max, &make_path_ends); + makeGroupPathEnds(to, scenes, min_max, &make_path_ends); } else { MakePathEndsAll make_path_ends(endpoint_path_count, this); - makeGroupPathEnds(to, corner, min_max, &make_path_ends); + makeGroupPathEnds(to, scenes, min_max, &make_path_ends); - for (auto path_min_max : MinMax::range()) { + for (const MinMax *path_min_max : MinMax::range()) { int mm_index = path_min_max->index(); - for (auto name_group : sdc_->groupPaths()) { - const char *name = name_group.first; - PathGroup *group = findPathGroup(name, path_min_max); + for (const Mode *mode : Scene::modes(scenes)) { + const Sdc *sdc = mode->sdc(); + for (const auto& [name, groups] : sdc->groupPaths()) { + PathGroup *group = findPathGroup(name, path_min_max); + if (group) + enumPathEnds(group, group_path_count, endpoint_path_count, + unique_pins, unique_edges, true); + } + } + const Sdc *sdc = mode_->sdc(); + for (const Clock *clk : sdc->clocks()) { + PathGroup *group = findPathGroup(clk, path_min_max); if (group) enumPathEnds(group, group_path_count, endpoint_path_count, - unique_pins, unique_edges, true); + unique_pins, unique_edges, true); } - - for (auto clk : sdc_->clks()) { - PathGroup *group = findPathGroup(clk, path_min_max); - if (group) - enumPathEnds(group, group_path_count, endpoint_path_count, - unique_pins, unique_edges, true); - } - PathGroup *group = unconstrained_[mm_index]; if (group) - enumPathEnds(group, group_path_count, endpoint_path_count, - unique_pins, unique_edges, false); + enumPathEnds(group, group_path_count, endpoint_path_count, + unique_pins, unique_edges, false); group = path_delay_[mm_index]; if (group) - enumPathEnds(group, group_path_count, endpoint_path_count, - unique_pins, unique_edges, true); + enumPathEnds(group, group_path_count, endpoint_path_count, + unique_pins, unique_edges, true); group = gated_clk_[mm_index]; if (group) - enumPathEnds(group, group_path_count, endpoint_path_count, - unique_pins, unique_edges, true); + enumPathEnds(group, group_path_count, endpoint_path_count, + unique_pins, unique_edges, true); group = async_[mm_index]; if (group) - enumPathEnds(group, group_path_count, endpoint_path_count, - unique_pins, unique_edges, true); + enumPathEnds(group, group_path_count, endpoint_path_count, + unique_pins, unique_edges, true); } } } void PathGroups::enumPathEnds(PathGroup *group, - int group_path_count, - int endpoint_path_count, - bool unique_pins, - bool unique_edges, - bool cmp_slack) + int group_path_count, + int endpoint_path_count, + bool unique_pins, + bool unique_edges, + bool cmp_slack) { // Insert the worst max_path path ends in the group into a path // enumerator. PathEnum path_enum(group_path_count, endpoint_path_count, - unique_pins, unique_edges, cmp_slack, this); - PathGroupIterator *end_iter = group->iterator(); - while (end_iter->hasNext()) { - PathEnd *end = end_iter->next(); + unique_pins, unique_edges, cmp_slack, this); + for (PathEnd *end : group->pathEnds()) { if (group->saveable(end) || group->enumMinSlackUnderMin(end)) path_enum.insert(end); } - delete end_iter; group->clear(); // Parallel path enumeratation to find the endpoint_path_count/max path ends. @@ -902,32 +915,28 @@ PathGroups::enumPathEnds(PathGroup *group, void PathGroups::makeGroupPathEnds(ExceptionTo *to, - const Corner *corner, - const MinMaxAll *min_max, - PathEndVisitor *visitor) + const SceneSeq &scenes, + const MinMaxAll *min_max, + PathEndVisitor *visitor) { - Network *network = this->network(); - Graph *graph = this->graph(); - Search *search = this->search(); if (exceptionToEmpty(to)) - makeGroupPathEnds(search->endpoints(), corner, min_max, visitor); + makeGroupPathEnds(search_->endpoints(), scenes, min_max, visitor); else { // Only visit -to filter pins. - VertexSet endpoints(graph_); - PinSet pins = to->allPins(network); - PinSet::Iterator pin_iter(pins); - while (pin_iter.hasNext()) { - const Pin *pin = pin_iter.next(); + ModeSeq modes = Scene::modes(scenes); + VertexSet endpoints = makeVertexSet(this); + PinSet pins = to->allPins(network_); + for (const Pin *pin : pins) { Vertex *vertex, *bidirect_drvr_vertex; - graph->pinVertices(pin, vertex, bidirect_drvr_vertex); + graph_->pinVertices(pin, vertex, bidirect_drvr_vertex); if (vertex - && search->isEndpoint(vertex)) - endpoints.insert(vertex); + && search_->isEndpoint(vertex, modes)) + endpoints.insert(vertex); if (bidirect_drvr_vertex - && search->isEndpoint(bidirect_drvr_vertex)) - endpoints.insert(bidirect_drvr_vertex); + && search_->isEndpoint(bidirect_drvr_vertex, modes)) + endpoints.insert(bidirect_drvr_vertex); } - makeGroupPathEnds(&endpoints, corner, min_max, visitor); + makeGroupPathEnds(endpoints, scenes, min_max, visitor); } } @@ -936,7 +945,7 @@ exceptionToEmpty(ExceptionTo *to) { return to == nullptr || (to->pins() == nullptr - && to->instances() == nullptr); + && to->instances() == nullptr); } //////////////////////////////////////////////////////////////// @@ -945,9 +954,9 @@ class MakeEndpointPathEnds : public VertexVisitor { public: MakeEndpointPathEnds(PathEndVisitor *path_end_visitor, - const Corner *corner, - const MinMaxAll *min_max, - const StaState *sta); + const SceneSet &scenes, + const MinMaxAll *min_max, + const StaState *sta); MakeEndpointPathEnds(const MakeEndpointPathEnds &make_path_ends); ~MakeEndpointPathEnds(); virtual VertexVisitor *copy() const; @@ -956,18 +965,18 @@ public: private: VisitPathEnds visit_path_ends_; PathEndVisitor *path_end_visitor_; - const Corner *corner_; + const SceneSet scenes_; const MinMaxAll *min_max_; const StaState *sta_; }; MakeEndpointPathEnds::MakeEndpointPathEnds(PathEndVisitor *path_end_visitor, - const Corner *corner, - const MinMaxAll *min_max, - const StaState *sta) : + const SceneSet &scenes, + const MinMaxAll *min_max, + const StaState *sta) : visit_path_ends_(sta), path_end_visitor_(path_end_visitor->copy()), - corner_(corner), + scenes_(scenes), min_max_(min_max), sta_(sta) { @@ -976,7 +985,7 @@ MakeEndpointPathEnds::MakeEndpointPathEnds(PathEndVisitor *path_end_visitor, MakeEndpointPathEnds::MakeEndpointPathEnds(const MakeEndpointPathEnds &make_path_ends) : visit_path_ends_(make_path_ends.sta_), path_end_visitor_(make_path_ends.path_end_visitor_->copy()), - corner_(make_path_ends.corner_), + scenes_(make_path_ends.scenes_), min_max_(make_path_ends.min_max_), sta_(make_path_ends.sta_) { @@ -990,33 +999,36 @@ MakeEndpointPathEnds::~MakeEndpointPathEnds() VertexVisitor * MakeEndpointPathEnds::copy() const { - return new MakeEndpointPathEnds(path_end_visitor_, corner_, min_max_, sta_); + return new MakeEndpointPathEnds(path_end_visitor_, scenes_, min_max_, sta_); } void MakeEndpointPathEnds::visit(Vertex *vertex) { - visit_path_ends_.visitPathEnds(vertex, corner_, min_max_, true, path_end_visitor_); + visit_path_ends_.visitPathEnds(vertex, scenes_, min_max_, + true, path_end_visitor_); } //////////////////////////////////////////////////////////////// void -PathGroups::makeGroupPathEnds(VertexSet *endpoints, - const Corner *corner, - const MinMaxAll *min_max, - PathEndVisitor *visitor) +PathGroups::makeGroupPathEnds(VertexSet &endpoints, + const SceneSeq &scenes, + const MinMaxAll *min_max, + PathEndVisitor *visitor) { if (thread_count_ == 1) { - MakeEndpointPathEnds end_visitor(visitor, corner, min_max, this); - for (auto endpoint : *endpoints) + MakeEndpointPathEnds end_visitor(visitor, Scene::sceneSet(scenes), + min_max, this); + for (Vertex *endpoint : endpoints) end_visitor.visit(endpoint); } else { - Vector visitors(thread_count_, - MakeEndpointPathEnds(visitor, corner, - min_max, this)); - for (const auto endpoint : *endpoints) { + std::vector + visitors(thread_count_, + MakeEndpointPathEnds(visitor, Scene::sceneSet(scenes), + min_max, this)); + for (const auto endpoint : endpoints) { dispatch_queue_->dispatch( [endpoint, &visitors](int i) { visitors[i].visit(endpoint); } ); } diff --git a/search/Property.cc b/search/Property.cc index ad63155c..07eddc0a 100644 --- a/search/Property.cc +++ b/search/Property.cc @@ -34,7 +34,7 @@ #include "Network.hh" #include "Graph.hh" #include "Clock.hh" -#include "Corner.hh" +#include "Scene.hh" #include "PathEnd.hh" #include "PathExpanded.hh" #include "Path.hh" @@ -50,9 +50,9 @@ class PropertyUnknown : public Exception { public: PropertyUnknown(const char *type, - const char *property); + const char *property); PropertyUnknown(const char *type, - const string property); + const string property); virtual ~PropertyUnknown() {} virtual const char *what() const noexcept; @@ -62,7 +62,7 @@ private: }; PropertyUnknown::PropertyUnknown(const char *type, - const char *property) : + const char *property) : Exception(), type_(type), property_(property) @@ -70,7 +70,7 @@ PropertyUnknown::PropertyUnknown(const char *type, } PropertyUnknown::PropertyUnknown(const char *type, - const string property) : + const string property) : Exception(), type_(type), property_(property) @@ -81,7 +81,7 @@ const char * PropertyUnknown::what() const noexcept { return stringPrint("%s objects do not have a %s property.", - type_, property_.c_str()); + type_, property_.c_str()); } //////////////////////////////////////////////////////////////// @@ -111,25 +111,25 @@ const char * PropertyTypeWrong::what() const noexcept { return stringPrint("property accessor %s is only valid for %s properties.", - accessor_, type_); + accessor_, type_); } //////////////////////////////////////////////////////////////// PropertyValue::PropertyValue() : - type_(type_none), + type_(Type::none), unit_(nullptr) { } PropertyValue::PropertyValue(const char *value) : - type_(type_string), + type_(Type::string), string_(stringCopy(value)), unit_(nullptr) { } PropertyValue::PropertyValue(std::string &value) : - type_(type_string), + type_(Type::string), string_(stringCopy(value.c_str())), unit_(nullptr) { @@ -137,148 +137,139 @@ PropertyValue::PropertyValue(std::string &value) : PropertyValue::PropertyValue(float value, const Unit *unit) : - type_(type_float), + type_(Type::float_), float_(value), unit_(unit) { } PropertyValue::PropertyValue(bool value) : - type_(type_bool), + type_(Type::bool_), bool_(value), unit_(nullptr) { } PropertyValue::PropertyValue(const LibertyLibrary *value) : - type_(type_liberty_library), + type_(Type::liberty_library), liberty_library_(value), unit_(nullptr) { } PropertyValue::PropertyValue(const LibertyCell *value) : - type_(type_liberty_cell), + type_(Type::liberty_cell), liberty_cell_(value), unit_(nullptr) { } PropertyValue::PropertyValue(const LibertyPort *value) : - type_(type_liberty_port), + type_(Type::liberty_port), liberty_port_(value), unit_(nullptr) { } PropertyValue::PropertyValue(const Library *value) : - type_(type_library), + type_(Type::library), library_(value), unit_(nullptr) { } PropertyValue::PropertyValue(const Cell *value) : - type_(type_cell), + type_(Type::cell), cell_(value), unit_(nullptr) { } PropertyValue::PropertyValue(const Port *value) : - type_(type_port), + type_(Type::port), port_(value), unit_(nullptr) { } PropertyValue::PropertyValue(const Instance *value) : - type_(type_instance), + type_(Type::instance), inst_(value), unit_(nullptr) { } PropertyValue::PropertyValue(const Pin *value) : - type_(type_pin), + type_(Type::pin), pin_(value), unit_(nullptr) { } PropertyValue::PropertyValue(PinSeq *value) : - type_(type_pins), + type_(Type::pins), pins_(value), unit_(nullptr) { } PropertyValue::PropertyValue(PinSet *value) : - type_(type_pins), + type_(Type::pins), pins_(new PinSeq), unit_(nullptr) { - PinSet::Iterator pin_iter(value); - while (pin_iter.hasNext()) { - const Pin *pin = pin_iter.next(); - pins_->push_back( pin); - } + for (const Pin *pin : *value) + pins_->push_back(pin); } PropertyValue::PropertyValue(const PinSet &value) : - type_(type_pins), + type_(Type::pins), pins_(new PinSeq), unit_(nullptr) { - PinSet::ConstIterator pin_iter(value); - while (pin_iter.hasNext()) { - const Pin *pin = pin_iter.next(); - pins_->push_back( pin); - } + for (const Pin *pin : value) + pins_->push_back(pin); } PropertyValue::PropertyValue(const Net *value) : - type_(type_net), + type_(Type::net), net_(value), unit_(nullptr) { } PropertyValue::PropertyValue(const Clock *value) : - type_(type_clk), + type_(Type::clk), clk_(value), unit_(nullptr) { } PropertyValue::PropertyValue(ClockSeq *value) : - type_(type_clks), + type_(Type::clks), clks_(new ClockSeq(*value)), unit_(nullptr) { } PropertyValue::PropertyValue(ClockSet *value) : - type_(type_clks), + type_(Type::clks), clks_(new ClockSeq), unit_(nullptr) { - ClockSet::Iterator clk_iter(value); - while (clk_iter.hasNext()) { - Clock *clk = clk_iter.next(); + for (Clock *clk : *value) clks_->push_back(clk); - } } PropertyValue::PropertyValue(ConstPathSeq *value) : - type_(type_paths), + type_(Type::paths), paths_(new ConstPathSeq(*value)), unit_(nullptr) { } PropertyValue::PropertyValue(PwrActivity *value) : - type_(type_pwr_activity), + type_(Type::pwr_activity), pwr_activity_(*value), unit_(nullptr) { @@ -289,125 +280,125 @@ PropertyValue::PropertyValue(const PropertyValue &value) : unit_(value.unit_) { switch (type_) { - case Type::type_none: + case Type::none: break; - case Type::type_string: + case Type::string: string_ = stringCopy(value.string_); break; - case Type::type_float: + case Type::float_: float_ = value.float_; break; - case Type::type_bool: + case Type::bool_: bool_ = value.bool_; break; - case Type::type_liberty_library: + case Type::liberty_library: liberty_library_ = value.liberty_library_; break; - case Type::type_liberty_cell: + case Type::liberty_cell: liberty_cell_ = value.liberty_cell_; break; - case Type::type_liberty_port: + case Type::liberty_port: liberty_port_ = value.liberty_port_; break; - case Type::type_library: + case Type::library: library_ = value.library_; break; - case Type::type_cell: + case Type::cell: cell_ = value.cell_; break; - case Type::type_port: + case Type::port: port_ = value.port_; break; - case Type::type_instance: + case Type::instance: inst_ = value.inst_; break; - case Type::type_pin: + case Type::pin: pin_ = value.pin_; break; - case Type::type_pins: + case Type::pins: pins_ = value.pins_ ? new PinSeq(*value.pins_) : nullptr; break; - case Type::type_net: + case Type::net: net_ = value.net_; break; - case Type::type_clk: + case Type::clk: clk_ = value.clk_; break; - case Type::type_clks: + case Type::clks: clks_ = value.clks_ ? new ClockSeq(*value.clks_) : nullptr; break; - case Type::type_paths: + case Type::paths: paths_ = value.paths_ ? new ConstPathSeq(*value.paths_) : nullptr; break; - case Type::type_pwr_activity: + case Type::pwr_activity: pwr_activity_ = value.pwr_activity_; break; } } -PropertyValue::PropertyValue(PropertyValue &&value) : +PropertyValue::PropertyValue(PropertyValue &&value) noexcept : type_(value.type_), unit_(value.unit_) { switch (type_) { - case Type::type_none: + case Type::none: break; - case Type::type_string: + case Type::string: string_ = value.string_; value.string_ = nullptr; break; - case Type::type_float: + case Type::float_: float_ = value.float_; break; - case Type::type_bool: + case Type::bool_: bool_ = value.bool_; break; - case Type::type_library: + case Type::library: library_ = value.library_; break; - case Type::type_cell: + case Type::cell: cell_ = value.cell_; break; - case Type::type_port: + case Type::port: port_ = value.port_; break; - case Type::type_liberty_library: + case Type::liberty_library: liberty_library_ = value.liberty_library_; break; - case Type::type_liberty_cell: + case Type::liberty_cell: liberty_cell_ = value.liberty_cell_; break; - case Type::type_liberty_port: + case Type::liberty_port: liberty_port_ = value.liberty_port_; break; - case Type::type_instance: + case Type::instance: inst_ = value.inst_; break; - case Type::type_pin: + case Type::pin: pin_ = value.pin_; break; - case Type::type_pins: + case Type::pins: pins_ = value.pins_; value.pins_ = nullptr; break; - case Type::type_net: + case Type::net: net_ = value.net_; break; - case Type::type_clk: + case Type::clk: clk_ = value.clk_; break; - case Type::type_clks: + case Type::clks: clks_ = value.clks_; // Steal the value. value.clks_ = nullptr; break; - case Type::type_paths: + case Type::paths: paths_ = value.paths_; // Steal the value. value.clks_ = nullptr; break; - case Type::type_pwr_activity: + case Type::pwr_activity: pwr_activity_ = value.pwr_activity_; break; } @@ -416,16 +407,16 @@ PropertyValue::PropertyValue(PropertyValue &&value) : PropertyValue::~PropertyValue() { switch (type_) { - case Type::type_string: + case Type::string: stringDelete(string_); break; - case Type::type_clks: + case Type::clks: delete clks_; break; - case Type::type_pins: + case Type::pins: delete pins_; break; - case Type::type_paths: + case Type::paths: delete paths_; break; default: @@ -440,57 +431,57 @@ PropertyValue::operator=(const PropertyValue &value) unit_ = value.unit_; switch (type_) { - case Type::type_none: + case Type::none: break; - case Type::type_string: + case Type::string: string_ = stringCopy(value.string_); break; - case Type::type_float: + case Type::float_: float_ = value.float_; break; - case Type::type_bool: + case Type::bool_: bool_ = value.bool_; break; - case Type::type_library: + case Type::library: library_ = value.library_; break; - case Type::type_cell: + case Type::cell: cell_ = value.cell_; break; - case Type::type_port: + case Type::port: port_ = value.port_; break; - case Type::type_liberty_library: + case Type::liberty_library: liberty_library_ = value.liberty_library_; break; - case Type::type_liberty_cell: + case Type::liberty_cell: liberty_cell_ = value.liberty_cell_; break; - case Type::type_liberty_port: + case Type::liberty_port: liberty_port_ = value.liberty_port_; break; - case Type::type_instance: + case Type::instance: inst_ = value.inst_; break; - case Type::type_pin: + case Type::pin: pin_ = value.pin_; break; - case Type::type_pins: + case Type::pins: pins_ = value.pins_ ? new PinSeq(*value.pins_) : nullptr; break; - case Type::type_net: + case Type::net: net_ = value.net_; break; - case Type::type_clk: + case Type::clk: clk_ = value.clk_; break; - case Type::type_clks: + case Type::clks: clks_ = value.clks_ ? new ClockSeq(*value.clks_) : nullptr; break; - case Type::type_paths: + case Type::paths: paths_ = value.paths_ ? new ConstPathSeq(*value.paths_) : nullptr; break; - case Type::type_pwr_activity: + case Type::pwr_activity: pwr_activity_ = value.pwr_activity_; break; } @@ -498,67 +489,67 @@ PropertyValue::operator=(const PropertyValue &value) } PropertyValue & -PropertyValue::operator=(PropertyValue &&value) +PropertyValue::operator=(PropertyValue &&value) noexcept { type_ = value.type_; unit_ = value.unit_; switch (type_) { - case Type::type_none: + case Type::none: break; - case Type::type_string: + case Type::string: string_ = value.string_; value.string_ = nullptr; break; - case Type::type_float: + case Type::float_: float_ = value.float_; break; - case Type::type_bool: + case Type::bool_: bool_ = value.bool_; break; - case Type::type_library: + case Type::library: library_ = value.library_; break; - case Type::type_cell: + case Type::cell: cell_ = value.cell_; break; - case Type::type_port: + case Type::port: port_ = value.port_; break; - case Type::type_liberty_library: + case Type::liberty_library: liberty_library_ = value.liberty_library_; break; - case Type::type_liberty_cell: + case Type::liberty_cell: liberty_cell_ = value.liberty_cell_; break; - case Type::type_liberty_port: + case Type::liberty_port: liberty_port_ = value.liberty_port_; break; - case Type::type_instance: + case Type::instance: inst_ = value.inst_; break; - case Type::type_pin: + case Type::pin: pin_ = value.pin_; break; - case Type::type_pins: + case Type::pins: pins_ = value.pins_; value.pins_ = nullptr; break; - case Type::type_net: + case Type::net: net_ = value.net_; break; - case Type::type_clk: + case Type::clk: clk_ = value.clk_; break; - case Type::type_clks: + case Type::clks: clks_ = value.clks_; value.clks_ = nullptr; break; - case Type::type_paths: + case Type::paths: paths_ = value.paths_; value.clks_ = nullptr; break; - case Type::type_pwr_activity: + case Type::pwr_activity: pwr_activity_ = value.pwr_activity_; break; } @@ -569,41 +560,41 @@ string PropertyValue::to_string(const Network *network) const { switch (type_) { - case Type::type_string: + case Type::string: return string_; - case Type::type_float: + case Type::float_: return unit_->asString(float_, 6); - case Type::type_bool: + case Type::bool_: // true/false would be better but these are TCL true/false values. if (bool_) return "1"; else return "0"; - case Type::type_liberty_library: + case Type::liberty_library: return liberty_library_->name(); - case Type::type_liberty_cell: + case Type::liberty_cell: return liberty_cell_->name(); - case Type::type_liberty_port: + case Type::liberty_port: return liberty_port_->name(); - case Type::type_library: + case Type::library: return network->name(library_); - case Type::type_cell: + case Type::cell: return network->name(cell_); - case Type::type_port: + case Type::port: return network->name(port_); - case Type::type_instance: + case Type::instance: return network->pathName(inst_); - case Type::type_pin: + case Type::pin: return network->pathName(pin_); - case Type::type_net: + case Type::net: return network->pathName(net_); - case Type::type_clk: + case Type::clk: return clk_->name(); - case Type::type_none: - case Type::type_pins: - case Type::type_clks: - case Type::type_paths: - case Type::type_pwr_activity: + case Type::none: + case Type::pins: + case Type::clks: + case Type::paths: + case Type::pwr_activity: return ""; } return ""; @@ -612,7 +603,7 @@ PropertyValue::to_string(const Network *network) const const char * PropertyValue::stringValue() const { - if (type_ != Type::type_string) + if (type_ != Type::string) throw PropertyTypeWrong("stringValue", "string"); return string_; } @@ -620,7 +611,7 @@ PropertyValue::stringValue() const float PropertyValue::floatValue() const { - if (type_ != Type::type_float) + if (type_ != Type::float_) throw PropertyTypeWrong("floatValue", "float"); return float_; } @@ -628,7 +619,7 @@ PropertyValue::floatValue() const bool PropertyValue::boolValue() const { - if (type_ != Type::type_bool) + if (type_ != Type::bool_) throw PropertyTypeWrong("boolValue", "boolt"); return bool_; } @@ -642,7 +633,7 @@ Properties::Properties(Sta *sta) : PropertyValue Properties::getProperty(const Library *lib, - const std::string property) + const std::string &property) { Network *network = sta_->cmdNetwork(); if (property == "name" @@ -651,7 +642,7 @@ Properties::getProperty(const Library *lib, else { PropertyValue value = registry_library_.getProperty(lib, property, "library", sta_); - if (value.type() != PropertyValue::Type::type_none) + if (value.type() != PropertyValue::Type::none) return value; else throw PropertyUnknown("library", property); @@ -662,7 +653,7 @@ Properties::getProperty(const Library *lib, PropertyValue Properties::getProperty(const LibertyLibrary *lib, - const std::string property) + const std::string &property) { if (property == "name" || property == "full_name") @@ -673,7 +664,7 @@ Properties::getProperty(const LibertyLibrary *lib, PropertyValue value = registry_liberty_library_.getProperty(lib, property, "liberty_library", sta_); - if (value.type() != PropertyValue::Type::type_none) + if (value.type() != PropertyValue::Type::none) return value; else throw PropertyUnknown("liberty library", property); @@ -684,7 +675,7 @@ Properties::getProperty(const LibertyLibrary *lib, PropertyValue Properties::getProperty(const Cell *cell, - const std::string property) + const std::string &property) { Network *network = sta_->cmdNetwork(); if (property == "name" @@ -704,7 +695,7 @@ Properties::getProperty(const Cell *cell, else { PropertyValue value = registry_cell_.getProperty(cell, property, "cell", sta_); - if (value.type() != PropertyValue::Type::type_none) + if (value.type() != PropertyValue::Type::none) return value; else throw PropertyUnknown("cell", property); @@ -715,7 +706,7 @@ Properties::getProperty(const Cell *cell, PropertyValue Properties::getProperty(const LibertyCell *cell, - const std::string property) + const std::string &property) { if (property == "name" || property == "base_name") @@ -745,7 +736,7 @@ Properties::getProperty(const LibertyCell *cell, else { PropertyValue value = registry_liberty_cell_.getProperty(cell, property, "liberty_cell", sta_); - if (value.type() != PropertyValue::Type::type_none) + if (value.type() != PropertyValue::Type::none) return value; else throw PropertyUnknown("liberty cell", property); @@ -756,14 +747,14 @@ Properties::getProperty(const LibertyCell *cell, PropertyValue Properties::getProperty(const Port *port, - const std::string property) + const std::string &property) { Network *network = sta_->cmdNetwork(); if (property == "name" - || property == "full_name") + || property == "full_name") return PropertyValue(network->name(port)); else if (property == "direction" - || property == "port_direction") + || property == "port_direction") return PropertyValue(network->direction(port)->name()); else if (property == "liberty_port") return PropertyValue(network->libertyPort(port)); @@ -771,40 +762,41 @@ Properties::getProperty(const Port *port, else if (property == "activity") { const Instance *top_inst = network->topInstance(); const Pin *pin = network->findPin(top_inst, port); - PwrActivity activity = sta_->activity(pin); + const Scene *scene = sta_->cmdScene(); + PwrActivity activity = sta_->activity(pin, scene); return PropertyValue(&activity); } else if (property == "slack_max") - return portSlack(port, MinMax::max()); + return portSlack(port, RiseFallBoth::riseFall(), MinMax::max()); else if (property == "slack_max_fall") - return portSlack(port, RiseFall::fall(), MinMax::max()); + return portSlack(port, RiseFallBoth::fall(), MinMax::max()); else if (property == "slack_max_rise") - return portSlack(port, RiseFall::rise(), MinMax::max()); + return portSlack(port, RiseFallBoth::rise(), MinMax::max()); else if (property == "slack_min") - return portSlack(port, MinMax::min()); + return portSlack(port, RiseFallBoth::riseFall(), MinMax::min()); else if (property == "slack_min_fall") - return portSlack(port, RiseFall::fall(), MinMax::min()); + return portSlack(port, RiseFallBoth::fall(), MinMax::min()); else if (property == "slack_min_rise") - return portSlack(port, RiseFall::rise(), MinMax::min()); + return portSlack(port, RiseFallBoth::rise(), MinMax::min()); else if (property == "slew_max") - return portSlew(port, MinMax::max()); + return portSlew(port, RiseFallBoth::fall(), MinMax::max()); else if (property == "slew_max_fall") - return portSlew(port, RiseFall::fall(), MinMax::max()); + return portSlew(port, RiseFallBoth::fall(), MinMax::max()); else if (property == "slew_max_rise") - return portSlew(port, RiseFall::rise(), MinMax::max()); + return portSlew(port, RiseFallBoth::rise(), MinMax::max()); else if (property == "slew_min") - return portSlew(port, MinMax::min()); + return portSlew(port, RiseFallBoth::fall(), MinMax::min()); else if (property == "slew_min_rise") - return portSlew(port, RiseFall::rise(), MinMax::min()); + return portSlew(port, RiseFallBoth::rise(), MinMax::min()); else if (property == "slew_min_fall") - return portSlew(port, RiseFall::fall(), MinMax::min()); + return portSlew(port, RiseFallBoth::fall(), MinMax::min()); else { PropertyValue value = registry_port_.getProperty(port, property, "port", sta_); - if (value.type() != PropertyValue::Type::type_none) + if (value.type() != PropertyValue::Type::none) return value; else throw PropertyUnknown("port", property); @@ -813,17 +805,7 @@ Properties::getProperty(const Port *port, PropertyValue Properties::portSlew(const Port *port, - const MinMax *min_max) -{ - Network *network = sta_->ensureLibLinked(); - Instance *top_inst = network->topInstance(); - Pin *pin = network->findPin(top_inst, port); - return pinSlew(pin, min_max); -} - -PropertyValue -Properties::portSlew(const Port *port, - const RiseFall *rf, + const RiseFallBoth *rf, const MinMax *min_max) { Network *network = sta_->ensureLibLinked(); @@ -834,17 +816,7 @@ Properties::portSlew(const Port *port, PropertyValue Properties::portSlack(const Port *port, - const MinMax *min_max) -{ - Network *network = sta_->ensureLibLinked(); - Instance *top_inst = network->topInstance(); - Pin *pin = network->findPin(top_inst, port); - return pinSlack(pin, min_max); -} - -PropertyValue -Properties::portSlack(const Port *port, - const RiseFall *rf, + const RiseFallBoth *rf, const MinMax *min_max) { Network *network = sta_->ensureLibLinked(); @@ -857,7 +829,7 @@ Properties::portSlack(const Port *port, PropertyValue Properties::getProperty(const LibertyPort *port, - const std::string property) + const std::string &property) { if (property == "name") return PropertyValue(port->name()); @@ -866,7 +838,7 @@ Properties::getProperty(const LibertyPort *port, else if (property == "lib_cell") return PropertyValue(port->libertyCell()); else if (property == "direction" - || property == "port_direction") + || property == "port_direction") return PropertyValue(port->direction()->name()); else if (property == "capacitance") { float cap = port->capacitance(RiseFall::rise(), MinMax::max()); @@ -925,7 +897,7 @@ Properties::getProperty(const LibertyPort *port, else { PropertyValue value = registry_liberty_port_.getProperty(port, property, "liberty_port", sta_); - if (value.type() != PropertyValue::Type::type_none) + if (value.type() != PropertyValue::Type::none) return value; else throw PropertyUnknown("liberty port", property); @@ -936,7 +908,7 @@ Properties::getProperty(const LibertyPort *port, PropertyValue Properties::getProperty(const Instance *inst, - const string property) + const std::string &property) { Network *network = sta_->ensureLinked(); LibertyCell *liberty_cell = network->libertyCell(inst); @@ -965,7 +937,7 @@ Properties::getProperty(const Instance *inst, else { PropertyValue value = registry_instance_.getProperty(inst, property, "instance", sta_); - if (value.type() != PropertyValue::Type::type_none) + if (value.type() != PropertyValue::Type::none) return value; else throw PropertyUnknown("instance", property); @@ -976,7 +948,7 @@ Properties::getProperty(const Instance *inst, PropertyValue Properties::getProperty(const Pin *pin, - const std::string property) + const std::string &property) { Network *network = sta_->ensureLinked(); if (property == "name" @@ -985,7 +957,7 @@ Properties::getProperty(const Pin *pin, else if (property == "full_name") return PropertyValue(network->pathName(pin)); else if (property == "direction" - || property == "pin_direction") + || property == "pin_direction") return PropertyValue(network->direction(pin)->name()); else if (property == "is_hierarchical") return PropertyValue(network->isHierarchical(pin)); @@ -1000,56 +972,59 @@ Properties::getProperty(const Pin *pin, return PropertyValue(port && port->isRegClk()); } else if (property == "clocks") { - ClockSet clks = sta_->clocks(pin); + const Mode *mode = sta_->cmdScene()->mode(); + ClockSet clks = sta_->clocks(pin, mode); return PropertyValue(&clks); } else if (property == "clock_domains") { - ClockSet clks = sta_->clockDomains(pin); + const Mode *mode = sta_->cmdScene()->mode(); + ClockSet clks = sta_->clockDomains(pin, mode); return PropertyValue(&clks); } else if (property == "activity") { - PwrActivity activity = sta_->activity(pin); + const Scene *scene = sta_->cmdScene(); + PwrActivity activity = sta_->activity(pin, scene); return PropertyValue(&activity); } else if (property == "arrival_max_rise") - return pinArrival(pin, RiseFall::rise(), MinMax::max()); + return pinArrival(pin, RiseFallBoth::rise(), MinMax::max()); else if (property == "arrival_max_fall") - return pinArrival(pin, RiseFall::fall(), MinMax::max()); + return pinArrival(pin, RiseFallBoth::fall(), MinMax::max()); else if (property == "arrival_min_rise") - return pinArrival(pin, RiseFall::rise(), MinMax::min()); + return pinArrival(pin, RiseFallBoth::rise(), MinMax::min()); else if (property == "arrival_min_fall") - return pinArrival(pin, RiseFall::fall(), MinMax::min()); + return pinArrival(pin, RiseFallBoth::fall(), MinMax::min()); else if (property == "slack_max") - return pinSlack(pin, MinMax::max()); + return pinSlack(pin, RiseFallBoth::riseFall(), MinMax::max()); else if (property == "slack_max_fall") - return pinSlack(pin, RiseFall::fall(), MinMax::max()); + return pinSlack(pin, RiseFallBoth::fall(), MinMax::max()); else if (property == "slack_max_rise") - return pinSlack(pin, RiseFall::rise(), MinMax::max()); + return pinSlack(pin, RiseFallBoth::rise(), MinMax::max()); else if (property == "slack_min") - return pinSlack(pin, MinMax::min()); + return pinSlack(pin, RiseFallBoth::riseFall(), MinMax::min()); else if (property == "slack_min_fall") - return pinSlack(pin, RiseFall::fall(), MinMax::min()); + return pinSlack(pin, RiseFallBoth::fall(), MinMax::min()); else if (property == "slack_min_rise") - return pinSlack(pin, RiseFall::rise(), MinMax::min()); + return pinSlack(pin, RiseFallBoth::rise(), MinMax::min()); else if (property == "slew_max") - return pinSlew(pin, MinMax::max()); + return pinSlew(pin, RiseFallBoth::riseFall(), MinMax::max()); else if (property == "slew_max_fall") - return pinSlew(pin, RiseFall::fall(), MinMax::max()); + return pinSlew(pin, RiseFallBoth::fall(), MinMax::max()); else if (property == "slew_max_rise") - return pinSlew(pin, RiseFall::rise(), MinMax::max()); + return pinSlew(pin, RiseFallBoth::rise(), MinMax::max()); else if (property == "slew_min") - return pinSlew(pin, MinMax::min()); + return pinSlew(pin, RiseFallBoth::riseFall(), MinMax::min()); else if (property == "slew_min_rise") - return pinSlew(pin, RiseFall::rise(), MinMax::min()); + return pinSlew(pin, RiseFallBoth::rise(), MinMax::min()); else if (property == "slew_min_fall") - return pinSlew(pin, RiseFall::fall(), MinMax::min()); + return pinSlew(pin, RiseFallBoth::fall(), MinMax::min()); else { PropertyValue value = registry_pin_.getProperty(pin, property, "pin", sta_); - if (value.type() != PropertyValue::Type::type_none) + if (value.type() != PropertyValue::Type::none) return value; else throw PropertyUnknown("pin", property); @@ -1058,32 +1033,25 @@ Properties::getProperty(const Pin *pin, PropertyValue Properties::pinArrival(const Pin *pin, - const RiseFall *rf, + const RiseFallBoth *rf, const MinMax *min_max) { - Arrival arrival = sta_->pinArrival(pin, rf, min_max);; + Arrival arrival = sta_->arrival(pin, rf, min_max);; return PropertyValue(delayPropertyValue(arrival)); } PropertyValue Properties::pinSlack(const Pin *pin, + const RiseFallBoth *rf, const MinMax *min_max) { - Slack slack = sta_->pinSlack(pin, min_max); - return PropertyValue(delayPropertyValue(slack)); -} - -PropertyValue -Properties::pinSlack(const Pin *pin, - const RiseFall *rf, - const MinMax *min_max) -{ - Slack slack = sta_->pinSlack(pin, rf, min_max); + Slack slack = sta_->slack(pin, rf, sta_->scenes(), min_max); return PropertyValue(delayPropertyValue(slack)); } PropertyValue Properties::pinSlew(const Pin *pin, + const RiseFallBoth *rf, const MinMax *min_max) { Graph *graph = sta_->ensureGraph(); @@ -1091,34 +1059,13 @@ Properties::pinSlew(const Pin *pin, graph->pinVertices(pin, vertex, bidirect_drvr_vertex); Slew slew = min_max->initValue(); if (vertex) { - Slew vertex_slew = sta_->vertexSlew(vertex, min_max); + Slew vertex_slew = sta_->slew(vertex, rf, sta_->scenes(), min_max); if (delayGreater(vertex_slew, slew, min_max, sta_)) slew = vertex_slew; } if (bidirect_drvr_vertex) { - Slew vertex_slew = sta_->vertexSlew(bidirect_drvr_vertex, min_max); - if (delayGreater(vertex_slew, slew, min_max, sta_)) - slew = vertex_slew; - } - return delayPropertyValue(slew); -} - -PropertyValue -Properties::pinSlew(const Pin *pin, - const RiseFall *rf, - const MinMax *min_max) -{ - Graph *graph = sta_->ensureGraph(); - Vertex *vertex, *bidirect_drvr_vertex; - graph->pinVertices(pin, vertex, bidirect_drvr_vertex); - Slew slew = min_max->initValue(); - if (vertex) { - Slew vertex_slew = sta_->vertexSlew(vertex, rf, min_max); - if (delayGreater(vertex_slew, slew, min_max, sta_)) - slew = vertex_slew; - } - if (bidirect_drvr_vertex) { - Slew vertex_slew = sta_->vertexSlew(bidirect_drvr_vertex, rf, min_max); + Slew vertex_slew = sta_->slew(bidirect_drvr_vertex, rf, + sta_->scenes(), min_max); if (delayGreater(vertex_slew, slew, min_max, sta_)) slew = vertex_slew; } @@ -1129,7 +1076,7 @@ Properties::pinSlew(const Pin *pin, PropertyValue Properties::getProperty(const Net *net, - const std::string property) + const std::string &property) { Network *network = sta_->ensureLinked(); if (property == "name") @@ -1138,7 +1085,7 @@ Properties::getProperty(const Net *net, return PropertyValue(network->pathName(net)); else { PropertyValue value = registry_net_.getProperty(net, property, "net", sta_); - if (value.type() != PropertyValue::Type::type_none) + if (value.type() != PropertyValue::Type::none) return value; else throw PropertyUnknown("net", property); @@ -1149,7 +1096,7 @@ Properties::getProperty(const Net *net, PropertyValue Properties::getProperty(Edge *edge, - const std::string property) + const std::string &property) { if (property == "full_name") { string full_name = edge->to_string(sta_); @@ -1184,12 +1131,12 @@ Properties::edgeDelay(Edge *edge, for (TimingArc *arc : arc_set->arcs()) { const RiseFall *to_rf = arc->toEdge()->asRiseFall(); if (to_rf == rf) { - for (const Corner *corner : *sta_->corners()) { - DcalcAnalysisPt *dcalc_ap = corner->findDcalcAnalysisPt(min_max); - ArcDelay arc_delay = sta_->arcDelay(edge, arc, dcalc_ap); - if (!delay_exists - || delayGreater(arc_delay, delay, min_max, sta_)) { - delay = arc_delay; + for (const Scene *scene : sta_->scenes()) { + DcalcAPIndex ap_index = scene->dcalcAnalysisPtIndex(min_max); + ArcDelay arc_delay = sta_->arcDelay(edge, arc, ap_index); + if (!delay_exists + || delayGreater(arc_delay, delay, min_max, sta_)) { + delay = arc_delay; delay_exists = true; } } @@ -1202,7 +1149,7 @@ Properties::edgeDelay(Edge *edge, PropertyValue Properties::getProperty(TimingArcSet *arc_set, - const std::string property) + const std::string &property) { if (property == "name" || property == "full_name") { @@ -1225,7 +1172,7 @@ Properties::getProperty(TimingArcSet *arc_set, PropertyValue Properties::getProperty(const Clock *clk, - const std::string property) + const std::string &property) { if (property == "name" || property == "full_name") @@ -1243,7 +1190,7 @@ Properties::getProperty(const Clock *clk, else { PropertyValue value = registry_clock_.getProperty(clk, property, "clock", sta_); - if (value.type() != PropertyValue::Type::type_none) + if (value.type() != PropertyValue::Type::none) return value; else throw PropertyUnknown("clock", property); @@ -1254,7 +1201,7 @@ Properties::getProperty(const Clock *clk, PropertyValue Properties::getProperty(PathEnd *end, - const std::string property) + const std::string &property) { if (property == "startpoint") { PathExpanded expanded(end->path(), sta_); @@ -1285,7 +1232,7 @@ Properties::getProperty(PathEnd *end, PropertyValue Properties::getProperty(Path *path, - const std::string property) + const std::string &property) { if (property == "pin") return PropertyValue(path->pin(sta_)); @@ -1320,70 +1267,70 @@ Properties::capacitancePropertyValue(float cap) //////////////////////////////////////////////////////////////// void -Properties::defineProperty(std::string &property, +Properties::defineProperty(std::string_view property, PropertyRegistry::PropertyHandler handler) { registry_library_.defineProperty(property, handler); } void -Properties::defineProperty(std::string &property, +Properties::defineProperty(std::string_view property, PropertyRegistry::PropertyHandler handler) { registry_liberty_library_.defineProperty(property, handler); } void -Properties::defineProperty(std::string &property, +Properties::defineProperty(std::string_view property, PropertyRegistry::PropertyHandler handler) { registry_cell_.defineProperty(property, handler); } void -Properties::defineProperty(std::string &property, +Properties::defineProperty(std::string_view property, PropertyRegistry::PropertyHandler handler) { registry_liberty_cell_.defineProperty(property, handler); } void -Properties::defineProperty(std::string &property, +Properties::defineProperty(std::string_view property, PropertyRegistry::PropertyHandler handler) { registry_port_.defineProperty(property, handler); } void -Properties::defineProperty(std::string &property, +Properties::defineProperty(std::string_view property, PropertyRegistry::PropertyHandler handler) { registry_liberty_port_.defineProperty(property, handler); } void -Properties::defineProperty(std::string &property, +Properties::defineProperty(std::string_view property, PropertyRegistry::PropertyHandler handler) { registry_instance_.defineProperty(property, handler); } void -Properties::defineProperty(std::string &property, +Properties::defineProperty(std::string_view property, PropertyRegistry::PropertyHandler handler) { registry_pin_.defineProperty(property, handler); } void -Properties::defineProperty(std::string &property, +Properties::defineProperty(std::string_view property, PropertyRegistry::PropertyHandler handler) { registry_net_.defineProperty(property, handler); } void -Properties::defineProperty(std::string &property, +Properties::defineProperty(std::string_view property, PropertyRegistry::PropertyHandler handler) { registry_clock_.defineProperty(property, handler); @@ -1399,7 +1346,7 @@ PropertyRegistry::getProperty(TYPE object, Sta *sta) { - auto itr = registry_.find({property}); + auto itr = registry_.find(property); if (itr != registry_.end()) return itr->second(object, sta); else @@ -1408,10 +1355,10 @@ PropertyRegistry::getProperty(TYPE object, template void -PropertyRegistry::defineProperty(const std::string &property, +PropertyRegistry::defineProperty(std::string_view property, PropertyHandler handler) { - registry_[property] = handler; + registry_[std::string(property)] = handler; } } // namespace diff --git a/search/Property.i b/search/Property.i index bb3853b2..45f02d08 100644 --- a/search/Property.i +++ b/search/Property.i @@ -37,7 +37,7 @@ using namespace sta; PropertyValue library_property(const Library *lib, - const char *property) + const char *property) { Properties &properties = Sta::sta()->properties(); return properties.getProperty(lib, property); @@ -45,7 +45,7 @@ library_property(const Library *lib, PropertyValue liberty_library_property(const LibertyLibrary *lib, - const char *property) + const char *property) { Properties &properties = Sta::sta()->properties(); return properties.getProperty(lib, property); @@ -53,7 +53,7 @@ liberty_library_property(const LibertyLibrary *lib, PropertyValue cell_property(const Cell *cell, - const char *property) + const char *property) { Properties &properties = Sta::sta()->properties(); return properties.getProperty(cell, property); @@ -61,7 +61,7 @@ cell_property(const Cell *cell, PropertyValue liberty_cell_property(const LibertyCell *cell, - const char *property) + const char *property) { Properties &properties = Sta::sta()->properties(); return properties.getProperty(cell, property); @@ -69,7 +69,7 @@ liberty_cell_property(const LibertyCell *cell, PropertyValue port_property(const Port *port, - const char *property) + const char *property) { Properties &properties = Sta::sta()->properties(); return properties.getProperty(port, property); @@ -77,7 +77,7 @@ port_property(const Port *port, PropertyValue liberty_port_property(const LibertyPort *port, - const char *property) + const char *property) { Properties &properties = Sta::sta()->properties(); return properties.getProperty(port, property); @@ -85,7 +85,7 @@ liberty_port_property(const LibertyPort *port, PropertyValue instance_property(const Instance *inst, - const char *property) + const char *property) { Properties &properties = Sta::sta()->properties(); return properties.getProperty(inst, property); @@ -93,7 +93,7 @@ instance_property(const Instance *inst, PropertyValue pin_property(const Pin *pin, - const char *property) + const char *property) { Properties &properties = Sta::sta()->properties(); return properties.getProperty(pin, property); @@ -101,7 +101,7 @@ pin_property(const Pin *pin, PropertyValue net_property(const Net *net, - const char *property) + const char *property) { Properties &properties = Sta::sta()->properties(); return properties.getProperty(net, property); @@ -109,7 +109,7 @@ net_property(const Net *net, PropertyValue edge_property(Edge *edge, - const char *property) + const char *property) { Properties &properties = Sta::sta()->properties(); return properties.getProperty(edge, property); @@ -117,7 +117,7 @@ edge_property(Edge *edge, PropertyValue clock_property(Clock *clk, - const char *property) + const char *property) { Properties &properties = Sta::sta()->properties(); return properties.getProperty(clk, property); @@ -125,7 +125,7 @@ clock_property(Clock *clk, PropertyValue path_end_property(PathEnd *end, - const char *property) + const char *property) { Properties &properties = Sta::sta()->properties(); return properties.getProperty(end, property); diff --git a/search/ReportPath.cc b/search/ReportPath.cc index 6b991557..9122a805 100644 --- a/search/ReportPath.cc +++ b/search/ReportPath.cc @@ -26,6 +26,7 @@ #include "ReportPath.hh" +#include "ContainerHelpers.hh" #include "Report.hh" #include "Error.hh" #include "StringUtil.hh" @@ -43,12 +44,10 @@ #include "InputDrive.hh" #include "Sdc.hh" #include "Parasitics.hh" -#include "DcalcAnalysisPt.hh" #include "ArcDelayCalc.hh" #include "GraphDelayCalc.hh" #include "ClkInfo.hh" #include "Tag.hh" -#include "PathAnalysisPt.hh" #include "PathGroup.hh" #include "CheckMinPulseWidths.hh" #include "CheckMinPeriods.hh" @@ -57,7 +56,8 @@ #include "Search.hh" #include "PathExpanded.hh" #include "Latches.hh" -#include "Corner.hh" +#include "Scene.hh" +#include "Mode.hh" #include "Genclks.hh" #include "Variables.hh" @@ -80,11 +80,11 @@ hierPinsThruEdge(const Edge *edge, const Graph *graph); ReportField::ReportField(const char *name, - const char *title, - int width, - bool left_justify, - Unit *unit, - bool enabled) : + const char *title, + int width, + bool left_justify, + Unit *unit, + bool enabled) : name_(name), title_(stringCopy(title)), left_justify_(left_justify), @@ -103,8 +103,8 @@ ReportField::~ReportField() void ReportField::setProperties(const char *title, - int width, - bool left_justify) + int width, + bool left_justify) { if (title_) stringDelete(title_); @@ -172,31 +172,31 @@ ReportPath::makeFields() { field_fanout_ = makeField("fanout", "Fanout", 6, false, nullptr, true); field_capacitance_ = makeField("capacitance", "Cap", 6, false, - units_->capacitanceUnit(), true); + units_->capacitanceUnit(), true); field_slew_ = makeField("slew", "Slew", 6, false, units_->timeUnit(), - true); + true); field_incr_ = makeField("incr", "Delay", 6, false, units_->timeUnit(), - true); + true); field_total_ = makeField("total", "Time", 6, false, units_->timeUnit(), - true); + true); field_edge_ = makeField("edge", "", 1, false, nullptr, true); field_case_ = makeField("case", "case", 11, false, nullptr, false); field_description_ = makeField("description", "Description", 36, - true, nullptr, true); + true, nullptr, true); field_src_attr_ = makeField("src_attr", "Src Attr", 40, - true, nullptr, true); + true, nullptr, true); } ReportField * ReportPath::makeField(const char *name, - const char *title, - int width, - bool left_justify, - Unit *unit, - bool enabled) + const char *title, + int width, + bool left_justify, + Unit *unit, + bool enabled) { ReportField *field = new ReportField(name, title, width, left_justify, - unit, enabled); + unit, enabled); fields_.push_back(field); return field; } @@ -215,11 +215,8 @@ void ReportPath::setReportFieldOrder(StringSeq *field_names) { // Disable all fields. - ReportFieldSeq::Iterator field_iter1(fields_); - while (field_iter1.hasNext()) { - ReportField *field = field_iter1.next(); + for (ReportField *field : fields_) field->setEnabled(false); - } ReportFieldSeq next_fields; for (const char *field_name : *field_names) { @@ -243,11 +240,11 @@ ReportPath::setReportFieldOrder(StringSeq *field_names) void ReportPath::setReportFields(bool report_input_pin, bool report_hier_pins, - bool report_net, - bool report_cap, - bool report_slew, - bool report_fanout, - bool report_src_attr) + bool report_net, + bool report_cap, + bool report_slew, + bool report_fanout, + bool report_src_attr) { report_input_pin_ = report_input_pin; report_hier_pins_ = report_hier_pins; @@ -300,7 +297,7 @@ ReportPath::reportPathEnd(const PathEnd *end) const void ReportPath::reportPathEnd(const PathEnd *end, - const PathEnd *prev_end, + const PathEnd *prev_end, bool last) const { switch (format_) { @@ -337,11 +334,10 @@ ReportPath::reportPathEnds(const PathEndSeq *ends) const { reportPathEndHeader(); if (ends && !ends->empty()) { - PathEnd *prev_end = nullptr; - PathEndSeq::ConstIterator end_iter(ends); - while (end_iter.hasNext()) { - PathEnd *end = end_iter.next(); - reportPathEnd(end, prev_end, !end_iter.hasNext()); + const PathEnd *prev_end = nullptr; + for (size_t i = 0; i < ends->size(); i++) { + const PathEnd *end = (*ends)[i]; + reportPathEnd(end, prev_end, i == ends->size() - 1); prev_end = end; } } @@ -397,7 +393,7 @@ ReportPath::reportPathEndFooter() const void ReportPath::reportEndpointHeader(const PathEnd *end, - const PathEnd *prev_end) const + const PathEnd *prev_end) const { PathGroup *prev_group = nullptr; if (prev_end) @@ -428,7 +424,7 @@ ReportPath::reportShort(const PathEndUnconstrained *end) const void ReportPath::reportShort(const PathEndUnconstrained *end, - const PathExpanded &expanded) const + const PathExpanded &expanded) const { reportStartpoint(end, expanded); reportUnclockedEndpoint(end, "internal pin"); @@ -444,7 +440,7 @@ ReportPath::reportFull(const PathEndUnconstrained *end) const reportPath(end, expanded); reportLine("data arrival time", end->dataArrivalTimeOffset(this), - end->pathEarlyLate(this)); + end->pathEarlyLate(this)); reportDashLine(); report_->reportLine("(Path is unconstrained)"); } @@ -460,7 +456,7 @@ ReportPath::reportShort(const PathEndCheck *end) const void ReportPath::reportShort(const PathEndCheck *end, - const PathExpanded &expanded) const + const PathExpanded &expanded) const { reportStartpoint(end, expanded); reportEndpoint(end); @@ -497,17 +493,17 @@ ReportPath::reportEndpoint(const PathEndCheck *end) const if (check_role == TimingRole::recovery() || check_role == TimingRole::removal()) { auto reason = stdstrPrint("%s check against %s-edge clock %s", - check_role->to_string().c_str(), - rise_fall, - clk_name.c_str()); + check_role->to_string().c_str(), + rise_fall, + clk_name.c_str()); reportEndpoint(inst_name, reason); } else if (check_generic_role == TimingRole::setup() - || check_generic_role == TimingRole::hold()) { + || check_generic_role == TimingRole::hold()) { LibertyCell *cell = network_->libertyCell(inst); if (cell->isClockGate()) { auto reason = stdstrPrint("%s clock gating-check end-point clocked by %s", - rise_fall, clk_name.c_str()); + rise_fall, clk_name.c_str()); reportEndpoint(inst_name, reason); } else { @@ -529,7 +525,7 @@ ReportPath::reportShort(const PathEndLatchCheck *end) const void ReportPath::reportShort(const PathEndLatchCheck *end, - const PathExpanded &expanded) const + const PathExpanded &expanded) const { reportStartpoint(end, expanded); reportEndpoint(end); @@ -559,7 +555,7 @@ ReportPath::reportFull(const PathEndLatchCheck *end) const Required req_time; Arrival borrow, adjusted_data_arrival, time_given_to_startpoint; end->latchRequired(this, req_time, borrow, adjusted_data_arrival, - time_given_to_startpoint); + time_given_to_startpoint); // Adjust required to requiredTimeOffset. req_time += end->sourceClkOffset(this); if (path_delay) { @@ -567,11 +563,11 @@ ReportPath::reportFull(const PathEndLatchCheck *end) const reportLine("max_delay", delay, delay, early_late); if (!ignore_clk_latency) { if (reportClkPath() - && isPropagated(end->targetClkPath())) - reportTgtClk(end, delay); + && isPropagated(end->targetClkPath())) + reportTgtClk(end, delay); else { - Delay delay1(delay); - reportCommonClkPessimism(end, delay1); + Delay delay1(delay); + reportCommonClkPessimism(end, delay1); } } } @@ -613,8 +609,8 @@ ReportPath::latchDesc(const PathEndLatchCheck *end) const void ReportPath::reportBorrowing(const PathEndLatchCheck *end, - Arrival &borrow, - Arrival &time_given_to_startpoint) const + Arrival &borrow, + Arrival &time_given_to_startpoint) const { Delay open_latency, latency_diff, max_borrow; float nom_pulse_width, open_uncertainty; @@ -622,8 +618,8 @@ ReportPath::reportBorrowing(const PathEndLatchCheck *end, bool borrow_limit_exists; const EarlyLate *early_late = EarlyLate::late(); end->latchBorrowInfo(this, nom_pulse_width, open_latency, latency_diff, - open_uncertainty, open_crpr, crpr_diff, - max_borrow, borrow_limit_exists); + open_uncertainty, open_crpr, crpr_diff, + max_borrow, borrow_limit_exists); report_->reportLine("Time Borrowing Information"); reportDashLineTotal(); if (borrow_limit_exists) @@ -636,7 +632,7 @@ ReportPath::reportBorrowing(const PathEndLatchCheck *end, auto width_msg = stdstrPrint("%s nominal pulse width", tgt_clk_name.c_str()); reportLineTotal(width_msg.c_str(), nom_pulse_width, early_late); if (!delayZero(latency_diff)) - reportLineTotalMinus("clock latency difference", latency_diff, early_late); + reportLineTotalMinus("clock latency difference", latency_diff, early_late); } else { auto width_msg = stdstrPrint("%s pulse width", tgt_clk_name.c_str()); @@ -651,7 +647,7 @@ ReportPath::reportBorrowing(const PathEndLatchCheck *end, } if (delayGreater(borrow, delay_zero, this) && (!fuzzyZero(open_uncertainty) - || !delayZero(open_crpr))) { + || !delayZero(open_crpr))) { reportDashLineTotal(); reportLineTotal("actual time borrow", borrow, early_late); if (!fuzzyZero(open_uncertainty)) @@ -677,7 +673,7 @@ ReportPath::reportShort(const PathEndPathDelay *end) const void ReportPath::reportShort(const PathEndPathDelay *end, - const PathExpanded &expanded) const + const PathExpanded &expanded) const { reportStartpoint(end, expanded); if (end->targetClk(this)) @@ -735,16 +731,16 @@ ReportPath::reportFull(const PathEndPathDelay *end) const if (tgt_clk) { const Path *tgt_clk_path = end->targetClkPath(); if (reportClkPath() - && isPropagated(tgt_clk_path, tgt_clk)) - reportTgtClk(end, delay, 0.0, true); + && isPropagated(tgt_clk_path, tgt_clk)) + reportTgtClk(end, delay, 0.0, true); else { - Arrival tgt_clk_delay = end->targetClkDelay(this); - Arrival tgt_clk_arrival = delay + tgt_clk_delay; - if (!delayZero(tgt_clk_delay)) - reportLine(clkNetworkDelayIdealProp(isPropagated(tgt_clk_path)), - tgt_clk_delay, tgt_clk_arrival, early_late); - reportClkUncertainty(end, tgt_clk_arrival); - reportCommonClkPessimism(end, tgt_clk_arrival); + Arrival tgt_clk_delay = end->targetClkDelay(this); + Arrival tgt_clk_arrival = delay + tgt_clk_delay; + if (!delayZero(tgt_clk_delay)) + reportLine(clkNetworkDelayIdealProp(isPropagated(tgt_clk_path)), + tgt_clk_delay, tgt_clk_arrival, early_late); + reportClkUncertainty(end, tgt_clk_arrival); + reportCommonClkPessimism(end, tgt_clk_arrival); } } } @@ -763,7 +759,7 @@ ReportPath::isPropagated(const Path *clk_path) const bool ReportPath::isPropagated(const Path *clk_path, - const Clock *clk) const + const Clock *clk) const { if (clk_path) return clk_path->clkInfo(search_)->isPropagated(); @@ -791,7 +787,7 @@ ReportPath::reportShort(const PathEndOutputDelay *end) const void ReportPath::reportShort(const PathEndOutputDelay *end, - const PathExpanded &expanded) const + const PathExpanded &expanded) const { reportStartpoint(end, expanded); reportEndpoint(end); @@ -856,7 +852,7 @@ ReportPath::reportShort(const PathEndGatedClock *end) const void ReportPath::reportShort(const PathEndGatedClock *end, - const PathExpanded &expanded) const + const PathExpanded &expanded) const { reportStartpoint(end, expanded); reportEndpoint(end); @@ -886,8 +882,8 @@ ReportPath::reportEndpoint(const PathEndGatedClock *end) const const char *rise_fall = asRisingFalling(clk_rf); // Note that target clock transition is ignored. auto reason = stdstrPrint("%s clock gating-check end-point clocked by %s", - rise_fall, - clk_name.c_str()); + rise_fall, + clk_name.c_str()); reportEndpoint(inst_name, reason); } @@ -902,7 +898,7 @@ ReportPath::reportShort(const PathEndDataCheck *end) const void ReportPath::reportShort(const PathEndDataCheck *end, - const PathExpanded &expanded) const + const PathExpanded &expanded) const { reportStartpoint(end, expanded); reportEndpoint(end); @@ -935,7 +931,7 @@ ReportPath::reportFull(const PathEndDataCheck *end) const float offset = prev - delayAsFloat(clk_delay) - tgt_clk_edge->time(); // Delay to startpoint is already included. reportPath6(data_clk_path, clk_expanded, clk_expanded.startIndex(), - true, false, prev, offset); + true, false, prev, offset); } reportRequired(end, checkRoleReason(end)); reportSlack(end); @@ -949,8 +945,8 @@ ReportPath::reportEndpoint(const PathEndDataCheck *end) const const char *tgt_clk_rf = asRisingFalling(end->dataClkPath()->transition(this)); const char *tgt_clk_name = end->targetClk(this)->name(); auto reason = stdstrPrint("%s edge-triggered data to data check clocked by %s", - tgt_clk_rf, - tgt_clk_name); + tgt_clk_rf, + tgt_clk_name); reportEndpoint(inst_name, reason); } @@ -1031,7 +1027,7 @@ ReportPath::reportSummaryLine(const PathEnd *end) const string ReportPath::pathStartpoint(const PathEnd *end, - const PathExpanded &expanded) const + const PathExpanded &expanded) const { const Path *start = expanded.startPath(); Pin *pin = start->pin(graph_); @@ -1185,7 +1181,8 @@ ReportPath::reportJson(const PathExpanded &expanded, const Net *net = network_->net(pin); const Instance *inst = network_->instance(pin); const RiseFall *rf = path->transition(this); - DcalcAnalysisPt *dcalc_ap = path->pathAnalysisPt(this)->dcalcAnalysisPt(); + const Scene *scene = path->scene(this); + const MinMax *min_max = path->minMax(this); bool is_driver = network_->isDriver(pin); stringAppend(result, "%*s {\n", indent, ""); @@ -1201,7 +1198,7 @@ ReportPath::reportJson(const PathExpanded &expanded, sdc_network_->name(cell)); stringAppend(result, "%*s \"verilog_src\": \"%s\",\n", indent, "", - sdc_network_->getAttribute(inst, "src").c_str()); + sdc_network_->getAttribute(inst, "src").c_str()); } stringAppend(result, "%*s \"pin\": \"%s\",\n", @@ -1241,7 +1238,7 @@ ReportPath::reportJson(const PathExpanded &expanded, if (is_driver) stringAppend(result, "%*s \"capacitance\": %.3e,\n", indent, "", - graph_delay_calc_->loadCap(pin, rf, dcalc_ap)); + graph_delay_calc_->loadCap(pin, rf, scene, min_max)); stringAppend(result, "%*s \"slew\": %.3e\n", indent, "", delayAsFloat(path->slew(this))); @@ -1284,8 +1281,8 @@ ReportPath::reportSlackOnly(const PathEnd *end) const //////////////////////////////////////////////////////////////// void -ReportPath::reportMpwCheck(const MinPulseWidthCheck *check, - bool verbose) const +ReportPath::reportMpwCheck(const MinPulseWidthCheck &check, + bool verbose) const { if (verbose) { reportVerbose(check); @@ -1299,20 +1296,20 @@ ReportPath::reportMpwCheck(const MinPulseWidthCheck *check, } void -ReportPath::reportMpwChecks(const MinPulseWidthCheckSeq *checks, - bool verbose) const +ReportPath::reportMpwChecks(const MinPulseWidthCheckSeq &checks, + bool verbose) const { - if (!checks->empty()) { + if (!checks.empty()) { if (verbose) { - for (const MinPulseWidthCheck *check : *checks) { + for (const MinPulseWidthCheck &check : checks) { reportVerbose(check); reportBlankLine(); } } else { reportMpwHeaderShort(); - for (const MinPulseWidthCheck *check : *checks) - reportShort(check); + for (const MinPulseWidthCheck &check : checks) + reportShort(check); } reportBlankLine(); } @@ -1343,24 +1340,24 @@ ReportPath::reportMpwHeaderShort() const } void -ReportPath::reportShort(const MinPulseWidthCheck *check) const +ReportPath::reportShort(const MinPulseWidthCheck &check) const { string line; - const char *pin_name = cmd_network_->pathName(check->pin(this)); + const char *pin_name = cmd_network_->pathName(check.pin(this)); const char *hi_low = mpwCheckHiLow(check); auto what = stdstrPrint("%s (%s)", pin_name, hi_low); reportDescription(what.c_str(), line); - reportSpaceFieldTime(check->minWidth(this), line); - reportSpaceFieldDelay(check->width(this), EarlyLate::late(), line); - reportSpaceSlack(check->slack(this), line); + reportSpaceFieldTime(check.minWidth(this), line); + reportSpaceFieldDelay(check.width(this), EarlyLate::late(), line); + reportSpaceSlack(check.slack(this), line); report_->reportLineString(line); } void -ReportPath::reportVerbose(const MinPulseWidthCheck *check) const +ReportPath::reportVerbose(const MinPulseWidthCheck &check) const { string line; - const char *pin_name = cmd_network_->pathName(check->pin(this)); + const char *pin_name = cmd_network_->pathName(check.pin(this)); line += "Pin: "; line += pin_name; report_->reportLineString(line); @@ -1370,7 +1367,7 @@ ReportPath::reportVerbose(const MinPulseWidthCheck *check) const reportPathHeader(); const EarlyLate *open_el = EarlyLate::late(); - const ClockEdge *open_clk_edge = check->openClkEdge(this); + const ClockEdge *open_clk_edge = check.openClkEdge(this); const Clock *open_clk = open_clk_edge->clock(); const char *open_clk_name = open_clk->name(); const char *open_rise_fall = asRiseFall(open_clk_edge->transition()); @@ -1378,48 +1375,48 @@ ReportPath::reportVerbose(const MinPulseWidthCheck *check) const auto open_clk_msg = stdstrPrint("clock %s (%s edge)", open_clk_name, open_rise_fall); reportLine(open_clk_msg.c_str(), open_clk_time, open_clk_time, open_el); - Arrival open_arrival = check->openArrival(this); - bool is_prop = isPropagated(check->openPath()); + Arrival open_arrival = check.openArrival(this); + bool is_prop = isPropagated(check.openPath()); const char *clk_ideal_prop = clkNetworkDelayIdealProp(is_prop); - reportLine(clk_ideal_prop, check->openDelay(this), open_arrival, open_el); + reportLine(clk_ideal_prop, check.openDelay(this), open_arrival, open_el); reportLine(pin_name, delay_zero, open_arrival, open_el); reportLine("open edge arrival time", open_arrival, open_el); reportBlankLine(); const EarlyLate *close_el = EarlyLate::late(); - const ClockEdge *close_clk_edge = check->closeClkEdge(this); + const ClockEdge *close_clk_edge = check.closeClkEdge(this); const Clock *close_clk = close_clk_edge->clock(); const char *close_clk_name = close_clk->name(); const char *close_rise_fall = asRiseFall(close_clk_edge->transition()); - float close_offset = check->closeOffset(this); + float close_offset = check.closeOffset(this); float close_clk_time = close_clk_edge->time() + close_offset; auto close_clk_msg = stdstrPrint("clock %s (%s edge)", close_clk_name, close_rise_fall); reportLine(close_clk_msg.c_str(), close_clk_time, close_clk_time, close_el); - Arrival close_arrival = check->closeArrival(this) + close_offset; - reportLine(clk_ideal_prop, check->closeDelay(this), close_arrival, close_el); + Arrival close_arrival = check.closeArrival(this) + close_offset; + reportLine(clk_ideal_prop, check.closeDelay(this), close_arrival, close_el); reportLine(pin_name, delay_zero, close_arrival, close_el); if (variables_->crprEnabled()) { - Crpr pessimism = check->checkCrpr(this); + Crpr pessimism = check.checkCrpr(this); close_arrival += pessimism; reportLine("clock reconvergence pessimism", pessimism, close_arrival, close_el); } reportLine("close edge arrival time", close_arrival, close_el); reportDashLine(); - float min_width = check->minWidth(this); + float min_width = check.minWidth(this); const char *hi_low = mpwCheckHiLow(check); auto rpw_msg = stdstrPrint("required pulse width (%s)", hi_low); reportLine(rpw_msg.c_str(), min_width, EarlyLate::early()); - reportLine("actual pulse width", check->width(this), EarlyLate::early()); + reportLine("actual pulse width", check.width(this), EarlyLate::early()); reportDashLine(); - reportSlack(check->slack(this)); + reportSlack(check.slack(this)); } const char * -ReportPath::mpwCheckHiLow(const MinPulseWidthCheck *check) const +ReportPath::mpwCheckHiLow(const MinPulseWidthCheck &check) const { - if (check->openTransition(this) == RiseFall::rise()) + if (check.openTransition(this) == RiseFall::rise()) return "high"; else return "low"; @@ -1428,8 +1425,8 @@ ReportPath::mpwCheckHiLow(const MinPulseWidthCheck *check) const //////////////////////////////////////////////////////////////// void -ReportPath::reportCheck(const MinPeriodCheck *check, - bool verbose) const +ReportPath::reportCheck(const MinPeriodCheck &check, + bool verbose) const { if (verbose) { reportVerbose(check); @@ -1443,20 +1440,20 @@ ReportPath::reportCheck(const MinPeriodCheck *check, } void -ReportPath::reportChecks(const MinPeriodCheckSeq *checks, - bool verbose) const +ReportPath::reportChecks(const MinPeriodCheckSeq &checks, + bool verbose) const { - if (!checks->empty()) { + if (!checks.empty()) { if (verbose) { - for (const MinPeriodCheck *check : *checks) { - reportVerbose(check); + for (const MinPeriodCheck &check : checks) { + reportVerbose(check); reportBlankLine(); } } else { reportPeriodHeaderShort(); - for (const MinPeriodCheck *check : *checks) - reportShort(check); + for (const MinPeriodCheck &check : checks) + reportShort(check); } reportBlankLine(); } @@ -1489,63 +1486,48 @@ ReportPath::reportPeriodHeaderShort() const } void -ReportPath::reportShort(const MinPeriodCheck *check) const +ReportPath::reportShort(const MinPeriodCheck &check) const { string line; - const char *pin_name = cmd_network_->pathName(check->pin()); + const char *pin_name = cmd_network_->pathName(check.pin()); reportDescription(pin_name, line); - reportSpaceFieldDelay(check->period(), EarlyLate::early(), line); - reportSpaceFieldDelay(check->minPeriod(this), EarlyLate::early(), line); - reportSpaceSlack(check->slack(this), line); + reportSpaceFieldDelay(check.period(), EarlyLate::early(), line); + reportSpaceFieldDelay(check.minPeriod(this), EarlyLate::early(), line); + reportSpaceSlack(check.slack(this), line); report_->reportLineString(line); } void -ReportPath::reportVerbose(const MinPeriodCheck *check) const +ReportPath::reportVerbose(const MinPeriodCheck &check) const { string line; - const char *pin_name = cmd_network_->pathName(check->pin()); + const char *pin_name = cmd_network_->pathName(check.pin()); line += "Pin: "; line += pin_name; report_->reportLineString(line); - reportLine("period", check->period(), EarlyLate::early()); - reportLine("min period", -check->minPeriod(this), EarlyLate::early()); + reportLine("period", check.period(), EarlyLate::early()); + reportLine("min period", -check.minPeriod(this), EarlyLate::early()); reportDashLine(); - reportSlack(check->slack(this)); + reportSlack(check.slack(this)); } //////////////////////////////////////////////////////////////// void -ReportPath::reportCheck(const MaxSkewCheck *check, - bool verbose) const +ReportPath::reportChecks(const MaxSkewCheckSeq &checks, + bool verbose) const { - if (verbose) { - reportVerbose(check); - reportBlankLine(); - } - else { - reportMaxSkewHeaderShort(); - reportShort(check); - } - reportBlankLine(); -} - -void -ReportPath::reportChecks(const MaxSkewCheckSeq *checks, - bool verbose) const -{ - if (!checks->empty()) { + if (!checks.empty()) { if (verbose) { - for (const MaxSkewCheck *check : *checks) - reportVerbose(check); + for (const MaxSkewCheck &check : checks) + reportVerbose(check); } else { reportMaxSkewHeaderShort(); - for (const MaxSkewCheck *check : *checks) - reportShort(check); + for (const MaxSkewCheck &check : checks) + reportShort(check); } reportBlankLine(); } @@ -1578,34 +1560,34 @@ ReportPath::reportMaxSkewHeaderShort() const } void -ReportPath::reportShort(const MaxSkewCheck *check) const +ReportPath::reportShort(const MaxSkewCheck &check) const { string line; - Pin *clk_pin = check->clkPin(this); + Pin *clk_pin = check.clkPin(this); const char *clk_pin_name = network_->pathName(clk_pin); - TimingArc *check_arc = check->checkArc(); + TimingArc *check_arc = check.checkArc(); auto what = stdstrPrint("%s (%s->%s)", - clk_pin_name, - check_arc->fromEdge()->to_string().c_str(), - check_arc->toEdge()->to_string().c_str()); + clk_pin_name, + check_arc->fromEdge()->to_string().c_str(), + check_arc->toEdge()->to_string().c_str()); reportDescription(what.c_str(), line); const EarlyLate *early_late = EarlyLate::early(); - reportSpaceFieldDelay(check->maxSkew(this), early_late, line); - reportSpaceFieldDelay(check->skew(), early_late, line); - reportSpaceSlack(check->slack(this), line); + reportSpaceFieldDelay(check.maxSkew(this), early_late, line); + reportSpaceFieldDelay(check.skew(), early_late, line); + reportSpaceSlack(check.slack(this), line); report_->reportLineString(line); } void -ReportPath::reportVerbose(const MaxSkewCheck *check) const +ReportPath::reportVerbose(const MaxSkewCheck &check) const { string line; - const char *clk_pin_name = cmd_network_->pathName(check->clkPin(this)); + const char *clk_pin_name = cmd_network_->pathName(check.clkPin(this)); line += "Constrained Pin: "; line += clk_pin_name; report_->reportLineString(line); - const char *ref_pin_name = cmd_network_->pathName(check->refPin(this)); + const char *ref_pin_name = cmd_network_->pathName(check.refPin(this)); line = "Reference Pin: "; line += ref_pin_name; report_->reportLineString(line); @@ -1615,20 +1597,20 @@ ReportPath::reportVerbose(const MaxSkewCheck *check) const reportBlankLine(); reportPathHeader(); - reportSkewClkPath("reference pin arrival time", check->refPath()); - reportSkewClkPath("constrained pin arrival time", check->clkPath()); + reportSkewClkPath("reference pin arrival time", check.refPath()); + reportSkewClkPath("constrained pin arrival time", check.clkPath()); reportDashLine(); - reportLine("allowable skew", check->maxSkew(this), EarlyLate::early()); - reportLine("actual skew", check->skew(), EarlyLate::late()); + reportLine("allowable skew", check.maxSkew(this), EarlyLate::early()); + reportLine("actual skew", check.skew(), EarlyLate::late()); reportDashLine(); - reportSlack(check->slack(this)); + reportSlack(check.slack(this)); } // Based on reportTgtClk. void ReportPath::reportSkewClkPath(const char *arrival_msg, - const Path *clk_path) const + const Path *clk_path) const { const ClockEdge *clk_edge = clk_path->clkEdge(this); const Clock *clk = clk_edge->clock(); @@ -1639,21 +1621,22 @@ ReportPath::reportSkewClkPath(const char *arrival_msg, float clk_time = clk_edge->time(); const Arrival &clk_arrival = search_->clkPathArrival(clk_path); Arrival clk_delay = clk_arrival - clk_time; - PathAnalysisPt *path_ap = clk_path->pathAnalysisPt(this); - const MinMax *min_max = path_ap->pathMinMax(); + const MinMax *min_max = clk_path->minMax(this); Vertex *clk_vertex = clk_path->vertex(this); reportClkLine(clk, clk_name.c_str(), clk_end_rf, clk_time, min_max); bool is_prop = isPropagated(clk_path); if (is_prop && reportClkPath()) { + const Mode *mode = clk_path->mode(this); + const Sdc *sdc = mode->sdc(); const EarlyLate *early_late = TimingRole::skew()->tgtClkEarlyLate(); - if (reportGenClkSrcPath(clk_path, clk, clk_rf, min_max, early_late)) - reportGenClkSrcAndPath(clk_path, clk, clk_rf, early_late, path_ap, - 0.0, 0.0, false); + if (reportGenClkSrcPath(clk_path, clk, clk_rf, min_max, early_late, sdc)) + reportGenClkSrcAndPath(clk_path, clk, clk_rf, early_late, 0.0, 0.0, + false, mode); else { Arrival insertion, latency; PathEnd::checkTgtClkDelay(clk_path, clk_edge, TimingRole::skew(), this, - insertion, latency); + insertion, latency); reportClkSrcLatency(insertion, clk_time, early_late); PathExpanded clk_expanded(clk_path, this); reportPath1(clk_path, clk_expanded, false, 0.0); @@ -1662,7 +1645,7 @@ ReportPath::reportSkewClkPath(const char *arrival_msg, else { reportLine(clkNetworkDelayIdealProp(is_prop), clk_delay, clk_arrival, early_late); reportLine(descriptionField(clk_vertex).c_str(), clk_arrival, - early_late, clk_end_rf); + early_late, clk_end_rf); } reportLine(arrival_msg, search_->clkPathArrival(clk_path), early_late); reportBlankLine(); @@ -1688,10 +1671,10 @@ ReportPath::reportLimitShortHeader(const ReportField *field) const void ReportPath::reportLimitShort(const ReportField *field, - Pin *pin, - float value, - float limit, - float slack) const + const Pin *pin, + float value, + float limit, + float slack) const { string line; const char *pin_name = cmd_network_->pathName(pin); @@ -1710,12 +1693,12 @@ ReportPath::reportLimitShort(const ReportField *field, void ReportPath::reportLimitVerbose(const ReportField *field, - Pin *pin, - const RiseFall *rf, - float value, - float limit, - float slack, - const Corner *corner, + const Pin *pin, + const RiseFall *rf, + float value, + float limit, + float slack, + const Scene *scene, const MinMax *min_max) const { string line; @@ -1726,10 +1709,10 @@ ReportPath::reportLimitVerbose(const ReportField *field, line += rf->shortName(); else line += ' '; - // Don't report corner if the default corner is the only corner. - if (corner && corners_->count() > 1) { + // Don't report scene if the default scene is the only scene. + if (scene && multiScene()) { line += " (corner "; - line += corner->name(); + line += scene->name(); line += ")"; } report_->reportLineString(line); @@ -1763,9 +1746,10 @@ ReportPath::reportLimitVerbose(const ReportField *field, void ReportPath::reportStartpoint(const PathEnd *end, - const PathExpanded &expanded) const + const PathExpanded &expanded) const { const Path *path = end->path(); + const Sdc *sdc = path->sdc(this); const Path *start = expanded.startPath(); const TimingArc *prev_arc = expanded.startPrevArc(); const Edge *prev_edge = start->prevEdge(this); @@ -1780,7 +1764,7 @@ ReportPath::reportStartpoint(const PathEnd *end, } else if (network_->isTopLevelPort(pin)) { if (clk - && clk != sdc_->defaultArrivalClock()) { + && clk != sdc->defaultArrivalClock()) { const char *clk_name = clk->name(); // Pin direction is "input" even for bidirects. auto reason = stdstrPrint("input port clocked by %s", clk_name); @@ -1796,7 +1780,7 @@ ReportPath::reportStartpoint(const PathEnd *end, const RiseFall *clk_rf = clk_edge->transition(); const Path *clk_path = expanded.clkPath(); bool clk_inverted = clk_path - && clk_rf != clk_path->transition(this); + && clk_rf != clk_path->transition(this); string clk_name = clkName(clk, clk_inverted); const char *reg_desc = edgeRegLatchDesc(prev_edge, prev_arc); auto reason = stdstrPrint("%s clocked by %s", reg_desc, clk_name.c_str()); @@ -1810,13 +1794,13 @@ ReportPath::reportStartpoint(const PathEnd *end, else if (network_->isLeaf(pin)) { if (clk_edge) { Clock *clk = clk_edge->clock(); - if (clk != sdc_->defaultArrivalClock()) { - const char *clk_name = clk->name(); - auto reason = stdstrPrint("internal path startpoint clocked by %s", clk_name); - reportStartpoint(pin_name, reason); + if (clk != sdc->defaultArrivalClock()) { + const char *clk_name = clk->name(); + auto reason = stdstrPrint("internal path startpoint clocked by %s", clk_name); + reportStartpoint(pin_name, reason); } else - reportStartpoint(pin_name, "internal path startpoint"); + reportStartpoint(pin_name, "internal path startpoint"); } else reportStartpoint(pin_name, "internal pin"); @@ -1836,23 +1820,23 @@ ReportPath::pathFromClkPin(const PathExpanded &expanded) const bool ReportPath::pathFromClkPin(const Path *path, - const Pin *start_pin) const + const Pin *start_pin) const { const Clock *clk = path->clock(search_); return clk - && clk->leafPins().hasKey(const_cast(start_pin)); + && clk->leafPins().contains(const_cast(start_pin)); } void ReportPath::reportStartpoint(const char *start, - const string reason) const + const string reason) const { reportStartEndPoint(start, reason, "Startpoint"); } void ReportPath::reportUnclockedEndpoint(const PathEnd *end, - const char *default_reason) const + const char *default_reason) const { Vertex *vertex = end->vertex(this); Pin *pin = vertex->pin(); @@ -1865,25 +1849,25 @@ ReportPath::reportUnclockedEndpoint(const PathEnd *end, while (edge_iter.hasNext()) { Edge *edge = edge_iter.next(); if (edge->role()->genericRole() == TimingRole::setup()) { - Vertex *clk_vertex = edge->from(graph_); - VertexOutEdgeIterator clk_edge_iter(clk_vertex, graph_); - while (clk_edge_iter.hasNext()) { - Edge *clk_edge = clk_edge_iter.next(); - if (clk_edge->role() == TimingRole::regClkToQ()) { - Instance *inst = network_->instance(pin); - const char *inst_name = cmd_network_->pathName(inst); - const char *reason = regDesc(clk_edge->timingArcSet()->isRisingFallingEdge()); - reportEndpoint(inst_name, reason); - return; - } - if (clk_edge->role() == TimingRole::latchEnToQ()) { - Instance *inst = network_->instance(pin); - const char *inst_name = cmd_network_->pathName(inst); - const char *reason = latchDesc(clk_edge->timingArcSet()->isRisingFallingEdge()); - reportEndpoint(inst_name, reason); - return; - } - } + Vertex *clk_vertex = edge->from(graph_); + VertexOutEdgeIterator clk_edge_iter(clk_vertex, graph_); + while (clk_edge_iter.hasNext()) { + Edge *clk_edge = clk_edge_iter.next(); + if (clk_edge->role() == TimingRole::regClkToQ()) { + Instance *inst = network_->instance(pin); + const char *inst_name = cmd_network_->pathName(inst); + const char *reason = regDesc(clk_edge->timingArcSet()->isRisingFallingEdge()); + reportEndpoint(inst_name, reason); + return; + } + if (clk_edge->role() == TimingRole::latchEnToQ()) { + Instance *inst = network_->instance(pin); + const char *inst_name = cmd_network_->pathName(inst); + const char *reason = latchDesc(clk_edge->timingArcSet()->isRisingFallingEdge()); + reportEndpoint(inst_name, reason); + return; + } + } } } reportEndpoint(cmd_network_->pathName(pin), default_reason); @@ -1894,15 +1878,15 @@ ReportPath::reportUnclockedEndpoint(const PathEnd *end, void ReportPath::reportEndpoint(const char *end, - const string reason) const + const string reason) const { reportStartEndPoint(end, reason, "Endpoint"); } void ReportPath::reportStartEndPoint(const char *pt, - string reason, - const char *key) const + string reason, + const char *key) const { string line; // Account for punctuation in the line. @@ -1947,9 +1931,15 @@ ReportPath::reportGroup(const PathEnd *end) const line += end->minMax(this)->to_string(); report_->reportLineString(line); - if (corners_->multiCorner()) { + if (modes_.size() > 1) { + line = "Mode: "; + line += end->path()->mode(this)->name(); + report_->reportLineString(line); + } + + if (multiScene()) { line = "Corner: "; - line += end->pathAnalysisPt(this)->corner()->name(); + line += end->path()->scene(this)->name(); report_->reportLineString(line); } } @@ -1974,7 +1964,7 @@ ReportPath::tgtClkName(const PathEnd *end) const string ReportPath::clkName(const Clock *clk, - bool inverted) const + bool inverted) const { string name = clk->name(); if (inverted) @@ -1997,37 +1987,37 @@ ReportPath::clkRegLatchDesc(const PathEnd *end) const TimingArcSet *arc_set = edge->timingArcSet(); const TimingRole *role = arc_set->role(); if (role == TimingRole::regClkToQ() - || role == TimingRole::latchEnToQ()) { + || role == TimingRole::latchEnToQ()) { const RiseFall *arc_rf = arc_set->isRisingFallingEdge(); clk_set = arc_set; if (arc_rf == check_clk_rf) - clk_rf_set = arc_set; + clk_rf_set = arc_set; } } if (clk_rf_set) return checkRegLatchDesc(clk_rf_set->role(), - clk_rf_set->isRisingFallingEdge()); + clk_rf_set->isRisingFallingEdge()); else if (clk_set) return checkRegLatchDesc(clk_set->role(), - clk_set->isRisingFallingEdge()); + clk_set->isRisingFallingEdge()); else return checkRegLatchDesc(TimingRole::regClkToQ(), check_clk_rf); } void ReportPath::reportSrcPathArrival(const PathEnd *end, - const PathExpanded &expanded) const + const PathExpanded &expanded) const { reportBlankLine(); reportSrcPath(end, expanded); reportLine("data arrival time", end->dataArrivalTimeOffset(this), - end->pathEarlyLate(this)); + end->pathEarlyLate(this)); reportBlankLine(); } void ReportPath::reportSrcPath(const PathEnd *end, - const PathExpanded &expanded) const + const PathExpanded &expanded) const { reportPathHeader(); float src_clk_offset = end->sourceClkOffset(this); @@ -2035,30 +2025,32 @@ ReportPath::reportSrcPath(const PathEnd *end, Arrival src_clk_latency = end->sourceClkLatency(this); const Path *path = end->path(); reportSrcClkAndPath(path, expanded, src_clk_offset, src_clk_insertion, - src_clk_latency, end->isPathDelay()); + src_clk_latency, end->isPathDelay()); } void ReportPath::reportSrcClkAndPath(const Path *path, - const PathExpanded &expanded, - float time_offset, - Arrival clk_insertion, - Arrival clk_latency, - bool is_path_delay) const + const PathExpanded &expanded, + float time_offset, + Arrival clk_insertion, + Arrival clk_latency, + bool is_path_delay) const { const ClockEdge *clk_edge = path->clkEdge(this); + const Mode *mode = path->mode(this); + const Sdc *sdc = mode->sdc(); const MinMax *min_max = path->minMax(this); if (clk_edge) { Clock *clk = clk_edge->clock(); const RiseFall *clk_rf = clk_edge->transition(); float clk_time = clk_edge->time() + time_offset; - if (clk == sdc_->defaultArrivalClock()) { + if (clk == sdc->defaultArrivalClock()) { if (!is_path_delay) { - float clk_end_time = clk_time + time_offset; - const EarlyLate *early_late = min_max; - reportLine("clock (input port clock) (rise edge)", - clk_end_time, clk_end_time, early_late); - reportLine(clkNetworkDelayIdealProp(false), 0.0, clk_end_time, early_late); + float clk_end_time = clk_time + time_offset; + const EarlyLate *early_late = min_max; + reportLine("clock (input port clock) (rise edge)", + clk_end_time, clk_end_time, early_late); + reportLine(clkNetworkDelayIdealProp(false), 0.0, clk_end_time, early_late); } reportPath1(path, expanded, false, time_offset); } @@ -2069,91 +2061,89 @@ ReportPath::reportSrcClkAndPath(const Path *path, const Path *clk_path = expanded.clkPath(); const RiseFall *clk_end_rf; if (clk_path) { - clk_end_time = search_->clkPathArrival(clk_path) + time_offset; - clk_delay = clk_end_time - clk_time; - clk_end_rf = clk_path->transition(this); + clk_end_time = search_->clkPathArrival(clk_path) + time_offset; + clk_delay = clk_end_time - clk_time; + clk_end_rf = clk_path->transition(this); } else { - // Path from input port or clk used as data. - clk_end_rf = clk_rf; - clk_delay = clk_insertion + clk_latency; - clk_end_time = clk_time + clk_delay; + // Path from input port or clk used as data. + clk_end_rf = clk_rf; + clk_delay = clk_insertion + clk_latency; + clk_end_time = clk_time + clk_delay; - const Path *first_path = expanded.startPath(); - const InputDelay *input_delay = pathInputDelay(first_path); - if (input_delay) { - path_from_input = true; - const Pin *ref_pin = input_delay->refPin(); - if (ref_pin && clk->isPropagated()) { - Path ref_path; - pathInputDelayRefPath(first_path, input_delay, ref_path); - if (!ref_path.isNull()) { - const Arrival &ref_end_time = ref_path.arrival(); - clk_delay = ref_end_time - clk_time; - clk_end_time = ref_end_time + time_offset; - input_has_ref_path = true; - } - } - } + const Path *first_path = expanded.startPath(); + const InputDelay *input_delay = pathInputDelay(first_path); + if (input_delay) { + path_from_input = true; + const Pin *ref_pin = input_delay->refPin(); + if (ref_pin && clk->isPropagated()) { + Path ref_path; + pathInputDelayRefPath(first_path, input_delay, ref_path); + if (!ref_path.isNull()) { + const Arrival &ref_end_time = ref_path.arrival(); + clk_delay = ref_end_time - clk_time; + clk_end_time = ref_end_time + time_offset; + input_has_ref_path = true; + } + } + } } string clk_name = clkName(clk, clk_rf != clk_end_rf); bool clk_used_as_data = pathFromClkPin(expanded); bool is_prop = isPropagated(path); const EarlyLate *early_late = min_max; - if (reportGenClkSrcPath(clk_path, clk, clk_rf, min_max, early_late) - && !(path_from_input && !input_has_ref_path)) { - reportClkLine(clk, clk_name.c_str(), clk_end_rf, clk_time, - min_max); - const PathAnalysisPt *path_ap = path->pathAnalysisPt(this); - reportGenClkSrcAndPath(path, clk, clk_rf, early_late, path_ap, - time_offset, time_offset, clk_used_as_data); + if (reportGenClkSrcPath(clk_path, clk, clk_rf, min_max, early_late, sdc) + && !(path_from_input && !input_has_ref_path)) { + reportClkLine(clk, clk_name.c_str(), clk_end_rf, clk_time, min_max); + reportGenClkSrcAndPath(path, clk, clk_rf, early_late, time_offset, + time_offset, clk_used_as_data, mode); } else if (clk_used_as_data - && pathFromGenPropClk(path, path->minMax(this))) { - reportClkLine(clk, clk_name.c_str(), clk_end_rf, clk_time, min_max); - const ClkInfo *clk_info = path->tag(search_)->clkInfo(); - if (clk_info->isPropagated()) - reportClkSrcLatency(clk_insertion, clk_time, early_late); - reportPath1(path, expanded, true, time_offset); + && pathFromGenPropClk(path, path->minMax(this))) { + reportClkLine(clk, clk_name.c_str(), clk_end_rf, clk_time, min_max); + const ClkInfo *clk_info = path->tag(search_)->clkInfo(); + if (clk_info->isPropagated()) + reportClkSrcLatency(clk_insertion, clk_time, early_late); + reportPath1(path, expanded, true, time_offset); } else if (is_prop - && reportClkPath() - && !(path_from_input && !input_has_ref_path)) { - reportClkLine(clk, clk_name.c_str(), clk_end_rf, clk_time, early_late); - reportClkSrcLatency(clk_insertion, clk_time, early_late); - reportPath1(path, expanded, false, time_offset); + && reportClkPath() + && !(path_from_input && !input_has_ref_path)) { + reportClkLine(clk, clk_name.c_str(), clk_end_rf, clk_time, early_late); + reportClkSrcLatency(clk_insertion, clk_time, early_late); + reportPath1(path, expanded, false, time_offset); } else if (clk_used_as_data) { - reportClkLine(clk, clk_name.c_str(), clk_end_rf, clk_time, early_late); - if (delayGreater(clk_insertion, 0.0, this)) - reportClkSrcLatency(clk_insertion, clk_time, early_late); - if (reportClkPath()) - reportPath1(path, expanded, true, time_offset); - else { - Arrival clk_arrival = clk_end_time; - Arrival end_arrival = path->arrival() + time_offset; - Delay clk_delay = end_arrival - clk_arrival; - reportLine("clock network delay", clk_delay, - end_arrival, early_late); - Vertex *end_vertex = path->vertex(this); - reportLine(descriptionField(end_vertex).c_str(), - end_arrival, early_late, clk_end_rf); - } + reportClkLine(clk, clk_name.c_str(), clk_end_rf, clk_time, early_late); + if (delayGreater(clk_insertion, 0.0, this)) + reportClkSrcLatency(clk_insertion, clk_time, early_late); + if (reportClkPath()) + reportPath1(path, expanded, true, time_offset); + else { + Arrival clk_arrival = clk_end_time; + Arrival end_arrival = path->arrival() + time_offset; + Delay clk_delay = end_arrival - clk_arrival; + reportLine("clock network delay", clk_delay, + end_arrival, early_late); + Vertex *end_vertex = path->vertex(this); + reportLine(descriptionField(end_vertex).c_str(), + end_arrival, early_late, clk_end_rf); + } } else { - if (is_path_delay) { - if (delayGreater(clk_delay, 0.0, this)) - reportLine(clkNetworkDelayIdealProp(is_prop), clk_delay, - clk_end_time, early_late); - } - else { - reportClkLine(clk, clk_name.c_str(), clk_end_rf, clk_time, min_max); - Arrival clk_arrival = clk_end_time; - reportLine(clkNetworkDelayIdealProp(is_prop), clk_delay, - clk_arrival, early_late); - } - reportPath1(path, expanded, false, time_offset); + if (is_path_delay) { + if (delayGreater(clk_delay, 0.0, this)) + reportLine(clkNetworkDelayIdealProp(is_prop), clk_delay, + clk_end_time, early_late); + } + else { + reportClkLine(clk, clk_name.c_str(), clk_end_rf, clk_time, min_max); + Arrival clk_arrival = clk_end_time; + reportLine(clkNetworkDelayIdealProp(is_prop), clk_delay, + clk_arrival, early_late); + } + reportPath1(path, expanded, false, time_offset); } } } @@ -2169,7 +2159,7 @@ ReportPath::reportTgtClk(const PathEnd *end) const void ReportPath::reportTgtClk(const PathEnd *end, - float prev_time) const + float prev_time) const { const Clock *clk = end->targetClk(this); const Path *clk_path = end->targetClkPath(); @@ -2178,8 +2168,8 @@ ReportPath::reportTgtClk(const PathEnd *end, void ReportPath::reportTgtClk(const PathEnd *end, - float prev_time, - bool is_prop) const + float prev_time, + bool is_prop) const { float src_offset = end->sourceClkOffset(this); reportTgtClk(end, prev_time, src_offset, is_prop); @@ -2187,9 +2177,9 @@ ReportPath::reportTgtClk(const PathEnd *end, void ReportPath::reportTgtClk(const PathEnd *end, - float prev_time, - float src_offset, - bool is_prop) const + float prev_time, + float src_offset, + bool is_prop) const { const ClockEdge *clk_edge = end->targetClkEdge(this); Clock *clk = clk_edge->clock(); @@ -2202,8 +2192,7 @@ ReportPath::reportTgtClk(const PathEnd *end, + src_offset; Arrival clk_delay = end->targetClkDelay(this); Arrival clk_arrival = clk_time + clk_delay; - PathAnalysisPt *path_ap = end->pathAnalysisPt(this)->tgtClkAnalysisPt(); - const MinMax *min_max = path_ap->pathMinMax(); + const MinMax *min_max = end->path()->tgtClkMinMax(this); const Path *clk_path = end->targetClkPath(); reportClkLine(clk, clk_name.c_str(), clk_end_rf, prev_time, clk_time, min_max); const TimingRole *check_role = end->checkRole(this); @@ -2212,27 +2201,28 @@ ReportPath::reportTgtClk(const PathEnd *end, + end->targetClkOffset(this) + end->targetClkMcpAdjustment(this); const EarlyLate *early_late = check_role->tgtClkEarlyLate(); - if (reportGenClkSrcPath(clk_path, clk, clk_rf, min_max, early_late)) { + const Mode *mode = end->path()->mode(this); + const Sdc *sdc = mode->sdc(); + if (reportGenClkSrcPath(clk_path, clk, clk_rf, min_max, early_late, sdc)) { float insertion_offset = - clk_path ? tgtClkInsertionOffet(clk_path, early_late, path_ap) : 0.0; - reportGenClkSrcAndPath(clk_path, clk, clk_rf, early_late, path_ap, - time_offset, time_offset + insertion_offset, false); + clk_path ? tgtClkInsertionOffet(clk_path, early_late) : 0.0; + reportGenClkSrcAndPath(clk_path, clk, clk_rf, early_late, time_offset, + time_offset + insertion_offset, false, mode); } else { Arrival insertion = end->targetClkInsertionDelay(this); if (clk_path) { - reportClkSrcLatency(insertion, clk_time, early_late); - PathExpanded clk_expanded(clk_path, this); - float insertion_offset = tgtClkInsertionOffet(clk_path, early_late, - path_ap); - reportPath6(clk_path, clk_expanded, 0, is_prop, reportClkPath(), - delay_zero, time_offset + insertion_offset); + reportClkSrcLatency(insertion, clk_time, early_late); + PathExpanded clk_expanded(clk_path, this); + float insertion_offset = tgtClkInsertionOffet(clk_path, early_late); + reportPath6(clk_path, clk_expanded, 0, is_prop, reportClkPath(), + delay_zero, time_offset + insertion_offset); } else { - // Output departure. - Arrival clk_arrival = clk_time + clk_delay; - reportLine(clkNetworkDelayIdealProp(clk->isPropagated()), - clk_delay, clk_arrival, min_max); + // Output departure. + Arrival clk_arrival = clk_time + clk_delay; + reportLine(clkNetworkDelayIdealProp(clk->isPropagated()), + clk_delay, clk_arrival, min_max); } } reportClkUncertainty(end, clk_arrival); @@ -2246,49 +2236,48 @@ ReportPath::reportTgtClk(const PathEnd *end, if (clk_path) { Vertex *clk_vertex = clk_path->vertex(this); reportLine(descriptionField(clk_vertex).c_str(), - prev_time - + end->targetClkArrival(this) - + end->sourceClkOffset(this), - min_max, clk_end_rf); + prev_time + + end->targetClkArrival(this) + + end->sourceClkOffset(this), + min_max, clk_end_rf); } } } float ReportPath::tgtClkInsertionOffet(const Path *clk_path, - const EarlyLate *early_late, - const PathAnalysisPt *path_ap) const + const EarlyLate *early_late) const { const ClkInfo *clk_info = clk_path->clkInfo(this); const Pin *src_pin = clk_info->clkSrc(); const ClockEdge *clk_edge = clk_info->clkEdge(); const Clock *clk = clk_edge->clock(); const RiseFall *clk_rf = clk_edge->transition(); - const MinMax *min_max = path_ap->pathMinMax(); + const MinMax *min_max = clk_path->minMax(this); + const Mode *mode = clk_path->mode(this); Arrival path_insertion = search_->clockInsertion(clk, src_pin, clk_rf, - min_max, min_max, - path_ap); + min_max, min_max, mode); Arrival tgt_insertion = search_->clockInsertion(clk, src_pin, clk_rf, - min_max, early_late, - path_ap); + min_max, early_late, mode); return delayAsFloat(tgt_insertion - path_insertion); } bool ReportPath::pathFromGenPropClk(const Path *clk_path, - const EarlyLate *early_late) const + const EarlyLate *early_late) const { const ClkInfo *clk_info = clk_path->tag(search_)->clkInfo(); const ClockEdge *clk_edge = clk_info->clkEdge(); if (clk_edge) { + const Sdc *sdc = clk_path->sdc(this); const Clock *clk = clk_edge->clock(); float insertion; bool exists; - sdc_->clockInsertion(clk, clk_info->clkSrc(), - clk_edge->transition(), - clk_path->minMax(this), - early_late, - insertion, exists); + sdc->clockInsertion(clk, clk_info->clkSrc(), + clk_edge->transition(), + clk_path->minMax(this), + early_late, + insertion, exists); return !exists && clk->isGeneratedWithPropagatedMaster(); } @@ -2298,36 +2287,37 @@ ReportPath::pathFromGenPropClk(const Path *clk_path, bool ReportPath::isGenPropClk(const Clock *clk, - const RiseFall *clk_rf, - const MinMax *min_max, - const EarlyLate *early_late) const + const RiseFall *clk_rf, + const MinMax *min_max, + const EarlyLate *early_late, + const Sdc *sdc) const { float insertion; bool exists; - sdc_->clockInsertion(clk, clk->srcPin(), clk_rf, - min_max, early_late, - insertion, exists); + sdc->clockInsertion(clk, clk->srcPin(), clk_rf, + min_max, early_late, + insertion, exists); return !exists && clk->isGeneratedWithPropagatedMaster(); } void ReportPath::reportClkLine(const Clock *clk, - const char *clk_name, - const RiseFall *clk_rf, - Arrival clk_time, - const MinMax *min_max) const + const char *clk_name, + const RiseFall *clk_rf, + Arrival clk_time, + const MinMax *min_max) const { reportClkLine(clk, clk_name, clk_rf, 0.0, clk_time, min_max); } void ReportPath::reportClkLine(const Clock *clk, - const char *clk_name, - const RiseFall *clk_rf, - Arrival prev_time, - Arrival clk_time, - const MinMax *min_max) const + const char *clk_name, + const RiseFall *clk_rf, + Arrival prev_time, + Arrival clk_time, + const MinMax *min_max) const { const char *rise_fall = asRiseFall(clk_rf); auto clk_msg = stdstrPrint("clock %s (%s edge)", clk_name, rise_fall); @@ -2342,60 +2332,60 @@ ReportPath::reportClkLine(const Clock *clk, bool ReportPath::reportGenClkSrcPath(const Path *clk_path, - const Clock *clk, - const RiseFall *clk_rf, - const MinMax *min_max, - const EarlyLate *early_late) const + const Clock *clk, + const RiseFall *clk_rf, + const MinMax *min_max, + const EarlyLate *early_late, + const Sdc *sdc) const { bool from_gen_prop_clk = clk_path ? pathFromGenPropClk(clk_path, early_late) - : isGenPropClk(clk, clk_rf, min_max, early_late); + : isGenPropClk(clk, clk_rf, min_max, early_late, sdc); return from_gen_prop_clk && format_ == ReportPathFormat::full_clock_expanded; } void ReportPath::reportGenClkSrcAndPath(const Path *path, - const Clock *clk, - const RiseFall *clk_rf, - const EarlyLate *early_late, - const PathAnalysisPt *path_ap, - float time_offset, - float path_time_offset, - bool clk_used_as_data) const + const Clock *clk, + const RiseFall *clk_rf, + const EarlyLate *early_late, + float time_offset, + float path_time_offset, + bool clk_used_as_data, + const Mode *mode) const { const Pin *clk_pin = path ? path->clkInfo(search_)->clkSrc() : clk->defaultPin(); float gclk_time = clk->edge(clk_rf)->time() + time_offset; bool skip_first_path = reportGenClkSrcPath1(clk, clk_pin, clk_rf, - early_late, path_ap, gclk_time, - time_offset, clk_used_as_data); + early_late, gclk_time, + time_offset, clk_used_as_data, + mode); if (path) { PathExpanded expanded(path, this); reportPath2(path, expanded, skip_first_path, clk_used_as_data, - path_time_offset); + path_time_offset); } } bool ReportPath::reportGenClkSrcPath1(const Clock *clk, - const Pin *clk_pin, - const RiseFall *clk_rf, - const EarlyLate *early_late, - const PathAnalysisPt *path_ap, - float gclk_time, - float time_offset, - bool clk_used_as_data) const + const Pin *clk_pin, + const RiseFall *clk_rf, + const EarlyLate *early_late, + float gclk_time, + float time_offset, + bool clk_used_as_data, + const Mode *mode) const { - PathAnalysisPt *insert_ap = path_ap->insertionAnalysisPt(early_late); - const MinMax *min_max = path_ap->pathMinMax(); - const Path *src_path = search_->genclks()->srcPath(clk, clk_pin, - clk_rf, insert_ap); + const Path *src_path = mode->genclks()->srcPath(clk, clk_pin, clk_rf, early_late); if (src_path) { const ClkInfo *src_clk_info = src_path->clkInfo(this); const ClockEdge *src_clk_edge = src_clk_info->clkEdge(); const Clock *src_clk = src_clk_info->clock(); + const MinMax *min_max = src_path->minMax(this); if (src_clk) { bool skip_first_path = false; const RiseFall *src_clk_rf = src_clk_edge->transition(); @@ -2403,15 +2393,17 @@ ReportPath::reportGenClkSrcPath1(const Clock *clk, if (src_clk->isGeneratedWithPropagatedMaster() && src_clk_info->isPropagated()) { skip_first_path = reportGenClkSrcPath1(src_clk, src_clk_pin, - src_clk_rf, early_late, path_ap, + src_clk_rf, early_late, gclk_time, time_offset, - clk_used_as_data); + clk_used_as_data, + mode); } else { + const Mode *mode = src_path->mode(this); const Arrival insertion = search_->clockInsertion(src_clk, src_clk_pin, src_clk_rf, - path_ap->pathMinMax(), - early_late, path_ap); + min_max, + early_late, mode); reportClkSrcLatency(insertion, gclk_time, early_late); } PathExpanded src_expanded(src_path, this); @@ -2426,35 +2418,35 @@ ReportPath::reportGenClkSrcPath1(const Clock *clk, if (clk->isPropagated()) reportClkSrcLatency(0.0, gclk_time, early_late); else if (!clk_used_as_data) - reportLine("clock network delay (ideal)", 0.0, gclk_time, min_max); + reportLine("clock network delay (ideal)", 0.0, gclk_time, MinMax::max()); } return src_path != nullptr; } void ReportPath::reportClkSrcLatency(Arrival insertion, - float clk_time, - const EarlyLate *early_late) const + float clk_time, + const EarlyLate *early_late) const { reportLine("clock source latency", insertion, clk_time + insertion, early_late); } void ReportPath::reportPathLine(const Path *path, - Arrival incr, - Arrival time, - const char *line_case) const + Arrival incr, + Arrival time, + const char *line_case) const { Vertex *vertex = path->vertex(this); Pin *pin = vertex->pin(); const string what = descriptionField(vertex); const RiseFall *rf = path->transition(this); bool is_driver = network_->isDriver(pin); - PathAnalysisPt *path_ap = path->pathAnalysisPt(this); - const EarlyLate *early_late = path_ap->pathMinMax(); - DcalcAnalysisPt *dcalc_ap = path_ap->dcalcAnalysisPt(); - DcalcAPIndex ap_index = dcalc_ap->index(); - Slew slew = graph_->slew(vertex, rf, ap_index); + const EarlyLate *early_late = path->minMax(this); + const Scene *scene = path->scene(this); + const MinMax *min_max = path->minMax(this); + DcalcAPIndex slew_index = path->dcalcAnalysisPtIndex(this); + Slew slew = graph_->slew(vertex, rf, slew_index); float cap = field_blank_; Instance *inst = network_->instance(pin); string src_attr = ""; @@ -2462,15 +2454,15 @@ ReportPath::reportPathLine(const Path *path, src_attr = network_->getAttribute(inst, "src"); // Don't show capacitance field for input pins. if (is_driver && field_capacitance_->enabled()) - cap = graph_delay_calc_->loadCap(pin, rf, dcalc_ap); + cap = graph_delay_calc_->loadCap(pin, rf, scene, min_max); reportLine(what.c_str(), cap, slew, field_blank_, - incr, time, false, early_late, rf, src_attr, - line_case); + incr, time, false, early_late, rf, src_attr, + line_case); } void ReportPath::reportRequired(const PathEnd *end, - string margin_msg) const + string margin_msg) const { Required req_time = end->requiredTimeOffset(this); const EarlyLate *early_late = end->clkEarlyLate(this); @@ -2493,7 +2485,7 @@ ReportPath::reportSlack(const PathEnd *end) const { const EarlyLate *early_late = end->pathEarlyLate(this); reportLine("data required time", end->requiredTimeOffset(this), - early_late->opposite()); + early_late->opposite()); reportLineNegative("data arrival time", end->dataArrivalTimeOffset(this), early_late); reportDashLine(); reportSlack(end->slack(this)); @@ -2511,7 +2503,7 @@ ReportPath::reportSlack(Slack slack) const void ReportPath::reportSpaceSlack(const PathEnd *end, - string &result) const + string &result) const { Slack slack = end->slack(this); reportSpaceSlack(slack, result); @@ -2519,7 +2511,7 @@ ReportPath::reportSpaceSlack(const PathEnd *end, void ReportPath::reportSpaceSlack(Slack slack, - string &result) const + string &result) const { const EarlyLate *early_late = EarlyLate::early(); reportSpaceFieldDelay(slack, early_late, result); @@ -2530,19 +2522,19 @@ ReportPath::reportSpaceSlack(Slack slack, void ReportPath::reportCommonClkPessimism(const PathEnd *end, - Arrival &clk_arrival) const + Arrival &clk_arrival) const { if (variables_->crprEnabled()) { Crpr pessimism = end->checkCrpr(this); clk_arrival += pessimism; reportLine("clock reconvergence pessimism", pessimism, clk_arrival, - end->clkEarlyLate(this)); + end->clkEarlyLate(this)); } } void ReportPath::reportClkUncertainty(const PathEnd *end, - Arrival &clk_arrival) const + Arrival &clk_arrival) const { const EarlyLate *early_late = end->clkEarlyLate(this); float uncertainty = end->targetNonInterClkUncertainty(this); @@ -2560,7 +2552,7 @@ ReportPath::reportClkUncertainty(const PathEnd *end, void ReportPath::reportPath(const PathEnd *end, - const PathExpanded &expanded) const + const PathExpanded &expanded) const { reportPathHeader(); // Source clk offset for path delays removes clock phase time. @@ -2602,9 +2594,9 @@ ReportPath::reportPathFull(const Path *path) const // Main entry point for reporting a path. void ReportPath::reportPath1(const Path *path, - const PathExpanded &expanded, - bool clk_used_as_data, - float time_offset) const + const PathExpanded &expanded, + bool clk_used_as_data, + float time_offset) const { reportPath2(path, expanded, false, clk_used_as_data, time_offset); } @@ -2612,38 +2604,38 @@ ReportPath::reportPath1(const Path *path, // Alternate entry point with skip_first_path arg. void ReportPath::reportPath2(const Path *path, - const PathExpanded &expanded, - bool skip_first_path, - bool clk_used_as_data, - float time_offset) const + const PathExpanded &expanded, + bool skip_first_path, + bool clk_used_as_data, + float time_offset) const { bool clk_is_propagated = path->clkInfo(search_)->isPropagated(); bool report_clk_path = (reportClkPath() && clk_is_propagated) || clk_used_as_data; bool propagated_clk = clk_is_propagated || clk_used_as_data; reportPath4(path, expanded, skip_first_path, propagated_clk, - report_clk_path, time_offset); + report_clk_path, time_offset); } // Alternate entry point with report_clk_path arg. void ReportPath::reportPath3(const Path *path, - const PathExpanded &expanded, - bool report_clk_path, - float time_offset) const + const PathExpanded &expanded, + bool report_clk_path, + float time_offset) const { bool propagated_clk = path->clkInfo(search_)->isPropagated(); reportPath4(path, expanded, false, propagated_clk, - report_clk_path, time_offset); + report_clk_path, time_offset); } void ReportPath::reportPath4(const Path *path, - const PathExpanded &expanded, - bool skip_first_path, - bool propagated_clk, - bool report_clk_path, - float time_offset) const + const PathExpanded &expanded, + bool skip_first_path, + bool propagated_clk, + bool report_clk_path, + float time_offset) const { const Path *d_path, *q_path; Edge *d_q_edge; @@ -2657,35 +2649,35 @@ ReportPath::reportPath4(const Path *path, const EarlyLate *early_late = latch_enable_path->minMax(this); latch_enable_time = search_->clkPathArrival(latch_enable_path); if (report_clk_path) { - PathExpanded enable_expanded(latch_enable_path, this); - // Report the path to the latch enable. - reportPath5(latch_enable_path, enable_expanded, skip_first_path, - propagated_clk, report_clk_path, time_offset); + PathExpanded enable_expanded(latch_enable_path, this); + // Report the path to the latch enable. + reportPath5(latch_enable_path, enable_expanded, skip_first_path, + propagated_clk, report_clk_path, time_offset); } Arrival time = latch_enable_time + latch_time_given; Arrival incr = latch_time_given; if (delayGreaterEqual(incr, 0.0, this)) - reportLine("time given to startpoint", incr, time, early_late); + reportLine("time given to startpoint", incr, time, early_late); else - reportLine("time borrowed from startpoint", incr, time, early_late); + reportLine("time borrowed from startpoint", incr, time, early_late); // Override latch D arrival with enable + given. reportPathLine(expanded.path(0), delay_zero, time, "latch_D"); reportPath6(path, expanded, 1, propagated_clk, report_clk_path, - latch_enable_time + latch_time_given, time_offset); + latch_enable_time + latch_time_given, time_offset); } } else reportPath5(path, expanded, skip_first_path, propagated_clk, - report_clk_path, time_offset); + report_clk_path, time_offset); } void ReportPath::reportPath5(const Path *path, - const PathExpanded &expanded, - bool skip_first_path, - bool propagated_clk, - bool report_clk_path, - float time_offset) const + const PathExpanded &expanded, + bool skip_first_path, + bool propagated_clk, + bool report_clk_path, + float time_offset) const { size_t path_first_index = 0; Arrival prev_time = 0.0; @@ -2695,23 +2687,24 @@ ReportPath::reportPath5(const Path *path, prev_time = start->arrival() + time_offset; } reportPath6(path, expanded, path_first_index, propagated_clk, - report_clk_path, prev_time, time_offset); + report_clk_path, prev_time, time_offset); } // This does the real workk of reporting an expanded path. void ReportPath::reportPath6(const Path *path, - const PathExpanded &expanded, - size_t path_first_index, - bool propagated_clk, - bool report_clk_path, - Arrival prev_time, - float time_offset) const + const PathExpanded &expanded, + size_t path_first_index, + bool propagated_clk, + bool report_clk_path, + Arrival prev_time, + float time_offset) const { size_t path_last_index = expanded.size() - 1; + const Scene *scene = path->scene(this); const MinMax *min_max = path->minMax(this); - DcalcAnalysisPt *dcalc_ap = path->pathAnalysisPt(this)->dcalcAnalysisPt(); - DcalcAPIndex ap_index = dcalc_ap->index(); + const Sdc *sdc = path->sdc(this); + DcalcAPIndex slew_index = path->dcalcAnalysisPtIndex(this); const Path *clk_path = expanded.clkPath(); Vertex *clk_start = clk_path ? clk_path->vertex(this) : nullptr; for (size_t i = path_first_index; i <= path_last_index; i++) { @@ -2731,86 +2724,86 @@ ReportPath::reportPath6(const Path *path, // Always show the search start point (register clk pin). // Skip reporting the clk tree unless it is requested. if (is_clk_start - || report_clk_path - || !is_clk) { + || report_clk_path + || !is_clk) { const RiseFall *rf = path1->transition(this); - Slew slew = graph_->slew(vertex, rf, ap_index); + Slew slew = graph_->slew(vertex, rf, slew_index); if (prev_arc == nullptr) { - // First path. - reportInputExternalDelay(path1, time_offset); - size_t next_index = i + 1; - const Path *next_path = expanded.path(next_index); - if (network_->isTopLevelPort(pin) - && next_path - && !nextArcAnnotated(next_path, next_index, expanded, ap_index) - && hasExtInputDriver(pin, rf, min_max)) { - // Pin is an input port with drive_cell/drive_resistance. - // The delay calculator annotates wire delays on the edges - // from the input to the loads. Report the wire delay on the - // input pin instead. - Arrival next_time = next_path->arrival() + time_offset; - incr = delayIncr(next_time, time, min_max); - time = next_time; - line_case = "input_drive"; - } - else if (is_clk) { - if (!propagated_clk) - // Clock latency at path endpoint in case latency was set - // on a clock pin other than the clock source. - time = search_->clkPathArrival(path1) + time_offset; - incr = 0.0; - line_case = "clk_first"; - } - else { - incr = 0.0; - line_case = "first"; - } + // First path. + reportInputExternalDelay(path1, time_offset); + size_t next_index = i + 1; + const Path *next_path = expanded.path(next_index); + if (network_->isTopLevelPort(pin) + && next_path + && !nextArcAnnotated(next_path, next_index, expanded, slew_index) + && hasExtInputDriver(pin, rf, min_max, sdc)) { + // Pin is an input port with drive_cell/drive_resistance. + // The delay calculator annotates wire delays on the edges + // from the input to the loads. Report the wire delay on the + // input pin instead. + Arrival next_time = next_path->arrival() + time_offset; + incr = delayIncr(next_time, time, min_max); + time = next_time; + line_case = "input_drive"; + } + else if (is_clk) { + if (!propagated_clk) + // Clock latency at path endpoint in case latency was set + // on a clock pin other than the clock source. + time = search_->clkPathArrival(path1) + time_offset; + incr = 0.0; + line_case = "clk_first"; + } + else { + incr = 0.0; + line_case = "first"; + } } else if (is_clk_start - && is_clk - && !report_clk_path) { - // Clock start point and clock path are not reported. - incr = 0.0; - if (!propagated_clk) { - // Ideal clock. - const ClockEdge *src_clk_edge = path->clkEdge(this); - time = search_->clkPathArrival(path1) + time_offset; - if (src_clk_edge) { - Clock *src_clk = src_clk_edge->clock(); - const RiseFall *src_clk_rf = src_clk_edge->transition(); - slew = src_clk->slew(src_clk_rf, min_max); - } - } - line_case = "clk_start"; + && is_clk + && !report_clk_path) { + // Clock start point and clock path are not reported. + incr = 0.0; + if (!propagated_clk) { + // Ideal clock. + const ClockEdge *src_clk_edge = path->clkEdge(this); + time = search_->clkPathArrival(path1) + time_offset; + if (src_clk_edge) { + Clock *src_clk = src_clk_edge->clock(); + const RiseFall *src_clk_rf = src_clk_edge->transition(); + slew = src_clk->slew(src_clk_rf, min_max); + } + } + line_case = "clk_start"; } else if (is_clk - && report_clk_path - && !propagated_clk) { - // Zero the clock network delays for ideal clocks. - incr = 0.0; - time = prev_time; - const ClockEdge *src_clk_edge = path->clkEdge(this); - const Clock *src_clk = src_clk_edge->clock(); - const RiseFall *src_clk_rf = src_clk_edge->transition(); - slew = src_clk->slew(src_clk_rf, min_max); - line_case = "clk_ideal"; + && report_clk_path + && !propagated_clk) { + // Zero the clock network delays for ideal clocks. + incr = 0.0; + time = prev_time; + const ClockEdge *src_clk_edge = path->clkEdge(this); + const Clock *src_clk = src_clk_edge->clock(); + const RiseFall *src_clk_rf = src_clk_edge->transition(); + slew = src_clk->slew(src_clk_rf, min_max); + line_case = "clk_ideal"; } else if (is_clk && !is_clk_start) { - incr = delayIncr(time, prev_time, min_max); - line_case = "clk_prop"; + incr = delayIncr(time, prev_time, min_max); + line_case = "clk_prop"; } else { - incr = delayIncr(time, prev_time, min_max); - line_case = "normal"; + incr = delayIncr(time, prev_time, min_max); + line_case = "normal"; } if (vertex->isDriver(network_)) { float cap = field_blank_; float fanout = field_blank_; if (field_capacitance_->enabled()) - cap = graph_delay_calc_->loadCap(pin, rf, dcalc_ap); + cap = graph_delay_calc_->loadCap(pin, rf, scene, min_max); if (field_fanout_->enabled()) - fanout = drvrFanout(vertex, dcalc_ap->corner(), min_max); + fanout = drvrFanout(vertex, scene, min_max); const string what = descriptionField(vertex); reportLine(what.c_str(), cap, slew, fanout, incr, time, false, min_max, rf, src_attr, @@ -2861,8 +2854,8 @@ ReportPath::reportHierPinsThru(const Path *path) const Delay ReportPath::delayIncr(Delay time, - Delay prev, - const MinMax *min_max) const + Delay prev, + const MinMax *min_max) const { if (report_sigmas_) return delayRemove(time, prev); @@ -2872,9 +2865,9 @@ ReportPath::delayIncr(Delay time, bool ReportPath::nextArcAnnotated(const Path *next_path, - size_t next_index, - const PathExpanded &expanded, - DcalcAPIndex ap_index) const + size_t next_index, + const PathExpanded &expanded, + DcalcAPIndex ap_index) const { const TimingArc *arc = expanded.path(next_index)->prevArc(this); Edge *edge = next_path->prevEdge(this); @@ -2934,9 +2927,10 @@ ReportPath::descriptionNet(const Pin *pin) const float ReportPath::drvrFanout(Vertex *drvr, - const Corner *corner, - const MinMax *min_max) const + const Scene *scene, + const MinMax *min_max) const { + const Sdc *sdc = scene->sdc(); float fanout = 0.0; VertexOutEdgeIterator iter(drvr, graph_); while (iter.hasNext()) { @@ -2946,7 +2940,7 @@ ReportPath::drvrFanout(Vertex *drvr, if (network_->isTopLevelPort(pin)) { // Output port counts as a fanout. Port *port = network_->port(pin); - fanout += sdc_->portExtFanout(port, corner, min_max) + 1; + fanout += sdc->portExtFanout(port, min_max) + 1; } else fanout++; @@ -2957,19 +2951,20 @@ ReportPath::drvrFanout(Vertex *drvr, bool ReportPath::hasExtInputDriver(const Pin *pin, - const RiseFall *rf, - const MinMax *min_max) const + const RiseFall *rf, + const MinMax *min_max, + const Sdc *sdc) const { Port *port = network_->port(pin); - InputDrive *drive = sdc_->findInputDrive(port); + InputDrive *drive = sdc->findInputDrive(port); return (drive - && (drive->hasDriveResistance(rf, min_max) - || drive->hasDriveCell(rf, min_max))); + && (drive->hasDriveResistance(rf, min_max) + || drive->hasDriveCell(rf, min_max))); } void ReportPath::reportInputExternalDelay(const Path *first_path, - float time_offset) const + float time_offset) const { const Pin *first_pin = first_path->pin(graph_); if (!pathFromClkPin(first_path, first_pin)) { @@ -2980,17 +2975,17 @@ ReportPath::reportInputExternalDelay(const Path *first_path, if (input_delay) { const Pin *ref_pin = input_delay->refPin(); if (ref_pin) { - Path ref_path; - pathInputDelayRefPath(first_path, input_delay, ref_path); - if (!ref_path.isNull() && reportClkPath()) { - PathExpanded ref_expanded(&ref_path, this); - reportPath3(&ref_path, ref_expanded, true, 0.0); - } + Path ref_path; + pathInputDelayRefPath(first_path, input_delay, ref_path); + if (!ref_path.isNull() && reportClkPath()) { + PathExpanded ref_expanded(&ref_path, this); + reportPath3(&ref_path, ref_expanded, true, 0.0); + } } float input_arrival = - input_delay->delays()->value(rf, first_path->minMax(this)); + input_delay->delays()->value(rf, first_path->minMax(this)); reportLine("input external delay", input_arrival, time, - early_late, rf); + early_late, rf); } else if (network_->isTopLevelPort(first_pin)) reportLine("input external delay", 0.0, time, early_late, rf); @@ -3006,17 +3001,17 @@ ReportPath::pathInputDelay(const Path *first_path) const void ReportPath::pathInputDelayRefPath(const Path *path, - const InputDelay *input_delay, - // Return value. - Path &ref_path) const + const InputDelay *input_delay, + // Return value. + Path &ref_path) const { const Pin *ref_pin = input_delay->refPin(); const RiseFall *ref_rf = input_delay->refTransition(); Vertex *ref_vertex = graph_->pinDrvrVertex(ref_pin); if (ref_vertex) { - const PathAnalysisPt *path_ap = path->pathAnalysisPt(this); const ClockEdge *clk_edge = path->clkEdge(this); - VertexPathIterator path_iter(ref_vertex, ref_rf, path_ap, this); + VertexPathIterator path_iter(ref_vertex, path->scene(this), + path->minMax(this), ref_rf,this); while (path_iter.hasNext()) { Path *path = path_iter.next(); if (path->isClock(this) @@ -3038,7 +3033,7 @@ ReportPath::reportPathHeader() const for (const ReportField *field : fields_) { if (field->enabled()) { if (!first_field) - line += ' '; + line += ' '; reportField(field->title(), field, line); first_field = false; } @@ -3051,87 +3046,87 @@ ReportPath::reportPathHeader() const // Report total. void ReportPath::reportLine(const char *what, - Delay total, - const EarlyLate *early_late) const + Delay total, + const EarlyLate *early_late) const { reportLine(what, field_blank_, field_blank_, field_blank_, - field_blank_, total, false, early_late, nullptr, - "", nullptr); + field_blank_, total, false, early_late, nullptr, + "", nullptr); } // Report negative total. void ReportPath::reportLineNegative(const char *what, - Delay total, - const EarlyLate *early_late) const + Delay total, + const EarlyLate *early_late) const { reportLine(what, field_blank_, field_blank_, field_blank_, - field_blank_, total, true, early_late, nullptr, - "", nullptr); + field_blank_, total, true, early_late, nullptr, + "", nullptr); } // Report total, and transition suffix. void ReportPath::reportLine(const char *what, - Delay total, - const EarlyLate *early_late, - const RiseFall *rf) const + Delay total, + const EarlyLate *early_late, + const RiseFall *rf) const { reportLine(what, field_blank_, field_blank_, field_blank_, - field_blank_, total, false, early_late, rf, "", - nullptr); + field_blank_, total, false, early_late, rf, "", + nullptr); } // Report increment, and total. void ReportPath::reportLine(const char *what, - Delay incr, - Delay total, - const EarlyLate *early_late) const + Delay incr, + Delay total, + const EarlyLate *early_late) const { reportLine(what, field_blank_, field_blank_, field_blank_, - incr, total, false, early_late, nullptr, "", - nullptr); + incr, total, false, early_late, nullptr, "", + nullptr); } // Report increment, total, and transition suffix. void ReportPath::reportLine(const char *what, - Delay incr, - Delay total, - const EarlyLate *early_late, - const RiseFall *rf) const + Delay incr, + Delay total, + const EarlyLate *early_late, + const RiseFall *rf) const { reportLine(what, field_blank_, field_blank_, field_blank_, - incr, total, false, early_late, rf, "", - nullptr); + incr, total, false, early_late, rf, "", + nullptr); } // Report slew, increment, and total. void ReportPath::reportLine(const char *what, - Slew slew, - Delay incr, - Delay total, - const EarlyLate *early_late) const + Slew slew, + Delay incr, + Delay total, + const EarlyLate *early_late) const { reportLine(what, field_blank_, slew, field_blank_, - incr, total, false, early_late, nullptr, - "", nullptr); + incr, total, false, early_late, nullptr, + "", nullptr); } void ReportPath::reportLine(const char *what, - float cap, - Slew slew, - float fanout, - Delay incr, - Delay total, - bool total_with_minus, - const EarlyLate *early_late, - const RiseFall *rf, - string src_attr, - const char *line_case) const + float cap, + Slew slew, + float fanout, + Delay incr, + Delay total, + bool total_with_minus, + const EarlyLate *early_late, + const RiseFall *rf, + string src_attr, + const char *line_case) const { string line; size_t field_index = 0; @@ -3141,44 +3136,44 @@ ReportPath::reportLine(const char *what, if (field->enabled()) { if (!first_field) - line += ' '; + line += ' '; if (field == field_description_) - reportDescription(what, first_field, last_field, line); + reportDescription(what, first_field, last_field, line); else if (field == field_fanout_) { - if (fanout == field_blank_) - reportFieldBlank(field, line); - else - line += stdstrPrint("%*d", + if (fanout == field_blank_) + reportFieldBlank(field, line); + else + line += stdstrPrint("%*d", field_fanout_->width(), static_cast(fanout)); } else if (field == field_capacitance_) - reportField(cap, field, line); + reportField(cap, field, line); else if (field == field_slew_) - reportFieldDelay(slew, early_late, field, line); + reportFieldDelay(slew, early_late, field, line); else if (field == field_incr_) - reportFieldDelay(incr, early_late, field, line); + reportFieldDelay(incr, early_late, field, line); else if (field == field_total_) { - if (total_with_minus) - reportFieldDelayMinus(total, early_late, field, line); - else - reportFieldDelay(total, early_late, field, line); + if (total_with_minus) + reportFieldDelayMinus(total, early_late, field, line); + else + reportFieldDelay(total, early_late, field, line); } else if (field == field_edge_) { - if (rf) - reportField(rf->shortName(), field, line); - else - reportFieldBlank(field, line); + if (rf) + reportField(rf->shortName(), field, line); + else + reportFieldBlank(field, line); } else if (field == field_src_attr_) { - if (src_attr != "") - reportField(src_attr.c_str(), field, line); - else - reportFieldBlank(field, line); + if (src_attr != "") + reportField(src_attr.c_str(), field, line); + else + reportFieldBlank(field, line); } else if (field == field_case_ && line_case) - line += line_case; + line += line_case; first_field = false; } @@ -3195,8 +3190,8 @@ ReportPath::reportLine(const char *what, // Only the total field. void ReportPath::reportLineTotal(const char *what, - Delay incr, - const EarlyLate *early_late) const + Delay incr, + const EarlyLate *early_late) const { reportLineTotal1(what, incr, false, early_late); } @@ -3204,17 +3199,17 @@ ReportPath::reportLineTotal(const char *what, // Only the total field and always with leading minus sign. void ReportPath::reportLineTotalMinus(const char *what, - Delay decr, - const EarlyLate *early_late) const + Delay decr, + const EarlyLate *early_late) const { reportLineTotal1(what, decr, true, early_late); } void ReportPath::reportLineTotal1(const char *what, - Delay incr, - bool incr_with_minus, - const EarlyLate *early_late) const + Delay incr, + bool incr_with_minus, + const EarlyLate *early_late) const { string line; reportDescription(what, line); @@ -3236,16 +3231,16 @@ ReportPath::reportDashLineTotal() const void ReportPath::reportDescription(const char *what, - string &line) const + string &line) const { reportDescription(what, false, false, line); } void ReportPath::reportDescription(const char *what, - bool first_field, - bool last_field, - string &line) const + bool first_field, + bool last_field, + string &line) const { line += what; int length = strlen(what); @@ -3264,8 +3259,8 @@ ReportPath::reportDescription(const char *what, void ReportPath::reportFieldTime(float value, - ReportField *field, - string &line) const + ReportField *field, + string &line) const { if (delayAsFloat(value) == field_blank_) reportFieldBlank(field, line); @@ -3280,7 +3275,7 @@ ReportPath::reportFieldTime(float value, void ReportPath::reportSpaceFieldTime(float value, - string &line) const + string &line) const { line += ' '; reportFieldTime(value, field_total_, line); @@ -3288,8 +3283,8 @@ ReportPath::reportSpaceFieldTime(float value, void ReportPath::reportSpaceFieldDelay(Delay value, - const EarlyLate *early_late, - string &line) const + const EarlyLate *early_late, + string &line) const { line += ' '; reportTotalDelay(value, early_late, line); @@ -3297,8 +3292,8 @@ ReportPath::reportSpaceFieldDelay(Delay value, void ReportPath::reportTotalDelay(Delay value, - const EarlyLate *early_late, - string &line) const + const EarlyLate *early_late, + string &line) const { const char *str = delayAsString(value, early_late, this, digits_); if (stringEq(str, minus_zero_)) @@ -3310,9 +3305,9 @@ ReportPath::reportTotalDelay(Delay value, // Total time always with leading minus sign. void ReportPath::reportFieldDelayMinus(Delay value, - const EarlyLate *early_late, - const ReportField *field, - string &line) const + const EarlyLate *early_late, + const ReportField *field, + string &line) const { if (delayAsFloat(value) == field_blank_) reportFieldBlank(field, line); @@ -3330,9 +3325,9 @@ ReportPath::reportFieldDelayMinus(Delay value, void ReportPath::reportFieldDelay(Delay value, - const EarlyLate *early_late, - const ReportField *field, - string &line) const + const EarlyLate *early_late, + const ReportField *field, + string &line) const { if (delayAsFloat(value) == field_blank_) reportFieldBlank(field, line); @@ -3349,8 +3344,8 @@ ReportPath::reportFieldDelay(Delay value, void ReportPath::reportField(float value, - const ReportField *field, - string &line) const + const ReportField *field, + string &line) const { if (value == field_blank_) reportFieldBlank(field, line); @@ -3371,8 +3366,8 @@ ReportPath::reportField(float value, void ReportPath::reportField(const char *value, - const ReportField *field, - string &line) const + const ReportField *field, + string &line) const { if (field->leftJustify()) line += value; @@ -3384,7 +3379,7 @@ ReportPath::reportField(const char *value, void ReportPath::reportFieldBlank(const ReportField *field, - string &line) const + string &line) const { line += field->blank(); } @@ -3396,7 +3391,7 @@ ReportPath::reportDashLine() const for (const ReportField *field : fields_) { if (field->enabled()) { for (int i = 0; i < field->width(); i++) - line += '-'; + line += '-'; } } line += "------"; @@ -3448,7 +3443,7 @@ ReportPath::asRiseFall(const RiseFall *rf) const // Find the startpoint type from the first path edge. const char * ReportPath::edgeRegLatchDesc(const Edge *first_edge, - const TimingArc *first_arc) const + const TimingArc *first_arc) const { const TimingRole *role = first_arc->role(); if (role == TimingRole::latchDtoQ()) { @@ -3459,7 +3454,7 @@ ReportPath::edgeRegLatchDesc(const Edge *first_edge, const FuncExpr *enable_func; const RiseFall *enable_rf; cell->latchEnable(first_edge->timingArcSet(), - enable_port, enable_func, enable_rf); + enable_port, enable_func, enable_rf); return latchDesc(enable_rf); } } @@ -3473,12 +3468,12 @@ ReportPath::edgeRegLatchDesc(const Edge *first_edge, const char * ReportPath::checkRegLatchDesc(const TimingRole *role, - const RiseFall *clk_rf) const + const RiseFall *clk_rf) const { if (role == TimingRole::regClkToQ()) return regDesc(clk_rf); else if (role == TimingRole::latchEnToQ() - || role == TimingRole::latchDtoQ()) + || role == TimingRole::latchDtoQ()) return latchDesc(clk_rf); else // Default when we don't know better. diff --git a/search/ReportPath.hh b/search/ReportPath.hh index b9f4364b..39c8b1a5 100644 --- a/search/ReportPath.hh +++ b/search/ReportPath.hh @@ -25,19 +25,22 @@ #pragma once #include +#include #include "StringSeq.hh" #include "SearchClass.hh" #include "PathEnd.hh" +#include "CheckMinPulseWidths.hh" +#include "CheckMinPeriods.hh" +#include "CheckMaxSkews.hh" namespace sta { -class Corner; -class DcalcAnalysisPt; +class Scene; class PathExpanded; class ReportField; -typedef Vector ReportFieldSeq; +using ReportFieldSeq = std::vector; class ReportPath : public StaState { @@ -49,11 +52,11 @@ public: void setReportFieldOrder(StringSeq *field_names); void setReportFields(bool report_input_pin, bool report_hier_pins, - bool report_net, - bool report_cap, - bool report_slew, - bool report_fanout, - bool report_src_attr); + bool report_net, + bool report_cap, + bool report_slew, + bool report_fanout, + bool report_src_attr); int digits() const { return digits_; } void setDigits(int digits); void setNoSplit(bool no_split); @@ -70,7 +73,7 @@ public: // Previous path end is used to detect path group changes // so headers are reported by group. void reportPathEnd(const PathEnd *end, - const PathEnd *prev_end, + const PathEnd *prev_end, bool last) const; void reportPathEnds(const PathEndSeq *ends) const; void reportPath(const Path *path) const; @@ -116,44 +119,42 @@ public: void reportSlackOnlyHeader() const; void reportSlackOnly(const PathEnd *end) const; - void reportMpwCheck(const MinPulseWidthCheck *check, - bool verbose) const; - void reportMpwChecks(const MinPulseWidthCheckSeq *checks, - bool verbose) const; + void reportMpwCheck(const MinPulseWidthCheck &check, + bool verbose) const; + void reportMpwChecks(const MinPulseWidthCheckSeq &checks, + bool verbose) const; void reportMpwHeaderShort() const; - void reportShort(const MinPulseWidthCheck *check) const; - void reportVerbose(const MinPulseWidthCheck *check) const; + void reportShort(const MinPulseWidthCheck &check) const; + void reportVerbose(const MinPulseWidthCheck &check) const; - void reportCheck(const MinPeriodCheck *check, - bool verbose) const; - void reportChecks(const MinPeriodCheckSeq *checks, - bool verbose) const; + void reportCheck(const MinPeriodCheck &check, + bool verbose) const; + void reportChecks(const MinPeriodCheckSeq &checks, + bool verbose) const; void reportPeriodHeaderShort() const; - void reportShort(const MinPeriodCheck *check) const; - void reportVerbose(const MinPeriodCheck *check) const; + void reportShort(const MinPeriodCheck &check) const; + void reportVerbose(const MinPeriodCheck &check) const; - void reportCheck(const MaxSkewCheck *check, - bool verbose) const; - void reportChecks(const MaxSkewCheckSeq *checks, - bool verbose) const; + void reportChecks(const MaxSkewCheckSeq &checks, + bool verbose) const; void reportMaxSkewHeaderShort() const; - void reportShort(const MaxSkewCheck *check) const; - void reportVerbose(const MaxSkewCheck *check) const; + void reportShort(const MaxSkewCheck &check) const; + void reportVerbose(const MaxSkewCheck &check) const; void reportLimitShortHeader(const ReportField *field) const; void reportLimitShort(const ReportField *field, - Pin *pin, - float value, - float limit, - float slack) const; + const Pin *pin, + float value, + float limit, + float slack) const; void reportLimitVerbose(const ReportField *field, - Pin *pin, - const RiseFall *rf, - float value, - float limit, - float slack, - const Corner *corner, - const MinMax *min_max) const; + const Pin *pin, + const RiseFall *rf, + float value, + float limit, + float slack, + const Scene *scene, + const MinMax *min_max) const; ReportField *fieldSlew() const { return field_slew_; } ReportField *fieldFanout() const { return field_fanout_; } ReportField *fieldCapacitance() const { return field_capacitance_; } @@ -162,27 +163,27 @@ public: protected: void makeFields(); ReportField *makeField(const char *name, - const char *title, - int width, - bool left_justify, - Unit *unit, - bool enabled); + const char *title, + int width, + bool left_justify, + Unit *unit, + bool enabled); void reportEndpointHeader(const PathEnd *end, - const PathEnd *prev_end) const; + const PathEnd *prev_end) const; void reportShort(const PathEndUnconstrained *end, - const PathExpanded &expanded) const; + const PathExpanded &expanded) const; void reportShort(const PathEndCheck *end, - const PathExpanded &expanded) const; + const PathExpanded &expanded) const; void reportShort(const PathEndLatchCheck *end, - const PathExpanded &expanded) const; + const PathExpanded &expanded) const; void reportShort(const PathEndPathDelay *end, - const PathExpanded &expanded) const; + const PathExpanded &expanded) const; void reportShort(const PathEndOutputDelay *end, - const PathExpanded &expanded) const; + const PathExpanded &expanded) const; void reportShort(const PathEndGatedClock *end, - const PathExpanded &expanded) const; + const PathExpanded &expanded) const; void reportShort(const PathEndDataCheck *end, - const PathExpanded &expanded) const; + const PathExpanded &expanded) const; void reportEndpoint(const PathEndOutputDelay *end) const; void reportEndpointOutputDelay(const PathEndClkConstrained *end) const; void reportEndpoint(const PathEndPathDelay *end) const; @@ -191,8 +192,8 @@ protected: std::string pathStartpoint(const PathEnd *end, const PathExpanded &expanded) const; void reportBorrowing(const PathEndLatchCheck *end, - Arrival &borrow, - Arrival &time_given_to_startpoint) const; + Arrival &borrow, + Arrival &time_given_to_startpoint) const; void reportEndpoint(const PathEndDataCheck *end) const; const char *clkNetworkDelayIdealProp(bool is_ideal) const; @@ -200,90 +201,92 @@ protected: std::string checkRoleString(const PathEnd *end) const; virtual void reportGroup(const PathEnd *end) const; void reportStartpoint(const PathEnd *end, - const PathExpanded &expanded) const; + const PathExpanded &expanded) const; void reportUnclockedEndpoint(const PathEnd *end, - const char *default_reason) const; + const char *default_reason) const; void reportEndpoint(const PathEndCheck *end) const; void reportEndpoint(const PathEndLatchCheck *end) const; const char *latchDesc(const PathEndLatchCheck *end) const; void reportStartpoint(const char *start, - const std::string reason) const; + const std::string reason) const; void reportEndpoint(const char *end, - const std::string reason) const; + const std::string reason) const; void reportStartEndPoint(const char *pt, - const std::string reason, - const char *key) const; + const std::string reason, + const char *key) const; std::string tgtClkName(const PathEnd *end) const; const char *clkRegLatchDesc(const PathEnd *end) const; void reportSrcPath(const PathEnd *end, - const PathExpanded &expanded) const; + const PathExpanded &expanded) const; void reportTgtClk(const PathEnd *end) const; void reportTgtClk(const PathEnd *end, - float prev_time) const; + float prev_time) const; void reportTgtClk(const PathEnd *end, - float prev_time, - bool is_prop) const; + float prev_time, + bool is_prop) const; void reportTgtClk(const PathEnd *end, float prev_time, float src_offset, bool is_prop) const; bool pathFromGenPropClk(const Path *clk_path, - const EarlyLate *early_late) const; + const EarlyLate *early_late) const; bool isGenPropClk(const Clock *clk, - const RiseFall *clk_rf, - const MinMax *min_max, - const EarlyLate *early_late) const; + const RiseFall *clk_rf, + const MinMax *min_max, + const EarlyLate *early_late, + const Sdc *sdc) const; void reportSrcClkAndPath(const Path *path, - const PathExpanded &expanded, - float time_offset, - Arrival clk_insertion, - Arrival clk_latency, - bool is_path_delay) const; + const PathExpanded &expanded, + float time_offset, + Arrival clk_insertion, + Arrival clk_latency, + bool is_path_delay) const; bool reportGenClkSrcPath(const Path *clk_path, const Clock *clk, - const RiseFall *clk_rf, - const MinMax *min_max, - const EarlyLate *early_late) const; + const RiseFall *clk_rf, + const MinMax *min_max, + const EarlyLate *early_late, + const Sdc *sdc) const; void reportGenClkSrcAndPath(const Path *path, - const Clock *clk, - const RiseFall *clk_rf, - const EarlyLate *early_late, - const PathAnalysisPt *path_ap, - float time_offset, - float path_time_offset, - bool clk_used_as_data) const; + const Clock *clk, + const RiseFall *clk_rf, + const EarlyLate *early_late, + float time_offset, + float path_time_offset, + bool clk_used_as_data, + const Mode *mode) const; bool reportGenClkSrcPath1(const Clock *clk, - const Pin *clk_pin, - const RiseFall *clk_rf, - const EarlyLate *early_late, - const PathAnalysisPt *path_ap, - float gclk_time, - float time_offset, - bool clk_used_as_data) const; + const Pin *clk_pin, + const RiseFall *clk_rf, + const EarlyLate *early_late, + float gclk_time, + float time_offset, + bool clk_used_as_data, + const Mode *mode) const; void reportClkSrcLatency(Arrival insertion, - float clk_time, - const EarlyLate *early_late) const; + float clk_time, + const EarlyLate *early_late) const; void reportPathLine(const Path *path, - Delay incr, - Arrival time, - const char *line_case) const; + Delay incr, + Arrival time, + const char *line_case) const; void reportCommonClkPessimism(const PathEnd *end, - Arrival &clk_arrival) const ; + Arrival &clk_arrival) const ; void reportClkUncertainty(const PathEnd *end, - Arrival &clk_arrival) const ; + Arrival &clk_arrival) const ; void reportClkLine(const Clock *clk, - const char *clk_name, - const RiseFall *clk_rf, - Arrival clk_time, - const MinMax *min_max) const ; + const char *clk_name, + const RiseFall *clk_rf, + Arrival clk_time, + const MinMax *min_max) const ; void reportClkLine(const Clock *clk, - const char *clk_name, - const RiseFall *clk_rf, - Arrival prev_time, - Arrival clk_time, - const MinMax *min_max) const ; + const char *clk_name, + const RiseFall *clk_rf, + Arrival prev_time, + Arrival clk_time, + const MinMax *min_max) const ; void reportRequired(const PathEnd *end, - std::string margin_msg) const ; + std::string margin_msg) const ; void reportSlack(const PathEnd *end) const ; void reportSlack(Slack slack) const ; void reportSpaceSlack(const PathEnd *end, @@ -291,125 +294,125 @@ protected: void reportSpaceSlack(Slack slack, std::string &line) const ; void reportSrcPathArrival(const PathEnd *end, - const PathExpanded &expanded) const ; + const PathExpanded &expanded) const ; void reportPath(const PathEnd *end, - const PathExpanded &expanded) const; + const PathExpanded &expanded) const; void reportPathFull(const Path *path) const; void reportPathHeader() const; void reportPath1(const Path *path, - const PathExpanded &expanded, - bool clk_used_as_data, - float time_offset) const; + const PathExpanded &expanded, + bool clk_used_as_data, + float time_offset) const; void reportPath2(const Path *path, - const PathExpanded &expanded, - bool skip_first_path, - bool clk_used_as_data, - float time_offset) const; + const PathExpanded &expanded, + bool skip_first_path, + bool clk_used_as_data, + float time_offset) const; void reportPath3(const Path *path, - const PathExpanded &expanded, - bool report_clk_path, - float time_offset) const; + const PathExpanded &expanded, + bool report_clk_path, + float time_offset) const; void reportPath4(const Path *path, - const PathExpanded &expanded, - bool skip_first_path, - bool propagated_clk, - bool report_clk_path, - float time_offset) const; + const PathExpanded &expanded, + bool skip_first_path, + bool propagated_clk, + bool report_clk_path, + float time_offset) const; void reportPath5(const Path *path, - const PathExpanded &expanded, - bool skip_first_path, - bool propagated_clk, - bool report_clk_path, - float time_offset) const; + const PathExpanded &expanded, + bool skip_first_path, + bool propagated_clk, + bool report_clk_path, + float time_offset) const; void reportPath6(const Path *path, - const PathExpanded &expanded, - size_t path_first_index, - bool propagated_clk, - bool report_clk_path, - Arrival prev_time, - float time_offset) const; + const PathExpanded &expanded, + size_t path_first_index, + bool propagated_clk, + bool report_clk_path, + Arrival prev_time, + float time_offset) const; void reportHierPinsThru(const Path *path) const; void reportInputExternalDelay(const Path *path, - float time_offset) const; + float time_offset) const; void reportLine(const char *what, - Delay total, - const EarlyLate *early_late) const; + Delay total, + const EarlyLate *early_late) const; void reportLineNegative(const char *what, - Delay total, - const EarlyLate *early_late) const; + Delay total, + const EarlyLate *early_late) const; void reportLine(const char *what, - Delay total, - const EarlyLate *early_late, - const RiseFall *rf) const; + Delay total, + const EarlyLate *early_late, + const RiseFall *rf) const; void reportLine(const char *what, - Delay incr, - Delay total, - const EarlyLate *early_late) const; + Delay incr, + Delay total, + const EarlyLate *early_late) const; void reportLine(const char *what, - Delay incr, - Delay total, - const EarlyLate *early_late, - const RiseFall *rf) const; + Delay incr, + Delay total, + const EarlyLate *early_late, + const RiseFall *rf) const; void reportLine(const char *what, - Slew slew, - Delay incr, - Delay total, - const EarlyLate *early_late) const; + Slew slew, + Delay incr, + Delay total, + const EarlyLate *early_late) const; void reportLine(const char *what, - float cap, - Slew slew, - float fanout, - Delay incr, - Delay total, - bool total_with_minus, - const EarlyLate *early_late, - const RiseFall *rf, - std::string src_attr, - const char *line_case) const; + float cap, + Slew slew, + float fanout, + Delay incr, + Delay total, + bool total_with_minus, + const EarlyLate *early_late, + const RiseFall *rf, + std::string src_attr, + const char *line_case) const; void reportLineTotal(const char *what, - Delay incr, - const EarlyLate *early_late) const; + Delay incr, + const EarlyLate *early_late) const; void reportLineTotalMinus(const char *what, - Delay decr, - const EarlyLate *early_late) const; + Delay decr, + const EarlyLate *early_late) const; void reportLineTotal1(const char *what, - Delay incr, - bool incr_with_minus, - const EarlyLate *early_late) const; + Delay incr, + bool incr_with_minus, + const EarlyLate *early_late) const; void reportDashLineTotal() const; void reportDescription(const char *what, std::string &result) const; void reportDescription(const char *what, - bool first_field, - bool last_field, + bool first_field, + bool last_field, std::string &result) const; void reportFieldTime(float value, - ReportField *field, - std::string &result) const; + ReportField *field, + std::string &result) const; void reportSpaceFieldTime(float value, - std::string &result) const; + std::string &result) const; void reportSpaceFieldDelay(Delay value, - const EarlyLate *early_late, - std::string &result) const; + const EarlyLate *early_late, + std::string &result) const; void reportFieldDelayMinus(Delay value, - const EarlyLate *early_late, - const ReportField *field, - std::string &result) const; + const EarlyLate *early_late, + const ReportField *field, + std::string &result) const; void reportTotalDelay(Delay value, - const EarlyLate *early_late, - std::string &result) const; + const EarlyLate *early_late, + std::string &result) const; void reportFieldDelay(Delay value, - const EarlyLate *early_late, - const ReportField *field, - std::string &result) const; + const EarlyLate *early_late, + const ReportField *field, + std::string &result) const; void reportField(float value, - const ReportField *field, - std::string &result) const; + const ReportField *field, + std::string &result) const; void reportField(const char *value, - const ReportField *field, - std::string &result) const; + const ReportField *field, + std::string &result) const; void reportFieldBlank(const ReportField *field, - std::string &result) const; + std::string &result) const; void reportDashLine() const; void reportDashLine(int line_width) const; void reportBlankLine() const; @@ -420,51 +423,51 @@ protected: std::string clkName(const Clock *clk, bool inverted) const; bool hasExtInputDriver(const Pin *pin, - const RiseFall *rf, - const MinMax *min_max) const; + const RiseFall *rf, + const MinMax *min_max, + const Sdc *sdc) const; float drvrFanout(Vertex *drvr, - const Corner *corner, - const MinMax *min_max) const; - const char *mpwCheckHiLow(const MinPulseWidthCheck *check) const; + const Scene *scene, + const MinMax *min_max) const; + const char *mpwCheckHiLow(const MinPulseWidthCheck &check) const; void reportSkewClkPath(const char *arrival_msg, - const Path *clk_path) const; + const Path *clk_path) const; const char *edgeRegLatchDesc(const Edge *edge, - const TimingArc *arc) const; + const TimingArc *arc) const; const char *checkRegLatchDesc(const TimingRole *role, - const RiseFall *clk_rf) const; + const RiseFall *clk_rf) const; const char *regDesc(const RiseFall *clk_rf) const; const char *latchDesc(const RiseFall *clk_rf) const; void pathClkPath(const Path *path, - const Path &clk_path) const; + const Path &clk_path) const; bool isPropagated(const Path *clk_path) const; bool isPropagated(const Path *clk_path, - const Clock *clk) const; + const Clock *clk) const; bool pathFromClkPin(const PathExpanded &expanded) const; bool pathFromClkPin(const Path *path, - const Pin *start_pin) const; + const Pin *start_pin) const; void latchPaths(const Path *path, // Return values. Path &d_path, - Path &q_path, - Edge *&d_q_edge) const; + Path &q_path, + Edge *&d_q_edge) const; bool nextArcAnnotated(const Path *next_path, - size_t next_index, - const PathExpanded &expanded, - DcalcAPIndex ap_index) const; + size_t next_index, + const PathExpanded &expanded, + DcalcAPIndex ap_index) const; float tgtClkInsertionOffet(const Path *clk_path, - const EarlyLate *early_late, - const PathAnalysisPt *path_ap) const; + const EarlyLate *early_late) const; // InputDelay used to seed path root. InputDelay *pathInputDelay(const Path *path) const; void pathInputDelayRefPath(const Path *path, - const InputDelay *input_delay, - // Return value. - Path &ref_path) const; + const InputDelay *input_delay, + // Return value. + Path &ref_path) const; const char *asRisingFalling(const RiseFall *rf) const; const char *asRiseFall(const RiseFall *rf) const; Delay delayIncr(Delay time, - Delay prev, - const MinMax *min_max) const; + Delay prev, + const MinMax *min_max) const; // Path options. ReportPathFormat format_; @@ -499,15 +502,15 @@ class ReportField { public: ReportField(const char *name, - const char *title, - int width, - bool left_justify, - Unit *unit, - bool enabled); + const char *title, + int width, + bool left_justify, + Unit *unit, + bool enabled); ~ReportField(); void setProperties(const char *title, - int width, - bool left_justify); + int width, + bool left_justify); const char *name() const { return name_; } const char *title() const { return title_; } int width() const { return width_; } diff --git a/search/Scene.cc b/search/Scene.cc new file mode 100644 index 00000000..154eab34 --- /dev/null +++ b/search/Scene.cc @@ -0,0 +1,187 @@ +// OpenSTA, Static Timing Analyzer +// Copyright (c) 2025, Parallax Software, Inc. +// +// This program is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see . +// +// The origin of this software must not be misrepresented; you must not +// claim that you wrote the original software. +// +// Altered source versions must be plainly marked as such, and must not be +// misrepresented as being the original software. +// +// This notice may not be removed or altered from any source distribution. + +#include "Scene.hh" + +#include "ContainerHelpers.hh" +#include "Parasitics.hh" +#include "Sdc.hh" +#include "Mode.hh" + +namespace sta { + +Scene::Scene(const std::string &name, + size_t index, + Mode *mode, + Parasitics *parasitics_min, + Parasitics *parasitics_max) : + name_(name), + index_(index), + mode_(mode), + parasitics_{parasitics_min, parasitics_max} +{ +} + +Scene::Scene(const std::string &name, + size_t index, + Mode *mode, + Parasitics *parasitics) : + name_(name), + index_(index), + mode_(mode) +{ + for (size_t mm_index : MinMax::rangeIndex()) + parasitics_[mm_index] = parasitics; +} + +size_t +Scene::pathIndex(const MinMax *min_max) const +{ + return index_ * MinMax::index_count + min_max->index(); +} + +void +Scene::setMode(Mode *mode) +{ + mode_ = mode; +} + +Sdc * +Scene::sdc() +{ + return mode_->sdc(); +} + +Sdc * +Scene::sdc() const +{ + return mode_->sdc(); +} + +Parasitics * +Scene::parasitics(const MinMax *min_max) const +{ + return parasitics_[min_max->index()]; +} + +void +Scene::setParasitics(Parasitics *parasitics, + const MinMaxAll *min_max) +{ + for (size_t mm : min_max->rangeIndex()) + parasitics_[mm] = parasitics; +} + +DcalcAPIndex +Scene::dcalcAnalysisPtIndex(const MinMax *min_max) const +{ + return index_ * MinMax::index_count + min_max->index(); +} + +const MinMax * +Scene::checkClkSlewMinMax(const MinMax *min_max) const +{ + switch (mode_->sdc()->analysisType()) { + case AnalysisType::single: + return MinMax::min(); + case AnalysisType::bc_wc: + return min_max; + case AnalysisType::ocv: + return min_max->opposite(); + default: + // suppress gcc warning + return min_max; + } +} + +DcalcAPIndex +Scene::checkClkSlewIndex(const MinMax *min_max) const +{ + return dcalcAnalysisPtIndex(checkClkSlewMinMax(min_max)); +} + +void +Scene::addLiberty(LibertyLibrary *lib, + const MinMax *min_max) +{ + liberty_[min_max->index()].push_back(lib); +} + +const LibertySeq & +Scene::libertyLibraries(const MinMax *min_max) const +{ + return liberty_[min_max->index()]; +} + +int +Scene::libertyIndex(const MinMax *min_max) const +{ + return index_ * MinMax::index_count + min_max->index(); +} + +//////////////////////////////////////////////////////////////// + +SceneSet +Scene::sceneSet(const SceneSeq &scenes) +{ + SceneSet scenes_set; + for (Scene *scene : scenes) + scenes_set.insert(scene); + return scenes_set; +} + +ModeSeq +Scene::modes(const SceneSeq &scenes) +{ + ModeSet mode_set; + for (const Scene *scene : scenes) + mode_set.insert(scene->mode()); + + ModeSeq modes; + for (Mode *mode : mode_set) + modes.push_back(mode); + return modes; +} + +ModeSet +Scene::modeSet(const SceneSeq &scenes) +{ + ModeSet modes; + for (const Scene *scene : scenes) + modes.insert(scene->mode()); + return modes; +} + +ModeSeq +Scene::modesSorted(const SceneSeq &scenes) +{ + ModeSeq modes = Scene::modes(scenes); + sort(modes, [] (const Mode *mode1, + const Mode *mode2) { + return mode1->name() < mode2->name(); + }); + return modes; +} + +} // namespace diff --git a/search/Search.cc b/search/Search.cc index 8a5f69a3..be52ad10 100644 --- a/search/Search.cc +++ b/search/Search.cc @@ -27,8 +27,9 @@ #include #include // abs +#include "ContainerHelpers.hh" #include "Mutex.hh" -#include "Report.hh" +#include "Report.hh" #include "Debug.hh" #include "Stats.hh" #include "Fuzzy.hh" @@ -48,11 +49,10 @@ #include "ExceptionPath.hh" #include "DataCheck.hh" #include "Sdc.hh" -#include "DcalcAnalysisPt.hh" +#include "Mode.hh" #include "SearchPred.hh" #include "Levelize.hh" #include "Bfs.hh" -#include "Corner.hh" #include "Sim.hh" #include "Path.hh" #include "ClkInfo.hh" @@ -60,7 +60,6 @@ #include "TagGroup.hh" #include "PathEnd.hh" #include "PathGroup.hh" -#include "PathAnalysisPt.hh" #include "VisitPathEnds.hh" #include "GatedClk.hh" #include "WorstSlack.hh" @@ -90,171 +89,215 @@ EvalPred::setSearchThruLatches(bool thru_latches) } bool -EvalPred::searchThru(Edge *edge) +EvalPred::searchThru(Edge *edge, + const Mode *mode) const { const TimingRole *role = edge->role(); - return SearchPred0::searchThru(edge) + return SearchPred0::searchThru(edge, mode) && (sta_->variables()->dynamicLoopBreaking() - || !edge->isDisabledLoop()) + || !edge->isDisabledLoop()) && !role->isTimingCheck() && (search_thru_latches_ - || role != TimingRole::latchDtoQ() - || sta_->latches()->latchDtoQState(edge) == LatchEnableState::open); + || role->isLatchDtoQ() + || sta_->latches()->latchDtoQState(edge, mode) == LatchEnableState::open); } bool -EvalPred::searchTo(const Vertex *to_vertex) +EvalPred::searchTo(const Vertex *to_vertex, + const Mode *mode) const { - const Sdc *sdc = sta_->sdc(); - const Pin *pin = to_vertex->pin(); - return SearchPred0::searchTo(to_vertex) - && !(sdc->isLeafPinClock(pin) - && !sdc->isPathDelayInternalTo(pin)); + const Pin *to_pin = to_vertex->pin(); + const Sdc *sdc = mode->sdc(); + return SearchPred0::searchTo(to_vertex, mode) + && !(sdc->isLeafPinClock(to_pin) + && !sdc->isPathDelayInternalTo(to_pin)) + // Fanin paths are broken by path delay internal pin startpoints. + && !sdc->isPathDelayInternalFromBreak(to_pin); } //////////////////////////////////////////////////////////////// -DynLoopSrchPred::DynLoopSrchPred(TagGroupBldr *tag_bldr) : - tag_bldr_(tag_bldr) +// EvalPred unless +// latch D->Q edge +class SearchThru : public EvalPred +{ +public: + SearchThru(const StaState *sta); + bool searchThru(Edge *edge, + const Mode *mode) const override; +}; + +SearchThru::SearchThru(const StaState *sta) : + EvalPred(sta) { } bool -DynLoopSrchPred::loopEnabled(Edge *edge, - bool dynamic_loop_breaking_enabled, - const Graph *graph, - Search *search) +SearchThru::searchThru(Edge *edge, + const Mode *mode) const +{ + return EvalPred::searchThru(edge, mode) + && !edge->role()->isLatchDtoQ(); +} + +//////////////////////////////////////////////////////////////// + +// SearchAdj is mode independent. Search unless +// disabled to break combinational loop +// latch D->Q edge +// timing check edge +// dynamic loop breaking pending tags +class SearchAdj : public SearchPred +{ +public: + SearchAdj(TagGroupBldr *tag_bldr, + const StaState *sta); + bool searchFrom(const Vertex *from_vertex, + const Mode *mode) const override; + bool searchThru(Edge *edge, + const Mode *mode) const override; + bool searchTo(const Vertex *to_vertex, + const Mode *mode) const override; + +protected: + bool loopEnabled(Edge *edge) const; + bool hasPendingLoopPaths(Edge *edge) const; + + TagGroupBldr *tag_bldr_; + const StaState *sta_; + +}; + +SearchAdj::SearchAdj(TagGroupBldr *tag_bldr, + const StaState *sta) : + SearchPred(sta), + tag_bldr_(tag_bldr), + sta_(sta) +{ +} + +bool +SearchAdj::searchFrom(const Vertex * /* from_vertex */, + const Mode *) const +{ + return true; +} + +bool +SearchAdj::searchThru(Edge *edge, + const Mode *) const +{ + const TimingRole *role = edge->role(); + const Variables *variables = sta_->variables(); + return !role->isTimingCheck() + && !role->isLatchDtoQ() + // Register/latch preset/clr edges are disabled by default. + && !(role == TimingRole::regSetClr() + && !variables->presetClrArcsEnabled()) + && !(edge->isBidirectInstPath() + && !variables->bidirectInstPathsEnabled()) + && (!edge->isDisabledLoop() + || (variables->dynamicLoopBreaking() + && hasPendingLoopPaths(edge))); +} + +bool +SearchAdj::loopEnabled(Edge *edge) const { return !edge->isDisabledLoop() - || (dynamic_loop_breaking_enabled - && hasPendingLoopPaths(edge, graph, search)); + || (sta_->variables()->dynamicLoopBreaking() + && hasPendingLoopPaths(edge)); } bool -DynLoopSrchPred::hasPendingLoopPaths(Edge *edge, - const Graph *graph, - Search *search) +SearchAdj::hasPendingLoopPaths(Edge *edge) const { if (tag_bldr_ && tag_bldr_->hasLoopTag()) { - Corners *corners = search->corners(); + const Graph *graph = sta_->graph(); + Search *search = sta_->search(); Vertex *from_vertex = edge->from(graph); TagGroup *prev_tag_group = search->tagGroup(from_vertex); for (auto const [from_tag, path_index] : tag_bldr_->pathIndexMap()) { if (from_tag->isLoop()) { - // Loop false path exceptions apply to rise/fall edges so to_rf - // does not matter. - PathAPIndex path_ap_index = from_tag->pathAPIndex(); - PathAnalysisPt *path_ap = corners->findPathAnalysisPt(path_ap_index); - Tag *to_tag = search->thruTag(from_tag, edge, RiseFall::rise(), - path_ap->pathMinMax(), path_ap, nullptr); - if (to_tag - && (prev_tag_group == nullptr - || !prev_tag_group->hasTag(from_tag))) - return true; + // Loop false path exceptions apply to rise/fall edges so to_rf + // does not matter. + Tag *to_tag = search->thruTag(from_tag, edge, RiseFall::rise(), nullptr); + if (to_tag + && (prev_tag_group == nullptr + || !prev_tag_group->hasTag(from_tag))) + return true; } } } return false; } -// EvalPred unless -// latch D->Q edge -class SearchThru : public EvalPred, public DynLoopSrchPred -{ -public: - SearchThru(TagGroupBldr *tag_bldr, - const StaState *sta); - virtual bool searchThru(Edge *edge); -}; - -SearchThru::SearchThru(TagGroupBldr *tag_bldr, - const StaState *sta) : - EvalPred(sta), - DynLoopSrchPred(tag_bldr) -{ -} - bool -SearchThru::searchThru(Edge *edge) +SearchAdj::searchTo(const Vertex * /* to_vertex */, + const Mode *) const { - const Graph *graph = sta_->graph(); - Search *search = sta_->search(); - return EvalPred::searchThru(edge) - // Only search thru latch D->Q if it is always open. - // Enqueue thru latches is handled explicitly by search. - && (edge->role() != TimingRole::latchDtoQ() - || sta_->latches()->latchDtoQState(edge) == LatchEnableState::open) - && loopEnabled(edge, sta_->variables()->dynamicLoopBreaking(), - graph, search); -} - -ClkArrivalSearchPred::ClkArrivalSearchPred(const StaState *sta) : - EvalPred(sta) -{ -} - -bool -ClkArrivalSearchPred::searchThru(Edge *edge) -{ - const TimingRole *role = edge->role(); - return (role->isWire() - || role == TimingRole::combinational()) - && EvalPred::searchThru(edge); + return true; } //////////////////////////////////////////////////////////////// Search::Search(StaState *sta) : - StaState(sta) -{ - init(sta); -} + StaState(sta), + unconstrained_paths_(false), + crpr_path_pruning_enabled_(true), + crpr_approx_missing_requireds_(true), -void -Search::init(StaState *sta) + search_thru_(new SearchThru(this)), + search_adj_(new SearchAdj(nullptr, this)), + eval_pred_(new EvalPred(this)), + + arrivals_exist_(false), + arrivals_seeded_(false), + invalid_arrivals_(makeVertexSet(this)), + arrival_iter_(new BfsFwdIterator(BfsIndex::arrival, nullptr, this)), + arrival_visitor_(new ArrivalVisitor(this)), + + requireds_exist_(false), + requireds_seeded_(false), + invalid_requireds_(makeVertexSet(this)), + required_iter_(new BfsBkwdIterator(BfsIndex::required, search_adj_, this)), + + tns_exists_(false), + invalid_tns_(makeVertexSet(this)), + worst_slacks_(nullptr), + clk_info_set_(new ClkInfoSet(ClkInfoLess(this))), + + tag_capacity_(128), + tags_(new Tag*[tag_capacity_]), + tag_set_(new TagSet(tag_capacity_, TagHash(this), TagEqual(this))), + tag_next_(0), + + tag_group_capacity_(tag_capacity_), + tag_groups_(new TagGroup*[tag_group_capacity_]), + tag_group_set_(new TagGroupSet(tag_group_capacity_)), + tag_group_next_(0), + + pending_latch_outputs_(makeVertexSet(this)), + pending_clk_endpoints_(makeVertexSet(this)), + endpoints_(makeVertexSet(this)), + endpoints_initialized_(false), + invalid_endpoints_(makeVertexSet(this)), + + have_filter_(false), + filter_from_(nullptr), + filter_thrus_(nullptr), + filter_to_(nullptr), + filtered_arrivals_(makeVertexSet(this)), + + found_downstream_clk_pins_(false), + postpone_latch_outputs_(false), + + visit_path_ends_(new VisitPathEnds(this)), + gated_clk_(new GatedClk(this)), + check_crpr_(new CheckCrpr(this)) { initVars(); - - search_adj_ = new SearchThru(nullptr, sta); - eval_pred_ = new EvalPred(sta); - check_crpr_ = new CheckCrpr(sta); - genclks_ = new Genclks(sta); - arrival_visitor_ = new ArrivalVisitor(sta); - clk_arrivals_valid_ = false; - arrivals_exist_ = false; - arrivals_at_endpoints_exist_ = false; - arrivals_seeded_ = false; - requireds_exist_ = false; - requireds_seeded_ = false; - invalid_arrivals_ = new VertexSet(graph_); - invalid_requireds_ = new VertexSet(graph_); - invalid_tns_ = new VertexSet(graph_); - tns_exists_ = false; - worst_slacks_ = nullptr; - arrival_iter_ = new BfsFwdIterator(BfsIndex::arrival, nullptr, sta); - required_iter_ = new BfsBkwdIterator(BfsIndex::required, search_adj_, sta); - tag_capacity_ = 128; - tag_set_ = new TagSet(tag_capacity_, TagHash(sta), TagEqual(sta)); - clk_info_set_ = new ClkInfoSet(ClkInfoLess(sta)); - tag_next_ = 0; - tags_ = new Tag*[tag_capacity_]; - tag_group_capacity_ = tag_capacity_; - tag_groups_ = new TagGroup*[tag_group_capacity_]; - tag_group_next_ = 0; - tag_group_set_ = new TagGroupSet(tag_group_capacity_); - pending_latch_outputs_ = new VertexSet(graph_); - visit_path_ends_ = new VisitPathEnds(this); - gated_clk_ = new GatedClk(this); - path_groups_ = nullptr; - endpoints_ = nullptr; - invalid_endpoints_ = nullptr; - filter_ = nullptr; - filter_from_ = nullptr; - filter_to_ = nullptr; - filtered_arrivals_ = new VertexSet(graph_); - found_downstream_clk_pins_ = false; - postpone_latch_outputs_ = false; } // Init "options". @@ -276,23 +319,16 @@ Search::~Search() delete [] tags_; delete [] tag_groups_; delete tag_group_set_; + delete search_thru_; delete search_adj_; delete eval_pred_; delete arrival_visitor_; delete arrival_iter_; delete required_iter_; - delete endpoints_; - delete invalid_arrivals_; - delete invalid_requireds_; - delete invalid_tns_; - delete invalid_endpoints_; - delete pending_latch_outputs_; delete visit_path_ends_; delete gated_clk_; delete worst_slacks_; delete check_crpr_; - delete genclks_; - delete filtered_arrivals_; deleteFilter(); } @@ -301,28 +337,33 @@ Search::clear() { initVars(); - clk_arrivals_valid_ = false; - arrivals_at_endpoints_exist_ = false; arrivals_seeded_ = false; requireds_exist_ = false; requireds_seeded_ = false; tns_exists_ = false; clearWorstSlack(); - invalid_arrivals_->clear(); + invalid_arrivals_.clear(); arrival_iter_->clear(); - invalid_requireds_->clear(); - invalid_tns_->clear(); + invalid_requireds_.clear(); + invalid_tns_.clear(); required_iter_->clear(); endpointsInvalid(); deletePathGroups(); deletePaths(); deleteTags(); clearPendingLatchOutputs(); + pending_clk_endpoints_.clear(); deleteFilter(); - genclks_->clear(); found_downstream_clk_pins_ = false; } +void +Search::deletePathGroups() +{ + for (Mode *mode : modes_) + mode->deletePathGroups(); +} + bool Search::crprPathPruningEnabled() const { @@ -359,26 +400,29 @@ Search::deleteTags() tag_group_free_indices_.clear(); tag_next_ = 0; - tag_set_->deleteContentsClear(); - tag_free_indices_.clear(); + deleteContents(tag_set_); - clk_info_set_->deleteContentsClear(); + deleteContents(clk_info_set_); deleteTagsPrev(); } void Search::deleteFilter() { - if (filter_) { - sdc_->deleteException(filter_); - filter_ = nullptr; - filter_from_ = nullptr; + if (have_filter_) { + for (const Mode *mode : modes_) + mode->sdc()->deleteFilter(); + have_filter_ = false; } - else { - // Filter owns filter_from_ if it exists. - delete filter_from_; - filter_from_ = nullptr; + delete filter_from_; + filter_from_ = nullptr; + + if (filter_thrus_) { + deleteContents(*filter_thrus_); + delete filter_thrus_; + filter_thrus_ = nullptr; } + delete filter_to_; filter_to_ = nullptr; } @@ -391,10 +435,12 @@ Search::copyState(const StaState *sta) arrival_iter_->copyState(sta); required_iter_->copyState(sta); arrival_visitor_->copyState(sta); + eval_pred_->copyState(sta); + search_thru_->copyState(sta); + search_adj_->copyState(sta); visit_path_ends_->copyState(sta); gated_clk_->copyState(sta); check_crpr_->copyState(sta); - genclks_->copyState(sta); } //////////////////////////////////////////////////////////////// @@ -410,11 +456,9 @@ Search::deletePaths() deletePaths(vertex); } - for (Path *path : enum_paths_) - delete path; - enum_paths_.clear(); + deleteContents(enum_paths_); - filtered_arrivals_->clear(); + filtered_arrivals_.clear(); arrivals_exist_ = false; } } @@ -439,10 +483,10 @@ void Search::deletePaths(Vertex *vertex) { debugPrint(debug_, "search", 4, "delete paths %s", - vertex->name(network_)); + vertex->to_string(this).c_str()); TagGroup *tag_group = tagGroup(vertex); if (tag_group) { - graph_->deletePaths(vertex); + vertex->deletePaths(); tag_group->decrRefCount(); } } @@ -454,42 +498,54 @@ Search::deletePaths(Vertex *vertex) // PathEnds are owned by Search PathGroups and deleted on next call. PathEndSeq Search::findPathEnds(ExceptionFrom *from, - ExceptionThruSeq *thrus, - ExceptionTo *to, - bool unconstrained, - const Corner *corner, - const MinMaxAll *min_max, - size_t group_path_count, - size_t endpoint_path_count, - bool unique_pins, - bool unique_edges, - float slack_min, - float slack_max, - bool sort_by_slack, - PathGroupNameSet *group_names, - bool setup, - bool hold, - bool recovery, - bool removal, - bool clk_gating_setup, - bool clk_gating_hold) + ExceptionThruSeq *thrus, + ExceptionTo *to, + bool unconstrained, + const SceneSeq &scenes, + const MinMaxAll *min_max, + size_t group_path_count, + size_t endpoint_path_count, + bool unique_pins, + bool unique_edges, + float slack_min, + float slack_max, + bool sort_by_slack, + StdStringSeq &group_names, + bool setup, + bool hold, + bool recovery, + bool removal, + bool clk_gating_setup, + bool clk_gating_hold) { findFilteredArrivals(from, thrus, to, unconstrained, true); if (!variables_->recoveryRemovalChecksEnabled()) recovery = removal = false; if (!variables_->gatedClkChecksEnabled()) clk_gating_setup = clk_gating_hold = false; - makePathGroups(group_path_count, endpoint_path_count, - unique_pins, unique_edges, - slack_min, slack_max, - group_names, setup, hold, - recovery, removal, - clk_gating_setup, clk_gating_hold); ensureDownstreamClkPins(); - PathEndSeq path_ends = path_groups_->makePathEnds(to, unconstrained_paths_, - corner, min_max, - sort_by_slack); - sdc_->reportClkToClkMaxCycleWarnings(); + const ModeSeq modes = Scene::modesSorted(scenes); + PathEndSeq path_ends; + for (Mode *mode : modes) { + PathGroups *path_groups = mode->makePathGroups(group_path_count, + endpoint_path_count, + unique_pins, unique_edges, + slack_min, slack_max, + group_names, + setup, hold, + recovery, removal, + clk_gating_setup, clk_gating_hold, + unconstrained_paths_); + SceneSeq mode_scenes; + for (Scene *scene : scenes) { + if (scene->mode() == mode) + mode_scenes.push_back(scene); + } + path_groups->makePathEnds(to, mode_scenes, min_max, sort_by_slack, + unconstrained_paths_, path_ends); + } + for (const Mode *mode : modes) + mode->sdc()->reportClkToClkMaxCycleWarnings(); return path_ends; } @@ -503,45 +559,25 @@ Search::findFilteredArrivals(ExceptionFrom *from, unconstrained_paths_ = unconstrained; checkFromThrusTo(from, thrus, to); filter_from_ = from; + filter_thrus_ = thrus; filter_to_ = to; if ((from && (from->pins() - || from->instances())) + || from->instances())) || thrus) { - filter_ = sdc_->makeFilterPath(from, thrus, nullptr); + for (const Mode *mode : modes_) { + Sdc *sdc = mode->sdc(); + sdc->makeFilter(from ? from->clone(network_) : nullptr, + thrus ? exceptionThrusClone(thrus, network_) : nullptr); + } + have_filter_ = true; findFilteredArrivals(thru_latches); } else // These cases do not require filtered arrivals. // -from clocks // -to - findAllArrivals(thru_latches); -} - -void -Search::makePathGroups(int group_path_count, - int endpoint_path_count, - bool unique_pins, - bool unique_edges, - float slack_min, - float slack_max, - PathGroupNameSet *group_names, - bool setup, - bool hold, - bool recovery, - bool removal, - bool clk_gating_setup, - bool clk_gating_hold) -{ - path_groups_ = new PathGroups(group_path_count, endpoint_path_count, - unique_pins, unique_edges, - slack_min, slack_max, - group_names, - setup, hold, - recovery, removal, - clk_gating_setup, clk_gating_hold, - unconstrained_paths_, - this); + findAllArrivals(thru_latches, false); } // From/thrus/to are used to make a filter exception. If the last @@ -551,16 +587,13 @@ Search::makePathGroups(int group_path_count, void Search::deleteFilteredArrivals() { - if (filter_) { - ExceptionFrom *from = filter_->from(); - ExceptionThruSeq *thrus = filter_->thrus(); - if ((from - && (from->pins() - || from->instances())) - || thrus) { - for (Vertex *vertex : *filtered_arrivals_) { - if (isClock(vertex)) - clk_arrivals_valid_ = false; + if (have_filter_) { + ExceptionThruSeq *thrus = filter_thrus_; + if ((filter_from_ + && (filter_from_->pins() + || filter_from_->instances())) + || thrus) { + for (Vertex *vertex : filtered_arrivals_) { deletePathsIncr(vertex); arrivalInvalid(vertex); requiredInvalid(vertex); @@ -573,21 +606,22 @@ Search::deleteFilteredArrivals() TagGroup *tag_group = tagGroup(vertex); if (tag_group && tag_group->hasFilterTag()) - filtered_arrivals_->erase(vertex); + filtered_arrivals_.erase(vertex); } - if (!filtered_arrivals_->empty()) { + if (!filtered_arrivals_.empty()) { report_->reportLine("Filtered verticies mismatch"); - for (Vertex *vertex : *filtered_arrivals_) + for (Vertex *vertex : filtered_arrivals_) report_->reportLine(" %s", vertex->to_string(this).c_str()); } } - filtered_arrivals_->clear(); + filtered_arrivals_.clear(); deleteFilterTagGroups(); deleteFilterTags(); deleteFilterClkInfos(); } - deleteFilter(); } + // Delete filter_from/thru/to even if there is no filter_. + deleteFilter(); } void @@ -596,7 +630,7 @@ Search::deleteFilterTagGroups() for (TagGroupIndex i = 0; i < tag_group_next_; i++) { TagGroup *group = tag_groups_[i]; if (group - && group->hasFilterTag()) + && group->hasFilterTag()) deleteTagGroup(group); } } @@ -616,12 +650,11 @@ Search::deleteFilterTags() for (TagIndex i = 0; i < tag_next_; i++) { Tag *tag = tags_[i]; if (tag - && (tag->isFilter() - || tag->clkInfo()->crprPathRefsFilter())) { + && (tag->isFilter() + || tag->clkInfo()->crprPathRefsFilter())) { tags_[i] = nullptr; tag_set_->erase(tag); delete tag; - tag_free_indices_.push_back(i); } } } @@ -643,15 +676,16 @@ Search::deleteFilterClkInfos() void Search::findFilteredArrivals(bool thru_latches) { - filtered_arrivals_->clear(); + filtered_arrivals_.clear(); findArrivalsSeed(); seedFilterStarts(); Level max_level = levelize_->maxLevel(); // Search always_to_endpoint to search from exisiting arrivals at // fanin startpoints to reach -thru/-to endpoints. - arrival_visitor_->init(true); + arrival_visitor_->init(true, false, eval_pred_); // Iterate until data arrivals at all latches stop changing. postpone_latch_outputs_ = true; + enqueuePendingClkFanouts(); for (int pass = 1; pass == 1 || (thru_latches && havePendingLatchOutputs()) ; pass++) { if (thru_latches) enqueuePendingLatchOutputs(); @@ -691,7 +725,7 @@ VertexSeq Search::filteredEndpoints() { VertexSeq ends; - for (Vertex *vertex : *filtered_arrivals_) { + for (Vertex *vertex : filtered_arrivals_) { if (isEndpoint(vertex)) ends.push_back(vertex); } @@ -702,18 +736,18 @@ class SeedFaninsThruHierPin : public HierPinThruVisitor { public: SeedFaninsThruHierPin(Graph *graph, - Search *search); + Search *search); protected: virtual void visit(const Pin *drvr, - const Pin *load); + const Pin *load); Graph *graph_; Search *search_; }; SeedFaninsThruHierPin::SeedFaninsThruHierPin(Graph *graph, - Search *search) : + Search *search) : HierPinThruVisitor(), graph_(graph), search_(search) @@ -722,19 +756,23 @@ SeedFaninsThruHierPin::SeedFaninsThruHierPin(Graph *graph, void SeedFaninsThruHierPin::visit(const Pin *drvr, - const Pin *) + const Pin *) { Vertex *vertex, *bidirect_drvr_vertex; graph_->pinVertices(drvr, vertex, bidirect_drvr_vertex); - search_->seedArrival(vertex); + search_->arrivalIterator()->enqueue(vertex); if (bidirect_drvr_vertex) - search_->seedArrival(bidirect_drvr_vertex); + search_->arrivalIterator()->enqueue(bidirect_drvr_vertex); } void Search::seedFilterStarts() { - ExceptionPt *first_pt = filter_->firstPt(); + ExceptionPt *first_pt = nullptr; + if (filter_from_) + first_pt = filter_from_; + else if (filter_thrus_) + first_pt = (*filter_thrus_)[0]; if (first_pt) { PinSet first_pins = first_pt->allPins(network_); for (const Pin *pin : first_pins) { @@ -746,9 +784,9 @@ Search::seedFilterStarts() Vertex *vertex, *bidirect_drvr_vertex; graph_->pinVertices(pin, vertex, bidirect_drvr_vertex); if (vertex) - seedArrival(vertex); + arrival_iter_->enqueue(vertex); if (bidirect_drvr_vertex) - seedArrival(bidirect_drvr_vertex); + arrival_iter_->enqueue(bidirect_drvr_vertex); } } } @@ -762,18 +800,17 @@ Search::deleteVertexBefore(Vertex *vertex) if (arrivals_exist_) { deletePathsIncr(vertex); arrival_iter_->deleteVertexBefore(vertex); - invalid_arrivals_->erase(vertex); - filtered_arrivals_->erase(vertex); + invalid_arrivals_.erase(vertex); + filtered_arrivals_.erase(vertex); } if (requireds_exist_) { required_iter_->deleteVertexBefore(vertex); - invalid_requireds_->erase(vertex); - invalid_tns_->erase(vertex); + invalid_requireds_.erase(vertex); + invalid_tns_.erase(vertex); } - if (endpoints_) - endpoints_->erase(vertex); - if (invalid_endpoints_) - invalid_endpoints_->erase(vertex); + if (endpoints_initialized_) + endpoints_.erase(vertex); + invalid_endpoints_.erase(vertex); } void @@ -794,7 +831,7 @@ bool Search::arrivalsValid() { return arrivals_exist_ - && invalid_arrivals_->empty(); + && invalid_arrivals_.empty(); } void @@ -808,21 +845,20 @@ Search::arrivalsInvalid() deletePathGroups(); deletePaths(); deleteTags(); - genclks_->clear(); + for (const Mode *mode : modes_) + mode->genclks()->clear(); deleteFilter(); - arrivals_at_endpoints_exist_ = false; arrivals_seeded_ = false; requireds_exist_ = false; requireds_seeded_ = false; - clk_arrivals_valid_ = false; arrival_iter_->clear(); required_iter_->clear(); // No need to keep track of incremental updates any more. - invalid_arrivals_->clear(); - invalid_requireds_->clear(); + invalid_arrivals_.clear(); + invalid_requireds_.clear(); tns_exists_ = false; clearWorstSlack(); - invalid_tns_->clear(); + invalid_tns_.clear(); } } @@ -832,10 +868,10 @@ Search::requiredsInvalid() debugPrint(debug_, "search", 1, "requireds invalid"); requireds_exist_ = false; requireds_seeded_ = false; - invalid_requireds_->clear(); + invalid_requireds_.clear(); tns_exists_ = false; clearWorstSlack(); - invalid_tns_->clear(); + invalid_tns_.clear(); } void @@ -847,7 +883,7 @@ Search::arrivalInvalid(Vertex *vertex) if (!arrival_iter_->inQueue(vertex)) { // Lock for StaDelayCalcObserver called by delay calc threads. LockGuard lock(invalid_arrivals_lock_); - invalid_arrivals_->insert(vertex); + invalid_arrivals_.insert(vertex); } tnsInvalid(vertex); } @@ -926,7 +962,7 @@ Search::requiredInvalid(Vertex *vertex) if (!required_iter_->inQueue(vertex)) { // Lock for StaDelayCalcObserver called by delay calc threads. LockGuard lock(invalid_arrivals_lock_); - invalid_requireds_->insert(vertex); + invalid_requireds_.insert(vertex); } tnsInvalid(vertex); } @@ -937,20 +973,7 @@ Search::requiredInvalid(Vertex *vertex) void Search::findClkArrivals() { - if (!clk_arrivals_valid_) { - genclks_->ensureInsertionDelays(); - Stats stats(debug_, report_); - debugPrint(debug_, "search", 1, "find clk arrivals"); - arrival_iter_->clear(); - seedClkVertexArrivals(); - ClkArrivalSearchPred search_clk(this); - arrival_visitor_->init(false, &search_clk); - arrival_iter_->visitParallel(levelize_->maxLevel(), arrival_visitor_); - deleteTagsPrev(); - arrivals_exist_ = true; - stats.report("Find clk arrivals"); - } - clk_arrivals_valid_ = true; + findAllArrivals(false, true); } void @@ -961,112 +984,46 @@ Search::seedClkVertexArrivals() for (const Pin *pin : clk_pins) { Vertex *vertex, *bidirect_drvr_vertex; graph_->pinVertices(pin, vertex, bidirect_drvr_vertex); - seedClkVertexArrivals(pin, vertex); + arrival_iter_->enqueue(vertex); if (bidirect_drvr_vertex) - seedClkVertexArrivals(pin, bidirect_drvr_vertex); + arrival_iter_->enqueue(bidirect_drvr_vertex); } } -void -Search::seedClkVertexArrivals(const Pin *pin, - Vertex *vertex) -{ - TagGroupBldr tag_bldr(true, this); - tag_bldr.init(vertex); - genclks_->copyGenClkSrcPaths(vertex, &tag_bldr); - seedClkArrivals(pin, vertex, &tag_bldr); - setVertexArrivals(vertex, &tag_bldr); -} - Arrival Search::clockInsertion(const Clock *clk, - const Pin *pin, - const RiseFall *rf, - const MinMax *min_max, - const EarlyLate *early_late, - const PathAnalysisPt *path_ap) const + const Pin *pin, + const RiseFall *rf, + const MinMax *min_max, + const EarlyLate *early_late, + const Mode *mode) const { float insert; bool exists; - sdc_->clockInsertion(clk, pin, rf, min_max, early_late, insert, exists); + mode->sdc()->clockInsertion(clk, pin, rf, min_max, early_late, insert, exists); if (exists) return insert; else if (clk->isGeneratedWithPropagatedMaster()) - return genclks_->insertionDelay(clk, pin, rf, early_late, path_ap); + return mode->genclks()->insertionDelay(clk, pin, rf, early_late); else return 0.0; } //////////////////////////////////////////////////////////////// -void -Search::visitStartpoints(VertexVisitor *visitor) -{ - Instance *top_inst = network_->topInstance(); - InstancePinIterator *pin_iter = network_->pinIterator(top_inst); - while (pin_iter->hasNext()) { - Pin *pin = pin_iter->next(); - if (network_->direction(pin)->isAnyInput()) { - Vertex *vertex = graph_->pinDrvrVertex(pin); - visitor->visit(vertex); - } - } - delete pin_iter; - - for (const auto [pin, input_delays] : sdc_->inputDelayPinMap()) { - // Already hit these. - if (!network_->isTopLevelPort(pin)) { - Vertex *vertex = graph_->pinDrvrVertex(pin); - if (vertex) - visitor->visit(vertex); - } - } - - for (const Clock *clk : sdc_->clks()) { - for (const Pin *pin : clk->leafPins()) { - // Already hit these. - if (!network_->isTopLevelPort(pin)) { - Vertex *vertex = graph_->pinDrvrVertex(pin); - visitor->visit(vertex); - } - } - } - - // Register clk pins. - for (Vertex *vertex : *graph_->regClkVertices()) - visitor->visit(vertex); - - const PinSet &startpoints = sdc_->pathDelayInternalFrom(); - for (const Pin *pin : startpoints) { - Vertex *vertex = graph_->pinDrvrVertex(pin); - visitor->visit(vertex); - } -} - -void -Search::visitEndpoints(VertexVisitor *visitor) -{ - for (Vertex *end : *endpoints()) { - Pin *pin = end->pin(); - // Filter register clock pins (fails on set_max_delay -from clk_src). - if (!network_->isRegClkPin(pin) - || sdc_->isPathDelayInternalTo(pin)) - visitor->visit(end); - } -} - -//////////////////////////////////////////////////////////////// - void Search::findAllArrivals() { - findAllArrivals(true); + findAllArrivals(true, false); } void -Search::findAllArrivals(bool thru_latches) +Search::findAllArrivals(bool thru_latches, + bool clks_only) { - arrival_visitor_->init(false); + if (!clks_only) + enqueuePendingClkFanouts(); + arrival_visitor_->init(false, clks_only, eval_pred_); // Iterate until data arrivals at all latches stop changing. postpone_latch_outputs_ = true; for (int pass = 1; pass == 1 || (thru_latches && havePendingLatchOutputs()); pass++) { @@ -1081,19 +1038,19 @@ Search::findAllArrivals(bool thru_latches) bool Search::havePendingLatchOutputs() { - return !pending_latch_outputs_->empty(); + return !pending_latch_outputs_.empty(); } void Search::clearPendingLatchOutputs() { - pending_latch_outputs_->clear(); + pending_latch_outputs_.clear(); } void Search::enqueuePendingLatchOutputs() { - for (Vertex *latch_vertex : *pending_latch_outputs_) { + for (Vertex *latch_vertex : pending_latch_outputs_) { debugPrint(debug_, "search", 2, "enqueue latch output %s", latch_vertex->to_string(this).c_str()); arrival_iter_->enqueue(latch_vertex); @@ -1101,6 +1058,24 @@ Search::enqueuePendingLatchOutputs() clearPendingLatchOutputs(); } +void +Search::enqueuePendingClkFanouts() +{ + for (Vertex *vertex : pending_clk_endpoints_) { + debugPrint(debug_, "search", 2, "enqueue clk fanout %s", + vertex->to_string(this).c_str()); + arrival_iter_->enqueueAdjacentVertices(vertex, search_adj_); + } + pending_clk_endpoints_.clear(); +} + +void +Search::postponeClkFanouts(Vertex *vertex) +{ + LockGuard lock(pending_clk_endpoints_lock_); + pending_clk_endpoints_.insert(vertex); +} + void Search::findArrivals() { @@ -1110,7 +1085,7 @@ Search::findArrivals() void Search::findArrivals(Level level) { - arrival_visitor_->init(false); + arrival_visitor_->init(false, false, eval_pred_); findArrivals1(level); } @@ -1125,11 +1100,6 @@ Search::findArrivals1(Level level) if (arrival_count > 0) deleteUnusedTagGroups(); stats.report("Find arrivals"); - if (arrival_iter_->empty() - && invalid_arrivals_->empty()) { - clk_arrivals_valid_ = true; - arrivals_at_endpoints_exist_ = true; - } arrivals_exist_ = true; debugPrint(debug_, "search", 1, "found %d arrivals", arrival_count); } @@ -1138,7 +1108,8 @@ void Search::findArrivalsSeed() { if (!arrivals_seeded_) { - genclks_->ensureInsertionDelays(); + for (const Mode *mode : modes_) + mode->genclks()->ensureInsertionDelays(); arrival_iter_->clear(); required_iter_->clear(); seedArrivals(); @@ -1157,17 +1128,17 @@ ArrivalVisitor::ArrivalVisitor(const StaState *sta) : PathVisitor(nullptr, false, sta) { init0(); - init(true); + init(true, false, nullptr); } // Copy constructor. ArrivalVisitor::ArrivalVisitor(bool always_to_endpoints, - SearchPred *pred, - const StaState *sta) : + SearchPred *pred, + const StaState *sta) : PathVisitor(pred, true, sta) { init0(); - init(always_to_endpoints, pred); + init(always_to_endpoints, false, pred); } void @@ -1175,22 +1146,18 @@ ArrivalVisitor::init0() { tag_bldr_ = new TagGroupBldr(true, this); tag_bldr_no_crpr_ = new TagGroupBldr(false, this); - adj_pred_ = new SearchThru(tag_bldr_, this); -} - -void -ArrivalVisitor::init(bool always_to_endpoints) -{ - init(always_to_endpoints, search_ ? search_->evalPred() : nullptr); + adj_pred_ = new SearchAdj(tag_bldr_, this); } void ArrivalVisitor::init(bool always_to_endpoints, - SearchPred *pred) + bool clks_only, + SearchPred *pred) { always_to_endpoints_ = always_to_endpoints; + clks_only_ = clks_only; pred_ = pred; - crpr_active_ = crprActive(); + crpr_active_ = variables_->crprEnabled(); } @@ -1200,6 +1167,13 @@ ArrivalVisitor::copy() const return new ArrivalVisitor(always_to_endpoints_, pred_, this); } +void +ArrivalVisitor::copyState(const StaState *sta) +{ + StaState::copyState(sta); + adj_pred_->copyState(sta); +} + ArrivalVisitor::~ArrivalVisitor() { delete tag_bldr_; @@ -1225,41 +1199,18 @@ ArrivalVisitor::visit(Vertex *vertex) && !has_fanin_one_) tag_bldr_no_crpr_->init(vertex); - // Fanin paths are broken by path delays internal pin startpoints. - if (!sdc_->isPathDelayInternalFromBreak(pin)) { - visitFaninPaths(vertex); - if (crpr_active_ - && search_->crprPathPruningEnabled() - // No crpr for ideal clocks. - && tag_bldr_->hasPropagatedClk() - && !has_fanin_one_) - pruneCrprArrivals(); - } + visitFaninPaths(vertex); + if (crpr_active_ + && search_->crprPathPruningEnabled() + // No crpr for ideal clocks. + && tag_bldr_->hasPropagatedClk() + && !has_fanin_one_) + pruneCrprArrivals(); // Insert paths that originate here. - if (!network_->isTopLevelPort(pin) - && sdc_->hasInputDelay(pin)) - // set_input_delay on internal pin. - search_->seedInputSegmentArrival(pin, vertex, tag_bldr_); - if (sdc_->isPathDelayInternalFrom(pin)) - // set_min/max_delay -from internal pin. - search_->makeUnclkedPaths(vertex, false, true, tag_bldr_); - if (sdc_->isLeafPinClock(pin)) - // set_min/max_delay -to internal pin also a clock src. Bizzaroland. - // Re-seed the clock arrivals on top of the propagated paths. - search_->seedClkArrivals(pin, vertex, tag_bldr_); - // Register/latch clock pin that is not connected to a declared clock. - // Seed with unclocked tag, zero arrival and allow search thru reg - // clk->q edges. - // These paths are required to report path delays from unclocked registers - // For example, "set_max_delay -to" from an unclocked source register. - bool is_clk = tag_bldr_->hasClkTag(); - if (vertex->isRegClk() && !is_clk) { - debugPrint(debug_, "search", 2, "arrival seed unclked reg clk %s", - network_->pathName(pin)); - search_->makeUnclkedPaths(vertex, true, false, tag_bldr_); - } + seedArrivals(vertex); + bool is_clk = tag_bldr_->hasClkTag(); bool arrivals_changed = search_->arrivalsChanged(vertex, tag_bldr_); // If vertex is a latch data input arrival that changed from the // previous eval pass enqueue the latch outputs to be re-evaled on the @@ -1268,17 +1219,69 @@ ArrivalVisitor::visit(Vertex *vertex) && network_->isLatchData(pin)) search_->enqueueLatchDataOutputs(vertex); - if (!search_->arrivalsAtEndpointsExist() - || always_to_endpoints_ - || arrivals_changed) - search_->arrivalIterator()->enqueueAdjacentVertices(vertex, adj_pred_); + if ((always_to_endpoints_ + || arrivals_changed)) { + if (clks_only_ + && vertex->isRegClk()) { + debugPrint(debug_, "search", 3, "postponing clk fanout"); + search_->postponeClkFanouts(vertex); + } + else + search_->arrivalIterator()->enqueueAdjacentVertices(vertex, adj_pred_); + } if (arrivals_changed) { debugPrint(debug_, "search", 4, "arrivals changed"); search_->setVertexArrivals(vertex, tag_bldr_); search_->tnsInvalid(vertex); constrainedRequiredsInvalid(vertex, is_clk); } - enqueueRefPinInputDelays(pin); +} + +void +ArrivalVisitor::seedArrivals(Vertex *vertex) +{ + const Pin *pin = vertex->pin(); + bool is_clk = tag_bldr_->hasClkTag(); + for (const Mode *mode : modes_) { + const Sdc *sdc = mode->sdc(); + mode->genclks()->copyGenClkSrcPaths(vertex, tag_bldr_); + if (sdc->isLeafPinClock(pin)) + search_->seedClkArrivals(pin, mode, tag_bldr_); + if (search_->isInputArrivalSrchStart(vertex)) + search_->seedInputArrival(pin, vertex, mode, tag_bldr_); + // Do not apply input delay to bidir load vertices. + if (!(network_->direction(pin)->isBidirect() + && !vertex->isBidirectDriver()) + && !network_->isTopLevelPort(pin) + && sdc->hasInputDelay(pin)) + search_->seedInputSegmentArrival(pin, vertex, mode, tag_bldr_); + if (sdc->isPathDelayInternalFrom(pin) + && !sdc->isLeafPinClock(pin)) + // set_min/max_delay -from internal pin. + search_->makeUnclkedPaths(vertex, false, true, tag_bldr_, mode); + if (search_->isSrchRoot(vertex, mode)) { + bool is_reg_clk = vertex->isRegClk(); + if (is_reg_clk + // Internal roots isolated by disabled pins are seeded with no clock. + || (search_->unconstrainedPaths() + && !network_->isTopLevelPort(pin))) { + debugPrint(debug_, "search", 2, "arrival seed unclked root %s", + network_->pathName(pin)); + search_->makeUnclkedPaths(vertex, is_reg_clk, false, tag_bldr_, mode); + } + } + // Register/latch clock pin that is not connected to a declared clock. + // Seed with unclocked tag, zero arrival and allow search thru reg + // clk->q edges. + // These paths are required to report path delays from unclocked registers + // For example, "set_max_delay -to" from an unclocked source register. + if (vertex->isRegClk() && !is_clk) { + debugPrint(debug_, "search", 2, "arrival seed unclked reg clk %s", + network_->pathName(pin)); + search_->makeUnclkedPaths(vertex, true, false, tag_bldr_, mode); + } + enqueueRefPinInputDelays(pin, sdc); + } } // When a clock arrival changes, the required time changes for any @@ -1286,7 +1289,7 @@ ArrivalVisitor::visit(Vertex *vertex) // by the clock pin. void ArrivalVisitor::constrainedRequiredsInvalid(Vertex *vertex, - bool is_clk) + bool is_clk) { Pin *pin = vertex->pin(); if (network_->isLoad(pin) @@ -1294,36 +1297,39 @@ ArrivalVisitor::constrainedRequiredsInvalid(Vertex *vertex, if (is_clk && network_->isCheckClk(pin)) { VertexOutEdgeIterator edge_iter(vertex, graph_); while (edge_iter.hasNext()) { - Edge *edge = edge_iter.next(); - if (edge->role()->isTimingCheck()) { - Vertex *to_vertex = edge->to(graph_); - search_->requiredInvalid(to_vertex); - } + Edge *edge = edge_iter.next(); + if (edge->role()->isTimingCheck()) { + Vertex *to_vertex = edge->to(graph_); + search_->requiredInvalid(to_vertex); + } } } // Data checks (vertex does not need to be a clk). - DataCheckSet *data_checks = sdc_->dataChecksFrom(pin); - if (data_checks) { - for (DataCheck *data_check : *data_checks) { - Pin *to = data_check->to(); - search_->requiredInvalid(to); + for (const Mode *mode : modes_) { + const Sdc *sdc = mode->sdc(); + DataCheckSet *data_checks = sdc->dataChecksFrom(pin); + if (data_checks) { + for (DataCheck *data_check : *data_checks) { + Pin *to = data_check->to(); + search_->requiredInvalid(to); + } + } + + // Gated clocks. + if (is_clk && variables_->gatedClkChecksEnabled()) { + PinSet enable_pins = search_->gatedClk()->gatedClkEnables(vertex, mode); + for (const Pin *enable : enable_pins) + search_->requiredInvalid(enable); } - } - // Gated clocks. - if (is_clk && variables_->gatedClkChecksEnabled()) { - PinSet enable_pins(network_); - search_->gatedClk()->gatedClkEnables(vertex, enable_pins); - for (const Pin *enable : enable_pins) - search_->requiredInvalid(enable); } } } bool Search::arrivalsChanged(Vertex *vertex, - TagGroupBldr *tag_bldr) + TagGroupBldr *tag_bldr) { - Path *paths1 = graph_->paths(vertex); + Path *paths1 = vertex->paths(); if (paths1) { TagGroup *tag_group = tagGroup(vertex); if (tag_group == nullptr @@ -1343,25 +1349,24 @@ Search::arrivalsChanged(Vertex *vertex, return false; } else - return true; + return !tag_bldr->empty(); } bool ArrivalVisitor::visitFromToPath(const Pin * /* from_pin */, - Vertex *from_vertex, - const RiseFall *from_rf, - Tag *from_tag, - Path *from_path, + Vertex *from_vertex, + const RiseFall *from_rf, + Tag *from_tag, + Path *from_path, const Arrival &from_arrival, - Edge *edge, - TimingArc *arc, - ArcDelay arc_delay, - Vertex * /* to_vertex */, - const RiseFall *to_rf, - Tag *to_tag, - Arrival &to_arrival, - const MinMax *min_max, - const PathAnalysisPt *) + Edge *edge, + TimingArc *arc, + ArcDelay arc_delay, + Vertex * /* to_vertex */, + const RiseFall *to_rf, + Tag *to_tag, + Arrival &to_arrival, + const MinMax *min_max) { debugPrint(debug_, "search", 3, " %s", from_vertex->to_string(this).c_str()); @@ -1388,13 +1393,13 @@ ArrivalVisitor::visitFromToPath(const Pin * /* from_pin */, match ? delayAsString(match->arrival(), this) : "MIA"); tag_bldr_->setMatchPath(match, path_index, to_tag, to_arrival, from_path, edge, arc); if (crpr_active_ - && !has_fanin_one_ - && to_clk_info->hasCrprClkPin() - && !to_is_clk) { + && !has_fanin_one_ + && to_clk_info->hasCrprClkPin() + && !to_is_clk) { tag_bldr_no_crpr_->tagMatchPath(to_tag, match, path_index); if (match == nullptr - || delayGreater(to_arrival, match->arrival(), min_max, this)) { - tag_bldr_no_crpr_->setMatchPath(match, path_index, to_tag, to_arrival, + || delayGreater(to_arrival, match->arrival(), min_max, this)) { + tag_bldr_no_crpr_->setMatchPath(match, path_index, to_tag, to_arrival, from_path, edge, arc); } } @@ -1413,33 +1418,32 @@ ArrivalVisitor::pruneCrprArrivals() const ClkInfo *clk_info = tag->clkInfo(); bool deleted_tag = false; if (!tag->isClock() - && clk_info->hasCrprClkPin()) { - PathAnalysisPt *path_ap = tag->pathAnalysisPt(this); - const MinMax *min_max = path_ap->pathMinMax(); + && clk_info->hasCrprClkPin()) { + const MinMax *min_max = tag->minMax(); Path *path_no_crpr = tag_bldr_no_crpr_->tagMatchPath(tag); if (path_no_crpr) { Arrival max_arrival = path_no_crpr->arrival(); - const ClkInfo *clk_info_no_crpr = path_no_crpr->clkInfo(this); - Arrival max_crpr = crpr->maxCrpr(clk_info_no_crpr); - Arrival max_arrival_max_crpr = (min_max == MinMax::max()) - ? max_arrival - max_crpr - : max_arrival + max_crpr; - debugPrint(debug_, "search", 4, " cmp %s %s - %s = %s", + const ClkInfo *clk_info_no_crpr = path_no_crpr->clkInfo(this); + Arrival max_crpr = crpr->maxCrpr(clk_info_no_crpr); + Arrival max_arrival_max_crpr = (min_max == MinMax::max()) + ? max_arrival - max_crpr + : max_arrival + max_crpr; + debugPrint(debug_, "search", 4, " cmp %s %s - %s = %s", tag->to_string(this).c_str(), delayAsString(max_arrival, this), delayAsString(max_crpr, this), delayAsString(max_arrival_max_crpr, this)); Arrival arrival = tag_bldr_->arrival(path_index); - // Latch D->Q path uses enable min so crpr clk path min/max - // does not match the path min/max. - if (delayGreater(max_arrival_max_crpr, arrival, min_max, this) - && clk_info_no_crpr->crprClkPath(this)->minMax(this) - == clk_info->crprClkPath(this)->minMax(this)) { - debugPrint(debug_, "search", 3, " pruned %s", + // Latch D->Q path uses enable min so crpr clk path min/max + // does not match the path min/max. + if (delayGreater(max_arrival_max_crpr, arrival, min_max, this) + && clk_info_no_crpr->crprClkPath(this)->minMax(this) + == clk_info->crprClkPath(this)->minMax(this)) { + debugPrint(debug_, "search", 3, " pruned %s", tag->to_string(this).c_str()); path_itr = path_index_map.erase(path_itr); deleted_tag = true; - } + } } } if (!deleted_tag) @@ -1451,46 +1455,33 @@ ArrivalVisitor::pruneCrprArrivals() // reference pin as if there is a timing arc from the reference pin to // the input delay pin. void -ArrivalVisitor::enqueueRefPinInputDelays(const Pin *ref_pin) +ArrivalVisitor::enqueueRefPinInputDelays(const Pin *ref_pin, + const Sdc *sdc) { - InputDelaySet *input_delays = sdc_->refPinInputDelays(ref_pin); + InputDelaySet *input_delays = sdc->refPinInputDelays(ref_pin); if (input_delays) { + BfsFwdIterator *arrival_iter = search_->arrivalIterator(); for (InputDelay *input_delay : *input_delays) { const Pin *pin = input_delay->pin(); Vertex *vertex, *bidirect_drvr_vertex; graph_->pinVertices(pin, vertex, bidirect_drvr_vertex); - seedInputDelayArrival(pin, vertex, input_delay); + arrival_iter->enqueue(vertex); if (bidirect_drvr_vertex) - seedInputDelayArrival(pin, bidirect_drvr_vertex, input_delay); + arrival_iter->enqueue(bidirect_drvr_vertex); } } } -void -ArrivalVisitor::seedInputDelayArrival(const Pin *pin, - Vertex *vertex, - InputDelay *input_delay) -{ - TagGroupBldr tag_bldr(true, this); - tag_bldr.init(vertex); - search_->genclks()->copyGenClkSrcPaths(vertex, &tag_bldr); - search_->seedInputDelayArrival(pin, vertex, input_delay, - !network_->isTopLevelPort(pin), &tag_bldr); - search_->setVertexArrivals(vertex, &tag_bldr); - search_->arrivalIterator()->enqueueAdjacentVertices(vertex, - search_->searchAdj()); -} - void Search::enqueueLatchDataOutputs(Vertex *vertex) { - VertexOutEdgeIterator out_edge_iter(vertex, graph_); - while (out_edge_iter.hasNext()) { - Edge *out_edge = out_edge_iter.next(); - if (latches_->isLatchDtoQ(out_edge)) { - Vertex *out_vertex = out_edge->to(graph_); + VertexOutEdgeIterator edge_iter(vertex, graph_); + while (edge_iter.hasNext()) { + Edge *edge = edge_iter.next(); + if (edge->role() == TimingRole::latchDtoQ()) { + Vertex *out_vertex = edge->to(graph_); LockGuard lock(pending_latch_outputs_lock_); - pending_latch_outputs_->insert(out_vertex); + pending_latch_outputs_.insert(out_vertex); } } } @@ -1499,31 +1490,34 @@ void Search::enqueueLatchOutput(Vertex *vertex) { LockGuard lock(pending_latch_outputs_lock_); - pending_latch_outputs_->insert(vertex); + pending_latch_outputs_.insert(vertex); } void Search::seedArrivals() { - VertexSet vertices(graph_); + VertexSet vertices = makeVertexSet(this); findClockVertices(vertices); findRootVertices(vertices); findInputDrvrVertices(vertices); for (Vertex *vertex : vertices) - seedArrival(vertex); + arrival_iter_->enqueue(vertex); } void Search::findClockVertices(VertexSet &vertices) { - for (const Clock *clk : sdc_->clks()) { - for (const Pin *pin : clk->leafPins()) { - Vertex *vertex, *bidirect_drvr_vertex; - graph_->pinVertices(pin, vertex, bidirect_drvr_vertex); - vertices.insert(vertex); - if (bidirect_drvr_vertex) - vertices.insert(bidirect_drvr_vertex); + for (const Mode *mode : modes_) { + const Sdc *sdc = mode->sdc(); + for (const Clock *clk : sdc->clocks()) { + for (const Pin *pin : clk->leafPins()) { + Vertex *vertex, *bidirect_drvr_vertex; + graph_->pinVertices(pin, vertex, bidirect_drvr_vertex); + vertices.insert(vertex); + if (bidirect_drvr_vertex) + vertices.insert(bidirect_drvr_vertex); + } } } } @@ -1531,166 +1525,124 @@ Search::findClockVertices(VertexSet &vertices) void Search::seedInvalidArrivals() { - for (Vertex *vertex : *invalid_arrivals_) - seedArrival(vertex); - invalid_arrivals_->clear(); -} - -void -Search::seedArrival(Vertex *vertex) -{ - const Pin *pin = vertex->pin(); - if (sdc_->isLeafPinClock(pin)) { - TagGroupBldr tag_bldr(true, this); - tag_bldr.init(vertex); - genclks_->copyGenClkSrcPaths(vertex, &tag_bldr); - seedClkArrivals(pin, vertex, &tag_bldr); - // Clock pin may also have input arrivals from other clocks. - seedInputArrival(pin, vertex, &tag_bldr); - setVertexArrivals(vertex, &tag_bldr); - } - else if (isInputArrivalSrchStart(vertex)) { - TagGroupBldr tag_bldr(true, this); - tag_bldr.init(vertex); - genclks_->copyGenClkSrcPaths(vertex, &tag_bldr); - seedInputArrival(pin, vertex, &tag_bldr); - setVertexArrivals(vertex, &tag_bldr); - if (!tag_bldr.empty()) - // Only search downstream if there were non-false paths from here. - arrival_iter_->enqueueAdjacentVertices(vertex, search_adj_); - } - else if (levelize_->isRoot(vertex)) { - bool is_reg_clk = vertex->isRegClk(); - if (is_reg_clk - // Internal roots isolated by disabled pins are seeded with no clock. - || (unconstrained_paths_ - && !network_->isTopLevelPort(pin))) { - debugPrint(debug_, "search", 2, "arrival seed unclked root %s", - network_->pathName(pin)); - TagGroupBldr tag_bldr(true, this); - tag_bldr.init(vertex); - genclks_->copyGenClkSrcPaths(vertex, &tag_bldr); - if (makeUnclkedPaths(vertex, is_reg_clk, false, &tag_bldr)) - // Only search downstream if there are no false paths from here. - arrival_iter_->enqueueAdjacentVertices(vertex, search_adj_); - setVertexArrivals(vertex, &tag_bldr); - } - else { - deletePathsIncr(vertex); - if (search_adj_->searchFrom(vertex)) - arrival_iter_->enqueueAdjacentVertices(vertex, search_adj_); - } - } - else { - debugPrint(debug_, "search", 4, "arrival enqueue %s %u", - network_->pathName(pin), - vertex->level()); + for (Vertex *vertex : invalid_arrivals_) arrival_iter_->enqueue(vertex); - } + invalid_arrivals_.clear(); } // Find all of the clock leaf pins. void Search::findClkVertexPins(PinSet &clk_pins) { - for (const Clock *clk : sdc_->clks()) { - for (const Pin *pin : clk->leafPins()) { - clk_pins.insert(pin); + for (Scene *scene : scenes_) { + const Sdc *sdc = scene->sdc(); + for (const Clock *clk : sdc->clocks()) { + for (const Pin *pin : clk->leafPins()) { + clk_pins.insert(pin); + } } } } void Search::seedClkArrivals(const Pin *pin, - Vertex *vertex, - TagGroupBldr *tag_bldr) + const Mode *mode, + TagGroupBldr *tag_bldr) { - for (const Clock *clk : *sdc_->findLeafPinClocks(pin)) { - debugPrint(debug_, "search", 2, "arrival seed clk %s pin %s", - clk->name(), network_->pathName(pin)); - for (PathAnalysisPt *path_ap : corners_->pathAnalysisPts()) { - const MinMax *min_max = path_ap->pathMinMax(); - for (const RiseFall *rf : RiseFall::range()) { - const ClockEdge *clk_edge = clk->edge(rf); - const EarlyLate *early_late = min_max; - if (clk->isGenerated() - && clk->masterClk() == nullptr) - seedClkDataArrival(pin, rf, clk, clk_edge, min_max, path_ap, - 0.0, tag_bldr); - else { - Arrival insertion = clockInsertion(clk, pin, rf, min_max, - early_late, path_ap); - seedClkArrival(pin, rf, clk, clk_edge, min_max, path_ap, - insertion, tag_bldr); - } + const Sdc *sdc = mode->sdc(); + ClockSet *clks = sdc->findLeafPinClocks(pin); + if (clks) { + for (const Clock *clk : *clks) { + debugPrint(debug_, "search", 2, "arrival seed clk %s/%s pin %s", + mode->name().c_str(), + clk->name(), + network_->pathName(pin)); + for (Scene *scene : mode->scenes()) { + for (const MinMax *min_max : MinMax::range()) { + for (const RiseFall *rf : RiseFall::range()) { + const ClockEdge *clk_edge = clk->edge(rf); + const EarlyLate *early_late = min_max; + if (clk->isGenerated() + && clk->masterClk() == nullptr) + seedClkDataArrival(pin, rf, clk, clk_edge, min_max, + 0.0, scene, tag_bldr); + else { + Arrival insertion = clockInsertion(clk, pin, rf, min_max, + early_late, mode); + seedClkArrival(pin, rf, clk, clk_edge, min_max, + insertion, scene, tag_bldr); + } + } + } } } - arrival_iter_->enqueueAdjacentVertices(vertex, search_adj_); } } void Search::seedClkArrival(const Pin *pin, - const RiseFall *rf, - const Clock *clk, - const ClockEdge *clk_edge, - const MinMax *min_max, - const PathAnalysisPt *path_ap, - Arrival insertion, - TagGroupBldr *tag_bldr) + const RiseFall *rf, + const Clock *clk, + const ClockEdge *clk_edge, + const MinMax *min_max, + Arrival insertion, + Scene *scene, + TagGroupBldr *tag_bldr) { + Sdc *sdc = scene->sdc(); bool is_propagated = false; float latency = 0.0; bool latency_exists; // Check for clk pin latency. - sdc_->clockLatency(clk, pin, rf, min_max, - latency, latency_exists); + sdc->clockLatency(clk, pin, rf, min_max, + latency, latency_exists); if (!latency_exists) { // Check for clk latency (lower priority). - sdc_->clockLatency(clk, rf, min_max, - latency, latency_exists); + sdc->clockLatency(clk, rf, min_max, + latency, latency_exists); if (latency_exists) { // Propagated pin overrides latency on clk. - if (sdc_->isPropagatedClock(pin)) { - latency = 0.0; - latency_exists = false; - is_propagated = true; + if (sdc->isPropagatedClock(pin)) { + latency = 0.0; + latency_exists = false; + is_propagated = true; } } else - is_propagated = sdc_->isPropagatedClock(pin) - || clk->isPropagated(); + is_propagated = sdc->isPropagatedClock(pin) + || clk->isPropagated(); } - ClockUncertainties *uncertainties = sdc_->clockUncertainties(pin); + const ClockUncertainties *uncertainties = sdc->clockUncertainties(pin); if (uncertainties == nullptr) uncertainties = clk->uncertainties(); // Propagate liberty "pulse_clock" transition to transitive fanout. LibertyPort *port = network_->libertyPort(pin); const RiseFall *pulse_clk_sense = (port ? port->pulseClkSense() : nullptr); - const ClkInfo *clk_info = findClkInfo(clk_edge, pin, is_propagated, nullptr, false, - pulse_clk_sense, insertion, latency, - uncertainties, path_ap, nullptr); + const ClkInfo *clk_info = findClkInfo(scene, clk_edge, pin, is_propagated, + nullptr, false, + pulse_clk_sense, insertion, latency, + uncertainties, min_max, nullptr); // Only false_paths -from apply to clock tree pins. ExceptionStateSet *states = nullptr; - sdc_->exceptionFromClkStates(pin,rf,clk,rf,min_max,states); - Tag *tag = findTag(rf, path_ap, clk_info, true, nullptr, false, states, - true, nullptr); + sdc->exceptionFromClkStates(pin,rf,clk,rf,min_max,states); + Tag *tag = findTag(scene, rf, min_max, clk_info, true, nullptr, false, + states, true, nullptr); Arrival arrival(clk_edge->time() + insertion); tag_bldr->setArrival(tag, arrival); } void Search::seedClkDataArrival(const Pin *pin, - const RiseFall *rf, - const Clock *clk, - const ClockEdge *clk_edge, - const MinMax *min_max, - const PathAnalysisPt *path_ap, - Arrival insertion, - TagGroupBldr *tag_bldr) -{ - Tag *tag = clkDataTag(pin, clk, rf, clk_edge, insertion, min_max, path_ap); + const RiseFall *rf, + const Clock *clk, + const ClockEdge *clk_edge, + const MinMax *min_max, + Arrival insertion, + Scene *scene, + TagGroupBldr *tag_bldr) +{ + Tag *tag = clkDataTag(pin, clk, rf, clk_edge, insertion, min_max, scene); if (tag) { // Data arrivals include insertion delay. Arrival arrival(clk_edge->time() + insertion); @@ -1700,21 +1652,22 @@ Search::seedClkDataArrival(const Pin *pin, Tag * Search::clkDataTag(const Pin *pin, - const Clock *clk, - const RiseFall *rf, - const ClockEdge *clk_edge, - Arrival insertion, - const MinMax *min_max, - const PathAnalysisPt *path_ap) + const Clock *clk, + const RiseFall *rf, + const ClockEdge *clk_edge, + Arrival insertion, + const MinMax *min_max, + Scene *scene) { + Sdc *sdc = scene->sdc(); ExceptionStateSet *states = nullptr; - if (sdc_->exceptionFromStates(pin, rf, clk, rf, min_max, states)) { + if (sdc->exceptionFromStates(pin, rf, clk, rf, min_max, states)) { bool is_propagated = (clk->isPropagated() - || sdc_->isPropagatedClock(pin)); - const ClkInfo *clk_info = findClkInfo(clk_edge, pin, is_propagated, - insertion, path_ap); - return findTag(rf, path_ap, clk_info, false, nullptr, false, states, - true, nullptr); + || sdc->isPropagatedClock(pin)); + const ClkInfo *clk_info = findClkInfo(scene, clk_edge, pin, is_propagated, + insertion, min_max); + return findTag(scene, rf, min_max, clk_info, false, nullptr, false, + states, true, nullptr); } else return nullptr; @@ -1724,41 +1677,63 @@ Search::clkDataTag(const Pin *pin, bool Search::makeUnclkedPaths(Vertex *vertex, - bool is_segment_start, - bool require_exception, - TagGroupBldr *tag_bldr) + bool is_segment_start, + bool require_exception, + TagGroupBldr *tag_bldr, + const Mode *mode) { bool search_from = false; const Pin *pin = vertex->pin(); - for (PathAnalysisPt *path_ap : corners_->pathAnalysisPts()) { - const MinMax *min_max = path_ap->pathMinMax(); - for (const RiseFall *rf : RiseFall::range()) { - Tag *tag = fromUnclkedInputTag(pin, rf, min_max, path_ap, - is_segment_start, - require_exception); - if (tag) { - tag_bldr->setArrival(tag, delay_zero); - search_from = true; + for (Scene *scene : mode->scenes()) { + for (const MinMax *min_max : MinMax::range()) { + for (const RiseFall *rf : RiseFall::range()) { + Tag *tag = fromUnclkedInputTag(pin, rf, min_max, is_segment_start, + require_exception, scene); + if (tag) { + tag_bldr->setArrival(tag, delay_zero); + search_from = true; + } } } } return search_from; } -// Find graph roots and input ports that do NOT have arrivals. void Search::findRootVertices(VertexSet &vertices) { - for (Vertex *vertex : levelize_->roots()) { - const Pin *pin = vertex->pin(); - if (!sdc_->isLeafPinClock(pin) - && !sdc_->hasInputDelay(pin) - && !vertex->isConstant()) { - vertices.insert(vertex); + VertexIterator vertex_iter(graph_); + while (vertex_iter.hasNext()) { + Vertex *vertex = vertex_iter.next(); + for (Mode *mode : modes_) { + if (isSrchRoot(vertex, mode)) { + vertices.insert(vertex); + break; + } } } } +bool +Search::isSrchRoot(Vertex *vertex, + const Mode *mode) const +{ + if (!eval_pred_->searchFrom(vertex, mode)) + return false; + else { + VertexInEdgeIterator edge_iter(vertex, graph_); + while (edge_iter.hasNext()) { + Edge *edge = edge_iter.next(); + Vertex *from_vertex = edge->from(graph_); + if (!edge->role()->isTimingCheck() + && (eval_pred_->searchFrom(from_vertex, mode) + && eval_pred_->searchThru(edge, mode))) + return false; + } + } + return true; +} + void Search::findInputDrvrVertices(VertexSet &vertices) { @@ -1772,13 +1747,6 @@ Search::findInputDrvrVertices(VertexSet &vertices) delete pin_iter; } -bool -Search::isSegmentStart(const Pin *pin) -{ - return sdc_->isInputDelayInternal(pin) - && !sdc_->isLeafPinClock(pin); -} - bool Search::isInputArrivalSrchStart(Vertex *vertex) { @@ -1786,103 +1754,65 @@ Search::isInputArrivalSrchStart(Vertex *vertex) PortDirection *dir = network_->direction(pin); bool is_top_level_port = network_->isTopLevelPort(pin); return (is_top_level_port - && (dir->isInput() - || (dir->isBidirect() && vertex->isBidirectDriver()))) ; -} - -// Seed input arrivals clocked by clks. -void -Search::seedInputArrivals(ClockSet *clks) -{ - // Input arrivals can be on internal pins, so iterate over the pins - // that have input arrivals rather than the top level input pins. - for (const auto [pin, input_delays] : sdc_->inputDelayPinMap()) { - if (!sdc_->isLeafPinClock(pin)) { - Vertex *vertex = graph_->pinDrvrVertex(pin); - seedInputArrival(pin, vertex, clks); - } - } + && (dir->isInput() + || (dir->isBidirect() && vertex->isBidirectDriver()))) ; } void Search::seedInputArrival(const Pin *pin, - Vertex *vertex, - ClockSet *wrt_clks) + Vertex *vertex, + const Mode *mode, + TagGroupBldr *tag_bldr) { - bool has_arrival = false; - // There can be multiple arrivals for a pin with wrt different clocks. - TagGroupBldr tag_bldr(true, this); - tag_bldr.init(vertex); - genclks_->copyGenClkSrcPaths(vertex, &tag_bldr); - InputDelaySet *input_delays = sdc_->inputDelaysLeafPin(pin); - if (input_delays) { - for (InputDelay *input_delay : *input_delays) { - Clock *input_clk = input_delay->clock(); - ClockSet *pin_clks = sdc_->findLeafPinClocks(pin); - if (input_clk && wrt_clks->hasKey(input_clk) - // Input arrivals wrt a clock source pin is the insertion - // delay (source latency), but arrivals wrt other clocks - // propagate. - && (pin_clks == nullptr - || !pin_clks->hasKey(input_clk))) { - seedInputDelayArrival(pin, vertex, input_delay, false, &tag_bldr); - has_arrival = true; - } - } - if (has_arrival) - setVertexArrivals(vertex, &tag_bldr); - } -} - -void -Search::seedInputArrival(const Pin *pin, - Vertex *vertex, - TagGroupBldr *tag_bldr) -{ - if (sdc_->hasInputDelay(pin)) - seedInputArrival1(pin, vertex, false, tag_bldr); - else if (!sdc_->isLeafPinClock(pin)) + const Sdc *sdc = mode->sdc(); + if (sdc->hasInputDelay(pin)) + seedInputArrival1(pin, vertex, false, mode, tag_bldr); + else if (!sdc->isLeafPinClock(pin)) // Seed inputs without set_input_delays. - seedInputDelayArrival(pin, vertex, nullptr, false, tag_bldr); + seedInputDelayArrival(pin, vertex, nullptr, false, mode, tag_bldr); } void Search::seedInputSegmentArrival(const Pin *pin, - Vertex *vertex, - TagGroupBldr *tag_bldr) + Vertex *vertex, + const Mode *mode, + TagGroupBldr *tag_bldr) { - seedInputArrival1(pin, vertex, true, tag_bldr); + seedInputArrival1(pin, vertex, true, mode, tag_bldr); } void Search::seedInputArrival1(const Pin *pin, - Vertex *vertex, - bool is_segment_start, - TagGroupBldr *tag_bldr) + Vertex *vertex, + bool is_segment_start, + const Mode *mode, + TagGroupBldr *tag_bldr) { // There can be multiple arrivals for a pin with wrt different clocks. - InputDelaySet *input_delays = sdc_->inputDelaysLeafPin(pin); + const Sdc *sdc = mode->sdc(); + InputDelaySet *input_delays = sdc->inputDelaysLeafPin(pin); if (input_delays) { for (InputDelay *input_delay : *input_delays) { Clock *input_clk = input_delay->clock(); - ClockSet *pin_clks = sdc_->findLeafPinClocks(pin); + ClockSet *pin_clks = sdc->findLeafPinClocks(pin); // Input arrival wrt a clock source pin is the clock insertion // delay (source latency), but arrivals wrt other clocks // propagate. if (pin_clks == nullptr - || !pin_clks->hasKey(input_clk)) - seedInputDelayArrival(pin, vertex, input_delay, is_segment_start, - tag_bldr); + || !pin_clks->contains(input_clk)) + seedInputDelayArrival(pin, vertex, input_delay, is_segment_start, + mode, tag_bldr); } } } void Search::seedInputDelayArrival(const Pin *pin, - Vertex *vertex, - InputDelay *input_delay, - bool is_segment_start, - TagGroupBldr *tag_bldr) + Vertex *vertex, + InputDelay *input_delay, + bool is_segment_start, + const Mode *mode, + TagGroupBldr *tag_bldr) { debugPrint(debug_, "search", 2, input_delay @@ -1891,46 +1821,50 @@ Search::seedInputDelayArrival(const Pin *pin, vertex->to_string(this).c_str()); const ClockEdge *clk_edge = nullptr; const Pin *ref_pin = nullptr; + const Sdc *sdc = mode->sdc(); if (input_delay) { clk_edge = input_delay->clkEdge(); if (clk_edge == nullptr - && variables_->useDefaultArrivalClock()) - clk_edge = sdc_->defaultArrivalClockEdge(); + && variables_->useDefaultArrivalClock()) + clk_edge = sdc->defaultArrivalClockEdge(); ref_pin = input_delay->refPin(); } else if (variables_->useDefaultArrivalClock()) - clk_edge = sdc_->defaultArrivalClockEdge(); + clk_edge = sdc->defaultArrivalClockEdge(); if (ref_pin) { Vertex *ref_vertex = graph_->pinLoadVertex(ref_pin); - for (PathAnalysisPt *path_ap : corners_->pathAnalysisPts()) { - const MinMax *min_max = path_ap->pathMinMax(); - const RiseFall *ref_rf = input_delay->refTransition(); - const Clock *clk = input_delay->clock(); - VertexPathIterator ref_path_iter(ref_vertex, ref_rf, path_ap, this); - while (ref_path_iter.hasNext()) { - Path *ref_path = ref_path_iter.next(); - if (ref_path->isClock(this) - && (clk == nullptr - || ref_path->clock(this) == clk)) { - float ref_arrival, ref_insertion, ref_latency; - inputDelayRefPinArrival(ref_path, ref_path->clkEdge(this), min_max, - ref_arrival, ref_insertion, ref_latency); - seedInputDelayArrival(pin, input_delay, ref_path->clkEdge(this), - ref_arrival, ref_insertion, ref_latency, - is_segment_start, min_max, path_ap, tag_bldr); - } + for (Scene *scene : mode->scenes()) { + for (const MinMax *min_max : MinMax::range()) { + const RiseFall *ref_rf = input_delay->refTransition(); + const Clock *clk = input_delay->clock(); + VertexPathIterator ref_path_iter(ref_vertex, scene, min_max, ref_rf, this); + while (ref_path_iter.hasNext()) { + Path *ref_path = ref_path_iter.next(); + if (ref_path->isClock(this) + && (clk == nullptr + || ref_path->clock(this) == clk)) { + float ref_arrival, ref_insertion, ref_latency; + inputDelayRefPinArrival(ref_path, ref_path->clkEdge(this), min_max, + sdc, ref_arrival, ref_insertion, + ref_latency); + seedInputDelayArrival(pin, input_delay, ref_path->clkEdge(this), + ref_arrival, ref_insertion, ref_latency, + is_segment_start, min_max, scene, tag_bldr); + } + } } } } else { - for (PathAnalysisPt *path_ap : corners_->pathAnalysisPts()) { - const MinMax *min_max = path_ap->pathMinMax(); + for (const MinMax *min_max : MinMax::range()) { float clk_arrival, clk_insertion, clk_latency; - inputDelayClkArrival(input_delay, clk_edge, min_max, path_ap, - clk_arrival, clk_insertion, clk_latency); - seedInputDelayArrival(pin, input_delay, clk_edge, - clk_arrival, clk_insertion, clk_latency, - is_segment_start, min_max, path_ap, tag_bldr); + inputDelayClkArrival(input_delay, clk_edge, min_max, mode, + clk_arrival, clk_insertion, clk_latency); + for (Scene *scene : mode->scenes()) { + seedInputDelayArrival(pin, input_delay, clk_edge, + clk_arrival, clk_insertion, clk_latency, + is_segment_start, min_max, scene, tag_bldr); + } } } } @@ -1939,12 +1873,13 @@ Search::seedInputDelayArrival(const Pin *pin, // from the clock source to the reference pin. void Search::inputDelayRefPinArrival(Path *ref_path, - const ClockEdge *clk_edge, - const MinMax *min_max, - // Return values. - float &ref_arrival, - float &ref_insertion, - float &ref_latency) + const ClockEdge *clk_edge, + const MinMax *min_max, + const Sdc *sdc, + // Return values. + float &ref_arrival, + float &ref_insertion, + float &ref_latency) { Clock *clk = clk_edge->clock(); if (clk->isPropagated()) { @@ -1958,7 +1893,7 @@ Search::inputDelayRefPinArrival(Path *ref_path, const EarlyLate *early_late = min_max; // Input delays from ideal clk reference pins include clock // insertion delay but not latency. - ref_insertion = sdc_->clockInsertion(clk, clk_rf, min_max, early_late); + ref_insertion = sdc->clockInsertion(clk, clk_rf, min_max, early_late); ref_arrival = clk_edge->time() + ref_insertion; ref_latency = 0.0; } @@ -1966,15 +1901,15 @@ Search::inputDelayRefPinArrival(Path *ref_path, void Search::seedInputDelayArrival(const Pin *pin, - InputDelay *input_delay, - const ClockEdge *clk_edge, - float clk_arrival, - float clk_insertion, - float clk_latency, - bool is_segment_start, - const MinMax *min_max, - PathAnalysisPt *path_ap, - TagGroupBldr *tag_bldr) + InputDelay *input_delay, + const ClockEdge *clk_edge, + float clk_arrival, + float clk_insertion, + float clk_latency, + bool is_segment_start, + const MinMax *min_max, + Scene *scene, + TagGroupBldr *tag_bldr) { for (const RiseFall *rf : RiseFall::range()) { if (input_delay) { @@ -1982,45 +1917,46 @@ Search::seedInputDelayArrival(const Pin *pin, bool exists; input_delay->delays()->value(rf, min_max, delay, exists); if (exists) - seedInputDelayArrival(pin, rf, clk_arrival + delay, - input_delay, clk_edge, - clk_insertion, clk_latency, is_segment_start, - min_max, path_ap, tag_bldr); + seedInputDelayArrival(pin, rf, clk_arrival + delay, + input_delay, clk_edge, + clk_insertion, clk_latency, is_segment_start, + min_max, scene, tag_bldr); } else seedInputDelayArrival(pin, rf, 0.0, nullptr, clk_edge, - clk_insertion, clk_latency, is_segment_start, - min_max, path_ap, tag_bldr); + clk_insertion, clk_latency, is_segment_start, + min_max, scene, tag_bldr); } } void Search::seedInputDelayArrival(const Pin *pin, - const RiseFall *rf, - float arrival, - InputDelay *input_delay, - const ClockEdge *clk_edge, - float clk_insertion, - float clk_latency, - bool is_segment_start, - const MinMax *min_max, - PathAnalysisPt *path_ap, - TagGroupBldr *tag_bldr) + const RiseFall *rf, + float arrival, + InputDelay *input_delay, + const ClockEdge *clk_edge, + float clk_insertion, + float clk_latency, + bool is_segment_start, + const MinMax *min_max, + Scene *scene, + TagGroupBldr *tag_bldr) { Tag *tag = inputDelayTag(pin, rf, clk_edge, clk_insertion, clk_latency, - input_delay, is_segment_start, min_max, path_ap); + input_delay, is_segment_start, min_max, scene); if (tag) tag_bldr->setArrival(tag, arrival); } void Search::inputDelayClkArrival(InputDelay *input_delay, - const ClockEdge *clk_edge, - const MinMax *min_max, - const PathAnalysisPt *path_ap, - // Return values. - float &clk_arrival, float &clk_insertion, - float &clk_latency) + const ClockEdge *clk_edge, + const MinMax *min_max, + const Mode *mode, + // Return values. + float &clk_arrival, + float &clk_insertion, + float &clk_latency) { clk_arrival = 0.0; clk_insertion = 0.0; @@ -2032,13 +1968,13 @@ Search::inputDelayClkArrival(InputDelay *input_delay, if (!input_delay->sourceLatencyIncluded()) { const EarlyLate *early_late = min_max; clk_insertion = delayAsFloat(clockInsertion(clk, clk->defaultPin(), - clk_rf, min_max, early_late, - path_ap)); + clk_rf, min_max, + early_late, mode)); clk_arrival += clk_insertion; } if (!clk->isPropagated() - && !input_delay->networkLatencyIncluded()) { - clk_latency = sdc_->clockLatency(clk, clk_rf, min_max); + && !input_delay->networkLatencyIncluded()) { + clk_latency = mode->sdc()->clockLatency(clk, clk_rf, min_max); clk_arrival += clk_latency; } } @@ -2046,14 +1982,14 @@ Search::inputDelayClkArrival(InputDelay *input_delay, Tag * Search::inputDelayTag(const Pin *pin, - const RiseFall *rf, - const ClockEdge *clk_edge, - float clk_insertion, - float clk_latency, - InputDelay *input_delay, - bool is_segment_start, - const MinMax *min_max, - const PathAnalysisPt *path_ap) + const RiseFall *rf, + const ClockEdge *clk_edge, + float clk_insertion, + float clk_latency, + InputDelay *input_delay, + bool is_segment_start, + const MinMax *min_max, + Scene *scene) { Clock *clk = nullptr; const Pin *clk_pin = nullptr; @@ -2068,22 +2004,24 @@ Search::inputDelayTag(const Pin *pin, clk_uncertainties = clk->uncertainties(); } + Sdc *sdc = scene->sdc(); ExceptionStateSet *states = nullptr; Tag *tag = nullptr; - if (sdc_->exceptionFromStates(pin,rf,clk,clk_rf,min_max,states)) { - const ClkInfo *clk_info = findClkInfo(clk_edge, clk_pin, is_propagated, nullptr, - false, nullptr, clk_insertion, clk_latency, - clk_uncertainties, path_ap, nullptr); - tag = findTag(rf, path_ap, clk_info, false, input_delay, is_segment_start, - states, true, nullptr); + if (sdc->exceptionFromStates(pin,rf,clk,clk_rf,min_max,states)) { + const ClkInfo *clk_info = findClkInfo(scene, clk_edge, clk_pin, + is_propagated, nullptr, + false, nullptr, clk_insertion, clk_latency, + clk_uncertainties, min_max, nullptr); + tag = findTag(scene, rf, min_max, clk_info, false, + input_delay, is_segment_start, states, true, nullptr); } if (tag) { const ClkInfo *clk_info = tag->clkInfo(); // Check for state changes on existing tag exceptions (pending -thru pins). tag = mutateTag(tag, pin, rf, false, clk_info, - pin, rf, false, false, is_segment_start, clk_info, - input_delay, min_max, path_ap, nullptr); + pin, rf, false, false, is_segment_start, clk_info, + input_delay, nullptr); } return tag; } @@ -2099,14 +2037,14 @@ PathVisitor::PathVisitor(const StaState *sta) : } PathVisitor::PathVisitor(SearchPred *pred, - bool make_tag_cache, - const StaState *sta) : + bool make_tag_cache, + const StaState *sta) : StaState(sta), pred_(pred), tag_cache_(make_tag_cache - ? new TagSet(128, TagSet::hasher(sta), TagSet::key_equal(sta)) - : nullptr) + ? new TagSet(128, TagSet::hasher(sta), TagSet::key_equal(sta)) + : nullptr) { } @@ -2118,19 +2056,14 @@ PathVisitor::~PathVisitor() void PathVisitor::visitFaninPaths(Vertex *to_vertex) { - if (pred_->searchTo(to_vertex)) { - VertexInEdgeIterator edge_iter(to_vertex, graph_); - while (edge_iter.hasNext()) { - Edge *edge = edge_iter.next(); - Vertex *from_vertex = edge->from(graph_); - const Pin *from_pin = from_vertex->pin(); - if (pred_->searchFrom(from_vertex) - && pred_->searchThru(edge)) { - const Pin *to_pin = to_vertex->pin(); - if (!visitEdge(from_pin, from_vertex, edge, to_pin, to_vertex)) - break; - } - } + VertexInEdgeIterator edge_iter(to_vertex, graph_); + while (edge_iter.hasNext()) { + Edge *edge = edge_iter.next(); + Vertex *from_vertex = edge->from(graph_); + const Pin *from_pin = from_vertex->pin(); + const Pin *to_pin = to_vertex->pin(); + if (!visitEdge(from_pin, from_vertex, edge, to_pin, to_vertex)) + break; } } @@ -2138,49 +2071,49 @@ void PathVisitor::visitFanoutPaths(Vertex *from_vertex) { const Pin *from_pin = from_vertex->pin(); - if (pred_->searchFrom(from_vertex)) { - VertexOutEdgeIterator edge_iter(from_vertex, graph_); - while (edge_iter.hasNext()) { - Edge *edge = edge_iter.next(); - Vertex *to_vertex = edge->to(graph_); - const Pin *to_pin = to_vertex->pin(); - if (pred_->searchTo(to_vertex) - && pred_->searchThru(edge)) { - debugPrint(debug_, "search", 3, " %s", - to_vertex->to_string(this).c_str()); - if (!visitEdge(from_pin, from_vertex, edge, to_pin, to_vertex)) - break; - } - } + VertexOutEdgeIterator edge_iter(from_vertex, graph_); + while (edge_iter.hasNext()) { + Edge *edge = edge_iter.next(); + Vertex *to_vertex = edge->to(graph_); + const Pin *to_pin = to_vertex->pin(); + debugPrint(debug_, "search", 3, " %s", + to_vertex->to_string(this).c_str()); + if (!visitEdge(from_pin, from_vertex, edge, to_pin, to_vertex)) + break; } } bool PathVisitor::visitEdge(const Pin *from_pin, - Vertex *from_vertex, - Edge *edge, - const Pin *to_pin, - Vertex *to_vertex) + Vertex *from_vertex, + Edge *edge, + const Pin *to_pin, + Vertex *to_vertex) { TagGroup *from_tag_group = search_->tagGroup(from_vertex); if (from_tag_group) { TimingArcSet *arc_set = edge->timingArcSet(); VertexPathIterator from_iter(from_vertex, search_); + const Mode *prev_mode = nullptr; while (from_iter.hasNext()) { Path *from_path = from_iter.next(); - PathAnalysisPt *path_ap = from_path->pathAnalysisPt(this); - const MinMax *min_max = path_ap->pathMinMax(); - const RiseFall *from_rf = from_path->transition(this); - TimingArc *arc1, *arc2; - arc_set->arcsFrom(from_rf, arc1, arc2); - if (!visitArc(from_pin, from_vertex, from_rf, from_path, - edge, arc1, to_pin, to_vertex, - min_max, path_ap)) - return false; - if (!visitArc(from_pin, from_vertex, from_rf, from_path, - edge, arc2, to_pin, to_vertex, - min_max, path_ap)) - return false; + const Mode *mode = from_path->mode(this); + if (mode == prev_mode + || (pred_->searchFrom(from_vertex, mode) + && pred_->searchThru(edge, mode) + && pred_->searchTo(to_vertex, mode))) { + prev_mode = mode; + const MinMax *min_max = from_path->minMax(this); + const RiseFall *from_rf = from_path->transition(this); + TimingArc *arc1, *arc2; + arc_set->arcsFrom(from_rf, arc1, arc2); + if (!visitArc(from_pin, from_vertex, from_rf, from_path, + edge, arc1, to_pin, to_vertex, min_max, mode)) + return false; + if (!visitArc(from_pin, from_vertex, from_rf, from_path, + edge, arc2, to_pin, to_vertex, min_max, mode)) + return false; + } } } return true; @@ -2188,88 +2121,93 @@ PathVisitor::visitEdge(const Pin *from_pin, bool PathVisitor::visitArc(const Pin *from_pin, - Vertex *from_vertex, - const RiseFall *from_rf, - Path *from_path, - Edge *edge, - TimingArc *arc, - const Pin *to_pin, - Vertex *to_vertex, - const MinMax *min_max, - PathAnalysisPt *path_ap) + Vertex *from_vertex, + const RiseFall *from_rf, + Path *from_path, + Edge *edge, + TimingArc *arc, + const Pin *to_pin, + Vertex *to_vertex, + const MinMax *min_max, + const Mode *mode) { if (arc) { const RiseFall *to_rf = arc->toEdge()->asRiseFall(); - if (searchThru(from_vertex, from_rf, edge, to_vertex, to_rf)) + if (searchThru(from_vertex, from_rf, edge, to_vertex, to_rf, mode)) return visitFromPath(from_pin, from_vertex, from_rf, from_path, - edge, arc, to_pin, to_vertex, to_rf, - min_max, path_ap); + edge, arc, to_pin, to_vertex, to_rf, min_max); } return true; } bool PathVisitor::visitFromPath(const Pin *from_pin, - Vertex *from_vertex, - const RiseFall *from_rf, - Path *from_path, - Edge *edge, - TimingArc *arc, - const Pin *to_pin, - Vertex *to_vertex, - const RiseFall *to_rf, - const MinMax *min_max, - const PathAnalysisPt *path_ap) + Vertex *from_vertex, + const RiseFall *from_rf, + Path *from_path, + Edge *edge, + TimingArc *arc, + const Pin *to_pin, + Vertex *to_vertex, + const RiseFall *to_rf, + const MinMax *min_max) { const TimingRole *role = edge->role(); Tag *from_tag = from_path->tag(this); + Scene *scene = from_tag->scene(); + const Mode *mode = scene->mode(); + const Sdc *sdc = scene->sdc(); const ClkInfo *from_clk_info = from_tag->clkInfo(); Tag *to_tag = nullptr; const ClockEdge *clk_edge = from_clk_info->clkEdge(); const Clock *clk = from_clk_info->clock(); Arrival from_arrival = from_path->arrival(); ArcDelay arc_delay = 0.0; + DcalcAPIndex dcalc_ap = from_path->dcalcAnalysisPtIndex(this); Arrival to_arrival; if (from_clk_info->isGenClkSrcPath()) { - if (!sdc_->clkStopPropagation(clk,from_pin,from_rf,to_pin,to_rf) - && (variables_->clkThruTristateEnabled() - || !(role == TimingRole::tristateEnable() - || role == TimingRole::tristateDisable()))) { - const Clock *gclk = from_tag->genClkSrcPathClk(this); + if (!sdc->clkStopPropagation(clk,from_pin,from_rf,to_pin,to_rf) + && (variables_->clkThruTristateEnabled() + || !(role == TimingRole::tristateEnable() + || role == TimingRole::tristateDisable()))) { + const Clock *gclk = from_tag->genClkSrcPathClk(); if (gclk) { - Genclks *genclks = search_->genclks(); - VertexSet *fanins = genclks->fanins(gclk); - // Note: encountering a latch d->q edge means find the - // latch feedback edges, but they are referenced for - // other edges in the gen clk fanout. - if (role == TimingRole::latchDtoQ()) - genclks->findLatchFdbkEdges(gclk); - EdgeSet *fdbk_edges = genclks->latchFdbkEdges(gclk); - if ((role == TimingRole::combinational() - || role == TimingRole::wire() - || !gclk->combinational()) - && fanins->hasKey(to_vertex) - && !(fdbk_edges && fdbk_edges->hasKey(edge))) { + Genclks *genclks = mode->genclks(); + VertexSet *fanins = genclks->fanins(gclk); + // Note: encountering a latch d->q edge means find the + // latch feedback edges, but they are referenced for + // other edges in the gen clk fanout. + if (role == TimingRole::latchDtoQ()) + genclks->findLatchFdbkEdges(gclk); + EdgeSet &fdbk_edges = genclks->latchFdbkEdges(gclk); + if ((role == TimingRole::combinational() + || role == TimingRole::wire() + || !gclk->combinational()) + && fanins->contains(to_vertex) + && !fdbk_edges.contains(edge)) { arc_delay = search_->deratedDelay(from_vertex, arc, edge, - true, path_ap); - const PathAnalysisPt *path_ap_opp = - path_ap->corner()->findPathAnalysisPt(min_max->opposite()); + true, min_max, dcalc_ap, sdc); + DcalcAPIndex dcalc_ap = scene->dcalcAnalysisPtIndex(min_max->opposite()); Delay arc_delay_opp = search_->deratedDelay(from_vertex, arc, edge, - true, path_ap_opp); + true, min_max, + dcalc_ap, + sdc); bool arc_delay_min_max_eq = fuzzyEqual(delayAsFloat(arc_delay), delayAsFloat(arc_delay_opp)); - to_tag = search_->thruClkTag(from_path, from_vertex, from_tag, true, + to_tag = search_->thruClkTag(from_path, from_vertex, from_tag, true, edge, to_rf, arc_delay_min_max_eq, - min_max, path_ap); + min_max, scene); + if (to_tag) to_arrival = from_arrival + arc_delay; - } + } } } } else if (role->genericRole() == TimingRole::regClkToQ()) { if (clk == nullptr - || !sdc_->clkStopPropagation(from_pin, clk)) { - arc_delay = search_->deratedDelay(from_vertex, arc, edge, false, path_ap); + || !sdc->clkStopPropagation(from_pin, clk)) { + arc_delay = search_->deratedDelay(from_vertex, arc, edge, false, + min_max, dcalc_ap, sdc); // Remove clock network delay for macros created with propagated // clocks when used in a context with ideal clocks. @@ -2285,30 +2223,30 @@ PathVisitor::visitFromPath(const Pin *from_pin, // Propagate from unclocked reg/latch clk pins, which have no // clk but are distinguished with a segment_start flag. if ((clk_edge == nullptr - && from_tag->isSegmentStart()) - // Do not propagate paths from input ports with default - // input arrival clk thru CLK->Q edges. - || (clk != sdc_->defaultArrivalClock() - // Only propagate paths from clocks that have not - // passed thru reg/latch D->Q edges. - && from_tag->isClock())) { - const RiseFall *clk_rf = clk_edge ? clk_edge->transition() : nullptr; - const ClkInfo *to_clk_info = from_clk_info; - if (from_clk_info->crprClkPath(this) == nullptr + && from_tag->isSegmentStart()) + // Do not propagate paths from input ports with default + // input arrival clk thru CLK->Q edges. + || (clk != sdc->defaultArrivalClock() + // Only propagate paths from clocks that have not + // passed thru reg/latch D->Q edges. + && from_tag->isClock())) { + const RiseFall *clk_rf = clk_edge ? clk_edge->transition() : nullptr; + const ClkInfo *to_clk_info = from_clk_info; + if (from_clk_info->crprClkPath(this) == nullptr || network_->direction(to_pin)->isInternal()) - to_clk_info = search_->clkInfoWithCrprClkPath(from_clk_info, - from_path, path_ap); - to_tag = search_->fromRegClkTag(from_pin, from_rf, clk, clk_rf, + to_clk_info = search_->clkInfoWithCrprClkPath(from_clk_info, + from_path); + to_tag = search_->fromRegClkTag(from_pin, from_rf, clk, clk_rf, to_clk_info, to_pin, to_rf, min_max, - path_ap); - if (to_tag) - to_tag = search_->thruTag(to_tag, edge, to_rf, min_max, path_ap, tag_cache_); + from_tag->scene()); + if (to_tag) + to_tag = search_->thruTag(to_tag, edge, to_rf, tag_cache_); from_arrival = search_->clkPathArrival(from_path, from_clk_info, - clk_edge, min_max, path_ap); - to_arrival = from_arrival + arc_delay; + clk_edge, min_max); + to_arrival = from_arrival + arc_delay; } else - to_tag = nullptr; + to_tag = nullptr; } } else if (edge->role() == TimingRole::latchDtoQ()) { @@ -2336,62 +2274,67 @@ PathVisitor::visitFromPath(const Pin *from_pin, } } if (!postponed) { - arc_delay = search_->deratedDelay(from_vertex, arc, edge, false, path_ap); - latches_->latchOutArrival(from_path, arc, edge, path_ap, - to_tag, arc_delay, to_arrival); + arc_delay = search_->deratedDelay(from_vertex, arc, edge, false, + min_max, dcalc_ap, sdc); + latches_->latchOutArrival(from_path, arc, edge, to_tag, + arc_delay, to_arrival); if (to_tag) - to_tag = search_->thruTag(to_tag, edge, to_rf, min_max, path_ap, tag_cache_); + to_tag = search_->thruTag(to_tag, edge, to_rf, tag_cache_); } } } else if (from_tag->isClock()) { - ClockSet *clks = sdc_->findLeafPinClocks(from_pin); + ClockSet *clks = sdc->findLeafPinClocks(from_pin); // Disable edges from hierarchical clock source pins that do // not go thru the hierarchical pin and edges from clock source pins // that traverse a hierarchical source pin of a different clock. // Clock arrivals used as data also need to be disabled. if (!(role == TimingRole::wire() - && sdc_->clkDisabledByHpinThru(clk, from_pin, to_pin)) + && sdc->clkDisabledByHpinThru(clk, from_pin, to_pin)) // Generated clock source pins have arrivals for the source clock. // Do not propagate them past the generated clock source pin. && !(clks - && !clks->hasKey(const_cast(from_tag->clock())))) { + && !clks->contains(const_cast(from_tag->clock())))) { // Propagate arrival as non-clock at the end of the clock tree. bool to_propagates_clk = - !sdc_->clkStopPropagation(clk,from_pin,from_rf,to_pin,to_rf) - && (variables_->clkThruTristateEnabled() - || !(role == TimingRole::tristateEnable() - || role == TimingRole::tristateDisable())); + !sdc->clkStopPropagation(clk,from_pin,from_rf,to_pin,to_rf) + && (variables_->clkThruTristateEnabled() + || !(role == TimingRole::tristateEnable() + || role == TimingRole::tristateDisable())); arc_delay = search_->deratedDelay(from_vertex, arc, edge, - to_propagates_clk, path_ap); - const PathAnalysisPt *path_ap_opp = - path_ap->corner()->findPathAnalysisPt(min_max->opposite()); + to_propagates_clk, min_max, + dcalc_ap, sdc); + DcalcAPIndex dcalc_ap_opp = + scene->dcalcAnalysisPtIndex(min_max->opposite()); Delay arc_delay_opp = search_->deratedDelay(from_vertex, arc, edge, - to_propagates_clk, path_ap_opp); + to_propagates_clk, + min_max, dcalc_ap_opp, sdc); bool arc_delay_min_max_eq = fuzzyEqual(delayAsFloat(arc_delay), delayAsFloat(arc_delay_opp)); to_tag = search_->thruClkTag(from_path, from_vertex, from_tag, to_propagates_clk, edge, to_rf, arc_delay_min_max_eq, - min_max, path_ap); + min_max, scene); to_arrival = from_arrival + arc_delay; } } else { - if (!(sdc_->isPathDelayInternalFromBreak(to_pin) - || sdc_->isPathDelayInternalToBreak(from_pin))) { - to_tag = search_->thruTag(from_tag, edge, to_rf, min_max, path_ap, tag_cache_); - arc_delay = search_->deratedDelay(from_vertex, arc, edge, false, path_ap); - if (!delayInf(arc_delay)) + if (!(sdc->isPathDelayInternalFromBreak(to_pin) + || sdc->isPathDelayInternalToBreak(from_pin))) { + arc_delay = search_->deratedDelay(from_vertex, arc, edge, false, + min_max, dcalc_ap, sdc); + if (!delayInf(arc_delay)) { to_arrival = from_arrival + arc_delay; + to_tag = search_->thruTag(from_tag, edge, to_rf, tag_cache_); + } } } if (to_tag) return visitFromToPath(from_pin, from_vertex, from_rf, from_tag, from_path, from_arrival, - edge, arc, arc_delay, - to_vertex, to_rf, to_tag, to_arrival, - min_max, path_ap); + edge, arc, arc_delay, + to_vertex, to_rf, to_tag, to_arrival, + min_max); else return true; } @@ -2401,18 +2344,17 @@ Search::clkPathArrival(const Path *clk_path) const { const ClkInfo *clk_info = clk_path->clkInfo(this); const ClockEdge *clk_edge = clk_info->clkEdge(); - const PathAnalysisPt *path_ap = clk_path->pathAnalysisPt(this); - const MinMax *min_max = path_ap->pathMinMax(); - return clkPathArrival(clk_path, clk_info, clk_edge, min_max, path_ap); + const MinMax *min_max = clk_path->minMax(this); + return clkPathArrival(clk_path, clk_info, clk_edge, min_max); } Arrival Search::clkPathArrival(const Path *clk_path, - const ClkInfo *clk_info, - const ClockEdge *clk_edge, - const MinMax *min_max, - const PathAnalysisPt *path_ap) const + const ClkInfo *clk_info, + const ClockEdge *clk_edge, + const MinMax *min_max) const { + const Scene *scene = clk_path->scene(this); if (clk_path->vertex(this)->isRegClk() && clk_path->isClock(this) && clk_edge @@ -2420,10 +2362,9 @@ Search::clkPathArrival(const Path *clk_path, // Ideal clock, apply ideal insertion delay and latency. const EarlyLate *early_late = min_max; return clk_edge->time() - + clockInsertion(clk_edge->clock(), - clk_info->clkSrc(), - clk_edge->transition(), - min_max, early_late, path_ap) + + clockInsertion(clk_edge->clock(), clk_info->clkSrc(), + clk_edge->transition(), min_max, + early_late, scene->mode()) + clk_info->latency(); } else @@ -2460,12 +2401,12 @@ Search::pathClkPathArrival1(const Path *path) const if (prev_edge) { const TimingRole *prev_role = prev_edge->role(); if (prev_role == TimingRole::regClkToQ() - || prev_role == TimingRole::latchEnToQ()) { - return p->prevPath(); + || prev_role == TimingRole::latchEnToQ()) { + return p->prevPath(); } else if (prev_role == TimingRole::latchDtoQ()) { - Path *enable_path = latches_->latchEnablePath(p, prev_edge); - return enable_path; + Path *enable_path = latches_->latchEnablePath(p, prev_edge); + return enable_path; } } p = prev_path; @@ -2479,17 +2420,19 @@ Search::pathClkPathArrival1(const Path *path) const // Return nullptr if a false path starts at pin/clk_edge. Tag * Search::fromUnclkedInputTag(const Pin *pin, - const RiseFall *rf, - const MinMax *min_max, - const PathAnalysisPt *path_ap, - bool is_segment_start, - bool require_exception) + const RiseFall *rf, + const MinMax *min_max, + bool is_segment_start, + bool require_exception, + Scene *scene) { + Sdc *sdc = scene->sdc(); ExceptionStateSet *states = nullptr; - if (sdc_->exceptionFromStates(pin, rf, nullptr, nullptr, min_max, states) + if (sdc->exceptionFromStates(pin, rf, nullptr, nullptr, min_max, states) && (!require_exception || states)) { - const ClkInfo *clk_info = findClkInfo(nullptr, nullptr, false, 0.0, path_ap); - return findTag(rf, path_ap, clk_info, false, nullptr, + const ClkInfo *clk_info = findClkInfo(scene, nullptr, nullptr, false, + 0.0, min_max); + return findTag(scene, rf, min_max, clk_info, false, nullptr, is_segment_start, states, true, nullptr); } return nullptr; @@ -2497,22 +2440,23 @@ Search::fromUnclkedInputTag(const Pin *pin, Tag * Search::fromRegClkTag(const Pin *from_pin, - const RiseFall *from_rf, - const Clock *clk, - const RiseFall *clk_rf, - const ClkInfo *clk_info, - const Pin *to_pin, - const RiseFall *to_rf, - const MinMax *min_max, - const PathAnalysisPt *path_ap) + const RiseFall *from_rf, + const Clock *clk, + const RiseFall *clk_rf, + const ClkInfo *clk_info, + const Pin *to_pin, + const RiseFall *to_rf, + const MinMax *min_max, + Scene *scene) { + Sdc *sdc = scene->sdc(); ExceptionStateSet *states = nullptr; - if (sdc_->exceptionFromStates(from_pin, from_rf, clk, clk_rf, - min_max, states)) { + if (sdc->exceptionFromStates(from_pin, from_rf, clk, clk_rf, + min_max, states)) { // Hack for filter -from reg/Q. - sdc_->filterRegQStates(to_pin, to_rf, min_max, states); - return findTag(to_rf, path_ap, clk_info, false, nullptr, false, states, - true, nullptr); + sdc->filterRegQStates(to_pin, to_rf, min_max, states); + return findTag(scene, to_rf, min_max, clk_info, false, nullptr, + false, states, true, nullptr); } else return nullptr; @@ -2521,20 +2465,22 @@ Search::fromRegClkTag(const Pin *from_pin, // Insert from_path as ClkInfo crpr_clk_path. const ClkInfo * Search::clkInfoWithCrprClkPath(const ClkInfo *from_clk_info, - Path *from_path, - const PathAnalysisPt *path_ap) + Path *from_path) { - if (crprActive()) - return findClkInfo(from_clk_info->clkEdge(), - from_clk_info->clkSrc(), - from_clk_info->isPropagated(), - from_clk_info->genClkSrc(), - from_clk_info->isGenClkSrcPath(), - from_clk_info->pulseClkSense(), - from_clk_info->insertion(), - from_clk_info->latency(), - from_clk_info->uncertainties(), - path_ap, from_path); + Scene *scene = from_clk_info->scene(); + if (crprActive(scene->mode())) + return findClkInfo(scene, + from_clk_info->clkEdge(), + from_clk_info->clkSrc(), + from_clk_info->isPropagated(), + from_clk_info->genClkSrc(), + from_clk_info->isGenClkSrcPath(), + from_clk_info->pulseClkSense(), + from_clk_info->insertion(), + from_clk_info->latency(), + from_clk_info->uncertainties(), + from_clk_info->minMax(), + from_path); else return from_clk_info; } @@ -2545,8 +2491,6 @@ Tag * Search::thruTag(Tag *from_tag, Edge *edge, const RiseFall *to_rf, - const MinMax *min_max, - const PathAnalysisPt *path_ap, TagSet *tag_cache) { const Pin *from_pin = edge->from(graph_)->pin(); @@ -2558,8 +2502,7 @@ Search::thruTag(Tag *from_tag, Tag *to_tag = mutateTag(from_tag, from_pin, from_rf, false, from_clk_info, to_pin, to_rf, false, to_is_reg_clk, false, // input delay is not propagated. - from_clk_info, nullptr, min_max, path_ap, - tag_cache); + from_clk_info, nullptr, tag_cache); return to_tag; } @@ -2567,13 +2510,13 @@ Search::thruTag(Tag *from_tag, Tag * Search::thruClkTag(Path *from_path, Vertex *from_vertex, - Tag *from_tag, - bool to_propagates_clk, - Edge *edge, - const RiseFall *to_rf, + Tag *from_tag, + bool to_propagates_clk, + Edge *edge, + const RiseFall *to_rf, bool arc_delay_min_max_eq, - const MinMax *min_max, - const PathAnalysisPt *path_ap) + const MinMax *min_max, + Scene *scene) { const Pin *from_pin = edge->from(graph_)->pin(); Vertex *to_vertex = edge->to(graph_); @@ -2584,32 +2527,35 @@ Search::thruClkTag(Path *from_path, bool to_is_reg_clk = to_vertex->isRegClk(); const TimingRole *role = edge->role(); bool to_is_clk = (from_is_clk - && to_propagates_clk - && (role->isWire() - || role == TimingRole::combinational())); + && to_propagates_clk + && (role->isWire() + || role == TimingRole::combinational())); const ClkInfo *to_clk_info = thruClkInfo(from_path, from_vertex, - from_clk_info, from_is_clk, - edge, to_vertex, to_pin, to_is_clk, - arc_delay_min_max_eq, min_max, path_ap); + from_clk_info, from_is_clk, + edge, to_vertex, to_pin, to_is_clk, + arc_delay_min_max_eq, min_max, scene); Tag *to_tag = mutateTag(from_tag,from_pin,from_rf,from_is_clk,from_clk_info, - to_pin, to_rf, to_is_clk, to_is_reg_clk, false, - to_clk_info, nullptr, min_max, path_ap, nullptr); + to_pin, to_rf, to_is_clk, to_is_reg_clk, false, + to_clk_info, nullptr, nullptr); return to_tag; } const ClkInfo * Search::thruClkInfo(Path *from_path, - Vertex *from_vertex, - const ClkInfo *from_clk_info, + Vertex *from_vertex, + const ClkInfo *from_clk_info, bool from_is_clk, - Edge *edge, - Vertex *to_vertex, - const Pin *to_pin, + Edge *edge, + Vertex *to_vertex, + const Pin *to_pin, bool to_is_clk, bool arc_delay_min_max_eq, - const MinMax *min_max, - const PathAnalysisPt *path_ap) + const MinMax *min_max, + Scene *scene) { + const ClkInfo *to_clk_info = from_clk_info; + const Sdc *sdc = scene->sdc(); + const Mode *mode = scene->mode(); bool changed = false; const ClockEdge *from_clk_edge = from_clk_info->clkEdge(); const RiseFall *clk_rf = from_clk_edge->transition(); @@ -2617,7 +2563,7 @@ Search::thruClkInfo(Path *from_path, bool from_clk_prop = from_clk_info->isPropagated(); bool to_clk_prop = from_clk_prop; if (!from_clk_prop - && sdc_->isPropagatedClock(to_pin)) { + && sdc->isPropagatedClock(to_pin)) { to_clk_prop = true; changed = true; } @@ -2627,15 +2573,15 @@ Search::thruClkInfo(Path *from_path, // the clkinfo. const Pin *gen_clk_src = nullptr; if (from_clk_info->isGenClkSrcPath() - && crprActive() - && sdc_->isClock(to_pin)) { + && crprActive(mode) + && sdc->isClock(to_pin)) { // Don't care that it could be a regular clock root. gen_clk_src = to_pin; changed = true; } Path *to_crpr_clk_path = nullptr; - if (crprActive() + if (crprActive(mode) // Update crpr clk path for combinational paths leaving the clock // network (ie, tristate en->out) and buffer driving reg clk. && ((from_is_clk @@ -2659,7 +2605,7 @@ Search::thruClkInfo(Path *from_path, changed = true; } else if (from_pulse_sense && - edge->timingArcSet()->sense() == TimingSense::negative_unate) { + edge->timingArcSet()->sense() == TimingSense::negative_unate) { to_pulse_sense = from_pulse_sense->opposite(); changed = true; } @@ -2669,8 +2615,8 @@ Search::thruClkInfo(Path *from_path, float to_latency = from_clk_info->latency(); float latency; bool exists; - sdc_->clockLatency(from_clk, to_pin, clk_rf, min_max, - latency, exists); + sdc->clockLatency(from_clk, to_pin, clk_rf, min_max, + latency, exists); if (exists) { // Latency on pin has precedence over fanin or hierarchical // pin latency. @@ -2680,8 +2626,8 @@ Search::thruClkInfo(Path *from_path, } else { // Check for hierarchical pin latency thru edge. - sdc_->clockLatency(edge, clk_rf, min_max, - latency, exists); + sdc->clockLatency(edge, clk_rf, min_max, + latency, exists); if (exists) { to_latency = latency; to_clk_prop = false; @@ -2689,24 +2635,27 @@ Search::thruClkInfo(Path *from_path, } } - ClockUncertainties *to_uncertainties = from_clk_info->uncertainties(); - ClockUncertainties *uncertainties = sdc_->clockUncertainties(to_pin); + const ClockUncertainties *to_uncertainties = from_clk_info->uncertainties(); + const ClockUncertainties *uncertainties = sdc->clockUncertainties(to_pin); if (uncertainties) { to_uncertainties = uncertainties; changed = true; } - if (changed) { - const ClkInfo *to_clk_info = findClkInfo(from_clk_edge, - from_clk_info->clkSrc(), - to_clk_prop, gen_clk_src, - from_clk_info->isGenClkSrcPath(), - to_pulse_sense, to_insertion, to_latency, - to_uncertainties, path_ap, - to_crpr_clk_path); - return to_clk_info; - } - return from_clk_info; + if (changed) + to_clk_info = findClkInfo(scene, from_clk_edge, from_clk_info->clkSrc(), + to_clk_prop, gen_clk_src, + from_clk_info->isGenClkSrcPath(), + to_pulse_sense, to_insertion, to_latency, + to_uncertainties, min_max, to_crpr_clk_path); + return to_clk_info; +} + +static size_t +tagsTableRfIndex(size_t tag_index, + const RiseFall *rf) +{ + return (tag_index / RiseFall::index_count) * RiseFall::index_count + rf->index(); } // Find the tag for a path going from from_tag thru edge to to_pin. @@ -2723,12 +2672,13 @@ Search::mutateTag(Tag *from_tag, bool to_is_segment_start, const ClkInfo *to_clk_info, InputDelay *to_input_delay, - const MinMax *min_max, - const PathAnalysisPt *path_ap, TagSet *tag_cache) { ExceptionStateSet *new_states = nullptr; ExceptionStateSet *from_states = from_tag->states(); + Scene *scene = from_tag->scene(); + Sdc *sdc = scene->sdc(); + const MinMax *min_max = from_tag->minMax(); if (from_states) { // Check for state changes in from_tag (but postpone copying state set). bool state_change = false; @@ -2738,7 +2688,7 @@ Search::mutateTag(Tag *from_tag, while (state->matchesNextThru(from_pin,to_pin,to_rf,min_max,network_)) { // Found a -thru that we've been waiting for. state = state->nextState(); - state_change = true; + state_change = true; break; } if (state_change) @@ -2753,32 +2703,32 @@ Search::mutateTag(Tag *from_tag, // to_pin/edge completes a loop path. || (exception->isLoop() && state->isComplete())) - return nullptr; + return nullptr; // Kill path delay tags past the -to pin. if ((exception->isPathDelay() - && sdc_->isCompleteTo(state, to_pin, to_rf, min_max)) + && sdc->isCompleteTo(state, to_pin, to_rf, min_max)) // Kill loop tags at register clock pins. || (exception->isLoop() && to_is_reg_clk)) { - state_change = true; + state_change = true; break; } } // Get the set of -thru exceptions starting at to_pin/edge. - sdc_->exceptionThruStates(from_pin, to_pin, to_rf, min_max, new_states); + sdc->exceptionThruStates(from_pin, to_pin, to_rf, min_max, new_states); if (new_states || state_change) { // Second pass to apply state changes and add updated existing // states to new states. if (new_states == nullptr) - new_states = new ExceptionStateSet(); + new_states = new ExceptionStateSet(); for (auto state : *from_states) { - ExceptionPath *exception = state->exception(); - // One edge may traverse multiple hierarchical thru pins. - while (state->matchesNextThru(from_pin,to_pin,to_rf,min_max,network_)) - // Found a -thru that we've been waiting for. - state = state->nextState(); + ExceptionPath *exception = state->exception(); + // One edge may traverse multiple hierarchical thru pins. + while (state->matchesNextThru(from_pin,to_pin,to_rf,min_max,network_)) + // Found a -thru that we've been waiting for. + state = state->nextState(); // Don't propagate a completed false path -thru unless it is a // clock. Clocks carry the completed false path to disable @@ -2794,34 +2744,35 @@ Search::mutateTag(Tag *from_tag, } // Kill path delay tags past the -to pin. - if (!((exception->isPathDelay() - && sdc_->isCompleteTo(state, from_pin, from_rf, min_max)) + if (!((exception->isPathDelay() + && sdc->isCompleteTo(state, from_pin, from_rf, min_max)) // Kill loop tags at register clock pins. || (to_is_reg_clk && exception->isLoop()))) - new_states->insert(state); + new_states->insert(state); } } } else // Get the set of -thru exceptions starting at to_pin/edge. - sdc_->exceptionThruStates(from_pin, to_pin, to_rf, min_max, new_states); + sdc->exceptionThruStates(from_pin, to_pin, to_rf, min_max, new_states); if (new_states) - return findTag(to_rf, path_ap, to_clk_info, to_is_clk, - from_tag->inputDelay(), to_is_segment_start, new_states, - true, tag_cache); + return findTag(scene, to_rf, min_max, to_clk_info, to_is_clk, + from_tag->inputDelay(), to_is_segment_start, + new_states, true, tag_cache); else { // No state change. if (to_clk_info == from_clk_info - && to_rf == from_rf - && to_is_clk == from_is_clk - && from_tag->isSegmentStart() == to_is_segment_start - && from_tag->inputDelay() == to_input_delay) - return from_tag; + && to_is_clk == from_is_clk + && from_tag->isSegmentStart() == to_is_segment_start + && from_tag->inputDelay() == to_input_delay) { + return tags_[tagsTableRfIndex(from_tag->index(), to_rf)]; + } else - return findTag(to_rf, path_ap, to_clk_info, to_is_clk, to_input_delay, - to_is_segment_start, from_states, false, tag_cache); + return findTag(scene, to_rf, min_max, to_clk_info, to_is_clk, + to_input_delay, to_is_segment_start, + from_states, false, tag_cache); } } @@ -2830,7 +2781,7 @@ Search::findTagGroup(TagGroupBldr *tag_bldr) { TagGroup probe(tag_bldr, this); LockGuard lock(tag_group_lock_); - TagGroup *tag_group = tag_group_set_->findKey(&probe); + TagGroup *tag_group = findKey(tag_group_set_, &probe); if (tag_group == nullptr) { TagGroupIndex tag_group_index; if (tag_group_free_indices_.empty()) @@ -2863,13 +2814,13 @@ Search::findTagGroup(TagGroupBldr *tag_bldr) void Search::setVertexArrivals(Vertex *vertex, - TagGroupBldr *tag_bldr) + TagGroupBldr *tag_bldr) { if (tag_bldr->empty()) deletePathsIncr(vertex); else { TagGroup *prev_tag_group = tagGroup(vertex); - Path *prev_paths = graph_->paths(vertex); + Path *prev_paths = vertex->paths(); TagGroup *tag_group = findTagGroup(tag_bldr); if (tag_group == prev_tag_group) { tag_bldr->copyPaths(tag_group, prev_paths); @@ -2877,19 +2828,19 @@ Search::setVertexArrivals(Vertex *vertex, } else { if (prev_tag_group) { - graph_->deletePaths(vertex); - prev_tag_group->decrRefCount(); + vertex->deletePaths(); + prev_tag_group->decrRefCount(); requiredInvalid(vertex); } size_t path_count = tag_group->pathCount(); - Path *paths = graph_->makePaths(vertex, path_count); + Path *paths = vertex->makePaths(path_count); tag_bldr->copyPaths(tag_group, paths); vertex->setTagGroupIndex(tag_group->index()); tag_group->incrRefCount(); } if (tag_group->hasFilterTag()) { LockGuard lock(filtered_arrivals_lock_); - filtered_arrivals_->insert(vertex); + filtered_arrivals_.insert(vertex); } } } @@ -2913,7 +2864,7 @@ class ReportPathLess public: ReportPathLess(const StaState *sta); bool operator()(const Path *path1, - const Path *path2) const; + const Path *path2) const; private: const StaState *sta_; @@ -2934,7 +2885,7 @@ ReportPathLess::operator()(const Path *path1, void Search::reportArrivals(Vertex *vertex, - bool report_tag_index) const + bool report_tag_index) const { report_->reportLine("Vertex %s", vertex->to_string(this).c_str()); TagGroup *tag_group = tagGroup(vertex); @@ -2947,32 +2898,35 @@ Search::reportArrivals(Vertex *vertex, const Path *path = path_iter.next(); paths.push_back(path); } - sort(paths.begin(), paths.end(), ReportPathLess(this)); + sort(paths, ReportPathLess(this)); for (const Path *path : paths) { const Tag *tag = path->tag(this); - const PathAnalysisPt *path_ap = tag->pathAnalysisPt(this); const RiseFall *rf = tag->transition(); const char *req = delayAsString(path->required(), this); + bool report_prev = false; std::string prev_str; - Path *prev_path = path->prevPath(); - if (prev_path) { - prev_str += prev_path->to_string(this); - prev_str += " "; - const Edge *prev_edge = path->prevEdge(this); - TimingArc *arc = path->prevArc(this); - prev_str += prev_edge->from(graph_)->to_string(this); - prev_str += " "; - prev_str += arc->fromEdge()->to_string(); - prev_str += " -> "; - prev_str += prev_edge->to(graph_)->to_string(this); - prev_str += " "; - prev_str += arc->toEdge()->to_string(); + if (report_prev) { + prev_str = "prev "; + Path *prev_path = path->prevPath(); + if (prev_path) { + prev_str += prev_path->to_string(this); + prev_str += " "; + const Edge *prev_edge = path->prevEdge(this); + TimingArc *arc = path->prevArc(this); + prev_str += prev_edge->from(graph_)->to_string(this); + prev_str += " "; + prev_str += arc->fromEdge()->to_string(); + prev_str += " -> "; + prev_str += prev_edge->to(graph_)->to_string(this); + prev_str += " "; + prev_str += arc->toEdge()->to_string(); + } + else + prev_str += "NULL"; } - else - prev_str = "NULL"; - report_->reportLine(" %s %s %s / %s %s prev %s", + report_->reportLine(" %s %s %s / %s %s%s", rf->to_string().c_str(), - path_ap->pathMinMax()->to_string().c_str(), + path->minMax(this)->to_string().c_str(), delayAsString(path->arrival(), this), req, tag->to_string(report_tag_index, false, this).c_str(), @@ -3031,7 +2985,7 @@ Search::reportTagGroups() const void Search::reportPathCountHistogram() const { - Vector vertex_counts(10); + std::vector vertex_counts(10); VertexIterator vertex_iter(graph_); while (vertex_iter.hasNext()) { Vertex *vertex = vertex_iter.next(); @@ -3039,7 +2993,7 @@ Search::reportPathCountHistogram() const if (tag_group) { size_t path_count = tag_group->pathCount(); if (path_count >= vertex_counts.size()) - vertex_counts.resize(path_count * 2); + vertex_counts.resize(path_count * 2); vertex_counts[path_count]++; } } @@ -3066,8 +3020,9 @@ Search::tagCount() const } Tag * -Search::findTag(const RiseFall *rf, - const PathAnalysisPt *path_ap, +Search::findTag(Scene *scene, + const RiseFall *rf, + const MinMax *min_max, const ClkInfo *clk_info, bool is_clk, InputDelay *input_delay, @@ -3076,33 +3031,39 @@ Search::findTag(const RiseFall *rf, bool own_states, TagSet *tag_cache) { - Tag probe(0, rf->index(), path_ap->index(), clk_info, is_clk, input_delay, - is_segment_start, states, false, this); + Tag probe(scene, 0, rf, min_max, clk_info, is_clk, + input_delay, is_segment_start, states, false); if (tag_cache) { - Tag *tag = tag_cache->findKey(&probe); + Tag *tag = findKey(tag_cache, &probe); if (tag) return tag; } + LockGuard lock(tag_lock_); - Tag *tag = tag_set_->findKey(&probe); + Tag *tag = findKey(tag_set_, &probe); if (tag == nullptr) { - ExceptionStateSet *new_states = !own_states && states - ? new ExceptionStateSet(*states) : states; - TagIndex tag_index; - if (tag_free_indices_.empty()) - tag_index = tag_next_++; - else { - tag_index = tag_free_indices_.back(); - tag_free_indices_.pop_back(); + // Make rise/fall versions of the tag to avoid tag_set lookups when the + // only change is the rise/fall edge. + for (const RiseFall *rf1 : RiseFall::range()) { + ExceptionStateSet *new_states = !own_states && states + ? new ExceptionStateSet(*states) : states; + TagIndex tag_index = tag_next_++; + Tag *tag1 = new Tag(scene, tag_index, rf1, min_max, clk_info, is_clk, + input_delay, is_segment_start, new_states, true); + own_states = false; + // Make sure tag can be indexed in tags_ before it is visible to + // other threads via tag_set_. + tags_[tagsTableRfIndex(tag_index, rf1)] = tag1; + tag_set_->insert(tag1); + if (tag_cache) + tag_cache->insert(tag1); + if (rf1 == rf) + tag = tag1; + + if (tag_next_ == tag_index_max) + report_->critical(1511, "max tag index exceeded"); } - tag = new Tag(tag_index, rf->index(), path_ap->index(), - clk_info, is_clk, input_delay, is_segment_start, - new_states, true, this); - own_states = false; - // Make sure tag can be indexed in tags_ before it is visible to - // other threads via tag_set_. - tags_[tag_index] = tag; - tag_set_->insert(tag); + // If tags_ needs to grow make the new array and copy the // contents into it before updating tags_ so that other threads // can use Search::tag(TagIndex) without returning gubbish. @@ -3115,15 +3076,9 @@ Search::findTag(const RiseFall *rf, tag_capacity_ = tag_capacity; tag_set_->reserve(tag_capacity); } - if (tag_next_ == tag_index_max) - report_->critical(1511, "max tag index exceeded"); } if (own_states) delete states; - - if (tag_cache) - tag_cache->insert(tag); - return tag; } @@ -3148,7 +3103,7 @@ Search::reportTags() const void Search::reportClkInfos() const { - Vector clk_infos; + std::vector clk_infos; // set -> vector for sorting. for (const ClkInfo *clk_info : *clk_info_set_) clk_infos.push_back(clk_info); @@ -3159,42 +3114,46 @@ Search::reportClkInfos() const } const ClkInfo * -Search::findClkInfo(const ClockEdge *clk_edge, - const Pin *clk_src, - bool is_propagated, +Search::findClkInfo(Scene *scene, + const ClockEdge *clk_edge, + const Pin *clk_src, + bool is_propagated, const Pin *gen_clk_src, - bool gen_clk_src_path, - const RiseFall *pulse_clk_sense, - Arrival insertion, - float latency, - ClockUncertainties *uncertainties, - const PathAnalysisPt *path_ap, - Path *crpr_clk_path) + bool gen_clk_src_path, + const RiseFall *pulse_clk_sense, + Arrival insertion, + float latency, + const ClockUncertainties *uncertainties, + const MinMax *min_max, + Path *crpr_clk_path) { - ClkInfo probe(clk_edge, clk_src, is_propagated, gen_clk_src, gen_clk_src_path, - pulse_clk_sense, insertion, latency, uncertainties, - path_ap->index(), crpr_clk_path, this); + const ClkInfo probe(scene, clk_edge, clk_src, is_propagated, gen_clk_src, + gen_clk_src_path, pulse_clk_sense, + insertion, latency, uncertainties, min_max, + crpr_clk_path, this); LockGuard lock(clk_info_lock_); - const ClkInfo *clk_info = clk_info_set_->findKey(&probe); + const ClkInfo *clk_info = findKey(clk_info_set_, &probe); if (clk_info == nullptr) { - clk_info = new ClkInfo(clk_edge, clk_src, - is_propagated, gen_clk_src, gen_clk_src_path, - pulse_clk_sense, insertion, latency, uncertainties, - path_ap->index(), crpr_clk_path, this); + clk_info = new ClkInfo(scene, clk_edge, clk_src, + is_propagated, gen_clk_src, gen_clk_src_path, + pulse_clk_sense, insertion, latency, uncertainties, + min_max, crpr_clk_path, this); clk_info_set_->insert(clk_info); } return clk_info; } const ClkInfo * -Search::findClkInfo(const ClockEdge *clk_edge, - const Pin *clk_src, - bool is_propagated, - Arrival insertion, - const PathAnalysisPt *path_ap) +Search::findClkInfo(Scene *scene, + const ClockEdge *clk_edge, + const Pin *clk_src, + bool is_propagated, + Arrival insertion, + const MinMax *min_max) { - return findClkInfo(clk_edge, clk_src, is_propagated, nullptr, false, nullptr, - insertion, 0.0, nullptr, path_ap, nullptr); + return findClkInfo(scene, clk_edge, clk_src, is_propagated, + nullptr, false, nullptr, + insertion, 0.0, nullptr, min_max, nullptr); } int @@ -3205,24 +3164,25 @@ Search::clkInfoCount() const ArcDelay Search::deratedDelay(const Vertex *from_vertex, - const TimingArc *arc, - const Edge *edge, - bool is_clk, - const PathAnalysisPt *path_ap) + const TimingArc *arc, + const Edge *edge, + bool is_clk, + const MinMax *min_max, + DcalcAPIndex dcalc_ap, + const Sdc *sdc) { - const DcalcAnalysisPt *dcalc_ap = path_ap->dcalcAnalysisPt(); - DcalcAPIndex ap_index = dcalc_ap->index(); - float derate = timingDerate(from_vertex, arc, edge, is_clk, path_ap); - ArcDelay delay = graph_->arcDelay(edge, arc, ap_index); + float derate = timingDerate(from_vertex, arc, edge, is_clk, sdc, min_max); + ArcDelay delay = graph_->arcDelay(edge, arc, dcalc_ap); return delay * derate; } float Search::timingDerate(const Vertex *from_vertex, - const TimingArc *arc, - const Edge *edge, - bool is_clk, - const PathAnalysisPt *path_ap) + const TimingArc *arc, + const Edge *edge, + bool is_clk, + const Sdc *sdc, + const MinMax *min_max) { PathClkOrData derate_clk_data = is_clk ? PathClkOrData::clk : PathClkOrData::data; @@ -3230,8 +3190,7 @@ Search::timingDerate(const Vertex *from_vertex, const Pin *pin = from_vertex->pin(); if (role->isWire()) { const RiseFall *rf = arc->toEdge()->asRiseFall(); - return sdc_->timingDerateNet(pin, derate_clk_data, rf, - path_ap->pathMinMax()); + return sdc->timingDerateNet(pin, derate_clk_data, rf, min_max); } else { TimingDerateCellType derate_type; @@ -3244,21 +3203,24 @@ Search::timingDerate(const Vertex *from_vertex, derate_type = TimingDerateCellType::cell_delay; rf = arc->fromEdge()->asRiseFall(); } - return sdc_->timingDerateInstance(pin, derate_type, derate_clk_data, rf, - path_ap->pathMinMax()); + return sdc->timingDerateInstance(pin, derate_type, derate_clk_data, + rf, min_max); } } ClockSet -Search::clockDomains(const Vertex *vertex) const +Search::clockDomains(const Vertex *vertex, + const Mode *mode) const + { ClockSet clks; - clockDomains(vertex, clks); + clockDomains(vertex, mode, clks); return clks; } void Search::clockDomains(const Vertex *vertex, + const Mode *mode, // Return value. ClockSet &clks) const { @@ -3266,80 +3228,65 @@ Search::clockDomains(const Vertex *vertex, while (path_iter.hasNext()) { Path *path = path_iter.next(); const Clock *clk = path->clock(this); - if (clk) + if (clk && path->mode(this) == mode) clks.insert(const_cast(clk)); } } ClockSet -Search::clockDomains(const Pin *pin) const +Search::clockDomains(const Pin *pin, + const Mode *mode) const { ClockSet clks; Vertex *vertex; Vertex *bidirect_drvr_vertex; graph_->pinVertices(pin, vertex, bidirect_drvr_vertex); if (vertex) - clockDomains(vertex, clks); + clockDomains(vertex, mode, clks); if (bidirect_drvr_vertex) - clockDomains(bidirect_drvr_vertex, clks); + clockDomains(bidirect_drvr_vertex, mode, clks); return clks; } ClockSet -Search::clocks(const Vertex *vertex) const +Search::clocks(const Pin *pin, + const Mode *mode) const { ClockSet clks; - clocks(vertex, clks); + Vertex *vertex; + Vertex *bidirect_drvr_vertex; + graph_->pinVertices(pin, vertex, bidirect_drvr_vertex); + if (vertex) + clocks(vertex, mode, clks); + if (bidirect_drvr_vertex) + clocks(bidirect_drvr_vertex, mode, clks); + return clks; +} + +ClockSet +Search::clocks(const Vertex *vertex, + const Mode *mode) const +{ + ClockSet clks; + clocks(vertex, mode, clks); return clks; } void Search::clocks(const Vertex *vertex, - // Return value. - ClockSet &clks) const + const Mode *mode, + // Return value. + ClockSet &clks) const { VertexPathIterator path_iter(const_cast(vertex), this); while (path_iter.hasNext()) { Path *path = path_iter.next(); - if (path->isClock(this)) + if (path->isClock(this) + && path->mode(this) == mode) clks.insert(const_cast(path->clock(this))); } } -ClockSet -Search::clocks(const Pin *pin) const -{ - ClockSet clks; - Vertex *vertex; - Vertex *bidirect_drvr_vertex; - graph_->pinVertices(pin, vertex, bidirect_drvr_vertex); - if (vertex) - clocks(vertex, clks); - if (bidirect_drvr_vertex) - clocks(bidirect_drvr_vertex, clks); - return clks; -} - -bool -Search::isClock(const Vertex *vertex) const -{ - TagGroup *tag_group = tagGroup(vertex); - if (tag_group) - return tag_group->hasClkTag(); - else - return false; -} - -bool -Search::isGenClkSrc(const Vertex *vertex) const -{ - TagGroup *tag_group = tagGroup(vertex); - if (tag_group) - return tag_group->hasGenClkSrcTag(); - else - return false; -} - //////////////////////////////////////////////////////////////// void @@ -3368,44 +3315,43 @@ void Search::seedRequireds() { ensureDownstreamClkPins(); - for (Vertex *vertex : *endpoints()) + for (Vertex *vertex : endpoints()) seedRequired(vertex); requireds_seeded_ = true; requireds_exist_ = true; } -VertexSet * +VertexSet & Search::endpoints() { - if (endpoints_ == nullptr) { - endpoints_ = new VertexSet(graph_); - invalid_endpoints_ = new VertexSet(graph_); + if (!endpoints_initialized_) { VertexIterator vertex_iter(graph_); while (vertex_iter.hasNext()) { Vertex *vertex = vertex_iter.next(); if (isEndpoint(vertex)) { - debugPrint(debug_, "endpoint", 2, "insert %s", + debugPrint(debug_, "endpoint", 2, "insert %s", vertex->to_string(this).c_str()); - endpoints_->insert(vertex); + endpoints_.insert(vertex); } } + endpoints_initialized_ = true; } - if (invalid_endpoints_) { - for (Vertex *vertex : *invalid_endpoints_) { + if (!invalid_endpoints_.empty()) { + for (Vertex *vertex : invalid_endpoints_) { if (isEndpoint(vertex)) { - debugPrint(debug_, "endpoint", 2, "insert %s", + debugPrint(debug_, "endpoint", 2, "insert %s", vertex->to_string(this).c_str()); - endpoints_->insert(vertex); + endpoints_.insert(vertex); } else { - if (debug_->check("endpoint", 2) - && endpoints_->hasKey(vertex)) - report_->reportLine("endpoint: remove %s", + if (debug_->check("endpoint", 2) + && endpoints_.contains(vertex)) + report_->reportLine("endpoint: remove %s", vertex->to_string(this).c_str()); - endpoints_->erase(vertex); + endpoints_.erase(vertex); } } - invalid_endpoints_->clear(); + invalid_endpoints_.clear(); } return endpoints_; } @@ -3413,44 +3359,67 @@ Search::endpoints() void Search::endpointInvalid(Vertex *vertex) { - if (invalid_endpoints_) { - debugPrint(debug_, "endpoint", 2, "invalid %s", - vertex->to_string(this).c_str()); - invalid_endpoints_->insert(vertex); - } + debugPrint(debug_, "endpoint", 2, "invalid %s", + vertex->to_string(this).c_str()); + invalid_endpoints_.insert(vertex); } bool Search::isEndpoint(Vertex *vertex) const { - return isEndpoint(vertex, search_adj_); + for (const Mode *mode : modes_) { + if (isEndpoint(vertex, search_thru_, mode)) + return true; + } + return false; } bool Search::isEndpoint(Vertex *vertex, - SearchPred *pred) const + const ModeSeq &modes) const { - Pin *pin = vertex->pin(); - return hasFanin(vertex, pred, graph_) - && ((vertex->hasChecks() - && hasEnabledChecks(vertex)) - || (variables_->gatedClkChecksEnabled() - && gated_clk_->isGatedClkEnable(vertex)) - || vertex->isConstrained() - || sdc_->isPathDelayInternalTo(pin) - || !hasFanout(vertex, pred, graph_) - // Unconstrained paths at register clk pins. - || (unconstrained_paths_ - && vertex->isRegClk())); + for (const Mode *mode : modes) { + if (isEndpoint(vertex, search_thru_, mode)) + return true; + } + return false; } bool -Search::hasEnabledChecks(Vertex *vertex) const +Search::isEndpoint(Vertex *vertex, + const Mode *mode) const +{ + return isEndpoint(vertex, search_thru_, mode); +} + +bool +Search::isEndpoint(Vertex *vertex, + SearchPred *pred, + const Mode *mode) const +{ + const Pin *pin = vertex->pin(); + const Sdc *sdc = mode->sdc(); + return hasFanin(vertex, pred, graph_, mode) + && ((vertex->hasChecks() + && hasEnabledChecks(vertex, mode)) + || sdc->isConstrainedEnd(pin) + || !hasFanout(vertex, pred, graph_, mode) + || sdc->isPathDelayInternalTo(pin) + // Unconstrained paths at register clk pins. + || (unconstrained_paths_ + && vertex->isRegClk()) + || (variables_->gatedClkChecksEnabled() + && gated_clk_->isGatedClkEnable(vertex, mode))); +} + +bool +Search::hasEnabledChecks(Vertex *vertex, + const Mode *mode) const { VertexInEdgeIterator edge_iter(vertex, graph_); while (edge_iter.hasNext()) { Edge *edge = edge_iter.next(); - if (visit_path_ends_->checkEdgeEnabled(edge)) + if (visit_path_ends_->checkEdgeEnabled(edge, mode)) return true; } return false; @@ -3459,18 +3428,17 @@ Search::hasEnabledChecks(Vertex *vertex) const void Search::endpointsInvalid() { - delete endpoints_; - delete invalid_endpoints_; - endpoints_ = nullptr; - invalid_endpoints_ = nullptr; + endpoints_.clear(); + endpoints_initialized_ = false; + invalid_endpoints_.clear(); } void Search::seedInvalidRequireds() { - for (Vertex *vertex : *invalid_requireds_) + for (Vertex *vertex : invalid_requireds_) required_iter_->enqueue(vertex); - invalid_requireds_->clear(); + invalid_requireds_.clear(); } //////////////////////////////////////////////////////////////// @@ -3480,7 +3448,7 @@ class FindEndRequiredVisitor : public PathEndVisitor { public: FindEndRequiredVisitor(RequiredCmp *required_cmp, - const StaState *sta); + const StaState *sta); FindEndRequiredVisitor(const StaState *sta); virtual ~FindEndRequiredVisitor(); virtual PathEndVisitor *copy() const; @@ -3493,7 +3461,7 @@ protected: }; FindEndRequiredVisitor::FindEndRequiredVisitor(RequiredCmp *required_cmp, - const StaState *sta) : + const StaState *sta) : sta_(sta), required_cmp_(required_cmp), own_required_cmp_(false) @@ -3567,7 +3535,7 @@ RequiredCmp::RequiredCmp() : void RequiredCmp::requiredsInit(Vertex *vertex, - const StaState *sta) + const StaState *sta) { Search *search = sta->search(); TagGroup *tag_group = search->tagGroup(vertex); @@ -3575,8 +3543,7 @@ RequiredCmp::requiredsInit(Vertex *vertex, size_t path_count = tag_group->pathCount(); requireds_.resize(path_count); for (auto const [tag, path_index] : *tag_group->pathIndexMap()) { - PathAnalysisPt *path_ap = tag->pathAnalysisPt(sta); - const MinMax *min_max = path_ap->pathMinMax(); + const MinMax *min_max = tag->minMax(); requireds_[path_index] = delayInitValue(min_max->opposite()); } } @@ -3587,9 +3554,9 @@ RequiredCmp::requiredsInit(Vertex *vertex, void RequiredCmp::requiredSet(size_t path_index, - Required &required, - const MinMax *min_max, - const StaState *sta) + Required &required, + const MinMax *min_max, + const StaState *sta) { if (delayGreater(required, requireds_[path_index], min_max, sta)) { requireds_[path_index] = required; @@ -3599,7 +3566,7 @@ RequiredCmp::requiredSet(size_t path_index, bool RequiredCmp::requiredsSave(Vertex *vertex, - const StaState *sta) + const StaState *sta) { bool requireds_changed = false; Debug *debug = sta->debug(); @@ -3637,7 +3604,7 @@ RequiredVisitor::RequiredVisitor(const StaState *sta) : } RequiredVisitor::RequiredVisitor(bool make_tag_cache, - const StaState *sta) : + const StaState *sta) : PathVisitor(sta->search()->evalPred(), make_tag_cache, sta), required_cmp_(new RequiredCmp), visit_path_ends_(new VisitPathEnds(sta)) @@ -3678,20 +3645,19 @@ RequiredVisitor::visit(Vertex *vertex) bool RequiredVisitor::visitFromToPath(const Pin *, - Vertex * /* from_vertex */, - const RiseFall *from_rf, - Tag *from_tag, - Path *from_path, + Vertex * /* from_vertex */, + const RiseFall *from_rf, + Tag *from_tag, + Path *from_path, const Arrival &, - Edge *edge, - TimingArc *, - ArcDelay arc_delay, - Vertex *to_vertex, - const RiseFall *to_rf, - Tag *to_tag, - Arrival &, - const MinMax *min_max, - const PathAnalysisPt *path_ap) + Edge *edge, + TimingArc *, + ArcDelay arc_delay, + Vertex *to_vertex, + const RiseFall *to_rf, + Tag *to_tag, + Arrival &, + const MinMax *min_max) { // Don't propagate required times through latch D->Q edges. if (edge->role() != TimingRole::latchDtoQ()) { @@ -3724,30 +3690,31 @@ RequiredVisitor::visitFromToPath(const Pin *, } else { if (search_->crprApproxMissingRequireds()) { - // Arrival on to_vertex that differs by crpr_pin was pruned. - // Find an arrival that matches everything but the crpr_pin - // as an appromate required. - VertexPathIterator to_iter(to_vertex, to_rf, path_ap, this); - while (to_iter.hasNext()) { - Path *to_path = to_iter.next(); - Tag *to_path_tag = to_path->tag(this); - if (Tag::matchNoCrpr(to_path_tag, to_tag)) { - Required to_required = to_path->required(); - Required from_required = to_required - arc_delay; - debugPrint(debug_, "search", 3, " to tag %2u: %s", + // Arrival on to_vertex that differs by crpr_pin was pruned. + // Find an arrival that matches everything but the crpr_pin + // as an appromate required. + VertexPathIterator to_iter(to_vertex, from_path->scene(this), + from_path->minMax(this), to_rf, this); + while (to_iter.hasNext()) { + Path *to_path = to_iter.next(); + Tag *to_path_tag = to_path->tag(this); + if (Tag::matchNoCrpr(to_path_tag, to_tag)) { + Required to_required = to_path->required(); + Required from_required = to_required - arc_delay; + debugPrint(debug_, "search", 3, " to tag %2u: %s", to_path_tag->index(), to_path_tag->to_string(this).c_str()); - debugPrint(debug_, "search", 3, " %s - %s = %s %s %s", + debugPrint(debug_, "search", 3, " %s - %s = %s %s %s", delayAsString(to_required, this), delayAsString(arc_delay, this), delayAsString(from_required, this), min_max == MinMax::max() ? "<" : ">", delayAsString(required_cmp_->required(path_index), this)); - required_cmp_->requiredSet(path_index, from_required, req_min, this); - break; - } - } + required_cmp_->requiredSet(path_index, from_required, req_min, this); + break; + } + } } } } @@ -3764,10 +3731,8 @@ Search::ensureDownstreamClkPins() // as having downstream clk pins. ClkTreeSearchPred pred(this); BfsBkwdIterator iter(BfsIndex::other, &pred, this); - for (Vertex *vertex : *graph_->regClkVertices()) { - if (!vertex->isConstant()) - iter.enqueue(vertex); - } + for (Vertex *vertex : graph_->regClkVertices()) + iter.enqueue(vertex); while (iter.hasNext()) { Vertex *vertex = iter.next(); @@ -3782,42 +3747,42 @@ Search::ensureDownstreamClkPins() bool Search::matchesFilter(Path *path, - const ClockEdge *to_clk_edge) + const ClockEdge *to_clk_edge) { - if (filter_ == nullptr + if (!have_filter_ && filter_from_ == nullptr && filter_to_ == nullptr) return true; - else if (filter_) { + else if (have_filter_) { // -from pins|inst // -thru // Path has to be tagged by traversing the filter exception points. ExceptionStateSet *states = path->tag(this)->states(); if (states) { for (auto state : *states) { - if (state->exception() == filter_ - && state->nextThru() == nullptr - && matchesFilterTo(path, to_clk_edge)) - return true; + if (state->exception()->isFilter() + && state->nextThru() == nullptr + && matchesFilterTo(path, to_clk_edge)) + return true; } } return false; } else if (filter_from_ - && filter_from_->pins() == nullptr - && filter_from_->instances() == nullptr - && filter_from_->clks()) { + && filter_from_->pins() == nullptr + && filter_from_->instances() == nullptr + && filter_from_->clks()) { // -from clks const ClockEdge *path_clk_edge = path->clkEdge(this); const Clock *path_clk = path_clk_edge ? path_clk_edge->clock() : nullptr; const RiseFall *path_clk_rf = path_clk_edge ? path_clk_edge->transition() : nullptr; - return filter_from_->clks()->hasKey(const_cast(path_clk)) + return filter_from_->clks()->contains(const_cast(path_clk)) && filter_from_->transition()->matches(path_clk_rf) && matchesFilterTo(path, to_clk_edge); } else if (filter_from_ == nullptr - && filter_to_) + && filter_to_) // -to return matchesFilterTo(path, to_clk_edge); else { @@ -3826,14 +3791,14 @@ Search::matchesFilter(Path *path, } } -// Similar to Constraints::exceptionMatchesTo. +// Similar to Sdf::exceptionMatchesTo. bool Search::matchesFilterTo(Path *path, - const ClockEdge *to_clk_edge) const + const ClockEdge *to_clk_edge) const { return (filter_to_ == nullptr - || filter_to_->matchesFilter(path->pin(graph_), to_clk_edge, - path->transition(this), network_)); + || filter_to_->matchesFilter(path->pin(graph_), to_clk_edge, + path->transition(this), network_)); } //////////////////////////////////////////////////////////////// @@ -3842,13 +3807,14 @@ Search::matchesFilterTo(Path *path, // including exceptions that start at the end pin or target clock. ExceptionPath * Search::exceptionTo(ExceptionPathType type, - const Path *path, - const Pin *pin, - const RiseFall *rf, - const ClockEdge *clk_edge, - const MinMax *min_max, - bool match_min_max_exactly, - bool require_to_pin) const + const Path *path, + const Pin *pin, + const RiseFall *rf, + const ClockEdge *clk_edge, + const MinMax *min_max, + bool match_min_max_exactly, + bool require_to_pin, + Sdc *sdc) const { // Find the highest priority exception carried by the path's tag. int hi_priority = -1; @@ -3859,22 +3825,22 @@ Search::exceptionTo(ExceptionPathType type, ExceptionPath *exception = state->exception(); int priority = exception->priority(min_max); if ((type == ExceptionPathType::any - || exception->type() == type) - && sdc_->isCompleteTo(state, pin, rf, clk_edge, min_max, - match_min_max_exactly, require_to_pin) - && (hi_priority_exception == nullptr - || priority > hi_priority - || (priority == hi_priority - && exception->tighterThan(hi_priority_exception)))) { - hi_priority = priority; - hi_priority_exception = exception; + || exception->type() == type) + && sdc->isCompleteTo(state, pin, rf, clk_edge, min_max, + match_min_max_exactly, require_to_pin) + && (hi_priority_exception == nullptr + || priority > hi_priority + || (priority == hi_priority + && exception->tighterThan(hi_priority_exception)))) { + hi_priority = priority; + hi_priority_exception = exception; } } } // Check for -to exceptions originating at the end pin or target clock. - sdc_->exceptionTo(type, pin, rf, clk_edge, min_max, - match_min_max_exactly, - hi_priority_exception, hi_priority); + sdc->exceptionTo(type, pin, rf, clk_edge, min_max, + match_min_max_exactly, + hi_priority_exception, hi_priority); return hi_priority_exception; } @@ -3888,21 +3854,22 @@ Search::groupPathsTo(const PathEnd *path_end) const const Path *path = path_end->path(); const Pin *pin = path->pin(this); const Tag *tag = path->tag(this); + Sdc *sdc = tag->scene()->sdc(); const RiseFall *rf = tag->transition(); const ClockEdge *clk_edge = path_end->targetClkEdge(this); - const MinMax *min_max = tag->minMax(this); + const MinMax *min_max = tag->minMax(); const ExceptionStateSet *states = path->tag(this)->states(); if (states) { for (auto state : *states) { ExceptionPath *exception = state->exception(); if (exception->isGroupPath() - && sdc_->exceptionMatchesTo(exception, pin, rf, clk_edge, min_max, - false, false)) - group_paths.push_back(exception); + && sdc->exceptionMatchesTo(exception, pin, rf, clk_edge, min_max, + false, false)) + group_paths.push_back(exception); } } // Check for group_path -to exceptions originating at the end pin or target clock. - sdc_->groupPathsTo(pin, rf, clk_edge, min_max, group_paths); + sdc->groupPathsTo(pin, rf, clk_edge, min_max, group_paths); return group_paths; } @@ -3913,9 +3880,9 @@ Search::totalNegativeSlack(const MinMax *min_max) { tnsPreamble(); Slack tns = 0.0; - for (Corner *corner : *corners_) { - PathAPIndex path_ap_index = corner->findPathAnalysisPt(min_max)->index(); - Slack tns1 = tns_[path_ap_index]; + for (Scene *scene : scenes_) { + size_t path_index = scene->pathIndex(min_max); + Slack tns1 = tns_[path_index]; if (delayLess(tns1, tns, this)) tns = tns1; } @@ -3923,11 +3890,11 @@ Search::totalNegativeSlack(const MinMax *min_max) } Slack -Search::totalNegativeSlack(const Corner *corner, - const MinMax *min_max) +Search::totalNegativeSlack(const Scene *scene, + const MinMax *min_max) { tnsPreamble(); - PathAPIndex path_ap_index = corner->findPathAnalysisPt(min_max)->index(); + PathAPIndex path_ap_index = scene->pathIndex(min_max); return tns_[path_ap_index]; } @@ -3935,9 +3902,9 @@ void Search::tnsPreamble() { wnsTnsPreamble(); - PathAPIndex path_ap_count = corners_->pathAnalysisPtCount(); - tns_.resize(path_ap_count); - tns_slacks_.resize(path_ap_count); + size_t path_count = scenePathCount(); + tns_.resize(path_count); + tns_slacks_.resize(path_count); if (tns_exists_) updateInvalidTns(); else @@ -3952,44 +3919,44 @@ Search::tnsInvalid(Vertex *vertex) debugPrint(debug_, "tns", 2, "tns invalid %s", vertex->to_string(this).c_str()); LockGuard lock(tns_lock_); - invalid_tns_->insert(vertex); + invalid_tns_.insert(vertex); } } void Search::updateInvalidTns() { - PathAPIndex path_ap_count = corners_->pathAnalysisPtCount(); - for (Vertex *vertex : *invalid_tns_) { + size_t path_count = scenePathCount(); + for (Vertex *vertex : invalid_tns_) { // Network edits can change endpointedness since tnsInvalid was called. if (isEndpoint(vertex)) { debugPrint(debug_, "tns", 2, "update tns %s", vertex->to_string(this).c_str()); - SlackSeq slacks(path_ap_count); + SlackSeq slacks(path_count); wnsSlacks(vertex, slacks); if (tns_exists_) - updateTns(vertex, slacks); + updateTns(vertex, slacks); if (worst_slacks_) - worst_slacks_->updateWorstSlacks(vertex, slacks); + worst_slacks_->updateWorstSlacks(vertex, slacks); } } - invalid_tns_->clear(); + invalid_tns_.clear(); } void Search::findTotalNegativeSlacks() { - PathAPIndex path_ap_count = corners_->pathAnalysisPtCount(); - for (PathAPIndex i = 0; i < path_ap_count; i++) { + size_t path_count = scenePathCount(); + for (size_t i = 0; i < path_count; i++) { tns_[i] = 0.0; tns_slacks_[i].clear(); } - for (Vertex *vertex : *endpoints()) { + for (Vertex *vertex : endpoints()) { // No locking required. - SlackSeq slacks(path_ap_count); + SlackSeq slacks(path_count); wnsSlacks(vertex, slacks); - for (PathAPIndex i = 0; i < path_ap_count; i++) + for (size_t i = 0; i < path_count; i++) tnsIncr(vertex, slacks[i], i); } tns_exists_ = true; @@ -3997,10 +3964,10 @@ Search::findTotalNegativeSlacks() void Search::updateTns(Vertex *vertex, - SlackSeq &slacks) + SlackSeq &slacks) { - PathAPIndex path_ap_count = corners_->pathAnalysisPtCount(); - for (PathAPIndex i = 0; i < path_ap_count; i++) { + size_t path_count = scenePathCount(); + for (size_t i = 0; i < path_count; i++) { tnsDecr(vertex, i); tnsIncr(vertex, slacks[i], i); } @@ -4008,15 +3975,15 @@ Search::updateTns(Vertex *vertex, void Search::tnsIncr(Vertex *vertex, - Slack slack, - PathAPIndex path_ap_index) + Slack slack, + PathAPIndex path_ap_index) { if (delayLess(slack, 0.0, this)) { debugPrint(debug_, "tns", 3, "tns+ %s %s", delayAsString(slack, this), vertex->to_string(this).c_str()); tns_[path_ap_index] += slack; - if (tns_slacks_[path_ap_index].hasKey(vertex)) + if (tns_slacks_[path_ap_index].contains(vertex)) report_->critical(1513, "tns incr existing vertex"); tns_slacks_[path_ap_index][vertex] = slack; } @@ -4024,11 +3991,11 @@ Search::tnsIncr(Vertex *vertex, void Search::tnsDecr(Vertex *vertex, - PathAPIndex path_ap_index) + PathAPIndex path_ap_index) { Slack slack; bool found; - tns_slacks_[path_ap_index].findKey(vertex, slack, found); + findKeyValue(tns_slacks_[path_ap_index], vertex, slack, found); if (found && delayLess(slack, 0.0, this)) { debugPrint(debug_, "tns", 3, "tns- %s %s", @@ -4045,8 +4012,8 @@ Search::tnsNotifyBefore(Vertex *vertex) { if (tns_exists_ && isEndpoint(vertex)) { - int ap_count = corners_->pathAnalysisPtCount(); - for (int i = 0; i < ap_count; i++) { + size_t path_count = scenePathCount(); + for (size_t i = 0; i < path_count; i++) { tnsDecr(vertex, i); } } @@ -4056,23 +4023,23 @@ Search::tnsNotifyBefore(Vertex *vertex) void Search::worstSlack(const MinMax *min_max, - // Return values. - Slack &worst_slack, - Vertex *&worst_vertex) + // Return values. + Slack &worst_slack, + Vertex *&worst_vertex) { worstSlackPreamble(); worst_slacks_->worstSlack(min_max, worst_slack, worst_vertex); } void -Search::worstSlack(const Corner *corner, - const MinMax *min_max, - // Return values. - Slack &worst_slack, - Vertex *&worst_vertex) +Search::worstSlack(const Scene *scene, + const MinMax *min_max, + // Return values. + Slack &worst_slack, + Vertex *&worst_vertex) { worstSlackPreamble(); - worst_slacks_->worstSlack(corner, min_max, worst_slack, worst_vertex); + worst_slacks_->worstSlack(scene, min_max, worst_slack, worst_vertex); } void @@ -4091,19 +4058,19 @@ Search::wnsTnsPreamble() findAllArrivals(); // Required times are only needed at endpoints. if (requireds_seeded_) { - for (auto itr = invalid_requireds_->begin(); itr != invalid_requireds_->end(); ) { + for (auto itr = invalid_requireds_.begin(); itr != invalid_requireds_.end(); ) { Vertex *vertex = *itr; debugPrint(debug_, "search", 2, "tns update required %s", vertex->to_string(this).c_str()); if (isEndpoint(vertex)) { - seedRequired(vertex); - // If the endpoint has fanout it's required time - // depends on downstream checks, so enqueue it to - // force required propagation to it's level if - // the required time is requested later. - if (hasFanout(vertex, search_adj_, graph_)) - required_iter_->enqueue(vertex); - itr = invalid_requireds_->erase(itr); + seedRequired(vertex); + // If the endpoint has fanout it's required time + // depends on downstream checks, so enqueue it to + // force required propagation to it's level if + // the required time is requested later. + if (vertex->hasFanout()) + required_iter_->enqueue(vertex); + itr = invalid_requireds_.erase(itr); } else itr++; @@ -4129,7 +4096,7 @@ class FindEndSlackVisitor : public PathEndVisitor { public: FindEndSlackVisitor(SlackSeq &slacks, - const StaState *sta); + const StaState *sta); FindEndSlackVisitor(const FindEndSlackVisitor &) = default; virtual PathEndVisitor *copy() const; virtual void visit(PathEnd *path_end); @@ -4140,7 +4107,7 @@ protected: }; FindEndSlackVisitor::FindEndSlackVisitor(SlackSeq &slacks, - const StaState *sta) : + const StaState *sta) : slacks_(slacks), sta_(sta) { @@ -4166,14 +4133,14 @@ FindEndSlackVisitor::visit(PathEnd *path_end) void Search::wnsSlacks(Vertex *vertex, - // Return values. - SlackSeq &slacks) + // Return values. + SlackSeq &slacks) { Slack slack_init = MinMax::min()->initValue(); - PathAPIndex path_ap_count = corners_->pathAnalysisPtCount(); - for (PathAPIndex i = 0; i < path_ap_count; i++) + size_t path_count = scenePathCount(); + for (size_t i = 0; i < path_count; i++) slacks[i] = slack_init; - if (hasFanout(vertex, search_adj_, graph_)) { + if (vertex->hasFanout()) { // If the vertex has fanout the path slacks include downstream // PathEnd slacks so find the endpoint slack directly. FindEndSlackVisitor end_visitor(slacks, this); @@ -4186,64 +4153,20 @@ Search::wnsSlacks(Vertex *vertex, PathAPIndex path_ap_index = path->pathAnalysisPtIndex(this); const Slack path_slack = path->slack(this); if (!path->tag(this)->isFilter() - && delayLess(path_slack, slacks[path_ap_index], this)) - slacks[path_ap_index] = path_slack; + && delayLess(path_slack, slacks[path_ap_index], this)) + slacks[path_ap_index] = path_slack; } } } Slack Search::wnsSlack(Vertex *vertex, - PathAPIndex path_ap_index) + PathAPIndex path_ap_index) { - PathAPIndex path_ap_count = corners_->pathAnalysisPtCount(); - SlackSeq slacks(path_ap_count); + size_t path_count = scenePathCount(); + SlackSeq slacks(path_count); wnsSlacks(vertex, slacks); return slacks[path_ap_index]; } -//////////////////////////////////////////////////////////////// - -void -Search::deletePathGroups() -{ - delete path_groups_; - path_groups_ = nullptr; -} - -PathGroupSeq -Search::pathGroups(const PathEnd *path_end) const -{ - if (path_groups_) - return path_groups_->pathGroups(path_end); - else - return PathGroupSeq(); -} - -bool -Search::havePathGroups() const -{ - return path_groups_ != nullptr; -} - -PathGroup * -Search::findPathGroup(const char *name, - const MinMax *min_max) const -{ - if (path_groups_) - return path_groups_->findPathGroup(name, min_max); - else - return nullptr; -} - -PathGroup * -Search::findPathGroup(const Clock *clk, - const MinMax *min_max) const -{ - if (path_groups_) - return path_groups_->findPathGroup(clk, min_max); - else - return nullptr; -} - } // namespace diff --git a/search/Search.i b/search/Search.i index 3e2e761a..8978d530 100644 --- a/search/Search.i +++ b/search/Search.i @@ -24,8 +24,12 @@ %module search +%include "std_string.i" + %{ +#include + #include "Units.hh" #include "PathGroup.hh" #include "Search.hh" @@ -33,6 +37,7 @@ #include "search/ReportPath.hh" #include "PathExpanded.hh" #include "Bfs.hh" +#include "Scene.hh" #include "Sta.hh" using namespace sta; @@ -67,36 +72,10 @@ private: ~PathEnd(); }; -class MinPulseWidthCheck -{ -private: - MinPulseWidthCheck(); - ~MinPulseWidthCheck(); -}; - -class MinPulseWidthCheckSeq -{ -private: - MinPulseWidthCheckSeq(); - ~MinPulseWidthCheckSeq(); -}; - -class MinPulseWidthCheckSeqIterator -{ -private: - MinPulseWidthCheckSeqIterator(); - ~MinPulseWidthCheckSeqIterator(); -}; - -class Corner -{ -private: - Corner(); - ~Corner(); -}; - %inline %{ +using std::string; + int group_path_count_max = PathGroup::group_path_count_max; //////////////////////////////////////////////////////////////// @@ -158,12 +137,6 @@ arrivals_invalid() sta->arrivalsInvalid(); } -PinSet -startpoints() -{ - return Sta::sta()->startpointPins(); -} - PinSet endpoints() { @@ -171,7 +144,7 @@ endpoints() } size_t -endpoint_path_count() +endpoint_count() { return Sta::sta()->endpointPins().size(); } @@ -189,10 +162,10 @@ total_negative_slack_cmd(const MinMax *min_max) } Slack -total_negative_slack_corner_cmd(const Corner *corner, - const MinMax *min_max) +total_negative_slack_scene_cmd(const Scene *scene, + const MinMax *min_max) { - return Sta::sta()->totalNegativeSlack(corner, min_max); + return Sta::sta()->totalNegativeSlack(scene, min_max); } Slack @@ -214,18 +187,18 @@ worst_slack_vertex(const MinMax *min_max) } Slack -worst_slack_corner(const Corner *corner, - const MinMax *min_max) +worst_slack_scene(const Scene *scene, + const MinMax *min_max) { Slack worst_slack; Vertex *worst_vertex; - Sta::sta()->worstSlack(corner, min_max, worst_slack, worst_vertex); + Sta::sta()->worstSlack(scene, min_max, worst_slack, worst_vertex); return worst_slack; } Path * vertex_worst_arrival_path(Vertex *vertex, - const MinMax *min_max) + const MinMax *min_max) { Sta *sta = Sta::sta(); sta->ensureLibLinked(); @@ -234,8 +207,8 @@ vertex_worst_arrival_path(Vertex *vertex, Path * vertex_worst_arrival_path_rf(Vertex *vertex, - const RiseFall *rf, - MinMax *min_max) + const RiseFall *rf, + MinMax *min_max) { Sta *sta = Sta::sta(); sta->ensureLibLinked(); @@ -244,7 +217,7 @@ vertex_worst_arrival_path_rf(Vertex *vertex, Path * vertex_worst_slack_path(Vertex *vertex, - const MinMax *min_max) + const MinMax *min_max) { Sta *sta = Sta::sta(); sta->ensureLibLinked(); @@ -253,18 +226,18 @@ vertex_worst_slack_path(Vertex *vertex, Slack endpoint_slack(const Pin *pin, - const char *path_group_name, - const MinMax *min_max) + const char *path_group_name, + const MinMax *min_max) { Sta *sta = Sta::sta(); sta->ensureLibLinked(); - if (sta->isGroupPathName(path_group_name)) { + if (sta->isGroupPathName(path_group_name, sta->cmdSdc())) { Slack slack = sta->endpointSlack(pin, std::string(path_group_name), min_max); return sta->units()->timeUnit()->staToUser(delayAsFloat(slack)); } else { sta->report()->error(1577, "%s is not a known path group name.", - path_group_name); + path_group_name); return INF; } } @@ -273,7 +246,7 @@ StdStringSeq path_group_names() { Sta *sta = Sta::sta(); - return sta->pathGroupNames(); + return sta->pathGroupNames(sta->cmdSdc()); } int @@ -290,7 +263,7 @@ report_tag_groups() void report_tag_arrivals_cmd(Vertex *vertex, - bool report_tag_index) + bool report_tag_index) { Sta::sta()->search()->reportArrivals(vertex, report_tag_index); } @@ -351,7 +324,9 @@ report_loops() char pin_sim_logic_value(const Pin *pin) { - return logicValueString(Sta::sta()->simLogicValue(pin)); + Sta *sta = Sta::sta(); + const Mode *sdc = sta->cmdMode(); + return logicValueString(sta->simLogicValue(pin, sdc)); } InstanceSeq @@ -364,38 +339,36 @@ slow_drivers(int count) PathEndSeq find_path_ends(ExceptionFrom *from, - ExceptionThruSeq *thrus, - ExceptionTo *to, - bool unconstrained, - Corner *corner, - const MinMaxAll *delay_min_max, - int group_path_count, - int endpoint_path_count, - bool unique_pins, - bool unique_edges, - float slack_min, - float slack_max, - bool sort_by_slack, - PathGroupNameSet *groups, - bool setup, - bool hold, - bool recovery, - bool removal, - bool clk_gating_setup, - bool clk_gating_hold) + ExceptionThruSeq *thrus, + ExceptionTo *to, + bool unconstrained, + SceneSeq scenes, + const MinMaxAll *delay_min_max, + int group_path_count, + int endpoint_path_count, + bool unique_pins, + bool unique_edges, + float slack_min, + float slack_max, + bool sort_by_slack, + StdStringSeq path_groups, + bool setup, + bool hold, + bool recovery, + bool removal, + bool clk_gating_setup, + bool clk_gating_hold) { Sta *sta = Sta::sta(); PathEndSeq ends = sta->findPathEnds(from, thrus, to, unconstrained, - corner, delay_min_max, + scenes, delay_min_max, group_path_count, endpoint_path_count, - unique_pins, unique_edges, + unique_pins, unique_edges, slack_min, slack_max, - sort_by_slack, - groups->size() ? groups : nullptr, + sort_by_slack, path_groups, setup, hold, recovery, removal, clk_gating_setup, clk_gating_hold); - delete groups; return ends; } @@ -421,7 +394,7 @@ report_path_end(PathEnd *end) void report_path_end2(PathEnd *end, - PathEnd *prev_end, + PathEnd *prev_end, bool last) { Sta::sta()->reportPathEnd(end, prev_end, last); @@ -443,26 +416,26 @@ set_report_path_field_order(StringSeq *field_names) void set_report_path_fields(bool report_input_pin, bool report_hier_pins, - bool report_net, - bool report_cap, - bool report_slew, - bool report_fanout, - bool report_src_attr) + bool report_net, + bool report_cap, + bool report_slew, + bool report_fanout, + bool report_src_attr) { Sta::sta()->setReportPathFields(report_input_pin, report_hier_pins, - report_net, - report_cap, - report_slew, - report_fanout, - report_src_attr); + report_net, + report_cap, + report_slew, + report_fanout, + report_src_attr); } void set_report_path_field_properties(const char *field_name, - const char *title, - int width, - bool left_justify) + const char *title, + int width, + bool left_justify) { Sta *sta = Sta::sta(); ReportField *field = sta->findReportPathField(field_name); @@ -474,7 +447,7 @@ set_report_path_field_properties(const char *field_name, void set_report_path_field_width(const char *field_name, - int width) + int width) { Sta *sta = Sta::sta(); ReportField *field = sta->findReportPathField(field_name); @@ -518,23 +491,40 @@ report_path_ends(PathEndSeq *ends) //////////////////////////////////////////////////////////////// void -report_clk_skew(ConstClockSeq clks, - const Corner *corner, - const SetupHold *setup_hold, - bool include_internal_latency, - int digits) +report_arrival_wrt_clks(const Pin *pin, + const Scene *scene, + int digits) { - Sta::sta()->reportClkSkew(clks, corner, setup_hold, - include_internal_latency, digits); + Sta::sta()->reportArrivalWrtClks(pin, scene, digits); } void -report_clk_latency(ConstClockSeq clks, - const Corner *corner, - bool include_internal_latency, - int digits) +report_required_wrt_clks(const Pin *pin, + const Scene *scene, + int digits) { - Sta::sta()->reportClkLatency(clks, corner, include_internal_latency, digits); + Sta::sta()->reportRequiredWrtClks(pin, scene, digits); +} + +void +report_slack_wrt_clks(const Pin *pin, + const Scene *scene, + int digits) +{ + Sta::sta()->reportSlackWrtClks(pin, scene, digits); +} + +//////////////////////////////////////////////////////////////// + +void +report_clk_skew(ConstClockSeq clks, + const SceneSeq scenes, + const SetupHold *setup_hold, + bool include_internal_latency, + int digits) +{ + Sta::sta()->reportClkSkew(clks, scenes, setup_hold, + include_internal_latency, digits); } float @@ -546,102 +536,50 @@ worst_clk_skew_cmd(const SetupHold *setup_hold, //////////////////////////////////////////////////////////////// -MinPulseWidthCheckSeq & -min_pulse_width_violations(const Corner *corner) -{ - return Sta::sta()->minPulseWidthViolations(corner); -} - -MinPulseWidthCheckSeq & -min_pulse_width_check_pins(PinSeq *pins, - const Corner *corner) -{ - Sta *sta = Sta::sta(); - MinPulseWidthCheckSeq &checks = sta->minPulseWidthChecks(pins, corner); - delete pins; - return checks; -} - -MinPulseWidthCheckSeq & -min_pulse_width_checks(const Corner *corner) -{ - return Sta::sta()->minPulseWidthChecks(corner); -} - -MinPulseWidthCheck * -min_pulse_width_check_slack(const Corner *corner) -{ - return Sta::sta()->minPulseWidthSlack(corner); -} - void -report_mpw_checks(MinPulseWidthCheckSeq *checks, - bool verbose) +report_clk_latency(ConstClockSeq clks, + const SceneSeq scenes, + bool include_internal_latency, + int digits) { - Sta::sta()->reportMpwChecks(checks, verbose); -} - -void -report_mpw_check(MinPulseWidthCheck *check, - bool verbose) -{ - Sta::sta()->reportMpwCheck(check, verbose); + Sta::sta()->reportClkLatency(clks, scenes, include_internal_latency, digits); } //////////////////////////////////////////////////////////////// -MinPeriodCheckSeq & -min_period_violations() -{ - return Sta::sta()->minPeriodViolations(); -} - -MinPeriodCheck * -min_period_check_slack() -{ - return Sta::sta()->minPeriodSlack(); -} - void -report_min_period_checks(MinPeriodCheckSeq *checks, - bool verbose) +report_min_pulse_width_checks(const Net *net, + size_t max_count, + bool violations, + bool verbose, + const SceneSeq scenes) { - Sta::sta()->reportChecks(checks, verbose); -} - -void -report_min_period_check(MinPeriodCheck *check, - bool verbose) -{ - Sta::sta()->reportCheck(check, verbose); + return Sta::sta()->reportMinPulseWidthChecks(net, max_count, violations, + verbose, scenes); } //////////////////////////////////////////////////////////////// -MaxSkewCheckSeq & -max_skew_violations() +void +report_min_period_checks(const Net *net, + size_t max_count, + bool violations, + bool verbose, + const SceneSeq scenes) { - return Sta::sta()->maxSkewViolations(); + Sta::sta()->reportMinPeriodChecks(net, max_count, violations, verbose, scenes); } -MaxSkewCheck * -max_skew_check_slack() -{ - return Sta::sta()->maxSkewSlack(); -} +//////////////////////////////////////////////////////////////// void -report_max_skew_checks(MaxSkewCheckSeq *checks, - bool verbose) +report_max_skew_checks(const Net *net, + size_t max_count, + bool violators, + bool verbose, + const SceneSeq scenes) { - Sta::sta()->reportChecks(checks, verbose); -} - -void -report_max_skew_check(MaxSkewCheck *check, - bool verbose) -{ - Sta::sta()->reportCheck(check, verbose); + Sta::sta()->reportMaxSkewChecks(net, max_count, violators, verbose, scenes); } //////////////////////////////////////////////////////////////// @@ -655,19 +593,22 @@ find_clk_min_period(const Clock *clk, //////////////////////////////////////////////////////////////// -PinSeq -check_slew_limits(Net *net, - bool violators, - const Corner *corner, - const MinMax *min_max) +void +report_slew_checks(const Net *net, + size_t max_count, + bool violators, + bool verbose, + const SceneSeq scenes, + const MinMax *min_max) { - return Sta::sta()->checkSlewLimits(net, violators, corner, min_max); + return Sta::sta()->reportSlewChecks(net, max_count, violators, verbose, + scenes, min_max); } size_t max_slew_violation_count() { - return Sta::sta()->checkSlewLimits(nullptr, true, nullptr, MinMax::max()).size(); + return Sta::sta()->maxSlewViolationCount(); } float @@ -694,103 +635,82 @@ max_slew_check_limit() return sta->units()->timeUnit()->staToUser(limit); } -void -report_slew_limit_short_header() -{ - Sta::sta()->reportSlewLimitShortHeader(); -} - -void -report_slew_limit_short(Pin *pin, - const Corner *corner, - const MinMax *min_max) -{ - Sta::sta()->reportSlewLimitShort(pin, corner, min_max); -} - -void -report_slew_limit_verbose(Pin *pin, - const Corner *corner, - const MinMax *min_max) -{ - Sta::sta()->reportSlewLimitVerbose(pin, corner, min_max); -} - //////////////////////////////////////////////////////////////// -PinSeq -check_fanout_limits(Net *net, - bool violators, - const MinMax *min_max) +void +report_fanout_checks(const Net *net, + size_t max_count, + bool violators, + bool verbose, + const SceneSeq scenes, + const MinMax *min_max) { - return Sta::sta()->checkFanoutLimits(net, violators, min_max); + Sta *sta = Sta::sta(); + return sta->reportFanoutChecks(net, max_count, violators, verbose, + scenes, min_max); } size_t max_fanout_violation_count() { - return Sta::sta()->checkFanoutLimits(nullptr, true, MinMax::max()).size(); + Sta *sta = Sta::sta(); + return sta->fanoutViolationCount(MinMax::max(), sta->modes()); } float -max_fanout_check_slack() +max_fanout_min_slack() { Sta *sta = Sta::sta(); const Pin *pin; - float fanout; - float slack; - float limit; - sta->maxFanoutCheck(pin, fanout, slack, limit); + float fanout, limit, slack; + const Mode *mode; + sta->maxFanoutMinSlackPin(sta->modes(), pin, fanout, limit, slack, mode); return slack;; } +// Deprecated 11/16/2025 float -max_fanout_check_limit() +max_fanout_check_slack() +{ + return max_fanout_min_slack(); +} + +float +max_fanout_min_slack_limit() { Sta *sta = Sta::sta(); const Pin *pin; - float fanout; - float slack; - float limit; - sta->maxFanoutCheck(pin, fanout, slack, limit); + float fanout, limit, slack; + const Mode *mode; + sta->maxFanoutMinSlackPin(sta->modes(), pin, fanout, limit, slack, mode); return limit;; } -void -report_fanout_limit_short_header() +// Deprecated 11/16/2025 +float +max_fanout_check_limit() { - Sta::sta()->reportFanoutLimitShortHeader(); -} - -void -report_fanout_limit_short(Pin *pin, - const MinMax *min_max) -{ - Sta::sta()->reportFanoutLimitShort(pin, min_max); -} - -void -report_fanout_limit_verbose(Pin *pin, - const MinMax *min_max) -{ - Sta::sta()->reportFanoutLimitVerbose(pin, min_max); + return max_fanout_min_slack_limit(); } //////////////////////////////////////////////////////////////// -PinSeq -check_capacitance_limits(Net *net, - bool violators, - const Corner *corner, - const MinMax *min_max) +void +report_capacitance_checks(const Net *net, + size_t max_count, + bool violators, + bool verbose, + const SceneSeq scenes, + const MinMax *min_max) { - return Sta::sta()->checkCapacitanceLimits(net, violators, corner, min_max); + Sta::sta()->reportCapacitanceChecks(net, max_count, violators, verbose, + scenes, min_max); } size_t max_capacitance_violation_count() { - return Sta::sta()->checkCapacitanceLimits(nullptr, true,nullptr,MinMax::max()).size(); + return Sta::sta()->maxCapacitanceViolationCount(); } float @@ -817,162 +737,206 @@ max_capacitance_check_limit() return sta->units()->capacitanceUnit()->staToUser(limit); } -void -report_capacitance_limit_short_header() -{ - Sta::sta()->reportCapacitanceLimitShortHeader(); -} - -void -report_capacitance_limit_short(Pin *pin, - const Corner *corner, - const MinMax *min_max) -{ - Sta::sta()->reportCapacitanceLimitShort(pin, corner, min_max); -} - -void -report_capacitance_limit_verbose(Pin *pin, - const Corner *corner, - const MinMax *min_max) -{ - Sta::sta()->reportCapacitanceLimitVerbose(pin, corner, min_max); -} - //////////////////////////////////////////////////////////////// void write_timing_model_cmd(const char *lib_name, const char *cell_name, const char *filename, - const Corner *corner) + const Scene *scene) { - Sta::sta()->writeTimingModel(lib_name, cell_name, filename, corner); + Sta::sta()->writeTimingModel(lib_name, cell_name, filename, scene); } //////////////////////////////////////////////////////////////// void -define_corners_cmd(StringSet *corner_names) +define_scene_cmd(const char *name, + const char *mode_name, + const StdStringSeq liberty_min_files, + const StdStringSeq liberty_max_files, + const char *spef_min_file, + const char *spef_max_file) { Sta *sta = Sta::sta(); - sta->makeCorners(corner_names); - delete corner_names; -} - -Corner * -cmd_corner() -{ - return Sta::sta()->cmdCorner(); + sta->makeScene(name, mode_name, + liberty_min_files, liberty_max_files, + spef_min_file, spef_max_file); } void -set_cmd_corner(Corner *corner) +define_scenes_cmd(StringSeq *scene_names) { - Sta::sta()->setCmdCorner(corner); + Sta *sta = Sta::sta(); + sta->makeScenes(scene_names); + delete scene_names; } -Corner * -find_corner(const char *corner_name) +Scene * +cmd_scene() { - return Sta::sta()->findCorner(corner_name); + return Sta::sta()->cmdScene(); } -Corners * -corners() +void +set_cmd_scene(Scene *scene) { - return Sta::sta()->corners(); + Sta::sta()->setCmdScene(scene); +} + +const SceneSeq +scenes() +{ + Sta *sta = Sta::sta(); + return sta->scenes(); +} + +Scene * +find_scene(const char *scene_name) +{ + return Sta::sta()->findScene(scene_name); +} + +SceneSeq +find_scenes_matching(std::string scene_name) +{ + return Sta::sta()->findScenes(scene_name); +} + +SceneSeq +find_mode_scenes_matching(std::string scene_name, + ModeSeq modes) +{ + return Sta::sta()->findScenes(scene_name, modes); } bool -multi_corner() +multi_scene() { - return Sta::sta()->multiCorner(); + return Sta::sta()->multiScene(); +} + +ClockSeq +get_scene_clocks(SceneSeq scenes) +{ + ClockSeq clks; + ModeSet modes = Scene::modeSet(scenes); + for (const Mode *mode : modes) { + for (Clock *clk : mode->sdc()->clocks()) + clks.push_back(clk); + } + return clks; +} + +//////////////////////////////////////////////////////////////// + +std::string +cmd_mode_name() +{ + return Sta::sta()->cmdMode()->name(); +} + +void +set_mode_cmd(std::string mode_name) +{ + Sta::sta()->setCmdMode(mode_name); +} + +ModeSeq +find_modes(std::string mode_name) +{ + return Sta::sta()->findModes(mode_name); } //////////////////////////////////////////////////////////////// CheckErrorSeq & check_timing_cmd(bool no_input_delay, - bool no_output_delay, - bool reg_multiple_clks, - bool reg_no_clks, - bool unconstrained_endpoints, - bool loops, - bool generated_clks) + bool no_output_delay, + bool reg_multiple_clks, + bool reg_no_clks, + bool unconstrained_endpoints, + bool loops, + bool generated_clks) { - return Sta::sta()->checkTiming(no_input_delay, no_output_delay, - reg_multiple_clks, reg_no_clks, - unconstrained_endpoints, - loops, generated_clks); + Sta *sta = Sta::sta(); + const Mode *sdc = sta->cmdMode(); + return sta->checkTiming(sdc, no_input_delay, no_output_delay, + reg_multiple_clks, reg_no_clks, + unconstrained_endpoints, + loops, generated_clks); } //////////////////////////////////////////////////////////////// PinSet find_fanin_pins(PinSeq *to, - bool flat, - bool startpoints_only, - int inst_levels, - int pin_levels, - bool thru_disabled, - bool thru_constants) + bool flat, + bool startpoints_only, + int inst_levels, + int pin_levels, + bool thru_disabled, + bool thru_constants) { Sta *sta = Sta::sta(); + const Mode *mode = sta->cmdMode(); PinSet fanin = sta->findFaninPins(to, flat, startpoints_only, inst_levels, pin_levels, - thru_disabled, thru_constants); + thru_disabled, thru_constants, mode); delete to; return fanin; } InstanceSet find_fanin_insts(PinSeq *to, - bool flat, - bool startpoints_only, - int inst_levels, - int pin_levels, - bool thru_disabled, - bool thru_constants) + bool flat, + bool startpoints_only, + int inst_levels, + int pin_levels, + bool thru_disabled, + bool thru_constants) { Sta *sta = Sta::sta(); + const Mode *mode = sta->cmdMode(); InstanceSet fanin = sta->findFaninInstances(to, flat, startpoints_only, inst_levels, pin_levels, - thru_disabled, thru_constants); + thru_disabled, thru_constants, mode); delete to; return fanin; } PinSet find_fanout_pins(PinSeq *from, - bool flat, - bool endpoints_only, - int inst_levels, - int pin_levels, - bool thru_disabled, - bool thru_constants) + bool flat, + bool endpoints_only, + int inst_levels, + int pin_levels, + bool thru_disabled, + bool thru_constants) { Sta *sta = Sta::sta(); + const Mode *mode = sta->cmdMode(); PinSet fanout = sta->findFanoutPins(from, flat, endpoints_only, inst_levels, pin_levels, - thru_disabled, thru_constants); + thru_disabled, thru_constants, mode); delete from; return fanout; } InstanceSet find_fanout_insts(PinSeq *from, - bool flat, - bool endpoints_only, - int inst_levels, - int pin_levels, - bool thru_disabled, - bool thru_constants) + bool flat, + bool endpoints_only, + int inst_levels, + int pin_levels, + bool thru_disabled, + bool thru_constants) { Sta *sta = Sta::sta(); + const Mode *mode = sta->cmdMode(); InstanceSet fanout = sta->findFanoutInstances(from, flat, endpoints_only, inst_levels, pin_levels, - thru_disabled, thru_constants); + thru_disabled, thru_constants, mode); delete from; return fanout; } @@ -1096,18 +1060,6 @@ set_bidirect_inst_paths_enabled(bool enabled) Sta::sta()->setBidirectInstPathsEnabled(enabled); } -bool -bidirect_net_paths_enabled() -{ - return Sta::sta()->bidirectNetPathsEnabled(); -} - -void -set_bidirect_net_paths_enabled(bool enabled) -{ - Sta::sta()->setBidirectNetPathsEnabled(enabled); -} - bool recovery_removal_checks_enabled() { @@ -1270,7 +1222,7 @@ edge() return self->transition(Sta::sta()); } -string +std::string tag() { Sta *sta = Sta::sta(); @@ -1310,13 +1262,3 @@ next() void finish() { delete self; } } - -%extend MinPulseWidthCheckSeqIterator { -bool has_next() { return self->hasNext(); } -MinPulseWidthCheck *next() { return self->next(); } -void finish() { delete self; } -} // MinPulseWidthCheckSeqIterator methods - -%extend Corner { -const char *name() { return self->name(); } -} diff --git a/search/Search.tcl b/search/Search.tcl index ba5acba4..a9c1312d 100644 --- a/search/Search.tcl +++ b/search/Search.tcl @@ -54,7 +54,7 @@ proc check_setup_cmd { cmd cmd_args } { } else { parse_key_args $cmd cmd_args keys {} \ flags {-no_input_delay -no_output_delay -multiple_clock -no_clock \ - -unconstrained_endpoints -loops -generated_clocks} + -unconstrained_endpoints -loops -generated_clocks} set no_input_delay [info exists flags(-no_input_delay)] set no_output_delay [info exists flags(-no_output_delay)] set multiple_clock [info exists flags(-multiple_clock)] @@ -65,15 +65,15 @@ proc check_setup_cmd { cmd cmd_args } { } set verbose [info exists flags(-verbose)] set errors [check_timing_cmd $no_input_delay $no_output_delay \ - $multiple_clock $no_clock \ - $unconstrained_endpoints $loops \ - $generated_clocks] + $multiple_clock $no_clock \ + $unconstrained_endpoints $loops \ + $generated_clocks] foreach error $errors { # First line is the error msg. report_line [lindex $error 0] if { $verbose } { foreach obj [lrange $error 1 end] { - report_line " $obj" + report_line " $obj" } } } @@ -98,7 +98,7 @@ define_cmd_args "find_timing_paths" \ [-to to_list|-rise_to to_list|-fall_to to_list]\ [-path_delay min|min_rise|min_fall|max|max_rise|max_fall|min_max]\ [-unconstrained] - [-corner corner]\ + [-scenes scenes]\ [-group_path_count path_count] \ [-endpoint_path_count path_count]\ [-unique_paths_to_endpoint]\ @@ -119,12 +119,12 @@ proc find_timing_paths_cmd { cmd args_var } { parse_key_args $cmd args \ keys {-from -rise_from -fall_from -to -rise_to -fall_to \ - -path_delay -corner -group_count -endpoint_count \ - -group_path_count -endpoint_path_count \ - -slack_max -slack_min -path_group} \ + -path_delay -corner -scenes -group_count -endpoint_count \ + -group_path_count -endpoint_path_count \ + -slack_max -slack_min -path_group} \ flags {-unconstrained -sort_by_slack \ - -unique_paths_to_endpoint \ - -unique_edges_to_endpoint} 0 + -unique_paths_to_endpoint \ + -unique_edges_to_endpoint} 0 set min_max "max" set end_rf "rise_fall" @@ -168,7 +168,7 @@ proc find_timing_paths_cmd { cmd args_var } { set unconstrained 0 } - set corner [parse_corner_or_all keys] + set scenes [parse_scenes_or_all keys] set endpoint_path_count 1 if { [info exists keys(-endpoint_count)] } { @@ -232,111 +232,20 @@ proc find_timing_paths_cmd { cmd args_var } { } set path_ends [find_path_ends $from $thrus $to $unconstrained \ - $corner $min_max \ - $group_path_count $endpoint_path_count \ - $unique_pins $unique_edges \ - $slack_min $slack_max \ - $sort_by_slack $groups \ - 1 1 1 1 1 1] + $scenes $min_max \ + $group_path_count $endpoint_path_count \ + $unique_pins $unique_edges \ + $slack_min $slack_max \ + $sort_by_slack $groups \ + 1 1 1 1 1 1] return $path_ends } ################################################################ -define_cmd_args "report_arrival" {pin} - -proc report_arrival { pin } { - report_delays_wrt_clks $pin "arrivals_clk_delays" -} - -proc report_delays_wrt_clks { pin_arg what } { - set pin [get_port_pin_error "pin" $pin_arg] - foreach vertex [$pin vertices] { - if { $vertex != "NULL" } { - report_delays_wrt_clk $vertex $what "NULL" "rise" - report_delays_wrt_clk $vertex $what [default_arrival_clock] "rise" - foreach clk [all_clocks] { - report_delays_wrt_clk $vertex $what $clk "rise" - report_delays_wrt_clk $vertex $what $clk "fall" - } - } - } -} - -proc report_delays_wrt_clk { vertex what clk clk_rf } { - global sta_report_default_digits - - set rise [$vertex $what rise $clk $clk_rf $sta_report_default_digits] - set fall [$vertex $what fall $clk $clk_rf $sta_report_default_digits] - # Filter INF/-INF arrivals. - if { !([delays_are_inf $rise] && [delays_are_inf $fall]) } { - set rise_fmt [format_delays $rise] - set fall_fmt [format_delays $fall] - if {$clk != "NULL"} { - set clk_str " ([get_name $clk] [rf_short_name $clk_rf])" - } else { - set clk_str "" - } - report_line "$clk_str r $rise_fmt f $fall_fmt" - } -} - -proc report_wrt_clks { pin_arg what } { - set pin [get_port_pin_error "pin" $pin_arg] - foreach vertex [$pin vertices] { - if { $vertex != "NULL" } { - report_wrt_clk $vertex $what "NULL" "rise" - report_wrt_clk $vertex $what [default_arrival_clock] "rise" - foreach clk [all_clocks] { - report_wrt_clk $vertex $what $clk "rise" - report_wrt_clk $vertex $what $clk "fall" - } - } - } -} - -proc report_wrt_clk { vertex what clk clk_rf } { - global sta_report_default_digits - - set rise [$vertex $what rise $clk $clk_rf] - set fall [$vertex $what fall $clk $clk_rf] - # Filter INF/-INF arrivals. - if { !([times_are_inf $rise] && [times_are_inf $fall]) } { - set rise_fmt [format_times $rise $sta_report_default_digits] - set fall_fmt [format_times $fall $sta_report_default_digits] - if {$clk != "NULL"} { - set clk_str " ([get_name $clk] [rf_short_name $clk_rf])" - } else { - set clk_str "" - } - report_line "$clk_str r $rise_fmt f $fall_fmt" - } -} - -proc times_are_inf { times } { - foreach time $times { - if { $time < 1e+10 && $time > -1e+10 } { - return 0 - } - } - return 1 -} - -proc delays_are_inf { delays } { - foreach delay $delays { - if { !([string match "INF*" $delay] \ - || [string match "-INF*" $delay]) } { - return 0 - } - } - return 1 -} - -################################################################ - define_cmd_args "report_clock_skew" {[-setup|-hold]\ - [-clock clocks]\ - [-corner corner]\ + [-clocks clocks]\ + [-scenes scenes]\ [-include_internal_latency] [-digits digits]} @@ -344,7 +253,7 @@ proc_redirect report_clock_skew { global sta_report_default_digits parse_key_args "report_clock_skew" args \ - keys {-clock -corner -digits} \ + keys {-clocks -corner -scenes -digits} \ flags {-setup -hold -include_internal_latency} check_argc_eq0 "report_clock_skew" $args @@ -358,12 +267,13 @@ proc_redirect report_clock_skew { set setup_hold "setup" } - if [info exists keys(-clock)] { - set clks [get_clocks_warn "-clocks" $keys(-clock)] + set scenes [parse_scenes_or_all keys] + if [info exists keys(-clocks)] { + puts "clks1 = [get_object_names $clks]" } else { - set clks [all_clocks] + set clks [get_scene_clocks $scenes] } - set corner [parse_corner_or_all keys] + set include_internal_latency [info exists flags(-include_internal_latency)] if [info exists keys(-digits)] { set digits $keys(-digits) @@ -372,14 +282,14 @@ proc_redirect report_clock_skew { set digits $sta_report_default_digits } if { $clks != {} } { - report_clk_skew $clks $corner $setup_hold $include_internal_latency $digits + report_clk_skew $clks $scenes $setup_hold $include_internal_latency $digits } } ################################################################ -define_cmd_args "report_clock_latency" {[-clock clocks]\ - [-corner corner]\ +define_cmd_args "report_clock_latency" {[-clocks clocks]\ + [-scenes scene]\ [-include_internal_latency] [-digits digits]} @@ -387,16 +297,16 @@ proc_redirect report_clock_latency { global sta_report_default_digits parse_key_args "report_clock_" args \ - keys {-clock -corner -digits} \ + keys {-clocks -scenes -digits} \ flags {-include_internal_latency} check_argc_eq0 "report_clock_latency" $args - if [info exists keys(-clock)] { - set clks [get_clocks_warn "-clocks" $keys(-clock)] + set scenes [parse_scenes_or_all keys] + if [info exists keys(-clocks)] { + set clks [get_clocks_warn "-clocks" $keys(-clocks)] } else { - set clks [all_clocks] + set clks [get_scene_clocks $scenes] } - set corner [parse_corner_or_all keys] set include_internal_latency [info exists flags(-include_internal_latency)] if [info exists keys(-digits)] { set digits $keys(-digits) @@ -405,7 +315,7 @@ proc_redirect report_clock_latency { set digits $sta_report_default_digits } if { $clks != {} } { - report_clk_latency $clks $corner $include_internal_latency $digits + report_clk_latency $clks $scenes $include_internal_latency $digits } } @@ -417,7 +327,7 @@ define_cmd_args "report_checks" \ [-to to_list|-rise_to to_list|-fall_to to_list]\ [-unconstrained]\ [-path_delay min|min_rise|min_fall|max|max_rise|max_fall|min_max]\ - [-corner corner]\ + [-scenes scenes]\ [-group_path_count path_count] \ [-endpoint_path_count path_count]\ [-unique_paths_to_endpoint]\ @@ -441,8 +351,7 @@ proc_redirect report_checks { ################################################################ define_cmd_args "report_check_types" \ - {[-violators] [-verbose]\ - [-corner corner]\ + {[-scenes scenes] [-violators] [-verbose]\ [-format slack_only|end]\ [-max_delay] [-min_delay]\ [-recovery] [-removal]\ @@ -452,13 +361,15 @@ define_cmd_args "report_check_types" \ [-max_capacitance] [-min_capacitance]\ [-min_pulse_width] [-min_period] [-max_skew]\ [-net net]\ + [-max_count max_count]\ [-digits digits] [-no_line_splits]\ [> filename] [>> filename]} proc_redirect report_check_types { variable path_options - parse_key_args "report_check_types" args keys {-net -corner}\ + parse_key_args "report_check_types" args \ + keys {-scenes -corner -net -max_count}\ flags {-violators -verbose -no_line_splits} 0 set violators [info exists flags(-violators)] @@ -477,13 +388,17 @@ proc_redirect report_check_types { set min_max "max" } - set corner [parse_corner_or_all keys] - set net "NULL" if { [info exists keys(-net)] } { set net [get_net_arg "-net" $keys(-net)] } + set max_count 1 + if { [info exists keys(-max_count)] } { + set max_count $keys(-max_count) + check_positive_integer "-max_count" $max_count + } + if { $args == {} } { if { $min_max == "max" || $min_max == "min_max" } { set setup 1 @@ -522,12 +437,12 @@ proc_redirect report_check_types { } else { parse_key_args "report_check_types" args keys {} \ flags {-max_delay -min_delay -recovery -removal \ - -clock_gating_setup -clock_gating_hold \ - -max_slew -min_slew \ - -max_fanout -min_fanout \ - -max_capacitance -min_capacitance \ - -min_pulse_width \ - -min_period -max_skew} 1 + -clock_gating_setup -clock_gating_hold \ + -max_slew -min_slew \ + -max_fanout -min_fanout \ + -max_capacitance -min_capacitance \ + -min_pulse_width \ + -min_period -max_skew} 1 set setup [info exists flags(-max_delay)] set hold [info exists flags(-min_delay)] @@ -545,24 +460,23 @@ proc_redirect report_check_types { set min_period [info exists flags(-min_period)] set max_skew [info exists flags(-max_skew)] if { [operating_condition_analysis_type] == "single" \ - && (($setup && $hold) \ - || ($recovery && $removal) \ - || ($clk_gating_setup && $clk_gating_hold)) } { + && (($setup && $hold) \ + || ($recovery && $removal) \ + || ($clk_gating_setup && $clk_gating_hold)) } { sta_error 520 "analysis type single is not consistent with doing both setup/max and hold/min checks." } } + set scenes [parse_scenes_or_all keys] if { $args != {} } { sta_error 521 "positional arguments not supported." } - set corner [parse_corner_or_all keys] - if { $setup || $hold || $recovery || $removal \ - || $clk_gating_setup || $clk_gating_hold } { + || $clk_gating_setup || $clk_gating_hold } { if { ($setup && $hold) \ - || ($recovery && $removal) \ - || ($clk_gating_setup && $clk_gating_hold) } { + || ($recovery && $removal) \ + || ($clk_gating_setup && $clk_gating_hold) } { set path_min_max "min_max" } elseif { $setup || $recovery || $clk_gating_setup } { set path_min_max "max" @@ -578,126 +492,43 @@ proc_redirect report_check_types { set slack_min [expr -$sta::float_inf] set slack_max $sta::float_inf } + set path_ends [find_path_ends "NULL" {} "NULL" 0 \ - $corner $path_min_max $group_path_count 1 1 0 \ - $slack_min $slack_max \ - 0 {} \ - $setup $hold \ - $recovery $removal \ - $clk_gating_setup $clk_gating_hold] + $scenes $path_min_max $group_path_count 1 1 0 \ + $slack_min $slack_max \ + 0 {} \ + $setup $hold \ + $recovery $removal \ + $clk_gating_setup $clk_gating_hold] report_path_ends $path_ends } if { $max_slew } { - report_slew_limits $net $corner "max" $violators $verbose $nosplit + report_slew_checks $net $max_count $violators $verbose $scenes "max" } if { $min_slew } { - report_slew_limits $net $corner "min" $violators $verbose $nosplit + report_slew_checks $net $max_count $violators $verbose $scenes "min" } if { $max_fanout } { - report_fanout_limits $net "max" $violators $verbose $nosplit + report_fanout_checks $net $max_count $violators $verbose $scenes "max" } if { $min_fanout } { - report_fanout_limits $net "min" $violators $verbose $nosplit + report_fanout_checks $net $max_count $violators $verbose $scenes "min" } if { $max_capacitance } { - report_capacitance_limits $net $corner "max" $violators $verbose $nosplit + report_capacitance_checks $net $max_count $violators $verbose $scenes "max" } if { $min_capacitance } { - report_capacitance_limits $net $corner "min" $violators $verbose $nosplit + report_capacitance_checks $net $max_count $violators $verbose $scenes "min" } if { $min_pulse_width } { - if { $violators } { - set checks [min_pulse_width_violations $corner] - report_mpw_checks $checks $verbose - } else { - set check [min_pulse_width_check_slack $corner] - if { $check != "NULL" } { - report_mpw_check $check $verbose - } - } + report_min_pulse_width_checks $net $max_count $violators $verbose $scenes } if { $min_period } { - if { $violators } { - set checks [min_period_violations] - report_min_period_checks $checks $verbose - } else { - set check [min_period_check_slack] - if { $check != "NULL" } { - report_min_period_check $check $verbose - } - } + report_min_period_checks $net $max_count $violators $verbose $scenes } if { $max_skew } { - if { $violators } { - set checks [max_skew_violations] - report_max_skew_checks $checks $verbose - } else { - set check [max_skew_check_slack] - if { $check != "NULL" } { - report_max_skew_check $check $verbose - } - } - } -} - -proc report_slew_limits { net corner min_max violators verbose nosplit } { - set pins [check_slew_limits $net $violators $corner $min_max] - if { $pins != {} } { - report_line "${min_max} slew" - report_line "" - if { $verbose } { - foreach pin $pins { - report_slew_limit_verbose $pin $corner $min_max - report_line "" - } - } else { - report_slew_limit_short_header - foreach pin $pins { - report_slew_limit_short $pin $corner $min_max - } - report_line "" - } - } -} - -proc report_fanout_limits { net min_max violators verbose nosplit } { - set pins [check_fanout_limits $net $violators $min_max] - if { $pins != {} } { - report_line "${min_max} fanout" - report_line "" - if { $verbose } { - foreach pin $pins { - report_fanout_limit_verbose $pin $min_max - report_line "" - } - } else { - report_fanout_limit_short_header - foreach pin $pins { - report_fanout_limit_short $pin $min_max - } - report_line "" - } - } -} - -proc report_capacitance_limits { net corner min_max violators verbose nosplit } { - set pins [check_capacitance_limits $net $violators $corner $min_max] - if { $pins != {} } { - report_line "${min_max} capacitance" - report_line "" - if { $verbose } { - foreach pin $pins { - report_capacitance_limit_verbose $pin $corner $min_max - report_line "" - } - } else { - report_capacitance_limit_short_header - foreach pin $pins { - report_capacitance_limit_short $pin $corner $min_max - } - report_line "" - } + report_max_skew_checks $net $max_count $violators $verbose $scenes } } @@ -780,33 +611,6 @@ proc_redirect report_worst_slack { ################################################################ -define_cmd_args "report_pulse_width_checks" \ - {[-verbose] [-corner corner] [-digits digits] [-no_line_splits] [pins]\ - [> filename] [>> filename]} - -proc_redirect report_pulse_width_checks { - variable path_options - - parse_key_args "report_pulse_width_checks" args keys {-corner} \ - flags {-verbose} 0 - # Only -digits and -no_line_splits are respected. - parse_report_path_options "report_pulse_width_checks" args "full" 0 - check_argc_eq0or1 "report_pulse_width_checks" $args - set corner [parse_corner_or_all keys] - set verbose [info exists flags(-verbose)] - if { [llength $args] == 1 } { - set pins [get_port_pins_error "pins" [lindex $args 0]] - set checks [min_pulse_width_check_pins $pins $corner] - } else { - set checks [min_pulse_width_checks $corner] - } - if { $checks != {} } { - report_mpw_checks $checks $verbose - } -} - -################################################################ - # Note that -all and -tags are intentionally "hidden". define_cmd_args "report_path" \ {[-min|-max]\ @@ -845,39 +649,39 @@ proc_redirect report_path { } else { foreach vertex [$pin vertices] { if { $vertex != "NULL" } { - if { $report_all } { - set first 1 - set path_iter [$vertex path_iterator $rf $min_max] - while {[$path_iter has_next]} { - set path [$path_iter next] - if { $first } { - report_line "Tag group: [$vertex tag_group_index]" - } else { - report_line "" - } - if { $report_tags } { - report_line "Tag: [$path tag]" - } - report_path_cmd $path - set first 0 - } - $path_iter finish - } else { - set worst_path [vertex_worst_arrival_path_rf $vertex $rf $min_max] - if { $worst_path != "NULL" } { - if { $report_tags } { - report_line "Tag: [$worst_path tag]" - } - report_path_cmd $worst_path - } - } + if { $report_all } { + set first 1 + set path_iter [$vertex path_iterator $rf $min_max] + while {[$path_iter has_next]} { + set path [$path_iter next] + if { $first } { + report_line "Tag group: [$vertex tag_group_index]" + } else { + report_line "" + } + if { $report_tags } { + report_line "Tag: [$path tag]" + } + report_path_cmd $path + set first 0 + } + $path_iter finish + } else { + set worst_path [vertex_worst_arrival_path_rf $vertex $rf $min_max] + if { $worst_path != "NULL" } { + if { $report_tags } { + report_line "Tag: [$worst_path tag]" + } + report_path_cmd $worst_path + } + } } } } } proc parse_report_path_options { cmd args_var default_format - unknown_key_is_error } { + unknown_key_is_error } { variable path_options variable report_path_field_width_extra global sta_report_default_digits @@ -893,7 +697,7 @@ proc parse_report_path_options { cmd args_var default_format if [info exists path_options(-format)] { set format $path_options(-format) set formats {full full_clock full_clock_expanded short \ - end slack_only summary json} + end slack_only summary json} if { [lsearch $formats $format] == -1 } { sta_error 524 "-format $format not recognized." } @@ -963,18 +767,65 @@ proc parse_report_path_options { cmd args_var default_format ################################################################ -define_cmd_args "report_required" {pin} +define_cmd_args "report_arrival" {[-scene scene] [-digits digits] pin} -proc report_required { pin } { - report_delays_wrt_clks $pin "requireds_clk_delays" +proc report_arrival { args } { + global sta_report_default_digits + + parse_key_args "report_arrival" args keys {-scene -digits} flags {} + check_argc_eq1 "report_arrival" $args + + set pin [get_port_pin_error "pin" [lindex $args 0]] + set scene [parse_scene keys] + if [info exists keys(-digits)] { + set digits $keys(-digits) + check_positive_integer "-digits" $digits + } else { + set digits $sta_report_default_digits + } + report_arrival_wrt_clks $pin $scene $digits } ################################################################ -define_cmd_args "report_slack" {pin} +define_cmd_args "report_required" {[-scene scene] [-digits digits] pin} -proc report_slack { pin } { - report_delays_wrt_clks $pin "slacks_clk_delays" +proc report_required { args } { + global sta_report_default_digits + + parse_key_args "report_required" args keys {-scene -digits} flags {} + check_argc_eq1 "report_required" $args + + set pin [get_port_pin_error "pin" [lindex $args 0]] + set scene [parse_scene keys] + if [info exists keys(-digits)] { + set digits $keys(-digits) + check_positive_integer "-digits" $digits + } else { + set digits $sta_report_default_digits + } + report_required_wrt_clks $pin $scene $digits +} + +################################################################ + +define_cmd_args "report_slack" {[-scene scene] [-digits digits] pin} + +proc report_slack { args } { + global sta_report_default_digits + + parse_key_args "report_slack" args keys {-scene -digits} flags {} + check_argc_eq1 "report_slack" $args + + set pin [get_port_pin_error "pin" [lindex $args 0]] + set scene [parse_scene keys] + if [info exists keys(-digits)] { + set digits $keys(-digits) + check_positive_integer "-digits" $digits + } else { + set digits $sta_report_default_digits + } + report_slack_wrt_clks $pin $scene $digits } ################################################################ @@ -990,16 +841,17 @@ proc report_tag_arrivals { pin } { ################################################################ define_hidden_cmd_args "total_negative_slack" \ - {[-corner corner] [-min]|[-max]} + {[-scene scene] [-min]|[-max]} proc total_negative_slack { args } { parse_key_args "total_negative_slack" args \ - keys {-corner} flags {-min -max} + keys {-scene -corner} flags {-min -max} check_argc_eq0 "total_negative_slack" $args set min_max [parse_min_max_flags flags] - if { [info exists keys(-corner)] } { - set corner [parse_corner_required keys] - set tns [total_negative_slack_corner_cmd $corner $min_max] + # compabibility 05/29/2025 + if { [info exists keys(-scene)] || [info exists keys(-corner)]} { + set scene [parse_scene_required keys] + set tns [total_negative_slack_scene_cmd $scene $min_max] } else { set tns [total_negative_slack_cmd $min_max] } @@ -1009,7 +861,7 @@ proc total_negative_slack { args } { ################################################################ define_hidden_cmd_args "worst_negative_slack" \ - {[-corner corner] [-min]|[-max]} + {[-scene scene] [-min]|[-max]} proc worst_negative_slack { args } { set worst_slack [worst_slack1 "worst_negative_slack" $args] @@ -1023,7 +875,7 @@ proc worst_negative_slack { args } { ################################################################ define_hidden_cmd_args "worst_slack" \ - {[-corner corner] [-min]|[-max]} + {[-scene scene] [-min]|[-max]} proc worst_slack { args } { return [worst_slack1 "worst_slack" $args] @@ -1032,12 +884,13 @@ proc worst_slack { args } { # arg parsing common to worst_slack/worst_negative_slack proc worst_slack1 { cmd args1 } { parse_key_args $cmd args1 \ - keys {-corner} flags {-min -max} + keys {-corner -scene} flags {-min -max} check_argc_eq0 $cmd $args1 set min_max [parse_min_max_flags flags] - if { [info exists keys(-corner)] } { - set corner [parse_corner_required keys] - set worst_slack [worst_slack_corner $corner $min_max] + # compabibility 05/29/2025 + if { [info exists keys(-scene)] || [info exists keys(-corner)]} { + set scene [parse_scene_required keys] + set worst_slack [worst_slack_scene $scene $min_max] } else { set worst_slack [worst_slack_cmd $min_max] } @@ -1067,14 +920,14 @@ proc worst_clock_skew { args } { ################################################################ -define_cmd_args "write_timing_model" {[-corner corner] \ +define_cmd_args "write_timing_model" {[-scene scene] \ [-library_name lib_name]\ [-cell_name cell_name]\ filename} proc write_timing_model { args } { parse_key_args "write_timing_model" args \ - keys {-library_name -cell_name -corner} flags {} + keys {-library_name -cell_name -scene} flags {} check_argc_eq1 "write_timing_model" $args set filename [file nativename [lindex $args 0]] @@ -1088,8 +941,8 @@ proc write_timing_model { args } { } else { set lib_name $cell_name } - set corner [parse_corner keys] - write_timing_model_cmd $lib_name $cell_name $filename $corner + set scene [parse_scene keys] + write_timing_model_cmd $lib_name $cell_name $filename $scene } diff --git a/search/SearchPred.cc b/search/SearchPred.cc index 9cb0401e..da7d5236 100644 --- a/search/SearchPred.cc +++ b/search/SearchPred.cc @@ -30,59 +30,113 @@ #include "Network.hh" #include "Graph.hh" #include "Sdc.hh" +#include "Mode.hh" #include "Levelize.hh" #include "Search.hh" #include "Latches.hh" +#include "Sim.hh" #include "Variables.hh" namespace sta { static bool -searchThruSimEdge(const Vertex *vertex, const RiseFall *rf); +searchThruSimEdge(const Vertex *vertex, + const RiseFall *rf, + const Mode *mode); static bool -searchThruTimingSense(const Edge *edge, const RiseFall *from_rf, - const RiseFall *to_rf); +searchThruTimingSense(const Edge *edge, + const RiseFall *from_rf, + const RiseFall *to_rf, + const Mode *mode); -SearchPred0::SearchPred0(const StaState *sta) : +SearchPred::SearchPred(const StaState *sta) : sta_(sta) { } -bool -SearchPred0::searchFrom(const Vertex *from_vertex) +void +SearchPred::copyState(const StaState *sta) { - return !(from_vertex->isDisabledConstraint() - || from_vertex->isConstant()); + sta_ = sta; } bool -SearchPred0::searchThru(Edge *edge) +SearchPred::searchFrom(const Vertex *from_vertex) const +{ + for (const Mode *mode : sta_->modes()) { + if (searchFrom(from_vertex, mode)) + return true; + } + return false; +} + +bool +SearchPred::searchThru(Edge *edge) const +{ + for (const Mode *mode : sta_->modes()) { + if (searchThru(edge, mode)) + return true; + } + return false; +} + +bool +SearchPred::searchTo(const Vertex *to_vertex) const +{ + for (const Mode *mode : sta_->modes()) { + if (searchTo(to_vertex, mode)) + return true; + } + return false; +} + +//////////////////////////////////////////////////////////////// + +SearchPred0::SearchPred0(const StaState *sta) : + SearchPred(sta) +{ +} + +bool +SearchPred0::searchFrom(const Vertex *from_vertex, + const Mode *mode) const +{ + const Pin *from_pin = from_vertex->pin(); + const Sdc *sdc = mode->sdc(); + const Sim *sim = mode->sim(); + return !(sdc->isDisabledConstraint(from_pin) + || sim->isConstant(from_vertex)); +} + +bool +SearchPred0::searchThru(Edge *edge, + const Mode *mode) const { const TimingRole *role = edge->role(); - const Sdc *sdc = sta_->sdc(); const Variables *variables = sta_->variables(); - return !(edge->isDisabledConstraint() - // Constants disable edge cond expression. - || edge->isDisabledCond() - || sdc->isDisabledCondDefault(edge) - // Register/latch preset/clr edges are disabled by default. - || (role == TimingRole::regSetClr() - && !variables->presetClrArcsEnabled()) - // Constants on other pins disable this edge (ie, a mux select). - || edge->simTimingSense() == TimingSense::none - || (edge->isBidirectInstPath() - && !variables->bidirectInstPathsEnabled()) - || (edge->isBidirectNetPath() - && !variables->bidirectNetPathsEnabled()) - || (role == TimingRole::latchDtoQ() - && sta_->latches()->latchDtoQState(edge) - == LatchEnableState::closed)); + const Sdc *sdc = mode->sdc(); + const Sim *sim = mode->sim(); + return !(sdc->isDisabledConstraint(edge) + // Constants disable edge cond expression. + || sim->isDisabledCond(edge) + || sdc->isDisabledCondDefault(edge) + // Register/latch preset/clr edges are disabled by default. + || (role == TimingRole::regSetClr() + && !variables->presetClrArcsEnabled()) + // Constants on other pins disable this edge (ie, a mux select). + || sim->simTimingSense(edge) == TimingSense::none + || (edge->isBidirectInstPath() + && !variables->bidirectInstPathsEnabled()) + || (role == TimingRole::latchDtoQ() + && sta_->latches()->latchDtoQState(edge, mode) + == LatchEnableState::closed)); } bool -SearchPred0::searchTo(const Vertex *to_vertex) +SearchPred0::searchTo(const Vertex *to_vertex, + const Mode *mode) const { - return !to_vertex->isConstant(); + return !mode->sim()->isConstant(to_vertex); } //////////////////////////////////////////////////////////////// @@ -93,123 +147,109 @@ SearchPred1::SearchPred1(const StaState *sta) : } bool -SearchPred1::searchThru(Edge *edge) +SearchPred1::searchThru(Edge *edge, + const Mode *mode) const { - return SearchPred0::searchThru(edge) + return SearchPred0::searchThru(edge, mode) && !edge->isDisabledLoop(); } //////////////////////////////////////////////////////////////// -SearchPred2::SearchPred2(const StaState *sta) : - SearchPred1(sta) -{ -} - -bool -SearchPred2::searchThru(Edge *edge) -{ - return SearchPred1::searchThru(edge) - && !edge->role()->isTimingCheck(); -} - -//////////////////////////////////////////////////////////////// - -SearchPredNonLatch2::SearchPredNonLatch2(const StaState *sta) : - SearchPred2(sta) -{ -} - -bool -SearchPredNonLatch2::searchThru(Edge *edge) -{ - return SearchPred2::searchThru(edge) - && !sta_->latches()->isLatchDtoQ(edge); -} - -//////////////////////////////////////////////////////////////// - -SearchPredNonReg2::SearchPredNonReg2(const StaState *sta) : - SearchPred2(sta) -{ -} - -bool -SearchPredNonReg2::searchThru(Edge *edge) -{ - const TimingRole *role = edge->role(); - return SearchPred2::searchThru(edge) - // Enqueue thru latches is handled explicitly by search. - && !sta_->latches()->isLatchDtoQ(edge) - && role->genericRole() != TimingRole::regClkToQ(); -} - -//////////////////////////////////////////////////////////////// - ClkTreeSearchPred::ClkTreeSearchPred(const StaState *sta) : - SearchPred1(sta) + SearchPred(sta) { } bool -ClkTreeSearchPred::searchThru(Edge *edge) +ClkTreeSearchPred::searchFrom(const Vertex *from_vertex, + const Mode *mode) const +{ + const Pin *from_pin = from_vertex->pin(); + const Sdc *sdc = mode->sdc(); + return !sdc->isDisabledConstraint(from_pin); +} + +bool +ClkTreeSearchPred::searchThru(Edge *edge, + const Mode *mode) const { - // Propagate clocks through constants. const TimingRole *role = edge->role(); - return (role->isWire() - || role == TimingRole::combinational()) - && (sta_->variables()->clkThruTristateEnabled() - || !(role == TimingRole::tristateEnable() - || role == TimingRole::tristateDisable())) - && SearchPred1::searchThru(edge); + const Sdc *sdc = mode->sdc(); + return searchThruAllow(role) + && !((role == TimingRole::tristateEnable() + && !sta_->variables()->clkThruTristateEnabled()) + || role == TimingRole::regSetClr() + || sdc->isDisabledConstraint(edge) + || sdc->isDisabledCondDefault(edge) + || edge->isBidirectInstPath() + || edge->isDisabledLoop()); +} + +bool +ClkTreeSearchPred::searchThruAllow(const TimingRole *role) const +{ + return role->isWire() + || role == TimingRole::combinational(); } bool isClkEnd(Vertex *vertex, - Graph *graph) + const Mode *mode) { + Graph *graph = mode->graph(); ClkTreeSearchPred pred(graph); VertexOutEdgeIterator edge_iter(vertex, graph); while (edge_iter.hasNext()) { Edge *edge = edge_iter.next(); - if (pred.searchThru(edge)) + if (pred.searchThru(edge, mode)) return false; } return true; } +bool +ClkTreeSearchPred::searchTo(const Vertex *, + const Mode *) const +{ + return true; +} + //////////////////////////////////////////////////////////////// bool searchThru(const Edge *edge, - const TimingArc *arc, - const Graph *graph) + const TimingArc *arc, + const Mode *mode) { + const Graph *graph = mode->graph(); const RiseFall *from_rf = arc->fromEdge()->asRiseFall(); const RiseFall *to_rf = arc->toEdge()->asRiseFall(); // Ignore transitions other than rise/fall. return from_rf && to_rf - && searchThru(edge->from(graph), from_rf, edge, edge->to(graph), to_rf); + && searchThru(edge->from(graph), from_rf, edge, edge->to(graph), to_rf, mode); } bool searchThru(Vertex *from_vertex, - const RiseFall *from_rf, - const Edge *edge, - Vertex *to_vertex, - const RiseFall *to_rf) + const RiseFall *from_rf, + const Edge *edge, + Vertex *to_vertex, + const RiseFall *to_rf, + const Mode *mode) { - return searchThruTimingSense(edge, from_rf, to_rf) - && searchThruSimEdge(from_vertex, from_rf) - && searchThruSimEdge(to_vertex, to_rf); + return searchThruTimingSense(edge, from_rf, to_rf, mode) + && searchThruSimEdge(from_vertex, from_rf, mode) + && searchThruSimEdge(to_vertex, to_rf, mode); } // set_case_analysis rising/falling filters rise/fall edges during search. static bool searchThruSimEdge(const Vertex *vertex, - const RiseFall *rf) + const RiseFall *rf, + const Mode *mode) { - LogicValue sim_value = vertex->simValue(); + LogicValue sim_value = mode->sim()->simValue(vertex->pin()); switch (sim_value) { case LogicValue::rise: return rf == RiseFall::rise(); @@ -221,10 +261,12 @@ searchThruSimEdge(const Vertex *vertex, } static bool -searchThruTimingSense(const Edge *edge, const RiseFall *from_rf, - const RiseFall *to_rf) +searchThruTimingSense(const Edge *edge, + const RiseFall *from_rf, + const RiseFall *to_rf, + const Mode *mode) { - switch (edge->simTimingSense()) { + switch (mode->sim()->simTimingSense(edge)) { case TimingSense::unknown: return true; case TimingSense::positive_unate: @@ -244,17 +286,18 @@ searchThruTimingSense(const Edge *edge, const RiseFall *from_rf, bool hasFanin(Vertex *vertex, - SearchPred *pred, - const Graph *graph) + SearchPred *pred, + const Graph *graph, + const Mode *mode) { - if (pred->searchTo(vertex)) { + if (pred->searchTo(vertex, mode)) { VertexInEdgeIterator edge_iter(vertex, graph); while (edge_iter.hasNext()) { Edge *edge = edge_iter.next(); Vertex *from_vertex = edge->from(graph); - if (pred->searchFrom(from_vertex) - && pred->searchThru(edge)) - return true; + if (pred->searchFrom(from_vertex, mode) + && pred->searchThru(edge, mode)) + return true; } } return false; @@ -262,17 +305,18 @@ hasFanin(Vertex *vertex, bool hasFanout(Vertex *vertex, - SearchPred *pred, - const Graph *graph) + SearchPred *pred, + const Graph *graph, + const Mode *mode) { - if (pred->searchFrom(vertex)) { + if (pred->searchFrom(vertex, mode)) { VertexOutEdgeIterator edge_iter(vertex, graph); while (edge_iter.hasNext()) { Edge *edge = edge_iter.next(); Vertex *to_vertex = edge->to(graph); - if (pred->searchTo(to_vertex) - && pred->searchThru(edge)) - return true; + if (pred->searchTo(to_vertex, mode) + && pred->searchThru(edge, mode)) + return true; } } return false; diff --git a/search/Sim.cc b/search/Sim.cc index 959b088b..70b6384e 100644 --- a/search/Sim.cc +++ b/search/Sim.cc @@ -27,6 +27,7 @@ // https://davidkebo.com/cudd #include "cudd.h" +#include "ContainerHelpers.hh" #include "Error.hh" #include "Mutex.hh" #include "Debug.hh" @@ -41,6 +42,7 @@ #include "Network.hh" #include "Sdc.hh" #include "Graph.hh" +#include "Mode.hh" namespace sta { @@ -48,10 +50,11 @@ static LogicValue logicNot(LogicValue value); static const Pin * findDrvrPin(const Pin *pin, - Network *network); + Network *network); Sim::Sim(StaState *sta) : StaState(sta), + mode_(nullptr), observer_(nullptr), valid_(false), incremental_(false), @@ -60,7 +63,6 @@ Sim::Sim(StaState *sta) : invalid_insts_(network_), invalid_drvr_pins_(network_), invalid_load_pins_(network_), - instances_with_const_pins_(network_), instances_to_annotate_(network_), bdd_(sta) { @@ -71,10 +73,24 @@ Sim::~Sim() delete observer_; } +void +Sim::copyState(const StaState *sta) +{ + StaState::copyState(sta); + // Notify sub-components. + observer_->copyState(sta); +} + +void +Sim::setMode(Mode *mode) +{ + mode_ = mode; +} + TimingSense Sim::functionSense(const FuncExpr *expr, - const Pin *input_pin, - const Instance *inst) + const Pin *input_pin, + const Instance *inst) { debugPrint(debug_, "sim", 4, "find sense pin %s %s", network_->pathName(input_pin), @@ -88,9 +104,9 @@ Sim::functionSense(const FuncExpr *expr, DdNode *input_node = bdd_.ensureNode(input_port); unsigned int input_index = Cudd_NodeReadIndex(input_node); increasing = (Cudd_Increasing(cudd_mgr, bdd, input_index) - == Cudd_ReadOne(cudd_mgr)); + == Cudd_ReadOne(cudd_mgr)); decreasing = (Cudd_Decreasing(cudd_mgr, bdd, input_index) - == Cudd_ReadOne(cudd_mgr)); + == Cudd_ReadOne(cudd_mgr)); Cudd_RecursiveDeref(cudd_mgr, bdd); bdd_.clearVarMap(); } @@ -109,7 +125,7 @@ Sim::functionSense(const FuncExpr *expr, LogicValue Sim::evalExpr(const FuncExpr *expr, - const Instance *inst) + const Instance *inst) { LockGuard lock(bdd_lock_); DdNode *bdd = funcBddSim(expr, inst); @@ -140,7 +156,7 @@ Sim::funcBddSim(const FuncExpr *expr, const LibertyPort *port = network_->libertyPort(pin); DdNode *port_node = bdd_.findNode(port); if (port_node) { - LogicValue value = logicValue(pin); + LogicValue value = simValue(pin); int var_index = Cudd_NodeReadIndex(port_node); switch (value) { case LogicValue::zero: @@ -164,8 +180,8 @@ static LogicValue logicNot(LogicValue value) { static LogicValue logic_not[5] = {LogicValue::one, LogicValue::zero, - LogicValue::unknown, LogicValue::unknown, - LogicValue::unknown}; + LogicValue::unknown, LogicValue::unknown, + LogicValue::unknown}; return logic_not[int(value)]; } @@ -176,11 +192,11 @@ Sim::clear() incremental_ = false; const_func_pins_.clear(); const_func_pins_valid_ = false; - instances_with_const_pins_.clear(); instances_to_annotate_.clear(); invalid_insts_.clear(); invalid_drvr_pins_.clear(); invalid_load_pins_.clear(); + clearSimValues(); } void @@ -190,6 +206,89 @@ Sim::setObserver(SimObserver *observer) observer_ = observer; } +SimObserver::SimObserver(StaState *sta) : + StaState(sta) +{ +} + +LogicValue +Sim::simValue(const Vertex *vertex) const +{ + if (vertex->hasSimValue()) { + LogicValue value; + bool exists; + findKeyValue(sim_value_map_, vertex->pin(), value, exists); + if (exists) + return value; + } + return LogicValue::unknown; +} + +LogicValue +Sim::simValue(const Pin *pin) const +{ + Vertex *vertex = graph_->pinLoadVertex(pin); + if (vertex) + return simValue(vertex); + LogicValue value; + bool exists; + findKeyValue(sim_value_map_, pin, value, exists); + if (exists) + return value; + else + return LogicValue::unknown; +} + +bool +Sim::isConstant(const Vertex *vertex) const +{ + LogicValue value = simValue(vertex); + return value == LogicValue::zero + || value == LogicValue::one; +} + +bool +Sim::isConstant(const Pin *pin) const +{ + LogicValue value = simValue(pin); + return value == LogicValue::zero + || value == LogicValue::one; +} + +TimingSense +Sim::simTimingSense(const Edge *edge) const +{ + if (edge->hasSimSense()) { + TimingSense sense; + bool exists; + findKeyValue(edge_timing_sense_map_, edge, sense, exists); + if (exists) + return sense; + } + return TimingSense::unknown; +} + +void +Sim::setSimTimingSense(Edge *edge, + TimingSense sense) +{ + if (sense == TimingSense::unknown) + edge_timing_sense_map_.erase(edge); + else { + edge_timing_sense_map_[edge] = sense; + edge->setHasSimSense(true); + } +} + +bool +Sim::isDisabledCond(const Edge *edge) const +{ + return edge->hasDisabledCond() + && edge_disabled_cond_set_.contains(edge); +} + +//////////////////////////////////////////////////////////////// + void Sim::ensureConstantsPropagated() { @@ -208,7 +307,7 @@ Sim::ensureConstantsPropagated() } invalid_insts_.clear(); propagateConstants(false); - annotateGraphEdges(); + findDisabledEdges(); valid_ = true; incremental_ = true; @@ -246,7 +345,7 @@ Sim::propagateToInvalidLoads() else { const Pin *drvr_pin = findDrvrPin(load_pin, network_); if (drvr_pin) - propagateDrvrToLoad(drvr_pin, load_pin); + propagateDrvrToLoad(drvr_pin, load_pin); } } invalid_load_pins_.clear(); @@ -256,15 +355,15 @@ void Sim::propagateFromInvalidDrvrsToLoads() { for (const Pin *drvr_pin : invalid_drvr_pins_) { - LogicValue value = const_func_pins_.hasKey(drvr_pin) + LogicValue value = const_func_pins_.contains(drvr_pin) ? pinConstFuncValue(drvr_pin) - : logicValue(drvr_pin); + : simValue(drvr_pin); PinConnectedPinIterator *load_iter=network_->connectedPinIterator(drvr_pin); while (load_iter->hasNext()) { const Pin *load_pin = load_iter->next(); if (load_pin != drvr_pin - && network_->isLoad(load_pin)) - setPinValue(load_pin, value); + && network_->isLoad(load_pin)) + setPinValue(load_pin, value); } delete load_iter; } @@ -273,9 +372,9 @@ Sim::propagateFromInvalidDrvrsToLoads() void Sim::propagateDrvrToLoad(const Pin *drvr_pin, - const Pin *load_pin) + const Pin *load_pin) { - LogicValue value = logicValue(drvr_pin); + LogicValue value = simValue(drvr_pin); setPinValue(load_pin, value); } @@ -295,8 +394,8 @@ Sim::ensureConstantFuncPins() Instance *inst = inst_iter->next(); InstancePinIterator *pin_iter = network_->pinIterator(inst); while (pin_iter->hasNext()) { - const Pin *pin = pin_iter->next(); - recordConstPinFunc(pin); + const Pin *pin = pin_iter->next(); + recordConstPinFunc(pin); } delete pin_iter; } @@ -312,10 +411,10 @@ Sim::recordConstPinFunc(const Pin *pin) if (port) { FuncExpr *expr = port->function(); if (expr - // Tristate outputs do not force the output to be constant. - && port->tristateEnable() == nullptr - && (expr->op() == FuncExpr::op_zero - || expr->op() == FuncExpr::op_one)) + // Tristate outputs do not force the output to be constant. + && port->tristateEnable() == nullptr + && (expr->op() == FuncExpr::Op::zero + || expr->op() == FuncExpr::Op::one)) const_func_pins_.insert(pin); } } @@ -323,7 +422,6 @@ Sim::recordConstPinFunc(const Pin *pin) void Sim::deleteInstanceBefore(const Instance *inst) { - instances_with_const_pins_.erase(inst); invalid_insts_.erase(inst); } @@ -337,6 +435,7 @@ Sim::makePinAfter(const Pin *pin) void Sim::deletePinBefore(const Pin *pin) { + sim_value_map_.erase(pin); // Incrementally update const_func_pins_. const_func_pins_.erase(pin); invalid_load_pins_.erase(pin); @@ -373,12 +472,8 @@ Sim::disconnectPinBefore(const Pin *pin) void Sim::pinSetFuncAfter(const Pin *pin) { - if (incremental_) { - Instance *inst = network_->instance(pin); - if (instances_with_const_pins_.hasKey(inst)) - invalid_insts_.insert(inst); + if (incremental_) valid_ = false; - } // Incrementally update const_func_pins_. const_func_pins_.erase(pin); recordConstPinFunc(pin); @@ -387,12 +482,13 @@ Sim::pinSetFuncAfter(const Pin *pin) void Sim::seedConstants() { + const Sdc *sdc = mode_->sdc(); // Propagate constants from inputs tied hi/low in the network. enqueueConstantPinInputs(); - // Propagate set_LogicValue::zero, set_LogicValue::one, set_logic_dc constants. - setConstraintConstPins(sdc_->logicValues()); + // Propagate set_logic_zero/one/dc constants. + setConstraintConstPins(sdc->logicValues()); // Propagate set_case_analysis constants. - setConstraintConstPins(sdc_->caseLogicValues()); + setConstraintConstPins(sdc->caseLogicValues()); // Propagate 0/1 constant functions. setConstFuncPins(); } @@ -408,7 +504,7 @@ Sim::propagateConstants(bool thru_sequentials) } void -Sim::setConstraintConstPins(LogicValueMap &value_map) +Sim::setConstraintConstPins(const LogicValueMap &value_map) { for (const auto [pin, value] : value_map) { debugPrint(debug_, "sim", 2, "case pin %s = %c", @@ -419,12 +515,12 @@ Sim::setConstraintConstPins(LogicValueMap &value_map) bool pin_is_output = network_->direction(pin)->isAnyOutput(); PinConnectedPinIterator *pin_iter=network_->connectedPinIterator(pin); while (pin_iter->hasNext()) { - const Pin *pin1 = pin_iter->next(); - if (network_->isLeaf(pin1) - && network_->direction(pin1)->isAnyInput() - && ((pin_is_output && !network_->isInside(pin1, pin)) - || (!pin_is_output && network_->isInside(pin1, pin)))) - setPinValue(pin1, value); + const Pin *pin1 = pin_iter->next(); + if (network_->isLeaf(pin1) + && network_->direction(pin1)->isAnyInput() + && ((pin_is_output && !network_->isInside(pin1, pin)) + || (!pin_is_output && network_->isInside(pin1, pin)))) + setPinValue(pin1, value); } delete pin_iter; } @@ -453,9 +549,9 @@ Sim::pinConstFuncValue(const Pin *pin) LibertyPort *port = network_->libertyPort(pin); if (port) { FuncExpr *expr = port->function(); - if (expr->op() == FuncExpr::op_zero) + if (expr->op() == FuncExpr::Op::zero) return LogicValue::zero; - else if (expr->op() == FuncExpr::op_one) + else if (expr->op() == FuncExpr::Op::one) return LogicValue::one; } return LogicValue::unknown; @@ -481,66 +577,50 @@ void Sim::removePropagatedValue(const Pin *pin) { Instance *inst = network_->instance(pin); - if (instances_with_const_pins_.hasKey(inst)) { - invalid_insts_.insert(inst); - valid_ = false; + invalid_insts_.insert(inst); + valid_ = false; - LogicValue constraint_value; - bool exists; - sdc_->caseLogicValue(pin, constraint_value, exists); + const Sdc *sdc = mode_->sdc(); + LogicValue constraint_value; + bool exists; + sdc->caseLogicValue(pin, constraint_value, exists); + if (!exists) { + sdc->logicValue(pin, constraint_value, exists); if (!exists) { - sdc_->logicValue(pin, constraint_value, exists); - if (!exists) { - debugPrint(debug_, "sim", 2, "pin %s remove prop constant", - network_->pathName(pin)); - Vertex *vertex, *bidirect_drvr_vertex; - graph_->pinVertices(pin, vertex, bidirect_drvr_vertex); - if (vertex) - setSimValue(vertex, LogicValue::unknown); - if (bidirect_drvr_vertex) - setSimValue(bidirect_drvr_vertex, LogicValue::unknown); - } + debugPrint(debug_, "sim", 2, "pin %s remove prop constant", + network_->pathName(pin)); + setSimValue(pin, LogicValue::unknown); } } } void Sim::setPinValue(const Pin *pin, - LogicValue value) + LogicValue value) { + const Sdc *sdc = mode_->sdc(); LogicValue constraint_value; bool exists; - sdc_->caseLogicValue(pin, constraint_value, exists); + sdc->caseLogicValue(pin, constraint_value, exists); if (!exists) - sdc_->logicValue(pin, constraint_value, exists); + sdc->logicValue(pin, constraint_value, exists); if (exists && value != constraint_value) { if (value != LogicValue::unknown) report_->warn(1521, "propagated logic value %c differs from constraint value of %c on pin %s.", - logicValueString(value), - logicValueString(constraint_value), - sdc_network_->pathName(pin)); + logicValueString(value), + logicValueString(constraint_value), + sdc_network_->pathName(pin)); } else { debugPrint(debug_, "sim", 3, "pin %s = %c", network_->pathName(pin), logicValueString(value)); - Vertex *vertex, *bidirect_drvr_vertex; - graph_->pinVertices(pin, vertex, bidirect_drvr_vertex); - // Set vertex constant flags. bool value_changed = false; - if (vertex) { - value_changed |= value != vertex->simValue(); - setSimValue(vertex, value); - } - if (bidirect_drvr_vertex) { - value_changed |= value != bidirect_drvr_vertex->simValue(); - setSimValue(bidirect_drvr_vertex, value); - } + value_changed |= value != simValue(pin); + setSimValue(pin, value); if (value_changed) { Instance *inst = network_->instance(pin); - if (logicValueZeroOne(value)) - instances_with_const_pins_.insert(inst); instances_to_annotate_.insert(inst); if (network_->isLeaf(inst) @@ -577,9 +657,9 @@ Sim::evalInstance(const Instance *inst, PortDirection *dir = port->direction(); if (dir->isAnyOutput()) { LogicValue value = LogicValue::unknown; - FuncExpr *expr = port->function(); + FuncExpr *expr = port->function(); LibertyCell *cell = port->libertyCell(); - if (expr) { + if (expr) { FuncExpr *tri_en_expr = port->tristateEnable(); if (tri_en_expr) { if (evalExpr(tri_en_expr, inst) == LogicValue::one) { @@ -619,7 +699,7 @@ Sim::evalInstance(const Instance *inst, port->name(), logicValueString(value)); } - if (value != logicValue(pin)) + if (value != simValue(pin)) setPinValue(pin, value); } } @@ -637,33 +717,41 @@ Sim::clockGateOutValue(const Instance *inst) if (port->isClockGateClock() || port->isClockGateEnable()) { Pin *gclk_pin = network_->findPin(inst, port); - if (gclk_pin) { - Vertex *gclk_vertex = graph_->pinLoadVertex(gclk_pin); - if (gclk_vertex->simValue() == LogicValue::zero) - return LogicValue::zero; - } + if (gclk_pin + && simValue(gclk_pin) == LogicValue::zero) + return LogicValue::zero; } } return LogicValue::unknown; } void -Sim::setSimValue(Vertex *vertex, - LogicValue value) +Sim::setSimValue(const Pin *pin, + LogicValue value) { - if (value != vertex->simValue()) { - vertex->setSimValue(value); + if (value != simValue(pin)) { + if (value == LogicValue::unknown) + sim_value_map_.erase(pin); + else { + sim_value_map_[pin] = value; + Vertex *vertex, *bidirect_drvr_vertex; + graph_->pinVertices(pin, vertex, bidirect_drvr_vertex); + if (vertex) + vertex->setHasSimValue(true); + if (bidirect_drvr_vertex) + bidirect_drvr_vertex->setHasSimValue(true); + } if (observer_) - observer_->valueChangeAfter(vertex); + observer_->valueChangeAfter(pin); } } TimingSense Sim::functionSense(const Instance *inst, - const Pin *from_pin, - const Pin *to_pin) + const Pin *from_pin, + const Pin *to_pin) { - if (logicZeroOne(from_pin)) + if (isConstant((from_pin))) return TimingSense::none; else { LibertyPort *from_port = network_->libertyPort(from_pin); @@ -671,144 +759,204 @@ Sim::functionSense(const Instance *inst, if (to_port) { const FuncExpr *func = to_port->function(); if (func) { - PortDirection *to_dir = to_port->direction(); - if (to_dir->isAnyTristate()) { - FuncExpr *tri_func = to_port->tristateEnable(); - if (tri_func) { - if (func->hasPort(from_port)) { - // from_pin is an input to the to_pin function. - LogicValue tri_enable = evalExpr(tri_func, inst); - if (tri_enable == LogicValue::zero) - // Tristate is disabled. - return TimingSense::none; - else - return functionSense(func, from_pin, inst); - } - } - else { - // Missing tristate enable function. - if (func->hasPort(from_port)) - // from_pin is an input to the to_pin function. - return functionSense(func, from_pin, inst); - } - } - else { - if (func->hasPort(from_port)) - // from_pin is an input to the to_pin function. - return functionSense(func, from_pin, inst); - } + PortDirection *to_dir = to_port->direction(); + if (to_dir->isAnyTristate()) { + FuncExpr *tri_func = to_port->tristateEnable(); + if (tri_func) { + if (func->hasPort(from_port)) { + // from_pin is an input to the to_pin function. + LogicValue tri_enable = evalExpr(tri_func, inst); + if (tri_enable == LogicValue::zero) + // Tristate is disabled. + return TimingSense::none; + else + return functionSense(func, from_pin, inst); + } + } + else { + // Missing tristate enable function. + if (func->hasPort(from_port)) + // from_pin is an input to the to_pin function. + return functionSense(func, from_pin, inst); + } + } + else { + if (func->hasPort(from_port)) + // from_pin is an input to the to_pin function. + return functionSense(func, from_pin, inst); + } } } return TimingSense::unknown; } } -LogicValue -Sim::logicValue(const Pin *pin) const -{ - Vertex *vertex = graph_->pinLoadVertex(pin); - if (vertex) - return vertex->simValue(); - else { - if (network_->isHierarchical(pin)) { - const Pin *drvr_pin = findDrvrPin(pin, network_); - if (drvr_pin) - return logicValue(drvr_pin); - } - return LogicValue::unknown; - } -} - static const Pin * findDrvrPin(const Pin *pin, - Network *network) + Network *network) { PinSet *drvrs = network->drivers(pin); - if (drvrs) { - PinSet::Iterator drvr_iter(drvrs); - if (drvr_iter.hasNext()) - return drvr_iter.next(); - } - return nullptr; -} - -bool -logicValueZeroOne(LogicValue value) -{ - return value == LogicValue::zero || value == LogicValue::one; -} - -bool -Sim::logicZeroOne(const Pin *pin) const -{ - return logicValueZeroOne(logicValue(pin)); -} - -bool -Sim::logicZeroOne(const Vertex *vertex) const -{ - return logicValueZeroOne(vertex->simValue()); + if (drvrs && !drvrs->empty()) + return *drvrs->begin(); + else + return nullptr; } void Sim::clearSimValues() { - for (const Instance *inst : instances_with_const_pins_) { - // Clear sim values on all pins before evaling functions. - clearInstSimValues(inst); - annotateVertexEdges(inst, false); + for (auto const [pin, value] : sim_value_map_) + observer_->valueChangeAfter(pin); + sim_value_map_.clear(); + edge_timing_sense_map_.clear(); + edge_disabled_cond_set_.clear(); +} + +//////////////////////////////////////////////////////////////// + +void +Sim::setIsDisabledCond(Edge *edge, + bool disabled) +{ + if (!disabled) + edge_disabled_cond_set_.erase(edge); + else { + edge_disabled_cond_set_.insert(edge); + edge->setHasDisabledCond(true); } - instances_with_const_pins_.clear(); +} + +bool +Sim::isDisabledCond(Edge *edge, + const Instance *inst, + const Pin *from_pin, + const Pin *to_pin) +{ + bool is_disabled; + FuncExpr *disable_cond; + isDisabledCond(edge, inst, from_pin, to_pin, is_disabled, disable_cond); + return is_disabled; } void -Sim::clearInstSimValues(const Instance *inst) +Sim::isDisabledCond(Edge *edge, + const Instance *inst, + const Pin *from_pin, + const Pin *to_pin, + // Return values. + bool &is_disabled, + FuncExpr *&disable_cond) { - debugPrint(debug_, "sim", 4, "clear %s", - network_->pathName(inst)); - InstancePinIterator *pin_iter = network_->pinIterator(inst); - while (pin_iter->hasNext()) { - Pin *pin = pin_iter->next(); - Vertex *vertex, *bidirect_drvr_vertex; - graph_->pinVertices(pin, vertex, bidirect_drvr_vertex); - if (vertex) - setSimValue(vertex, LogicValue::unknown); - if (bidirect_drvr_vertex) - setSimValue(bidirect_drvr_vertex, LogicValue::unknown); + TimingArcSet *arc_set = edge->timingArcSet(); + FuncExpr *cond = arc_set->cond(); + if (cond) { + LogicValue cond_value = evalExpr(cond, inst); + disable_cond = cond; + is_disabled = (cond_value == LogicValue::zero); + } + else { + // Unconditional "default" arc set is disabled if another + // conditional arc from/to the same pins is enabled (condition + // evals to logic one). + LibertyCell *cell = network_->libertyCell(inst); + LibertyPort *from_port = network_->libertyPort(from_pin); + LibertyPort *to_port = network_->libertyPort(to_pin); + is_disabled = false; + for (TimingArcSet *cond_set : cell->timingArcSets(from_port, to_port)) { + FuncExpr *cond = cond_set->cond(); + if (cond && evalExpr(cond, inst) == LogicValue::one) { + disable_cond = cond; + is_disabled = true; + break; + } + } } - delete pin_iter; } -// Annotate graph edges disabled by constant values. -void -Sim::annotateGraphEdges() +bool +Sim::isDisabledMode(Edge *edge, + const Instance *inst) { - for (const Instance *inst : instances_to_annotate_) - annotateVertexEdges(inst, true); + bool is_disabled; + FuncExpr *disable_cond; + isDisabledMode(edge, inst, is_disabled, disable_cond); + return is_disabled; } void -Sim::annotateVertexEdges(const Instance *inst, - bool annotate) +Sim::isDisabledMode(Edge *edge, + const Instance *inst, + // Return values. + bool &is_disabled, + FuncExpr *&disable_cond) { - debugPrint(debug_, "sim", 4, "annotate %s %s", - network_->pathName(inst), - annotate ? "true" : "false"); + // Default values. + is_disabled = false; + disable_cond = 0; + TimingArcSet *arc_set = edge->timingArcSet(); + const char *mode_name = arc_set->modeName(); + const char *mode_value = arc_set->modeValue(); + if (mode_name && mode_value) { + LibertyCell *cell = network_->libertyCell(inst); + ModeDef *mode_def = cell->findModeDef(mode_name); + if (mode_def) { + ModeValueDef *value_def = mode_def->findValueDef(mode_value); + if (value_def) { + FuncExpr *cond = value_def->cond(); + if (cond) { + LogicValue cond_value = evalExpr(cond, inst); + if (cond_value == LogicValue::zero) { + // For a mode value to be disabled by having a value of + // logic zero one mode value must logic one. + for (const auto [name, value_def] : *mode_def->values()) { + if (value_def) { + FuncExpr *cond1 = value_def->cond(); + if (cond1) { + LogicValue cond_value1 = evalExpr(cond1, inst); + if (cond_value1 == LogicValue::one) { + disable_cond = cond; + is_disabled = true; + break; + } + } + } + } + } + } + } + } + } +} + +//////////////////////////////////////////////////////////////// + +// Find graph edges disabled by constant values. +void +Sim::findDisabledEdges() +{ + for (const Instance *inst : instances_to_annotate_) + findDisabledEdges(inst); + instances_to_annotate_.clear(); +} + +void +Sim::findDisabledEdges(const Instance *inst) +{ + debugPrint(debug_, "sim", 4, "annotate %s", network_->pathName(inst)); InstancePinIterator *pin_iter = network_->pinIterator(inst); while (pin_iter->hasNext()) { Pin *pin = pin_iter->next(); Vertex *vertex = graph_->pinDrvrVertex(pin); if (vertex) - annotateVertexEdges(inst, pin, vertex, annotate); + findDisabledEdges(inst, pin, vertex); } delete pin_iter; } void -Sim::annotateVertexEdges(const Instance *inst, - const Pin *pin, - Vertex *vertex, - bool annotate) +Sim::findDisabledEdges(const Instance *inst, + const Pin *pin, + Vertex *vertex) { bool fanin_disables_changed = false; VertexInEdgeIterator edge_iter(vertex, graph_); @@ -819,148 +967,36 @@ Sim::annotateVertexEdges(const Instance *inst, Pin *from_pin = from_vertex->pin(); TimingSense sense = TimingSense::unknown; bool is_disabled_cond = false; - if (annotate) { - // Set timing sense on edges in instances that have constant pins. - if (logicZeroOne(from_vertex)) - sense = TimingSense::none; - else - sense = functionSense(inst, from_pin, pin); + // Set timing sense on edges in instances that have constant pins. + if (isConstant(from_vertex)) + sense = TimingSense::none; + else + sense = functionSense(inst, from_pin, pin); + + if (sense != TimingSense::none) + // Disable conditional timing edges based on constant pins. + is_disabled_cond = isDisabledCond(edge, inst, from_pin, pin) + // Disable mode conditional timing + // edges based on constant pins. + || isDisabledMode(edge,inst); - if (sense != TimingSense::none) - // Disable conditional timing edges based on constant pins. - is_disabled_cond = isCondDisabled(edge, inst, from_pin, - pin, network_,sim_) - // Disable mode conditional timing - // edges based on constant pins. - || isModeDisabled(edge,inst,network_,sim_); - } bool disables_changed = false; - if (sense != edge->simTimingSense()) { - edge->setSimTimingSense(sense); - disables_changed = true; - fanin_disables_changed = true; + if (sense != simTimingSense(edge)) { + setSimTimingSense(edge, sense); + disables_changed = true; + fanin_disables_changed = true; } - if (is_disabled_cond != edge->isDisabledCond()) { - edge->setIsDisabledCond(is_disabled_cond); - disables_changed = true; - fanin_disables_changed = true; + if (is_disabled_cond != isDisabledCond(edge)) { + setIsDisabledCond(edge, is_disabled_cond); + disables_changed = true; + fanin_disables_changed = true; } if (observer_ && disables_changed) - observer_->fanoutEdgesChangeAfter(from_vertex); + observer_->fanoutEdgesChangeAfter(from_vertex->pin()); } } if (observer_ && fanin_disables_changed) - observer_->faninEdgesChangeAfter(vertex); -} - -bool -isCondDisabled(Edge *edge, - const Instance *inst, - const Pin *from_pin, - const Pin *to_pin, - const Network *network, - Sim *sim) -{ - bool is_disabled; - FuncExpr *disable_cond; - isCondDisabled(edge, inst, from_pin, to_pin, network, sim, - is_disabled, disable_cond); - return is_disabled; -} - -void -isCondDisabled(Edge *edge, - const Instance *inst, - const Pin *from_pin, - const Pin *to_pin, - const Network *network, - Sim *sim, - bool &is_disabled, - FuncExpr *&disable_cond) -{ - TimingArcSet *arc_set = edge->timingArcSet(); - FuncExpr *cond = arc_set->cond(); - if (cond) { - LogicValue cond_value = sim->evalExpr(cond, inst); - disable_cond = cond; - is_disabled = (cond_value == LogicValue::zero); - } - else { - // Unconditional "default" arc set is disabled if another - // conditional arc from/to the same pins is enabled (condition - // evals to logic one). - LibertyCell *cell = network->libertyCell(inst); - LibertyPort *from_port = network->libertyPort(from_pin); - LibertyPort *to_port = network->libertyPort(to_pin); - is_disabled = false; - for (TimingArcSet *cond_set : cell->timingArcSets(from_port, to_port)) { - FuncExpr *cond = cond_set->cond(); - if (cond && sim->evalExpr(cond, inst) == LogicValue::one) { - disable_cond = cond; - is_disabled = true; - break; - } - } - } -} - -bool -isModeDisabled(Edge *edge, - const Instance *inst, - const Network *network, - Sim *sim) -{ - bool is_disabled; - FuncExpr *disable_cond; - isModeDisabled(edge, inst, network, sim, - is_disabled, disable_cond); - return is_disabled; -} - -void -isModeDisabled(Edge *edge, - const Instance *inst, - const Network *network, - Sim *sim, - bool &is_disabled, - FuncExpr *&disable_cond) -{ - // Default values. - is_disabled = false; - disable_cond = 0; - TimingArcSet *arc_set = edge->timingArcSet(); - const char *mode_name = arc_set->modeName(); - const char *mode_value = arc_set->modeValue(); - if (mode_name && mode_value) { - LibertyCell *cell = network->libertyCell(inst); - ModeDef *mode_def = cell->findModeDef(mode_name); - if (mode_def) { - ModeValueDef *value_def = mode_def->findValueDef(mode_value); - if (value_def) { - FuncExpr *cond = value_def->cond(); - if (cond) { - LogicValue cond_value = sim->evalExpr(cond, inst); - if (cond_value == LogicValue::zero) { - // For a mode value to be disabled by having a value of - // logic zero one mode value must logic one. - for (const auto [name, value_def] : *mode_def->values()) { - if (value_def) { - FuncExpr *cond1 = value_def->cond(); - if (cond1) { - LogicValue cond_value1 = sim->evalExpr(cond1, inst); - if (cond_value1 == LogicValue::one) { - disable_cond = cond; - is_disabled = true; - break; - } - } - } - } - } - } - } - } - } + observer_->faninEdgesChangeAfter(vertex->pin()); } } // namespace diff --git a/search/Sim.hh b/search/Sim.hh index 958e9d82..84117094 100644 --- a/search/Sim.hh +++ b/search/Sim.hh @@ -26,9 +26,10 @@ #include #include +#include +#include #include "StaConfig.hh" // CUDD -#include "Map.hh" #include "NetworkClass.hh" #include "GraphClass.hh" #include "SdcClass.hh" @@ -39,33 +40,75 @@ namespace sta { class SimObserver; -typedef Map PinValueMap; -typedef std::queue EvalQueue; +using SimValueMap = std::unordered_map; +using EdgeDisabledCondSet = std::unordered_set; +using EdgeTimingSenseMap = std::unordered_map; +using EvalQueue = std::queue; // Propagate constants from constraints and netlist tie high/low // connections thru gates. class Sim : public StaState { public: - explicit Sim(StaState *sta); + Sim(StaState *sta); virtual ~Sim(); + virtual void copyState(const StaState *sta); void clear(); + void setMode(Mode *mode); // Set the observer for simulation value changes. void setObserver(SimObserver *observer); void ensureConstantsPropagated(); void constantsInvalid(); + + // Dertived by Sim from set_case_analysis or set_logic constant. + LogicValue simValue(const Pin *pin) const; + LogicValue simValue(const Vertex *vertex) const; + // Constant zero/one from simulation. + bool isConstant(const Pin *pin) const; + bool isConstant(const Vertex *vertex) const; + // Timing sense for the to_pin function after simplifying the + // function based constants on the instance pins. + TimingSense simTimingSense(const Edge *edge) const; + // Edge is disabled by constants in condition (when) function. + bool isDisabledCond(const Edge *edge) const; + LogicValue evalExpr(const FuncExpr *expr, - const Instance *inst); - LogicValue logicValue(const Pin *pin) const; - bool logicZeroOne(const Pin *pin) const; - bool logicZeroOne(const Vertex *vertex) const; + const Instance *inst); // Timing sense for the function between from_pin and to_pin // after simplifying the function based constants on the pins. - virtual TimingSense functionSense(const Instance *inst, - const Pin *from_pin, - const Pin *to_pin); + TimingSense functionSense(const Instance *inst, + const Pin *from_pin, + const Pin *to_pin); + // Propagate liberty constant functions and pins tied high/low through + // combinational logic and registers (ignores Sdc). + // Used by OpenROAD/Restructure.cpp void findLogicConstants(); + // Edge cond (liberty "when") function is disabled (evals to zero). + bool isDisabledCond(Edge *edge, + const Instance *inst, + const Pin *from_pin, + const Pin *to_pin); + // isDisabledCond but also return the cond expression that causes + // the disable. This can differ from the edge cond expression + // when the default timing edge is disabled by another edge between + // the same pins that is enabled. + void isDisabledCond(Edge *edge, + const Instance *inst, + const Pin *from_pin, + const Pin *to_pin, + // Return values. + bool &is_disabled, + FuncExpr *&disable_cond); + // Edge mode function is disabled (evals zero). + bool isDisabledMode(Edge *edge, + const Instance *inst); + void isDisabledMode(Edge *edge, + const Instance *inst, + // Return values. + bool &is_disabled, + FuncExpr *&disable_cond); + // Network edits. void deleteInstanceBefore(const Instance *inst); void makePinAfter(const Pin *pin); @@ -73,54 +116,63 @@ public: void connectPinAfter(const Pin *pin); void disconnectPinBefore(const Pin *pin); void pinSetFuncAfter(const Pin *pin); + const SimValueMap &simValues() const { return sim_value_map_; } protected: void ensureConstantFuncPins(); void recordConstPinFunc(const Pin *pin); - virtual void seedConstants(); + void seedConstants(); void seedInvalidConstants(); void propagateConstants(bool thru_sequentials); - void setConstraintConstPins(LogicValueMap &pin_value_map); + void setConstraintConstPins(const LogicValueMap &pin_value_map); void setConstFuncPins(); LogicValue pinConstFuncValue(const Pin *pin); void enqueueConstantPinInputs(); - virtual void setPinValue(const Pin *pin, - LogicValue value); + void setSimValue(const Pin *pin, + LogicValue value); + void setPinValue(const Pin *pin, + LogicValue value); + void setSimTimingSense(Edge *edge, + TimingSense sense); + void setIsDisabledCond(Edge *edge, + bool disabled); void enqueue(const Instance *inst); void evalInstance(const Instance *inst, bool thru_sequentials); LogicValue clockGateOutValue(const Instance *inst); TimingSense functionSense(const FuncExpr *expr, - const Pin *input_pin, - const Instance *inst); + const Pin *input_pin, + const Instance *inst); void functionSense(const FuncExpr *expr, - const Pin *input_pin, - const Instance *inst, - // return values - TimingSense &sense, - LogicValue &value) const; + const Pin *input_pin, + const Instance *inst, + // return values + TimingSense &sense, + LogicValue &value) const; void clearSimValues(); - virtual void clearInstSimValues(const Instance *inst); - void annotateGraphEdges(); - void annotateVertexEdges(const Instance *inst, - const Pin *pin, - Vertex *vertex, - bool annotate); - void annotateVertexEdges(const Instance *inst, - bool annotate); + + void findDisabledEdges(); + void findDisabledEdges(const Instance *inst); + void findDisabledEdges(const Instance *inst, + const Pin *pin, + Vertex *vertex); + void removePropagatedValue(const Pin *pin); void propagateFromInvalidDrvrsToLoads(); void propagateToInvalidLoads(); void propagateDrvrToLoad(const Pin *drvr_pin, - const Pin *load_pin); - void setSimValue(Vertex *vertex, - LogicValue value); + const Pin *load_pin); DdNode *funcBddSim(const FuncExpr *expr, const Instance *inst); + Mode *mode_; SimObserver *observer_; bool valid_; bool incremental_; + // Constants propagated by Sim.cc + SimValueMap sim_value_map_; + EdgeDisabledCondSet edge_disabled_cond_set_; + EdgeTimingSenseMap edge_timing_sense_map_; // Cache of pins that have constant functions (tie high and tie low // cell instances). PinSet const_func_pins_; @@ -132,63 +184,20 @@ protected: // Load pins that waiting for the driver constant to propagate. PinSet invalid_load_pins_; EvalQueue eval_queue_; - // Instances with constant pin values for annotateVertexEdges. - InstanceSet instances_with_const_pins_; InstanceSet instances_to_annotate_; Bdd bdd_; mutable std::mutex bdd_lock_; }; // Abstract base class for Sim value change observer. -class SimObserver +class SimObserver : public StaState { public: - SimObserver() {} + SimObserver(StaState *sta); virtual ~SimObserver() {} - virtual void valueChangeAfter(Vertex *vertex) = 0; - virtual void faninEdgesChangeAfter(Vertex *vertex) = 0; - virtual void fanoutEdgesChangeAfter(Vertex *vertex) = 0; + virtual void valueChangeAfter(const Pin *pin) = 0; + virtual void faninEdgesChangeAfter(const Pin *pin) = 0; + virtual void fanoutEdgesChangeAfter(const Pin *pin) = 0; }; -bool -logicValueZeroOne(LogicValue value); - -// Edge cond (liberty "when") function is disabled (evals to zero). -bool -isCondDisabled(Edge *edge, - const Instance *inst, - const Pin *from_pin, - const Pin *to_pin, - const Network *network, - Sim *sim); - -// isCondDisabled but also return the cond expression that causes -// the disable. This can differ from the edge cond expression -// when the default timing edge is disabled by another edge between -// the same pins that is enabled. -void -isCondDisabled(Edge *edge, - const Instance *inst, - const Pin *from_pin, - const Pin *to_pin, - const Network *network, - Sim *sim, - bool &is_disabled, - FuncExpr *&disable_cond); - - -// Edge mode function is disabled (evals to zero). -bool -isModeDisabled(Edge *edge, - const Instance *inst, - const Network *network, - Sim *sim); -void -isModeDisabled(Edge *edge, - const Instance *inst, - const Network *network, - Sim *sim, - bool &is_disabled, - FuncExpr *&disable_cond); - } // namespace diff --git a/search/Sta.cc b/search/Sta.cc index eb389646..b79a74c9 100644 --- a/search/Sta.cc +++ b/search/Sta.cc @@ -24,13 +24,17 @@ #include "Sta.hh" +#include + #include "Machine.hh" +#include "ContainerHelpers.hh" #include "DispatchQueue.hh" #include "ReportTcl.hh" #include "Debug.hh" #include "Stats.hh" #include "Fuzzy.hh" #include "Units.hh" +#include "PatternMatch.hh" #include "TimingArc.hh" #include "FuncExpr.hh" #include "EquivCells.hh" @@ -44,10 +48,10 @@ #include "Graph.hh" #include "GraphCmp.hh" #include "Sdc.hh" +#include "Mode.hh" #include "Variables.hh" #include "WriteSdc.hh" #include "ExceptionPath.hh" -#include "MakeConcreteParasitics.hh" #include "Parasitics.hh" #include "parasitics/SpefReader.hh" #include "parasitics/ReportParasiticAnnotation.hh" @@ -59,15 +63,13 @@ #include "Sim.hh" #include "ClkInfo.hh" #include "TagGroup.hh" -#include "PathAnalysisPt.hh" -#include "Corner.hh" #include "Search.hh" #include "Latches.hh" #include "PathGroup.hh" #include "CheckTiming.hh" -#include "CheckSlewLimits.hh" -#include "CheckFanoutLimits.hh" -#include "CheckCapacitanceLimits.hh" +#include "CheckSlews.hh" +#include "CheckFanouts.hh" +#include "CheckCapacitances.hh" #include "CheckMinPulseWidths.hh" #include "CheckMinPeriods.hh" #include "CheckMaxSkews.hh" @@ -81,6 +83,7 @@ #include "VisitPathEnds.hh" #include "PathExpanded.hh" #include "MakeTimingModel.hh" +#include "parasitics/ConcreteParasitics.hh" #include "spice/WritePathSpice.hh" namespace sta { @@ -89,14 +92,12 @@ using std::string; using std::min; using std::max; -static const ClockEdge *clk_edge_wildcard = reinterpret_cast(1); - static bool libertyPortCapsEqual(const LibertyPort *port1, const LibertyPort *port2); static bool hasDisabledArcs(Edge *edge, - Graph *graph); + const Mode *mode); static InstanceSet pinInstances(PinSet &pins, const Network *network); @@ -114,7 +115,7 @@ pinInstances(PinSet &pins, class StaDelayCalcObserver : public DelayCalcObserver { public: - explicit StaDelayCalcObserver(Search *search); + StaDelayCalcObserver(Search *search); virtual void delayChangedFrom(Vertex *vertex); virtual void delayChangedTo(Vertex *vertex); virtual void checkDelayChangedTo(Vertex *vertex); @@ -152,26 +153,14 @@ StaDelayCalcObserver::checkDelayChangedTo(Vertex *vertex) class StaSimObserver : public SimObserver { public: - StaSimObserver(GraphDelayCalc *graph_delay_calc, - Levelize *levelize, - Search *search); - virtual void valueChangeAfter(Vertex *vertex); - virtual void faninEdgesChangeAfter(Vertex *vertex); - virtual void fanoutEdgesChangeAfter(Vertex *vertex); - -private: - GraphDelayCalc *graph_delay_calc_; - Levelize *levelize_; - Search *search_; + StaSimObserver(StaState *sta); + void valueChangeAfter(const Pin *pin) override; + void faninEdgesChangeAfter(const Pin *pin) override; + void fanoutEdgesChangeAfter(const Pin *pin) override; }; -StaSimObserver::StaSimObserver(GraphDelayCalc *graph_delay_calc, - Levelize *levelize, - Search *search) : - SimObserver(), - graph_delay_calc_(graph_delay_calc), - levelize_(levelize), - search_(search) +StaSimObserver::StaSimObserver(StaState *sta) : + SimObserver(sta) { } @@ -180,26 +169,28 @@ StaSimObserver::StaSimObserver(GraphDelayCalc *graph_delay_calc, // because the search predicate does not search through constants. // This observer makes sure the delays and arrivals are invalidated. void -StaSimObserver::valueChangeAfter(Vertex *vertex) +StaSimObserver::valueChangeAfter(const Pin *pin) { - graph_delay_calc_->delayInvalid(vertex); + Vertex *vertex = graph_->pinDrvrVertex(pin); + if (vertex) { search_->arrivalInvalid(vertex); search_->requiredInvalid(vertex); search_->endpointInvalid(vertex); - levelize_->invalidFrom(vertex); + } } void -StaSimObserver::faninEdgesChangeAfter(Vertex *vertex) +StaSimObserver::faninEdgesChangeAfter(const Pin *pin) { - graph_delay_calc_->delayInvalid(vertex); + Vertex *vertex = graph_->pinDrvrVertex(pin); search_->arrivalInvalid(vertex); search_->endpointInvalid(vertex); } void -StaSimObserver::fanoutEdgesChangeAfter(Vertex *vertex) +StaSimObserver::fanoutEdgesChangeAfter(const Pin *pin) { + Vertex *vertex = graph_->pinDrvrVertex(pin); search_->requiredInvalid(vertex); search_->endpointInvalid(vertex); } @@ -272,13 +263,13 @@ Sta *Sta::sta_; Sta::Sta() : StaState(), + cmd_scene_(nullptr), current_instance_(nullptr), - cmd_corner_(nullptr), verilog_reader_(nullptr), check_timing_(nullptr), - check_slew_limits_(nullptr), - check_fanout_limits_(nullptr), - check_capacitance_limits_(nullptr), + check_slews_(nullptr), + check_fanouts_(nullptr), + check_capacitances_(nullptr), check_min_pulse_widths_(nullptr), check_min_periods_(nullptr), check_max_skews_(nullptr), @@ -287,9 +278,6 @@ Sta::Sta() : power_(nullptr), update_genclks_(false), equiv_cells_(nullptr), - graph_sdc_annotated_(false), - // Default to same parasitics for all corners. - parasitics_per_corner_(false), properties_(this) { } @@ -302,16 +290,12 @@ Sta::makeComponents() makeDebug(); makeUnits(); makeNetwork(); - makeSdc(); makeLevelize(); - makeParasitics(); - makeCorners(); + makeDefaultScene(); makeArcDelayCalc(); makeGraphDelayCalc(); - makeSim(); makeSearch(); makeLatches(); - makeClkNetwork(); makeSdcNetwork(); makeReportPath(); makePower(); @@ -322,15 +306,14 @@ Sta::makeComponents() updateComponentsState(); makeObservers(); - // This must follow updateComponentsState. - makeParasiticAnalysisPts(); } void Sta::makeObservers() { graph_delay_calc_->setObserver(new StaDelayCalcObserver(search_)); - sim_->setObserver(new StaSimObserver(graph_delay_calc_, levelize_, search_)); + for (Mode *mode : modes_) + mode->sim()->setObserver(new StaSimObserver(this)); levelize_->setObserver(new StaLevelizeObserver(search_, graph_delay_calc_)); } @@ -365,20 +348,18 @@ Sta::updateComponentsState() sdc_network_->copyState(this); if (graph_) graph_->copyState(this); - sdc_->copyState(this); - corners_->copyState(this); + for (Mode *mode : modes_) + mode->copyState(this); levelize_->copyState(this); - parasitics_->copyState(this); arc_delay_calc_->copyState(this); - sim_->copyState(this); search_->copyState(this); latches_->copyState(this); graph_delay_calc_->copyState(this); report_path_->copyState(this); if (check_timing_) check_timing_->copyState(this); - clk_network_->copyState(this); clk_skews_->copyState(this); + if (power_) power_->copyState(this); } @@ -407,24 +388,12 @@ Sta::makeNetwork() network_ = makeConcreteNetwork(); } -void -Sta::makeSdc() -{ - sdc_ = new Sdc(this); -} - void Sta::makeLevelize() { levelize_ = new Levelize(this); } -void -Sta::makeParasitics() -{ - parasitics_ = makeConcreteParasitics(this); -} - void Sta::makeArcDelayCalc() { @@ -437,12 +406,6 @@ Sta::makeGraphDelayCalc() graph_delay_calc_ = new GraphDelayCalc(this); } -void -Sta::makeSim() -{ - sim_ = new Sim(this); -} - void Sta::makeSearch() { @@ -468,21 +431,21 @@ Sta::makeCheckTiming() } void -Sta::makeCheckSlewLimits() +Sta::makeCheckSlews() { - check_slew_limits_ = new CheckSlewLimits(this); + check_slews_ = new CheckSlews(this); } void -Sta::makeCheckFanoutLimits() +Sta::makeCheckFanouts() { - check_fanout_limits_ = new CheckFanoutLimits(this); + check_fanouts_ = new CheckFanouts(this); } void -Sta::makeCheckCapacitanceLimits() +Sta::makeCheckCapacitances() { - check_capacitance_limits_ = new CheckCapacitanceLimits(this); + check_capacitances_ = new CheckCapacitances(this); } void @@ -509,12 +472,6 @@ Sta::makeReportPath() report_path_ = new ReportPath(this); } -void -Sta::makeClkNetwork() -{ - clk_network_ = new ClkNetwork(this); -} - void Sta::makePower() { @@ -546,9 +503,9 @@ Sta::~Sta() // to deleted before the network. delete verilog_reader_; // Delete "top down" to minimize chance of referencing deleted memory. - delete check_slew_limits_; - delete check_fanout_limits_; - delete check_capacitance_limits_; + delete check_slews_; + delete check_fanouts_; + delete check_capacitances_; delete check_min_pulse_widths_; delete check_min_periods_; delete check_max_skews_; @@ -558,39 +515,36 @@ Sta::~Sta() // Sdc references search filter, so delete search first. delete search_; delete latches_; - delete parasitics_; delete arc_delay_calc_; delete graph_delay_calc_; - delete sim_; delete levelize_; - delete sdc_; - delete corners_; delete graph_; delete sdc_network_; delete network_; delete debug_; delete units_; delete report_; - delete clk_network_; delete power_; delete equiv_cells_; delete dispatch_queue_; + deleteContents(parasitics_name_map_); + deleteContents(modes_); + deleteContents(scenes_); } void Sta::clear() { - clkPinsInvalid(); - // Constraints reference search filter, so clear search first. + // Sdc holds search filter, so clear search first. search_->clear(); - sdc_->clear(); - graph_sdc_annotated_ = false; - // corners are NOT cleared because they are used to index liberty files. + for (Mode *mode : modes_) { + mode->sdc()->clear(); + mode->clkNetwork()->clkPinsInvalid(); + } + // scenes are NOT cleared because they are used to index liberty files. levelize_->clear(); - if (parasitics_) - parasitics_->clear(); + deleteParasitics(); graph_delay_calc_->clear(); - sim_->clear(); power_->clear(); if (check_min_pulse_widths_) check_min_pulse_widths_->clear(); @@ -604,16 +558,68 @@ Sta::clear() updateComponentsState(); } +Sdc * +Sta::cmdSdc() const +{ + return cmdMode()->sdc(); +} + +void +Sta::setCmdMode(const string &mode_name) +{ + if (!mode_name.empty()) { + if (!mode_name_map_.contains(mode_name)) { + if (modes_.size() == 1 + && modes_[0]->name() == "default") { + // No need for default mode if one is defined. + delete modes_[0]; + mode_name_map_.clear(); + modes_.clear(); + } + Mode *mode = new Mode(mode_name, mode_name_map_.size(), this); + mode_name_map_[mode_name] = mode; + modes_.push_back(mode); + mode->sim()->setMode(mode); + mode->sim()->setObserver(new StaSimObserver(this)); + + if (scenes_.size() == 1 + && scenes_[0]->name() == "default") + scenes_[0]->setMode(mode); + updateComponentsState(); + } + } +} + +Mode * +Sta::findMode(const std::string &mode_name) const +{ + return findKey(mode_name_map_, mode_name); +} + +ModeSeq +Sta::findModes(const std::string &name) const +{ + ModeSeq matches; + PatternMatch pattern(name.c_str()); + for (Mode *mode : modes_) { + if (pattern.match(mode->name())) + matches.push_back(mode); + } + return matches; +} + void Sta::networkChanged() { // Everything else from clear(). search_->clear(); levelize_->clear(); - if (parasitics_) - parasitics_->clear(); + deleteContents(parasitics_name_map_); graph_delay_calc_->clear(); - sim_->clear(); + for (const Mode *mode : modes_) + mode->sim()->clear(); + for (Scene *scene : scenes_) + scene->setParasitics(nullptr, MinMaxAll::minMax()); if (check_min_pulse_widths_) check_min_pulse_widths_->clear(); if (check_min_periods_) @@ -621,7 +627,6 @@ Sta::networkChanged() clk_skews_->clear(); delete graph_; graph_ = nullptr; - graph_sdc_annotated_ = false; current_instance_ = nullptr; updateComponentsState(); } @@ -685,12 +690,12 @@ Sta::setCurrentInstance(Instance *inst) LibertyLibrary * Sta::readLiberty(const char *filename, - Corner *corner, + Scene *scene, const MinMaxAll *min_max, bool infer_latches) { Stats stats(debug_, report_); - LibertyLibrary *library = readLibertyFile(filename, corner, min_max, + LibertyLibrary *library = readLibertyFile(filename, scene, min_max, infer_latches); if (library // The default library is the first library read. @@ -706,7 +711,7 @@ Sta::readLiberty(const char *filename, LibertyLibrary * Sta::readLibertyFile(const char *filename, - Corner *corner, + Scene *scene, const MinMaxAll *min_max, bool infer_latches) { @@ -716,11 +721,11 @@ Sta::readLibertyFile(const char *filename, // Don't map liberty cells if they are redefined by reading another // library with the same cell names. if (min_max == MinMaxAll::all()) { - readLibertyAfter(liberty, corner, MinMax::min()); - readLibertyAfter(liberty, corner, MinMax::max()); + readLibertyAfter(liberty, scene, MinMax::min()); + readLibertyAfter(liberty, scene, MinMax::max()); } else - readLibertyAfter(liberty, corner, min_max->asMinMax()); + readLibertyAfter(liberty, scene, min_max->asMinMax()); network_->readLibertyAfter(liberty); } return liberty; @@ -735,11 +740,11 @@ Sta::readLibertyFile(const char *filename, void Sta::readLibertyAfter(LibertyLibrary *liberty, - Corner *corner, + Scene *scene, const MinMax *min_max) { - corner->addLiberty(liberty, min_max); - LibertyLibrary::makeCornerMap(liberty, corner->libertyIndex(min_max), + scene->addLiberty(liberty, min_max); + LibertyLibrary::makeSceneMap(liberty, scene->libertyIndex(min_max), network_, report_); } @@ -791,38 +796,40 @@ Sta::setDebugLevel(const char *what, //////////////////////////////////////////////////////////////// void -Sta::setAnalysisType(AnalysisType analysis_type) +Sta::setAnalysisType(AnalysisType analysis_type, + Sdc *sdc) { - if (analysis_type != sdc_->analysisType()) { - sdc_->setAnalysisType(analysis_type); + if (analysis_type != sdc->analysisType()) { + sdc->setAnalysisType(analysis_type); delaysInvalid(); search_->deletePathGroups(); - corners_->analysisTypeChanged(); if (graph_) - graph_->setDelayCount(corners_->dcalcAnalysisPtCount()); + graph_->setDelayCount(dcalcAnalysisPtCount()); } } OperatingConditions * -Sta::operatingConditions(const MinMax *min_max) const +Sta::operatingConditions(const MinMax *min_max, + const Sdc *sdc) const { - return sdc_->operatingConditions(min_max); + return sdc->operatingConditions(min_max); } void Sta::setOperatingConditions(OperatingConditions *op_cond, - const MinMaxAll *min_max) + const MinMaxAll *min_max, + Sdc *sdc) { - sdc_->setOperatingConditions(op_cond, min_max); - corners_->operatingConditionsChanged(); + sdc->setOperatingConditions(op_cond, min_max); delaysInvalid(); } const Pvt * Sta::pvt(Instance *inst, - const MinMax *min_max) + const MinMax *min_max, + Sdc *sdc) { - return sdc_->pvt(inst, min_max); + return sdc->pvt(inst, min_max); } void @@ -830,34 +837,38 @@ Sta::setPvt(Instance *inst, const MinMaxAll *min_max, float process, float voltage, - float temperature) + float temperature, + Sdc *sdc) { Pvt pvt(process, voltage, temperature); - setPvt(inst, min_max, pvt); + setPvt(inst, min_max, pvt, sdc); } void Sta::setPvt(const Instance *inst, const MinMaxAll *min_max, - const Pvt &pvt) + const Pvt &pvt, + Sdc *sdc) { - sdc_->setPvt(inst, min_max, pvt); + sdc->setPvt(inst, min_max, pvt); delaysInvalidFrom(inst); } void Sta::setVoltage(const MinMax *min_max, - float voltage) + float voltage, + Sdc *sdc) { - sdc_->setVoltage(min_max, voltage); + sdc->setVoltage(min_max, voltage); } void Sta::setVoltage(const Net *net, const MinMax *min_max, - float voltage) + float voltage, + Sdc *sdc) { - sdc_->setVoltage(net, min_max, voltage); + sdc->setVoltage(net, min_max, voltage); } void @@ -865,9 +876,10 @@ Sta::setTimingDerate(TimingDerateType type, PathClkOrData clk_data, const RiseFallBoth *rf, const EarlyLate *early_late, - float derate) + float derate, + Sdc *sdc) { - sdc_->setTimingDerate(type, clk_data, rf, early_late, derate); + sdc->setTimingDerate(type, clk_data, rf, early_late, derate); // Delay calculation results are still valid. // The search derates delays while finding arrival times. search_->arrivalsInvalid(); @@ -878,9 +890,10 @@ Sta::setTimingDerate(const Net *net, PathClkOrData clk_data, const RiseFallBoth *rf, const EarlyLate *early_late, - float derate) + float derate, + Sdc *sdc) { - sdc_->setTimingDerate(net, clk_data, rf, early_late, derate); + sdc->setTimingDerate(net, clk_data, rf, early_late, derate); // Delay calculation results are still valid. // The search derates delays while finding arrival times. search_->arrivalsInvalid(); @@ -892,9 +905,10 @@ Sta::setTimingDerate(const Instance *inst, PathClkOrData clk_data, const RiseFallBoth *rf, const EarlyLate *early_late, - float derate) + float derate, + Sdc *sdc) { - sdc_->setTimingDerate(inst, type, clk_data, rf, early_late, derate); + sdc->setTimingDerate(inst, type, clk_data, rf, early_late, derate); // Delay calculation results are still valid. // The search derates delays while finding arrival times. search_->arrivalsInvalid(); @@ -906,18 +920,19 @@ Sta::setTimingDerate(const LibertyCell *cell, PathClkOrData clk_data, const RiseFallBoth *rf, const EarlyLate *early_late, - float derate) + float derate, + Sdc *sdc) { - sdc_->setTimingDerate(cell, type, clk_data, rf, early_late, derate); + sdc->setTimingDerate(cell, type, clk_data, rf, early_late, derate); // Delay calculation results are still valid. // The search derates delays while finding arrival times. search_->arrivalsInvalid(); } void -Sta::unsetTimingDerate() +Sta::unsetTimingDerate(Sdc *sdc) { - sdc_->unsetTimingDerate(); + sdc->unsetTimingDerate(); // Delay calculation results are still valid. // The search derates delays while finding arrival times. search_->arrivalsInvalid(); @@ -927,9 +942,10 @@ void Sta::setInputSlew(const Port *port, const RiseFallBoth *rf, const MinMaxAll *min_max, - float slew) + float slew, + Sdc *sdc) { - sdc_->setInputSlew(port, rf, min_max, slew); + sdc->setInputSlew(port, rf, min_max, slew); delaysInvalidFrom(port); } @@ -941,9 +957,10 @@ Sta::setDriveCell(const LibertyLibrary *library, float *from_slews, const LibertyPort *to_port, const RiseFallBoth *rf, - const MinMaxAll *min_max) + const MinMaxAll *min_max, + Sdc *sdc) { - sdc_->setDriveCell(library, cell, port, from_port, from_slews, to_port, + sdc->setDriveCell(library, cell, port, from_port, from_slews, to_port, rf, min_max); delaysInvalidFrom(port); } @@ -952,87 +969,98 @@ void Sta::setDriveResistance(const Port *port, const RiseFallBoth *rf, const MinMaxAll *min_max, - float res) + float res, + Sdc *sdc) { - sdc_->setDriveResistance(port, rf, min_max, res); + sdc->setDriveResistance(port, rf, min_max, res); delaysInvalidFrom(port); } void Sta::setLatchBorrowLimit(const Pin *pin, - float limit) + float limit, + Sdc *sdc) { - sdc_->setLatchBorrowLimit(pin, limit); + sdc->setLatchBorrowLimit(pin, limit); search_->requiredInvalid(pin); } void Sta::setLatchBorrowLimit(const Instance *inst, - float limit) + float limit, + Sdc *sdc) { - sdc_->setLatchBorrowLimit(inst, limit); + sdc->setLatchBorrowLimit(inst, limit); search_->requiredInvalid(inst); } void Sta::setLatchBorrowLimit(const Clock *clk, - float limit) + float limit, + Sdc *sdc) { - sdc_->setLatchBorrowLimit(clk, limit); + sdc->setLatchBorrowLimit(clk, limit); search_->arrivalsInvalid(); } void Sta::setMinPulseWidth(const RiseFallBoth *rf, - float min_width) + float min_width, + Sdc *sdc) { - sdc_->setMinPulseWidth(rf, min_width); + sdc->setMinPulseWidth(rf, min_width); } void Sta::setMinPulseWidth(const Pin *pin, const RiseFallBoth *rf, - float min_width) + float min_width, + Sdc *sdc) { - sdc_->setMinPulseWidth(pin, rf, min_width); + sdc->setMinPulseWidth(pin, rf, min_width); } void Sta::setMinPulseWidth(const Instance *inst, const RiseFallBoth *rf, - float min_width) + float min_width, + Sdc *sdc) { - sdc_->setMinPulseWidth(inst, rf, min_width); + sdc->setMinPulseWidth(inst, rf, min_width); } void Sta::setMinPulseWidth(const Clock *clk, const RiseFallBoth *rf, - float min_width) + float min_width, + Sdc *sdc) { - sdc_->setMinPulseWidth(clk, rf, min_width); + sdc->setMinPulseWidth(clk, rf, min_width); } void -Sta::setWireloadMode(WireloadMode mode) +Sta::setWireloadMode(WireloadMode mode, + Sdc *sdc) { - sdc_->setWireloadMode(mode); + sdc->setWireloadMode(mode); delaysInvalid(); } void Sta::setWireload(Wireload *wireload, - const MinMaxAll *min_max) + const MinMaxAll *min_max, + Sdc *sdc) { - sdc_->setWireload(wireload, min_max); + sdc->setWireload(wireload, min_max); delaysInvalid(); } void Sta::setWireloadSelection(WireloadSelection *selection, - const MinMaxAll *min_max) + const MinMaxAll *min_max, + Sdc *sdc) { - sdc_->setWireloadSelection(selection, min_max); + sdc->setWireloadSelection(selection, min_max); delaysInvalid(); } @@ -1041,71 +1069,80 @@ Sta::setSlewLimit(Clock *clk, const RiseFallBoth *rf, const PathClkOrData clk_data, const MinMax *min_max, - float slew) + float slew, + Sdc *sdc) { - sdc_->setSlewLimit(clk, rf, clk_data, min_max, slew); + sdc->setSlewLimit(clk, rf, clk_data, min_max, slew); } void Sta::setSlewLimit(Port *port, const MinMax *min_max, - float slew) + float slew, + Sdc *sdc) { - sdc_->setSlewLimit(port, min_max, slew); + sdc->setSlewLimit(port, min_max, slew); } void Sta::setSlewLimit(Cell *cell, const MinMax *min_max, - float slew) + float slew, + Sdc *sdc) { - sdc_->setSlewLimit(cell, min_max, slew); + sdc->setSlewLimit(cell, min_max, slew); } void Sta::setCapacitanceLimit(Cell *cell, const MinMax *min_max, - float cap) + float cap, + Sdc *sdc) { - sdc_->setCapacitanceLimit(cell, min_max, cap); + sdc->setCapacitanceLimit(cell, min_max, cap); } void Sta::setCapacitanceLimit(Port *port, const MinMax *min_max, - float cap) + float cap, + Sdc *sdc) { - sdc_->setCapacitanceLimit(port, min_max, cap); + sdc->setCapacitanceLimit(port, min_max, cap); } void Sta::setCapacitanceLimit(Pin *pin, const MinMax *min_max, - float cap) + float cap, + Sdc *sdc) { - sdc_->setCapacitanceLimit(pin, min_max, cap); + sdc->setCapacitanceLimit(pin, min_max, cap); } void Sta::setFanoutLimit(Cell *cell, const MinMax *min_max, - float fanout) + float fanout, + Sdc *sdc) { - sdc_->setFanoutLimit(cell, min_max, fanout); + sdc->setFanoutLimit(cell, min_max, fanout); } void Sta::setFanoutLimit(Port *port, const MinMax *min_max, - float fanout) + float fanout, + Sdc *sdc) { - sdc_->setFanoutLimit(port, min_max, fanout); + sdc->setFanoutLimit(port, min_max, fanout); } void -Sta::setMaxArea(float area) +Sta::setMaxArea(float area, + Sdc *sdc) { - sdc_->setMaxArea(area); + sdc->setMaxArea(area); } void @@ -1114,12 +1151,14 @@ Sta::makeClock(const char *name, bool add_to_pins, float period, FloatSeq *waveform, - char *comment) + char *comment, + const Mode *mode) { - sdc_->makeClock(name, pins, add_to_pins, period, waveform, comment); + mode->sdc()->makeClock(name, pins, add_to_pins, period, waveform, comment); update_genclks_ = true; search_->arrivalsInvalid(); power_->activitiesInvalid(); + mode->clkNetwork()->clkPinsInvalid(); } void @@ -1135,9 +1174,10 @@ Sta::makeGeneratedClock(const char *name, bool combinational, IntSeq *edges, FloatSeq *edge_shifts, - char *comment) + char *comment, + const Mode *mode) { - sdc_->makeGeneratedClock(name, pins, add_to_pins, + mode->sdc()->makeGeneratedClock(name, pins, add_to_pins, src_pin, master_clk, divide_by, multiply_by, duty_cycle, invert, combinational, @@ -1145,68 +1185,77 @@ Sta::makeGeneratedClock(const char *name, update_genclks_ = true; search_->arrivalsInvalid(); power_->activitiesInvalid(); + mode->clkNetwork()->clkPinsInvalid(); } void -Sta::removeClock(Clock *clk) +Sta::removeClock(Clock *clk, + Sdc *sdc) { - sdc_->removeClock(clk); + sdc->removeClock(clk); search_->arrivalsInvalid(); power_->activitiesInvalid(); } bool -Sta::isClockSrc(const Pin *pin) const +Sta::isClockSrc(const Pin *pin, + const Sdc *sdc) const { - return sdc_->isClock(pin); + return sdc->isClock(pin); } void -Sta::setPropagatedClock(Clock *clk) +Sta::setPropagatedClock(Clock *clk, + const Mode *mode) { - sdc_->setPropagatedClock(clk); + mode->sdc()->setPropagatedClock(clk); delaysInvalid(); - clkPinsInvalid(); + mode->clkNetwork()->clkPinsInvalid(); } void -Sta::removePropagatedClock(Clock *clk) +Sta::removePropagatedClock(Clock *clk, + const Mode *mode) { - sdc_->removePropagatedClock(clk); + mode->sdc()->removePropagatedClock(clk); delaysInvalid(); - clkPinsInvalid(); + mode->clkNetwork()->clkPinsInvalid(); } void -Sta::setPropagatedClock(Pin *pin) +Sta::setPropagatedClock(Pin *pin, + const Mode *mode) { - sdc_->setPropagatedClock(pin); + mode->sdc()->setPropagatedClock(pin); delaysInvalid(); - clkPinsInvalid(); + mode->clkNetwork()->clkPinsInvalid(); } void -Sta::removePropagatedClock(Pin *pin) +Sta::removePropagatedClock(Pin *pin, + const Mode *mode) { - sdc_->removePropagatedClock(pin); + mode->sdc()->removePropagatedClock(pin); delaysInvalid(); - clkPinsInvalid(); + mode->clkNetwork()->clkPinsInvalid(); } void Sta::setClockSlew(Clock *clk, const RiseFallBoth *rf, const MinMaxAll *min_max, - float slew) + float slew, + Sdc *sdc) { - sdc_->setClockSlew(clk, rf, min_max, slew); + sdc->setClockSlew(clk, rf, min_max, slew); clockSlewChanged(clk); } void -Sta::removeClockSlew(Clock *clk) +Sta::removeClockSlew(Clock *clk, + Sdc *sdc) { - sdc_->removeClockSlew(clk); + sdc->removeClockSlew(clk); clockSlewChanged(clk); } @@ -1223,36 +1272,19 @@ Sta::setClockLatency(Clock *clk, Pin *pin, const RiseFallBoth *rf, const MinMaxAll *min_max, - float delay) + float delay, + Sdc *sdc) { - sdcChangedGraph(); - sdc_->setClockLatency(clk, pin, rf, min_max, delay); + sdc->setClockLatency(clk, pin, rf, min_max, delay); search_->arrivalsInvalid(); } -void -Sta::sdcChangedGraph() -{ - if (graph_sdc_annotated_) - sdc_->removeGraphAnnotations(); - graph_sdc_annotated_ = false; -} - -void -Sta::ensureGraphSdcAnnotated() -{ - if (!graph_sdc_annotated_) { - sdc_->annotateGraph(); - graph_sdc_annotated_ = true; - } -} - void Sta::removeClockLatency(const Clock *clk, - const Pin *pin) + const Pin *pin, + Sdc *sdc) { - sdcChangedGraph(); - sdc_->removeClockLatency(clk, pin); + sdc->removeClockLatency(clk, pin); search_->arrivalsInvalid(); } @@ -1262,17 +1294,19 @@ Sta::setClockInsertion(const Clock *clk, const RiseFallBoth *rf, const MinMaxAll *min_max, const EarlyLateAll *early_late, - float delay) + float delay, + Sdc *sdc) { - sdc_->setClockInsertion(clk, pin, rf, min_max, early_late, delay); + sdc->setClockInsertion(clk, pin, rf, min_max, early_late, delay); search_->arrivalsInvalid(); } void Sta::removeClockInsertion(const Clock *clk, - const Pin *pin) + const Pin *pin, + Sdc *sdc) { - sdc_->removeClockInsertion(clk, pin); + sdc->removeClockInsertion(clk, pin); search_->arrivalsInvalid(); } @@ -1296,17 +1330,19 @@ Sta::removeClockUncertainty(Clock *clk, void Sta::setClockUncertainty(Pin *pin, const SetupHoldAll *setup_hold, - float uncertainty) + float uncertainty, + Sdc *sdc) { - sdc_->setClockUncertainty(pin, setup_hold, uncertainty); + sdc->setClockUncertainty(pin, setup_hold, uncertainty); search_->arrivalsInvalid(); } void Sta::removeClockUncertainty(Pin *pin, - const SetupHoldAll *setup_hold) + const SetupHoldAll *setup_hold, + Sdc *sdc) { - sdc_->removeClockUncertainty(pin, setup_hold); + sdc->removeClockUncertainty(pin, setup_hold); search_->arrivalsInvalid(); } @@ -1316,9 +1352,10 @@ Sta::setClockUncertainty(Clock *from_clk, Clock *to_clk, const RiseFallBoth *to_rf, const SetupHoldAll *setup_hold, - float uncertainty) + float uncertainty, + Sdc *sdc) { - sdc_->setClockUncertainty(from_clk, from_rf, to_clk, to_rf, + sdc->setClockUncertainty(from_clk, from_rf, to_clk, to_rf, setup_hold, uncertainty); search_->arrivalsInvalid(); } @@ -1328,9 +1365,10 @@ Sta::removeClockUncertainty(Clock *from_clk, const RiseFallBoth *from_rf, Clock *to_clk, const RiseFallBoth *to_rf, - const SetupHoldAll *setup_hold) + const SetupHoldAll *setup_hold, + Sdc *sdc) { - sdc_->removeClockUncertainty(from_clk, from_rf, to_clk, to_rf, setup_hold); + sdc->removeClockUncertainty(from_clk, from_rf, to_clk, to_rf, setup_hold); search_->arrivalsInvalid(); } @@ -1340,9 +1378,10 @@ Sta::makeClockGroups(const char *name, bool physically_exclusive, bool asynchronous, bool allow_paths, - const char *comment) + const char *comment, + Sdc *sdc) { - ClockGroups *groups = sdc_->makeClockGroups(name, + ClockGroups *groups = sdc->makeClockGroups(name, logically_exclusive, physically_exclusive, asynchronous, @@ -1353,39 +1392,44 @@ Sta::makeClockGroups(const char *name, } void -Sta::removeClockGroupsLogicallyExclusive(const char *name) +Sta::removeClockGroupsLogicallyExclusive(const char *name, + Sdc *sdc) { - sdc_->removeClockGroupsLogicallyExclusive(name); + sdc->removeClockGroupsLogicallyExclusive(name); search_->requiredsInvalid(); } void -Sta::removeClockGroupsPhysicallyExclusive(const char *name) +Sta::removeClockGroupsPhysicallyExclusive(const char *name, + Sdc *sdc) { - sdc_->removeClockGroupsPhysicallyExclusive(name); + sdc->removeClockGroupsPhysicallyExclusive(name); search_->requiredsInvalid(); } void -Sta::removeClockGroupsAsynchronous(const char *name) +Sta::removeClockGroupsAsynchronous(const char *name, + Sdc *sdc) { - sdc_->removeClockGroupsAsynchronous(name); + sdc->removeClockGroupsAsynchronous(name); search_->requiredsInvalid(); } void Sta::makeClockGroup(ClockGroups *clk_groups, - ClockSet *clks) + ClockSet *clks, + Sdc *sdc) { - sdc_->makeClockGroup(clk_groups, clks); + sdc->makeClockGroup(clk_groups, clks); } void Sta::setClockSense(PinSet *pins, ClockSet *clks, - ClockSense sense) + ClockSense sense, + Sdc *sdc) { - sdc_->setClockSense(pins, clks, sense); + sdc->setClockSense(pins, clks, sense); search_->arrivalsInvalid(); } @@ -1394,9 +1438,10 @@ Sta::setClockSense(PinSet *pins, void Sta::setClockGatingCheck(const RiseFallBoth *rf, const SetupHold *setup_hold, - float margin) + float margin, + Sdc *sdc) { - sdc_->setClockGatingCheck(rf, setup_hold, margin); + sdc->setClockGatingCheck(rf, setup_hold, margin); search_->arrivalsInvalid(); } @@ -1404,9 +1449,10 @@ void Sta::setClockGatingCheck(Clock *clk, const RiseFallBoth *rf, const SetupHold *setup_hold, - float margin) + float margin, + Sdc *sdc) { - sdc_->setClockGatingCheck(clk, rf, setup_hold, margin); + sdc->setClockGatingCheck(clk, rf, setup_hold, margin); search_->arrivalsInvalid(); } @@ -1415,9 +1461,10 @@ Sta::setClockGatingCheck(Instance *inst, const RiseFallBoth *rf, const SetupHold *setup_hold, float margin, - LogicValue active_value) + LogicValue active_value, + Sdc *sdc) { - sdc_->setClockGatingCheck(inst, rf, setup_hold, margin,active_value); + sdc->setClockGatingCheck(inst, rf, setup_hold, margin,active_value); search_->arrivalsInvalid(); } @@ -1426,9 +1473,10 @@ Sta::setClockGatingCheck(Pin *pin, const RiseFallBoth *rf, const SetupHold *setup_hold, float margin, - LogicValue active_value) + LogicValue active_value, + Sdc *sdc) { - sdc_->setClockGatingCheck(pin, rf, setup_hold, margin,active_value); + sdc->setClockGatingCheck(pin, rf, setup_hold, margin,active_value); search_->arrivalsInvalid(); } @@ -1439,10 +1487,10 @@ Sta::setDataCheck(Pin *from, const RiseFallBoth *to_rf, Clock *clk, const SetupHoldAll *setup_hold, - float margin) + float margin, + Sdc *sdc) { - sdcChangedGraph(); - sdc_->setDataCheck(from, from_rf, to, to_rf, clk, setup_hold,margin); + sdc->setDataCheck(from, from_rf, to, to_rf, clk, setup_hold,margin); search_->requiredInvalid(to); } @@ -1452,33 +1500,30 @@ Sta::removeDataCheck(Pin *from, Pin *to, const RiseFallBoth *to_rf, Clock *clk, - const SetupHoldAll *setup_hold) + const SetupHoldAll *setup_hold, + Sdc *sdc) { - sdc_->removeDataCheck(from, from_rf, to, to_rf, clk, setup_hold); + sdc->removeDataCheck(from, from_rf, to, to_rf, clk, setup_hold); search_->requiredInvalid(to); } //////////////////////////////////////////////////////////////// void -Sta::disable(Pin *pin) +Sta::disable(Pin *pin, + Sdc *sdc) { - sdcChangedGraph(); - sdc_->disable(pin); - // Levelization respects disabled edges. - levelize_->invalid(); + sdc->disable(pin); graph_delay_calc_->delayInvalid(pin); search_->arrivalsInvalid(); } void -Sta::removeDisable(Pin *pin) +Sta::removeDisable(Pin *pin, + Sdc *sdc) { - sdcChangedGraph(); - sdc_->removeDisable(pin); + sdc->removeDisable(pin); disableAfter(); - // Levelization respects disabled edges. - levelize_->invalid(); graph_delay_calc_->delayInvalid(pin); search_->arrivalsInvalid(); } @@ -1486,11 +1531,10 @@ Sta::removeDisable(Pin *pin) void Sta::disable(Instance *inst, LibertyPort *from, - LibertyPort *to) + LibertyPort *to, + Sdc *sdc) { - sdcChangedGraph(); - sdc_->disable(inst, from, to); - + sdc->disable(inst, from, to); if (from) { Pin *from_pin = network_->findPin(inst, from); graph_delay_calc_->delayInvalid(from_pin); @@ -1507,19 +1551,16 @@ Sta::disable(Instance *inst, } delete pin_iter; } - // Levelization respects disabled edges. - levelize_->invalid(); search_->arrivalsInvalid(); } void Sta::removeDisable(Instance *inst, LibertyPort *from, - LibertyPort *to) + LibertyPort *to, + Sdc *sdc) { - sdcChangedGraph(); - sdc_->removeDisable(inst, from, to); - + sdc->removeDisable(inst, from, to); if (from) { Pin *from_pin = network_->findPin(inst, from); graph_delay_calc_->delayInvalid(from_pin); @@ -1536,100 +1577,105 @@ Sta::removeDisable(Instance *inst, } delete pin_iter; } - // Levelization respects disabled edges. - levelize_->invalid(); search_->arrivalsInvalid(); } void Sta::disable(LibertyCell *cell, LibertyPort *from, - LibertyPort *to) + LibertyPort *to, + Sdc *sdc) { - sdc_->disable(cell, from, to); + sdc->disable(cell, from, to); disableAfter(); } void Sta::removeDisable(LibertyCell *cell, LibertyPort *from, - LibertyPort *to) + LibertyPort *to, + Sdc *sdc) { - sdc_->removeDisable(cell, from, to); + sdc->removeDisable(cell, from, to); disableAfter(); } void -Sta::disable(LibertyPort *port) +Sta::disable(LibertyPort *port, + Sdc *sdc) { - sdcChangedGraph(); - sdc_->disable(port); + sdc->disable(port); disableAfter(); } void -Sta::removeDisable(LibertyPort *port) +Sta::removeDisable(LibertyPort *port, + Sdc *sdc) { - sdcChangedGraph(); - sdc_->removeDisable(port); + sdc->removeDisable(port); disableAfter(); } void -Sta::disable(Port *port) +Sta::disable(Port *port, + Sdc *sdc) { - sdc_->disable(port); + sdc->disable(port); disableAfter(); } void -Sta::removeDisable(Port *port) +Sta::removeDisable(Port *port, + Sdc *sdc) { - sdc_->removeDisable(port); + sdc->removeDisable(port); disableAfter(); } void -Sta::disable(Edge *edge) +Sta::disable(Edge *edge, + Sdc *sdc) { - sdc_->disable(edge); + sdc->disable(edge); disableAfter(); } void -Sta::removeDisable(Edge *edge) +Sta::removeDisable(Edge *edge, + Sdc *sdc) { - sdc_->removeDisable(edge); + sdc->removeDisable(edge); disableAfter(); } void -Sta::disable(TimingArcSet *arc_set) +Sta::disable(TimingArcSet *arc_set, + Sdc *sdc) { - sdc_->disable(arc_set); + sdc->disable(arc_set); disableAfter(); } void -Sta::removeDisable(TimingArcSet *arc_set) +Sta::removeDisable(TimingArcSet *arc_set, + Sdc *sdc) { - sdc_->removeDisable(arc_set); + sdc->removeDisable(arc_set); disableAfter(); } void Sta::disableAfter() { - // Levelization respects disabled edges. - levelize_->invalid(); delaysInvalid(); } //////////////////////////////////////////////////////////////// EdgeSeq -Sta::disabledEdges() +Sta::disabledEdges(const Mode *mode) { + const Sdc *sdc = mode->sdc(); ensureLevelized(); EdgeSeq disabled_edges; VertexIterator vertex_iter(graph_); @@ -1638,9 +1684,9 @@ Sta::disabledEdges() VertexOutEdgeIterator edge_iter(vertex, graph_); while (edge_iter.hasNext()) { Edge *edge = edge_iter.next(); - if (isDisabledConstant(edge) + if (isDisabledConstant(edge, mode) || isDisabledCondDefault(edge) - || isDisabledConstraint(edge) + || isDisabledConstraint(edge, sdc) || edge->isDisabledLoop() || isDisabledPresetClr(edge)) disabled_edges.push_back(edge); @@ -1651,52 +1697,51 @@ Sta::disabledEdges() EdgeSeq -Sta::disabledEdgesSorted() +Sta::disabledEdgesSorted(const Mode *mode) { - EdgeSeq disabled_edges = disabledEdges(); + EdgeSeq disabled_edges = disabledEdges(mode); sortEdges(&disabled_edges, network_, graph_); return disabled_edges; } bool -Sta::isDisabledConstraint(Edge *edge) +Sta::isDisabledConstraint(Edge *edge, + const Sdc *sdc) { Pin *from_pin = edge->from(graph_)->pin(); Pin *to_pin = edge->to(graph_)->pin(); - const Instance *inst = network_->instance(from_pin); - TimingArcSet *arc_set = edge->timingArcSet(); - return sdc_->isDisabled(from_pin) - || sdc_->isDisabled(to_pin) - || sdc_->isDisabled(inst, from_pin, to_pin, edge->role()) - || sdc_->isDisabled(edge) - || sdc_->isDisabled(arc_set); + return sdc->isDisabledConstraint(from_pin) + || sdc->isDisabledConstraint(to_pin) + || sdc->isDisabledConstraint(edge); } bool -Sta::isDisabledConstant(Edge *edge) +Sta::isDisabledConstant(Edge *edge, + const Mode *mode) { - sim_->ensureConstantsPropagated(); + Sim *sim = mode->sim(); + sim->ensureConstantsPropagated(); const TimingRole *role = edge->role(); Vertex *from_vertex = edge->from(graph_); Pin *from_pin = from_vertex->pin(); Vertex *to_vertex = edge->to(graph_); Pin *to_pin = to_vertex->pin(); const Instance *inst = network_->instance(from_pin); - return sim_->logicZeroOne(from_vertex) - || sim_->logicZeroOne(to_vertex) + return sim->isConstant(from_vertex) + || sim->isConstant(to_vertex) || (!role->isWire() - && (isCondDisabled(edge, inst, from_pin, to_pin, network_, sim_) - || isModeDisabled(edge, inst, network_, sim_) - || hasDisabledArcs(edge, graph_))); + && (sim->isDisabledCond(edge, inst, from_pin, to_pin) + || sim->isDisabledMode(edge, inst) + || hasDisabledArcs(edge, mode))); } static bool hasDisabledArcs(Edge *edge, - Graph *graph) + const Mode *mode) { TimingArcSet *arc_set = edge->timingArcSet(); for (TimingArc *arc : arc_set->arcs()) { - if (!searchThru(edge, arc, graph)) + if (!searchThru(edge, arc, mode)) return true; } return false; @@ -1709,39 +1754,40 @@ Sta::isDisabledLoop(Edge *edge) const } PinSet -Sta::disabledConstantPins(Edge *edge) +Sta::disabledConstantPins(Edge *edge, + const Mode *mode) { - sim_->ensureConstantsPropagated(); + Sim *sim = mode->sim(); + sim->ensureConstantsPropagated(); PinSet pins(network_); Vertex *from_vertex = edge->from(graph_); Pin *from_pin = from_vertex->pin(); Vertex *to_vertex = edge->to(graph_); const Pin *to_pin = to_vertex->pin(); - if (sim_->logicZeroOne(from_vertex)) + if (sim->isConstant(from_vertex)) pins.insert(from_pin); if (edge->role()->isWire()) { - if (sim_->logicZeroOne(to_vertex)) + if (sim->isConstant(to_vertex)) pins.insert(to_pin); } else { const Instance *inst = network_->instance(to_pin); bool is_disabled; FuncExpr *disable_cond; - isCondDisabled(edge, inst, from_pin, to_pin, network_, sim_, + sim->isDisabledCond(edge, inst, from_pin, to_pin, is_disabled, disable_cond); if (is_disabled) - exprConstantPins(disable_cond, inst, pins); - isModeDisabled(edge, inst, network_, sim_, - is_disabled, disable_cond); + exprConstantPins(disable_cond, inst, mode, pins); + sim->isDisabledMode(edge, inst, is_disabled, disable_cond); if (is_disabled) - exprConstantPins(disable_cond, inst, pins); - if (hasDisabledArcs(edge, graph_)) { + exprConstantPins(disable_cond, inst, mode, pins); + if (hasDisabledArcs(edge, mode)) { LibertyPort *to_port = network_->libertyPort(to_pin); if (to_port) { FuncExpr *func = to_port->function(); if (func - && sim_->functionSense(inst, from_pin, to_pin) != edge->sense()) - exprConstantPins(func, inst, pins); + && sim->functionSense(inst, from_pin, to_pin) != edge->sense()) + exprConstantPins(func, inst, mode, pins); } } } @@ -1749,25 +1795,27 @@ Sta::disabledConstantPins(Edge *edge) } TimingSense -Sta::simTimingSense(Edge *edge) +Sta::simTimingSense(Edge *edge, + const Mode *mode) { Pin *from_pin = edge->from(graph_)->pin(); Pin *to_pin = edge->to(graph_)->pin(); Instance *inst = network_->instance(from_pin); - return sim_->functionSense(inst, from_pin, to_pin); + return mode->sim()->functionSense(inst, from_pin, to_pin); } void Sta::exprConstantPins(FuncExpr *expr, const Instance *inst, + const Mode *mode, + // Return value. PinSet &pins) { - FuncExprPortIterator port_iter(expr); - while (port_iter.hasNext()) { - LibertyPort *port = port_iter.next(); + LibertyPortSet ports = expr->ports(); + for (LibertyPort *port : ports) { Pin *pin = network_->findPin(inst, port); if (pin) { - LogicValue value = sim_->logicValue(pin); + LogicValue value = mode->sim()->simValue(pin); if (value != LogicValue::unknown) pins.insert(pin); } @@ -1781,13 +1829,6 @@ Sta::isDisabledBidirectInstPath(Edge *edge) const && edge->isBidirectInstPath(); } -bool -Sta::isDisabledBidirectNetPath(Edge *edge) const -{ - return !variables_->bidirectNetPathsEnabled() - && edge->isBidirectNetPath(); -} - bool Sta::isDisabledPresetClr(Edge *edge) const { @@ -1796,42 +1837,44 @@ Sta::isDisabledPresetClr(Edge *edge) const } void -Sta::disableClockGatingCheck(Instance *inst) +Sta::disableClockGatingCheck(Instance *inst, + Sdc *sdc) { - sdc_->disableClockGatingCheck(inst); + sdc->disableClockGatingCheck(inst); search_->endpointsInvalid(); } void -Sta::disableClockGatingCheck(Pin *pin) +Sta::disableClockGatingCheck(Pin *pin, + Sdc *sdc) { - sdc_->disableClockGatingCheck(pin); + sdc->disableClockGatingCheck(pin); search_->endpointsInvalid(); } void -Sta::removeDisableClockGatingCheck(Instance *inst) +Sta::removeDisableClockGatingCheck(Instance *inst, + Sdc *sdc) { - sdc_->removeDisableClockGatingCheck(inst); + sdc->removeDisableClockGatingCheck(inst); search_->endpointsInvalid(); } void -Sta::removeDisableClockGatingCheck(Pin *pin) +Sta::removeDisableClockGatingCheck(Pin *pin, + Sdc *sdc) { - sdc_->removeDisableClockGatingCheck(pin); + sdc->removeDisableClockGatingCheck(pin); search_->endpointsInvalid(); } void Sta::setLogicValue(Pin *pin, - LogicValue value) + LogicValue value, + Mode *mode) { - sdc_->setLogicValue(pin, value); - // Levelization respects constant disabled edges. - levelize_->invalid(); - power_->activitiesInvalid(); - sim_->constantsInvalid(); + mode->sdc()->setLogicValue(pin, value); + mode->sim()->constantsInvalid(); // Constants disable edges which isolate downstream vertices of the // graph from the delay calculator's BFS search. This means that // simply invaldating the delays downstream from the constant pin @@ -1839,32 +1882,32 @@ Sta::setLogicValue(Pin *pin, // calculator searched thru disabled edges but ignored their // results. delaysInvalid(); + power_->activitiesInvalid(); } void Sta::setCaseAnalysis(Pin *pin, - LogicValue value) + LogicValue value, + Mode *mode) { - sdc_->setCaseAnalysis(pin, value); - power_->activitiesInvalid(); // Levelization respects constant disabled edges. - levelize_->invalid(); - sim_->constantsInvalid(); + mode->sdc()->setCaseAnalysis(pin, value); + mode->sim()->constantsInvalid(); // Constants disable edges which isolate downstream vertices of the // graph from the delay calculator's BFS search. This means that // simply invaldating the delays downstream from the constant pin // fails. This could be handled incrementally by invalidating delays // on the output of gates one level downstream. delaysInvalid(); + power_->activitiesInvalid(); } void -Sta::removeCaseAnalysis(Pin *pin) +Sta::removeCaseAnalysis(Pin *pin, + Mode *mode) { - sdc_->removeCaseAnalysis(pin); - // Levelization respects constant disabled edges. - levelize_->invalid(); - sim_->constantsInvalid(); + mode->sdc()->removeCaseAnalysis(pin); + mode->sim()->constantsInvalid(); // Constants disable edges which isolate downstream vertices of the // graph from the delay calculator's BFS search. This means that // simply invaldating the delays downstream from the constant pin @@ -1883,9 +1926,10 @@ Sta::setInputDelay(const Pin *pin, bool network_latency_included, const MinMaxAll *min_max, bool add, - float delay) + float delay, + Sdc *sdc) { - sdc_->setInputDelay(pin, rf, clk, clk_rf, ref_pin, + sdc->setInputDelay(pin, rf, clk, clk_rf, ref_pin, source_latency_included, network_latency_included, min_max, add, delay); @@ -1897,9 +1941,10 @@ Sta::removeInputDelay(const Pin *pin, const RiseFallBoth *rf, const Clock *clk, const RiseFall *clk_rf, - const MinMaxAll *min_max) + const MinMaxAll *min_max, + Sdc *sdc) { - sdc_->removeInputDelay(pin, rf, clk, clk_rf, min_max); + sdc->removeInputDelay(pin, rf, clk, clk_rf, min_max); search_->arrivalInvalid(pin); } @@ -1913,12 +1958,12 @@ Sta::setOutputDelay(const Pin *pin, bool network_latency_included, const MinMaxAll *min_max, bool add, - float delay) + float delay, + Sdc *sdc) { - sdc_->setOutputDelay(pin, rf, clk, clk_rf, ref_pin, + sdc->setOutputDelay(pin, rf, clk, clk_rf, ref_pin, source_latency_included,network_latency_included, min_max, add, delay); - sdcChangedGraph(); search_->requiredInvalid(pin); } @@ -1927,10 +1972,10 @@ Sta::removeOutputDelay(const Pin *pin, const RiseFallBoth *rf, const Clock *clk, const RiseFall *clk_rf, - const MinMaxAll *min_max) + const MinMaxAll *min_max, + Sdc *sdc) { - sdc_->removeOutputDelay(pin, rf, clk, clk_rf, min_max); - sdcChangedGraph(); + sdc->removeOutputDelay(pin, rf, clk, clk_rf, min_max); search_->arrivalInvalid(pin); } @@ -1939,9 +1984,10 @@ Sta::makeFalsePath(ExceptionFrom *from, ExceptionThruSeq *thrus, ExceptionTo *to, const MinMaxAll *min_max, - const char *comment) + const char *comment, + Sdc *sdc) { - sdc_->makeFalsePath(from, thrus, to, min_max, comment); + sdc->makeFalsePath(from, thrus, to, min_max, comment); search_->arrivalsInvalid(); } @@ -1952,9 +1998,10 @@ Sta::makeMulticyclePath(ExceptionFrom *from, const MinMaxAll *min_max, bool use_end_clk, int path_multiplier, - const char *comment) + const char *comment, + Sdc *sdc) { - sdc_->makeMulticyclePath(from, thrus, to, min_max, + sdc->makeMulticyclePath(from, thrus, to, min_max, use_end_clk, path_multiplier, comment); search_->arrivalsInvalid(); @@ -1968,9 +2015,10 @@ Sta::makePathDelay(ExceptionFrom *from, bool ignore_clk_latency, bool break_path, float delay, - const char *comment) + const char *comment, + Sdc *sdc) { - sdc_->makePathDelay(from, thrus, to, min_max, + sdc->makePathDelay(from, thrus, to, min_max, ignore_clk_latency, break_path, delay, comment); search_->endpointsInvalid(); @@ -1981,9 +2029,10 @@ void Sta::resetPath(ExceptionFrom *from, ExceptionThruSeq *thrus, ExceptionTo *to, - const MinMaxAll *min_max) + const MinMaxAll *min_max, + Sdc *sdc) { - sdc_->resetPath(from, thrus, to, min_max); + sdc->resetPath(from, thrus, to, min_max); search_->arrivalsInvalid(); } @@ -1993,23 +2042,26 @@ Sta::makeGroupPath(const char *name, ExceptionFrom *from, ExceptionThruSeq *thrus, ExceptionTo *to, - const char *comment) + const char *comment, + Sdc *sdc) { - sdc_->makeGroupPath(name, is_default, from, thrus, to, comment); + sdc->makeGroupPath(name, is_default, from, thrus, to, comment); search_->arrivalsInvalid(); } bool -Sta::isGroupPathName(const char *group_name) +Sta::isGroupPathName(const char *group_name, + const Sdc *sdc) { - return isPathGroupName(group_name); + return isPathGroupName(group_name, sdc); } bool -Sta::isPathGroupName(const char *group_name) const +Sta::isPathGroupName(const char *group_name, + const Sdc *sdc) const { - return sdc_->findClock(group_name) - || sdc_->isGroupPathName(group_name) + return sdc->findClock(group_name) + || sdc->isGroupPathName(group_name) || stringEq(group_name, PathGroups::asyncPathGroupName()) || stringEq(group_name, PathGroups::pathDelayGroupName()) || stringEq(group_name, PathGroups::gatedClkGroupName()) @@ -2017,13 +2069,13 @@ Sta::isPathGroupName(const char *group_name) const } StdStringSeq -Sta::pathGroupNames() const +Sta::pathGroupNames(const Sdc *sdc) const { StdStringSeq names; - for (const Clock *clk : *sdc_->clocks()) + for (const Clock *clk : sdc->clocks()) names.push_back(clk->name()); - for (auto const &[name, group] : sdc_->groupPaths()) + for (auto const &[name, group] : sdc->groupPaths()) names.push_back(name); names.push_back(PathGroups::asyncPathGroupName()); @@ -2037,22 +2089,23 @@ ExceptionFrom * Sta::makeExceptionFrom(PinSet *from_pins, ClockSet *from_clks, InstanceSet *from_insts, - const RiseFallBoth *from_rf) + const RiseFallBoth *from_rf, + const Sdc *sdc) { - return sdc_->makeExceptionFrom(from_pins, from_clks, from_insts, - from_rf); + return sdc->makeExceptionFrom(from_pins, from_clks, from_insts, from_rf); } void Sta::checkExceptionFromPins(ExceptionFrom *from, const char *file, - int line) const + int line, + const Sdc *sdc) const { if (from) { - PinSet::ConstIterator pin_iter(from->pins()); - while (pin_iter.hasNext()) { - const Pin *pin = pin_iter.next(); - if (!sdc_->isExceptionStartpoint(pin)) { + PinSet *pins = from->pins(); + if (pins) { + for (const Pin *pin : *pins) { + if (!sdc->isExceptionStartpoint(pin)) { if (line) report_->fileWarn(1554, file, line, "'%s' is not a valid start point.", cmd_network_->pathName(pin)); @@ -2062,6 +2115,7 @@ Sta::checkExceptionFromPins(ExceptionFrom *from, } } } + } } void @@ -2074,9 +2128,10 @@ ExceptionThru * Sta::makeExceptionThru(PinSet *pins, NetSet *nets, InstanceSet *insts, - const RiseFallBoth *rf) + const RiseFallBoth *rf, + const Sdc *sdc) { - return sdc_->makeExceptionThru(pins, nets, insts, rf); + return sdc->makeExceptionThru(pins, nets, insts, rf); } void @@ -2090,9 +2145,10 @@ Sta::makeExceptionTo(PinSet *to_pins, ClockSet *to_clks, InstanceSet *to_insts, const RiseFallBoth *rf, - const RiseFallBoth *end_rf) + const RiseFallBoth *end_rf, + const Sdc *sdc) { - return sdc_->makeExceptionTo(to_pins, to_clks, to_insts, rf, end_rf); + return sdc->makeExceptionTo(to_pins, to_clks, to_insts, rf, end_rf); } void @@ -2104,13 +2160,14 @@ Sta::deleteExceptionTo(ExceptionTo *to) void Sta::checkExceptionToPins(ExceptionTo *to, const char *file, - int line) const + int line, + const Sdc *sdc) const { if (to) { - PinSet::Iterator pin_iter(to->pins()); - while (pin_iter.hasNext()) { - const Pin *pin = pin_iter.next(); - if (!sdc_->isExceptionEndpoint(pin)) { + PinSet *pins = to->pins(); + if (pins) { + for (const Pin *pin : *pins) { + if (!sdc->isExceptionEndpoint(pin)) { if (line) report_->fileWarn(1551, file, line, "'%s' is not a valid endpoint.", cmd_network_->pathName(pin)); @@ -2120,31 +2177,12 @@ Sta::checkExceptionToPins(ExceptionTo *to, } } } + } } void -Sta::removeConstraints() -{ - levelize_->invalid(); - graph_delay_calc_->clear(); - search_->clear(); - sim_->constantsInvalid(); - if (graph_) - sdc_->removeGraphAnnotations(); - sdc_->clear(); - clk_network_->clear(); -} - -void -Sta::constraintsChanged() -{ - levelize_->invalid(); - delaysInvalid(); - sim_->constantsInvalid(); -} - -void -Sta::writeSdc(const char *filename, +Sta::writeSdc(const Sdc *sdc, + const char *filename, bool leaf, bool native, int digits, @@ -2152,14 +2190,15 @@ Sta::writeSdc(const char *filename, bool no_timestamp) { ensureLibLinked(); - sta::writeSdc(network_->topInstance(), filename, "write_sdc", - leaf, native, digits, gzip, no_timestamp, sdc_); + sta::writeSdc(sdc, network_->topInstance(), filename, "write_sdc", + leaf, native, digits, gzip, no_timestamp); } //////////////////////////////////////////////////////////////// CheckErrorSeq & -Sta::checkTiming(bool no_input_delay, +Sta::checkTiming(const Mode *mode, + bool no_input_delay, bool no_output_delay, bool reg_multiple_clks, bool reg_no_clks, @@ -2167,15 +2206,20 @@ Sta::checkTiming(bool no_input_delay, bool loops, bool generated_clks) { + if (unconstrained_endpoints) { + // Only arrivals to find unconstrained_endpoints. searchPreamble(); - if (unconstrained_endpoints) - // Only need non-clock arrivals for unconstrained_endpoints. search_->findAllArrivals(); - else - search_->findClkArrivals(); + } + else { + ensureGraph(); + ensureLevelized(); + mode->sim()->ensureConstantsPropagated(); + mode->clkNetwork()->ensureClkNetwork(); + } if (check_timing_ == nullptr) makeCheckTiming(); - return check_timing_->check(no_input_delay, no_output_delay, + return check_timing_->check(mode, no_input_delay, no_output_delay, reg_multiple_clks, reg_no_clks, unconstrained_endpoints, loops, generated_clks); @@ -2192,9 +2236,7 @@ Sta::crprEnabled() const void Sta::setCrprEnabled(bool enabled) { - // Pessimism is only relevant for on_chip_variation analysis. - if (sdc_->analysisType() == AnalysisType::ocv - && enabled != variables_->crprEnabled()) + if (enabled != variables_->crprEnabled()) search_->arrivalsInvalid(); variables_->setCrprEnabled(enabled); } @@ -2209,8 +2251,7 @@ void Sta::setCrprMode(CrprMode mode) { // Pessimism is only relevant for on_chip_variation analysis. - if (sdc_->analysisType() == AnalysisType::ocv - && variables_->crprEnabled() + if (variables_->crprEnabled() && variables_->crprMode() != mode) search_->arrivalsInvalid(); variables_->setCrprMode(mode); @@ -2301,21 +2342,6 @@ Sta::setBidirectInstPathsEnabled(bool enabled) } } -bool -Sta::bidirectNetPathsEnabled() const -{ - return variables_->bidirectNetPathsEnabled(); -} - -void -Sta::setBidirectNetPathsEnabled(bool enabled) -{ - if (variables_->bidirectNetPathsEnabled() != enabled) { - delaysInvalid(); - variables_->setBidirectNetPathsEnabled(enabled); - } -} - bool Sta::recoveryRemovalChecksEnabled() const { @@ -2356,11 +2382,12 @@ void Sta::setDynamicLoopBreaking(bool enable) { if (variables_->dynamicLoopBreaking() != enable) { - if (levelize_->levelized()) { + for (Mode *mode : modes_) { + Sdc *sdc = mode->sdc(); if (enable) - sdc_->makeLoopExceptions(); + sdc->makeLoopExceptions(); else - sdc_->deleteLoopExceptions(); + sdc->deleteLoopExceptions(); } search_->arrivalsInvalid(); variables_->setDynamicLoopBreaking(enable); @@ -2411,54 +2438,222 @@ Sta::setClkThruTristateEnabled(bool enable) //////////////////////////////////////////////////////////////// -Corner * -Sta::findCorner(const char *corner_name) -{ - return corners_->findCorner(corner_name); -} - -bool -Sta::multiCorner() -{ - return corners_->multiCorner(); -} - -// Init one corner named "default". +// Init one scene named "default". void -Sta::makeCorners() +Sta::makeDefaultScene() { - corners_ = new Corners(this); - StringSet corner_names; - corner_names.insert("default"); - corners_->makeCorners(&corner_names); - cmd_corner_ = corners_->findCorner(0); - sdc_->makeCornersAfter(corners_); + const char *name = "default"; + StringSeq scene_names; + scene_names.push_back(name); + Parasitics *parasitics = makeConcreteParasitics(name, ""); + + Mode *mode = new Mode(name, 0, this); + modes_.push_back(mode); + mode_name_map_[name] = mode; + mode->sim()->setMode(mode); + mode->sim()->setObserver(new StaSimObserver(this)); + + deleteScenes(); + makeScene(name, mode, parasitics); + + cmd_scene_ = scenes_[0]; } +// define_corners (before read_liberty). void -Sta::makeCorners(StringSet *corner_names) +Sta::makeScenes(StringSeq *scene_names) { - if (corner_names->size() > corner_count_max) - report_->error(1553, "maximum corner count exceeded"); - sdc_->makeCornersBefore(); - parasitics_->deleteParasitics(); - corners_->makeCorners(corner_names); - makeParasiticAnalysisPts(); - cmd_corner_ = corners_->findCorner(0); + if (scene_names->size() > scene_count_max) + report_->error(1553, "maximum scene count exceeded"); + Parasitics *parasitics = findParasitics("default"); + Mode *mode = modes_[0]; + mode->sdc()->makeSceneBefore(); + mode->clear(); + + deleteScenes(); + for (const char *name : *scene_names) + makeScene(name, mode, parasitics); + + cmd_scene_ = scenes_[0]; updateComponentsState(); - sdc_->makeCornersAfter(corners_); -} - -Corner * -Sta::cmdCorner() const -{ - return cmd_corner_; + if (graph_) + graph_->makeSceneAfter(); } void -Sta::setCmdCorner(Corner *corner) +Sta::makeScene(const std::string &name, + const std::string &mode_name, + const StdStringSeq &liberty_min_files, + const StdStringSeq &liberty_max_files, + const std::string &spef_min_file, + const std::string &spef_max_file) { - cmd_corner_ = corner; + Mode *mode = findMode(mode_name); + Parasitics *parasitics_default = findParasitics("default"); + Parasitics *parasitics_min = parasitics_default; + Parasitics *parasitics_max = parasitics_default; + if (!spef_min_file.empty() && !spef_max_file.empty()) { + parasitics_min = findParasitics(spef_min_file); + parasitics_max = findParasitics(spef_max_file); + if (parasitics_min == nullptr) + report_->error(1558, "Spef file %s not found.", spef_min_file.c_str()); + if (parasitics_max == nullptr + && spef_max_file != spef_min_file) + report_->error(1559, "Spef file %s not found.", spef_max_file.c_str()); + } + + mode->sdc()->makeSceneBefore(); + Scene *scene = makeScene(name, mode, parasitics_min, parasitics_max); + updateComponentsState(); + if (graph_) + graph_->makeSceneAfter(); + updateSceneLiberty(scene, liberty_min_files, MinMax::min()); + updateSceneLiberty(scene, liberty_max_files, MinMax::max()); + cmd_scene_ = scene; +} + +Scene * +Sta::makeScene(const std::string &name, + Mode *mode, + Parasitics *parasitics) +{ + Scene *scene = new Scene(name, scenes_.size(), mode, parasitics); + scene_name_map_[name] = scene; + scenes_.push_back(scene); + mode->addScene(scene); + return scene; +} + +void +Sta::deleteScenes() +{ + for (Scene *scene : scenes_) { + scene->mode()->removeScene(scene); + delete scene; + } + scenes_.clear(); + scene_name_map_.clear(); +} + +Scene * +Sta::makeScene(const std::string &name, + Mode *mode, + Parasitics *parasitics_min, + Parasitics *parasitics_max) +{ + if (scenes_.size() == 1 + && findScene("default")) + deleteScenes(); + + Scene *scene = new Scene(name, scenes_.size(), mode, + parasitics_min, parasitics_max); + scene_name_map_[name] = scene; + scenes_.push_back(scene); + mode->addScene(scene); + return scene; +} + +Scene * +Sta::findScene(const std::string &name) const +{ + return findKey(scene_name_map_, name); +} + +SceneSeq +Sta::findScenes(const std::string &name) const +{ + SceneSeq matches; + PatternMatch pattern(name.c_str()); + for (Scene *scene : scenes_) { + if (pattern.match(scene->name())) + matches.push_back(scene); + } + return matches; +} + +SceneSeq +Sta::findScenes(const std::string &name, + ModeSeq &modes) const +{ + SceneSeq matches; + PatternMatch pattern(name.c_str()); + for (Mode *mode : modes) { + for (Scene *scene : mode->scenes()) { + if (pattern.match(scene->name())) + matches.push_back(scene); + } + } + return matches; +} + +void +Sta::updateSceneLiberty(Scene *scene, + const StdStringSeq &liberty_files, + const MinMax *min_max) +{ + for (const std::string &lib_file : liberty_files) { + LibertyLibrary *lib = findLibertyFileBasename(lib_file); + if (lib) + LibertyLibrary::makeSceneMap(lib, scene->libertyIndex(min_max), + network_, report_); + else + report_->warn(1555, "liberty filename %s not found.", lib_file.c_str()); + } +} + +LibertyLibrary * +Sta::findLibertyFileBasename(const std::string &filename) const +{ + LibertyLibraryIterator *lib_iter = network_->libertyLibraryIterator(); + while (lib_iter->hasNext()) { + LibertyLibrary *lib = lib_iter->next(); + auto lib_file = std::filesystem::path(lib->filename()).filename().stem(); + auto stem = lib_file.stem(); + if (stem.string() == filename) { + delete lib_iter; + return lib; + } + } + delete lib_iter; + return nullptr; +} + +void +Sta::updateLibertyScenes() +{ + for (Scene *scene : scenes_) { + LibertyLibraryIterator *iter = network_->libertyLibraryIterator(); + while (iter->hasNext()) { + LibertyLibrary *lib = iter->next(); + for (const MinMax *min_max : MinMax::range()) { + LibertyLibrary::makeSceneMap(lib, scene->libertyIndex(min_max), + network_, report_); + } + } + } +} + +Scene * +Sta::cmdScene() const +{ + return cmd_scene_; +} + +void +Sta::setCmdScene(Scene *scene) +{ + cmd_scene_ = scene; +} + +SceneSeq +Sta::makeSceneSeq(Scene *scene) const +{ + SceneSeq scenes; + if (scene) + scenes.push_back(scene); + else + scenes = scenes_; + return scenes; } //////////////////////////////////////////////////////////////// @@ -2471,7 +2666,7 @@ Sta::findPathEnds(ExceptionFrom *from, ExceptionThruSeq *thrus, ExceptionTo *to, bool unconstrained, - const Corner *corner, + const SceneSeq &scenes, const MinMaxAll *min_max, int group_path_count, int endpoint_path_count, @@ -2480,7 +2675,7 @@ Sta::findPathEnds(ExceptionFrom *from, float slack_min, float slack_max, bool sort_by_slack, - PathGroupNameSet *group_names, + StdStringSeq &group_names, bool setup, bool hold, bool recovery, @@ -2491,10 +2686,9 @@ Sta::findPathEnds(ExceptionFrom *from, searchPreamble(); clk_skews_->clear(); return search_->findPathEnds(from, thrus, to, unconstrained, - corner, min_max, group_path_count, + scenes, min_max, group_path_count, endpoint_path_count, - unique_pins, unique_edges, - slack_min, slack_max, + unique_pins, unique_edges, slack_min, slack_max, sort_by_slack, group_names, setup, hold, recovery, removal, @@ -2505,18 +2699,21 @@ Sta::findPathEnds(ExceptionFrom *from, // Overall flow: // make graph -// propagate constants // levelize // delay calculation // update generated clocks +// propagate constants // find arrivals void Sta::searchPreamble() { findDelays(); + for (Mode *mode : modes_) { + mode->sim()->ensureConstantsPropagated(); + mode->sdc()->searchPreamble(); + } updateGeneratedClks(); - sdc_->searchPreamble(); // Delete results from last findPathEnds because they point to filtered arrivals. search_->deletePathGroups(); search_->deleteFilteredArrivals(); @@ -2623,13 +2820,13 @@ Sta::updateTiming(bool full) void Sta::reportClkSkew(ConstClockSeq &clks, - const Corner *corner, + const SceneSeq &scenes, const SetupHold *setup_hold, bool include_internal_latency, int digits) { clkSkewPreamble(); - clk_skews_->reportClkSkew(clks, corner, setup_hold, + clk_skews_->reportClkSkew(clks, scenes, setup_hold, include_internal_latency, digits); } @@ -2639,7 +2836,7 @@ Sta::findWorstClkSkew(const SetupHold *setup_hold, { clkSkewPreamble(); - return clk_skews_->findWorstClkSkew(nullptr, setup_hold, + return clk_skews_->findWorstClkSkew(scenes_, setup_hold, include_internal_latency); } @@ -2659,22 +2856,23 @@ Sta::makeClkSkews() void Sta::reportClkLatency(ConstClockSeq &clks, - const Corner *corner, + const SceneSeq &scenes, bool include_internal_latency, int digits) { ensureClkArrivals(); ClkLatency clk_latency(this); - clk_latency.reportClkLatency(clks, corner, include_internal_latency, digits); + clk_latency.reportClkLatency(clks, scenes, include_internal_latency, digits); } ClkDelays Sta::findClkDelays(const Clock *clk, + const Scene *scene, bool include_internal_latency) { ensureClkArrivals(); ClkLatency clk_latency(this); - return clk_latency.findClkDelays(clk, nullptr, include_internal_latency); + return clk_latency.findClkDelays(clk, scene, include_internal_latency); } //////////////////////////////////////////////////////////////// @@ -2701,17 +2899,7 @@ Sta::ensureClkArrivals() //////////////////////////////////////////////////////////////// -PinSet -Sta::startpointPins() -{ - ensureGraph(); - PinSet pins(network_); - VertexPinCollector visitor(pins); - search_->visitStartpoints(&visitor); - return pins; -} - -VertexSet * +VertexSet & Sta::endpoints() { ensureGraph(); @@ -2723,7 +2911,7 @@ Sta::endpointPins() { ensureGraph(); PinSet pins(network_); - for (Vertex *vertex : *search_->endpoints()) + for (Vertex *vertex : search_->endpoints()) pins.insert(vertex->pin()); return pins; } @@ -2732,8 +2920,8 @@ int Sta::endpointViolationCount(const MinMax *min_max) { int violations = 0; - for (Vertex *end : *search_->endpoints()) { - if (delayLess(vertexSlack(end, min_max), 0.0, this)) + for (Vertex *end : search_->endpoints()) { + if (delayLess(slack(end, min_max), 0.0, this)) violations++; } return violations; @@ -2751,22 +2939,6 @@ Sta::findRequireds() //////////////////////////////////////////////////////////////// -VertexPathIterator * -Sta::vertexPathIterator(Vertex *vertex, - const RiseFall *rf, - const PathAnalysisPt *path_ap) -{ - return new VertexPathIterator(vertex, rf, path_ap, this); -} - -VertexPathIterator * -Sta::vertexPathIterator(Vertex *vertex, - const RiseFall *rf, - const MinMax *min_max) -{ - return new VertexPathIterator(vertex, rf, min_max, this); -} - Path * Sta::vertexWorstArrivalPath(Vertex *vertex, const MinMax *min_max) @@ -2851,59 +3023,43 @@ Sta::vertexWorstSlackPath(Vertex *vertex, } Arrival -Sta::pinArrival(const Pin *pin, - const RiseFall *rf, +Sta::arrival(const Pin *pin, + const RiseFallBoth *rf, const MinMax *min_max) { Vertex *vertex, *bidirect_vertex; graph_->pinVertices(pin, vertex, bidirect_vertex); - Arrival arrival; + Arrival worst_arrival = min_max->initValue(); if (vertex) - arrival = vertexArrival(vertex, rf, clk_edge_wildcard, nullptr, min_max); + worst_arrival = arrival(vertex, rf, scenes_, min_max); if (bidirect_vertex) { - Arrival arrival1 = vertexArrival(bidirect_vertex, rf, clk_edge_wildcard, - nullptr, min_max); - if (delayLess(arrival1, arrival, this)) - arrival = arrival1; + Arrival arrival2 = arrival(bidirect_vertex, rf, scenes_, min_max); + if (delayGreater(arrival2, worst_arrival, min_max, this)) + worst_arrival = arrival2; } - return arrival; + return worst_arrival; } Arrival -Sta::vertexArrival(Vertex *vertex, - const MinMax *min_max) -{ - return vertexArrival(vertex, nullptr, clk_edge_wildcard, nullptr, min_max); -} - -Arrival -Sta::vertexArrival(Vertex *vertex, - const RiseFall *rf, - const PathAnalysisPt *path_ap) -{ - return vertexArrival(vertex, rf, clk_edge_wildcard, path_ap, nullptr); -} - -Arrival -Sta::vertexArrival(Vertex *vertex, - const RiseFall *rf, - const ClockEdge *clk_edge, - const PathAnalysisPt *path_ap, +Sta::arrival(Vertex *vertex, + const RiseFallBoth *rf, + const SceneSeq &scenes, const MinMax *min_max) { searchPreamble(); search_->findArrivals(vertex->level()); - if (min_max == nullptr) - min_max = path_ap->pathMinMax(); + const SceneSet scenes_set = Scene::sceneSet(scenes); Arrival arrival = min_max->initValue(); - VertexPathIterator path_iter(vertex, rf, path_ap, this); + VertexPathIterator path_iter(vertex, this); while (path_iter.hasNext()) { Path *path = path_iter.next(); const Arrival &path_arrival = path->arrival(); const ClkInfo *clk_info = path->clkInfo(search_); - if ((clk_edge == clk_edge_wildcard - || clk_info->clkEdge() == clk_edge) - && !clk_info->isGenClkSrcPath() + if (!clk_info->isGenClkSrcPath() + && (rf == RiseFallBoth::riseFall() + || path->transition(this)->asRiseFallBoth() == rf) + && path->minMax(this) == min_max + && scenes_set.contains(path->scene(this)) && delayGreater(path->arrival(), arrival, min_max, this)) arrival = path_arrival; } @@ -2911,118 +3067,131 @@ Sta::vertexArrival(Vertex *vertex, } Required -Sta::vertexRequired(Vertex *vertex, - const MinMax *min_max) -{ - return vertexRequired(vertex, nullptr, clk_edge_wildcard, nullptr, min_max); -} - -Required -Sta::vertexRequired(Vertex *vertex, - const RiseFall *rf, - const MinMax *min_max) -{ - return vertexRequired(vertex, rf, clk_edge_wildcard, nullptr, min_max); -} - -Required -Sta::vertexRequired(Vertex *vertex, - const RiseFall *rf, - const PathAnalysisPt *path_ap) -{ - return vertexRequired(vertex, rf, clk_edge_wildcard, path_ap, nullptr); -} - -Required -Sta::vertexRequired(Vertex *vertex, - const RiseFall *rf, - const ClockEdge *clk_edge, - const PathAnalysisPt *path_ap) -{ - return vertexRequired(vertex, rf, clk_edge, path_ap, nullptr); -} - -Required -Sta::vertexRequired(Vertex *vertex, - const RiseFall *rf, - const ClockEdge *clk_edge, - const PathAnalysisPt *path_ap, +Sta::required(Vertex *vertex, + const RiseFallBoth *rf, + const SceneSeq &scenes, const MinMax *min_max) { findRequired(vertex); - const MinMax *req_min_max = min_max - ? min_max->opposite() - : path_ap->pathMinMax()->opposite(); + const SceneSet scenes_set = Scene::sceneSet(scenes); + const MinMax *req_min_max = min_max->opposite(); Required required = req_min_max->initValue(); - VertexPathIterator path_iter(vertex, rf, path_ap, min_max, this); + VertexPathIterator path_iter(vertex, this); while (path_iter.hasNext()) { const Path *path = path_iter.next(); const Required path_required = path->required(); - if ((clk_edge == clk_edge_wildcard - || path->clkEdge(search_) == clk_edge) + if ((rf == RiseFallBoth::riseFall() + || path->transition(this)->asRiseFallBoth() == rf) + && path->minMax(this) == min_max + && scenes_set.contains(path->scene(this)) && delayGreater(path_required, required, req_min_max, this)) required = path_required; } return required; } +//////////////////////////////////////////////////////////////// + Slack -Sta::netSlack(const Net *net, +Sta::slack(const Net *net, const MinMax *min_max) { ensureGraph(); - Slack slack = MinMax::min()->initValue(); + Slack min_slack = MinMax::min()->initValue(); NetConnectedPinIterator *pin_iter = network_->connectedPinIterator(net); while (pin_iter->hasNext()) { const Pin *pin = pin_iter->next(); if (network_->isLoad(pin)) { Vertex *vertex = graph_->pinLoadVertex(pin); - Slack pin_slack = vertexSlack(vertex, min_max); - if (delayLess(pin_slack, slack, this)) - slack = pin_slack; + Slack pin_slack = slack(vertex, min_max); + if (delayLess(pin_slack, min_slack, this)) + min_slack = pin_slack; } } delete pin_iter; - return slack; + return min_slack; } Slack -Sta::pinSlack(const Pin *pin, +Sta::slack(const Pin *pin, + const RiseFallBoth *rf, + const SceneSeq &scenes, const MinMax *min_max) { ensureGraph(); Vertex *vertex, *bidirect_drvr_vertex; graph_->pinVertices(pin, vertex, bidirect_drvr_vertex); - Slack slack = MinMax::min()->initValue(); + Slack min_slack = MinMax::min()->initValue(); if (vertex) - slack = vertexSlack(vertex, min_max); + min_slack = slack(vertex, rf, scenes, min_max); if (bidirect_drvr_vertex) { - Slack slack1 = vertexSlack(bidirect_drvr_vertex, min_max); - if (delayLess(slack1, slack, this)) - slack = slack1; + Slack slack1 = slack(bidirect_drvr_vertex, rf, scenes, min_max); + if (delayLess(slack1, min_slack, this)) + min_slack = slack1; } - return slack; + return min_slack; } Slack -Sta::pinSlack(const Pin *pin, +Sta::slack(Vertex *vertex, + const MinMax *min_max) +{ + return slack(vertex, RiseFallBoth::riseFall(), scenes_, min_max); +} + +Slack +Sta::slack(Vertex *vertex, const RiseFall *rf, const MinMax *min_max) { - ensureGraph(); - Vertex *vertex, *bidirect_drvr_vertex; - graph_->pinVertices(pin, vertex, bidirect_drvr_vertex); - Slack slack = MinMax::min()->initValue(); - if (vertex) - slack = vertexSlack(vertex, rf, min_max); - if (bidirect_drvr_vertex) { - Slack slack1 = vertexSlack(bidirect_drvr_vertex, rf, min_max); - if (delayLess(slack1, slack, this)) - slack = slack1; + return slack(vertex, rf->asRiseFallBoth(), scenes_, min_max); +} + +Slack +Sta::slack(Vertex *vertex, + const RiseFallBoth *rf, + const SceneSeq &scenes, + const MinMax *min_max) +{ + findRequired(vertex); + const SceneSet scenes_set = Scene::sceneSet(scenes); + const MinMax *min = MinMax::min(); + Slack slack = min->initValue(); + VertexPathIterator path_iter(vertex, this); + while (path_iter.hasNext()) { + Path *path = path_iter.next(); + Slack path_slack = path->slack(this); + if ((rf == RiseFallBoth::riseFall() + || path->transition(this)->asRiseFallBoth() == rf) + && path->minMax(this) == min_max + && scenes_set.contains(path->scene(this)) + && delayLess(path_slack, slack, this)) + slack = path_slack; } return slack; } +void +Sta::slacks(Vertex *vertex, + Slack (&slacks)[RiseFall::index_count][MinMax::index_count]) +{ + findRequired(vertex); + for (int rf_index : RiseFall::rangeIndex()) { + for (const MinMax *min_max : MinMax::range()) { + slacks[rf_index][min_max->index()] = MinMax::min()->initValue(); + } + } + VertexPathIterator path_iter(vertex, this); + while (path_iter.hasNext()) { + Path *path = path_iter.next(); + Slack path_slack = path->slack(this); + int rf_index = path->rfIndex(this); + int mm_index = path->minMax(this)->index(); + if (delayLess(path_slack, slacks[rf_index][mm_index], this)) + slacks[rf_index][mm_index] = path_slack; + } +} + //////////////////////////////////////////////////////////////// class EndpointPathEndVisitor : public PathEndVisitor @@ -3093,99 +3262,136 @@ Sta::endpointSlack(const Pin *pin, //////////////////////////////////////////////////////////////// -Slack -Sta::vertexSlack(Vertex *vertex, - const MinMax *min_max) +void +Sta::reportArrivalWrtClks(const Pin *pin, + const Scene *scene, + int digits) { - findRequired(vertex); - Slack slack = MinMax::min()->initValue(); - VertexPathIterator path_iter(vertex, this); - while (path_iter.hasNext()) { - Path *path = path_iter.next(); - if (path->minMax(this) == min_max) { - Slack path_slack = path->slack(this); - if (delayLess(path_slack, slack, this)) - slack = path_slack; - } - } - return slack; -} - -Slack -Sta::vertexSlack(Vertex *vertex, - const RiseFall *rf, - const MinMax *min_max) -{ - findRequired(vertex); - Slack slack = MinMax::min()->initValue(); - VertexPathIterator path_iter(vertex, rf, min_max, this); - while (path_iter.hasNext()) { - Path *path = path_iter.next(); - Slack path_slack = path->slack(this); - if (delayLess(path_slack, slack, this)) - slack = path_slack; - } - return slack; -} - -Slack -Sta::vertexSlack(Vertex *vertex, - const RiseFall *rf, - const PathAnalysisPt *path_ap) -{ - findRequired(vertex); - return vertexSlack1(vertex, rf, clk_edge_wildcard, path_ap); -} - -Slack -Sta::vertexSlack(Vertex *vertex, - const RiseFall *rf, - const ClockEdge *clk_edge, - const PathAnalysisPt *path_ap) -{ - findRequired(vertex); - return vertexSlack1(vertex, rf, clk_edge, path_ap); -} - -Slack -Sta::vertexSlack1(Vertex *vertex, - const RiseFall *rf, - const ClockEdge *clk_edge, - const PathAnalysisPt *path_ap) -{ - const MinMax *min = MinMax::min(); - Slack slack = min->initValue(); - VertexPathIterator path_iter(vertex, rf, path_ap, this); - while (path_iter.hasNext()) { - Path *path = path_iter.next(); - Slack path_slack = path->slack(this); - if ((clk_edge == clk_edge_wildcard - || path->clkEdge(search_) == clk_edge) - && delayLess(path_slack, slack, this)) - slack = path_slack; - } - return slack; + reportDelaysWrtClks(pin, scene, digits, + [] (const Path *path) { + return path->arrival(); + }); } void -Sta::vertexSlacks(Vertex *vertex, - Slack (&slacks)[RiseFall::index_count][MinMax::index_count]) +Sta::reportRequiredWrtClks(const Pin *pin, + const Scene *scene, + int digits) +{ + reportDelaysWrtClks(pin, scene, digits, + [] (const Path *path) { + return path->required(); + }); +} + +void +Sta::reportSlackWrtClks(const Pin *pin, + const Scene *scene, + int digits) +{ + reportDelaysWrtClks(pin, scene, digits, + [this] (const Path *path) { + return path->slack(this); + }); +} + +void +Sta::reportDelaysWrtClks(const Pin *pin, + const Scene *scene, + int digits, + PathDelayFunc get_path_delay) +{ + ensureGraph(); + Vertex *vertex, *bidir_vertex; + graph_->pinVertices(pin, vertex, bidir_vertex); + if (vertex) + reportDelaysWrtClks(vertex, scene, digits, get_path_delay); + if (bidir_vertex) + reportDelaysWrtClks(vertex, scene, digits, get_path_delay); +} + +void +Sta::reportDelaysWrtClks(Vertex *vertex, + const Scene *scene, + int digits, + PathDelayFunc get_path_delay) { findRequired(vertex); - for (int rf_index : RiseFall::rangeIndex()) { - for (const MinMax *min_max : MinMax::range()) { - slacks[rf_index][min_max->index()] = MinMax::min()->initValue(); + const Sdc *sdc = scene->sdc(); + reportDelaysWrtClks(vertex, nullptr, scene, digits, get_path_delay); + const ClockEdge *default_clk_edge = sdc->defaultArrivalClock()->edge(RiseFall::rise()); + reportDelaysWrtClks(vertex, default_clk_edge, scene, digits, get_path_delay); + for (const Clock *clk : sdc->sortedClocks()) { + for (const RiseFall *rf : RiseFall::range()) { + const ClockEdge *clk_edge = clk->edge(rf); + reportDelaysWrtClks(vertex, clk_edge, scene, digits, get_path_delay); } } - VertexPathIterator path_iter(vertex, this); +} + +void +Sta::reportDelaysWrtClks(Vertex *vertex, + const ClockEdge *clk_edge, + const Scene *scene, + int digits, + PathDelayFunc get_path_delay) +{ + RiseFallMinMaxDelay delays = findDelaysWrtClks(vertex, clk_edge, scene, + get_path_delay); + if (!delays.empty()) { + std::string clk_name; + if (clk_edge) { + clk_name = " ("; + clk_name += clk_edge->name(); + clk_name += ')'; + } + report_->reportLine("%s r %s:%s f %s:%s", + clk_name.c_str(), + formatDelay(RiseFall::rise(), MinMax::min(), + delays, digits).c_str(), + formatDelay(RiseFall::rise(), MinMax::max(), + delays, digits).c_str(), + formatDelay(RiseFall::fall(), MinMax::min(), + delays, digits).c_str(), + formatDelay(RiseFall::fall(), MinMax::max(), + delays, digits).c_str()); + } +} + +RiseFallMinMaxDelay +Sta::findDelaysWrtClks(Vertex *vertex, + const ClockEdge *clk_edge, + const Scene *scene, + PathDelayFunc get_path_delay) +{ + RiseFallMinMaxDelay delays; + VertexPathIterator path_iter(vertex, scene, nullptr, nullptr, this); while (path_iter.hasNext()) { Path *path = path_iter.next(); - Slack path_slack = path->slack(this); - int rf_index = path->rfIndex(this); - int mm_index = path->minMax(this)->index(); - if (delayLess(path_slack, slacks[rf_index][mm_index], this)) - slacks[rf_index][mm_index] = path_slack; + Delay delay = get_path_delay(path); + const RiseFall *rf = path->transition(this); + const MinMax *min_max = path->minMax(this); + const ClockEdge *path_clk_edge = path->clkEdge(this); + if (path_clk_edge == clk_edge + && !delayInf(delay)) + delays.mergeValue(rf, min_max, delay, this); } + return delays; +} + +std::string +Sta::formatDelay(const RiseFall *rf, + const MinMax *min_max, + const RiseFallMinMaxDelay &delays, + int digits) +{ + Delay delay; + bool exists; + delays.value(rf, min_max, delay, exists); + if (exists) + return delayAsString(delay, this, digits); + else + return "---"; } //////////////////////////////////////////////////////////////// @@ -3270,7 +3476,7 @@ Sta::findClkMinPeriod(const Clock *clk, search_->findArrivals(); VisitPathEnds visit_ends(this); MinPeriodEndVisitor min_period_visitor(clk, include_port_paths, this); - for (Vertex *vertex : *search_->endpoints()) { + for (Vertex *vertex : search_->endpoints()) { findRequired(vertex); visit_ends.visitPathEnds(vertex, &min_period_visitor); } @@ -3286,7 +3492,7 @@ Sta::findRequired(Vertex *vertex) search_->findAllArrivals(); if (search_->isEndpoint(vertex) // Need to include downstream required times if there is fanout. - && !hasFanout(vertex, search_->searchAdj(), graph_)) + && !hasFanout(vertex, search_->searchAdj(), graph_, cmdMode())) search_->seedRequired(vertex); else search_->findRequireds(vertex->level()); @@ -3300,11 +3506,11 @@ Sta::totalNegativeSlack(const MinMax *min_max) } Slack -Sta::totalNegativeSlack(const Corner *corner, +Sta::totalNegativeSlack(const Scene *scene, const MinMax *min_max) { searchPreamble(); - return search_->totalNegativeSlack(corner, min_max); + return search_->totalNegativeSlack(scene, min_max); } Slack @@ -3328,14 +3534,14 @@ Sta::worstSlack(const MinMax *min_max, } void -Sta::worstSlack(const Corner *corner, +Sta::worstSlack(const Scene *scene, const MinMax *min_max, // Return values. Slack &worst_slack, Vertex *&worst_vertex) { searchPreamble(); - return search_->worstSlack(corner, min_max, worst_slack, worst_vertex); + return search_->worstSlack(scene, min_max, worst_slack, worst_vertex); } //////////////////////////////////////////////////////////////// @@ -3343,12 +3549,12 @@ Sta::worstSlack(const Corner *corner, string Sta::reportDelayCalc(Edge *edge, TimingArc *arc, - const Corner *corner, + const Scene *scene, const MinMax *min_max, int digits) { findDelays(); - return graph_delay_calc_->reportDelayCalc(edge, arc, corner, min_max, digits); + return graph_delay_calc_->reportDelayCalc(edge, arc, scene, min_max, digits); } void @@ -3385,8 +3591,9 @@ Sta::findDelays(Level level) void Sta::delayCalcPreamble() { - ensureLibLinked(); - ensureClkNetwork(); + ensureLevelized(); + for (Mode *mode : modes_) + mode->clkNetwork()->ensureClkNetwork(); } void @@ -3398,27 +3605,31 @@ Sta::setIncrementalDelayTolerance(float tol) ArcDelay Sta::arcDelay(Edge *edge, TimingArc *arc, - const DcalcAnalysisPt *dcalc_ap) + DcalcAPIndex ap_index) { findDelays(edge->to(graph_)); - return graph_->arcDelay(edge, arc, dcalc_ap->index()); + return graph_->arcDelay(edge, arc, ap_index); } bool Sta::arcDelayAnnotated(Edge *edge, TimingArc *arc, - DcalcAnalysisPt *dcalc_ap) + const Scene *scene, + const MinMax *min_max) { - return graph_->arcDelayAnnotated(edge, arc, dcalc_ap->index()); + DcalcAPIndex ap_index = scene->dcalcAnalysisPtIndex(min_max); + return graph_->arcDelayAnnotated(edge, arc, ap_index); } void Sta::setArcDelayAnnotated(Edge *edge, TimingArc *arc, - DcalcAnalysisPt *dcalc_ap, + const Scene *scene, + const MinMax *min_max, bool annotated) { - graph_->setArcDelayAnnotated(edge, arc, dcalc_ap->index(), annotated); + DcalcAPIndex ap_index = scene->dcalcAnalysisPtIndex(min_max); + graph_->setArcDelayAnnotated(edge, arc, ap_index, annotated); Vertex *to = edge->to(graph_); search_->arrivalInvalid(to); search_->requiredInvalid(edge->from(graph_)); @@ -3427,49 +3638,17 @@ Sta::setArcDelayAnnotated(Edge *edge, } Slew -Sta::vertexSlew(Vertex *vertex, - const RiseFall *rf, - const Corner *corner, - const MinMax *min_max) -{ - findDelays(vertex); - const DcalcAnalysisPt *dcalc_ap = corner->findDcalcAnalysisPt(min_max); - return graph_->slew(vertex, rf, dcalc_ap->index()); -} - -Slew -Sta::vertexSlew(Vertex *vertex, - const RiseFall *rf, - const DcalcAnalysisPt *dcalc_ap) -{ - findDelays(vertex); - return graph_->slew(vertex, rf, dcalc_ap->index()); -} - -Slew -Sta::vertexSlew(Vertex *vertex, - const RiseFall *rf, +Sta::slew(Vertex *vertex, + const RiseFallBoth *rf, + const SceneSeq &scenes, const MinMax *min_max) { findDelays(vertex); Slew mm_slew = min_max->initValue(); - for (const DcalcAnalysisPt *dcalc_ap : corners_->dcalcAnalysisPts()) { - Slew slew = graph_->slew(vertex, rf, dcalc_ap->index()); - if (delayGreater(slew, mm_slew, min_max, this)) - mm_slew = slew; - } - return mm_slew; -} - -Slew -Sta::vertexSlew(Vertex *vertex, - const MinMax *min_max) -{ - findDelays(vertex); - Slew mm_slew = min_max->initValue(); - for (const DcalcAnalysisPt *dcalc_ap : corners_->dcalcAnalysisPts()) { - for (const RiseFall *rf : RiseFall::range()) { - Slew slew = graph_->slew(vertex, rf, dcalc_ap->index()); + for (const Scene *scene : scenes) { + DcalcAPIndex ap_index = scene->dcalcAnalysisPtIndex(min_max); + for (const RiseFall *rf : rf->range()) { + Slew slew = graph_->slew(vertex, rf, ap_index); if (delayGreater(slew, mm_slew, min_max, this)) mm_slew = slew; } @@ -3518,7 +3697,7 @@ Sta::ensureGraph() void Sta::makeGraph() { - graph_ = new Graph(this, 2, corners_->dcalcAnalysisPtCount()); + graph_ = new Graph(this, 2, dcalcAnalysisPtCount()); graph_->makeGraph(); } @@ -3526,10 +3705,6 @@ void Sta::ensureLevelized() { ensureGraph(); - ensureGraphSdcAnnotated(); - // Need constant propagation before levelization to know edges that - // are disabled by constants. - sim_->ensureConstantsPropagated(); levelize_->ensureLevelized(); } @@ -3538,12 +3713,15 @@ Sta::updateGeneratedClks() { if (update_genclks_) { ensureLevelized(); + for (Mode *mode : modes_) { + Genclks *genclks = mode->genclks(); + Sdc *sdc = mode->sdc(); bool gen_clk_changed = true; while (gen_clk_changed) { gen_clk_changed = false; - for (Clock *clk : sdc_->clks()) { + for (Clock *clk : sdc->clocks()) { if (clk->isGenerated() && !clk->waveformValid()) { - search_->genclks()->ensureMaster(clk); + genclks->ensureMaster(clk, sdc); Clock *master_clk = clk->masterClk(); if (master_clk && master_clk->waveformValid()) { clk->generate(master_clk); @@ -3553,6 +3731,7 @@ Sta::updateGeneratedClks() } } } + } update_genclks_ = false; } @@ -3570,18 +3749,6 @@ Sta::graphLoops() return levelize_->loops(); } -PathAnalysisPt * -Sta::pathAnalysisPt(Path *path) -{ - return path->pathAnalysisPt(this); -} - -DcalcAnalysisPt * -Sta::pathDcalcAnalysisPt(Path *path) -{ - return pathAnalysisPt(path)->dcalcAnalysisPt(); -} - Vertex * Sta::maxPathCountVertex() const { @@ -3642,14 +3809,13 @@ Sta::clkInfoCount() const void Sta::setArcDelay(Edge *edge, TimingArc *arc, - const Corner *corner, + const Scene *scene, const MinMaxAll *min_max, ArcDelay delay) { ensureGraph(); for (const MinMax *mm : min_max->range()) { - const DcalcAnalysisPt *dcalc_ap = corner->findDcalcAnalysisPt(mm); - DcalcAPIndex ap_index = dcalc_ap->index(); + DcalcAPIndex ap_index = scene->dcalcAnalysisPtIndex(mm); graph_->setArcDelay(edge, arc, ap_index, delay); // Don't let delay calculation clobber the value. graph_->setArcDelayAnnotated(edge, arc, ap_index, true); @@ -3664,15 +3830,14 @@ Sta::setArcDelay(Edge *edge, void Sta::setAnnotatedSlew(Vertex *vertex, - const Corner *corner, + const Scene *scene, const MinMaxAll *min_max, const RiseFallBoth *rf, float slew) { ensureGraph(); for (const MinMax *mm : min_max->range()) { - const DcalcAnalysisPt *dcalc_ap = corner->findDcalcAnalysisPt(mm); - DcalcAPIndex ap_index = dcalc_ap->index(); + DcalcAPIndex ap_index = scene->dcalcAnalysisPtIndex(mm); for (const RiseFall *rf1 : rf->range()) { graph_->setSlew(vertex, rf1, ap_index, slew); // Don't let delay calculation clobber the value. @@ -3684,7 +3849,7 @@ Sta::setAnnotatedSlew(Vertex *vertex, void Sta::writeSdf(const char *filename, - const Corner *corner, + const Scene *scene, char divider, bool include_typ, int digits, @@ -3693,7 +3858,7 @@ Sta::writeSdf(const char *filename, bool no_version) { findDelays(); - sta::writeSdf(filename, corner, divider, include_typ, digits, gzip, + sta::writeSdf(filename, scene, divider, include_typ, digits, gzip, no_timestamp, no_version, this); } @@ -3707,50 +3872,55 @@ Sta::removeDelaySlewAnnotations() } LogicValue -Sta::simLogicValue(const Pin *pin) +Sta::simLogicValue(const Pin *pin, + const Mode *mode) { ensureGraph(); - sim_->ensureConstantsPropagated(); - return sim_->logicValue(pin); + Sim *sim = mode->sim(); + sim->ensureConstantsPropagated(); + return sim->simValue(pin); } +//////////////////////////////////////////////////////////////// + +// These constants are mode/sdc independent. + void Sta::findLogicConstants() { ensureGraph(); - sim_->findLogicConstants(); + // Sdc independent constants so any mode should return the same values. + Sim *sim = cmdMode()->sim(); + sim->findLogicConstants(); } void Sta::clearLogicConstants() { - sim_->clear(); + Sim *sim = cmdMode()->sim(); + sim->clear(); } +//////////////////////////////////////////////////////////////// + void Sta::setPortExtPinCap(const Port *port, const RiseFallBoth *rf, - const Corner *corner, const MinMaxAll *min_max, - float cap) + float cap, + Sdc *sdc) { for (const RiseFall *rf1 : rf->range()) { - for (const MinMax *mm : min_max->range()) { - if (corner == nullptr) { - for (const Corner *corner : *corners_) - sdc_->setPortExtPinCap(port, rf1, corner, mm, cap); - } - else - sdc_->setPortExtPinCap(port, rf1, corner, mm, cap); - } + for (const MinMax *mm : min_max->range()) + sdc->setPortExtPinCap(port, rf1, mm, cap); } delaysInvalidFromFanin(port); } void Sta::portExtCaps(const Port *port, - const Corner *corner, const MinMax *min_max, + const Sdc *sdc, float &pin_cap, float &wire_cap, int &fanout) @@ -3765,7 +3935,7 @@ Sta::portExtCaps(const Port *port, float pin_cap1, wire_cap1; int fanout1; bool pin_exists1, wire_exists1, fanout_exists1; - sdc_->portExtCap(port, rf, corner, min_max, + sdc->portExtCap(port, rf, min_max, pin_cap1, pin_exists1, wire_cap1, wire_exists1, fanout1, fanout_exists1); @@ -3792,82 +3962,63 @@ Sta::portExtCaps(const Port *port, void Sta::setPortExtWireCap(const Port *port, - bool subtract_pin_cap, const RiseFallBoth *rf, - const Corner *corner, const MinMaxAll *min_max, - float cap) + float cap, + Sdc *sdc) { for (const RiseFall *rf1 : rf->range()) { - for (const MinMax *mm : min_max->range()) { - if (corner == nullptr) { - for (const Corner *corner : *corners_) - sdc_->setPortExtWireCap(port, subtract_pin_cap, rf1, corner, mm, cap); - } - else - sdc_->setPortExtWireCap(port, subtract_pin_cap, rf1, corner, mm, cap); - } + for (const MinMax *mm : min_max->range()) + sdc->setPortExtWireCap(port, rf1, mm, cap); } delaysInvalidFromFanin(port); } void -Sta::removeNetLoadCaps() const +Sta::removeNetLoadCaps(Sdc *sdc) const { - sdc_->removeNetLoadCaps(); + sdc->removeNetLoadCaps(); delaysInvalid(); } void Sta::setPortExtFanout(const Port *port, int fanout, - const Corner *corner, - const MinMaxAll *min_max) + const MinMaxAll *min_max, + Sdc *sdc) { - for (const MinMax *mm : min_max->range()) { - if (corner == nullptr) { - for (const Corner *corner : *corners_) - sdc_->setPortExtFanout(port, corner, mm, fanout); - } - else - sdc_->setPortExtFanout(port, corner, mm, fanout); - } + for (const MinMax *mm : min_max->range()) + sdc->setPortExtFanout(port, mm, fanout); delaysInvalidFromFanin(port); } void Sta::setNetWireCap(const Net *net, bool subtract_pin_cap, - const Corner *corner, const MinMaxAll *min_max, - float cap) + float cap, + Sdc *sdc) { - for (const MinMax *mm : min_max->range()) { - if (corner == nullptr) { - for (const Corner *corner : *corners_) - sdc_->setNetWireCap(net, subtract_pin_cap, corner, mm, cap); - } - else - sdc_->setNetWireCap(net, subtract_pin_cap, corner, mm, cap); - } + for (const MinMax *mm : min_max->range()) + sdc->setNetWireCap(net, subtract_pin_cap, mm, cap); delaysInvalidFromFanin(net); } void Sta::connectedCap(const Pin *drvr_pin, const RiseFall *rf, - const Corner *corner, + const Scene *scene, const MinMax *min_max, float &pin_cap, float &wire_cap) const { - const DcalcAnalysisPt *dcalc_ap = corner->findDcalcAnalysisPt(min_max); - graph_delay_calc_->loadCap(drvr_pin, rf, dcalc_ap, pin_cap, wire_cap); + graph_delay_calc_->loadCap(drvr_pin, rf, scene, min_max, + pin_cap, wire_cap); } void Sta::connectedCap(const Net *net, - Corner *corner, + Scene *scene, const MinMax *min_max, float &pin_cap, float &wire_cap) const @@ -3876,10 +4027,10 @@ Sta::connectedCap(const Net *net, if (drvr_pin) { pin_cap = min_max->initValue(); wire_cap = min_max->initValue(); - for (const Corner *corner : makeCornerSeq(corner)) { + for (const Scene *scene : makeSceneSeq(scene)) { for (const RiseFall *rf : RiseFall::range()) { float pin_cap1, wire_cap1; - connectedCap(drvr_pin, rf, corner, min_max, pin_cap1, wire_cap1); + connectedCap(drvr_pin, rf, scene, min_max, pin_cap1, wire_cap1); pin_cap = min_max->minMax(pin_cap, pin_cap1); wire_cap = min_max->minMax(wire_cap, wire_cap1); } @@ -3891,28 +4042,18 @@ Sta::connectedCap(const Net *net, } } -CornerSeq -Sta::makeCornerSeq(Corner *corner) const -{ - CornerSeq corners; - if (corner) - corners.push_back(corner); - else - corners = corners_->corners(); - return corners; -} - float Sta::capacitance(const LibertyPort *port, - Corner *corner, + Scene *scene, const MinMax *min_max) { - OperatingConditions *op_cond = operatingConditions(min_max); float cap = min_max->initValue(); - for (const Corner *corner : makeCornerSeq(corner)) { - const LibertyPort *corner_port = port->cornerPort(corner, min_max); + for (const Scene *scene : makeSceneSeq(scene)) { + const Sdc *sdc = scene->sdc(); + OperatingConditions *op_cond = operatingConditions(min_max, sdc); + const LibertyPort *scene_port = port->scenePort(scene, min_max); for (const RiseFall *rf : RiseFall::range()) - cap = min_max->minMax(cap, corner_port->capacitance(rf, min_max, op_cond, op_cond)); + cap = min_max->minMax(cap, scene_port->capacitance(rf, min_max, op_cond, op_cond)); } return cap; } @@ -3940,17 +4081,19 @@ Sta::findNetParasiticDrvrPin(const Net *net) const void Sta::setResistance(const Net *net, const MinMaxAll *min_max, - float res) + float res, + Sdc *sdc) { - sdc_->setResistance(net, min_max, res); + sdc->setResistance(net, min_max, res); } //////////////////////////////////////////////////////////////// bool -Sta::readSpef(const char *filename, +Sta::readSpef(const std::string &name, + const std::string &filename, Instance *instance, - const Corner *corner, + Scene *scene, // -scene deprecated 11/20/2025 const MinMaxAll *min_max, bool pin_cap_included, bool keep_coupling_caps, @@ -3958,43 +4101,66 @@ Sta::readSpef(const char *filename, bool reduce) { ensureLibLinked(); - setParasiticAnalysisPts(corner != nullptr); - const MinMax *ap_min_max = (min_max == MinMaxAll::all()) - ? MinMax::max() - : min_max->asMinMax(); - const Corner *ap_corner = corner ? corner : corners_->corners()[0]; - ParasiticAnalysisPt *ap = ap_corner->findParasiticAnalysisPt(ap_min_max); - bool success = readSpefFile(filename, instance, ap, + Parasitics *parasitics = nullptr; + // Use -name to distinguish rel 2.7 args for compatibility. + if (name.empty()) { + std::string spef_name = "default"; + if (scene + || min_max != MinMaxAll::minMax()) { + if (scene) + spef_name = scene->name(); + if (min_max != MinMaxAll::minMax()) { + spef_name += "_"; + spef_name += min_max->to_string(); + } + parasitics = makeConcreteParasitics(spef_name, filename); + } + else + parasitics = findParasitics(spef_name); + if (scene) + scene->setParasitics(parasitics, min_max); + else { + parasitics = findParasitics(spef_name); + for (Scene *scene : scenes_) + scene->setParasitics(parasitics, min_max); + } + } + else { + parasitics = findParasitics(name); + if (parasitics == nullptr) + parasitics = makeConcreteParasitics(name, filename); + } + + bool success = readSpefFile(filename.c_str(), instance, pin_cap_included, keep_coupling_caps, coupling_cap_factor, reduce, - corner, min_max, this); + scene, min_max, parasitics, this); delaysInvalid(); return success; } -void -Sta::setParasiticAnalysisPts(bool per_corner) +Parasitics * +Sta::findParasitics(const std::string &name) { - if (per_corner != parasitics_per_corner_) { - deleteParasitics(); - parasitics_per_corner_ = per_corner; - makeParasiticAnalysisPts(); - } + return findKey(parasitics_name_map_, name); } void -Sta::makeParasiticAnalysisPts() -{ - corners_->makeParasiticAnalysisPts(parasitics_per_corner_); -} - -void -Sta::reportParasiticAnnotation(bool report_unannotated, - const Corner *corner) +Sta::reportParasiticAnnotation(const string &spef_name, + bool report_unannotated) { ensureLibLinked(); ensureGraph(); - sta::reportParasiticAnnotation(report_unannotated, corner, this); + Parasitics *parasitics = nullptr; + if (!spef_name.empty()) { + parasitics = findParasitics(spef_name); + if (parasitics == nullptr) + report_->error(1560, "spef %s not found.", spef_name.c_str()); + } + else + parasitics = cmd_scene_->parasitics(MinMax::max()); + sta::reportParasiticAnnotation(parasitics, report_unannotated, + cmd_scene_, this); } void @@ -4006,11 +4172,11 @@ Sta::findPiElmore(Pin *drvr_pin, float &c1, bool &exists) const { - Corner *corner = cmd_corner_; - const ParasiticAnalysisPt *ap = corner->findParasiticAnalysisPt(min_max); - Parasitic *pi_elmore = parasitics_->findPiElmore(drvr_pin, rf, ap); + Scene *scene = cmd_scene_; + const Parasitics *parasitics = scene->parasitics(min_max); + Parasitic *pi_elmore = parasitics->findPiElmore(drvr_pin, rf, min_max); if (pi_elmore) { - parasitics_->piModel(pi_elmore, c2, rpi, c1); + parasitics->piModel(pi_elmore, c2, rpi, c1); exists = true; } else @@ -4025,10 +4191,10 @@ Sta::makePiElmore(Pin *drvr_pin, float rpi, float c1) { - const Corner *corner = cmd_corner_; + const Scene *scene = cmd_scene_; for (const MinMax *mm : min_max->range()) { - ParasiticAnalysisPt *ap = corner->findParasiticAnalysisPt(mm); - parasitics_->makePiElmore(drvr_pin, rf, ap, c2, rpi, c1); + Parasitics *parasitics = scene->parasitics(mm); + parasitics->makePiElmore(drvr_pin, rf, mm, c2, rpi, c1); } delaysInvalidFrom(drvr_pin); } @@ -4041,11 +4207,11 @@ Sta::findElmore(Pin *drvr_pin, float &elmore, bool &exists) const { - Corner *corner = cmd_corner_; - const ParasiticAnalysisPt *ap = corner->findParasiticAnalysisPt(min_max); - Parasitic *pi_elmore = parasitics_->findPiElmore(drvr_pin, rf, ap); + Scene *scene = cmd_scene_; + const Parasitics *parasitics = scene->parasitics(min_max); + Parasitic *pi_elmore = parasitics->findPiElmore(drvr_pin, rf, min_max); if (pi_elmore) - parasitics_->findElmore(pi_elmore, load_pin, elmore, exists); + parasitics->findElmore(pi_elmore, load_pin, elmore, exists); else exists = false; } @@ -4057,12 +4223,12 @@ Sta::setElmore(Pin *drvr_pin, const MinMaxAll *min_max, float elmore) { - const Corner *corner = cmd_corner_; + const Scene *scene = cmd_scene_; for (const MinMax *mm : min_max->range()) { - const ParasiticAnalysisPt *ap = corner->findParasiticAnalysisPt(mm); - Parasitic *pi_elmore = parasitics_->findPiElmore(drvr_pin, rf, ap); + Parasitics *parasitics = scene->parasitics(mm); + Parasitic *pi_elmore = parasitics->findPiElmore(drvr_pin, rf, mm); if (pi_elmore) - parasitics_->setElmore(pi_elmore, load_pin, elmore); + parasitics->setElmore(pi_elmore, load_pin, elmore); } delaysInvalidFrom(drvr_pin); } @@ -4070,17 +4236,39 @@ Sta::setElmore(Pin *drvr_pin, void Sta::deleteParasitics() { - parasitics_->deleteParasitics(); + Parasitics *parasitics_default = findParasitics("default"); + for (auto [name, parasitics] : parasitics_name_map_) { + if (parasitics != parasitics_default) + delete parasitics; + } + parasitics_name_map_.clear(); + + parasitics_name_map_[parasitics_default->name()] = parasitics_default; + + for (Scene *scene : scenes_) + scene->setParasitics(parasitics_default, MinMaxAll::minMax()); + delaysInvalid(); } +Parasitics * +Sta::makeConcreteParasitics(std::string name, + std::string filename) +{ + Parasitics *parasitics = new ConcreteParasitics(name, filename, this); + parasitics_name_map_[name] = parasitics; + return parasitics; +} + Parasitic * Sta::makeParasiticNetwork(const Net *net, bool includes_pin_caps, - const ParasiticAnalysisPt *ap) + const Scene *scene, + const MinMax *min_max) { - Parasitic *parasitic = parasitics_->makeParasiticNetwork(net, includes_pin_caps, ap); - delaysInvalidFromFanin(const_cast(net)); + Parasitics *parasitics = scene->parasitics(min_max); + Parasitic *parasitic = parasitics->makeParasiticNetwork(net, includes_pin_caps); + delaysInvalidFromFanin(net); return parasitic; } @@ -4284,7 +4472,7 @@ Sta::replaceEquivCellBefore(const Instance *inst, if (to_set) edge->setTimingArcSet(to_set); else - report_->critical(1555, "corresponding timing arc set not found in equiv cells"); + report_->critical(1556, "corresponding timing arc set not found in equiv cells"); } } } @@ -4307,8 +4495,10 @@ Sta::replaceEquivCellAfter(const Instance *inst) InstancePinIterator *pin_iter = network_->pinIterator(inst); while (pin_iter->hasNext()) { Pin *pin = pin_iter->next(); - if (network_->direction(pin)->isAnyInput()) - parasitics_->loadPinCapacitanceChanged(pin); + if (network_->direction(pin)->isAnyInput()) { + for (auto [name, parasitics] : parasitics_name_map_) + parasitics->loadPinCapacitanceChanged(pin); + } } delete pin_iter; } @@ -4336,10 +4526,13 @@ Sta::replaceCellPinInvalidate(const LibertyPort *from_port, bool Sta::idealClockMode() { - for (Clock *clk : sdc_->clks()) { + for (Mode *mode : modes_) { + Sdc *sdc = mode->sdc(); + for (Clock *clk : sdc->clocks()) { if (clk->isPropagated()) return false; } + } return true; } @@ -4393,9 +4586,12 @@ Sta::replaceCellAfter(const Instance *inst) InstancePinIterator *pin_iter = network_->pinIterator(inst); while (pin_iter->hasNext()) { Pin *pin = pin_iter->next(); - sim_->pinSetFuncAfter(pin); - if (network_->direction(pin)->isAnyInput()) - parasitics_->loadPinCapacitanceChanged(pin); + for (const Mode *mode : modes_) + mode->sim()->pinSetFuncAfter(pin); + if (network_->direction(pin)->isAnyInput()) { + for (auto [name, parasitics] : parasitics_name_map_) + parasitics->loadPinCapacitanceChanged(pin); + } } delete pin_iter; } @@ -4444,8 +4640,10 @@ Sta::connectPinAfter(const Pin *pin) } } } - sdc_->connectPinAfter(pin); - sim_->connectPinAfter(pin); + for (Mode *mode : modes_) { + mode->sdc()->connectPinAfter(pin); + mode->sim()->connectPinAfter(pin); + } clk_skews_->clear(); } @@ -4459,15 +4657,18 @@ Sta::connectDrvrPinAfter(Vertex *vertex) Vertex *to_vertex = edge->to(graph_); search_->arrivalInvalid(to_vertex); search_->endpointInvalid(to_vertex); - sdc_->clkHpinDisablesChanged(to_vertex->pin()); + for (Mode *mode : modes_) + mode->sdc()->clkHpinDisablesChanged(to_vertex->pin()); } Pin *pin = vertex->pin(); - sdc_->clkHpinDisablesChanged(pin); + for (Mode *mode : modes_) { + mode->sdc()->clkHpinDisablesChanged(pin); + mode->clkNetwork()->connectPinAfter(pin); + } graph_delay_calc_->delayInvalid(vertex); search_->requiredInvalid(vertex); search_->endpointInvalid(vertex); levelize_->relevelizeFrom(vertex); - clk_network_->connectPinAfter(pin); } void @@ -4480,15 +4681,18 @@ Sta::connectLoadPinAfter(Vertex *vertex) Vertex *from_vertex = edge->from(graph_); graph_delay_calc_->delayInvalid(from_vertex); search_->requiredInvalid(from_vertex); - sdc_->clkHpinDisablesChanged(from_vertex->pin()); + for (Mode *mode : modes_) + mode->sdc()->clkHpinDisablesChanged(from_vertex->pin()); levelize_->relevelizeFrom(from_vertex); } Pin *pin = vertex->pin(); - sdc_->clkHpinDisablesChanged(pin); + for (Mode *mode : modes_) { + mode->sdc()->clkHpinDisablesChanged(pin); + mode->clkNetwork()->connectPinAfter(pin); + } graph_delay_calc_->delayInvalid(vertex); search_->arrivalInvalid(vertex); search_->endpointInvalid(vertex); - clk_network_->connectPinAfter(pin); } void @@ -4497,8 +4701,16 @@ Sta::disconnectPinBefore(const Pin *pin) debugPrint(debug_, "network_edit", 1, "disconnect %s from %s", sdc_network_->pathName(pin), sdc_network_->pathName(network_->net(pin))); - parasitics_->disconnectPinBefore(pin, network_); - sim_->disconnectPinBefore(pin); + + for (auto [name, parasitics] : parasitics_name_map_) + parasitics->disconnectPinBefore(pin); + bool is_hierarchical = network_->isHierarchical(pin); + for (Mode *mode : modes_) { + mode->sim()->disconnectPinBefore(pin); + if (!is_hierarchical) + mode->clkNetwork()->disconnectPinBefore(pin); + } + if (graph_) { if (network_->isDriver(pin)) { Vertex *vertex = graph_->pinDrvrVertex(pin); @@ -4510,7 +4722,6 @@ Sta::disconnectPinBefore(const Pin *pin) if (edge->role()->isWire()) deleteEdge(edge); } - clk_network_->disconnectPinBefore(pin); } } if (network_->isLoad(pin)) { @@ -4523,17 +4734,18 @@ Sta::disconnectPinBefore(const Pin *pin) if (edge->role()->isWire()) deleteEdge(edge); } - clk_network_->disconnectPinBefore(pin); } } - if (network_->isHierarchical(pin)) { + if (is_hierarchical) { // Delete wire edges thru pin. EdgesThruHierPinIterator edge_iter(pin, network_, graph_); while (edge_iter.hasNext()) { Edge *edge = edge_iter.next(); if (edge->role()->isWire()) { deleteEdge(edge); - clk_network_->disconnectPinBefore(edge->from(graph_)->pin()); + const Pin *from_pin = edge->from(graph_)->pin(); + for (Mode *mode : modes_) + mode->clkNetwork()->disconnectPinBefore(from_pin); } } } @@ -4552,7 +4764,8 @@ Sta::deleteEdge(Edge *edge) graph_delay_calc_->delayInvalid(to); levelize_->relevelizeFrom(to); levelize_->deleteEdgeBefore(edge); - sdc_->clkHpinDisablesChanged(edge->from(graph_)->pin()); + for (Mode *mode : modes_) + mode->sdc()->clkHpinDisablesChanged(edge->from(graph_)->pin()); graph_->deleteEdge(edge); } @@ -4581,7 +4794,8 @@ Sta::deleteNetBefore(const Net *net) } delete pin_iter; } - sdc_->deleteNetBefore(net); + for (Mode *mode : modes_) + mode->sdc()->deleteNetBefore(net); } void @@ -4607,8 +4821,10 @@ Sta::deleteInstanceBefore(const Instance *inst) void Sta::deleteLeafInstanceBefore(const Instance *inst) { - sim_->deleteInstanceBefore(inst); - sdc_->deleteInstanceBefore(inst); + for (Mode *mode : modes_) { + mode->sim()->deleteInstanceBefore(inst); + mode->sdc()->deleteInstanceBefore(inst); + } power_->deleteInstanceBefore(inst); } @@ -4684,9 +4900,12 @@ Sta::deletePinBefore(const Pin *pin) } } } - sdc_->deletePinBefore(pin); - sim_->deletePinBefore(pin); - clk_network_->deletePinBefore(pin); + + for (const Mode *mode : modes_) { + mode->sdc()->deletePinBefore(pin); + mode->sim()->deletePinBefore(pin); + mode->clkNetwork()->deletePinBefore(pin); + } power_->deletePinBefore(pin); clk_skews_->clear(); } @@ -4796,18 +5015,20 @@ Sta::delaysInvalidFromFanin(Vertex *vertex) //////////////////////////////////////////////////////////////// ClockSet -Sta::clocks(const Pin *pin) +Sta::clocks(const Pin *pin, + const Mode *mode) { ensureClkArrivals(); - return search_->clocks(pin); + return search_->clocks(pin, mode); } ClockSet -Sta::clockDomains(const Pin *pin) +Sta::clockDomains(const Pin *pin, + const Mode *mode) { searchPreamble(); search_->findAllArrivals(); - return search_->clockDomains(pin); + return search_->clockDomains(pin, mode); } //////////////////////////////////////////////////////////////// @@ -4816,59 +5037,68 @@ InstanceSet Sta::findRegisterInstances(ClockSet *clks, const RiseFallBoth *clk_rf, bool edge_triggered, - bool latches) + bool latches, + const Mode *mode) { - findRegisterPreamble(); - return findRegInstances(clks, clk_rf, edge_triggered, latches, this); + findRegisterPreamble(mode); + return findRegInstances(clks, clk_rf, edge_triggered, latches, + mode, this); } PinSet Sta::findRegisterDataPins(ClockSet *clks, const RiseFallBoth *clk_rf, bool edge_triggered, - bool latches) + bool latches, + const Mode *mode) { - findRegisterPreamble(); - return findRegDataPins(clks, clk_rf, edge_triggered, latches, this); + findRegisterPreamble(mode); + return findRegDataPins(clks, clk_rf, edge_triggered, latches, + mode, this); } PinSet Sta::findRegisterClkPins(ClockSet *clks, const RiseFallBoth *clk_rf, bool edge_triggered, - bool latches) + bool latches, + const Mode *mode) { - findRegisterPreamble(); - return findRegClkPins(clks, clk_rf, edge_triggered, latches, this); + findRegisterPreamble(mode); + return findRegClkPins(clks, clk_rf, edge_triggered, latches, + mode, this); } PinSet Sta::findRegisterAsyncPins(ClockSet *clks, const RiseFallBoth *clk_rf, bool edge_triggered, - bool latches) + bool latches, + const Mode *mode) { - findRegisterPreamble(); - return findRegAsyncPins(clks, clk_rf, edge_triggered, latches, this); + findRegisterPreamble(mode); + return findRegAsyncPins(clks, clk_rf, edge_triggered, latches, + mode, this); } PinSet Sta::findRegisterOutputPins(ClockSet *clks, const RiseFallBoth *clk_rf, bool edge_triggered, - bool latches) + bool latches, + const Mode *mode) { - findRegisterPreamble(); - return findRegOutputPins(clks, clk_rf, edge_triggered, latches, this); + findRegisterPreamble(mode); + return findRegOutputPins(clks, clk_rf, edge_triggered, latches, + mode, this); } void -Sta::findRegisterPreamble() +Sta::findRegisterPreamble(const Mode *mode) { ensureLibLinked(); ensureGraph(); - ensureGraphSdcAnnotated(); - sim_->ensureConstantsPropagated(); + mode->sim()->ensureConstantsPropagated(); } //////////////////////////////////////////////////////////////// @@ -4879,13 +5109,16 @@ public: FanInOutSrchPred(bool thru_disabled, bool thru_constants, const StaState *sta); - virtual bool searchFrom(const Vertex *from_vertex); - virtual bool searchThru(Edge *edge); - virtual bool searchTo(const Vertex *to_vertex); + bool searchFrom(const Vertex *from_vertex, + const Mode *mode) const override; + bool searchThru(Edge *edge, + const Mode *mode) const override; + bool searchTo(const Vertex *to_vertex, + const Mode *mode) const override; protected: bool crossesHierarchy(Edge *edge); - virtual bool searchThruRole(Edge *edge); + virtual bool searchThruRole(Edge *edge) const; bool thru_disabled_; bool thru_constants_; @@ -4895,7 +5128,7 @@ protected: FanInOutSrchPred::FanInOutSrchPred(bool thru_disabled, bool thru_constants, const StaState *sta) : - SearchPred(), + SearchPred(sta), thru_disabled_(thru_disabled), thru_constants_(thru_constants), sta_(sta) @@ -4903,28 +5136,34 @@ FanInOutSrchPred::FanInOutSrchPred(bool thru_disabled, } bool -FanInOutSrchPred::searchFrom(const Vertex *from_vertex) +FanInOutSrchPred::searchFrom(const Vertex *from_vertex, + const Mode *mode) const { + const Pin *from_pin = from_vertex->pin(); + const Sdc *sdc = mode->sdc(); return (thru_disabled_ - || !from_vertex->isDisabledConstraint()) + || !sdc->isDisabledConstraint(from_pin)) && (thru_constants_ - || !from_vertex->isConstant()); + || !mode->sim()->isConstant(from_vertex)); } bool -FanInOutSrchPred::searchThru(Edge *edge) +FanInOutSrchPred::searchThru(Edge *edge, + const Mode *mode) const { + const Sdc *sdc = mode->sdc(); + const Sim *sim = mode->sim(); return searchThruRole(edge) && (thru_disabled_ - || !(edge->isDisabledConstraint() - || edge->isDisabledCond() + || !(sdc->isDisabledConstraint(edge) + || sim->isDisabledCond(edge) || sta_->isDisabledCondDefault(edge))) && (thru_constants_ - || edge->simTimingSense() != TimingSense::none); + || sim->simTimingSense(edge) != TimingSense::none); } bool -FanInOutSrchPred::searchThruRole(Edge *edge) +FanInOutSrchPred::searchThruRole(Edge *edge) const { const TimingRole *role = edge->role(); return role == TimingRole::wire() @@ -4946,12 +5185,15 @@ FanInOutSrchPred::crossesHierarchy(Edge *edge) } bool -FanInOutSrchPred::searchTo(const Vertex *to_vertex) +FanInOutSrchPred::searchTo(const Vertex *to_vertex, + const Mode *mode) const { + const Pin *to_pin = to_vertex->pin(); + const Sdc *sdc = mode->sdc(); return (thru_disabled_ - || !to_vertex->isDisabledConstraint()) + || !sdc->isDisabledConstraint(to_pin)) && (thru_constants_ - || !to_vertex->isConstant()); + || !mode->sim()->isConstant(to_vertex)); } class FaninSrchPred : public FanInOutSrchPred @@ -4962,7 +5204,7 @@ public: const StaState *sta); protected: - virtual bool searchThruRole(Edge *edge); + bool searchThruRole(Edge *edge) const override; }; FaninSrchPred::FaninSrchPred(bool thru_disabled, @@ -4973,7 +5215,7 @@ FaninSrchPred::FaninSrchPred(bool thru_disabled, } bool -FaninSrchPred::searchThruRole(Edge *edge) +FaninSrchPred::searchThruRole(Edge *edge) const { const TimingRole *role = edge->role(); return role == TimingRole::wire() @@ -4991,10 +5233,12 @@ Sta::findFaninPins(PinSeq *to, int inst_levels, int pin_levels, bool thru_disabled, - bool thru_constants) + bool thru_constants, + const Mode *mode) { ensureGraph(); ensureLevelized(); + mode->sim()->ensureConstantsPropagated(); PinSet fanin(network_); FaninSrchPred pred(thru_disabled, thru_constants, this); for (const Pin *pin : *to) { @@ -5003,13 +5247,13 @@ Sta::findFaninPins(PinSeq *to, while (edge_iter.hasNext()) { Edge *edge = edge_iter.next(); findFaninPins(edge->from(graph_), flat, startpoints_only, - inst_levels, pin_levels, fanin, pred); + inst_levels, pin_levels, fanin, pred, mode); } } else { Vertex *vertex = graph_->pinLoadVertex(pin); findFaninPins(vertex, flat, startpoints_only, - inst_levels, pin_levels, fanin, pred); + inst_levels, pin_levels, fanin, pred, mode); } } return fanin; @@ -5022,18 +5266,17 @@ Sta::findFaninPins(Vertex *vertex, int inst_levels, int pin_levels, PinSet &fanin, - SearchPred &pred) + SearchPred &pred, + const Mode *mode) { - VertexSet visited(graph_); + VertexSet visited = makeVertexSet(this); findFaninPins(vertex, flat, inst_levels, - pin_levels, visited, &pred, 0, 0); - VertexSet::Iterator visited_iter(visited); - while (visited_iter.hasNext()) { - Vertex *visited_vertex = visited_iter.next(); + pin_levels, visited, &pred, 0, 0, mode); + for (Vertex *visited_vertex : visited) { Pin *visited_pin = visited_vertex->pin(); if (!startpoints_only || network_->isRegClkPin(visited_pin) - || !hasFanin(visited_vertex, &pred, graph_)) + || !hasFanin(visited_vertex, &pred, graph_, mode)) fanin.insert(visited_pin); } } @@ -5046,11 +5289,12 @@ Sta::findFaninPins(Vertex *to, VertexSet &visited, SearchPred *pred, int inst_level, - int pin_level) + int pin_level, + const Mode *mode) { debugPrint(debug_, "fanin", 1, "%s", to->to_string(this).c_str()); - if (!visited.hasKey(to)) { + if (!visited.contains(to)) { visited.insert(to); Pin *to_pin = to->pin(); bool is_reg_clk_pin = network_->isRegClkPin(to_pin); @@ -5059,19 +5303,19 @@ Sta::findFaninPins(Vertex *to, || inst_level < inst_levels) && (pin_levels <= 0 || pin_level < pin_levels) - && pred->searchTo(to)) { + && pred->searchTo(to, mode)) { VertexInEdgeIterator edge_iter(to, graph_); while (edge_iter.hasNext()) { Edge *edge = edge_iter.next(); Vertex *from_vertex = edge->from(graph_); - if (pred->searchThru(edge) + if (pred->searchThru(edge, mode) && (flat || !crossesHierarchy(edge)) - && pred->searchFrom(from_vertex)) { + && pred->searchFrom(from_vertex, mode)) { findFaninPins(from_vertex, flat, inst_levels, pin_levels, visited, pred, edge->role()->isWire() ? inst_level : inst_level+1, - pin_level+1); + pin_level+1, mode); } } } @@ -5085,10 +5329,11 @@ Sta::findFaninInstances(PinSeq *to, int inst_levels, int pin_levels, bool thru_disabled, - bool thru_constants) + bool thru_constants, + const Mode *mode) { PinSet pins = findFaninPins(to, flat, startpoints_only, inst_levels, - pin_levels, thru_disabled, thru_constants); + pin_levels, thru_disabled, thru_constants, mode); return pinInstances(pins, network_); } @@ -5099,27 +5344,27 @@ Sta::findFanoutPins(PinSeq *from, int inst_levels, int pin_levels, bool thru_disabled, - bool thru_constants) + bool thru_constants, + const Mode *mode) { ensureGraph(); ensureLevelized(); + mode->sim()->ensureConstantsPropagated(); PinSet fanout(network_); FanInOutSrchPred pred(thru_disabled, thru_constants, this); - PinSeq::Iterator from_iter(from); - while (from_iter.hasNext()) { - const Pin *pin = from_iter.next(); + for (const Pin *pin : *from) { if (network_->isHierarchical(pin)) { EdgesThruHierPinIterator edge_iter(pin, network_, graph_); while (edge_iter.hasNext()) { Edge *edge = edge_iter.next(); findFanoutPins(edge->to(graph_), flat, endpoints_only, - inst_levels, pin_levels, fanout, pred); + inst_levels, pin_levels, fanout, pred, mode); } } else { Vertex *vertex = graph_->pinDrvrVertex(pin); findFanoutPins(vertex, flat, endpoints_only, - inst_levels, pin_levels, fanout, pred); + inst_levels, pin_levels, fanout, pred, mode); } } return fanout; @@ -5132,17 +5377,16 @@ Sta::findFanoutPins(Vertex *vertex, int inst_levels, int pin_levels, PinSet &fanout, - SearchPred &pred) + SearchPred &pred, + const Mode *mode) { - VertexSet visited(graph_); + VertexSet visited = makeVertexSet(this); findFanoutPins(vertex, flat, inst_levels, - pin_levels, visited, &pred, 0, 0); - VertexSet::Iterator visited_iter(visited); - while (visited_iter.hasNext()) { - Vertex *visited_vertex = visited_iter.next(); + pin_levels, visited, &pred, 0, 0, mode); + for (Vertex *visited_vertex : visited) { Pin *visited_pin = visited_vertex->pin(); if (!endpoints_only - || search_->isEndpoint(visited_vertex, &pred)) + || search_->isEndpoint(visited_vertex, &pred, mode)) fanout.insert(visited_pin); } } @@ -5156,30 +5400,31 @@ Sta::findFanoutPins(Vertex *from, VertexSet &visited, SearchPred *pred, int inst_level, - int pin_level) + int pin_level, + const Mode *mode) { debugPrint(debug_, "fanout", 1, "%s", from->to_string(this).c_str()); - if (!visited.hasKey(from)) { + if (!visited.contains(from)) { visited.insert(from); - if (!search_->isEndpoint(from, pred) + if (!search_->isEndpoint(from, pred, mode) && (inst_levels <= 0 || inst_level < inst_levels) && (pin_levels <= 0 || pin_level < pin_levels) - && pred->searchFrom(from)) { + && pred->searchFrom(from, mode)) { VertexOutEdgeIterator edge_iter(from, graph_); while (edge_iter.hasNext()) { Edge *edge = edge_iter.next(); Vertex *to_vertex = edge->to(graph_); - if (pred->searchThru(edge) + if (pred->searchThru(edge, mode) && (flat || !crossesHierarchy(edge)) - && pred->searchTo(to_vertex)) { + && pred->searchTo(to_vertex, mode)) { findFanoutPins(to_vertex, flat, inst_levels, pin_levels, visited, pred, edge->role()->isWire() ? inst_level : inst_level+1, - pin_level+1); + pin_level+1, mode); } } } @@ -5193,10 +5438,11 @@ Sta::findFanoutInstances(PinSeq *from, int inst_levels, int pin_levels, bool thru_disabled, - bool thru_constants) + bool thru_constants, + const Mode *mode) { PinSet pins = findFanoutPins(from, flat, endpoints_only, inst_levels, - pin_levels, thru_disabled, thru_constants); + pin_levels, thru_disabled, thru_constants, mode); return pinInstances(pins, network_); } @@ -5245,7 +5491,8 @@ instMaxSlew(const Instance *inst, Pin *pin = pin_iter->next(); if (network->isDriver(pin)) { Vertex *vertex = graph->pinDrvrVertex(pin); - Slew slew = sta->vertexSlew(vertex, MinMax::max()); + Slew slew = sta->slew(vertex, RiseFallBoth::riseFall(), + sta->scenes(), MinMax::max()); if (delayGreater(slew, max_slew, sta)) max_slew = slew; } @@ -5272,79 +5519,77 @@ Sta::slowDrivers(int count) //////////////////////////////////////////////////////////////// void -Sta::checkSlewLimitPreamble() +Sta::reportSlewChecks(const Net *net, + size_t max_count, + bool violators, + bool verbose, + const SceneSeq &scenes, + const MinMax *min_max) { - if (sdc_->haveClkSlewLimits()) + checkSlewsPreamble(); + SlewCheckSeq &checks = check_slews_->check(net, max_count, violators, scenes, min_max); + if (!checks.empty()) { + report_->reportLine("%s slew", min_max->to_string().c_str()); + report_->reportLine(""); + + if (!verbose) + report_path_->reportLimitShortHeader(report_path_->fieldSlew()); + for (SlewCheck &check : checks) { + if (verbose) + report_path_->reportLimitVerbose(report_path_->fieldSlew(), + check.pin(), check.edge(), + delayAsFloat(check.slew()), + check.limit(), check.slack(), + check.scene(), min_max); + else + report_path_->reportLimitShort(report_path_->fieldSlew(), check.pin(), + delayAsFloat(check.slew()), + check.limit(), check.slack()); + } + report_->reportLine(""); + } +} + +void +Sta::checkSlewsPreamble() +{ + ensureLevelized(); + bool have_clk_slew_limits = false; + for (Mode *mode : modes_) { + if (mode->sdc()->haveClkSlewLimits()) + have_clk_slew_limits = true; + mode->clkNetwork()->ensureClkNetwork(); + } + if (have_clk_slew_limits) // Arrivals are needed to know pin clock domains. updateTiming(false); else findDelays(); - if (check_slew_limits_ == nullptr) - makeCheckSlewLimits(); - ensureClkNetwork(); -} - -PinSeq -Sta::checkSlewLimits(Net *net, - bool violators, - const Corner *corner, - const MinMax *min_max) -{ - checkSlewLimitPreamble(); - return check_slew_limits_->checkSlewLimits(net, violators, corner, min_max); -} - -void -Sta::reportSlewLimitShortHeader() -{ - report_path_->reportLimitShortHeader(report_path_->fieldSlew()); -} - -void -Sta::reportSlewLimitShort(Pin *pin, - const Corner *corner, - const MinMax *min_max) -{ - const Corner *corner1; - const RiseFall *rf1; - Slew slew1; - float limit1, slack1; - check_slew_limits_->checkSlew(pin, corner, min_max, true, - corner1, rf1, slew1, limit1, slack1); - report_path_->reportLimitShort(report_path_->fieldSlew(), pin, - delayAsFloat(slew1), limit1, slack1); -} - -void -Sta::reportSlewLimitVerbose(Pin *pin, - const Corner *corner, - const MinMax *min_max) -{ - const Corner *corner1; - const RiseFall *rf1; - Slew slew1; - float limit1, slack1; - check_slew_limits_->checkSlew(pin, corner, min_max, true, - corner1, rf1, slew1, limit1, slack1); - report_path_->reportLimitVerbose(report_path_->fieldSlew(), pin, rf1, - delayAsFloat(slew1), - limit1, slack1, corner1, min_max); + if (check_slews_ == nullptr) + makeCheckSlews(); } void Sta::checkSlew(const Pin *pin, - const Corner *corner, + const SceneSeq &scenes, const MinMax *min_max, bool check_clks, // Return values. - const Corner *&corner1, - const RiseFall *&rf, Slew &slew, float &limit, - float &slack) + float &slack, + const RiseFall *&rf, + const Scene *&scene) { - check_slew_limits_->checkSlew(pin, corner, min_max, check_clks, - corner1, rf, slew, limit, slack); + check_slews_->check(pin, scenes, min_max, check_clks, + slew, limit, slack, rf, scene); +} + +size_t +Sta::maxSlewViolationCount() +{ + checkSlewsPreamble(); + return check_slews_->check(nullptr, 1, true, scenes_, MinMax::max()).size(); } void @@ -5354,188 +5599,210 @@ Sta::maxSlewCheck(// Return values. float &slack, float &limit) { - checkSlewLimitPreamble(); - PinSeq pins = check_slew_limits_->checkSlewLimits(nullptr, false, nullptr, - MinMax::max()); + checkSlewsPreamble(); + SlewCheckSeq &checks = check_slews_->check(nullptr, 1, false, scenes_, MinMax::max()); + if (!checks.empty()) { + SlewCheck &check = checks[0]; + pin = check.pin(); + slew = check.slew(); + slack = check.slack(); + limit = check.limit(); + } + else { pin = nullptr; slew = 0.0; slack = INF; - limit = INF; - if (!pins.empty()) { - pin = pins[0]; - const Corner *corner; - const RiseFall *rf; - check_slew_limits_->checkSlew(pin, nullptr, MinMax::max(), true, - corner, rf, slew, limit, slack); } } void Sta::findSlewLimit(const LibertyPort *port, - const Corner *corner, + const Scene *scene, const MinMax *min_max, // Return values. float &limit, bool &exists) { - if (check_slew_limits_ == nullptr) - makeCheckSlewLimits(); - check_slew_limits_->findLimit(port, corner, min_max, + if (check_slews_ == nullptr) + makeCheckSlews(); + check_slews_->findLimit(port, scene, min_max, limit, exists); } ////////////////////////////////////////////////////////////////' void -Sta::checkFanoutLimitPreamble() -{ - if (check_fanout_limits_ == nullptr) - makeCheckFanoutLimits(); - ensureClkNetwork(); -} - -PinSeq -Sta::checkFanoutLimits(Net *net, +Sta::reportFanoutChecks(const Net *net, + size_t max_count, bool violators, + bool verbose, + const SceneSeq &scenes, const MinMax *min_max) { - checkFanoutLimitPreamble(); - return check_fanout_limits_->checkFanoutLimits(net, violators, min_max); -} + checkFanoutPreamble(); + const ModeSeq modes = Scene::modesSorted(scenes); + FanoutCheckSeq &checks = check_fanouts_->check(net, max_count, violators, + modes, min_max); + if (!checks.empty()) { + report_->reportLine("%s fanout", min_max->to_string().c_str()); + report_->reportLine(""); -void -Sta::reportFanoutLimitShortHeader() -{ + if (!verbose) report_path_->reportLimitShortHeader(report_path_->fieldFanout()); -} -void -Sta::reportFanoutLimitShort(Pin *pin, - const MinMax *min_max) -{ - float fanout, limit, slack; - check_fanout_limits_->checkFanout(pin, min_max, - fanout, limit, slack); - report_path_->reportLimitShort(report_path_->fieldFanout(), - pin, fanout, limit, slack); -} - -void -Sta::reportFanoutLimitVerbose(Pin *pin, - const MinMax *min_max) -{ - float fanout, limit, slack; - check_fanout_limits_->checkFanout(pin, min_max, - fanout, limit, slack); + for (const FanoutCheck &check : checks) { + if (verbose) report_path_->reportLimitVerbose(report_path_->fieldFanout(), - pin, nullptr, fanout, - limit, slack, nullptr, min_max); + check.pin(), nullptr, check.fanout(), + check.limit(), check.slack(), nullptr, + min_max); + else + report_path_->reportLimitShort(report_path_->fieldFanout(), + check.pin(), check.fanout(), + check.limit(), check.slack()); + } + report_->reportLine(""); + } +} + +void +Sta::checkFanoutPreamble() +{ + if (check_fanouts_ == nullptr) + makeCheckFanouts(); + ensureLevelized(); + for (Mode *mode : modes_) { + mode->sim()->ensureConstantsPropagated(); + mode->clkNetwork()->ensureClkNetwork(); + } +} + +size_t +Sta::fanoutViolationCount(const MinMax *min_max, + const ModeSeq &modes) +{ + FanoutCheckSeq &checks = check_fanouts_->check(nullptr, 0, true, modes, min_max); + return checks.size(); } void Sta::checkFanout(const Pin *pin, + const Mode *mode, const MinMax *min_max, // Return values. float &fanout, float &limit, float &slack) { - check_fanout_limits_->checkFanout(pin, min_max, - fanout, limit, slack); + FanoutCheck check = check_fanouts_->check(pin, mode, min_max); + pin = check.pin(); + fanout = check.fanout(); + limit = check.limit(); + slack = check.slack(); } void -Sta::maxFanoutCheck(// Return values. +Sta::maxFanoutMinSlackPin(const ModeSeq &modes, + // Return values. const Pin *&pin, float &fanout, + float &limit, float &slack, - float &limit) + const Mode *&mode) { - checkFanoutLimitPreamble(); - PinSeq pins = check_fanout_limits_->checkFanoutLimits(nullptr, false, MinMax::max()); + checkFanoutPreamble(); + FanoutCheckSeq &checks = check_fanouts_->check(nullptr, 1, false, + modes, MinMax::max()); + if (!checks.empty()) { + FanoutCheck &check = checks[0]; + pin = check.pin(); + fanout = check.fanout(); + limit = check.limit(); + slack = check.slack(); + mode = check.mode(); + } + else { pin = nullptr; fanout = 0; - slack = INF; limit = INF; - if (!pins.empty()) { - pin = pins[0]; - check_fanout_limits_->checkFanout(pin, MinMax::max(), - fanout, limit, slack); + slack = INF; + mode = nullptr; } } ////////////////////////////////////////////////////////////////' void -Sta::checkCapacitanceLimitPreamble() -{ - if (check_capacitance_limits_ == nullptr) - makeCheckCapacitanceLimits(); - ensureClkNetwork(); -} - -PinSeq -Sta::checkCapacitanceLimits(Net *net, +Sta::reportCapacitanceChecks(const Net *net, + size_t max_count, bool violators, - const Corner *corner, + bool verbose, + const SceneSeq &scenes, const MinMax *min_max) { - checkCapacitanceLimitPreamble(); - return check_capacitance_limits_->checkCapacitanceLimits(net, violators, - corner, min_max); -} + checkCapacitancesPreamble(scenes); + CapacitanceCheckSeq &checks = check_capacitances_->check(net, max_count, + violators, + scenes, min_max); + if (!checks.empty()) { + report_->reportLine("%s capacitance", min_max->to_string().c_str()); + report_->reportLine(""); -void -Sta::reportCapacitanceLimitShortHeader() -{ + if (!verbose) report_path_->reportLimitShortHeader(report_path_->fieldCapacitance()); -} - -void -Sta::reportCapacitanceLimitShort(Pin *pin, - const Corner *corner, - const MinMax *min_max) -{ - const Corner *corner1; - const RiseFall *rf; - float capacitance, limit, slack; - check_capacitance_limits_->checkCapacitance(pin, corner, min_max, - corner1, rf, capacitance, - limit, slack); - report_path_->reportLimitShort(report_path_->fieldCapacitance(), - pin, capacitance, limit, slack); -} - -void -Sta::reportCapacitanceLimitVerbose(Pin *pin, - const Corner *corner, - const MinMax *min_max) -{ - const Corner *corner1; - const RiseFall *rf1; - float capacitance1, limit1, slack1; - check_capacitance_limits_->checkCapacitance(pin, corner, min_max, - corner1, rf1, capacitance1, - limit1, slack1); + for (CapacitanceCheck &check : checks) { + if (verbose) report_path_->reportLimitVerbose(report_path_->fieldCapacitance(), - pin, rf1, capacitance1, - limit1, slack1, corner1, min_max); + check.pin(), check.rf(), check.capacitance(), + check.limit(), check.slack(), check.scene(), + min_max); + else + report_path_->reportLimitShort(report_path_->fieldCapacitance(), + check.pin(), check.capacitance(), + check.limit(), check.slack()); + report_->reportLine(""); + } + } +} + +void +Sta::checkCapacitancesPreamble(const SceneSeq &scenes) +{ + ensureLevelized(); + if (check_capacitances_ == nullptr) + makeCheckCapacitances(); + for (Mode *mode : Scene::modes(scenes)) { + mode->sim()->ensureConstantsPropagated(); + mode->clkNetwork()->ensureClkNetwork(); + } } void Sta::checkCapacitance(const Pin *pin, - const Corner *corner, + const SceneSeq &scenes, const MinMax *min_max, // Return values. - const Corner *&corner1, - const RiseFall *&rf, float &capacitance, float &limit, - float &slack) + float &slack, + const RiseFall *&rf, + const Scene *&scene) { - check_capacitance_limits_->checkCapacitance(pin, corner, min_max, - corner1, rf, capacitance, - limit, slack); + CapacitanceCheck check = check_capacitances_->check(pin, scenes, min_max); + pin = check.pin(); + capacitance = check.capacitance(); + limit = check.limit(); + slack = check.slack(); + rf = check.rf(); + scene = check.scene(); +} + +size_t +Sta::maxCapacitanceViolationCount() +{ + checkCapacitancesPreamble(scenes_); + return check_capacitances_->check(nullptr, 1, true, scenes_, + MinMax::max()).size(); } void @@ -5545,131 +5812,70 @@ Sta::maxCapacitanceCheck(// Return values. float &slack, float &limit) { - checkCapacitanceLimitPreamble(); - PinSeq pins = check_capacitance_limits_->checkCapacitanceLimits(nullptr, false, - nullptr, + checkCapacitancesPreamble(scenes_); + CapacitanceCheckSeq &checks = check_capacitances_->check(nullptr, 1, false, + scenes_, MinMax::max()); pin = nullptr; capacitance = 0.0; slack = INF; limit = INF; - if (!pins.empty()) { - pin = pins[0]; - const Corner *corner; - const RiseFall *rf; - check_capacitance_limits_->checkCapacitance(pin, nullptr, MinMax::max(), - corner, rf, capacitance, limit, slack); + if (!checks.empty()) { + const CapacitanceCheck &check = checks[0]; + pin = check.pin(); + capacitance = check.capacitance(); + limit = check.limit(); + slack = check.slack(); } } //////////////////////////////////////////////////////////////// void -Sta::minPulseWidthPreamble() +Sta::reportMinPulseWidthChecks(const Net *net, + size_t max_count, + bool violators, + bool verbose, + const SceneSeq &scenes) { ensureClkArrivals(); if (check_min_pulse_widths_ == nullptr) makeCheckMinPulseWidths(); -} - -MinPulseWidthCheckSeq & -Sta::minPulseWidthChecks(PinSeq *pins, - const Corner *corner) -{ - minPulseWidthPreamble(); - return check_min_pulse_widths_->check(pins, corner); -} - -MinPulseWidthCheckSeq & -Sta::minPulseWidthChecks(const Corner *corner) -{ - minPulseWidthPreamble(); - return check_min_pulse_widths_->check(corner); -} - -MinPulseWidthCheckSeq & -Sta::minPulseWidthViolations(const Corner *corner) -{ - minPulseWidthPreamble(); - return check_min_pulse_widths_->violations(corner); -} - -MinPulseWidthCheck * -Sta::minPulseWidthSlack(const Corner *corner) -{ - minPulseWidthPreamble(); - return check_min_pulse_widths_->minSlackCheck(corner); -} - -void -Sta::reportMpwChecks(MinPulseWidthCheckSeq *checks, - bool verbose) -{ + MinPulseWidthCheckSeq &checks = + check_min_pulse_widths_->check(net, max_count, violators, scenes); report_path_->reportMpwChecks(checks, verbose); } -void -Sta::reportMpwCheck(MinPulseWidthCheck *check, - bool verbose) -{ - report_path_->reportMpwCheck(check, verbose); -} - //////////////////////////////////////////////////////////////// -MinPeriodCheckSeq & -Sta::minPeriodViolations() -{ - minPeriodPreamble(); - const Corner *corner = cmdCorner(); - return check_min_periods_->violations(corner); -} - -MinPeriodCheck * -Sta::minPeriodSlack() -{ - minPeriodPreamble(); - const Corner *corner = cmdCorner(); - return check_min_periods_->minSlackCheck(corner); -} - void -Sta::minPeriodPreamble() +Sta::reportMinPeriodChecks(const Net *net, + size_t max_count, + bool violators, + bool verbose, + const SceneSeq &scenes) { // Need clk arrivals to know what clks arrive at the clk tree endpoints. ensureClkArrivals(); if (check_min_periods_ == nullptr) makeCheckMinPeriods(); -} - -void -Sta::reportChecks(MinPeriodCheckSeq *checks, - bool verbose) -{ + MinPeriodCheckSeq &checks = check_min_periods_->check(net, max_count, + violators, scenes); report_path_->reportChecks(checks, verbose); } -void -Sta::reportCheck(MinPeriodCheck *check, - bool verbose) -{ - report_path_->reportCheck(check, verbose); -} - //////////////////////////////////////////////////////////////// -MaxSkewCheckSeq & -Sta::maxSkewViolations() +void +Sta::reportMaxSkewChecks(const Net *net, + size_t max_count, + bool violators, + bool verbose, + const SceneSeq &scenes) { maxSkewPreamble(); - return check_max_skews_->violations(); -} - -MaxSkewCheck * -Sta::maxSkewSlack() -{ - maxSkewPreamble(); - return check_max_skews_->minSlackCheck(); + MaxSkewCheckSeq &checks = check_max_skews_->check(net, max_count, violators, scenes); + report_path_->reportChecks(checks, verbose); } void @@ -5680,20 +5886,6 @@ Sta::maxSkewPreamble() makeCheckMaxSkews(); } -void -Sta::reportChecks(MaxSkewCheckSeq *checks, - bool verbose) -{ - report_path_->reportChecks(checks, verbose); -} - -void -Sta::reportCheck(MaxSkewCheck *check, - bool verbose) -{ - report_path_->reportCheck(check, verbose); -} - //////////////////////////////////////////////////////////////// void @@ -5719,29 +5911,77 @@ void Sta::writeTimingModel(const char *lib_name, const char *cell_name, const char *filename, - const Corner *corner) + const Scene *scene) { ensureLibLinked(); ensureGraph(); LibertyLibrary *library = makeTimingModel(lib_name, cell_name, filename, - corner, this); + scene, this); writeLiberty(library, filename, this); } //////////////////////////////////////////////////////////////// void -Sta::powerPreamble() +Sta::reportPowerDesign(const Scene *scene, + int digits) +{ + powerPreamble(scene); + power_->reportDesign(scene, digits); +} + +void +Sta::reportPowerInsts(const InstanceSeq &insts, + const Scene *scene, + int digits) +{ + powerPreamble(scene); + power_->reportInsts(insts, scene, digits); +} + +void +Sta::reportPowerHighestInsts(size_t count, + const Scene *scene, + int digits) +{ + powerPreamble(scene); + power_->reportHighestInsts(count, scene, digits); +} + +void +Sta::reportPowerDesignJson(const Scene *scene, + int digits) +{ + powerPreamble(scene); + power_->reportDesignJson(scene, digits); +} + +void +Sta::reportPowerInstsJson(const InstanceSeq &insts, + const Scene *scene, + int digits) +{ + powerPreamble(scene); + power_->reportInstsJson(insts, scene, digits); +} + +void +Sta::powerPreamble(const Scene *scene) { ensureLibLinked(); // Use arrivals to find clocking info. searchPreamble(); search_->findAllArrivals(); - ensureClkNetwork(); + if (scene) + scene->mode()->clkNetwork()->ensureClkNetwork(); + else { + for (Mode *mode : modes_) + mode->clkNetwork()->ensureClkNetwork(); + } } void -Sta::power(const Corner *corner, +Sta::power(const Scene *scene, // Return values. PowerResult &total, PowerResult &sequential, @@ -5750,23 +5990,24 @@ Sta::power(const Corner *corner, PowerResult ¯o, PowerResult &pad) { - powerPreamble(); - power_->power(corner, total, sequential, combinational, clock, macro, pad); + powerPreamble(scene); + power_->power(scene, total, sequential, combinational, clock, macro, pad); } PowerResult Sta::power(const Instance *inst, - const Corner *corner) + const Scene *scene) { - powerPreamble(); - return power_->power(inst, corner); + powerPreamble(scene); + return power_->power(inst, scene); } PwrActivity -Sta::activity(const Pin *pin) +Sta::activity(const Pin *pin, + const Scene *scene) { - powerPreamble(); - return power_->pinActivity(pin); + powerPreamble(scene); + return power_->pinActivity(pin, scene); } //////////////////////////////////////////////////////////////// @@ -5790,46 +6031,51 @@ Sta::writePathSpice(Path *path, //////////////////////////////////////////////////////////////// void -Sta::ensureClkNetwork() +Sta::ensureClkNetwork(const Mode *mode) { ensureLevelized(); - clk_network_->ensureClkNetwork(); + mode->clkNetwork()->ensureClkNetwork(); } bool -Sta::isClock(const Pin *pin) const +Sta::isClock(const Pin *pin, + const Mode *mode) const { - return clk_network_->isClock(pin); + return mode->clkNetwork()->isClock(pin); } bool -Sta::isClock(const Net *net) const +Sta::isClock(const Net *net, + const Mode *mode) const { - return clk_network_->isClock(net); + return mode->clkNetwork()->isClock(net); } bool -Sta::isIdealClock(const Pin *pin) const +Sta::isIdealClock(const Pin *pin, + const Mode *mode) const { - return clk_network_->isIdealClock(pin); + return mode->clkNetwork()->isIdealClock(pin); } bool -Sta::isPropagatedClock(const Pin *pin) const +Sta::isPropagatedClock(const Pin *pin, + const Mode *mode) const { - return clk_network_->isPropagatedClock(pin); + return mode->clkNetwork()->isPropagatedClock(pin); } const PinSet * -Sta::pins(const Clock *clk) +Sta::pins(const Clock *clk, + const Mode *mode) { - return clk_network_->pins(clk); + return mode->clkNetwork()->pins(clk); } void -Sta::clkPinsInvalid() +Sta::clkPinsInvalid(const Mode *mode) { - clk_network_->clkPinsInvalid(); + mode->clkNetwork()->clkPinsInvalid(); } } // namespace diff --git a/search/StaState.cc b/search/StaState.cc index c9eb7438..fca51792 100644 --- a/search/StaState.cc +++ b/search/StaState.cc @@ -26,6 +26,7 @@ #include +#include "ContainerHelpers.hh" #include "DispatchQueue.hh" #include "Units.hh" #include "Network.hh" @@ -33,6 +34,8 @@ #include "Sdc.hh" #include "Graph.hh" #include "TimingArc.hh" +#include "Mode.hh" +#include "Scene.hh" namespace sta { @@ -41,17 +44,12 @@ StaState::StaState() : debug_(nullptr), units_(nullptr), network_(nullptr), - sdc_(nullptr), - corners_(nullptr), graph_(nullptr), levelize_(nullptr), - parasitics_(nullptr), arc_delay_calc_(nullptr), graph_delay_calc_(nullptr), - sim_(nullptr), search_(nullptr), latches_(nullptr), - clk_network_(nullptr), variables_(nullptr), thread_count_(1), dispatch_queue_(nullptr), @@ -113,17 +111,60 @@ StaState::setDebug(Debug *debug) } bool -StaState::crprActive() const +StaState::crprActive(const Mode *mode) const { - return sdc_->analysisType() == AnalysisType::ocv + return mode->sdc()->analysisType() == AnalysisType::ocv && variables_->crprEnabled(); } bool -StaState::isDisabledCondDefault(Edge *edge) const +StaState::isDisabledCondDefault(const Edge *edge) const { return !variables_->condDefaultArcsEnabled() && edge->timingArcSet()->isCondDefault(); } +//////////////////////////////////////////////////////////////// + +size_t +StaState::scenePathCount() const +{ + return scenes_.size() * MinMax::index_count; +} + +// The clock insertion delay (source latency) required for setup and +// hold checks is: +// +// hold check +// report_timing -delay_type min +// path insertion pll_delay +// src clk min early max +// tgt clk max late min +// +// setup check +// report_timing -delay_type max +// path insertion pll_delay +// src clk max late min +// tgt clk min early max +// +// For analysis type single or bc_wc only one path is required, but as +// shown above both early and late insertion delays are required. +// To find propagated generated clock insertion delays both early and +// late clock network paths are required. Thus, analysis type single +// makes min and max analysis points. +// Only one of them is enabled to "report paths". + +DcalcAPIndex +StaState::dcalcAnalysisPtCount() const +{ + return MinMax::index_count * scenes_.size(); +} + +const SceneSet +StaState::scenesSet() +{ + return Scene::sceneSet(scenes_); +} + + } // namespace diff --git a/search/Tag.cc b/search/Tag.cc index 27badadc..5e368d80 100644 --- a/search/Tag.cc +++ b/search/Tag.cc @@ -31,23 +31,23 @@ #include "ExceptionPath.hh" #include "Sdc.hh" #include "Graph.hh" -#include "Corner.hh" +#include "Scene.hh" #include "Search.hh" -#include "PathAnalysisPt.hh" #include "ClkInfo.hh" namespace sta { -Tag::Tag(TagIndex index, - int rf_index, - PathAPIndex path_ap_index, - const ClkInfo *clk_info, - bool is_clk, - InputDelay *input_delay, - bool is_segment_start, - ExceptionStateSet *states, - bool own_states, - const StaState *sta) : +Tag::Tag(Scene *scene, + TagIndex index, + const RiseFall *rf, + const MinMax *min_max, + const ClkInfo *clk_info, + bool is_clk, + InputDelay *input_delay, + bool is_segment_start, + ExceptionStateSet *states, + bool own_states) : + scene_(scene), clk_info_(clk_info), input_delay_(input_delay), states_(states), @@ -57,18 +57,18 @@ Tag::Tag(TagIndex index, is_loop_(false), is_segment_start_(is_segment_start), own_states_(own_states), - rf_index_(rf_index), - path_ap_index_(path_ap_index) + rf_index_(rf->index()), + min_max_index_(min_max->index()) { findHash(); if (states_) { - FilterPath *filter = sta->search()->filter(); + FilterPath *filter = scene_->sdc()->filter(); for (ExceptionState *state : *states_) { ExceptionPath *exception = state->exception(); if (exception->isLoop()) - is_loop_ = true; + is_loop_ = true; if (exception == filter) - is_filter_ = true; + is_filter_ = true; } } } @@ -91,24 +91,25 @@ Tag::to_string(bool report_index, const StaState *sta) const { const Network *network = sta->network(); - const Corners *corners = sta->corners(); std::string result; - if (report_index) + if (report_index) { result += std::to_string(index_); + result += " "; + } + + result += scene_->name(); + result += " "; if (report_rf_min_max) { const RiseFall *rf = transition(); - PathAnalysisPt *path_ap = corners->findPathAnalysisPt(path_ap_index_); + const MinMax *min_max = minMax(); + result += rf->to_string(); result += " "; - result += rf->to_string().c_str(); + result += min_max->to_string(); result += " "; - result += path_ap->pathMinMax()->to_string(); - result += "/"; - result += std::to_string(path_ap_index_); } - result += " "; const ClockEdge *clk_edge = clkEdge(); if (clk_edge) result += clk_edge->name(); @@ -121,11 +122,11 @@ Tag::to_string(bool report_index, if (is_clk_) { result += "clock"; if (clk_info_->isPropagated()) - result += " prop"; + result += " prop"; else - result += " ideal"; + result += " ideal"; if (is_genclk_src) - result += " "; + result += " "; } if (clk_info_->isGenClkSrcPath()) result += "genclk"; @@ -162,13 +163,13 @@ Tag::to_string(bool report_index, result += " "; result += exception->asString(network); if (state->nextThru()) { - result += " (next thru "; - result += state->nextThru()->asString(network); - result += ")"; + result += " (next thru "; + result += state->nextThru()->asString(network); + result += ")"; } else { - if (exception->thrus() != nullptr) - result += " (thrus complete)"; + if (exception->thrus() != nullptr) + result += " (thrus complete)"; } } } @@ -182,16 +183,9 @@ Tag::transition() const } const MinMax * -Tag::minMax(const StaState *sta) const +Tag::minMax() const { - return pathAnalysisPt(sta)->pathMinMax(); -} - -PathAnalysisPt * -Tag::pathAnalysisPt(const StaState *sta) const -{ - const Corners *corners = sta->corners(); - return corners->findPathAnalysisPt(path_ap_index_); + return MinMax::find(min_max_index_); } void @@ -225,24 +219,24 @@ Tag::isGenClkSrcPath() const } const Clock * -Tag::genClkSrcPathClk(const StaState *sta) const +Tag::genClkSrcPathClk() const { if (clk_info_->isGenClkSrcPath() && states_) { - FilterPath *filter = sta->search()->filter(); + FilterPath *filter = scene_->sdc()->filter(); for (ExceptionState *state : *states_) { ExceptionPath *except = state->exception(); if (except->isFilter() - && except != filter) { - ExceptionTo *to = except->to(); - if (to) { - ClockSet *clks = to->clks(); - if (clks && clks->size() == 1) { - ClockSet::Iterator clk_iter(clks); - const Clock *clk = clk_iter.next(); - return clk; - } - } + && except != filter) { + ExceptionTo *to = except->to(); + if (to) { + ClockSet *clks = to->clks(); + if (clks && clks->size() == 1) { + ClockSet::iterator clk_iter = clks->begin(); + const Clock *clk = *clk_iter; + return clk; + } + } } } } @@ -254,8 +248,9 @@ Tag::findHash() { // Common to hash_ and match_hash_. hash_ = hash_init_value; + hashIncr(hash_, scene_->index()); hashIncr(hash_, rf_index_); - hashIncr(hash_, path_ap_index_); + hashIncr(hash_, min_max_index_); hashIncr(hash_, is_clk_); hashIncr(hash_, is_segment_start_); if (states_) { @@ -275,7 +270,7 @@ Tag::findHash() size_t Tag::hash(bool match_crpr_clk_pin, - const StaState *sta) const + const StaState *sta) const { if (match_crpr_clk_pin) return hashSum(hash_, clk_info_->crprClkVertexId(sta)); @@ -302,32 +297,32 @@ TagLess::TagLess(const StaState *sta) : bool TagLess::operator()(const Tag *tag1, - const Tag *tag2) const + const Tag *tag2) const { return Tag::cmp(tag1, tag2, sta_) < 0; } int Tag::cmp(const Tag *tag1, - const Tag *tag2, - const StaState *sta) + const Tag *tag2, + const StaState *sta) { if (tag1 == tag2) return 0; + size_t scene_index1 = tag1->scene()->index(); + size_t scene_index2 = tag2->scene()->index(); + if (scene_index1 < scene_index2) + return -1; + else if (scene_index1 > scene_index2) + return 1; + const ClkInfo *clk_info1 = tag1->clkInfo(); const ClkInfo *clk_info2 = tag2->clkInfo(); int clk_cmp = ClkInfo::cmp(clk_info1, clk_info2, sta); if (clk_cmp != 0) return clk_cmp; - PathAPIndex path_ap_index1 = tag1->pathAPIndex(); - PathAPIndex path_ap_index2 = tag2->pathAPIndex(); - if (path_ap_index1 < path_ap_index2) - return -1; - if (path_ap_index1 > path_ap_index2) - return 1; - int rf_index1 = tag1->rfIndex(); int rf_index2 = tag2->rfIndex(); if (rf_index1 < rf_index2) @@ -335,6 +330,13 @@ Tag::cmp(const Tag *tag1, if (rf_index1 > rf_index2) return 1; + int mm_index1 = tag1->minMaxIndex(); + int mm_index2 = tag2->minMaxIndex(); + if (mm_index1 < mm_index2) + return -1; + if (mm_index1 > mm_index2) + return 1; + bool is_clk1 = tag1->isClock(); bool is_clk2 = tag2->isClock(); if (!is_clk1 && is_clk2) @@ -363,8 +365,8 @@ Tag::cmp(const Tag *tag1, bool Tag::equal(const Tag *tag1, - const Tag *tag2, - const StaState *sta) + const Tag *tag2, + const StaState *sta) { return cmp(tag1, tag2, sta) == 0; } @@ -373,7 +375,7 @@ Tag::equal(const Tag *tag1, bool TagIndexLess::operator()(const Tag *tag1, - const Tag *tag2) const + const Tag *tag2) const { return tag1->index() < tag2->index(); } @@ -381,7 +383,7 @@ TagIndexLess::operator()(const Tag *tag1, //////////////////////////////////////////////////////////////// TagMatchLess::TagMatchLess(bool match_crpr_clk_pin, - const StaState *sta) : + const StaState *sta) : match_crpr_clk_pin_(match_crpr_clk_pin), sta_(sta) { @@ -389,7 +391,7 @@ TagMatchLess::TagMatchLess(bool match_crpr_clk_pin, bool TagMatchLess::operator()(const Tag *tag1, - const Tag *tag2) const + const Tag *tag2) const { return Tag::matchCmp(tag1, tag2, match_crpr_clk_pin_, sta_) < 0; } @@ -398,30 +400,37 @@ TagMatchLess::operator()(const Tag *tag1, bool Tag::match(const Tag *tag1, - const Tag *tag2, - const StaState *sta) + const Tag *tag2, + const StaState *sta) { return Tag::matchCmp(tag1, tag2, true, sta) == 0; } bool Tag::match(const Tag *tag1, - const Tag *tag2, - bool match_crpr_clk_pin, - const StaState *sta) + const Tag *tag2, + bool match_crpr_clk_pin, + const StaState *sta) { return Tag::matchCmp(tag1, tag2, match_crpr_clk_pin, sta) == 0; } int Tag::matchCmp(const Tag *tag1, - const Tag *tag2, - bool match_crpr_clk_pin, - const StaState *sta) + const Tag *tag2, + bool match_crpr_clk_pin, + const StaState *sta) { if (tag1 == tag2) return 0; + size_t scene_index1 = tag1->scene()->index(); + size_t scene_index2 = tag2->scene()->index(); + if (scene_index1 < scene_index2) + return -1; + else if (scene_index1 > scene_index2) + return 1; + int rf_index1 = tag1->rfIndex(); int rf_index2 = tag2->rfIndex(); if (rf_index1 < rf_index2) @@ -429,11 +438,11 @@ Tag::matchCmp(const Tag *tag1, if (rf_index1 > rf_index2) return 1; - PathAPIndex path_ap_index1 = tag1->pathAPIndex(); - PathAPIndex path_ap_index2 = tag2->pathAPIndex(); - if (path_ap_index1 < path_ap_index2) + int mm_index1 = tag1->minMaxIndex(); + int mm_index2 = tag2->minMaxIndex(); + if (mm_index1 < mm_index2) return -1; - if (path_ap_index1 > path_ap_index2) + if (mm_index1 > mm_index2) return 1; const ClkInfo *clk_info1 = tag1->clkInfo(); @@ -468,8 +477,7 @@ Tag::matchCmp(const Tag *tag1, if (is_segment_start1 && !is_segment_start2) return 1; - if (match_crpr_clk_pin - && sta->crprActive()) { + if (match_crpr_clk_pin) { VertexId crpr_vertex1 = clk_info1->crprClkVertexId(sta); VertexId crpr_vertex2 = clk_info2->crprClkVertexId(sta); if (crpr_vertex1 < crpr_vertex2) @@ -483,54 +491,59 @@ Tag::matchCmp(const Tag *tag1, bool Tag::matchNoCrpr(const Tag *tag1, - const Tag *tag2) + const Tag *tag2) { const ClkInfo *clk_info1 = tag1->clkInfo(); const ClkInfo *clk_info2 = tag2->clkInfo(); return tag1 == tag2 - || (clk_info1->clkEdge() == clk_info2->clkEdge() - && tag1->rfIndex() == tag2->rfIndex() - && tag1->pathAPIndex() == tag2->pathAPIndex() - && tag1->isClock() == tag2->isClock() - && clk_info1->isGenClkSrcPath() == clk_info2->isGenClkSrcPath() - && Tag::stateEqual(tag1, tag2)); + || (tag1->scene() == tag2->scene() + && clk_info1->clkEdge() == clk_info2->clkEdge() + && tag1->rfIndex() == tag2->rfIndex() + && tag1->minMaxIndex() == tag2->minMaxIndex() + && tag1->isClock() == tag2->isClock() + && clk_info1->isGenClkSrcPath() == clk_info2->isGenClkSrcPath() + && Tag::stateEqual(tag1, tag2)); } bool Tag::matchNoPathAp(const Tag *tag1, - const Tag *tag2) + const Tag *tag2) { const ClkInfo *clk_info1 = tag1->clkInfo(); const ClkInfo *clk_info2 = tag2->clkInfo(); return tag1 == tag2 - || (clk_info1->clkEdge() == clk_info2->clkEdge() - && tag1->rfIndex() == tag2->rfIndex() - && tag1->isClock() == tag2->isClock() - && tag1->isSegmentStart() == tag2->isSegmentStart() - && clk_info1->isGenClkSrcPath() == clk_info2->isGenClkSrcPath() - && Tag::stateEqual(tag1, tag2)); + || (tag1->scene() == tag2->scene() + && clk_info1->clkEdge() == clk_info2->clkEdge() + && tag1->rfIndex() == tag2->rfIndex() + // min_max not matched + && tag1->isClock() == tag2->isClock() + && tag1->isSegmentStart() == tag2->isSegmentStart() + && clk_info1->isGenClkSrcPath() == clk_info2->isGenClkSrcPath() + && Tag::stateEqual(tag1, tag2)); } bool Tag::matchCrpr(const Tag *tag1, - const Tag *tag2) + const Tag *tag2) { const ClkInfo *clk_info1 = tag1->clkInfo(); const ClkInfo *clk_info2 = tag2->clkInfo(); return tag1 == tag2 - || (clk_info1->clkEdge() == clk_info2->clkEdge() - && tag1->rfIndex() == tag2->rfIndex() - && tag1->isClock() == tag2->isClock() - && tag1->isSegmentStart() == tag2->isSegmentStart() - && clk_info1->isGenClkSrcPath() == clk_info2->isGenClkSrcPath() - && stateEqualCrpr(tag1, tag2)); + || (tag1->scene() == tag2->scene() + && clk_info1->clkEdge() == clk_info2->clkEdge() + && tag1->rfIndex() == tag2->rfIndex() + // min_max not matched + && tag1->isClock() == tag2->isClock() + && tag1->isSegmentStart() == tag2->isSegmentStart() + && clk_info1->isGenClkSrcPath() == clk_info2->isGenClkSrcPath() + && stateEqualCrpr(tag1, tag2)); } //////////////////////////////////////////////////////////////// int Tag::stateCmp(const Tag *tag1, - const Tag *tag2) + const Tag *tag2) { ExceptionStateSet *states1 = tag1->states(); ExceptionStateSet *states2 = tag2->states(); @@ -553,23 +566,24 @@ Tag::stateCmp(const Tag *tag1, if (state_size1 > state_size2) return 1; - ExceptionStateSet::Iterator state_iter1(states1); - ExceptionStateSet::Iterator state_iter2(states2); - while (state_iter1.hasNext() - && state_iter2.hasNext()) { - ExceptionState *state1 = state_iter1.next(); - ExceptionState *state2 = state_iter2.next(); - if (exceptionStateLess(state1, state2)) - return -1; - if (exceptionStateLess(state2, state1)) - return 1; + auto iter1 = states1->begin(); + auto iter2 = states2->begin(); + while (iter1 != states1->end() + && iter2 != states2->end()) { + ExceptionState *state1 = *iter1; + ExceptionState *state2 = *iter2; + int state_cmp = exceptionStateCmp(state1, state2); + if (state_cmp != 0) + return state_cmp; + ++iter1; + ++iter2; } return 0; } bool Tag::stateEqual(const Tag *tag1, - const Tag *tag2) + const Tag *tag2) { return stateCmp(tag1, tag2) == 0; } @@ -577,37 +591,43 @@ Tag::stateEqual(const Tag *tag1, // Match loop exception states only for crpr min/max paths. bool Tag::stateEqualCrpr(const Tag *tag1, - const Tag *tag2) + const Tag *tag2) { ExceptionStateSet *states1 = tag1->states(); ExceptionStateSet *states2 = tag2->states(); - ExceptionStateSet::Iterator state_iter1(states1); - ExceptionStateSet::Iterator state_iter2(states2); - ExceptionState *state1, *state2; - do { - state1 = nullptr; - while (state_iter1.hasNext()) { - state1 = state_iter1.next(); - ExceptionPath *exception1 = state1->exception(); - if (exception1->isLoop()) - break; - else - state1 = nullptr; - } - state2 = nullptr; - while (state_iter2.hasNext()) { - state2 = state_iter2.next(); - ExceptionPath *exception2 = state2->exception(); - if (exception2->isLoop()) - break; - else - state2 = nullptr; - } - if (state1 != state2) - return false; - } while (state1 && state2); - return state1 == nullptr - && state2 == nullptr; + if (states1 && states2) { + auto iter1 = states1->begin(); + auto iter2 = states2->begin(); + ExceptionState *state1, *state2; + do { + state1 = nullptr; + while (iter1 != states1->end()) { + state1 = *iter1; + ++iter1; + ExceptionPath *exception1 = state1->exception(); + if (exception1->isLoop()) + break; + else + state1 = nullptr; + } + state2 = nullptr; + while (iter2 != states2->end()) { + state2 = *iter2; + ++iter2; + ExceptionPath *exception2 = state2->exception(); + if (exception2->isLoop()) + break; + else + state2 = nullptr; + } + if (state1 != state2) + return false; + } while (state1 && state2); + return state1 == nullptr + && state2 == nullptr; + } + else + return true; } //////////////////////////////////////////////////////////////// @@ -620,8 +640,7 @@ TagHash::TagHash(const StaState *sta) : size_t TagHash::operator()(const Tag *tag) const { - bool crpr_on = sta_->crprActive(); - return tag->matchHash(crpr_on, sta_); + return tag->matchHash(true, sta_); } TagEqual::TagEqual(const StaState *sta) : @@ -631,13 +650,13 @@ TagEqual::TagEqual(const StaState *sta) : bool TagEqual::operator()(const Tag *tag1, - const Tag *tag2) const + const Tag *tag2) const { return Tag::equal(tag1, tag2, sta_); } TagMatchHash::TagMatchHash(bool match_crpr_clk_pin, - const StaState *sta) : + const StaState *sta) : match_crpr_clk_pin_(match_crpr_clk_pin), sta_(sta) { @@ -650,7 +669,7 @@ TagMatchHash::operator()(const Tag *tag) const } TagMatchEqual::TagMatchEqual(bool match_crpr_clk_pin, - const StaState *sta) : + const StaState *sta) : match_crpr_clk_pin_(match_crpr_clk_pin), sta_(sta) { @@ -658,7 +677,7 @@ TagMatchEqual::TagMatchEqual(bool match_crpr_clk_pin, bool TagMatchEqual::operator()(const Tag *tag1, - const Tag *tag2) const + const Tag *tag2) const { return Tag::match(tag1, tag2, match_crpr_clk_pin_, sta_); } diff --git a/search/Tag.hh b/search/Tag.hh index e084bd29..1b24c190 100644 --- a/search/Tag.hh +++ b/search/Tag.hh @@ -24,12 +24,11 @@ #pragma once -#include "Vector.hh" -#include "Set.hh" #include "Transition.hh" #include "SdcClass.hh" #include "SearchClass.hh" #include "Path.hh" +#include "Scene.hh" namespace sta { @@ -51,21 +50,22 @@ namespace sta { class Tag { public: - Tag(TagIndex index, - int rf_index, - PathAPIndex path_ap_index, + Tag(Scene *scene, + TagIndex index, + const RiseFall *rf, + const MinMax *min_max, const ClkInfo *clk_info, bool is_clk, InputDelay *input_delay, bool is_segment_start, ExceptionStateSet *states, - bool own_states, - const StaState *sta); + bool own_states); ~Tag(); std::string to_string(const StaState *sta) const; std::string to_string(bool report_index, bool report_rf_min_max, const StaState *sta) const; + Scene *scene() const { return scene_; } const ClkInfo *clkInfo() const { return clk_info_; } bool isClock() const { return is_clk_; } const ClockEdge *clkEdge() const; @@ -73,60 +73,60 @@ public: const Pin *clkSrc() const; int rfIndex() const { return rf_index_; } const RiseFall *transition() const; - const MinMax *minMax(const StaState *sta) const; - PathAnalysisPt *pathAnalysisPt(const StaState *sta) const; - PathAPIndex pathAPIndex() const { return path_ap_index_; } + const MinMax *minMax() const; + int minMaxIndex() const { return min_max_index_; } TagIndex index() const { return index_; } ExceptionStateSet *states() const { return states_; } void setStates(ExceptionStateSet *states); bool isGenClkSrcPath() const; - const Clock *genClkSrcPathClk(const StaState *sta) const; + const Clock *genClkSrcPathClk() const; // Input delay at search startpoint (not propagated). InputDelay *inputDelay() const { return input_delay_; } bool isLoop() const { return is_loop_; } bool isFilter() const { return is_filter_; } bool isSegmentStart() const { return is_segment_start_; } size_t hash(bool match_crpr_clk_pin, - const StaState *sta) const; + const StaState *sta) const; size_t matchHash(bool match_crpr_clk_pin, const StaState *sta) const; static int cmp(const Tag *tag1, - const Tag *tag2, - const StaState *sta); + const Tag *tag2, + const StaState *sta); static int matchCmp(const Tag *tag1, - const Tag *tag2, - bool match_clk_clk_pin, - const StaState *sta); + const Tag *tag2, + bool match_clk_clk_pin, + const StaState *sta); static bool match(const Tag *tag1, - const Tag *tag2, - bool match_crpr_clk_pin, - const StaState *sta); + const Tag *tag2, + bool match_crpr_clk_pin, + const StaState *sta); static bool equal(const Tag *tag1, - const Tag *tag2, - const StaState *sta); + const Tag *tag2, + const StaState *sta); static bool matchNoPathAp(const Tag *tag1, - const Tag *tag2); + const Tag *tag2); static bool matchCrpr(const Tag *tag1, - const Tag *tag2); + const Tag *tag2); static bool matchNoCrpr(const Tag *tag1, - const Tag *tag2); + const Tag *tag2); protected: void findHash(); // Match tag clock edge, clock driver and exception states but not clk info. static bool match(const Tag *tag1, - const Tag *tag2, - const StaState *sta); + const Tag *tag2, + const StaState *sta); static bool stateEqual(const Tag *tag1, - const Tag *tag2); + const Tag *tag2); static int stateCmp(const Tag *tag1, - const Tag *tag2); + const Tag *tag2); static bool stateEqualCrpr(const Tag *tag1, - const Tag *tag2); + const Tag *tag2); private: + Scene *scene_; const ClkInfo *clk_info_; InputDelay *input_delay_; ExceptionStateSet *states_; @@ -140,7 +140,7 @@ private: // Indicates that states_ is owned by the tag. bool own_states_:1; unsigned int rf_index_:RiseFall::index_bit_count; - unsigned int path_ap_index_:path_ap_index_bit_count; + unsigned int min_max_index_:MinMax::index_bit_count; }; class TagLess @@ -148,7 +148,7 @@ class TagLess public: TagLess(const StaState *sta); bool operator()(const Tag *tag1, - const Tag *tag2) const; + const Tag *tag2) const; private: const StaState *sta_; @@ -158,7 +158,7 @@ class TagIndexLess { public: bool operator()(const Tag *tag1, - const Tag *tag2) const; + const Tag *tag2) const; }; class TagHash @@ -176,7 +176,7 @@ class TagEqual public: TagEqual(const StaState *sta); bool operator()(const Tag *tag1, - const Tag *tag2) const; + const Tag *tag2) const; private: const StaState *sta_; diff --git a/search/TagGroup.cc b/search/TagGroup.cc index 2496ef11..93e0251e 100644 --- a/search/TagGroup.cc +++ b/search/TagGroup.cc @@ -27,22 +27,21 @@ #include "Report.hh" #include "Debug.hh" #include "Graph.hh" -#include "PathAnalysisPt.hh" #include "ClkInfo.hh" #include "Tag.hh" -#include "Corner.hh" +#include "Scene.hh" #include "Search.hh" #include "Path.hh" namespace sta { TagGroup::TagGroup(TagGroupIndex index, - PathIndexMap *path_index_map, - bool has_clk_tag, - bool has_genclk_src_tag, - bool has_filter_tag, - bool has_loop_tag, - const StaState *sta) : + PathIndexMap *path_index_map, + bool has_clk_tag, + bool has_genclk_src_tag, + bool has_filter_tag, + bool has_loop_tag, + const StaState *sta) : path_index_map_(path_index_map), hash_(hash(path_index_map, sta)), ref_count_(0), @@ -56,7 +55,7 @@ TagGroup::TagGroup(TagGroupIndex index, } TagGroup::TagGroup(TagGroupBldr *tag_bldr, - const StaState *sta) : + const StaState *sta) : path_index_map_(&tag_bldr->pathIndexMap()), hash_(hash(path_index_map_, sta)), ref_count_(0), @@ -84,28 +83,30 @@ TagGroup::decrRefCount() size_t TagGroup::hash(PathIndexMap *path_index_map, - const StaState *sta) + const StaState *sta) { - bool crpr_on = sta->crprActive(); size_t hash = 0; for (auto const [tag, path_index] : *path_index_map) - hash += tag->hash(crpr_on, sta); + hash += tag->hash(true, sta); return hash; } bool TagGroup::hasTag(Tag *tag) const { - return path_index_map_->hasKey(tag); + return path_index_map_->contains(tag); } size_t TagGroup::pathIndex(Tag *tag) const { - size_t path_index = 0; + size_t path_index; bool exists; - pathIndex(tag, path_index, exists); - return path_index; + findKeyValue(path_index_map_, tag, path_index, exists); + if (exists) + return path_index; + else + return 0; } void @@ -113,7 +114,7 @@ TagGroup::pathIndex(Tag *tag, size_t &path_index, bool &exists) const { - path_index_map_->findKey(tag, path_index, exists); + findKeyValue(path_index_map_, tag, path_index, exists); } void @@ -145,8 +146,8 @@ pathIndexMapReport(const PathIndexMap *path_index_map, //////////////////////////////////////////////////////////////// TagGroupBldr::TagGroupBldr(bool match_crpr_clk_pin, - const StaState *sta) : - default_path_count_(sta->corners()->count() + const StaState *sta) : + default_path_count_(sta->scenes().size() * RiseFall::index_count * MinMax::index_count), path_index_map_(TagMatchLess(match_crpr_clk_pin, sta)), @@ -203,8 +204,7 @@ TagGroupBldr::tagMatchPath(Tag *tag, // Match is not necessarily equal to original tag because it // must only satisfy tagMatch. bool exists; - Tag *tag_match; - path_index_map_.findKey(tag, tag_match, path_index, exists); + findKeyValue(path_index_map_, tag, path_index, exists); if (exists) match = &paths_[path_index]; else { @@ -221,7 +221,7 @@ TagGroupBldr::arrival(size_t path_index) const void TagGroupBldr::setArrival(Tag *tag, - const Arrival &arrival) + const Arrival &arrival) { // Find matching group tag (not necessarily equal to original tag). Path *match; @@ -245,7 +245,7 @@ TagGroupBldr::setMatchPath(Path *match, if (tag_match != tag) { // Replace tag in arrival map. path_index_map_.erase(tag_match); - path_index_map_.insert(tag, path_index); + path_index_map_[tag] = path_index; } paths_[path_index].init(vertex_, tag, arrival, prev_path, prev_edge, prev_arc, sta_); @@ -263,7 +263,7 @@ TagGroupBldr::insertPath(Tag *tag, { size_t path_index = paths_.size(); - path_index_map_.insert(tag, path_index); + path_index_map_[tag] = path_index; paths_.emplace_back(vertex_, tag, arrival, prev_path, prev_edge, prev_arc, sta_); @@ -289,11 +289,11 @@ TagGroupBldr::insertPath(const Path &path) TagGroup * TagGroupBldr::makeTagGroup(TagGroupIndex index, - const StaState *sta) + const StaState *sta) { return new TagGroup(index, makePathIndexMap(sta), - has_clk_tag_, has_genclk_src_tag_, has_filter_tag_, - has_loop_tag_, sta); + has_clk_tag_, has_genclk_src_tag_, has_filter_tag_, + has_loop_tag_, sta); } @@ -301,10 +301,9 @@ PathIndexMap * TagGroupBldr::makePathIndexMap(const StaState *sta) { PathIndexMap *path_index_map = new PathIndexMap(TagMatchLess(true, sta)); - size_t path_index = 0; for (auto const [tag, path_index1] : path_index_map_) { - path_index_map->insert(tag, path_index); + (*path_index_map)[tag] = path_index; path_index++; } return path_index_map; @@ -339,12 +338,8 @@ pathIndexMapEqual(const PathIndexMap *path_index_map1, { if (path_index_map1->size() == path_index_map2->size()) { for (auto const [tag1, path_index1] : *path_index_map1) { - Tag *tag2; - size_t path_index2; - bool exists2; - path_index_map2->findKey(tag1, tag2, path_index2, exists2); - if (!exists2) - return false; + if (!path_index_map2->contains(tag1)) + return false; } return true; } @@ -354,11 +349,11 @@ pathIndexMapEqual(const PathIndexMap *path_index_map1, bool TagGroupEqual::operator()(const TagGroup *tag_group1, - const TagGroup *tag_group2) const + const TagGroup *tag_group2) const { return tag_group1 == tag_group2 || (tag_group1->hash() == tag_group2->hash() - && pathIndexMapEqual(tag_group1->pathIndexMap(), + && pathIndexMapEqual(tag_group1->pathIndexMap(), tag_group2->pathIndexMap())); } diff --git a/search/TagGroup.hh b/search/TagGroup.hh index 88722d5f..2a02f2b9 100644 --- a/search/TagGroup.hh +++ b/search/TagGroup.hh @@ -26,9 +26,6 @@ #include -#include "Vector.hh" -#include "Map.hh" -#include "Iterator.hh" #include "MinMax.hh" #include "Transition.hh" #include "GraphClass.hh" @@ -43,15 +40,15 @@ class TagGroup { public: TagGroup(TagGroupIndex index, - PathIndexMap *path_index_map, - bool has_clk_tag, - bool has_genclk_src_tag, - bool has_filter_tag, - bool has_loop_tag, - const StaState *sta); + PathIndexMap *path_index_map, + bool has_clk_tag, + bool has_genclk_src_tag, + bool has_filter_tag, + bool has_loop_tag, + const StaState *sta); // For Search::findTagGroup to probe. TagGroup(TagGroupBldr *tag_bldr, - const StaState *sta); + const StaState *sta); ~TagGroup(); TagGroupIndex index() const { return index_; } size_t hash() const { return hash_; } @@ -75,7 +72,7 @@ public: protected: static size_t hash(PathIndexMap *path_index_map, - const StaState *sta); + const StaState *sta); // tag -> path index PathIndexMap *path_index_map_; @@ -99,7 +96,7 @@ class TagGroupEqual { public: bool operator()(const TagGroup *group1, - const TagGroup *group2) const; + const TagGroup *group2) const; }; // Incremental tag group used to build tag group and associated @@ -108,12 +105,12 @@ class TagGroupBldr { public: TagGroupBldr(bool match_crpr_clk_pin, - const StaState *sta); + const StaState *sta); void init(Vertex *vertex); bool empty(); void reportArrivalEntries() const; TagGroup *makeTagGroup(TagGroupIndex index, - const StaState *sta); + const StaState *sta); size_t pathCount() const { return path_index_map_.size();; } bool hasClkTag() const { return has_clk_tag_; } bool hasGenClkSrcTag() const { return has_genclk_src_tag_; } @@ -128,7 +125,7 @@ public: Arrival arrival(size_t path_index) const; // prev_path == hull void setArrival(Tag *tag, - const Arrival &arrival); + const Arrival &arrival); void setMatchPath(Path *match, size_t path_index, Tag *tag, diff --git a/search/VisitPathEnds.cc b/search/VisitPathEnds.cc index b5a762d5..52859010 100644 --- a/search/VisitPathEnds.cc +++ b/search/VisitPathEnds.cc @@ -31,15 +31,17 @@ #include "ExceptionPath.hh" #include "PortDelay.hh" #include "Sdc.hh" +#include "Mode.hh" #include "Graph.hh" #include "ClkInfo.hh" #include "Tag.hh" #include "Path.hh" -#include "PathAnalysisPt.hh" #include "PathEnd.hh" #include "Search.hh" #include "GatedClk.hh" +#include "Sim.hh" #include "Variables.hh" +#include "Scene.hh" namespace sta { @@ -50,17 +52,17 @@ VisitPathEnds::VisitPathEnds(const StaState *sta) : void VisitPathEnds::visitPathEnds(Vertex *vertex, - PathEndVisitor *visitor) + PathEndVisitor *visitor) { - visitPathEnds(vertex, nullptr, MinMaxAll::all(), false, visitor); + visitPathEnds(vertex, Scene::sceneSet(scenes_), MinMaxAll::all(), false, visitor); } void VisitPathEnds::visitPathEnds(Vertex *vertex, - const Corner *corner, - const MinMaxAll *min_max, - bool filtered, - PathEndVisitor *visitor) + const SceneSet &scenes, + const MinMaxAll *min_max, + bool filtered, + PathEndVisitor *visitor) { // Ignore slack on bidirect driver vertex. The load vertex gets the slack. if (!vertex->isBidirectDriver()) { @@ -69,115 +71,115 @@ VisitPathEnds::visitPathEnds(Vertex *vertex, vertex->to_string(this).c_str()); visitor->vertexBegin(vertex); bool is_constrained = false; - visitClkedPathEnds(pin, vertex, corner, min_max, filtered, visitor, - is_constrained); + visitClkedPathEnds(pin, vertex, scenes, min_max, filtered, visitor, + is_constrained); if (search_->unconstrainedPaths() - && !is_constrained - && !vertex->isDisabledConstraint()) - visitUnconstrainedPathEnds(pin, vertex, corner, min_max, filtered, - visitor); + && !is_constrained) + visitUnconstrainedPathEnds(pin, vertex, scenes, min_max, filtered, + visitor); visitor->vertexEnd(vertex); } } void VisitPathEnds::visitClkedPathEnds(const Pin *pin, - Vertex *vertex, - const Corner *corner, - const MinMaxAll *min_max, - bool filtered, - PathEndVisitor *visitor, - bool &is_constrained) + Vertex *vertex, + const SceneSet &scenes, + const MinMaxAll *min_max, + bool filtered, + PathEndVisitor *visitor, + bool &is_constrained) { - bool is_segment_start = search_->isSegmentStart(pin); VertexPathIterator path_iter(vertex, this); while (path_iter.hasNext()) { Path *path = path_iter.next(); - PathAnalysisPt *path_ap = path->pathAnalysisPt(this); - const MinMax *path_min_max = path_ap->pathMinMax(); + const MinMax *path_min_max = path->minMax(this); const RiseFall *end_rf = path->transition(this); Tag *tag = path->tag(this); - if ((corner == nullptr - || path_ap->corner() == corner) - && min_max->matches(path_min_max) - // Ignore generated clock source paths. - && !path->clkInfo(this)->isGenClkSrcPath() - && !falsePathTo(path, pin, end_rf, path_min_max) - // Ignore segment startpoint paths. - && (!is_segment_start - || !tag->isSegmentStart())) { + const Mode *mode = path->mode(this); + const Sdc *sdc = mode->sdc(); + Scene *scene = path->scene(this); + if (scenes.contains(scene) + && min_max->matches(path_min_max) + // Ignore generated clock source paths. + && !path->clkInfo(this)->isGenClkSrcPath() + && !falsePathTo(path, pin, end_rf, path_min_max) + // Ignore segment startpoint paths. + && !tag->isSegmentStart()) { // set_output_delay to timing check has precedence. - if (sdc_->hasOutputDelay(pin)) - visitOutputDelayEnd(pin, path, end_rf, path_ap, filtered, visitor, - is_constrained); + if (sdc->hasOutputDelay(pin)) + visitOutputDelayEnd(pin, path, end_rf, filtered, visitor, + is_constrained); else if (vertex->hasChecks()) - visitCheckEnd(pin, vertex, path, end_rf, path_ap, filtered, visitor, - is_constrained); + visitCheckEnd(pin, vertex, path, end_rf, filtered, visitor, + is_constrained); else if (!filtered || search_->matchesFilter(path, nullptr)) { - PathDelay *path_delay = pathDelayTo(path, pin, end_rf, path_min_max); - if (path_delay) { - PathEndPathDelay path_end(path_delay, path, this); - visitor->visit(&path_end); - is_constrained = true; - } + PathDelay *path_delay = pathDelayTo(path, pin, end_rf, path_min_max); + if (path_delay) { + PathEndPathDelay path_end(path_delay, path, this); + visitor->visit(&path_end); + is_constrained = true; + } } if (variables_->gatedClkChecksEnabled()) - visitGatedClkEnd(pin, vertex, path, end_rf, path_ap, filtered, visitor, - is_constrained); - visitDataCheckEnd(pin, path, end_rf, path_ap, filtered, visitor, - is_constrained); + visitGatedClkEnd(pin, vertex, path, end_rf, filtered, visitor, + is_constrained); + visitDataCheckEnd(pin, path, end_rf, filtered, visitor, + is_constrained); } } } void VisitPathEnds::visitCheckEnd(const Pin *pin, - Vertex *vertex, - Path *path, - const RiseFall *end_rf, - const PathAnalysisPt *path_ap, - bool filtered, - PathEndVisitor *visitor, - bool &is_constrained) + Vertex *vertex, + Path *path, + const RiseFall *end_rf, + bool filtered, + PathEndVisitor *visitor, + bool &is_constrained) { const ClockEdge *src_clk_edge = path->clkEdge(this); const Clock *src_clk = path->clock(this); - const MinMax *min_max = path_ap->pathMinMax(); - const PathAnalysisPt *tgt_clk_path_ap = path_ap->tgtClkAnalysisPt(); + const MinMax *min_max = path->minMax(this); + const MinMax *tgt_min_max = path->tgtClkMinMax(this); bool check_clked = false; + const Scene *scene = path->scene(this); + const Mode *mode = scene->mode(); + const Sdc *sdc = scene->sdc(); VertexInEdgeIterator edge_iter(vertex, graph_); while (edge_iter.hasNext()) { Edge *edge = edge_iter.next(); Vertex *tgt_clk_vertex = edge->from(graph_); const TimingRole *check_role = edge->role(); - if (checkEdgeEnabled(edge) - && check_role->pathMinMax() == min_max) { + if (checkEdgeEnabled(edge, mode) + && check_role->pathMinMax() == min_max) { TimingArcSet *arc_set = edge->timingArcSet(); for (TimingArc *check_arc : arc_set->arcs()) { - const RiseFall *clk_rf = check_arc->fromEdge()->asRiseFall(); - if (check_arc->toEdge()->asRiseFall() == end_rf - && clk_rf) { - VertexPathIterator tgt_clk_path_iter(tgt_clk_vertex, clk_rf, - tgt_clk_path_ap, this); - while (tgt_clk_path_iter.hasNext()) { - Path *tgt_clk_path = tgt_clk_path_iter.next(); - const ClkInfo *tgt_clk_info = tgt_clk_path->clkInfo(this); - const ClockEdge *tgt_clk_edge = tgt_clk_path->clkEdge(this); - const Clock *tgt_clk = tgt_clk_path->clock(this); - const Pin *tgt_pin = tgt_clk_vertex->pin(); - ExceptionPath *exception = exceptionTo(path, pin, end_rf, - tgt_clk_edge, min_max); - // Ignore generated clock source paths. - if (!tgt_clk_info->isGenClkSrcPath() + const RiseFall *clk_rf = check_arc->fromEdge()->asRiseFall(); + if (check_arc->toEdge()->asRiseFall() == end_rf + && clk_rf) { + VertexPathIterator tgt_clk_path_iter(tgt_clk_vertex, scene, + tgt_min_max, clk_rf, this); + while (tgt_clk_path_iter.hasNext()) { + Path *tgt_clk_path = tgt_clk_path_iter.next(); + const ClkInfo *tgt_clk_info = tgt_clk_path->clkInfo(this); + const ClockEdge *tgt_clk_edge = tgt_clk_path->clkEdge(this); + const Clock *tgt_clk = tgt_clk_path->clock(this); + const Pin *tgt_pin = tgt_clk_vertex->pin(); + ExceptionPath *exception = exceptionTo(path, pin, end_rf, + tgt_clk_edge, min_max); + // Ignore generated clock source paths. + if (!tgt_clk_info->isGenClkSrcPath() && tgt_clk_path->isClock(this)) { check_clked = true; if (!filtered || search_->matchesFilter(path, tgt_clk_edge)) { if (src_clk_edge - && tgt_clk != sdc_->defaultArrivalClock() - && sdc_->sameClockGroup(src_clk, tgt_clk) - && !sdc_->clkStopPropagation(tgt_pin, tgt_clk) + && tgt_clk != sdc->defaultArrivalClock() + && sdc->sameClockGroup(src_clk, tgt_clk) + && !sdc->clkStopPropagation(tgt_pin, tgt_clk) // False paths and path delays override // paths. && (exception == nullptr @@ -203,8 +205,7 @@ VisitPathEnds::visitCheckEnd(const Pin *pin, else if (exception && exception->isPathDelay() && (src_clk == nullptr - || sdc_->sameClockGroup(src_clk, - tgt_clk))) { + || sdc->sameClockGroup(src_clk, tgt_clk))) { PathDelay *path_delay = dynamic_cast(exception); if (network_->isLatchData(pin) && check_role == TimingRole::setup()) { @@ -221,113 +222,117 @@ VisitPathEnds::visitCheckEnd(const Pin *pin, } } } - } - } - } + } + } + } } } } if (!check_clked) - visitCheckEndUnclked(pin, vertex, path, end_rf, path_ap, filtered, - visitor, is_constrained); + visitCheckEndUnclked(pin, vertex, path, end_rf, filtered, + visitor, is_constrained); } void VisitPathEnds::visitCheckEndUnclked(const Pin *pin, - Vertex *vertex, - Path *path, - const RiseFall *end_rf, - const PathAnalysisPt *path_ap, - bool filtered, - PathEndVisitor *visitor, - bool &is_constrained) + Vertex *vertex, + Path *path, + const RiseFall *end_rf, + bool filtered, + PathEndVisitor *visitor, + bool &is_constrained) { - const MinMax *min_max = path_ap->pathMinMax(); + const Mode *mode = path->mode(this); + const MinMax *min_max = path->minMax(this); VertexInEdgeIterator edge_iter(vertex, graph_); while (edge_iter.hasNext()) { Edge *edge = edge_iter.next(); const TimingRole *check_role = edge->role(); - if (checkEdgeEnabled(edge) - && check_role->pathMinMax() == min_max) { + if (checkEdgeEnabled(edge, mode) + && check_role->pathMinMax() == min_max) { TimingArcSet *arc_set = edge->timingArcSet(); for (TimingArc *check_arc : arc_set->arcs()) { - const RiseFall *clk_rf = check_arc->fromEdge()->asRiseFall(); - if (check_arc->toEdge()->asRiseFall() == end_rf - && clk_rf - && (!filtered - || search_->matchesFilter(path, nullptr))) { - ExceptionPath *exception = exceptionTo(path, pin, end_rf, - nullptr, min_max); - // False paths and path delays override multicycle paths. - if (exception - && exception->isPathDelay()) { - PathDelay *path_delay = dynamic_cast(exception); - PathEndPathDelay path_end(path_delay, path, nullptr, - check_arc, edge, this); - visitor->visit(&path_end); - is_constrained = true; - } - } + const RiseFall *clk_rf = check_arc->fromEdge()->asRiseFall(); + if (check_arc->toEdge()->asRiseFall() == end_rf + && clk_rf + && (!filtered + || search_->matchesFilter(path, nullptr))) { + ExceptionPath *exception = exceptionTo(path, pin, end_rf, + nullptr, min_max); + // False paths and path delays override multicycle paths. + if (exception + && exception->isPathDelay()) { + PathDelay *path_delay = dynamic_cast(exception); + PathEndPathDelay path_end(path_delay, path, nullptr, + check_arc, edge, this); + visitor->visit(&path_end); + is_constrained = true; + } + } } } } } bool -VisitPathEnds::checkEdgeEnabled(Edge *edge) const +VisitPathEnds::checkEdgeEnabled(const Edge *edge, + const Mode *mode) const { const TimingRole *check_role = edge->role(); + const Sdc *sdc = mode->sdc(); return check_role->isTimingCheck() - && search_->evalPred()->searchFrom(edge->from(graph_)) - && !edge->isDisabledConstraint() - && !edge->isDisabledCond() - && !sdc_->isDisabledCondDefault(edge) + && search_->evalPred()->searchFrom(edge->from(graph_), mode) + && !sdc->isDisabledConstraint(edge) + && !mode->sim()->isDisabledCond(edge) + && !isDisabledCondDefault(edge) && !((check_role == TimingRole::recovery() - || check_role == TimingRole::removal()) - && !variables_->recoveryRemovalChecksEnabled()); + || check_role == TimingRole::removal()) + && !variables_->recoveryRemovalChecksEnabled()); } void VisitPathEnds::visitOutputDelayEnd(const Pin *pin, - Path *path, - const RiseFall *end_rf, - const PathAnalysisPt *path_ap, - bool filtered, - PathEndVisitor *visitor, - bool &is_constrained) + Path *path, + const RiseFall *end_rf, + bool filtered, + PathEndVisitor *visitor, + bool &is_constrained) { - const MinMax *min_max = path_ap->pathMinMax(); - OutputDelaySet *output_delays = sdc_->outputDelaysLeafPin(pin); + const Scene *scene = path->scene(this); + const Sdc *sdc = scene->sdc(); + const MinMax *min_max = path->minMax(this); + OutputDelaySet *output_delays = sdc->outputDelaysLeafPin(pin); if (output_delays) { for (OutputDelay *output_delay : *output_delays) { float margin; bool exists; output_delay->delays()->value(end_rf, min_max, margin, exists); if (exists) { - const Pin *ref_pin = output_delay->refPin(); - const ClockEdge *tgt_clk_edge = output_delay->clkEdge(); - if (!filtered - || search_->matchesFilter(path, tgt_clk_edge)) { - if (ref_pin) { - Clock *tgt_clk = output_delay->clock(); - Vertex *ref_vertex = graph_->pinLoadVertex(ref_pin); - const RiseFall *ref_rf = output_delay->refTransition(); - VertexPathIterator ref_path_iter(ref_vertex,ref_rf,path_ap,this); - while (ref_path_iter.hasNext()) { - Path *ref_path = ref_path_iter.next(); - if (ref_path->isClock(this) - && (tgt_clk == nullptr - || ref_path->clock(this) == tgt_clk)) - visitOutputDelayEnd1(output_delay, pin, path, end_rf, - ref_path->clkEdge(this), ref_path, min_max, - visitor, is_constrained); - } - } - else - visitOutputDelayEnd1(output_delay, pin, path, end_rf, - tgt_clk_edge, nullptr, min_max, - visitor, is_constrained); - } + const Pin *ref_pin = output_delay->refPin(); + const ClockEdge *tgt_clk_edge = output_delay->clkEdge(); + if (!filtered + || search_->matchesFilter(path, tgt_clk_edge)) { + if (ref_pin) { + Clock *tgt_clk = output_delay->clock(); + Vertex *ref_vertex = graph_->pinLoadVertex(ref_pin); + const RiseFall *ref_rf = output_delay->refTransition(); + VertexPathIterator ref_path_iter(ref_vertex, scene, min_max, + ref_rf, this); + while (ref_path_iter.hasNext()) { + Path *ref_path = ref_path_iter.next(); + if (ref_path->isClock(this) + && (tgt_clk == nullptr + || ref_path->clock(this) == tgt_clk)) + visitOutputDelayEnd1(output_delay, pin, path, end_rf, + ref_path->clkEdge(this), ref_path, min_max, + visitor, is_constrained); + } + } + else + visitOutputDelayEnd1(output_delay, pin, path, end_rf, + tgt_clk_edge, nullptr, min_max, + visitor, is_constrained); + } } } } @@ -335,20 +340,21 @@ VisitPathEnds::visitOutputDelayEnd(const Pin *pin, void VisitPathEnds::visitOutputDelayEnd1(OutputDelay *output_delay, - const Pin *pin, - Path *path, - const RiseFall *end_rf, - const ClockEdge *tgt_clk_edge, - Path *ref_path, - const MinMax *min_max, - PathEndVisitor *visitor, - bool &is_constrained) + const Pin *pin, + Path *path, + const RiseFall *end_rf, + const ClockEdge *tgt_clk_edge, + Path *ref_path, + const MinMax *min_max, + PathEndVisitor *visitor, + bool &is_constrained) { // Target clk is not required for path delay, // but the exception may be -to clk. ExceptionPath *exception = exceptionTo(path, pin, end_rf, tgt_clk_edge, - min_max); + min_max); const ClockEdge *src_clk_edge = path->clkEdge(this); + const Sdc *sdc = path->sdc(this); if (exception && exception->isPathDelay()) { PathDelay *path_delay = dynamic_cast(exception); @@ -358,12 +364,12 @@ VisitPathEnds::visitOutputDelayEnd1(OutputDelay *output_delay, } else if (src_clk_edge && tgt_clk_edge - && sdc_->sameClockGroup(path->clock(this), tgt_clk_edge->clock()) - // False paths and path delays override. - && (exception == nullptr - || exception->isFilter() - || exception->isGroupPath() - || exception->isMultiCycle())) { + && sdc->sameClockGroup(path->clock(this), tgt_clk_edge->clock()) + // False paths and path delays override. + && (exception == nullptr + || exception->isFilter() + || exception->isGroupPath() + || exception->isMultiCycle())) { MultiCyclePath *mcp = dynamic_cast(exception); PathEndOutputDelay path_end(output_delay, path, ref_path, mcp, this); visitor->visit(&path_end); @@ -376,71 +382,77 @@ VisitPathEnds::visitOutputDelayEnd1(OutputDelay *output_delay, // Look for clock gating functions where path is the clock enable. void VisitPathEnds::visitGatedClkEnd(const Pin *pin, - Vertex *vertex, - Path *path, - const RiseFall *end_rf, - const PathAnalysisPt *path_ap, - bool filtered, - PathEndVisitor *visitor, - bool &is_constrained) + Vertex *vertex, + Path *path, + const RiseFall *end_rf, + bool filtered, + PathEndVisitor *visitor, + bool &is_constrained) { + const Scene *scene = path->scene(this); + const Sdc *sdc = scene->sdc(); const ClockEdge *src_clk_edge = path->clkEdge(this); - if (src_clk_edge) { + if (src_clk_edge + && !path->isClock(this) + && !sdc->isDisableClockGatingCheck(pin) + && !sdc->isDisableClockGatingCheck(network_->instance(pin))) { + const Mode *mode = scene->mode(); GatedClk *gated_clk = search_->gatedClk(); Clock *src_clk = src_clk_edge->clock(); bool is_gated_clk_enable; const Pin *clk_pin; LogicValue logic_active_value; - gated_clk->isGatedClkEnable(vertex, - is_gated_clk_enable, clk_pin, logic_active_value); + gated_clk->isGatedClkEnable(vertex, mode, + is_gated_clk_enable, clk_pin, logic_active_value); if (is_gated_clk_enable) { - const PathAnalysisPt *clk_path_ap = path_ap->tgtClkAnalysisPt(); - const MinMax *min_max = path_ap->pathMinMax(); + const MinMax *min_max = path->minMax(this); + const MinMax *tgt_min_max = path->tgtClkMinMax(this); Vertex *clk_vertex = graph_->pinLoadVertex(clk_pin); LogicValue active_value = - sdc_->clockGatingActiveValue(clk_pin, pin); + sdc->clockGatingActiveValue(clk_pin, pin); const RiseFall *clk_rf = - // Clock active value specified by set_clock_gating_check - // overrides the library cell function active value. - gated_clk->gatedClkActiveTrans((active_value == LogicValue::unknown) ? - logic_active_value : active_value, - min_max); - VertexPathIterator clk_path_iter(clk_vertex, clk_rf, clk_path_ap, this); + // Clock active value specified by set_clock_gating_check + // overrides the library cell function active value. + gated_clk->gatedClkActiveTrans((active_value == LogicValue::unknown) ? + logic_active_value : active_value, + min_max); + VertexPathIterator clk_path_iter(clk_vertex, scene, tgt_min_max, + clk_rf, this); while (clk_path_iter.hasNext()) { - Path *clk_path = clk_path_iter.next(); - const ClockEdge *clk_edge = clk_path->clkEdge(this); - const Clock *clk = clk_edge ? clk_edge->clock() : nullptr; - if (clk_path->isClock(this) - // Ignore unclocked paths (from path delay constraints). - && clk_edge - && clk_edge != sdc_->defaultArrivalClockEdge() - // Ignore generated clock source paths. - && !path->clkInfo(this)->isGenClkSrcPath() - && !sdc_->clkStopPropagation(pin, clk) - && clk_vertex->hasDownstreamClkPin()) { - const TimingRole *check_role = (min_max == MinMax::max()) - ? TimingRole::gatedClockSetup() - : TimingRole::gatedClockHold(); - float margin = clockGatingMargin(clk, clk_pin, - pin, end_rf, min_max); - ExceptionPath *exception = exceptionTo(path, pin, end_rf, - clk_edge, min_max); - if (sdc_->sameClockGroup(src_clk, clk) - // False paths and path delays override. - && (exception == nullptr - || exception->isFilter() - || exception->isGroupPath() - || exception->isMultiCycle()) - && (!filtered - || search_->matchesFilter(path, clk_edge))) { - MultiCyclePath *mcp = - dynamic_cast(exception); - PathEndGatedClock path_end(path, clk_path, check_role, - mcp, margin, this); - visitor->visit(&path_end); - is_constrained = true; - } - } + Path *clk_path = clk_path_iter.next(); + const ClockEdge *clk_edge = clk_path->clkEdge(this); + const Clock *clk = clk_edge ? clk_edge->clock() : nullptr; + if (clk_path->isClock(this) + // Ignore unclocked paths (from path delay constraints). + && clk_edge + && clk_edge != sdc->defaultArrivalClockEdge() + // Ignore generated clock source paths. + && !path->clkInfo(this)->isGenClkSrcPath() + && !sdc->clkStopPropagation(pin, clk) + && clk_vertex->hasDownstreamClkPin()) { + const TimingRole *check_role = (min_max == MinMax::max()) + ? TimingRole::gatedClockSetup() + : TimingRole::gatedClockHold(); + float margin = clockGatingMargin(clk, clk_pin, pin, + end_rf, min_max, sdc); + ExceptionPath *exception = exceptionTo(path, pin, end_rf, + clk_edge, min_max); + if (sdc->sameClockGroup(src_clk, clk) + // False paths and path delays override. + && (exception == nullptr + || exception->isFilter() + || exception->isGroupPath() + || exception->isMultiCycle()) + && (!filtered + || search_->matchesFilter(path, clk_edge))) { + MultiCyclePath *mcp = + dynamic_cast(exception); + PathEndGatedClock path_end(path, clk_path, check_role, + mcp, margin, this); + visitor->visit(&path_end); + is_constrained = true; + } + } } } } @@ -450,32 +462,33 @@ VisitPathEnds::visitGatedClkEnd(const Pin *pin, // Look for margin from highest precedence level to lowest. float VisitPathEnds::clockGatingMargin(const Clock *clk, - const Pin *clk_pin, - const Pin *enable_pin, - const RiseFall *enable_rf, - const SetupHold *setup_hold) + const Pin *clk_pin, + const Pin *enable_pin, + const RiseFall *enable_rf, + const SetupHold *setup_hold, + const Sdc *sdc) { bool exists; float margin; - sdc_->clockGatingMarginEnablePin(enable_pin, enable_rf, - setup_hold, exists, margin); + sdc->clockGatingMarginEnablePin(enable_pin, enable_rf, + setup_hold, exists, margin); if (exists) return margin; Instance *inst = network_->instance(enable_pin); - sdc_->clockGatingMarginInstance(inst, enable_rf, setup_hold, - exists, margin); + sdc->clockGatingMarginInstance(inst, enable_rf, setup_hold, + exists, margin); if (exists) return margin; - sdc_->clockGatingMarginClkPin(clk_pin, enable_rf, setup_hold, - exists, margin); + sdc->clockGatingMarginClkPin(clk_pin, enable_rf, setup_hold, + exists, margin); if (exists) return margin; - sdc_->clockGatingMarginClk(clk, enable_rf, setup_hold, - exists, margin); + sdc->clockGatingMarginClk(clk, enable_rf, setup_hold, + exists, margin); if (exists) return margin; - sdc_->clockGatingMargin(enable_rf, setup_hold, - exists, margin); + sdc->clockGatingMargin(enable_rf, setup_hold, + exists, margin); if (exists) return margin; else @@ -486,34 +499,31 @@ VisitPathEnds::clockGatingMargin(const Clock *clk, void VisitPathEnds::visitDataCheckEnd(const Pin *pin, - Path *path, - const RiseFall *end_rf, - const PathAnalysisPt *path_ap, - bool filtered, - PathEndVisitor *visitor, - bool &is_constrained) + Path *path, + const RiseFall *end_rf, + bool filtered, + PathEndVisitor *visitor, + bool &is_constrained) { const ClockEdge *src_clk_edge = path->clkEdge(this); if (src_clk_edge) { - DataCheckSet *checks = sdc_->dataChecksTo(pin); + const Sdc *sdc = path->sdc(this); + DataCheckSet *checks = sdc->dataChecksTo(pin); if (checks) { const Clock *src_clk = src_clk_edge->clock(); - const MinMax *min_max = path_ap->pathMinMax(); - const PathAnalysisPt *clk_ap = path_ap->tgtClkAnalysisPt(); - DataCheckSet::Iterator check_iter(checks); - while (check_iter.hasNext()) { - DataCheck *check = check_iter.next(); - const Pin *from_pin = check->from(); - Vertex *from_vertex = graph_->pinLoadVertex(from_pin); - for (auto from_rf : RiseFall::range()) { - float margin; - bool margin_exists; - check->margin(from_rf, end_rf, min_max, margin, margin_exists); - if (margin_exists) - visitDataCheckEnd1(check, pin, path, src_clk, end_rf, - min_max, clk_ap, from_pin, from_vertex, - from_rf, filtered, visitor, is_constrained); - } + const MinMax *min_max = path->minMax(this); + for (DataCheck *check : *checks) { + const Pin *from_pin = check->from(); + Vertex *from_vertex = graph_->pinLoadVertex(from_pin); + for (auto from_rf : RiseFall::range()) { + float margin; + bool margin_exists; + check->margin(from_rf, end_rf, min_max, margin, margin_exists); + if (margin_exists) + visitDataCheckEnd1(check, pin, path, src_clk, end_rf, + min_max, from_pin, from_vertex, + from_rf, filtered, visitor, is_constrained); + } } } } @@ -521,21 +531,24 @@ VisitPathEnds::visitDataCheckEnd(const Pin *pin, bool VisitPathEnds::visitDataCheckEnd1(DataCheck *check, - const Pin *pin, - Path *path, - const Clock *src_clk, - const RiseFall *end_rf, - const MinMax *min_max, - const PathAnalysisPt *clk_ap, - const Pin *from_pin, - Vertex *from_vertex, - const RiseFall *from_rf, - bool filtered, - PathEndVisitor *visitor, - bool &is_constrained) + const Pin *pin, + Path *path, + const Clock *src_clk, + const RiseFall *end_rf, + const MinMax *min_max, + const Pin *from_pin, + Vertex *from_vertex, + const RiseFall *from_rf, + bool filtered, + PathEndVisitor *visitor, + bool &is_constrained) { bool found_from_path = false; - VertexPathIterator tgt_clk_path_iter(from_vertex,from_rf,clk_ap,this); + const Scene *scene = path->scene(this); + const Sdc *sdc = scene->sdc(); + const MinMax *tgt_min_max = path->tgtClkMinMax(this); + VertexPathIterator tgt_clk_path_iter(from_vertex, scene, tgt_min_max, + from_rf,this); while (tgt_clk_path_iter.hasNext()) { Path *tgt_clk_path = tgt_clk_path_iter.next(); const ClockEdge *tgt_clk_edge = tgt_clk_path->clkEdge(this); @@ -546,19 +559,19 @@ VisitPathEnds::visitDataCheckEnd1(DataCheck *check, const Clock *tgt_clk = tgt_clk_edge->clock(); ExceptionPath *exception = exceptionTo(path, pin, end_rf, tgt_clk_edge, min_max); - if (sdc_->sameClockGroup(src_clk, tgt_clk) - && !sdc_->clkStopPropagation(from_pin, tgt_clk) - // False paths and path delays override. - && (exception == 0 - || exception->isFilter() - || exception->isGroupPath() - || exception->isMultiCycle()) - && (!filtered - || search_->matchesFilter(path, tgt_clk_edge))) { - MultiCyclePath *mcp=dynamic_cast(exception); - PathEndDataCheck path_end(check, path, tgt_clk_path, mcp, this); - visitor->visit(&path_end); - is_constrained = true; + if (sdc->sameClockGroup(src_clk, tgt_clk) + && !sdc->clkStopPropagation(from_pin, tgt_clk) + // False paths and path delays override. + && (exception == 0 + || exception->isFilter() + || exception->isGroupPath() + || exception->isMultiCycle()) + && (!filtered + || search_->matchesFilter(path, tgt_clk_edge))) { + MultiCyclePath *mcp=dynamic_cast(exception); + PathEndDataCheck path_end(check, path, tgt_clk_path, mcp, this); + visitor->visit(&path_end); + is_constrained = true; } } } @@ -569,26 +582,27 @@ VisitPathEnds::visitDataCheckEnd1(DataCheck *check, void VisitPathEnds::visitUnconstrainedPathEnds(const Pin *pin, - Vertex *vertex, - const Corner *corner, - const MinMaxAll *min_max, - bool filtered, - PathEndVisitor *visitor) + Vertex *vertex, + const SceneSet &scenes, + const MinMaxAll *min_max, + bool filtered, + PathEndVisitor *visitor) { VertexPathIterator path_iter(vertex, this); while (path_iter.hasNext()) { Path *path = path_iter.next(); - PathAnalysisPt *path_ap = path->pathAnalysisPt(this); - const MinMax *path_min_max = path_ap->pathMinMax(); - if ((corner == nullptr - || path_ap->corner() == corner) - && min_max->matches(path_min_max) - // Ignore generated clock source paths. - && !path->clkInfo(this)->isGenClkSrcPath() - && (!filtered - || search_->matchesFilter(path, nullptr)) - && !falsePathTo(path, pin, path->transition(this), - path->minMax(this))) { + const MinMax *path_min_max = path->minMax(this); + Scene *scene = path->scene(this); + const Sdc *sdc = scene->sdc(); + if (scenes.contains(scene) + && min_max->matches(path_min_max) + && !sdc->isDisabledConstraint(pin) + // Ignore generated clock source paths. + && !path->clkInfo(this)->isGenClkSrcPath() + && (!filtered + || search_->matchesFilter(path, nullptr)) + && !falsePathTo(path, pin, path->transition(this), + path_min_max)) { PathEndUnconstrained path_end(path); visitor->visit(&path_end); } @@ -599,40 +613,41 @@ VisitPathEnds::visitUnconstrainedPathEnds(const Pin *pin, bool VisitPathEnds::falsePathTo(Path *path, - const Pin *pin, - const RiseFall *rf, - const MinMax *min_max) + const Pin *pin, + const RiseFall *rf, + const MinMax *min_max) { ExceptionPath *exception = search_->exceptionTo(ExceptionPathType::false_path, path, - pin, rf, nullptr, min_max, - false, false); + pin, rf, nullptr, min_max, + false, false, path->sdc(this)); return exception != nullptr; } PathDelay * VisitPathEnds::pathDelayTo(Path *path, - const Pin *pin, - const RiseFall *rf, - const MinMax *min_max) + const Pin *pin, + const RiseFall *rf, + const MinMax *min_max) { ExceptionPath *exception = search_->exceptionTo(ExceptionPathType::path_delay, - path, pin, rf, nullptr, - min_max, false, - // Register clk pins only - // match with -to pin. - network_->isRegClkPin(pin)); + path, pin, rf, nullptr, + min_max, false, + // Register clk pins only + // match with -to pin. + network_->isRegClkPin(pin), + path->sdc(this)); return dynamic_cast(exception); } ExceptionPath * VisitPathEnds::exceptionTo(const Path *path, - const Pin *pin, - const RiseFall *rf, - const ClockEdge *clk_edge, - const MinMax *min_max) const + const Pin *pin, + const RiseFall *rf, + const ClockEdge *clk_edge, + const MinMax *min_max) const { return search_->exceptionTo(ExceptionPathType::any, path, pin, rf, clk_edge, - min_max, false, false); + min_max, false, false, path->sdc(this)); } } // namespace diff --git a/search/WorstSlack.cc b/search/WorstSlack.cc index e61fccca..cad69282 100644 --- a/search/WorstSlack.cc +++ b/search/WorstSlack.cc @@ -24,38 +24,38 @@ #include "WorstSlack.hh" +#include "ContainerHelpers.hh" #include "Debug.hh" #include "Report.hh" #include "Mutex.hh" #include "Graph.hh" -#include "Corner.hh" +#include "Scene.hh" #include "Search.hh" -#include "PathAnalysisPt.hh" namespace sta { using std::min; WorstSlacks::WorstSlacks(StaState *sta) : - worst_slacks_(sta->corners()->pathAnalysisPtCount(), sta), + worst_slacks_(sta->scenePathCount(), sta), sta_(sta) { } void WorstSlacks::worstSlack(const MinMax *min_max, - // Return values. - Slack &worst_slack, - Vertex *&worst_vertex) + // Return values. + Slack &worst_slack, + Vertex *&worst_vertex) { worst_slack = MinMax::min()->initValue(); worst_vertex = nullptr; - for (auto corner : *sta_->corners()) { - PathAPIndex path_ap_index = corner->findPathAnalysisPt(min_max)->index(); + for (Scene *scene : sta_->scenes()) { + PathAPIndex path_ap_index = scene->pathIndex(min_max); Slack worst_slack1; Vertex *worst_vertex1; worst_slacks_[path_ap_index].worstSlack(path_ap_index, - worst_slack1, worst_vertex1); + worst_slack1, worst_vertex1); if (delayLess(worst_slack1, worst_slack, sta_)) { worst_slack = worst_slack1; worst_vertex = worst_vertex1; @@ -64,22 +64,22 @@ WorstSlacks::worstSlack(const MinMax *min_max, } void -WorstSlacks::worstSlack(const Corner *corner, - const MinMax *min_max, - // Return values. - Slack &worst_slack, - Vertex *&worst_vertex) +WorstSlacks::worstSlack(const Scene *scene, + const MinMax *min_max, + // Return values. + Slack &worst_slack, + Vertex *&worst_vertex) { - PathAPIndex path_ap_index = corner->findPathAnalysisPt(min_max)->index(); + PathAPIndex path_ap_index = scene->pathIndex(min_max); worst_slacks_[path_ap_index].worstSlack(path_ap_index, - worst_slack, worst_vertex); + worst_slack, worst_vertex); } void WorstSlacks::updateWorstSlacks(Vertex *vertex, - SlackSeq &slacks) + SlackSeq &slacks) { - PathAPIndex path_ap_count = sta_->corners()->pathAnalysisPtCount(); + PathAPIndex path_ap_count = sta_->scenePathCount(); for (PathAPIndex i = 0; i < path_ap_count; i++) worst_slacks_[i].updateWorstSlack(vertex, slacks, i); } @@ -87,11 +87,8 @@ WorstSlacks::updateWorstSlacks(Vertex *vertex, void WorstSlacks::worstSlackNotifyBefore(Vertex *vertex) { - WorstSlackSeq::Iterator worst_iter(worst_slacks_); - while (worst_iter.hasNext()) { - WorstSlack &worst_slack = worst_iter.next(); + for (WorstSlack &worst_slack : worst_slacks_) worst_slack.deleteVertexBefore(vertex); - } } //////////////////////////////////////////////////////////////// @@ -102,7 +99,7 @@ WorstSlack::WorstSlack(StaState *sta) : worst_vertex_(nullptr), worst_slack_(slack_init_), slack_threshold_(slack_init_), - queue_(new VertexSet(graph_)), + queue_(new VertexSet(VertexIdLess(graph_))), min_queue_size_(10), max_queue_size_(20) { @@ -119,7 +116,7 @@ WorstSlack::WorstSlack(const WorstSlack &worst_slack) : worst_vertex_(nullptr), worst_slack_(slack_init_), slack_threshold_(slack_init_), - queue_(new VertexSet(graph_)), + queue_(new VertexSet(VertexIdLess(graph_))), min_queue_size_(10), max_queue_size_(20) { @@ -138,9 +135,9 @@ WorstSlack::deleteVertexBefore(Vertex *vertex) void WorstSlack::worstSlack(PathAPIndex path_ap_index, - // Return values. - Slack &worst_slack, - Vertex *&worst_vertex) + // Return values. + Slack &worst_slack, + Vertex *&worst_vertex) { findWorstSlack(path_ap_index); worst_slack = worst_slack_; @@ -167,16 +164,16 @@ WorstSlack::initQueue(PathAPIndex path_ap_index) worst_vertex_ = nullptr; worst_slack_ = slack_init_; slack_threshold_ = slack_init_; - for(Vertex *vertex : *search_->endpoints()) { + for(Vertex *vertex : search_->endpoints()) { Slack slack = search_->wnsSlack(vertex, path_ap_index); if (!delayEqual(slack, slack_init_)) { if (delayLess(slack, worst_slack_, this)) - setWorstSlack(vertex, slack); + setWorstSlack(vertex, slack); if (delayLessEqual(slack, slack_threshold_, this)) - queue_->insert(vertex); + queue_->insert(vertex); int queue_size = queue_->size(); if (queue_size >= max_queue_size_) - sortQueue(path_ap_index); + sortQueue(path_ap_index); } } debugPrint(debug_, "wns", 3, "threshold %s", @@ -206,12 +203,10 @@ WorstSlack::sortQueue(PathAPIndex path_ap_index) // Reinsert vertices with slack < threshold. queue_->clear(); - VertexSeq::Iterator queue_iter2(vertices); - while (queue_iter2.hasNext()) { - Vertex *vertex = queue_iter2.next(); + for (Vertex *vertex : vertices) { Slack slack = search_->wnsSlack(vertex, path_ap_index); if (delayGreater(slack, slack_threshold_, this)) - break; + break; queue_->insert(vertex); } max_queue_size_ = queue_->size() * 2; @@ -239,20 +234,20 @@ void WorstSlack::checkQueue(PathAPIndex path_ap_index) { VertexSeq ends; - for(Vertex *end : *search_->endpoints()) { + for(Vertex *end : search_->endpoints()) { if (delayLessEqual(search_->wnsSlack(end, path_ap_index), - slack_threshold_, this)) + slack_threshold_, this)) ends.push_back(end); } WnsSlackLess slack_less(path_ap_index, this); sort(ends, slack_less); - VertexSet end_set(graph_); + VertexSet end_set = makeVertexSet(this); for (Vertex *end : ends) { end_set.insert(end); - if (!queue_->hasKey(end) - && delayLessEqual(search_->wnsSlack(end, path_ap_index), - slack_threshold_, this)) + if (!queue_->contains(end) + && delayLessEqual(search_->wnsSlack(end, path_ap_index), + slack_threshold_, this)) report_->reportLine("WorstSlack queue missing %s %s < %s", end->to_string(this).c_str(), delayAsString(search_->wnsSlack(end, path_ap_index), this), @@ -260,7 +255,7 @@ WorstSlack::checkQueue(PathAPIndex path_ap_index) } for (Vertex *end : *queue_) { - if (!end_set.hasKey(end)) + if (!end_set.contains(end)) report_->reportLine("WorstSlack queue extra %s %s > %s", end->to_string(this).c_str(), delayAsString(search_->wnsSlack(end, path_ap_index), this), @@ -270,8 +265,8 @@ WorstSlack::checkQueue(PathAPIndex path_ap_index) void WorstSlack::updateWorstSlack(Vertex *vertex, - SlackSeq &slacks, - PathAPIndex path_ap_index) + SlackSeq &slacks, + PathAPIndex path_ap_index) { // Do not touch the state unless queue has been initialized if (!queue_->empty()) { @@ -305,7 +300,7 @@ WorstSlack::updateWorstSlack(Vertex *vertex, void WorstSlack::setWorstSlack(Vertex *vertex, - Slack slack) + Slack slack) { debugPrint(debug_, "wns", 3, "%s %s", vertex->to_string(this).c_str(), @@ -317,7 +312,7 @@ WorstSlack::setWorstSlack(Vertex *vertex, //////////////////////////////////////////////////////////////// WnsSlackLess::WnsSlackLess(PathAPIndex path_ap_index, - const StaState *sta) : + const StaState *sta) : path_ap_index_(path_ap_index), search_(sta->search()) { @@ -325,11 +320,11 @@ WnsSlackLess::WnsSlackLess(PathAPIndex path_ap_index, bool WnsSlackLess::operator()(Vertex *vertex1, - Vertex *vertex2) + Vertex *vertex2) { return delayLess(search_->wnsSlack(vertex1, path_ap_index_), - search_->wnsSlack(vertex2, path_ap_index_), - search_); + search_->wnsSlack(vertex2, path_ap_index_), + search_); } } // namespace diff --git a/search/WorstSlack.hh b/search/WorstSlack.hh index c304fd6b..b23b8a9e 100644 --- a/search/WorstSlack.hh +++ b/search/WorstSlack.hh @@ -25,9 +25,9 @@ #pragma once #include +#include #include "MinMax.hh" -#include "Vector.hh" #include "GraphClass.hh" #include "SearchClass.hh" #include "StaState.hh" @@ -38,23 +38,23 @@ class StaState; class WorstSlack; class WnsSlackLess; -typedef Vector WorstSlackSeq; +using WorstSlackSeq = std::vector; class WorstSlacks { public: WorstSlacks(StaState *sta); void worstSlack(const MinMax *min_max, - // Return values. - Slack &worst_slack, - Vertex *&worst_vertex); - void worstSlack(const Corner *corner, - const MinMax *min_max, - // Return values. - Slack &worst_slack, - Vertex *&worst_vertex); + // Return values. + Slack &worst_slack, + Vertex *&worst_vertex); + void worstSlack(const Scene *scene, + const MinMax *min_max, + // Return values. + Slack &worst_slack, + Vertex *&worst_vertex); void updateWorstSlacks(Vertex *vertex, - SlackSeq &slacks); + SlackSeq &slacks); void worstSlackNotifyBefore(Vertex *vertex); protected: @@ -66,9 +66,9 @@ class WnsSlackLess { public: WnsSlackLess(PathAPIndex path_ap_index, - const StaState *sta); + const StaState *sta); bool operator()(Vertex *vertex1, - Vertex *vertex2); + Vertex *vertex2); private: PathAPIndex path_ap_index_; @@ -82,12 +82,12 @@ public: ~WorstSlack(); WorstSlack(const WorstSlack &); void worstSlack(PathAPIndex path_ap_index, - // Return values. - Slack &worst_slack, - Vertex *&worst_vertex); + // Return values. + Slack &worst_slack, + Vertex *&worst_vertex); void updateWorstSlack(Vertex *vertex, - SlackSeq &slacks, - PathAPIndex path_ap_index); + SlackSeq &slacks, + PathAPIndex path_ap_index); void deleteVertexBefore(Vertex *vertex); protected: @@ -95,7 +95,7 @@ protected: void initQueue(PathAPIndex path_ap_index); void findWorstInQueue(PathAPIndex path_ap_index); void setWorstSlack(Vertex *vertex, - Slack slack); + Slack slack); void sortQueue(PathAPIndex path_ap_index); void checkQueue(PathAPIndex path_ap_index); diff --git a/spice/WritePathSpice.cc b/spice/WritePathSpice.cc index ae8bab8f..694ba7b3 100644 --- a/spice/WritePathSpice.cc +++ b/spice/WritePathSpice.cc @@ -41,9 +41,7 @@ #include "Network.hh" #include "Graph.hh" #include "Sdc.hh" -#include "DcalcAnalysisPt.hh" #include "Parasitics.hh" -#include "PathAnalysisPt.hh" #include "Path.hh" #include "PathExpanded.hh" #include "StaState.hh" @@ -65,14 +63,14 @@ class WritePathSpice : public WriteSpice { public: WritePathSpice(Path *path, - const char *spice_filename, + const char *spice_filename, const char *subckt_filename, - const char *lib_subckt_filename, - const char *model_filename, - const char *power_name, - const char *gnd_name, + const char *lib_subckt_filename, + const char *model_filename, + const char *power_name, + const char *gnd_name, CircuitSim ckt_sim, - const StaState *sta); + const StaState *sta); void writeSpice(); private: @@ -92,10 +90,10 @@ private: float maxTime(); float pathMaxTime(); void writeMeasureDelayStmt(Stage stage, - const Path *from_path, - const Path *to_path); + const Path *from_path, + const Path *to_path); void writeMeasureSlewStmt(Stage stage, - const Path *path); + const Path *path); void writeInputWaveform(); void writeClkWaveform(); @@ -138,8 +136,8 @@ private: float findSlew(const Path *path); float findSlew(const Path *path, - const RiseFall *rf, - const TimingArc *next_arc); + const RiseFall *rf, + const TimingArc *next_arc); Path *path_; PathExpanded path_expanded_; // Input clock waveform cycles. @@ -160,14 +158,14 @@ private: void writePathSpice(Path *path, - const char *spice_filename, - const char *subckt_filename, - const char *lib_subckt_filename, - const char *model_filename, + const char *spice_filename, + const char *subckt_filename, + const char *lib_subckt_filename, + const char *model_filename, const char *power_name, - const char *gnd_name, + const char *gnd_name, CircuitSim ckt_sim, - StaState *sta) + StaState *sta) { WritePathSpice writer(path, spice_filename, subckt_filename, lib_subckt_filename, model_filename, @@ -177,16 +175,16 @@ writePathSpice(Path *path, WritePathSpice::WritePathSpice(Path *path, const char *spice_filename, - const char *subckt_filename, - const char *lib_subckt_filename, - const char *model_filename, - const char *power_name, - const char *gnd_name, + const char *subckt_filename, + const char *lib_subckt_filename, + const char *model_filename, + const char *power_name, + const char *gnd_name, CircuitSim ckt_sim, - const StaState *sta) : + const StaState *sta) : WriteSpice(spice_filename, subckt_filename, lib_subckt_filename, model_filename, power_name, gnd_name, ckt_sim, - path->dcalcAnalysisPt(sta), sta), + path->scene(sta), path->minMax(sta), sta), path_(path), path_expanded_(sta), clk_cycle_count_(3), @@ -297,16 +295,16 @@ WritePathSpice::writeStageInstances() const char *stage_cname = stage_name.c_str(); if (stage == stageFirst()) streamPrint(spice_stream_, "x%s %s %s %s\n", - stage_cname, - stageDrvrPinName(stage), - stageLoadPinName(stage), - stage_cname); + stage_cname, + stageDrvrPinName(stage), + stageLoadPinName(stage), + stage_cname); else { streamPrint(spice_stream_, "x%s %s %s %s %s\n", - stage_cname, - stageGateInputPinName(stage), - stageDrvrPinName(stage), - stageLoadPinName(stage), + stage_cname, + stageGateInputPinName(stage), + stageDrvrPinName(stage), + stageLoadPinName(stage), stage_cname); } } @@ -380,7 +378,7 @@ WritePathSpice::writeClkWaveform() float slew0 = findSlew(input_path, rf0, next_arc); float slew1 = findSlew(input_path, rf1, next_arc); streamPrint(spice_stream_, "v1 %s 0 pwl(\n", - stageDrvrPinName(input_stage)); + stageDrvrPinName(input_stage)); streamPrint(spice_stream_, "+%.3e %.3e\n", 0.0, volt0); for (int cycle = 0; cycle < clk_cycle_count_; cycle++) { float time0 = time_offset + cycle * period; @@ -438,8 +436,8 @@ WritePathSpice::writeMeasureStmts() void WritePathSpice::writeMeasureDelayStmt(Stage stage, - const Path *from_path, - const Path *to_path) + const Path *from_path, + const Path *to_path) { writeMeasureDelayStmt(from_path->pin(this), from_path->transition(this), to_path->pin(this), to_path->transition(this), @@ -448,7 +446,7 @@ WritePathSpice::writeMeasureDelayStmt(Stage stage, void WritePathSpice::writeMeasureSlewStmt(Stage stage, - const Path *path) + const Path *path) { const Pin *pin = path->pin(this); const RiseFall *rf = path->transition(this); @@ -484,9 +482,9 @@ WritePathSpice::writeInputStage(Stage stage) const char *load_pin_name = stageLoadPinName(stage); string prefix = stageName(stage); streamPrint(spice_stream_, ".subckt %s %s %s\n", - prefix.c_str(), - drvr_pin_name, - load_pin_name); + prefix.c_str(), + drvr_pin_name, + load_pin_name); writeStageParasitics(stage); streamPrint(spice_stream_, ".ends\n\n"); } @@ -508,16 +506,16 @@ WritePathSpice::writeGateStage(Stage stage) LibertyPort *drvr_port = stageDrvrPort(stage); streamPrint(spice_stream_, ".subckt %s %s %s %s\n", - subckt_name.c_str(), - input_pin_name, - drvr_pin_name, - load_pin_name); + subckt_name.c_str(), + input_pin_name, + drvr_pin_name, + load_pin_name); // Driver subckt call. streamPrint(spice_stream_, "* Gate %s %s -> %s\n", - network_->pathName(inst), - input_port->name(), - drvr_port->name()); + network_->pathName(inst), + input_port->name(), + drvr_port->name()); writeSubcktInst(inst); const Path *drvr_path = stageDrvrPath(stage); @@ -551,13 +549,12 @@ void WritePathSpice::writeStageParasitics(Stage stage) { const Path *drvr_path = stageDrvrPath(stage); - DcalcAnalysisPt *dcalc_ap = drvr_path->dcalcAnalysisPt(this); - ParasiticAnalysisPt *parasitic_ap = dcalc_ap->parasiticAnalysisPt(); + const MinMax *min_max = drvr_path->minMax(this); const Pin *drvr_pin = stageDrvrPin(stage); - const Parasitic *parasitic = parasitics_->findParasiticNetwork(drvr_pin, parasitic_ap); + const Parasitic *parasitic = parasitics_->findParasiticNetwork(drvr_pin); if (parasitic == nullptr) { const RiseFall *drvr_rf = drvr_path->transition(this); - parasitic = parasitics_->findPiElmore(drvr_pin, drvr_rf, parasitic_ap); + parasitic = parasitics_->findPiElmore(drvr_pin, drvr_rf, min_max); } NetSet coupling_nets; writeDrvrParasitics(drvr_pin, parasitic, coupling_nets); @@ -583,19 +580,19 @@ WritePathSpice::findPathCellNames() if (arc) { LibertyCell *cell = arc->set()->libertyCell(); if (cell) { - debugPrint(debug_, "write_spice", 2, "cell %s", cell->name()); - path_cell_names.insert(cell->name()); + debugPrint(debug_, "write_spice", 2, "cell %s", cell->name()); + path_cell_names.insert(cell->name()); } // Include side receivers. Pin *drvr_pin = stageDrvrPin(stage); auto pin_iter = network_->connectedPinIterator(drvr_pin); while (pin_iter->hasNext()) { - const Pin *pin = pin_iter->next(); - LibertyPort *port = network_->libertyPort(pin); - if (port) { - LibertyCell *cell = port->libertyCell(); - path_cell_names.insert(cell->name()); - } + const Pin *pin = pin_iter->next(); + LibertyPort *port = network_->libertyPort(pin); + if (port) { + LibertyCell *cell = port->libertyCell(); + path_cell_names.insert(cell->name()); + } } delete pin_iter; } diff --git a/spice/WritePathSpice.hh b/spice/WritePathSpice.hh index bf4ab506..a6d014d1 100644 --- a/spice/WritePathSpice.hh +++ b/spice/WritePathSpice.hh @@ -36,17 +36,17 @@ class StaState; // Throws FileNotReadable, FileNotWritable, SubcktEndsMissing void writePathSpice(Path *path, - // Spice file written for path. - const char *spice_filename, - // Subckts used by path included in spice file. - const char *subckt_filename, - // File of all cell spice subckt definitions. - const char *lib_subckt_filename, - // Device model file included in spice file. - const char *model_filename, + // Spice file written for path. + const char *spice_filename, + // Subckts used by path included in spice file. + const char *subckt_filename, + // File of all cell spice subckt definitions. + const char *lib_subckt_filename, + // Device model file included in spice file. + const char *model_filename, const char *power_name, - const char *gnd_name, + const char *gnd_name, CircuitSim ckt_sim, - StaState *sta); + StaState *sta); } // namespace diff --git a/spice/WriteSpice.cc b/spice/WriteSpice.cc index f336bc8f..9ef7b05d 100644 --- a/spice/WriteSpice.cc +++ b/spice/WriteSpice.cc @@ -27,6 +27,9 @@ #include // swap #include +#include "cudd.h" + +#include "ContainerHelpers.hh" #include "Debug.hh" #include "Units.hh" #include "TableModel.hh" @@ -41,9 +44,9 @@ #include "search/Sim.hh" #include "Clock.hh" #include "Path.hh" -#include "DcalcAnalysisPt.hh" #include "Bdd.hh" -#include "cudd.h" +#include "Sdc.hh" +#include "Mode.hh" namespace sta { @@ -93,7 +96,8 @@ WriteSpice::WriteSpice(const char *spice_filename, const char *power_name, const char *gnd_name, CircuitSim ckt_sim, - const DcalcAnalysisPt *dcalc_ap, + const Scene *scene, + const MinMax *min_max, const StaState *sta) : StaState(sta), spice_filename_(spice_filename), @@ -103,13 +107,15 @@ WriteSpice::WriteSpice(const char *spice_filename, power_name_(power_name), gnd_name_(gnd_name), ckt_sim_(ckt_sim), - dcalc_ap_(dcalc_ap), + scene_(scene), + min_max_(min_max), default_library_(network_->defaultLibertyLibrary()), short_ckt_resistance_(.0001), cap_index_(1), res_index_(1), volt_index_(1), - bdd_(sta) + bdd_(sta), + parasitics_(scene->parasitics(min_max)) { } @@ -119,7 +125,8 @@ WriteSpice::initPowerGnd() bool exists = false; default_library_->supplyVoltage(power_name_, power_voltage_, exists); if (!exists) { - const OperatingConditions *op_cond = dcalc_ap_->operatingConditions(); + const OperatingConditions *op_cond = + scene_->sdc()->operatingConditions(min_max_); if (op_cond == nullptr) op_cond = network_->defaultLibertyLibrary()->defaultOperatingConditions(); power_voltage_ = op_cond->voltage(); @@ -211,7 +218,7 @@ WriteSpice::writeSubckts(StdStringSet &cell_names) if (tokens.size() >= 2 && stringEqual(tokens[0].c_str(), ".subckt")) { const char *cell_name = tokens[1].c_str(); - if (cell_names.find(cell_name) != cell_names.end()) { + if (cell_names.contains(cell_name)) { subckts_stream << line << "\n"; bool found_ends = false; while (getline(lib_subckts_stream, line)) { @@ -288,7 +295,7 @@ WriteSpice::findCellSubckts(StdStringSet &cell_names) if (tokens.size() >= 2 && stringEqual(tokens[0].c_str(), ".subckt")) { const char *cell_name = tokens[1].c_str(); - if (cell_names.find(cell_name) != cell_names.end()) { + if (cell_names.contains(cell_name)) { // Scan the subckt definition for subckt calls. string stmt; while (getline(lib_subckts_stream, line)) { @@ -370,15 +377,15 @@ WriteSpice::writeSubcktInstVoltSrcs(const Instance *inst, else if (stringEq(subckt_port_name, gnd_name_)) writeVoltageSource(inst_name, subckt_port_name, gnd_voltage_); else if (port - && excluded_input_pins.find(pin) == excluded_input_pins.end() + && !excluded_input_pins.contains(pin) && port->direction()->isAnyInput()) { // Input voltage to sensitize path from gate input to output. // Look for tie high/low or propagated constant values. - LogicValue port_value = sim_->logicValue(pin); + LogicValue port_value = scene_->mode()->sim()->simValue(pin); if (port_value == LogicValue::unknown) { bool has_value; LogicValue value; - port_values.findKey(port, value, has_value); + findKeyValue(port_values, port, value, has_value); if (has_value) port_value = value; } @@ -468,7 +475,8 @@ WriteSpice::findSlew(Vertex *vertex, const RiseFall *rf, const TimingArc *next_arc) { - float slew = delayAsFloat(graph_->slew(vertex, rf, dcalc_ap_->index())); + DcalcAPIndex ap_index = scene_->dcalcAnalysisPtIndex(min_max_); + float slew = delayAsFloat(graph_->slew(vertex, rf, ap_index)); if (slew == 0.0 && next_arc) slew = slewAxisMinValue(next_arc); if (slew == 0.0) @@ -480,7 +488,7 @@ WriteSpice::findSlew(Vertex *vertex, float WriteSpice::slewAxisMinValue(const TimingArc *arc) { - GateTableModel *gate_model = arc->gateTableModel(dcalc_ap_); + GateTableModel *gate_model = arc->gateTableModel(scene_, min_max_); if (gate_model) { const TableModel *model = gate_model->delayModel(); const TableAxis *axis1 = model->axis1(); @@ -533,8 +541,7 @@ WriteSpice::writeParasiticNetwork(const Pin *drvr_pin, set reachable_pins; // Sort resistors for consistent regression results. ParasiticResistorSeq resistors = parasitics_->resistors(parasitic); - sort(resistors.begin(), resistors.end(), - [this] (const ParasiticResistor *r1, + sort(resistors, [this] (const ParasiticResistor *r1, const ParasiticResistor *r2) { return parasitics_->id(r1) < parasitics_->id(r2); }); @@ -564,7 +571,7 @@ WriteSpice::writeParasiticNetwork(const Pin *drvr_pin, if (pin != drvr_pin && network_->isLoad(pin) && !network_->isHierarchical(pin) - && reachable_pins.find(pin) == reachable_pins.end()) { + && !reachable_pins.contains(pin)) { streamPrint(spice_stream_, "R%d %s %s %.3e\n", res_index_++, network_->pathName(drvr_pin), @@ -577,8 +584,7 @@ WriteSpice::writeParasiticNetwork(const Pin *drvr_pin, // Grounded node capacitors. // Sort nodes for consistent regression results. ParasiticNodeSeq nodes = parasitics_->nodes(parasitic); - sort(nodes.begin(), nodes.end(), - [this] (const ParasiticNode *node1, + sort(nodes, [this] (const ParasiticNode *node1, const ParasiticNode *node2) { const char *name1 = parasitics_->name(node1); const char *name2 = parasitics_->name(node2); @@ -598,8 +604,7 @@ WriteSpice::writeParasiticNetwork(const Pin *drvr_pin, // Sort coupling capacitors for consistent regression results. ParasiticCapacitorSeq capacitors = parasitics_->capacitors(parasitic); - sort(capacitors.begin(), capacitors.end(), - [this] (const ParasiticCapacitor *c1, + sort(capacitors, [this] (const ParasiticCapacitor *c1, const ParasiticCapacitor *c2) { return parasitics_->id(c1) < parasitics_->id(c2); }); @@ -614,7 +619,7 @@ WriteSpice::writeParasiticNetwork(const Pin *drvr_pin, swap(net1, net2); swap(node1, node2); } - if (net2 && coupling_nets.hasKey(net2)) + if (net2 && coupling_nets.contains(net2)) // Write half the capacitance because the coupled net will do the same. streamPrint(spice_stream_, "C%d %s %s %.3e\n", cap_index_++, @@ -965,19 +970,19 @@ WriteSpice::onePort(FuncExpr *expr) FuncExpr *right = expr->right(); LibertyPort *port; switch (expr->op()) { - case FuncExpr::op_port: + case FuncExpr::Op::port: return expr->port(); - case FuncExpr::op_not: + case FuncExpr::Op::not_: return onePort(left); - case FuncExpr::op_or: - case FuncExpr::op_and: - case FuncExpr::op_xor: + case FuncExpr::Op::or_: + case FuncExpr::Op::and_: + case FuncExpr::Op::xor_: port = onePort(left); if (port == nullptr) port = onePort(right); return port; - case FuncExpr::op_one: - case FuncExpr::op_zero: + case FuncExpr::Op::one: + case FuncExpr::Op::zero: default: return nullptr; } @@ -1018,7 +1023,7 @@ WriteSpice::writeSubcktInstLoads(const Pin *drvr_pin, && network_->direction(load_pin)->isAnyInput() && !network_->isHierarchical(load_pin) && !network_->isTopLevelPort(load_pin) - && !written_insts.hasKey(load_inst)) { + && !written_insts.contains(load_inst)) { writeSubcktInst(load_inst); writeSubcktInstVoltSrcs(load_inst, port_values, excluded_input_pins); streamPrint(spice_stream_, "\n"); diff --git a/spice/WriteSpice.hh b/spice/WriteSpice.hh index 98995a44..3e55e294 100644 --- a/spice/WriteSpice.hh +++ b/spice/WriteSpice.hh @@ -39,10 +39,10 @@ namespace sta { -typedef std::map ParasiticNodeMap; -typedef Map CellSpicePortNames; -typedef Map LibertyPortLogicValues; -typedef std::vector StdStringSeq; +using ParasiticNodeMap = std::map; +using CellSpicePortNames = std::map; +using LibertyPortLogicValues = std::map; +using StdStringSeq = std::vector; // Utilities for writing a spice deck. class WriteSpice : public StaState @@ -55,7 +55,8 @@ public: const char *power_name, const char *gnd_name, CircuitSim ckt_sim, - const DcalcAnalysisPt *dcalc_ap, + const Scene *scene, + const MinMax *min_max, const StaState *sta); protected: @@ -68,28 +69,23 @@ protected: void writeSubckts(StdStringSet &cell_names); void findCellSubckts(StdStringSet &cell_names); void recordSpicePortNames(const char *cell_name, - StringVector &tokens); + StringVector &tokens); void writeSubcktInst(const Instance *inst); void writeSubcktInstVoltSrcs(const Instance *inst, - LibertyPortLogicValues &port_values, + LibertyPortLogicValues &port_values, const PinSet &excluded_input_pins); float pgPortVoltage(LibertyPort *pg_port); void writeVoltageSource(const char *inst_name, - const char *port_name, - float voltage); + const char *port_name, + float voltage); void writeVoltageSource(LibertyCell *cell, - const char *inst_name, - const char *subckt_port_name, - const char *pg_port_name, - float voltage); + const char *inst_name, + const char *subckt_port_name, + const char *pg_port_name, + float voltage); void writeClkedStepSource(const Pin *pin, - const RiseFall *rf, - const Clock *clk); - void writeDrvrParasitics(const Pin *drvr_pin, - const RiseFall *drvr_rf, - // Nets with parasitics to include coupling caps to. - const NetSet &coupling_nets, - const ParasiticAnalysisPt *parasitic_ap); + const RiseFall *rf, + const Clock *clk); void writeDrvrParasitics(const Pin *drvr_pin, const Parasitic *parasitic, const NetSet &coupling_nets); @@ -103,23 +99,23 @@ protected: void writeVoltageSource(const char *node_name, float voltage); void writeRampVoltSource(const Pin *pin, - const RiseFall *rf, - float time, - float slew); + const RiseFall *rf, + float time, + float slew); void writeWaveformVoltSource(const Pin *pin, DriverWaveform *drvr_waveform, const RiseFall *rf, float delay, float slew); void writeWaveformEdge(const RiseFall *rf, - float time, - float slew); + float time, + float slew); float railToRailSlew(float slew, const RiseFall *rf); void seqPortValues(Sequential *seq, - const RiseFall *rf, - // Return values. - LibertyPortLogicValues &port_values); + const RiseFall *rf, + // Return values. + LibertyPortLogicValues &port_values); LibertyPort *onePort(FuncExpr *expr); void writeMeasureDelayStmt(const Pin *from_pin, const RiseFall *from_rf, @@ -131,8 +127,8 @@ protected: std::string prefix); const char *spiceTrans(const RiseFall *rf); float findSlew(Vertex *vertex, - const RiseFall *rf, - const TimingArc *next_arc); + const RiseFall *rf, + const TimingArc *next_arc); float slewAxisMinValue(const TimingArc *arc); float clkWaveformTimeOffset(const Clock *clk); @@ -140,21 +136,21 @@ protected: const Pin *drvr_pin, const RiseFall *drvr_rf, const Edge *gate_edge, - // Return values. - LibertyPortLogicValues &port_values, - bool &is_clked); + // Return values. + LibertyPortLogicValues &port_values, + bool &is_clked); void regPortValues(const Pin *input_pin, const RiseFall *drvr_rf, const LibertyPort *drvr_port, const FuncExpr *drvr_func, - // Return values. - LibertyPortLogicValues &port_values, + // Return values. + LibertyPortLogicValues &port_values, bool &is_clked); void gatePortValues(const Instance *inst, - const FuncExpr *expr, - const LibertyPort *input_port, - // Return values. - LibertyPortLogicValues &port_values); + const FuncExpr *expr, + const LibertyPort *input_port, + // Return values. + LibertyPortLogicValues &port_values); void writeSubcktInstLoads(const Pin *drvr_pin, const Pin *path_load, const PinSet &excluded_input_pins, @@ -171,7 +167,8 @@ protected: const char *power_name_; const char *gnd_name_; CircuitSim ckt_sim_; - const DcalcAnalysisPt *dcalc_ap_; + const Scene *scene_; + const MinMax *min_max_; std::ofstream spice_stream_; LibertyLibrary *default_library_; @@ -187,11 +184,12 @@ protected: int volt_index_; CellSpicePortNames cell_spice_port_names_; Bdd bdd_; + Parasitics *parasitics_; }; void streamPrint(std::ofstream &stream, - const char *fmt, - ...) __attribute__((format (printf, 2, 3))); + const char *fmt, + ...) __attribute__((format (printf, 2, 3))); } // namespace diff --git a/spice/WriteSpice.i b/spice/WriteSpice.i index 727bf82b..e7adadbe 100644 --- a/spice/WriteSpice.i +++ b/spice/WriteSpice.i @@ -34,12 +34,12 @@ void write_path_spice_cmd(Path *path, - const char *spice_filename, - const char *subckt_filename, - const char *lib_subckt_filename, - const char *model_filename, - const char *power_name, - const char *gnd_name, + const char *spice_filename, + const char *subckt_filename, + const char *lib_subckt_filename, + const char *model_filename, + const char *power_name, + const char *gnd_name, CircuitSim ckt_sim) { Sta *sta = Sta::sta(); diff --git a/spice/WriteSpice.tcl b/spice/WriteSpice.tcl index af15905b..7bf9674e 100644 --- a/spice/WriteSpice.tcl +++ b/spice/WriteSpice.tcl @@ -25,17 +25,17 @@ namespace eval sta { define_cmd_args "write_path_spice" { -path_args path_args\ - -spice_directory spice_directory\ - -lib_subckt_file lib_subckts_file\ - -model_file model_file\ - -power power\ - -ground ground\ + -spice_directory spice_directory\ + -lib_subckt_file lib_subckts_file\ + -model_file model_file\ + -power power\ + -ground ground\ [-simulator hspice|ngspice|xyce]} proc write_path_spice { args } { parse_key_args "write_path_spice" args \ keys {-spice_directory -lib_subckt_file -model_file \ - -power -ground -path_args -simulator} \ + -power -ground -path_args -simulator} \ flags {} if { [info exists keys(-spice_directory)] } { @@ -100,7 +100,7 @@ proc write_path_spice { args } { set spice_file [file join $spice_dir "$path_name.sp"] set subckt_file [file join $spice_dir "$path_name.subckt"] write_path_spice_cmd $path $spice_file $subckt_file \ - $lib_subckt_file $model_file $power $ground $ckt_sim + $lib_subckt_file $model_file $power $ground $ckt_sim incr path_index } } @@ -132,13 +132,13 @@ define_cmd_args "write_gate_spice" \ -power power\ -ground ground\ [-simulator hspice|ngspice|xyce]\ - [-corner corner]\ + [-scene scene]\ [-min] [-max]} proc write_gate_spice { args } { parse_key_args "write_gate_spice" args \ keys {-gates -spice_filename -lib_subckt_file -model_file \ - -power -ground -simulator -corner}\ + -power -ground -simulator -scene -corner}\ flags {-measure_stmts -min -max} if { [info exists keys(-gates)] } { @@ -188,7 +188,7 @@ proc write_gate_spice { args } { set ckt_sim [parse_ckt_sim_key keys] - set corner [parse_corner keys] + set scene [parse_scene keys] set min_max [parse_min_max_flags flags] check_argc_eq0 "write_gate_spice" $args @@ -197,7 +197,7 @@ proc write_gate_spice { args } { set subckt_file [file join $spice_dir "$spice_root.subckt"] write_gate_spice_cmd $gates $spice_file $subckt_file \ $lib_subckt_file $model_file $power $ground $ckt_sim \ - $corner $min_max + $scene $min_max } ################################################################ @@ -207,11 +207,11 @@ define_cmd_args "write_gate_gnuplot" \ { -gates {{instance input_port driver_port edge [delay]}...}\ -plot_pins plot_pins\ -plot_basename plot_basename\ - [-corner corner] [-min] [-max]} + [-scene scene] [-min] [-max]} proc write_gate_gnuplot { args } { parse_key_args "write_gate_gnuplot" args \ - keys {-gates -plot_pins -plot_basename -spice_waveforms -corner} \ + keys {-gates -plot_pins -plot_basename -spice_waveforms -corner -scene} \ flags {-min -max} if { [info exists keys(-gates)] } { @@ -262,11 +262,11 @@ proc write_gate_gnuplot { args } { set sim_wave_filename $keys(-spice_waveforms) } - set corner [parse_corner keys] + set scene [parse_scene keys] set min_max [parse_min_max_flags flags] write_gate_gnuplot_cmd $gates $plot_pins $sim_wave_filename \ - $gnuplot_filename $csv_filename $corner $min_max + $gnuplot_filename $csv_filename $scene $min_max } proc parse_gate_drvr_pin { gate_arg } { diff --git a/spice/Xyce.hh b/spice/Xyce.hh index 848c9987..c13a918b 100644 --- a/spice/Xyce.hh +++ b/spice/Xyce.hh @@ -31,8 +31,8 @@ namespace sta { -typedef std::vector StdStringSeq; -typedef std::vector WaveformSeq; +using StdStringSeq = std::vector; +using WaveformSeq = std::vector; void readXyceCsv(const char *csv_filename, diff --git a/tcl/CmdArgs.tcl b/tcl/CmdArgs.tcl index c1a59889..094fc633 100644 --- a/tcl/CmdArgs.tcl +++ b/tcl/CmdArgs.tcl @@ -48,8 +48,8 @@ namespace eval sta { # net proc get_object_args { objects clks_var libcells_var libports_var \ - cells_var insts_var ports_var pins_var nets_var \ - edges_var timing_arc_sets_var } { + cells_var insts_var ports_var pins_var nets_var \ + edges_var timing_arc_sets_var } { if { $clks_var != {} } { upvar 1 $clks_var clks } @@ -87,97 +87,97 @@ proc get_object_args { objects clks_var libcells_var libports_var \ if { [llength $obj] > 1 } { # List arg. Recursive call without initing objects. get_object_args $obj $clks_var $libcells_var $libports_var $cells_var $insts_var \ - $ports_var $pins_var $nets_var $edges_var $timing_arc_sets_var + $ports_var $pins_var $nets_var $edges_var $timing_arc_sets_var } elseif { [is_object $obj] } { # Explicit object arg. set object_type [object_type $obj] if { $pins_var != {} && $object_type == "Pin" } { - lappend pins $obj + lappend pins $obj } elseif { $insts_var != {} && $object_type == "Instance" } { - lappend insts $obj + lappend insts $obj } elseif { $nets_var != {} && $object_type == "Net" } { - lappend nets $obj + lappend nets $obj } elseif { $ports_var != {} && $object_type == "Port" } { - lappend ports $obj + lappend ports $obj } elseif { $edges_var != {} && $object_type == "Edge" } { - lappend edges $obj + lappend edges $obj } elseif { $clks_var != {} && $object_type == "Clock" } { - lappend clks $obj + lappend clks $obj } elseif { $libcells_var != {} && $object_type == "LibertyCell" } { - lappend libcells $obj + lappend libcells $obj } elseif { $libports_var != {} && $object_type == "LibertyPort" } { - lappend libports $obj + lappend libports $obj } elseif { $cells_var != {} && $object_type == "Cell" } { - lappend cells $obj + lappend cells $obj } elseif { $timing_arc_sets_var != {} \ - && $object_type == "TimingArcSet" } { - lappend timing_arc_sets $obj + && $object_type == "TimingArcSet" } { + lappend timing_arc_sets $obj } else { - sta_error 100 "unsupported object type $object_type." + sta_error 100 "unsupported object type $object_type." } } elseif { $obj != {} } { # Check for implicit arg. # Search for most general object type first. set matches {} if { $clks_var != {} } { - set matches [get_clocks -quiet $obj] + set matches [get_clocks -quiet $obj] } if { $matches != {} } { - set clks [concat $clks $matches] + set clks [concat $clks $matches] } else { - if { $libcells_var != {} } { - set matches [get_lib_cells -quiet $obj] - } - if { $matches != {} } { - set libcells [concat $libcells $matches] - } else { - - if { $libports_var != {} } { - set matches [get_lib_pins -quiet $obj] - } - if { $matches != {} } { - set libports [concat $libports $matches] - } else { - - if { $cells_var != {} } { - set matches [find_cells_matching $obj 0 0] - } - if { $matches != {} } { - set cells [concat $cells $matches] - } else { - - if { $insts_var != {} } { - set matches [get_cells -quiet $obj] - } - if { $matches != {} } { - set insts [concat $insts $matches] - } else { - if { $ports_var != {} } { - set matches [get_ports -quiet $obj] - } - if { $matches != {} } { - set ports [concat $ports $matches] - } else { - if { $pins_var != {} } { - set matches [get_pins -quiet $obj] - } - if { $matches != {} } { - set pins [concat $pins $matches] - } else { - if { $nets_var != {} } { - set matches [get_nets -quiet $obj] - } - if { $matches != {} } { - set nets [concat $nets $matches] - } else { - sta_warn 101 "object '$obj' not found." - } - } - } - } - } - } - } + if { $libcells_var != {} } { + set matches [get_lib_cells -quiet $obj] + } + if { $matches != {} } { + set libcells [concat $libcells $matches] + } else { + + if { $libports_var != {} } { + set matches [get_lib_pins -quiet $obj] + } + if { $matches != {} } { + set libports [concat $libports $matches] + } else { + + if { $cells_var != {} } { + set matches [find_cells_matching $obj 0 0] + } + if { $matches != {} } { + set cells [concat $cells $matches] + } else { + + if { $insts_var != {} } { + set matches [get_cells -quiet $obj] + } + if { $matches != {} } { + set insts [concat $insts $matches] + } else { + if { $ports_var != {} } { + set matches [get_ports -quiet $obj] + } + if { $matches != {} } { + set ports [concat $ports $matches] + } else { + if { $pins_var != {} } { + set matches [get_pins -quiet $obj] + } + if { $matches != {} } { + set pins [concat $pins $matches] + } else { + if { $nets_var != {} } { + set matches [get_nets -quiet $obj] + } + if { $matches != {} } { + set nets [concat $nets $matches] + } else { + sta_warn 101 "object '$obj' not found." + } + } + } + } + } + } + } } } } @@ -194,7 +194,7 @@ proc parse_clk_cell_port_args { objects clks_var cells_var ports_var } { } proc parse_clk_cell_port_pin_args { objects clks_var cells_var ports_var \ - pins_arg } { + pins_arg } { upvar 1 $clks_var clks upvar 1 $cells_var cells upvar 1 $ports_var ports @@ -243,13 +243,13 @@ proc parse_clk_port_pin_arg { objects clks_var pins_var } { } proc parse_libcell_libport_inst_port_pin_edge_timing_arc_set_arg { objects \ - libcells_var \ - libports_var \ - insts_var \ - ports_var \ - pins_var \ - edges_var \ - timing_arc_sets_var } { + libcells_var \ + libports_var \ + insts_var \ + ports_var \ + pins_var \ + edges_var \ + timing_arc_sets_var } { upvar 1 $libcells_var libcells upvar 1 $libports_var libports upvar 1 $insts_var insts @@ -399,87 +399,156 @@ proc get_ports_or_pins { pattern } { ################################################################ -# -corner keyword is optional. -# If -corner keyword is missing: -# one corner: return default -# multiple corners: error -proc parse_corner { keys_var } { +# -scene keyword is optional. +# If -scene keyword is missing: +# one scene: return default +# multiple scenes: error +proc parse_scene { keys_var } { upvar 1 $keys_var keys + set scene_arg "" + # compabibility 05/29/2025 if { [info exists keys(-corner)] } { - set corner_arg $keys(-corner) - if { [is_object $corner_arg] } { - set object_type [object_type $corner_arg] - if { $object_type == "Corner" } { - return $corner_arg + set scene_arg $keys(-corner) + } + if { [info exists keys(-scene)] } { + set scene_arg $keys(-scene) + } + if { $scene_arg != "" } { + if { [is_object $scene_arg] } { + set object_type [object_type $scene_arg] + if { $object_type == "Scene" } { + return $scene_arg } else { - sta_error 144 "corner object type '$object_type' is not a corner." + sta_error 144 "scene object type '$object_type' is not a scene." } } else { - set corner [find_corner $corner_arg] - if { $corner == "NULL" } { - sta_error 102 "$corner_arg is not the name of process corner." + set scene [find_scene $scene_arg] + if { $scene == "NULL" } { + sta_error 102 "$scene_arg is not the name of a scene." } else { - return $corner + return $scene } } - } elseif { [multi_corner] } { - sta_error 103 "-corner keyword required with multi-corner analysis." + } elseif { [multi_scene] } { + sta_error 103 "-scene keyword required with multi-scene analysis." } else { - return [cmd_corner] + return [cmd_scene] } } -# -corner keyword is required. -proc parse_corner_required { keys_var } { +# -scene keyword is required. +proc parse_scene_required { keys_var } { upvar 1 $keys_var keys + set scene_name "" + if { [info exists keys(-scene)] } { + set scene_name $keys(-scene) + } + # compabibility 05/29/2025 if { [info exists keys(-corner)] } { - set corner_name $keys(-corner) - set corner [find_corner $corner_name] - if { $corner == "NULL" } { - sta_error 104 "$corner_name is not the name of process corner." + set scene_name $keys(-corner) + } + if { $scene_name != "" } { + set scene [find_scene $scene_name] + if { $scene == "NULL" } { + sta_error 104 "$scene_name is not the name of a scene." } else { - return $corner + return $scene } } else { - sta_error 105 "missing -corner arg." + sta_error 105 "missing -scene arg." } } -proc parse_corner_or_default { keys_var } { +proc parse_scene_or_default { keys_var } { upvar 1 $keys_var keys + set scene_name "" + if { [info exists keys(-scene)] } { + set scene_name $keys(-scene) + } + # compabibility 05/29/2025 if { [info exists keys(-corner)] } { - set corner_name $keys(-corner) - set corner [find_corner $corner_name] - if { $corner == "NULL" } { - sta_error 106 "$corner_name is not the name of process corner." + set scene_name $keys(-corner) + } + if { $scene_name != "" } { + set scene [find_scene $scene_name] + if { $scene == "NULL" } { + sta_error 106 "$scene_name is not the name of a scene." } else { - return $corner + return $scene } } else { - return [cmd_corner] + return [cmd_scene] } } -# Return NULL for all. -proc parse_corner_or_all { keys_var } { +# If -scene/-corner return scene, else return NULL. +proc parse_scene_or_null { keys_var } { upvar 1 $keys_var keys + set scene_name "" + if { [info exists keys(-scene)] } { + set scene_name $keys(-scene) + } + # compabibility 05/29/2025 if { [info exists keys(-corner)] } { - set corner_name $keys(-corner) - set corner [find_corner $corner_name] - if { $corner == "NULL" } { - sta_error 107 "$corner_name is not the name of process corner." + set scene_name $keys(-corner) + } + if { $scene_name != "" } { + set scene [find_scene $scene_name] + if { $scene == "NULL" } { + sta_error 107 "$scene_name is not the name of a scene." } else { - return $corner + return $scene } } else { return "NULL" } } +# If -scenes/-corner return scenes, else return default scene. +proc parse_scenes_or_default { keys_var } { + upvar 1 $keys_var keys + + if { [info exists keys(-scenes)] } { + return [find_scenes $keys(-scenes)] + } elseif { [info exists keys(-corner)] } { + # compabibility 05/29/2025 + return [find_scenes $keys(-corner)] + } else { + return [cmd_scene] + } +} + +# If -scenes/-corner return scenes, else return all scenes. +proc parse_scenes_or_all { keys_var } { + upvar 1 $keys_var keys + + if { [info exists keys(-scenes)] } { + return [find_scenes $keys(-scenes)] + } elseif { [info exists keys(-corner)] } { + # compabibility 05/29/2025 + return [find_scenes $keys(-corner)] + } else { + return [scenes] + } +} + +proc find_scenes { scene_names } { + set scenes {} + foreach scene_name $scene_names { + set scene [find_scene $scene_name] + if { $scene == "NULL" } { + sta_error 134 "$scene_name is not the name of a scene." + } else { + lappend scenes $scene + } + } + return $scenes +} + ################################################################ proc parse_rise_fall_flags { flags_var } { @@ -617,7 +686,7 @@ proc get_lib_cell_arg { arg_name arg error_proc } { if { $library != "NULL" } { set lib_cell [$library find_liberty_cell $cell_name] if { $lib_cell == "NULL" } { - $error_proc 117 "liberty cell '$arg' not found." + $error_proc 117 "liberty cell '$arg' not found." } } else { $error_proc 118 "library '$lib_name' not found." @@ -643,14 +712,14 @@ proc get_lib_cells_arg { arg_name arglist error_proc } { } elseif { [is_object $arg] } { set object_type [object_type $arg] if { $object_type == "LibertyCell" } { - lappend lib_cells $arg + lappend lib_cells $arg } else { - $error_proc 120 "unsupported object type $object_type." + $error_proc 120 "unsupported object type $object_type." } } elseif { $arg != {} } { set arg_lib_cells [get_lib_cells1 $arg $error_proc] if { $arg_lib_cells != {} } { - set lib_cells [concat $lib_cells $arg_lib_cells] + set lib_cells [concat $lib_cells $arg_lib_cells] } } } diff --git a/tcl/CmdUtil.tcl b/tcl/CmdUtil.tcl index a2380ace..3eab6018 100644 --- a/tcl/CmdUtil.tcl +++ b/tcl/CmdUtil.tcl @@ -65,15 +65,15 @@ proc show_cmd_args { cmd } { # Break the arglist up into max_col length lines. while {1} { if {[regexp {(^[\n ]*)([a-zA-Z0-9_\\\|\-]+|\[[^\[]+\])(.*)} \ - $arglist ignore space arg rest]} { + $arglist ignore space arg rest]} { set arg_length [string length $arg] if { $col + $arg_length < $max_col } { - set line "$line $arg" - set col [expr $col + $arg_length + 1] + set line "$line $arg" + set col [expr $col + $arg_length + 1] } else { report_line $line - set line "$indent_str $arg" - set col [expr $indent + $arg_length + 1] + set line "$indent_str $arg" + set col [expr $indent + $arg_length + 1] } set arglist $rest } else { @@ -147,7 +147,7 @@ define_cmd_args "set_cmd_units" \ proc set_cmd_units { args } { parse_key_args "set_cmd_units" args \ keys {-capacitance -resistance -time -voltage -current -power \ - -distance -digits -suffix} \ + -distance -digits -suffix} \ flags {} check_argc_eq0 "set_cmd_units" $args @@ -207,25 +207,25 @@ proc delete_objects_from_list_cmd { list objects } { # type. if {$list_is_object && ![is_object $obj]} { if {$list_type == "Clock"} { - set obj [find_clock $obj] + set obj [find_clock $obj] } elseif {$list_type == "Port"} { - set top_instance [top_instance] - set top_cell [$top_instance cell] - set obj [$top_cell find_port $obj] + set top_instance [top_instance] + set top_cell [$top_instance cell] + set obj [$top_cell find_port $obj] } elseif {$list_type == "Pin"} { - set obj [find_pin $obj] + set obj [find_pin $obj] } elseif {$list_type == "Instance"} { - set obj [find_instance $obj] + set obj [find_instance $obj] } elseif {$list_type == "Net"} { - set obj [find_net $obj] + set obj [find_net $obj] } elseif {$list_type == "LibertyLibrary"} { - set obj [find_liberty $obj] + set obj [find_liberty $obj] } elseif {$list_type == "LibertyCell"} { - set obj [find_liberty_cell $obj] + set obj [find_liberty_cell $obj] } elseif {$list_type == "LibertyPort"} { - set obj [get_lib_pins $obj] + set obj [get_lib_pins $obj] } else { - sta_error 164 "unsupported object type $list_type." + sta_error 164 "unsupported object type $list_type." } } set index [lsearch $list $obj] diff --git a/tcl/Sta.tcl b/tcl/Sta.tcl index 60c9cc2b..65d9d950 100644 --- a/tcl/Sta.tcl +++ b/tcl/Sta.tcl @@ -30,6 +30,122 @@ namespace eval sta { # ################################################################ +define_cmd_args "define_scene" {name -mode mode_name\ + -liberty liberty_files \ + | -liberty_min liberty_min_files -liberty_max liberty_max_files\ + [-spef spef_file | -spef_min spef_min_file -spef_max spef_max_file]} + +proc define_scene { args } { + parse_key_args "define_scene" args \ + keys {-mode -liberty -liberty_min -liberty_max \ + -spef -spef_min -spef_max} \ + flags {} + + check_argc_eq1 "define_scene" $args + set name [lindex $args 0] + + if { [info exists keys(-mode)] } { + set mode_name $keys(-mode) + } else { + set mode_name [sta::cmd_mode_name] + } + + set liberty_min_files {} + set liberty_max_files {} + if { [info exists keys(-liberty)] } { + set liberty_files $keys(-liberty) + set liberty_min_files $liberty_files + set liberty_max_files $liberty_files + } else { + if { [info exists keys(-liberty_min)] && [info exists keys(-liberty_max)] } { + set liberty_min_files $keys(-liberty_min) + set liberty_max_files $keys(-liberty_max) + } else { + sta_error 483 "-liberty or -liberty_min and -liberty_max are required arguments." + } + } + + set spef_min_file "" + set spef_max_file "" + if { [info exists keys(-spef)] } { + set spef_file $keys(-spef) + set spef_min_file $spef_file + set spef_max_file $spef_file + } elseif { [info exists keys(-spef_min)] && [info exists keys(-spef_max)] } { + set spef_min_file $keys(-spef_min) + set spef_max_file $keys(-spef_max) + } elseif { [info exists keys(-spef_min)] ||[info exists keys(-spef_max)] } { + sta_error 484 "-spef_min and -spef_max are required arguments." + } + + define_scene_cmd $name $mode_name \ + $liberty_min_files $liberty_max_files \ + $spef_min_file $spef_max_file +} + +# deprecated 11/22/2025 +define_cmd_args "define_corners" { corner1 [corner2]... } + +proc define_corners { args } { + if { [get_libs -quiet *] != {} } { + sta_error 482 "define_corners must be called before read_liberty." + } + if { [llength $args] == 0 } { + sta_error 577 "define_corners must define at least one corner." + } + define_scenes_cmd $args +} + +################################################################ + +define_cmd_args "set_scene" {scene_name} + +proc set_scene { args } { + check_argc_eq1 "set_scene" $args + set_scene_cmd [lindex $args 0] +} + +################################################################ + +define_cmd_args "get_scenes" {[-modes mode_names] scene_names} + +proc get_scenes { args } { + parse_key_args "get_scenes" args keys {-modes} flags {} + check_argc_eq0or1 "get_scenes" $args + + if { [llength $args] == 0 } { + set scene_name "*" + } else { + set scene_name [lindex $args 0] + } + set mode_names {} + if { [info exists keys(-modes)] } { + set mode_names $keys(-modes) + return [find_mode_scenes_matching $scene_name $mode_names] + } else { + return [find_scenes_matching $scene_name] + } +} + +################################################################ + +define_cmd_args "get_modes" {mode_name} + +proc get_modes { args } { + return [find_modes [lindex $args 0]] +} + +################################################################ + +define_cmd_args "set_mode" {mode_name} + +proc set_mode { args } { + check_argc_eq1 "set_mode" $args + set_mode_cmd [lindex $args 0] +} + +################################################################ + define_cmd_args "get_fanin" \ {-to sink_list [-flat] [-only_cells] [-startpoints_only]\ [-levels level_count] [-pin_levels pin_count]\ @@ -85,10 +201,10 @@ proc get_fanin { args } { } if { $only_insts } { return [find_fanin_insts $pins $flat $startpoints_only \ - $inst_levels $pin_levels $thru_disabled $thru_constants] + $inst_levels $pin_levels $thru_disabled $thru_constants] } else { return [find_fanin_pins $pins $flat $startpoints_only \ - $inst_levels $pin_levels $thru_disabled $thru_constants] + $inst_levels $pin_levels $thru_disabled $thru_constants] } } @@ -143,10 +259,10 @@ proc get_fanout { args } { } if { $only_insts } { return [find_fanout_insts $pins $flat $endpoints_only \ - $inst_levels $pin_levels $thru_disabled $thru_constants] + $inst_levels $pin_levels $thru_disabled $thru_constants] } else { return [find_fanout_pins $pins $flat $endpoints_only \ - $inst_levels $pin_levels $thru_disabled $thru_constants] + $inst_levels $pin_levels $thru_disabled $thru_constants] } } @@ -167,15 +283,15 @@ proc get_timing_edges_cmd { cmd cmd_args } { set arcs {} if { [info exists keys(-of_objects)] } { if { [info exists keys(-from)] \ - || [info exists keys(-from)] } { + || [info exists keys(-from)] } { sta_error 540 "-from/-to arguments not supported with -of_objects." } set arcs [get_timing_arcs_objects $keys(-of_objects)] } elseif { [info exists keys(-from)] \ - && [info exists keys(-to)] } { + && [info exists keys(-to)] } { set arcs [get_timing_arcs_from_to \ - [get_port_pin_error "from" $keys(-from)] \ - [get_port_pin_error "to" $keys(-to)]] + [get_port_pin_error "from" $keys(-from)] \ + [get_port_pin_error "to" $keys(-to)]] } elseif { [info exists keys(-from)] } { set arcs [get_timing_arcs_from $keys(-from)] } elseif { [info exists keys(-to)] } { @@ -214,10 +330,10 @@ proc instance_edges { inst } { foreach vertex [$pin vertices] { set edge_iter [$vertex out_edge_iterator] while {[$edge_iter has_next]} { - set edge [$edge_iter next] - if { [$edge role] != "wire" } { - lappend edges $edge - } + set edge [$edge_iter next] + if { [$edge role] != "wire" } { + lappend edges $edge + } } $edge_iter finish } @@ -234,10 +350,10 @@ proc get_timing_arcs_from_to { from_pin_arg to_pin_arg } { foreach to_vertex [$to_pin vertices] { set edge_iter [$from_vertex out_edge_iterator] while {[$edge_iter has_next]} { - set edge [$edge_iter next] - if { [$edge to] == $to_vertex } { - lappend edges $edge - } + set edge [$edge_iter next] + if { [$edge to] == $to_vertex } { + lappend edges $edge + } } $edge_iter finish } @@ -304,7 +420,7 @@ proc report_clock1 { clk } { } else { set wave "" foreach edge $waveform { - set wave "$wave[format "%10s" [format_time $edge $digits]]" + set wave "$wave[format %10s [format_time $edge $digits]]" } } if {[$clk is_generated]} { diff --git a/tcl/StaTclTypes.i b/tcl/StaTclTypes.i index f4c0e384..e5b68051 100644 --- a/tcl/StaTclTypes.i +++ b/tcl/StaTclTypes.i @@ -30,7 +30,6 @@ #include "StringSet.hh" #include "StringSeq.hh" #include "PatternMatch.hh" -#include "Vector.hh" #include "Network.hh" #include "Liberty.hh" #include "FuncExpr.hh" @@ -40,7 +39,7 @@ #include "Graph.hh" #include "NetworkClass.hh" #include "Clock.hh" -#include "Corner.hh" +#include "Scene.hh" #include "Search.hh" #include "Path.hh" #include "search/Tag.hh" @@ -53,15 +52,15 @@ namespace sta { -typedef MinPulseWidthCheckSeq::Iterator MinPulseWidthCheckSeqIterator; typedef MinMaxAll MinMaxAllNull; +typedef std::vector StdStringSeq; #if TCL_MAJOR_VERSION < 9 typedef int Tcl_Size; #endif template -Vector * +std::vector * tclListSeqPtr(Tcl_Obj *const source, swig_type_info *swig_type, Tcl_Interp *interp) @@ -71,7 +70,7 @@ tclListSeqPtr(Tcl_Obj *const source, if (Tcl_ListObjGetElements(interp, source, &argc, &argv) == TCL_OK && argc > 0) { - Vector *seq = new Vector; + std::vector *seq = new std::vector; for (int i = 0; i < argc; i++) { void *obj; // Ignore returned TCL_ERROR because can't get swig_type_info. @@ -276,8 +275,8 @@ using namespace sta; //////////////////////////////////////////////////////////////// // String that is deleted after crossing over to tcland. -%typemap(out) string { - string &str = $1; +%typemap(out) std::string { + std::string &str = $1; // String is volatile because it is deleted. Tcl_SetResult(interp, const_cast(str.c_str()), TCL_VOLATILE); } @@ -302,6 +301,14 @@ using namespace sta; $1 = tclListSetStdString($input, interp); } +%typemap(in) StdStringSeq { + $1 = tclListSeqStdString($input, interp); +} + +%typemap(in) StdStringSeq* { + $1 = tclListSeqStdString($input, interp); +} + %typemap(out) StringSeq* { StringSeq *strs = $1; Tcl_Obj *list = Tcl_NewListObj(0, nullptr); @@ -322,6 +329,14 @@ using namespace sta; Tcl_SetObjResult(interp, list); } +%typemap(in) StdStringSet* { + $1 = tclListSetStdString($input, interp); +} + +%typemap(in) StdStringSeq { + $1 = tclListSeqStdString($input, interp); +} + %typemap(out) StdStringSeq { StdStringSeq &strs = $1; Tcl_Obj *list = Tcl_NewListObj(0, nullptr); @@ -578,6 +593,10 @@ using namespace sta; $1 = tclListSeqPtr($input, SWIGTYPE_p_Instance, interp); } +%typemap(in) InstanceSeq { + $1 = tclListSeq($input, SWIGTYPE_p_Instance, interp); + } + %typemap(out) InstanceSeq { seqTclList($1, SWIGTYPE_p_Instance, interp); } @@ -922,7 +941,7 @@ using namespace sta; || stringEqual(arg, "min")) $1 = const_cast(MinMax::min()); else if (stringEqual(arg, "setup") - || stringEqual(arg, "max")) + || stringEqual(arg, "max")) $1 = const_cast(MinMax::max()); else { tclArgError(interp, 2162, "%s not setup, hold, min or max.", arg); @@ -939,13 +958,14 @@ using namespace sta; || stringEqual(arg, "min")) $1 = const_cast(SetupHoldAll::min()); else if (stringEqual(arg, "setup") - || stringEqual(arg, "max")) + || stringEqual(arg, "max")) $1 = const_cast(SetupHoldAll::max()); else if (stringEqual(arg, "setup_hold") - || stringEqual(arg, "min_max")) + || stringEqual(arg, "min_max")) $1 = const_cast(SetupHoldAll::all()); else { - tclArgError(interp, 2163, "%s not setup, hold, setup_hold, min, max or min_max.", arg); + tclArgError(interp, 2163, "%s not setup, hold, setup_hold, min, max or min_max.", + arg); return TCL_ERROR; } } @@ -1109,16 +1129,12 @@ using namespace sta; %typemap(out) CheckErrorSeq & { Tcl_Obj *error_list = Tcl_NewListObj(0, nullptr); CheckErrorSeq *check_errors = $1; - CheckErrorSeq::Iterator check_iter(check_errors); - while (check_iter.hasNext()) { - CheckError *error = check_iter.next(); + for (CheckError *error : *check_errors) { Tcl_Obj *string_list = Tcl_NewListObj(0, nullptr); - CheckError::Iterator string_iter(error); - while (string_iter.hasNext()) { - const char *str = string_iter.next(); + for (const char *str : *error) { size_t str_len = strlen(str); Tcl_Obj *obj = Tcl_NewStringObj(const_cast(str), - static_cast(str_len)); + static_cast(str_len)); Tcl_ListObjAppendElement(interp, string_list, obj); } Tcl_ListObjAppendElement(interp, error_list, string_list); @@ -1153,11 +1169,6 @@ using namespace sta; seqTclList($1, SWIGTYPE_p_PathEnd, interp); } -%typemap(out) MinPulseWidthCheckSeqIterator* { - Tcl_Obj *obj = SWIG_NewInstanceObj($1, $1_descriptor, false); - Tcl_SetObjResult(interp, obj); -} - %typemap(out) PathSeq* { Tcl_Obj *obj = SWIG_NewInstanceObj($1, $1_descriptor, false); Tcl_SetObjResult(interp, obj); @@ -1174,21 +1185,6 @@ using namespace sta; Tcl_SetObjResult(interp, list); } -%typemap(out) MinPulseWidthCheck* { - Tcl_Obj *obj = SWIG_NewInstanceObj($1, $1_descriptor, false); - Tcl_SetObjResult(interp, obj); -} - -%typemap(out) MinPulseWidthCheckSeq & { - Tcl_Obj *obj = SWIG_NewInstanceObj($1, $1_descriptor, false); - Tcl_SetObjResult(interp, obj); -} - -%typemap(out) MinPulseWidthCheckSeqIterator & { - Tcl_Obj *obj = SWIG_NewInstanceObj($1, $1_descriptor, false); - Tcl_SetObjResult(interp, obj); -} - %typemap(out) VertexPathIterator* { Tcl_Obj *obj = SWIG_NewInstanceObj($1, $1_descriptor, false); Tcl_SetObjResult(interp, obj); @@ -1247,24 +1243,107 @@ using namespace sta; Tcl_SetObjResult(interp,Tcl_NewDoubleObj(delayAsFloat($1))); } -%typemap(in) PathGroupNameSet* { - $1 = tclListSetConstChar($input, interp); -} - %typemap(in) StringSet* { $1 = tclListSetConstChar($input, interp); } -%typemap(out) Corner* { - Tcl_Obj *obj = SWIG_NewInstanceObj($1, $1_descriptor, false); - Tcl_SetObjResult(interp, obj); +%typemap(out) Mode* { + const Mode *mode = $1; + if (mode) + Tcl_SetResult(interp, const_cast($1->name().c_str()), TCL_VOLATILE); + else + Tcl_SetResult(interp, const_cast("NULL"), TCL_STATIC); } -%typemap(out) Corners* { +%typemap(in) ModeSeq { + Tcl_Size argc; + Tcl_Obj **argv; + + Sta *sta = Sta::sta(); + std::vector seq; + if (Tcl_ListObjGetElements(interp, $input, &argc, &argv) == TCL_OK + && argc > 0) { + for (int i = 0; i < argc; i++) { + int length; + const char *mode_name = Tcl_GetStringFromObj(argv[i], &length); + Mode *mode = sta->findMode(mode_name); + if (mode) + seq.push_back(mode); + else { + tclArgError(interp, 2174, "mode %s not found.", mode_name); + return TCL_ERROR; + } + } + } + $1 = seq; +} + +%typemap(out) ModeSeq { Tcl_Obj *list = Tcl_NewListObj(0, nullptr); - Corners *corners = $1; - for (Corner *corner : *corners) { - Tcl_Obj *obj = SWIG_NewInstanceObj(corner, SWIGTYPE_p_Corner, false); + ModeSeq &modes = $1; + for (Mode *mode : modes) { + const std::string &mode_name = mode->name(); + Tcl_Obj *obj = Tcl_NewStringObj(mode_name.c_str(), mode_name.size()); + Tcl_ListObjAppendElement(interp, list, obj); + } + Tcl_SetObjResult(interp, list); +} + +%typemap(in) Scene* { + sta::Sta *sta = Sta::sta(); + int length; + char *scene_name = Tcl_GetStringFromObj($input, &length); + // parse_scene_or_all support depreated 11/21/2025 + if (stringEq(scene_name, "NULL")) + $1 = nullptr; + else { + Scene *scene = sta->findScene(scene_name); + if (scene) + $1 = scene; + else { + tclArgError(interp, 2173, "scene %s not found.", scene_name); + return TCL_ERROR; + } + } +} + +%typemap(out) Scene* { + const Scene *scene = $1; + if (scene) + Tcl_SetResult(interp, const_cast($1->name().c_str()), TCL_VOLATILE); + else + Tcl_SetResult(interp, const_cast("NULL"), TCL_STATIC); +} + +%typemap(in) SceneSeq { + Tcl_Size argc; + Tcl_Obj **argv; + + Sta *sta = Sta::sta(); + std::vector seq; + if (Tcl_ListObjGetElements(interp, $input, &argc, &argv) == TCL_OK + && argc > 0) { + for (int i = 0; i < argc; i++) { + int length; + const char *scene_name = Tcl_GetStringFromObj(argv[i], &length); + Scene *scene = sta->findScene(scene_name); + if (scene) + seq.push_back(scene); + else { + tclArgError(interp, 2172, "scene %s not found.", scene_name); + return TCL_ERROR; + } + } + } + $1 = seq; +} + +%typemap(out) SceneSeq { + Tcl_Obj *list = Tcl_NewListObj(0, nullptr); + SceneSeq &scenes = $1; + for (Scene *scene : scenes) { + const std::string &scene_name = scene->name(); + Tcl_Obj *obj = Tcl_NewStringObj(scene_name.c_str(), scene_name.size()); Tcl_ListObjAppendElement(interp, list, obj); } Tcl_SetObjResult(interp, list); @@ -1279,108 +1358,103 @@ using namespace sta; %typemap(out) PropertyValue { PropertyValue value = $1; switch (value.type()) { - case PropertyValue::Type::type_none: + case PropertyValue::Type::none: Tcl_SetResult(interp, const_cast(""), TCL_STATIC); break; - case PropertyValue::Type::type_string: + case PropertyValue::Type::string: Tcl_SetResult(interp, const_cast(value.stringValue()), TCL_VOLATILE); break; - case PropertyValue::Type::type_float: { + case PropertyValue::Type::float_: { const Unit *unit = value.unit(); const char *float_string = unit->asString(value.floatValue(), 6); Tcl_SetResult(interp, const_cast(float_string), TCL_VOLATILE); } break; - case PropertyValue::Type::type_bool: { + case PropertyValue::Type::bool_: { const char *bool_string = value.boolValue() ? "1" : "0"; Tcl_SetResult(interp, const_cast(bool_string), TCL_STATIC); } break; - case PropertyValue::Type::type_library: { + case PropertyValue::Type::library: { Tcl_Obj *obj = SWIG_NewInstanceObj(const_cast(value.library()), - SWIGTYPE_p_Library, false); + SWIGTYPE_p_Library, false); Tcl_SetObjResult(interp, obj); } break; - case PropertyValue::Type::type_cell: { + case PropertyValue::Type::cell: { Tcl_Obj *obj = SWIG_NewInstanceObj(const_cast(value.cell()), - SWIGTYPE_p_Cell, false); + SWIGTYPE_p_Cell, false); Tcl_SetObjResult(interp, obj); } break; - case PropertyValue::Type::type_port: { + case PropertyValue::Type::port: { Tcl_Obj *obj = SWIG_NewInstanceObj(const_cast(value.port()), - SWIGTYPE_p_Port, false); + SWIGTYPE_p_Port, false); Tcl_SetObjResult(interp, obj); } break; - case PropertyValue::Type::type_liberty_library: { + case PropertyValue::Type::liberty_library: { Tcl_Obj *obj = SWIG_NewInstanceObj(const_cast(value.libertyLibrary()), - SWIGTYPE_p_LibertyLibrary, false); + SWIGTYPE_p_LibertyLibrary, false); Tcl_SetObjResult(interp, obj); } break; - case PropertyValue::Type::type_liberty_cell: { + case PropertyValue::Type::liberty_cell: { Tcl_Obj *obj = SWIG_NewInstanceObj(const_cast(value.libertyCell()), - SWIGTYPE_p_LibertyCell, false); + SWIGTYPE_p_LibertyCell, false); Tcl_SetObjResult(interp, obj); } break; - case PropertyValue::Type::type_liberty_port: { + case PropertyValue::Type::liberty_port: { Tcl_Obj *obj = SWIG_NewInstanceObj(const_cast(value.libertyPort()), - SWIGTYPE_p_LibertyPort, false); + SWIGTYPE_p_LibertyPort, false); Tcl_SetObjResult(interp, obj); } break; - case PropertyValue::Type::type_instance: { + case PropertyValue::Type::instance: { Tcl_Obj *obj = SWIG_NewInstanceObj(const_cast(value.instance()), - SWIGTYPE_p_Instance, false); + SWIGTYPE_p_Instance, false); Tcl_SetObjResult(interp, obj); } break; - case PropertyValue::Type::type_pin: { + case PropertyValue::Type::pin: { Tcl_Obj *obj = SWIG_NewInstanceObj(const_cast(value.pin()), SWIGTYPE_p_Pin, false); Tcl_SetObjResult(interp, obj); } break; - case PropertyValue::Type::type_pins: { + case PropertyValue::Type::pins: { Tcl_Obj *list = Tcl_NewListObj(0, nullptr); - PinSeq *pins = value.pins(); - PinSeq::Iterator pin_iter(pins); - while (pin_iter.hasNext()) { - const Pin *pin = pin_iter.next(); + for (const Pin *pin : *value.pins()) { Tcl_Obj *obj = SWIG_NewInstanceObj(const_cast(pin), SWIGTYPE_p_Pin, false); Tcl_ListObjAppendElement(interp, list, obj); } Tcl_SetObjResult(interp, list); } break; - case PropertyValue::Type::type_net: { + case PropertyValue::Type::net: { Tcl_Obj *obj = SWIG_NewInstanceObj(const_cast(value.net()), - SWIGTYPE_p_Net, false); + SWIGTYPE_p_Net, false); Tcl_SetObjResult(interp, obj); } break; - case PropertyValue::Type::type_clk: { + case PropertyValue::Type::clk: { Tcl_Obj *obj = SWIG_NewInstanceObj(const_cast(value.clock()), - SWIGTYPE_p_Clock, false); + SWIGTYPE_p_Clock, false); Tcl_SetObjResult(interp, obj); } break; - case PropertyValue::Type::type_clks: { + case PropertyValue::Type::clks: { Tcl_Obj *list = Tcl_NewListObj(0, nullptr); ClockSeq *clks = value.clocks(); - ClockSeq::Iterator clk_iter(clks); - while (clk_iter.hasNext()) { - Clock *clk = clk_iter.next(); + for (Clock *clk : *clks) { Tcl_Obj *obj = SWIG_NewInstanceObj(clk, SWIGTYPE_p_Clock, false); Tcl_ListObjAppendElement(interp, list, obj); } Tcl_SetObjResult(interp, list); } break; - case PropertyValue::Type::type_paths: { + case PropertyValue::Type::paths: { Tcl_Obj *list = Tcl_NewListObj(0, nullptr); for (const Path *path : *value.paths()) { Tcl_Obj *obj = SWIG_NewInstanceObj(const_cast(path), SWIGTYPE_p_Path, false); @@ -1389,7 +1463,7 @@ using namespace sta; Tcl_SetObjResult(interp, list); } break; - case PropertyValue::Type::type_pwr_activity: { + case PropertyValue::Type::pwr_activity: { PwrActivity activity = value.pwrActivity(); Tcl_Obj *list = Tcl_NewListObj(0, nullptr); Tcl_Obj *obj; diff --git a/tcl/TclTypeHelpers.cc b/tcl/TclTypeHelpers.cc index f5d73442..c5cc219d 100644 --- a/tcl/TclTypeHelpers.cc +++ b/tcl/TclTypeHelpers.cc @@ -32,7 +32,7 @@ namespace sta { StringSet * tclListSetConstChar(Tcl_Obj *const source, - Tcl_Interp *interp) + Tcl_Interp *interp) { Tcl_Size argc; Tcl_Obj **argv; @@ -52,7 +52,7 @@ tclListSetConstChar(Tcl_Obj *const source, StringSeq * tclListSeqConstChar(Tcl_Obj *const source, - Tcl_Interp *interp) + Tcl_Interp *interp) { Tcl_Size argc; Tcl_Obj **argv; @@ -70,9 +70,47 @@ tclListSeqConstChar(Tcl_Obj *const source, return nullptr; } +StdStringSeq +tclListSeqStdString(Tcl_Obj *const source, + Tcl_Interp *interp) +{ + Tcl_Size argc; + Tcl_Obj **argv; + + StdStringSeq seq; + if (Tcl_ListObjGetElements(interp, source, &argc, &argv) == TCL_OK) { + for (int i = 0; i < argc; i++) { + int length; + const char *str = Tcl_GetStringFromObj(argv[i], &length); + seq.push_back(str); + } + } + return seq; +} + +StdStringSeq * +tclListSeqStdStringPtr(Tcl_Obj *const source, + Tcl_Interp *interp) +{ + Tcl_Size argc; + Tcl_Obj **argv; + + if (Tcl_ListObjGetElements(interp, source, &argc, &argv) == TCL_OK) { + StdStringSeq *seq = new StdStringSeq; + for (int i = 0; i < argc; i++) { + int length; + const char *str = Tcl_GetStringFromObj(argv[i], &length); + seq->push_back(str); + } + return seq; + } + else + return nullptr; +} + StdStringSet * tclListSetStdString(Tcl_Obj *const source, - Tcl_Interp *interp) + Tcl_Interp *interp) { Tcl_Size argc; Tcl_Obj **argv; @@ -90,7 +128,6 @@ tclListSetStdString(Tcl_Obj *const source, return nullptr; } - void tclArgError(Tcl_Interp *interp, int id, @@ -107,10 +144,10 @@ tclArgError(Tcl_Interp *interp, void objectListNext(const char *list, - const char *type, - // Return values. - bool &type_match, - const char *&next) + const char *type, + // Return values. + bool &type_match, + const char *&next) { // Default return values (failure). type_match = false; @@ -122,21 +159,21 @@ objectListNext(const char *list, while (*s && isxdigit(*s)) s++; if ((s - list - 1) == sizeof(void*) * 2 - && *s && *s++ == '_' - && *s && *s++ == 'p' - && *s && *s++ == '_') { + && *s && *s++ == '_' + && *s && *s++ == 'p' + && *s && *s++ == '_') { const char *t = type; while (*s && *s != ' ') { - if (*s != *t) - return; - s++; - t++; + if (*s != *t) + return; + s++; + t++; } type_match = true; if (*s) - next = s + 1; + next = s + 1; else - next = nullptr; + next = nullptr; } } } diff --git a/tcl/Util.tcl b/tcl/Util.tcl index ad47cdce..49028698 100644 --- a/tcl/Util.tcl +++ b/tcl/Util.tcl @@ -37,7 +37,7 @@ namespace eval sta { # $flag_var(flag) -> 1 if the flag is present # Keys and flags are removed from arg_var in the caller. proc parse_key_args { cmd arg_var key_var keys {flag_var ""} {flags {}} \ - {unknown_key_is_error 1} } { + {unknown_key_is_error 1} } { upvar 1 $arg_var args upvar 1 $key_var key_value upvar 1 $flag_var flag_present @@ -47,41 +47,41 @@ proc parse_key_args { cmd arg_var key_var keys {flag_var ""} {flags {}} \ if { [is_keyword_arg $arg] } { set key_index [lsearch -exact $keys $arg] if { $key_index >= 0 } { - set key $arg - if { [llength $args] == 1 } { - sta_error 560 "$cmd $key missing value." - } - set key_value($key) [lindex $args 1] - set args [lrange $args 1 end] + set key $arg + if { [llength $args] == 1 } { + sta_error 560 "$cmd $key missing value." + } + set key_value($key) [lindex $args 1] + set args [lrange $args 1 end] } else { - set flag_index [lsearch -exact $flags $arg] - if { $flag_index >= 0 } { - set flag_present($arg) 1 - } else { - # No exact keyword/flag match found. - # Try finding a keyword/flag that begins with - # the same substring. - set wild_arg "${arg}*" - set key_index [lsearch -glob $keys $wild_arg] - if { $key_index >= 0 } { - set key [lindex $keys $key_index] - if { [llength $args] == 1 } { - sta_error 561 "$cmd $key missing value." - } - set key_value($key) [lindex $args 1] - set args [lrange $args 1 end] - } else { - set flag_index [lsearch -glob $flags $wild_arg] - if { $flag_index >= 0 } { - set flag [lindex $flags $flag_index] - set flag_present($flag) 1 - } elseif { $unknown_key_is_error } { - sta_error 562 "$cmd $arg is not a known keyword or flag." - } else { - lappend args_rtn $arg - } - } - } + set flag_index [lsearch -exact $flags $arg] + if { $flag_index >= 0 } { + set flag_present($arg) 1 + } else { + # No exact keyword/flag match found. + # Try finding a keyword/flag that begins with + # the same substring. + set wild_arg "${arg}*" + set key_index [lsearch -glob $keys $wild_arg] + if { $key_index >= 0 } { + set key [lindex $keys $key_index] + if { [llength $args] == 1 } { + sta_error 561 "$cmd $key missing value." + } + set key_value($key) [lindex $args 1] + set args [lrange $args 1 end] + } else { + set flag_index [lsearch -glob $flags $wild_arg] + if { $flag_index >= 0 } { + set flag [lindex $flags $flag_index] + set flag_present($flag) 1 + } elseif { $unknown_key_is_error } { + sta_error 562 "$cmd $arg is not a known keyword or flag." + } else { + lappend args_rtn $arg + } + } + } } } else { lappend args_rtn $arg @@ -109,8 +109,8 @@ proc check_for_key_args { cmd arg_var } { proc is_keyword_arg { arg } { if { [string length $arg] >= 2 \ - && [string index $arg 0] == "-" \ - && [string is alpha [string index $arg 1]] } { + && [string index $arg 0] == "-" \ + && [string is alpha [string index $arg 1]] } { return 1 } else { return 0 @@ -124,11 +124,11 @@ proc is_keyword_arg { arg } { # The value of the last expression in the body is returned. proc proc_redirect { proc_name body } { set proc_body [concat "proc $proc_name { args } {" \ - "global errorCode errorInfo;" \ - "set redirect \[parse_redirect_args args\];" \ - "set code \[catch {" $body "} ret \];" \ - "if {\$redirect} { redirect_file_end };" \ - "if {\$code == 1} {return -code \$code -errorcode \$errorCode -errorinfo \$errorInfo \$ret} else {return \$ret} }" ] + "global errorCode errorInfo;" \ + "set redirect \[parse_redirect_args args\];" \ + "set code \[catch {" $body "} ret \];" \ + "if {\$redirect} { redirect_file_end };" \ + "if {\$code == 1} {return -code \$code -errorcode \$errorCode -errorinfo \$errorInfo \$ret} else {return \$ret} }" ] eval $proc_body } diff --git a/tcl/Variables.tcl b/tcl/Variables.tcl index a019c295..336e7286 100644 --- a/tcl/Variables.tcl +++ b/tcl/Variables.tcl @@ -41,7 +41,7 @@ proc trace_report_default_digits { name1 name2 op } { if { $op == "w" } { if { !([string is integer $sta_report_default_digits] \ - && $sta_report_default_digits >= 0) } { + && $sta_report_default_digits >= 0) } { sta_error 590 "sta_report_default_digits must be a positive integer." } } @@ -96,14 +96,6 @@ proc trace_internal_bidirect_instance_paths_enabled { name1 name2 op } { bidirect_inst_paths_enabled set_bidirect_inst_paths_enabled } -trace variable ::sta_bidirect_net_paths_enabled "rw" \ - sta::trace_bidirect_net_paths_enabled - -proc trace_bidirect_net_paths_enabled { name1 name2 op } { - trace_boolean_var $op ::sta_bidirect_net_paths_enabled \ - bidirect_net_paths_enabled set_bidirect_net_paths_enabled -} - trace variable ::sta_clock_through_tristate_enabled "rw" \ sta::trace_clock_through_tristate_enabled diff --git a/test/disconnect_mcp_pin.ok b/test/disconnect_mcp_pin.ok index a0645c2b..c05e6a3b 100644 --- a/test/disconnect_mcp_pin.ok +++ b/test/disconnect_mcp_pin.ok @@ -1,7 +1,7 @@ -Warning: disconnect_mcp_pin.tcl line 15, 'u0/A' is not a valid endpoint. -Warning: disconnect_mcp_pin.tcl line 16, 'u1/A' is not a valid endpoint. -Warning: disconnect_mcp_pin.tcl line 17, 'u0/A' is not a valid endpoint. -Warning: disconnect_mcp_pin.tcl line 18, 'u1/A' is not a valid endpoint. +Warning 1551: disconnect_mcp_pin.tcl line 15, 'u0/A' is not a valid endpoint. +Warning 1551: disconnect_mcp_pin.tcl line 16, 'u1/A' is not a valid endpoint. +Warning 1551: disconnect_mcp_pin.tcl line 17, 'u0/A' is not a valid endpoint. +Warning 1551: disconnect_mcp_pin.tcl line 18, 'u1/A' is not a valid endpoint. Startpoint: data_in[1] (input port clocked by clk) Endpoint: u1 (falling edge-triggered data to data check clocked by clk) Path Group: clk diff --git a/test/liberty_arcs_one2one_1.ok b/test/liberty_arcs_one2one_1.ok index 64c906ff..dc99d32b 100644 --- a/test/liberty_arcs_one2one_1.ok +++ b/test/liberty_arcs_one2one_1.ok @@ -1,4 +1,4 @@ -Warning: liberty_arcs_one2one_1.lib line 48, timing port A and related port Y are different sizes. +Warning 1216: liberty_arcs_one2one_1.lib line 48, timing port A and related port Y are different sizes. report_edges -from partial_wide_inv_cell/A[0] A[0] -> Y[0] combinational ^ -> v 1.00:1.00 diff --git a/test/liberty_arcs_one2one_2.ok b/test/liberty_arcs_one2one_2.ok index 879b8a74..323145d3 100644 --- a/test/liberty_arcs_one2one_2.ok +++ b/test/liberty_arcs_one2one_2.ok @@ -1,4 +1,4 @@ -Warning: liberty_arcs_one2one_2.lib line 48, timing port A and related port Y are different sizes. +Warning 1216: liberty_arcs_one2one_2.lib line 48, timing port A and related port Y are different sizes. report_edges -to partial_wide_inv_cell/Y[0] A[0] -> Y[0] combinational ^ -> v 1.00:1.00 diff --git a/test/mcmm3.ok b/test/mcmm3.ok new file mode 100644 index 00000000..e220a881 --- /dev/null +++ b/test/mcmm3.ok @@ -0,0 +1,208 @@ +Startpoint: r2 (rising edge-triggered flip-flop clocked by m1_clk) +Endpoint: r3 (rising edge-triggered flip-flop clocked by m1_clk) +Path Group: m1_clk +Path Type: max +Mode: mode1 +Corner: scene1 + + Delay Time Description +--------------------------------------------------------- + 0.00 0.00 clock m1_clk (rise edge) + 0.00 0.00 clock network delay (ideal) + 0.00 0.00 ^ r2/CLK (DFFHQx4_ASAP7_75t_R) + 52.65 52.65 ^ r2/Q (DFFHQx4_ASAP7_75t_R) + 49.30 101.95 ^ u1/Y (BUFx2_ASAP7_75t_R) + 61.03 162.97 ^ u2/Y (AND2x2_ASAP7_75t_R) + 15.77 178.74 ^ r3/D (DFFHQx4_ASAP7_75t_R) + 178.74 data arrival time + +1000.00 1000.00 clock m1_clk (rise edge) + 0.00 1000.00 clock network delay (ideal) + 0.00 1000.00 clock reconvergence pessimism + 1000.00 ^ r3/CLK (DFFHQx4_ASAP7_75t_R) + -13.66 986.34 library setup time + 986.34 data required time +--------------------------------------------------------- + 986.34 data required time + -178.74 data arrival time +--------------------------------------------------------- + 807.59 slack (MET) + + +Startpoint: r1 (rising edge-triggered flip-flop clocked by m2_clk) +Endpoint: r3 (rising edge-triggered flip-flop clocked by m2_clk) +Path Group: m2_clk +Path Type: max +Mode: mode2 +Corner: scene2 + + Delay Time Description +--------------------------------------------------------- + 0.00 0.00 clock m2_clk (rise edge) + 0.00 0.00 clock network delay (ideal) + 0.00 0.00 ^ r1/CLK (DFFHQx4_ASAP7_75t_R) + 123.56 123.56 ^ r1/Q (DFFHQx4_ASAP7_75t_R) + 112.01 235.57 ^ u2/Y (AND2x2_ASAP7_75t_R) + 22.14 257.71 ^ r3/D (DFFHQx4_ASAP7_75t_R) + 257.71 data arrival time + + 500.00 500.00 clock m2_clk (rise edge) + 0.00 500.00 clock network delay (ideal) + 0.00 500.00 clock reconvergence pessimism + 500.00 ^ r3/CLK (DFFHQx4_ASAP7_75t_R) + -40.66 459.34 library setup time + 459.34 data required time +--------------------------------------------------------- + 459.34 data required time + -257.71 data arrival time +--------------------------------------------------------- + 201.62 slack (MET) + + +Startpoint: r2 (rising edge-triggered flip-flop clocked by m1_clk) +Endpoint: r3 (rising edge-triggered flip-flop clocked by m1_clk) +Path Group: m1_clk +Path Type: max +Mode: mode1 +Corner: scene1 + + Delay Time Description +--------------------------------------------------------- + 0.00 0.00 clock m1_clk (rise edge) + 0.00 0.00 clock network delay (ideal) + 0.00 0.00 ^ r2/CLK (DFFHQx4_ASAP7_75t_R) + 52.65 52.65 ^ r2/Q (DFFHQx4_ASAP7_75t_R) + 49.30 101.95 ^ u1/Y (BUFx2_ASAP7_75t_R) + 61.03 162.97 ^ u2/Y (AND2x2_ASAP7_75t_R) + 15.77 178.74 ^ r3/D (DFFHQx4_ASAP7_75t_R) + 178.74 data arrival time + +1000.00 1000.00 clock m1_clk (rise edge) + 0.00 1000.00 clock network delay (ideal) + 0.00 1000.00 clock reconvergence pessimism + 1000.00 ^ r3/CLK (DFFHQx4_ASAP7_75t_R) + -13.66 986.34 library setup time + 986.34 data required time +--------------------------------------------------------- + 986.34 data required time + -178.74 data arrival time +--------------------------------------------------------- + 807.59 slack (MET) + + +Startpoint: in1 (input port clocked by m1_clk) +Endpoint: r1 (rising edge-triggered flip-flop clocked by m1_clk) +Path Group: m1_clk +Path Type: max +Mode: mode1 +Corner: scene1 + + Delay Time Description +--------------------------------------------------------- + 0.00 0.00 clock m1_clk (rise edge) + 0.00 0.00 clock network delay (ideal) + 100.00 100.00 ^ input external delay + 0.00 100.00 ^ in1 (in) + 12.28 112.28 ^ r1/D (DFFHQx4_ASAP7_75t_R) + 112.28 data arrival time + +1000.00 1000.00 clock m1_clk (rise edge) + 0.00 1000.00 clock network delay (ideal) + 0.00 1000.00 clock reconvergence pessimism + 1000.00 ^ r1/CLK (DFFHQx4_ASAP7_75t_R) + -12.80 987.20 library setup time + 987.20 data required time +--------------------------------------------------------- + 987.20 data required time + -112.28 data arrival time +--------------------------------------------------------- + 874.92 slack (MET) + + +Startpoint: in2 (input port clocked by m1_clk) +Endpoint: r2 (rising edge-triggered flip-flop clocked by m1_clk) +Path Group: m1_clk +Path Type: max +Mode: mode1 +Corner: scene1 + + Delay Time Description +--------------------------------------------------------- + 0.00 0.00 clock m1_clk (rise edge) + 0.00 0.00 clock network delay (ideal) + 100.00 100.00 ^ input external delay + 0.00 100.00 ^ in2 (in) + 12.28 112.28 ^ r2/D (DFFHQx4_ASAP7_75t_R) + 112.28 data arrival time + +1000.00 1000.00 clock m1_clk (rise edge) + 0.00 1000.00 clock network delay (ideal) + 0.00 1000.00 clock reconvergence pessimism + 1000.00 ^ r2/CLK (DFFHQx4_ASAP7_75t_R) + -12.80 987.20 library setup time + 987.20 data required time +--------------------------------------------------------- + 987.20 data required time + -112.28 data arrival time +--------------------------------------------------------- + 874.92 slack (MET) + + +Startpoint: r1 (rising edge-triggered flip-flop clocked by m2_clk) +Endpoint: r3 (rising edge-triggered flip-flop clocked by m2_clk) +Path Group: m2_clk +Path Type: max +Mode: mode2 +Corner: scene2 + + Delay Time Description +--------------------------------------------------------- + 0.00 0.00 clock m2_clk (rise edge) + 0.00 0.00 clock network delay (ideal) + 0.00 0.00 ^ r1/CLK (DFFHQx4_ASAP7_75t_R) + 123.56 123.56 ^ r1/Q (DFFHQx4_ASAP7_75t_R) + 112.01 235.57 ^ u2/Y (AND2x2_ASAP7_75t_R) + 22.14 257.71 ^ r3/D (DFFHQx4_ASAP7_75t_R) + 257.71 data arrival time + + 500.00 500.00 clock m2_clk (rise edge) + 0.00 500.00 clock network delay (ideal) + 0.00 500.00 clock reconvergence pessimism + 500.00 ^ r3/CLK (DFFHQx4_ASAP7_75t_R) + -40.66 459.34 library setup time + 459.34 data required time +--------------------------------------------------------- + 459.34 data required time + -257.71 data arrival time +--------------------------------------------------------- + 201.62 slack (MET) + + +Startpoint: r3 (rising edge-triggered flip-flop clocked by m2_clk) +Endpoint: out (output port clocked by m2_clk) +Path Group: m2_clk +Path Type: max +Mode: mode2 +Corner: scene2 + + Delay Time Description +--------------------------------------------------------- + 0.00 0.00 clock m2_clk (rise edge) + 0.00 0.00 clock network delay (ideal) + 0.00 0.00 ^ r3/CLK (DFFHQx4_ASAP7_75t_R) + 123.30 123.30 ^ r3/Q (DFFHQx4_ASAP7_75t_R) + 19.50 142.80 ^ out (out) + 142.80 data arrival time + + 500.00 500.00 clock m2_clk (rise edge) + 0.00 500.00 clock network delay (ideal) + 0.00 500.00 clock reconvergence pessimism +-100.00 400.00 output external delay + 400.00 data required time +--------------------------------------------------------- + 400.00 data required time + -142.80 data arrival time +--------------------------------------------------------- + 257.20 slack (MET) + + diff --git a/test/power.ok b/test/power.ok index 19f4adfd..a79a9ab6 100644 --- a/test/power.ok +++ b/test/power.ok @@ -1,12 +1,12 @@ -Warning: gcd_sky130hd.v line 527, module sky130_fd_sc_hd__tapvpwrvgnd_1 not found. Creating black box for TAP_11. +Warning 198: gcd_sky130hd.v line 527, module sky130_fd_sc_hd__tapvpwrvgnd_1 not found. Creating black box for TAP_11. Group Internal Switching Leakage Total Power Power Power Power (Watts) ---------------------------------------------------------------- -Sequential 3.07e-04 4.76e-05 2.96e-10 3.54e-04 40.0% -Combinational 1.59e-04 2.05e-04 6.86e-10 3.64e-04 41.1% -Clock 4.68e-05 1.20e-04 2.30e-11 1.67e-04 18.9% +Sequential 3.06e-04 4.71e-05 2.96e-10 3.53e-04 40.1% +Combinational 1.57e-04 2.03e-04 6.86e-10 3.60e-04 40.9% +Clock 4.68e-05 1.20e-04 2.30e-11 1.67e-04 19.0% Macro 0.00e+00 0.00e+00 0.00e+00 0.00e+00 0.0% Pad 0.00e+00 0.00e+00 0.00e+00 0.00e+00 0.0% ---------------------------------------------------------------- -Total 5.12e-04 3.73e-04 1.00e-09 8.85e-04 100.0% - 57.8% 42.2% 0.0% +Total 5.10e-04 3.70e-04 1.00e-09 8.81e-04 100.0% + 57.9% 42.1% 0.0% diff --git a/test/power_json.tcl b/test/power_json.tcl index 7edf1d3c..108b81b2 100644 --- a/test/power_json.tcl +++ b/test/power_json.tcl @@ -1,4 +1,4 @@ -# report_power reg1_asap7 +# report_power json read_liberty asap7_small.lib.gz read_verilog reg1_asap7.v link_design top diff --git a/test/power_vcd.ok b/test/power_vcd.ok index 47a16002..5733375e 100644 --- a/test/power_vcd.ok +++ b/test/power_vcd.ok @@ -1,4 +1,4 @@ -Warning: gcd_sky130hd.v line 527, module sky130_fd_sc_hd__tapvpwrvgnd_1 not found. Creating black box for TAP_11. +Warning 198: gcd_sky130hd.v line 527, module sky130_fd_sc_hd__tapvpwrvgnd_1 not found. Creating black box for TAP_11. Annotated 937 pin activities. vcd 937 unannotated 0 diff --git a/test/prima3.ok b/test/prima3.ok index 98c9c3cd..a4ac1d9c 100644 --- a/test/prima3.ok +++ b/test/prima3.ok @@ -1,13 +1,3 @@ -Warning: asap7_simple.lib.gz line 71029, timing group from output port. -Warning: asap7_simple.lib.gz line 71505, timing group from output port. -Warning: asap7_simple.lib.gz line 71981, timing group from output port. -Warning: asap7_simple.lib.gz line 72457, timing group from output port. -Warning: asap7_simple.lib.gz line 72933, timing group from output port. -Warning: asap7_simple.lib.gz line 73409, timing group from output port. -Warning: asap7_simple.lib.gz line 73885, timing group from output port. -Warning: asap7_simple.lib.gz line 81795, timing group from output port. -Warning: asap7_simple.lib.gz line 82271, timing group from output port. -Warning: asap7_simple.lib.gz line 82747, timing group from output port. Startpoint: r2 (rising edge-triggered flip-flop clocked by clk) Endpoint: r3 (rising edge-triggered flip-flop clocked by clk) Path Group: clk diff --git a/test/regression.tcl b/test/regression.tcl index a6a86f97..447a85ad 100755 --- a/test/regression.tcl +++ b/test/regression.tcl @@ -84,8 +84,8 @@ proc parse_args {} { } elseif { $arg == "-threads" } { set threads [lindex $argv 1] if { !([string is integer $threads] || $threads == "max") } { - puts "Error: -threads arg $threads is not an integer or max." - exit 0 + puts "Error: -threads arg $threads is not an integer or max." + exit 0 } lappend app_options "-threads" lappend app_options $threads @@ -131,12 +131,12 @@ proc expand_tests { argv } { if { [info exists test_groups($arg)] } { set tests [concat $tests $test_groups($arg)] } elseif { [string first "*" $arg] != -1 \ - || [string first "?" $arg] != -1 } { + || [string first "?" $arg] != -1 } { # Find wildcard matches. foreach test [group_tests "all"] { - if [string match $arg $test] { - lappend tests $test - } + if [string match $arg $test] { + lappend tests $test + } } } elseif { [lsearch [group_tests "all"] $arg] != -1 } { lappend tests $arg @@ -175,52 +175,52 @@ proc run_test { test } { puts " *ERROR* [lrange $test_errors 1 end]" append_failure $test incr errors(error) - + # For some reason seg faults aren't echoed in the log - add them. if { [llength $test_errors] > 1 && [file exists $log_file] } { - set log_ch [open $log_file "a"] - puts $log_ch $test_errors - close $log_ch + set log_ch [open $log_file "a"] + puts $log_ch $test_errors + close $log_ch } # Report partial log diff anyway. if [file exists $ok_file] { - catch [concat exec diff $diff_options $ok_file $log_file \ - >> $diff_file] + catch [concat exec diff $diff_options $ok_file $log_file \ + >> $diff_file] } } else { set error_msg "" if { [lsearch $test_errors "MEMORY"] != -1 } { - append error_msg " *MEMORY*" - append_failure $test - incr errors(memory) + append error_msg " *MEMORY*" + append_failure $test + incr errors(memory) } if { [lsearch $test_errors "LEAK"] != -1 } { - append error_msg " *LEAK*" - append_failure $test - incr errors(leak) + append error_msg " *LEAK*" + append_failure $test + incr errors(leak) } if { $report_stats } { - append error_msg " [test_stats_summary $test]" + append error_msg " [test_stats_summary $test]" } if [file exists $ok_file] { - # Filter dos '/r's from log file. - set tmp_file [file join $result_dir $test.tmp] - exec tr -d "\r" < $log_file > $tmp_file - file rename -force $tmp_file $log_file - if [catch [concat exec diff $diff_options $ok_file $log_file \ - >> $diff_file]] { - puts " *FAIL*$error_msg" - append_failure $test - incr errors(fail) - } else { - puts " pass$error_msg" - } + # Filter dos '/r's from log file. + set tmp_file [file join $result_dir $test.tmp] + exec tr -d "\r" < $log_file > $tmp_file + file rename -force $tmp_file $log_file + if [catch [concat exec diff $diff_options $ok_file $log_file \ + >> $diff_file]] { + puts " *FAIL*$error_msg" + append_failure $test + incr errors(fail) + } else { + puts " pass$error_msg" + } } else { puts " *NO OK FILE*" - append_failure $test - incr errors(no_ok) + append_failure $test + incr errors(no_ok) } } } else { @@ -282,7 +282,6 @@ proc run_test_app { test cmd_file log_file } { proc run_test_plain { test cmd_file log_file } { global app_path app_options result_dir errorCode global report_stats - global test_expect_eror if { ![file exists $app_path] } { return "ERROR $app_path not found." @@ -299,25 +298,22 @@ proc run_test_plain { test cmd_file log_file } { } close $run_stream - if { [catch [concat exec $app_path $app_options $run_file >& $log_file]] \ - && ![info exists test_expect_eror($test)] } { + if { [catch [concat exec $app_path $app_options $run_file >& $log_file]] } { set signal [lindex $errorCode 2] set error [lindex $errorCode 3] # Error strings are not consistent across platforms but signal # names are. if { $signal == "SIGSEGV" } { - # Save corefiles to regression results directory. - set pid [lindex $errorCode 1] - set sys_corefile [test_sys_core_file $test $pid] - if { [file exists $sys_corefile] } { - file copy $sys_corefile [test_core_file $test] - } + # Save corefiles to regression results directory. + set pid [lindex $errorCode 1] + set sys_corefile [test_sys_core_file $test $pid] + if { [file exists $sys_corefile] } { + file copy $sys_corefile [test_core_file $test] + } } - cleanse_logfile $test $log_file return "ERROR $error" } file delete $run_file - cleanse_logfile $test $log_file return "" } } @@ -333,13 +329,12 @@ proc run_test_valgrind { test cmd_file log_file } { close $vg_stream set cmd [concat exec valgrind $valgrind_options \ - $app_path $app_options $vg_cmd_file >& $log_file] + $app_path $app_options $vg_cmd_file >& $log_file] set error_msg "" if { [catch $cmd] } { set error_msg "ERROR [lindex $errorCode 3]" } file delete $vg_cmd_file - cleanse_logfile $test $log_file set error_msg [concat $error_msg [cleanse_valgrind_logfile $test $log_file]] return $error_msg } @@ -386,13 +381,13 @@ proc cleanse_valgrind_logfile { test log_file } { if {[regexp "^==" $line]} { puts $valgrind $line if {[regexp $valgrind_leak_regexp $line]} { - set leaks 1 + set leaks 1 } if {[regexp $valgrind_mem_regexp $line]} { - set mem_errors 1 + set mem_errors 1 } if {[regexp $valgrind_shared_lib_failure_regexp $line]} { - set valgrind_shared_lib_failure 1 + set valgrind_shared_lib_failure 1 } } elseif {[regexp {^--[0-9]+} $line]} { # Valgrind notification line. @@ -459,8 +454,8 @@ proc found_errors {} { global errors return [expr $errors(error) != 0 || $errors(fail) != 0 \ - || $errors(no_cmd) != 0 || $errors(no_ok) != 0 \ - || $errors(memory) != 0 || $errors(leak) != 0] + || $errors(no_cmd) != 0 || $errors(no_ok) != 0 \ + || $errors(memory) != 0 || $errors(leak) != 0] } ################################################################ @@ -474,10 +469,10 @@ proc save_ok_main {} { if [file exists $failure_file] { set fail_ch [open $failure_file "r"] while { ! [eof $fail_ch] } { - set test [gets $fail_ch] - if { $test != "" } { - save_ok $test - } + set test [gets $fail_ch] + if { $test != "" } { + save_ok $test + } } close $fail_ch } diff --git a/test/regression_vars.tcl b/test/regression_vars.tcl index acf6906b..c1ed29ea 100644 --- a/test/regression_vars.tcl +++ b/test/regression_vars.tcl @@ -56,10 +56,6 @@ if { [exec "uname"] == "Darwin" } { append valgrind_options " --dsymutil=yes" } -proc cleanse_logfile { test log_file } { - # Nothing to be done here. -} - ################################################################ # Record a test in the regression suite. @@ -136,6 +132,7 @@ proc record_example_tests { tests } { record_example_tests { delay_calc min_max_delays + mcmm3 multi_corner power power_vcd diff --git a/test/report_json1.ok b/test/report_json1.ok index 51e8ae79..7f70fbf7 100644 --- a/test/report_json1.ok +++ b/test/report_json1.ok @@ -36,7 +36,7 @@ "net": "mid", "arrival": 3.296e-10, "capacitance": 1.949e-15, - "slew": 3.612e-11 + "slew": 4.035e-11 }, { "instance": "_1416_[0]", @@ -45,7 +45,7 @@ "pin": "_1416_[0]/D", "net": "mid", "arrival": 3.296e-10, - "slew": 3.612e-11 + "slew": 4.035e-11 } ], "target_clock": "clk", @@ -72,9 +72,9 @@ ], "data_arrival_time": 3.296e-10, "crpr": 0.000e+00, - "margin": 1.207e-10, - "required_time": 9.879e-09, - "slack": 9.550e-09 + "margin": 1.225e-10, + "required_time": 9.877e-09, + "slack": 9.548e-09 } ] } diff --git a/test/suppress_msg.ok b/test/suppress_msg.ok index 1e892fe8..0fd4d548 100644 --- a/test/suppress_msg.ok +++ b/test/suppress_msg.ok @@ -1,12 +1,12 @@ -Warning: suppress_msg.tcl line 18, cmd warn 1 +Warning 1: suppress_msg.tcl line 18, cmd warn 1 caught Error: suppress_msg.tcl line 18, cmd error 1 -Warning: cmd warn 2 -caught Error: cmd error 2 +Warning 1: cmd warn 2 +caught Error: 2cmd error 2 after error caught caught after error -Warning: suppress_msg.tcl line 51, cmd warn 7 +Warning 1: suppress_msg.tcl line 51, cmd warn 7 caught Error: suppress_msg.tcl line 51, cmd error 7 -Warning: cmd warn 8 -caught Error: cmd error 8 +Warning 1: cmd warn 8 +caught Error: 2cmd error 8 diff --git a/util/Debug.cc b/util/Debug.cc index 16836d7a..ba46f808 100644 --- a/util/Debug.cc +++ b/util/Debug.cc @@ -24,6 +24,7 @@ #include "Debug.hh" +#include "ContainerHelpers.hh" #include "Report.hh" namespace sta { @@ -33,35 +34,18 @@ bool debug_on = false; Debug::Debug(Report *report) : report_(report), debug_on_(false), - debug_map_(nullptr), stats_level_(0) { } -Debug::~Debug() -{ - if (debug_map_) { - DebugMap::Iterator debug_iter(debug_map_); - // Delete the debug map keys. - while (debug_iter.hasNext()) { - const char *what; - int level; - debug_iter.next(what, level); - delete [] what; - } - delete debug_map_; - } -} - bool Debug::check(const char *what, - int level) const + int level) const { - if (debug_on_ - && debug_map_) { + if (debug_on_) { int dbg_level; bool exists; - debug_map_->findKey(what, dbg_level, exists); + findKeyValue(debug_map_, what, dbg_level, exists); if (exists) return dbg_level >= level; } @@ -71,11 +55,10 @@ Debug::check(const char *what, int Debug::level(const char *what) { - if (debug_map_) { - const char *key; + if (debug_on_) { int dbg_level; bool exists; - debug_map_->findKey(what, key, dbg_level, exists); + findKeyValue(debug_map_, what, dbg_level, exists); if (exists) return dbg_level; } @@ -84,29 +67,16 @@ Debug::level(const char *what) void Debug::setLevel(const char *what, - int level) + int level) { if (stringEq(what, "stats")) stats_level_ = level; else if (level == 0) { - if (debug_map_) { - int dbg_level; - bool exists; - const char *key; - debug_map_->findKey(what, key, dbg_level, exists); - if (exists) { - debug_map_->erase(what); - delete [] key; - } - debug_on_ = !debug_map_->empty(); - } + debug_map_.erase(what); + debug_on_ = !debug_map_.empty(); } else { - char *what_cpy = new char[strlen(what) + 1]; - strcpy(what_cpy, what); - if (debug_map_ == nullptr) - debug_map_ = new DebugMap; - (*debug_map_)[what_cpy] = level; + debug_map_[what] = level; debug_on_ = true; } } diff --git a/util/Error.cc b/util/Error.cc index b198c4a4..4f0062fe 100644 --- a/util/Error.cc +++ b/util/Error.cc @@ -37,7 +37,7 @@ Exception::Exception() : } ExceptionMsg::ExceptionMsg(const char *msg, - const bool suppressed) : + const bool suppressed) : Exception(), msg_(msg), suppressed_(suppressed) @@ -51,7 +51,7 @@ ExceptionMsg::what() const noexcept } ExceptionLine::ExceptionLine(const char *filename, - int line) : + int line) : Exception(), filename_(filename), line_(line) diff --git a/util/Fuzzy.cc b/util/Fuzzy.cc index b6c69e6e..f7158366 100644 --- a/util/Fuzzy.cc +++ b/util/Fuzzy.cc @@ -38,7 +38,7 @@ constexpr static float float_equal_tolerance = 1E-15F; bool fuzzyEqual(float v1, - float v2) + float v2) { if (v1 == v2) return true; @@ -59,28 +59,28 @@ fuzzyZero(float v) bool fuzzyLess(float v1, - float v2) + float v2) { return v1 < v2 && !fuzzyEqual(v1, v2); } bool fuzzyLessEqual(float v1, - float v2) + float v2) { return v1 < v2 || fuzzyEqual(v1, v2); } bool fuzzyGreater(float v1, - float v2) + float v2) { return v1 > v2 && !fuzzyEqual(v1, v2); } bool fuzzyGreaterEqual(float v1, - float v2) + float v2) { return v1 > v2 || fuzzyEqual(v1, v2); } diff --git a/util/MachineLinux.cc b/util/MachineLinux.cc index 231634d6..261d143f 100644 --- a/util/MachineLinux.cc +++ b/util/MachineLinux.cc @@ -91,13 +91,13 @@ memoryUsage() while (fgets(line, line_length, status) != nullptr) { char *field = strtok(line, " \t"); if (field && stringEq(field, "VmRSS:")) { - char *size = strtok(nullptr, " \t"); - if (size) { - char *ignore; - // VmRSS is in kilobytes. - memory = strtol(size, &ignore, 10) * 1000; - break; - } + char *size = strtok(nullptr, " \t"); + if (size) { + char *ignore; + // VmRSS is in kilobytes. + memory = strtol(size, &ignore, 10) * 1000; + break; + } } } fclose(status); diff --git a/util/MinMax.cc b/util/MinMax.cc index 074030bd..864b09de 100644 --- a/util/MinMax.cc +++ b/util/MinMax.cc @@ -35,14 +35,14 @@ const float INF = 1E+30F; static bool compareMin(float value1, - float value2) + float value2) { return value1 < value2; } static bool compareMax(float value1, - float value2) + float value2) { return value1 > value2; } @@ -55,10 +55,10 @@ const std::array MinMax::range_{&min_, &max_}; const std::array MinMax::range_index_{min_.index(), max_.index()}; MinMax::MinMax(const char *name, - int index, - float init_value, + int index, + float init_value, int init_value_int, - bool (*compare)(float value1, float value2)) : + bool (*compare)(float value1, float value2)) : name_(name), index_(index), init_value_(init_value), @@ -92,7 +92,7 @@ MinMax::find(const char *min_max) || stringEq(min_max, "early")) return &min_; else if (stringEq(min_max, "max") - || stringEq(min_max, "late")) + || stringEq(min_max, "late")) return &max_; else return nullptr; @@ -111,14 +111,14 @@ MinMax::find(int index) bool MinMax::compare(float value1, - float value2) const + float value2) const { return compare_(value1, value2); } float MinMax::minMax(float value1, - float value2) const + float value2) const { if (compare_(value1, value2)) return value1; @@ -131,12 +131,12 @@ MinMax::minMax(float value1, const MinMaxAll MinMaxAll::min_("min", 0, {MinMax::min()}, {MinMax::min()->index()}); const MinMaxAll MinMaxAll::max_("max", 1, {MinMax::max()}, {MinMax::max()->index()}); const MinMaxAll MinMaxAll::all_("all", 2, {MinMax::min(), MinMax::max()}, - {MinMax::min()->index(), MinMax::max()->index()}); + {MinMax::min()->index(), MinMax::max()->index()}); MinMaxAll::MinMaxAll(const char *name, - int index, - std::vector range, - std::vector range_index) : + int index, + std::vector range, + std::vector range_index) : name_(name), index_(index), range_(range), @@ -172,11 +172,11 @@ MinMaxAll::find(const char *min_max) || stringEq(min_max, "early")) return &min_; else if (stringEq(min_max, "max") - || stringEq(min_max, "late")) + || stringEq(min_max, "late")) return &max_; else if (stringEq(min_max, "all") - || stringEq(min_max, "min_max") - || stringEq(min_max, "minmax")) + || stringEq(min_max, "min_max") + || stringEq(min_max, "minmax")) return &all_; else return nullptr; diff --git a/util/PatternMatch.cc b/util/PatternMatch.cc index 2dd32df9..8b1e49e8 100644 --- a/util/PatternMatch.cc +++ b/util/PatternMatch.cc @@ -31,9 +31,9 @@ namespace sta { using std::string; PatternMatch::PatternMatch(const char *pattern, - bool is_regexp, - bool nocase, - Tcl_Interp *interp) : + bool is_regexp, + bool nocase, + Tcl_Interp *interp) : pattern_(pattern), is_regexp_(is_regexp), nocase_(nocase), @@ -54,7 +54,7 @@ PatternMatch::PatternMatch(const char *pattern) : } PatternMatch::PatternMatch(const char *pattern, - const PatternMatch *inherit_from) : + const PatternMatch *inherit_from) : pattern_(pattern), is_regexp_(inherit_from->is_regexp_), nocase_(inherit_from->nocase_), @@ -66,7 +66,7 @@ PatternMatch::PatternMatch(const char *pattern, } PatternMatch::PatternMatch(const string &pattern, - const PatternMatch *inherit_from) : + const PatternMatch *inherit_from) : pattern_(pattern.c_str()), is_regexp_(inherit_from->is_regexp_), nocase_(inherit_from->nocase_), @@ -88,7 +88,7 @@ PatternMatch::compileRegexp() anchored_pattern += pattern_; anchored_pattern += '$'; Tcl_Obj *pattern_obj = Tcl_NewStringObj(anchored_pattern.c_str(), - anchored_pattern.size()); + anchored_pattern.size()); Tcl_IncrRefCount(pattern_obj); regexp_ = Tcl_GetRegExpFromObj(interp_, pattern_obj, flags); Tcl_DecrRefCount(pattern_obj); @@ -155,7 +155,7 @@ RegexpCompileError::what() const noexcept bool patternMatch(const char *pattern, - const char *str) + const char *str) { const char *p = pattern; const char *s = str; @@ -171,7 +171,7 @@ patternMatch(const char *pattern, return true; while (*s) { if (patternMatch(p + 1, s)) - return true; + return true; s++; } } @@ -180,8 +180,8 @@ patternMatch(const char *pattern, inline bool equalCase(char s, - char p, - bool nocase) + char p, + bool nocase) { return nocase ? tolower(s) == tolower(p) @@ -190,8 +190,8 @@ bool equalCase(char s, bool patternMatchNoCase(const char *pattern, - const char *str, - bool nocase) + const char *str, + bool nocase) { const char *p = pattern; const char *s = str; @@ -207,7 +207,7 @@ patternMatchNoCase(const char *pattern, return true; while (*s) { if (patternMatchNoCase(p + 1, s, nocase)) - return true; + return true; s++; } } diff --git a/util/Report.cc b/util/Report.cc index 413d03c4..f2d0955d 100644 --- a/util/Report.cc +++ b/util/Report.cc @@ -185,7 +185,7 @@ Report::warn(int id, if (!isSuppressed(id)) { va_list args; va_start(args, fmt); - printToBuffer("Warning: "); + printToBuffer("Warning %d: ", id); printToBufferAppend(fmt, args); printBufferLine(); va_end(args); @@ -199,7 +199,7 @@ Report::vwarn(int id, { // Skip suppressed messages. if (!isSuppressed(id)) { - printToBuffer("Warning: "); + printToBuffer("Warning %d: ", id); printToBufferAppend(fmt, args); printBufferLine(); } @@ -216,7 +216,7 @@ Report::fileWarn(int id, if (!isSuppressed(id)) { va_list args; va_start(args, fmt); - printToBuffer("Warning: %s line %d, ", filename, line); + printToBuffer("Warning %d: %s line %d, ", id, filename, line); printToBufferAppend(fmt, args); printBufferLine(); va_end(args); @@ -232,7 +232,7 @@ Report::vfileWarn(int id, { // Skip suppressed messages. if (!isSuppressed(id)) { - printToBuffer("Warning: %s line %d, ", filename, line); + printToBuffer("Warning %d: %s line %d, ", id, filename, line); printToBufferAppend(fmt, args); printBufferLine(); } @@ -247,7 +247,8 @@ Report::error(int id, va_list args; va_start(args, fmt); // No prefix msg, no \n. - printToBuffer(fmt, args); + printToBuffer("%d", id); + printToBufferAppend(fmt, args); va_end(args); throw ExceptionMsg(buffer_, isSuppressed(id)); } @@ -258,7 +259,8 @@ Report::verror(int id, va_list args) { // No prefix msg, no \n. - printToBuffer(fmt, args); + printToBuffer("%d", id); + printToBufferAppend(fmt, args); throw ExceptionMsg(buffer_, isSuppressed(id)); } @@ -272,7 +274,7 @@ Report::fileError(int id, va_list args; va_start(args, fmt); // No prefix msg, no \n. - printToBuffer("%s line %d, ", filename, line); + printToBuffer("%d %s line %d, ", id, filename, line); printToBufferAppend(fmt, args); va_end(args); throw ExceptionMsg(buffer_, isSuppressed(id)); @@ -286,7 +288,7 @@ Report::vfileError(int id, va_list args) { // No prefix msg, no \n. - printToBuffer("%s line %d, ", filename, line); + printToBuffer("%d %s line %d, ", id, filename, line); printToBufferAppend(fmt, args); throw ExceptionMsg(buffer_, isSuppressed(id)); } @@ -294,13 +296,13 @@ Report::vfileError(int id, //////////////////////////////////////////////////////////////// void -Report::critical(int /* id */, +Report::critical(int id, const char *fmt, ...) { va_list args; va_start(args, fmt); - printToBuffer("Critical: "); + printToBuffer("Critical %d: ", id); printToBufferAppend(fmt, args); printBufferLine(); va_end(args); @@ -308,7 +310,7 @@ Report::critical(int /* id */, } void -Report::fileCritical(int /* id */, +Report::fileCritical(int id, const char *filename, int line, const char *fmt, @@ -316,7 +318,7 @@ Report::fileCritical(int /* id */, { va_list args; va_start(args, fmt); - printToBuffer("Critical: %s line %d, ", filename, line); + printToBuffer("Critical %d: %s line %d, ", id, filename, line); printToBufferAppend(fmt, args); printBufferLine(); va_end(args); @@ -340,7 +342,7 @@ Report::unsuppressMsgId(int id) bool Report::isSuppressed(int id) { - return suppressed_msg_ids_.find(id) != suppressed_msg_ids_.end(); + return suppressed_msg_ids_.contains(id); } //////////////////////////////////////////////////////////////// diff --git a/util/RiseFallMinMax.cc b/util/RiseFallMinMax.cc index abc96eb3..4b21a426 100644 --- a/util/RiseFallMinMax.cc +++ b/util/RiseFallMinMax.cc @@ -69,8 +69,8 @@ RiseFallMinMax::setValue(float value) void RiseFallMinMax::setValue(const RiseFallBoth *rf, - const MinMaxAll *min_max, - float value) + const MinMaxAll *min_max, + float value) { for (auto rf_index : rf->rangeIndex()) { for (auto mm_index : min_max->rangeIndex()) { @@ -82,7 +82,7 @@ RiseFallMinMax::setValue(const RiseFallBoth *rf, void RiseFallMinMax::removeValue(const RiseFallBoth *rf, - const MinMax *min_max) + const MinMax *min_max) { int mm_index = min_max->index(); for (auto rf_index : rf->rangeIndex()) @@ -91,7 +91,7 @@ RiseFallMinMax::removeValue(const RiseFallBoth *rf, void RiseFallMinMax::removeValue(const RiseFallBoth *rf, - const MinMaxAll *min_max) + const MinMaxAll *min_max) { for (auto mm : min_max->range()) removeValue(rf, mm); @@ -99,16 +99,16 @@ RiseFallMinMax::removeValue(const RiseFallBoth *rf, void RiseFallMinMax::mergeValue(const RiseFallBoth *rf, - const MinMaxAll *min_max, - float value) + const MinMaxAll *min_max, + float value) { for (auto rf_index : rf->rangeIndex()) { for (auto mm : min_max->range()) { int mm_index = mm->index(); if (!exists_[rf_index][mm_index] - || mm->compare(value, values_[rf_index][mm_index])) { - values_[rf_index][mm_index] = value; - exists_[rf_index][mm_index] = true; + || mm->compare(value, values_[rf_index][mm_index])) { + values_[rf_index][mm_index] = value; + exists_[rf_index][mm_index] = true; } } } @@ -116,8 +116,8 @@ RiseFallMinMax::mergeValue(const RiseFallBoth *rf, void RiseFallMinMax::mergeValue(const RiseFall *rf, - const MinMax *min_max, - float value) + const MinMax *min_max, + float value) { int rf_index = rf->index(); int mm_index = min_max->index(); @@ -130,8 +130,8 @@ RiseFallMinMax::mergeValue(const RiseFall *rf, void RiseFallMinMax::setValue(const RiseFallBoth *rf, - const MinMax *min_max, - float value) + const MinMax *min_max, + float value) { int mm_index = min_max->index(); for (auto rf_index : rf->rangeIndex()) { @@ -142,8 +142,8 @@ RiseFallMinMax::setValue(const RiseFallBoth *rf, void RiseFallMinMax::setValue(const RiseFall *rf, - const MinMax *min_max, - float value) + const MinMax *min_max, + float value) { int rf_index = rf->index(); int mm_index = min_max->index(); @@ -164,8 +164,8 @@ RiseFallMinMax::setValues(RiseFallMinMax *values) void RiseFallMinMax::value(const RiseFall *rf, - const MinMax *min_max, - // Return values. + const MinMax *min_max, + // Return values. float &value, bool &exists) const { @@ -188,7 +188,7 @@ RiseFallMinMax::value(const MinMax *min_max) const float RiseFallMinMax::value(const RiseFall *rf, - const MinMax *min_max) const + const MinMax *min_max) const { return values_[rf->index()][min_max->index()]; } @@ -201,16 +201,16 @@ RiseFallMinMax::hasValue() const void RiseFallMinMax::maxValue(// Return values - float &max_value, - bool &exists) const + float &max_value, + bool &exists) const { max_value = MinMax::max()->initValue(); exists = false; for (int rf_index = 0 ; rf_index < RiseFall::index_count ; rf_index++) { for (int mm_index = 0; mm_index < MinMax::index_count; mm_index++) { if (exists_[rf_index][mm_index]) { - max_value = std::max(max_value, values_[rf_index][mm_index]); - exists = true; + max_value = std::max(max_value, values_[rf_index][mm_index]); + exists = true; } } } @@ -222,7 +222,7 @@ RiseFallMinMax::empty() const for (int rf_index = 0 ; rf_index < RiseFall::index_count ; rf_index++) { for (int mm_index = 0; mm_index < MinMax::index_count; mm_index++) { if (exists_[rf_index][mm_index]) - return false; + return false; } } return true; @@ -243,13 +243,13 @@ RiseFallMinMax::mergeWith(RiseFallMinMax *rfmm) bool exists1 = exists_[rf_index][mm_index]; bool exists2 = rfmm->exists_[rf_index][mm_index]; if (exists1 && exists2) { - float rfmm_value = rfmm->values_[rf_index][mm_index]; - if (min_max->compare(rfmm_value, values_[rf_index][mm_index])) - values_[rf_index][mm_index] = rfmm_value; + float rfmm_value = rfmm->values_[rf_index][mm_index]; + if (min_max->compare(rfmm_value, values_[rf_index][mm_index])) + values_[rf_index][mm_index] = rfmm_value; } else if (!exists1 && exists2) { - values_[rf_index][mm_index] = rfmm->values_[rf_index][mm_index]; - exists_[rf_index][mm_index] = true; + values_[rf_index][mm_index] = rfmm->values_[rf_index][mm_index]; + exists_[rf_index][mm_index] = true; } } } @@ -263,10 +263,10 @@ RiseFallMinMax::equal(const RiseFallMinMax *values) const bool exists1 = exists_[rf_index][mm_index]; bool exists2 = values->exists_[rf_index][mm_index]; if (exists1 != exists2) - return false; + return false; if (exists1 && exists2 - && values_[rf_index][mm_index] != values->values_[rf_index][mm_index]) - return false; + && values_[rf_index][mm_index] != values->values_[rf_index][mm_index]) + return false; } } return true; @@ -286,9 +286,9 @@ RiseFallMinMax::isOneValue(float &value) const value = values_[0][0]; for (int rf_index = 0 ; rf_index < RiseFall::index_count ; rf_index++) { for (int mm_index=0; mm_indexindex(); if (exists_[0][mm_index]) { value = values_[0][mm_index]; for (int rf_index = 0 ; rf_index < RiseFall::index_count ; rf_index++) { if (!exists_[rf_index][mm_index] - || values_[rf_index][mm_index] != value) - return false; + || values_[rf_index][mm_index] != value) + return false; } return true; } diff --git a/util/RiseFallMinMaxDelay.cc b/util/RiseFallMinMaxDelay.cc new file mode 100644 index 00000000..c0746997 --- /dev/null +++ b/util/RiseFallMinMaxDelay.cc @@ -0,0 +1,77 @@ +// OpenSTA, Static Timing Analyzer +// Copyright (c) 2025, Parallax Software, Inc. +// +// This program is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see . +// +// The origin of this software must not be misrepresented; you must not +// claim that you wrote the original software. +// +// Altered source versions must be plainly marked as such, and must not be +// misrepresented as being the original software. +// +// This notice may not be removed or altered from any source distribution. + +#include "RiseFallMinMaxDelay.hh" + +namespace sta { + +RiseFallMinMaxDelay::RiseFallMinMaxDelay() +{ + for (int rf_index = 0; rf_indexindex()][min_max->index()]; + if (exists) + value = values_[rf->index()][min_max->index()]; +} + +void +RiseFallMinMaxDelay::mergeValue(const RiseFall *rf, + const MinMax *min_max, + Delay &value, + const StaState *sta) +{ + int rf_index = rf->index(); + int mm_index = min_max->index(); + if (!exists_[rf_index][mm_index] + || delayGreater(value, values_[rf_index][mm_index], min_max, sta)) { + values_[rf_index][mm_index] = value; + exists_[rf_index][mm_index] = true; + } +} + +} // namespace diff --git a/util/RiseFallValues.cc b/util/RiseFallValues.cc index 6dd4fda4..fb52568f 100644 --- a/util/RiseFallValues.cc +++ b/util/RiseFallValues.cc @@ -54,7 +54,7 @@ RiseFallValues::setValue(float value) void RiseFallValues::setValue(const RiseFallBoth *rf, - float value) + float value) { for (auto rf_index : rf->rangeIndex()) { values_[rf_index] = value; @@ -64,7 +64,7 @@ RiseFallValues::setValue(const RiseFallBoth *rf, void RiseFallValues::setValue(const RiseFall *rf, - float value) + float value) { int rf_index = rf->index(); values_[rf_index] = value; @@ -82,7 +82,7 @@ RiseFallValues::setValues(RiseFallValues *values) void RiseFallValues::value(const RiseFall *rf, - float &value, bool &exists) const + float &value, bool &exists) const { int rf_index = rf->index(); exists = exists_[rf_index]; diff --git a/util/StringSeq.cc b/util/StringSeq.cc index 67d51a4b..f5615d6c 100644 --- a/util/StringSeq.cc +++ b/util/StringSeq.cc @@ -29,11 +29,8 @@ namespace sta { void deleteContents(StringSeq *strings) { - StringSeq::Iterator iter(strings); - while (iter.hasNext()) { - const char *string = iter.next(); + for (const char *string : *strings) stringDelete(string); - } } } // namespace diff --git a/util/StringSet.cc b/util/StringSet.cc index 22d0d303..79863547 100644 --- a/util/StringSet.cc +++ b/util/StringSet.cc @@ -29,11 +29,8 @@ namespace sta { void deleteContents(StringSet *strings) { - StringSet::Iterator iter(strings); - while (iter.hasNext()) { - const char *string = iter.next(); + for (const char *string : *strings) stringDelete(string); - } } } // namespace diff --git a/util/StringUtil.cc b/util/StringUtil.cc index e9b0d74a..16237331 100644 --- a/util/StringUtil.cc +++ b/util/StringUtil.cc @@ -41,14 +41,14 @@ using std::string; static void stringPrintTmp(const char *fmt, - va_list args, - // Return values. - char *&str, - size_t &length); + va_list args, + // Return values. + char *&str, + size_t &length); static void getTmpString(// Return values. - char *&str, - size_t &length); + char *&str, + size_t &length); char * stringCopy(const char *str) @@ -77,8 +77,8 @@ isDigits(const char *str) // print for c++ strings. void stringPrint(string &str, - const char *fmt, - ...) + const char *fmt, + ...) { va_list args; va_start(args, fmt); @@ -105,7 +105,7 @@ stringAppend(string &str, string stdstrPrint(const char *fmt, - ...) + ...) { va_list args; va_start(args, fmt); @@ -118,7 +118,7 @@ stdstrPrint(const char *fmt, char * stringPrint(const char *fmt, - ...) + ...) { va_list args; va_start(args, fmt); @@ -129,7 +129,7 @@ stringPrint(const char *fmt, char * stringPrintArgs(const char *fmt, - va_list args) + va_list args) { char *tmp; size_t tmp_length; @@ -141,7 +141,7 @@ stringPrintArgs(const char *fmt, char * stringPrintTmp(const char *fmt, - ...) + ...) { va_list args; va_start(args, fmt); @@ -154,11 +154,11 @@ stringPrintTmp(const char *fmt, static void stringPrintTmp(const char *fmt, - va_list args, - // Return values. - char *&tmp, - // strlen(tmp), not including terminating '\0'. - size_t &tmp_length) + va_list args, + // Return values. + char *&tmp, + // strlen(tmp), not including terminating '\0'. + size_t &tmp_length) { size_t tmp_length1; getTmpString(tmp, tmp_length1); @@ -188,8 +188,8 @@ thread_local static int tmp_string_next = 0; static void getTmpString(// Return values. - char *&str, - size_t &length) + char *&str, + size_t &length) { if (tmp_string_next == tmp_string_count) tmp_string_next = 0; diff --git a/util/TokenParser.cc b/util/TokenParser.cc index dba068df..e048cecf 100644 --- a/util/TokenParser.cc +++ b/util/TokenParser.cc @@ -58,20 +58,20 @@ TokenParser::hasNext() token_ = token_end_ + 1; // Skip spaces. while (*token_ != '\0' && isspace(*token_)) - token_++; + token_++; // Skip delimiters. while (*token_ != '\0' && strchr(delimiters_,*token_) != nullptr) token_++; if (*token_ == '\0') - token_ = nullptr; + token_ = nullptr; else { - token_end_ = strpbrk(token_, delimiters_); - if (token_end_) { - // Save the delimiter. - token_delimiter_ = *token_end_; - // Replace the separator with a terminator. - *token_end_ = '\0'; - } + token_end_ = strpbrk(token_, delimiters_); + if (token_end_) { + // Save the delimiter. + token_delimiter_ = *token_end_; + // Replace the separator with a terminator. + *token_end_ = '\0'; + } } } else diff --git a/util/Transition.cc b/util/Transition.cc index 5188f9f2..a77a898b 100644 --- a/util/Transition.cc +++ b/util/Transition.cc @@ -24,6 +24,8 @@ #include "Transition.hh" +#include "ContainerHelpers.hh" + namespace sta { using std::max; @@ -157,9 +159,9 @@ RiseFallBoth::matches(const Transition *tr) const { return this == &rise_fall_ || (this == &rise_ - && tr == Transition::rise()) + && tr == Transition::rise()) || (this == &fall_ - && tr == Transition::fall()); + && tr == Transition::fall()); } //////////////////////////////////////////////////////////////// @@ -183,9 +185,9 @@ const Transition Transition::tr_ZX_{"ZX", "ZX", nullptr, 11}; const Transition Transition::rise_fall_{"*", "**", nullptr, -1}; Transition::Transition(const char *name, - const char *init_final, - const RiseFall *as_rise_fall, - int sdf_triple_index) : + const char *init_final, + const RiseFall *as_rise_fall, + int sdf_triple_index) : name_(name), init_final_(init_final), as_rise_fall_(as_rise_fall), @@ -205,7 +207,7 @@ Transition::matches(const Transition *tr) const const Transition * Transition::find(const char *tr_str) { - return transition_map_.findKey(tr_str); + return findKey(transition_map_, tr_str); } const RiseFallBoth * diff --git a/util/Util.i b/util/Util.i index 6c7ec10f..5bc47a53 100644 --- a/util/Util.i +++ b/util/Util.i @@ -226,7 +226,7 @@ log_end() void set_debug(const char *what, - int level) + int level) { Sta::sta()->setDebugLevel(what, level); } @@ -264,7 +264,7 @@ object_type(const char *obj) bool is_object_list(const char *list, - const char *type) + const char *type) { const char *s = list; while (s) { @@ -390,7 +390,7 @@ area_sta_ui(double value) void set_cmd_unit_scale(const char *unit_name, - float scale) + float scale) { Unit *unit = Sta::sta()->units()->find(unit_name); if (unit) @@ -399,7 +399,7 @@ set_cmd_unit_scale(const char *unit_name, void set_cmd_unit_digits(const char *unit_name, - int digits) + int digits) { Unit *unit = Sta::sta()->units()->find(unit_name); if (unit) @@ -408,7 +408,7 @@ set_cmd_unit_digits(const char *unit_name, void set_cmd_unit_suffix(const char *unit_name, - const char *suffix) + const char *suffix) { Unit *unit = Sta::sta()->units()->find(unit_name); if (unit) { @@ -473,7 +473,7 @@ unit_scale(const char *unit_name) // Pass value arg as string to support NaNs. const char * format_time(const char *value, - int digits) + int digits) { float value1 = strtof(value, nullptr); return Sta::sta()->units()->timeUnit()->asString(value1, digits); @@ -481,7 +481,7 @@ format_time(const char *value, const char * format_capacitance(const char *value, - int digits) + int digits) { float value1 = strtof(value, nullptr); return Sta::sta()->units()->capacitanceUnit()->asString(value1, digits); @@ -489,7 +489,7 @@ format_capacitance(const char *value, const char * format_resistance(const char *value, - int digits) + int digits) { float value1 = strtof(value, nullptr); return Sta::sta()->units()->resistanceUnit()->asString(value1, digits); @@ -497,7 +497,7 @@ format_resistance(const char *value, const char * format_voltage(const char *value, - int digits) + int digits) { float value1 = strtof(value, nullptr); return Sta::sta()->units()->voltageUnit()->asString(value1, digits); @@ -505,7 +505,7 @@ format_voltage(const char *value, const char * format_current(const char *value, - int digits) + int digits) { float value1 = strtof(value, nullptr); return Sta::sta()->units()->currentUnit()->asString(value1, digits); @@ -513,7 +513,7 @@ format_current(const char *value, const char * format_power(const char *value, - int digits) + int digits) { float value1 = strtof(value, nullptr); return Sta::sta()->units()->powerUnit()->asString(value1, digits); @@ -521,7 +521,7 @@ format_power(const char *value, const char * format_distance(const char *value, - int digits) + int digits) { float value1 = strtof(value, nullptr); Unit *dist_unit = Sta::sta()->units()->distanceUnit(); @@ -530,7 +530,7 @@ format_distance(const char *value, const char * format_area(const char *value, - int digits) + int digits) { float value1 = strtof(value, nullptr); Unit *dist_unit = Sta::sta()->units()->distanceUnit(); @@ -555,7 +555,7 @@ fall_short_name() bool fuzzy_equal(float value1, - float value2) + float value2) { return fuzzyEqual(value1, value2); } diff --git a/verilog/Verilog.i b/verilog/Verilog.i index 5e1744ef..c1485fea 100644 --- a/verilog/Verilog.i +++ b/verilog/Verilog.i @@ -39,8 +39,8 @@ read_verilog_cmd(const char *filename) void write_verilog_cmd(const char *filename, - bool include_pwr_gnd, - CellSeq *remove_cells) + bool include_pwr_gnd, + CellSeq *remove_cells) { // This does NOT want the SDC (cmd) network because it wants // to see the sta internal names. diff --git a/verilog/Verilog.tcl b/verilog/Verilog.tcl index f4a459f5..73e753de 100644 --- a/verilog/Verilog.tcl +++ b/verilog/Verilog.tcl @@ -32,7 +32,7 @@ proc_redirect read_verilog { } define_cmd_args "write_verilog" {[-include_pwr_gnd]\ - [-remove_cells cells] filename} + [-remove_cells cells] filename} proc write_verilog { args } { # -sort deprecated 12/12/2025 diff --git a/verilog/VerilogParse.yy b/verilog/VerilogParse.yy index 530e9cf2..8572f71d 100644 --- a/verilog/VerilogParse.yy +++ b/verilog/VerilogParse.yy @@ -223,9 +223,8 @@ stmts: { if ($2) $1->push_back($2); } | stmts stmt_seq // Append stmt_seq to stmts. - { sta::VerilogStmtSeq::Iterator iter($2); - while (iter.hasNext()) - $1->push_back(iter.next()); + { for (sta::VerilogStmt *stmt : *$2) + $1->push_back(stmt); delete $2; } ; diff --git a/verilog/VerilogReader.cc b/verilog/VerilogReader.cc index 26ed54d8..e7ac21d3 100644 --- a/verilog/VerilogReader.cc +++ b/verilog/VerilogReader.cc @@ -26,6 +26,7 @@ #include +#include "ContainerHelpers.hh" #include "Zlib.hh" #include "Debug.hh" #include "Report.hh" @@ -43,14 +44,14 @@ namespace sta { using std::string; -typedef unsigned long long VerilogConstant10; +using VerilogConstant10 = unsigned long long; static string verilogBusBitName(const string &bus_name, int index); static int hierarchyLevel(Net *net, - Network *network); + Network *network); VerilogReader * makeVerilogReader(NetworkReader *network) @@ -60,7 +61,7 @@ makeVerilogReader(NetworkReader *network) bool readVerilogFile(const char *filename, - VerilogReader *verilog_reader) + VerilogReader *verilog_reader) { return verilog_reader->read(filename); } @@ -78,9 +79,9 @@ class VerilogError public: VerilogError(int id, const char *filename, - int line, - const char *msg, - bool warn); + int line, + const char *msg, + bool warn); ~VerilogError(); const char *msg() const { return msg_; } const char *filename() const { return filename_; } @@ -100,9 +101,9 @@ private: VerilogError::VerilogError(int id, const char *filename, - int line, - const char *msg, - bool warn) : + int line, + const char *msg, + bool warn) : id_(id), filename_(filename), line_(line), @@ -121,14 +122,14 @@ class VerilogErrorCmp { public: bool operator()(const VerilogError *error1, - const VerilogError *error2) const + const VerilogError *error2) const { int file_cmp = strcmp(error1->filename_, error2->filename_); if (file_cmp == 0) { if (error1->line_ == error2->line_) - return strcmp(error1->msg_, error2->msg_) < 0; + return strcmp(error1->msg_, error2->msg_) < 0; else - return error1->line_ < error2->line_; + return error1->line_ < error2->line_; } else return file_cmp < 0; @@ -222,15 +223,15 @@ VerilogReader::init(const char *filename) VerilogModule * VerilogReader::module(Cell *cell) { - return module_map_.findKey(cell); + return findKey(module_map_, cell); } void VerilogReader::makeModule(const string *module_vname, - VerilogNetSeq *ports, - VerilogStmtSeq *stmts, + VerilogNetSeq *ports, + VerilogStmtSeq *stmts, VerilogAttrStmtSeq *attr_stmts, - int line) + int line) { const string module_name = moduleVerilogToSta(module_vname); Cell *cell = network_->findCell(library_, module_name.c_str()); @@ -242,7 +243,7 @@ VerilogReader::makeModule(const string *module_vname, } VerilogModule *module = new VerilogModule(module_name.c_str(), ports, stmts, - attr_stmts, filename_, line, this); + attr_stmts, filename_, line, this); cell = network_->makeCell(library_, module_name.c_str(), false, filename_.c_str()); for (VerilogAttrStmt *stmt : *attr_stmts) { @@ -258,10 +259,10 @@ VerilogReader::makeModule(const string *module_vname, void VerilogReader::makeModule(const string *module_name, - VerilogStmtSeq *port_dcls, - VerilogStmtSeq *stmts, + VerilogStmtSeq *port_dcls, + VerilogStmtSeq *stmts, VerilogAttrStmtSeq *attr_stmts, - int line) + int line) { VerilogNetSeq *ports = new VerilogNetSeq; // Pull the port names out of the port declarations. @@ -269,8 +270,8 @@ VerilogReader::makeModule(const string *module_name, if (dcl->isDeclaration()) { VerilogDcl *dcl1 = dynamic_cast(dcl); for (VerilogDclArg *arg : *dcl1->args()) { - VerilogNetNamed *port = new VerilogNetScalar(arg->netName()); - ports->push_back(port); + VerilogNetNamed *port = new VerilogNetScalar(arg->netName()); + ports->push_back(port); } // Add the port declarations to the statements. stmts->push_back(dcl); @@ -282,34 +283,34 @@ VerilogReader::makeModule(const string *module_name, void VerilogReader::makeCellPorts(Cell *cell, - VerilogModule *module, - VerilogNetSeq *ports) + VerilogModule *module, + VerilogNetSeq *ports) { StdStringSet port_names; for (VerilogNet *mod_port : *ports) { const string &port_name = mod_port->name(); - if (port_names.find(port_name) == port_names.end()) { + if (!port_names.contains(port_name)) { port_names.insert(port_name); if (mod_port->isNamed()) { - if (mod_port->isNamedPortRef()) - makeNamedPortRefCellPorts(cell, module, mod_port, port_names); - else - makeCellPort(cell, module, mod_port->name()); + if (mod_port->isNamedPortRef()) + makeNamedPortRefCellPorts(cell, module, mod_port, port_names); + else + makeCellPort(cell, module, mod_port->name()); } } else warn(165, module->filename(), module->line(), - "module %s repeated port name %s.", - module->name().c_str(), - port_name.c_str()); + "module %s repeated port name %s.", + module->name().c_str(), + port_name.c_str()); } checkModuleDcls(module, port_names); } Port * VerilogReader::makeCellPort(Cell *cell, - VerilogModule *module, - const string &port_name) + VerilogModule *module, + const string &port_name) { VerilogDcl *dcl = module->declaration(port_name.c_str()); if (dcl) { @@ -317,25 +318,25 @@ VerilogReader::makeCellPort(Cell *cell, VerilogDclBus *dcl_bus = dynamic_cast(dcl); Port *port = dcl->isBus() ? network_->makeBusPort(cell, port_name.c_str(), dcl_bus->fromIndex(), - dcl_bus->toIndex()) + dcl_bus->toIndex()) : network_->makePort(cell, port_name.c_str()); network_->setDirection(port, dir); return port; } else { warn(166, module->filename(), module->line(), - "module %s missing declaration for port %s.", - module->name().c_str(), - port_name.c_str()); + "module %s missing declaration for port %s.", + module->name().c_str(), + port_name.c_str()); return network_->makePort(cell, port_name.c_str()); } } void VerilogReader::makeNamedPortRefCellPorts(Cell *cell, - VerilogModule *module, - VerilogNet *mod_port, - StdStringSet &port_names) + VerilogModule *module, + VerilogNet *mod_port, + StdStringSet &port_names) { PortSeq *member_ports = new PortSeq; VerilogNetNameIterator *net_name_iter = mod_port->nameIterator(module,this); @@ -353,40 +354,40 @@ VerilogReader::makeNamedPortRefCellPorts(Cell *cell, // Make sure each declaration appears in the module port list. void VerilogReader::checkModuleDcls(VerilogModule *module, - std::set &port_names) + std::set &port_names) { for (auto const & [port_name, dcl] : *module->declarationMap()) { PortDirection *dir = dcl->direction(); if (dir->isInput() - || dir->isOutput() - || dir->isBidirect()) { - if (port_names.find(port_name) == port_names.end()) - linkWarn(197, module->filename(), module->line(), - "module %s declared signal %s is not in the port list.", - module->name().c_str(), - port_name.c_str()); + || dir->isOutput() + || dir->isBidirect()) { + if (!port_names.contains(port_name)) + linkWarn(197, module->filename(), module->line(), + "module %s declared signal %s is not in the port list.", + module->name().c_str(), + port_name.c_str()); } } } VerilogDcl * VerilogReader::makeDcl(PortDirection *dir, - VerilogDclArgSeq *args, + VerilogDclArgSeq *args, VerilogAttrStmtSeq *attr_stmts, - int line) + int line) { if (dir->isInternal()) { // Prune wire declarations without assigns because they just eat memory. VerilogDclArgSeq *assign_args = nullptr; for (VerilogDclArg *arg : *args) { if (arg->assign()) { - if (assign_args == nullptr) - assign_args = new VerilogDclArgSeq; - assign_args->push_back(arg); + if (assign_args == nullptr) + assign_args = new VerilogDclArgSeq; + assign_args->push_back(arg); } else { - delete arg; - dcl_arg_count_--; + delete arg; + dcl_arg_count_--; } } delete args; @@ -395,7 +396,7 @@ VerilogReader::makeDcl(PortDirection *dir, return new VerilogDcl(dir, assign_args, attr_stmts, line); } else { - attr_stmts->deleteContents(); + deleteContents(attr_stmts); delete attr_stmts; return nullptr; } @@ -408,9 +409,9 @@ VerilogReader::makeDcl(PortDirection *dir, VerilogDcl * VerilogReader::makeDcl(PortDirection *dir, - VerilogDclArg *arg, + VerilogDclArg *arg, VerilogAttrStmtSeq *attr_stmts, - int line) + int line) { dcl_count_++; return new VerilogDcl(dir, arg, attr_stmts, line); @@ -418,11 +419,11 @@ VerilogReader::makeDcl(PortDirection *dir, VerilogDclBus * VerilogReader::makeDclBus(PortDirection *dir, - int from_index, - int to_index, - VerilogDclArg *arg, + int from_index, + int to_index, + VerilogDclArg *arg, VerilogAttrStmtSeq *attr_stmts, - int line) + int line) { dcl_bus_count_++; return new VerilogDclBus(dir, from_index, to_index, arg, attr_stmts, @@ -431,11 +432,11 @@ VerilogReader::makeDclBus(PortDirection *dir, VerilogDclBus * VerilogReader::makeDclBus(PortDirection *dir, - int from_index, - int to_index, - VerilogDclArgSeq *args, + int from_index, + int to_index, + VerilogDclArgSeq *args, VerilogAttrStmtSeq *attr_stmts, - int line) + int line) { dcl_bus_count_++; return new VerilogDclBus(dir, from_index, to_index, args, attr_stmts, @@ -461,8 +462,8 @@ VerilogReader::makeDclArg(VerilogAssign *assign) VerilogNetPartSelect * VerilogReader::makeNetPartSelect(const string *net_vname, - int from_index, - int to_index) + int from_index, + int to_index) { net_part_select_count_++; if (report_stmt_stats_) @@ -497,7 +498,7 @@ VerilogReader::makeNetScalar(const string *net_vname) VerilogNetBitSelect * VerilogReader::makeNetBitSelect(const string *net_vname, - int index) + int index) { net_bit_select_count_++; if (report_stmt_stats_) @@ -510,8 +511,8 @@ VerilogReader::makeNetBitSelect(const string *net_vname, VerilogAssign * VerilogReader::makeAssign(VerilogNet *lhs, - VerilogNet *rhs, - int line) + VerilogNet *rhs, + int line) { assign_count_++; return new VerilogAssign(lhs, rhs, line); @@ -538,14 +539,14 @@ VerilogReader::makeModuleInst(const string *module_vname, StdStringSeq net_names(port_count); for (VerilogNet *vnet : *pins) { VerilogNetPortRefScalarNet *vpin = - dynamic_cast(vnet); + dynamic_cast(vnet); const char *port_name = vpin->name().c_str(); const string &net_name = vpin->netName(); Port *port = network_->findPort(cell, port_name); LibertyPort *lport = network_->libertyPort(port); if (lport->isBus()) { - LibertyPortMemberIterator member_iter(lport); - lport = member_iter.next(); + LibertyPortMemberIterator member_iter(lport); + lport = member_iter.next(); } int pin_index = lport->pinIndex(); net_names[pin_index] = net_name; @@ -553,7 +554,7 @@ VerilogReader::makeModuleInst(const string *module_vname, net_port_ref_scalar_net_count_--; } VerilogInst *inst = new VerilogLibertyInst(liberty_cell, inst_name, - net_names, attr_stmts, line); + net_names, attr_stmts, line); delete pins; if (report_stmt_stats_) { inst_names_ += inst_name.size() + 1; @@ -583,7 +584,7 @@ VerilogReader::makeModuleInst(const string *module_vname, bool VerilogReader::hasScalarNamedPortRefs(LibertyCell *liberty_cell, - VerilogNetSeq *pins) + VerilogNetSeq *pins) { if (pins && pins->size() > 0 @@ -592,12 +593,12 @@ VerilogReader::hasScalarNamedPortRefs(LibertyCell *liberty_cell, const char *port_name = vpin->name().c_str(); LibertyPort *port = liberty_cell->findLibertyPort(port_name); if (port) { - if (!(port->size() == 1 - && (vpin->isNamedPortRefScalarNet()))) - return false; + if (!(port->size() == 1 + && (vpin->isNamedPortRefScalarNet()))) + return false; } else - return false; + return false; } return true; } @@ -619,7 +620,7 @@ VerilogReader::makeNetNamedPortRefScalarNet(const string *port_vname) VerilogNetPortRef * VerilogReader::makeNetNamedPortRefScalarNet(const string *port_vname, - const string *net_vname) + const string *net_vname) { net_port_ref_scalar_net_count_++; if (report_stmt_stats_) { @@ -638,8 +639,8 @@ VerilogReader::makeNetNamedPortRefScalarNet(const string *port_vname, VerilogNetPortRef * VerilogReader::makeNetNamedPortRefBitSelect(const string *port_vname, - const string *bus_vname, - int index) + const string *bus_vname, + int index) { net_port_ref_scalar_net_count_++; const string bus_name = portVerilogToSta(bus_vname); @@ -658,7 +659,7 @@ VerilogReader::makeNetNamedPortRefBitSelect(const string *port_vname, VerilogNetPortRef * VerilogReader::makeNetNamedPortRefScalar(const string *port_vname, - VerilogNet *net) + VerilogNet *net) { net_port_ref_scalar_count_++; if (report_stmt_stats_) @@ -671,8 +672,8 @@ VerilogReader::makeNetNamedPortRefScalar(const string *port_vname, VerilogNetPortRef * VerilogReader::makeNetNamedPortRefBit(const string *port_vname, - int index, - VerilogNet *net) + int index, + VerilogNet *net) { net_port_ref_bit_count_++; const string port_name = portVerilogToSta(port_vname); @@ -684,9 +685,9 @@ VerilogReader::makeNetNamedPortRefBit(const string *port_vname, VerilogNetPortRef * VerilogReader::makeNetNamedPortRefPart(const string *port_vname, - int from_index, - int to_index, - VerilogNet *net) + int from_index, + int to_index, + VerilogNet *net) { net_port_ref_part_count_++; const string port_name = portVerilogToSta(port_vname); @@ -711,7 +712,7 @@ VerilogReader::makeNetConcat(VerilogNetSeq *nets) sizeof(class_name), \ (count * sizeof(class_name) * 1e-6)) -#define printStringMemory(name, count) \ +#define printStringMemory(name, count) \ report_->reportLine(" %-20s %6.1fMb", name, count * 1e-6) void @@ -727,17 +728,17 @@ VerilogReader::reportStmtCounts() printClassMemory("bus declarations", VerilogDclBus, dcl_bus_count_); printClassMemory("declaration args", VerilogDclArg, dcl_arg_count_); printClassMemory("port ref scalar", VerilogNetPortRefScalar, - net_port_ref_scalar_count_); + net_port_ref_scalar_count_); printClassMemory("port ref scalar net", VerilogNetPortRefScalarNet, - net_port_ref_scalar_net_count_); + net_port_ref_scalar_net_count_); printClassMemory("port ref bit", VerilogNetPortRefBit, - net_port_ref_bit_count_); + net_port_ref_bit_count_); printClassMemory("port ref part", VerilogNetPortRefPart, - net_port_ref_part_count_); + net_port_ref_part_count_); printClassMemory("scalar nets", VerilogNetScalar, net_scalar_count_); printClassMemory("bus bit nets",VerilogNetBitSelect,net_bit_select_count_); printClassMemory("bus range nets", VerilogNetPartSelect, - net_part_select_count_); + net_part_select_count_); printClassMemory("constant nets", VerilogNetConstant, net_constant_count_); printClassMemory("concats", VerilogNetConcat, concat_count_); printClassMemory("assigns", VerilogAssign, assign_count_); @@ -752,8 +753,8 @@ VerilogReader::reportStmtCounts() void VerilogReader::error(int id, const char *filename, - int line, - const char *fmt, ...) + int line, + const char *fmt, ...) { va_list args; va_start(args, fmt); @@ -764,8 +765,8 @@ VerilogReader::error(int id, void VerilogReader::warn(int id, const char *filename, - int line, - const char *fmt, ...) + int line, + const char *fmt, ...) { va_list args; va_start(args, fmt); @@ -794,11 +795,11 @@ VerilogModule::VerilogModule(const string &name, VerilogModule::~VerilogModule() { - ports_->deleteContents(); + deleteContents(ports_); delete ports_; - stmts_->deleteContents(); + deleteContents(stmts_); delete stmts_; - attr_stmts_->deleteContents(); + deleteContents(attr_stmts_); delete attr_stmts_; } @@ -811,13 +812,13 @@ VerilogModule::parseStmts(VerilogReader *reader) parseDcl(dynamic_cast(stmt), reader); else if (stmt->isInstance()) checkInstanceName(dynamic_cast(stmt), inst_names, - reader); + reader); } } void VerilogModule::parseDcl(VerilogDcl *dcl, - VerilogReader *reader) + VerilogReader *reader) { for (VerilogDclArg *arg : *dcl->args()) { if (arg->isNamed()) { @@ -861,21 +862,21 @@ VerilogModule::parseDcl(VerilogDcl *dcl, // expansion so errors are only reported once. void VerilogModule::checkInstanceName(VerilogInst *inst, - StdStringSet &inst_names, - VerilogReader *reader) + StdStringSet &inst_names, + VerilogReader *reader) { string inst_name = inst->instanceName(); - if (inst_names.find(inst_name) != inst_names.end()) { + if (inst_names.contains(inst_name)) { int i = 1; string replacement_name; do { replacement_name = stdstrPrint("%s_%d", inst_name.c_str(), i++); - } while (inst_names.find(replacement_name) != inst_names.end()); + } while (inst_names.contains(replacement_name)); string inst_vname = instanceVerilogName(inst_name.c_str()); reader->warn(1396, filename_.c_str(), inst->line(), - "instance name %s duplicated - renamed to %s.", - inst_vname.c_str(), - replacement_name.c_str()); + "instance name %s duplicated - renamed to %s.", + inst_vname.c_str(), + replacement_name.c_str()); inst_name = replacement_name; inst->setInstanceName(inst_name); } @@ -885,7 +886,7 @@ VerilogModule::checkInstanceName(VerilogInst *inst, VerilogDcl * VerilogModule::declaration(const string &net_name) { - return dcl_map_.findKey(net_name.c_str()); + return findKey(dcl_map_, net_name.c_str()); } //////////////////////////////////////////////////////////////// @@ -906,7 +907,7 @@ VerilogInst::VerilogInst(const string &inst_name, VerilogInst::~VerilogInst() { - attr_stmts_->deleteContents(); + deleteContents(attr_stmts_); delete attr_stmts_; } @@ -930,7 +931,7 @@ VerilogModuleInst::VerilogModuleInst(const string &module_name, VerilogModuleInst::~VerilogModuleInst() { if (pins_) { - pins_->deleteContents(); + deleteContents(pins_); delete pins_; } } @@ -987,9 +988,9 @@ VerilogDcl::VerilogDcl(PortDirection *dir, VerilogDcl::~VerilogDcl() { - args_->deleteContents(); + deleteContents(args_); delete args_; - attr_stmts_->deleteContents(); + deleteContents(attr_stmts_); delete attr_stmts_; } @@ -1061,8 +1062,8 @@ VerilogDclArg::netName() } VerilogAssign::VerilogAssign(VerilogNet *lhs, - VerilogNet *rhs, - int line) : + VerilogNet *rhs, + int line) : VerilogStmt(line), lhs_(lhs), rhs_(rhs) @@ -1126,8 +1127,8 @@ class VerilogBusNetNameIterator : public VerilogNetNameIterator { public: VerilogBusNetNameIterator(const string bus_name, - int from_index, - int to_index); + int from_index, + int to_index); virtual bool hasNext(); virtual const string &next(); @@ -1140,8 +1141,8 @@ protected: }; VerilogBusNetNameIterator::VerilogBusNetNameIterator(const string bus_name, - int from_index, - int to_index) : + int from_index, + int to_index) : bus_name_(bus_name), from_index_(from_index), to_index_(to_index), @@ -1153,9 +1154,9 @@ bool VerilogBusNetNameIterator::hasNext() { return (to_index_ > from_index_ - && index_ <= to_index_) + && index_ <= to_index_) || (to_index_ <= from_index_ - && index_ >= to_index_); + && index_ >= to_index_); } const string & @@ -1180,7 +1181,7 @@ class VerilogConstantNetNameIterator : public VerilogNetNameIterator { public: VerilogConstantNetNameIterator(VerilogConstantValue *value, - const string &zero, + const string &zero, const string &one); virtual bool hasNext(); virtual const string &next(); @@ -1194,8 +1195,8 @@ private: VerilogConstantNetNameIterator:: VerilogConstantNetNameIterator(VerilogConstantValue *value, - const string &zero, - const string &one) : + const string &zero, + const string &one) : value_(value), zero_(zero), one_(one), @@ -1219,8 +1220,8 @@ class VerilogNetConcatNameIterator : public VerilogNetNameIterator { public: VerilogNetConcatNameIterator(VerilogNetSeq *nets, - VerilogModule *module, - VerilogReader *reader); + VerilogModule *module, + VerilogReader *reader); virtual ~VerilogNetConcatNameIterator(); virtual bool hasNext(); virtual const string &next(); @@ -1228,21 +1229,25 @@ public: private: VerilogModule *module_; VerilogReader *reader_; - VerilogNetSeq::Iterator net_iter_; + VerilogNetSeq *nets_; + VerilogNetSeq::iterator net_iter_; VerilogNetNameIterator *net_name_iter_; }; VerilogNetConcatNameIterator:: VerilogNetConcatNameIterator(VerilogNetSeq *nets, - VerilogModule *module, - VerilogReader *reader) : + VerilogModule *module, + VerilogReader *reader) : module_(module), reader_(reader), - net_iter_(nets), + nets_(nets), + net_iter_(nets->begin()), net_name_iter_(nullptr) { - if (net_iter_.hasNext()) - net_name_iter_ = net_iter_.next()->nameIterator(module, reader); + if (net_iter_ != nets_->end()) { + VerilogNet *net = *net_iter_++; + net_name_iter_ = net->nameIterator(module, reader); + } } VerilogNetConcatNameIterator::~VerilogNetConcatNameIterator() @@ -1254,7 +1259,7 @@ bool VerilogNetConcatNameIterator::hasNext() { return (net_name_iter_ && net_name_iter_->hasNext()) - || net_iter_.hasNext(); + || net_iter_ != nets_->end(); } const string & @@ -1263,12 +1268,12 @@ VerilogNetConcatNameIterator::next() if (net_name_iter_ && net_name_iter_->hasNext()) return net_name_iter_->next(); else { - if (net_iter_.hasNext()) { - VerilogNet *net = net_iter_.next(); + if (net_iter_ != nets_->end()) { + VerilogNet *net = *net_iter_++; delete net_name_iter_; net_name_iter_ = net->nameIterator(module_, reader_); if (net_name_iter_ && net_name_iter_->hasNext()) - return net_name_iter_->next(); + return net_name_iter_->next(); } } static const string null; @@ -1296,7 +1301,7 @@ VerilogNetScalar::VerilogNetScalar(const string &name) : static int verilogNetScalarSize(const char *name, - VerilogModule *module) + VerilogModule *module) { VerilogDcl *dcl = module->declaration(name); if (dcl) @@ -1314,14 +1319,14 @@ VerilogNetScalar::size(VerilogModule *module) static VerilogNetNameIterator * verilogNetScalarNameIterator(const string &name, - VerilogModule *module) + VerilogModule *module) { if (!name.empty()) { VerilogDcl *dcl = module->declaration(name); if (dcl && dcl->isBus()) { VerilogDclBus *dcl_bus = dynamic_cast(dcl); return new VerilogBusNetNameIterator(name, dcl_bus->fromIndex(), - dcl_bus->toIndex()); + dcl_bus->toIndex()); } } return new VerilogOneNetNameIterator(name); @@ -1329,13 +1334,13 @@ verilogNetScalarNameIterator(const string &name, VerilogNetNameIterator * VerilogNetScalar::nameIterator(VerilogModule *module, - VerilogReader *) + VerilogReader *) { return verilogNetScalarNameIterator(name_.c_str(), module); } VerilogNetBitSelect::VerilogNetBitSelect(const string &name, - int index) : + int index) : VerilogNetNamed(verilogBusBitName(name, index)), index_(index) { @@ -1349,14 +1354,14 @@ VerilogNetBitSelect::size(VerilogModule *) VerilogNetNameIterator * VerilogNetBitSelect::nameIterator(VerilogModule *, - VerilogReader *) + VerilogReader *) { return new VerilogOneNetNameIterator(name_); } VerilogNetPartSelect::VerilogNetPartSelect(const string &name, - int from_index, - int to_index): + int from_index, + int to_index): VerilogNetNamed(name), from_index_(from_index), to_index_(to_index) @@ -1374,13 +1379,13 @@ VerilogNetPartSelect::size(VerilogModule *) VerilogNetNameIterator * VerilogNetPartSelect::nameIterator(VerilogModule *, - VerilogReader *) + VerilogReader *) { return new VerilogBusNetNameIterator(name_.c_str(), from_index_, to_index_); } VerilogNetConstant::VerilogNetConstant(const string *constant, - VerilogReader *reader, + VerilogReader *reader, int line) { parseConstant(constant, reader, line); @@ -1388,7 +1393,7 @@ VerilogNetConstant::VerilogNetConstant(const string *constant, void VerilogNetConstant::parseConstant(const string *constant, - VerilogReader *reader, + VerilogReader *reader, int line) { // Find constant size. @@ -1430,9 +1435,9 @@ VerilogNetConstant::parseConstant(const string *constant, void VerilogNetConstant::parseConstant(const string *constant, - size_t base_idx, - int base, - int digit_bit_count) + size_t base_idx, + int base, + int digit_bit_count) { // Scan the constant from LSD to MSD. size_t size = value_->size(); @@ -1449,9 +1454,9 @@ VerilogNetConstant::parseConstant(const string *constant, unsigned value_digit = strtoul(value_digit_str, &end, base); unsigned mask = 1; for (int b = 0; b < digit_bit_count && bit < size; b++) { - bool value_bit = (value_digit & mask) != 0; - (*value_)[bit++] = value_bit; - mask = mask << 1; + bool value_bit = (value_digit & mask) != 0; + (*value_)[bit++] = value_bit; + mask = mask << 1; } } } @@ -1460,7 +1465,7 @@ VerilogNetConstant::parseConstant(const string *constant, void VerilogNetConstant::parseConstant10(const string *constant, size_t base_idx, - VerilogReader *reader, + VerilogReader *reader, int line) { // Copy the constant skipping underscores. @@ -1479,8 +1484,8 @@ VerilogNetConstant::parseConstant10(const string *constant, || (length == max_length && tmp > constant10_max)) reader->warn(1397, reader->filename(), line, - "base 10 constant greater than %s not supported.", - constant10_max.c_str()); + "base 10 constant greater than %s not supported.", + constant10_max.c_str()); else { size_t *end = nullptr; VerilogConstant10 value = std::stoull(tmp, end, 10); @@ -1499,11 +1504,11 @@ VerilogNetConstant::~VerilogNetConstant() VerilogNetNameIterator * VerilogNetConstant::nameIterator(VerilogModule *, - VerilogReader *reader) + VerilogReader *reader) { return new VerilogConstantNetNameIterator(value_, - reader->zeroNetName(), - reader->oneNetName()); + reader->zeroNetName(), + reader->oneNetName()); } @@ -1521,25 +1526,22 @@ VerilogNetConcat::VerilogNetConcat(VerilogNetSeq *nets) : VerilogNetConcat::~VerilogNetConcat() { - nets_->deleteContents(); + deleteContents(nets_); delete nets_; } int VerilogNetConcat::size(VerilogModule *module) { - VerilogNetSeq::Iterator net_iter(nets_); int sz = 0; - while (net_iter.hasNext()) { - VerilogNet *net = net_iter.next(); + for (VerilogNet *net : *nets_) sz += net->size(module); - } return sz; } VerilogNetNameIterator * VerilogNetConcat::nameIterator(VerilogModule *module, - VerilogReader *reader) + VerilogReader *reader) { return new VerilogNetConcatNameIterator(nets_, module, reader); } @@ -1577,13 +1579,13 @@ VerilogNetPortRefScalarNet::size(VerilogModule *module) VerilogNetNameIterator * VerilogNetPortRefScalarNet::nameIterator(VerilogModule *module, - VerilogReader *) + VerilogReader *) { return verilogNetScalarNameIterator(net_name_, module); } VerilogNetPortRefScalar::VerilogNetPortRefScalar(const string &name, - VerilogNet *net) : + VerilogNet *net) : VerilogNetPortRef(name), net_(net) { @@ -1605,7 +1607,7 @@ VerilogNetPortRefScalar::size(VerilogModule *module) VerilogNetNameIterator * VerilogNetPortRefScalar::nameIterator(VerilogModule *module, - VerilogReader *reader) + VerilogReader *reader) { if (net_) return net_->nameIterator(module, reader); @@ -1614,17 +1616,17 @@ VerilogNetPortRefScalar::nameIterator(VerilogModule *module, } VerilogNetPortRefBit::VerilogNetPortRefBit(const string &name, - int index, - VerilogNet *net) : + int index, + VerilogNet *net) : VerilogNetPortRefScalar(name, net), bit_name_(verilogBusBitName(name, index)) { } VerilogNetPortRefPart::VerilogNetPortRefPart(const string &name, - int from_index, - int to_index, - VerilogNet *net) : + int from_index, + int to_index, + VerilogNet *net) : VerilogNetPortRefBit(name, from_index, net), to_index_(to_index) { @@ -1662,7 +1664,7 @@ VerilogAttrStmt::VerilogAttrStmt(VerilogAttrEntrySeq *attrs): VerilogAttrStmt::~VerilogAttrStmt() { - attrs_->deleteContents(); + deleteContents(attrs_); delete attrs_; } @@ -1680,20 +1682,20 @@ VerilogAttrStmt::attrs() //////////////////////////////////////////////////////////////// // Verilog net name to network net map. -typedef Map BindingMap; +using BindingMap = std::map; class VerilogBindingTbl { public: VerilogBindingTbl(const string &zero_net_name_, - const string &one_net_name_); + const string &one_net_name_); Net *ensureNetBinding(const char *net_name, - Instance *inst, - NetworkReader *network); + Instance *inst, + NetworkReader *network); Net *find(const char *name, - NetworkReader *network); + NetworkReader *network); void bind(const char *name, - Net *net); + Net *net); private: const string &zero_net_name_; @@ -1713,33 +1715,31 @@ VerilogReader::linkNetwork(const char *top_cell_name, // Seed the recursion for expansion with the top level instance. Instance *top_instance = network_->makeInstance(top_cell, top_cell_name, nullptr); VerilogBindingTbl bindings(zero_net_name_, one_net_name_); - VerilogNetSeq::Iterator port_iter(module->ports()); - while (port_iter.hasNext()) { - VerilogNet *mod_port = port_iter.next(); - VerilogNetNameIterator *net_name_iter = mod_port->nameIterator(module, - this); - while (net_name_iter->hasNext()) { - const string &net_name = net_name_iter->next(); - Port *port = network_->findPort(top_cell, net_name.c_str()); - Net *net = bindings.ensureNetBinding(net_name.c_str(), top_instance, network_); - // Guard against repeated port name. - if (network_->findPin(top_instance, port) == nullptr) { - Pin *pin = network_->makePin(top_instance, port, nullptr); - network_->makeTerm(pin, net); - } - } - delete net_name_iter; + for (VerilogNet *mod_port : *module->ports()) { + VerilogNetNameIterator *net_name_iter = mod_port->nameIterator(module, + this); + while (net_name_iter->hasNext()) { + const string &net_name = net_name_iter->next(); + Port *port = network_->findPort(top_cell, net_name.c_str()); + Net *net = bindings.ensureNetBinding(net_name.c_str(), top_instance, network_); + // Guard against repeated port name. + if (network_->findPin(top_instance, port) == nullptr) { + Pin *pin = network_->makePin(top_instance, port, nullptr); + network_->makeTerm(pin, net); + } + } + delete net_name_iter; } makeModuleInstBody(module, top_instance, &bindings, make_black_boxes); bool errors = reportLinkErrors(); if (delete_modules) deleteModules(); if (errors) { - network_->deleteInstance(top_instance); - return nullptr; + network_->deleteInstance(top_instance); + return nullptr; } else - return top_instance; + return top_instance; } else { report_->error(1398, "%s is not a verilog module.", top_cell_name); @@ -1754,50 +1754,46 @@ VerilogReader::linkNetwork(const char *top_cell_name, void VerilogReader::makeModuleInstBody(VerilogModule *module, - Instance *inst, - VerilogBindingTbl *bindings, - bool make_black_boxes) + Instance *inst, + VerilogBindingTbl *bindings, + bool make_black_boxes) { - VerilogStmtSeq::Iterator stmt_iter(module->stmts()); - while (stmt_iter.hasNext()) { - VerilogStmt *stmt = stmt_iter.next(); + for (VerilogStmt *stmt : *module->stmts()) { if (stmt->isModuleInst()) makeModuleInstNetwork(dynamic_cast(stmt), - inst, module, bindings, make_black_boxes); + inst, module, bindings, make_black_boxes); else if (stmt->isLibertyInst()) makeLibertyInst(dynamic_cast(stmt), - inst, module, bindings); + inst, module, bindings); else if (stmt->isDeclaration()) { VerilogDcl *dcl = dynamic_cast(stmt); PortDirection *dir = dcl->direction(); - VerilogDclArgSeq::Iterator arg_iter(dcl->args()); - while (arg_iter.hasNext()) { - VerilogDclArg *arg = arg_iter.next(); - VerilogAssign *assign = arg->assign(); - if (assign) - mergeAssignNet(assign, module, inst, bindings); - if (dir->isGround()) { - Net *net = bindings->ensureNetBinding(arg->netName().c_str(),inst,network_); - network_->addConstantNet(net, LogicValue::zero); - } - if (dir->isPower()) { - Net *net = bindings->ensureNetBinding(arg->netName().c_str(),inst,network_); - network_->addConstantNet(net, LogicValue::one); - } + for (VerilogDclArg *arg : *dcl->args()) { + VerilogAssign *assign = arg->assign(); + if (assign) + mergeAssignNet(assign, module, inst, bindings); + if (dir->isGround()) { + Net *net = bindings->ensureNetBinding(arg->netName().c_str(),inst,network_); + network_->addConstantNet(net, LogicValue::zero); + } + if (dir->isPower()) { + Net *net = bindings->ensureNetBinding(arg->netName().c_str(),inst,network_); + network_->addConstantNet(net, LogicValue::one); + } } } else if (stmt->isAssign()) mergeAssignNet(dynamic_cast(stmt), module, inst, - bindings); + bindings); } } void VerilogReader::makeModuleInstNetwork(VerilogModuleInst *mod_inst, - Instance *parent, - VerilogModule *parent_module, - VerilogBindingTbl *parent_bindings, - bool make_black_boxes) + Instance *parent, + VerilogModule *parent_module, + VerilogBindingTbl *parent_bindings, + bool make_black_boxes) { const string &module_name = mod_inst->moduleName(); Cell *cell = network_->findAnyCell(module_name.c_str()); @@ -1806,22 +1802,22 @@ VerilogReader::makeModuleInstNetwork(VerilogModuleInst *mod_inst, if (make_black_boxes) { cell = makeBlackBox(mod_inst, parent_module); linkWarn(198, parent_module->filename(), mod_inst->line(), - "module %s not found. Creating black box for %s.", - mod_inst->moduleName().c_str(), - inst_vname.c_str()); + "module %s not found. Creating black box for %s.", + mod_inst->moduleName().c_str(), + inst_vname.c_str()); } else linkError(199, parent_module->filename(), mod_inst->line(), - "module %s not found for instance %s.", - mod_inst->moduleName().c_str(), - inst_vname.c_str()); + "module %s not found for instance %s.", + mod_inst->moduleName().c_str(), + inst_vname.c_str()); } if (cell) { LibertyCell *lib_cell = network_->libertyCell(cell); if (lib_cell) cell = network_->cell(lib_cell); Instance *inst = network_->makeInstance(cell, mod_inst->instanceName().c_str(), - parent); + parent); VerilogAttrStmtSeq *attr_stmts = mod_inst->attrStmts(); for (VerilogAttrStmt *stmt : *attr_stmts) { for (VerilogAttrEntry *entry : *stmt->attrs()) { @@ -1833,19 +1829,19 @@ VerilogReader::makeModuleInstNetwork(VerilogModuleInst *mod_inst, // Make all pins so timing arcs are built. LibertyCellPortBitIterator port_iter(lib_cell); while (port_iter.hasNext()) { - LibertyPort *port = port_iter.next(); - network_->makePin(inst, reinterpret_cast(port), nullptr); + LibertyPort *port = port_iter.next(); + network_->makePin(inst, reinterpret_cast(port), nullptr); } } bool is_leaf = network_->isLeaf(cell); VerilogBindingTbl bindings(zero_net_name_, one_net_name_); if (mod_inst->hasPins()) { if (mod_inst->namedPins()) - makeNamedInstPins(cell, inst, mod_inst, &bindings, parent, - parent_module, parent_bindings, is_leaf); + makeNamedInstPins(cell, inst, mod_inst, &bindings, parent, + parent_module, parent_bindings, is_leaf); else - makeOrderedInstPins(cell, inst, mod_inst, &bindings, parent, - parent_module, parent_bindings, is_leaf); + makeOrderedInstPins(cell, inst, mod_inst, &bindings, parent, + parent_module, parent_bindings, is_leaf); } if (!is_leaf) { VerilogModule *module = this->module(cell); @@ -1857,96 +1853,97 @@ VerilogReader::makeModuleInstNetwork(VerilogModuleInst *mod_inst, void VerilogReader::makeNamedInstPins(Cell *cell, - Instance *inst, - VerilogModuleInst *mod_inst, - VerilogBindingTbl *bindings, - Instance *parent, - VerilogModule *parent_module, - VerilogBindingTbl *parent_bindings, - bool is_leaf) + Instance *inst, + VerilogModuleInst *mod_inst, + VerilogBindingTbl *bindings, + Instance *parent, + VerilogModule *parent_module, + VerilogBindingTbl *parent_bindings, + bool is_leaf) { string inst_vname = instanceVerilogName(mod_inst->instanceName().c_str()); - VerilogNetSeq::Iterator pin_iter(mod_inst->pins()); - while (pin_iter.hasNext()) { - VerilogNetPortRef *vpin = dynamic_cast(pin_iter.next()); + for (auto mpin : *mod_inst->pins()) { + VerilogNetPortRef *vpin = dynamic_cast(mpin); const char *port_name = vpin->name().c_str(); Port *port = network_->findPort(cell, port_name); if (port) { if (vpin->hasNet() - && network_->size(port) != vpin->size(parent_module)) { - linkWarn(200, parent_module->filename(), mod_inst->line(), - "instance %s port %s size %d does not match net size %d.", - inst_vname.c_str(), - network_->name(port), - network_->size(port), - vpin->size(parent_module)); + && network_->size(port) != vpin->size(parent_module)) { + linkWarn(200, parent_module->filename(), mod_inst->line(), + "instance %s port %s size %d does not match net size %d.", + inst_vname.c_str(), + network_->name(port), + network_->size(port), + vpin->size(parent_module)); } else { - VerilogNetNameIterator *net_name_iter = - vpin->nameIterator(parent_module, this); - if (network_->hasMembers(port)) { - PortMemberIterator *port_iter = network_->memberIterator(port); - while (port_iter->hasNext()) { - Port *port = port_iter->next(); - makeInstPin(inst, port, net_name_iter, bindings, - parent, parent_bindings, is_leaf); - } - delete port_iter; - } - else { - makeInstPin(inst, port, net_name_iter, bindings, - parent, parent_bindings, is_leaf); - } - delete net_name_iter; + VerilogNetNameIterator *net_name_iter = + vpin->nameIterator(parent_module, this); + if (network_->hasMembers(port)) { + PortMemberIterator *port_iter = network_->memberIterator(port); + while (port_iter->hasNext()) { + Port *port = port_iter->next(); + makeInstPin(inst, port, net_name_iter, bindings, + parent, parent_bindings, is_leaf); + } + delete port_iter; + } + else { + makeInstPin(inst, port, net_name_iter, bindings, + parent, parent_bindings, is_leaf); + } + delete net_name_iter; } } else linkWarn(201, parent_module->filename(), mod_inst->line(), - "instance %s port %s not found.", - inst_vname.c_str(), - port_name); + "instance %s port %s not found.", + inst_vname.c_str(), + port_name); } } void VerilogReader::makeOrderedInstPins(Cell *cell, - Instance *inst, - VerilogModuleInst *mod_inst, - VerilogBindingTbl *bindings, - Instance *parent, - VerilogModule *parent_module, - VerilogBindingTbl *parent_bindings, - bool is_leaf) + Instance *inst, + VerilogModuleInst *mod_inst, + VerilogBindingTbl *bindings, + Instance *parent, + VerilogModule *parent_module, + VerilogBindingTbl *parent_bindings, + bool is_leaf) { CellPortIterator *port_iter = network_->portIterator(cell); - VerilogNetSeq::Iterator pin_iter(mod_inst->pins()); - while (pin_iter.hasNext() && port_iter->hasNext()) { - VerilogNet *net = pin_iter.next(); + VerilogNetSeq *mod_pins = mod_inst->pins(); + VerilogNetSeq::iterator pin_iter = mod_pins->begin(); + while (pin_iter != mod_pins->end() + && port_iter->hasNext()) { + VerilogNet *net = *pin_iter++; Port *port = port_iter->next(); if (network_->size(port) != net->size(parent_module)) { string inst_vname = instanceVerilogName(mod_inst->instanceName().c_str()); linkWarn(202, parent_module->filename(), mod_inst->line(), - "instance %s port %s size %d does not match net size %d.", - inst_vname.c_str(), - network_->name(port), - network_->size(port), - net->size(parent_module)); + "instance %s port %s size %d does not match net size %d.", + inst_vname.c_str(), + network_->name(port), + network_->size(port), + net->size(parent_module)); } else { VerilogNetNameIterator *net_name_iter=net->nameIterator(parent_module, - this); + this); if (network_->isBus(port)) { - PortMemberIterator *member_iter = network_->memberIterator(port); - while (member_iter->hasNext() && net_name_iter->hasNext()) { - Port *port = member_iter->next(); - makeInstPin(inst, port, net_name_iter, bindings, - parent, parent_bindings, is_leaf); - } - delete member_iter; + PortMemberIterator *member_iter = network_->memberIterator(port); + while (member_iter->hasNext() && net_name_iter->hasNext()) { + Port *port = member_iter->next(); + makeInstPin(inst, port, net_name_iter, bindings, + parent, parent_bindings, is_leaf); + } + delete member_iter; } else - makeInstPin(inst, port, net_name_iter, bindings, - parent, parent_bindings, is_leaf); + makeInstPin(inst, port, net_name_iter, bindings, + parent, parent_bindings, is_leaf); delete net_name_iter; } } @@ -1955,28 +1952,28 @@ VerilogReader::makeOrderedInstPins(Cell *cell, void VerilogReader::makeInstPin(Instance *inst, - Port *port, - VerilogNetNameIterator *net_name_iter, - VerilogBindingTbl *bindings, - Instance *parent, - VerilogBindingTbl *parent_bindings, - bool is_leaf) + Port *port, + VerilogNetNameIterator *net_name_iter, + VerilogBindingTbl *bindings, + Instance *parent, + VerilogBindingTbl *parent_bindings, + bool is_leaf) { string net_name; if (net_name_iter->hasNext()) net_name = net_name_iter->next(); makeInstPin(inst, port, net_name, bindings, parent, parent_bindings, - is_leaf); + is_leaf); } void VerilogReader::makeInstPin(Instance *inst, - Port *port, - const string &net_name, - VerilogBindingTbl *bindings, - Instance *parent, - VerilogBindingTbl *parent_bindings, - bool is_leaf) + Port *port, + const string &net_name, + VerilogBindingTbl *bindings, + Instance *parent, + VerilogBindingTbl *parent_bindings, + bool is_leaf) { Net *net = nullptr; if (!net_name.empty()) @@ -1998,14 +1995,14 @@ VerilogReader::makeInstPin(Instance *inst, void VerilogReader::makeLibertyInst(VerilogLibertyInst *lib_inst, - Instance *parent, - VerilogModule *parent_module, - VerilogBindingTbl *parent_bindings) + Instance *parent, + VerilogModule *parent_module, + VerilogBindingTbl *parent_bindings) { LibertyCell *lib_cell = lib_inst->cell(); Cell *cell = reinterpret_cast(lib_cell); Instance *inst = network_->makeInstance(cell, lib_inst->instanceName().c_str(), - parent); + parent); VerilogAttrStmtSeq *attr_stmts = lib_inst->attrStmts(); for (VerilogAttrStmt *stmt : *attr_stmts) { for (VerilogAttrEntry *entry : *stmt->attrs()) { @@ -2043,11 +2040,11 @@ VerilogReader::makeLibertyInst(VerilogLibertyInst *lib_inst, Cell * VerilogReader::makeBlackBox(VerilogModuleInst *mod_inst, - VerilogModule *parent_module) + VerilogModule *parent_module) { const string &module_name = mod_inst->moduleName(); Cell *cell = network_->makeCell(library_, module_name.c_str(), true, - parent_module->filename()); + parent_module->filename()); if (mod_inst->namedPins()) makeBlackBoxNamedPorts(cell, mod_inst, parent_module); else @@ -2057,12 +2054,11 @@ VerilogReader::makeBlackBox(VerilogModuleInst *mod_inst, void VerilogReader::makeBlackBoxNamedPorts(Cell *cell, - VerilogModuleInst *mod_inst, - VerilogModule *parent_module) + VerilogModuleInst *mod_inst, + VerilogModule *parent_module) { - VerilogNetSeq::Iterator pin_iter(mod_inst->pins()); - while (pin_iter.hasNext()) { - VerilogNetNamed *vpin = dynamic_cast(pin_iter.next()); + for (VerilogNet *mpin : *mod_inst->pins()) { + VerilogNetNamed *vpin = dynamic_cast(mpin); const char *port_name = vpin->name().c_str(); size_t size = vpin->size(parent_module); Port *port = (size == 1) @@ -2074,21 +2070,22 @@ VerilogReader::makeBlackBoxNamedPorts(Cell *cell, void VerilogReader::makeBlackBoxOrderedPorts(Cell *cell, - VerilogModuleInst *mod_inst, - VerilogModule *parent_module) + VerilogModuleInst *mod_inst, + VerilogModule *parent_module) { int port_index = 0; - VerilogNetSeq::Iterator pin_iter(mod_inst->pins()); - while (pin_iter.hasNext()) { - VerilogNet *net = pin_iter.next(); - size_t size = net->size(parent_module); - char *port_name = stringPrint("p_%d", port_index); - Port *port = (size == 1) - ? network_->makePort(cell, port_name) - : network_->makeBusPort(cell, port_name, size - 1, 0); - stringDelete(port_name); - network_->setDirection(port, PortDirection::unknown()); - port_index++; + VerilogNetSeq *nets = mod_inst->pins(); + if (nets) { + for (VerilogNet *net : *nets) { + size_t size = net->size(parent_module); + char *port_name = stringPrint("p_%d", port_index); + Port *port = (size == 1) + ? network_->makePort(cell, port_name) + : network_->makeBusPort(cell, port_name, size - 1, 0); + stringDelete(port_name); + network_->setDirection(port, PortDirection::unknown()); + port_index++; + } } } @@ -2102,9 +2099,9 @@ VerilogReader::isBlackBox(Cell *cell) void VerilogReader::mergeAssignNet(VerilogAssign *assign, - VerilogModule *module, - Instance *inst, - VerilogBindingTbl *bindings) + VerilogModule *module, + Instance *inst, + VerilogBindingTbl *bindings) { VerilogNet *lhs = assign->lhs(); VerilogNet *rhs = assign->rhs(); @@ -2120,9 +2117,9 @@ VerilogReader::mergeAssignNet(VerilogAssign *assign, // instances from the bottom up does not reference deleted nets // by referencing the mergedInto field. if (hierarchyLevel(lhs_net,network_) >= hierarchyLevel(rhs_net,network_)) - network_->mergeInto(lhs_net, rhs_net); + network_->mergeInto(lhs_net, rhs_net); else - network_->mergeInto(rhs_net, lhs_net); + network_->mergeInto(rhs_net, lhs_net); // No need to update binding tables because the VerilogBindingTbl::find // finds the net that survives the merge. } @@ -2131,14 +2128,14 @@ VerilogReader::mergeAssignNet(VerilogAssign *assign, } else linkWarn(203, module->filename(), assign->line(), - "assign left hand side size %d not equal right hand size %d.", - lhs->size(module), - rhs->size(module)); + "assign left hand side size %d not equal right hand size %d.", + lhs->size(module), + rhs->size(module)); } static int hierarchyLevel(Net *net, - Network *network) + Network *network) { Instance *parent = network->instance(net); int level = 0; @@ -2152,7 +2149,7 @@ hierarchyLevel(Net *net, //////////////////////////////////////////////////////////////// VerilogBindingTbl::VerilogBindingTbl(const string &zero_net_name, - const string &one_net_name) : + const string &one_net_name) : zero_net_name_(zero_net_name), one_net_name_(one_net_name) { @@ -2164,7 +2161,7 @@ VerilogBindingTbl::VerilogBindingTbl(const string &zero_net_name, Net * VerilogBindingTbl::find(const char *name, NetworkReader *network) { - Net *net = map_.findKey(name); + Net *net = findKey(map_, name); while (net && network->mergedInto(net)) net = network->mergedInto(net); return net; @@ -2172,15 +2169,15 @@ VerilogBindingTbl::find(const char *name, NetworkReader *network) void VerilogBindingTbl::bind(const char *name, - Net *net) + Net *net) { map_[name] = net; } Net * VerilogBindingTbl::ensureNetBinding(const char *net_name, - Instance *inst, - NetworkReader *network) + Instance *inst, + NetworkReader *network) { Net *net = find(net_name, network); if (net == nullptr) { @@ -2199,8 +2196,8 @@ VerilogBindingTbl::ensureNetBinding(const char *net_name, void VerilogReader::linkWarn(int id, const char *filename, - int line, - const char *msg, ...) + int line, + const char *msg, ...) { va_list args; va_start(args, msg); @@ -2213,8 +2210,8 @@ VerilogReader::linkWarn(int id, void VerilogReader::linkError(int id, const char *filename, - int line, - const char *msg, ...) + int line, + const char *msg, ...) { va_list args; va_start(args, msg); @@ -2231,9 +2228,7 @@ VerilogReader::reportLinkErrors() // they are discovered. sort(link_errors_, VerilogErrorCmp()); bool errors = false; - VerilogErrorSeq::Iterator error_iter(link_errors_); - while (error_iter.hasNext()) { - VerilogError *error = error_iter.next(); + for (VerilogError *error : link_errors_) { // Report as warnings to avoid throwing. report_->fileWarn(error->id(), error->filename(), error->line(), "%s", error->msg()); errors |= !error->warn(); diff --git a/verilog/VerilogReader.hh b/verilog/VerilogReader.hh deleted file mode 100644 index aca56682..00000000 --- a/verilog/VerilogReader.hh +++ /dev/null @@ -1,296 +0,0 @@ -// OpenSTA, Static Timing Analyzer -// Copyright (c) 2025, Parallax Software, Inc. -// -// This program is free software: you can redistribute it and/or modify -// it under the terms of the GNU General Public License as published by -// the Free Software Foundation, either version 3 of the License, or -// (at your option) any later version. -// -// This program is distributed in the hope that it will be useful, -// but WITHOUT ANY WARRANTY; without even the implied warranty of -// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -// GNU General Public License for more details. -// -// You should have received a copy of the GNU General Public License -// along with this program. If not, see . -// -// The origin of this software must not be misrepresented; you must not -// claim that you wrote the original software. -// -// Altered source versions must be plainly marked as such, and must not be -// misrepresented as being the original software. -// -// This notice may not be removed or altered from any source distribution. - -#pragma once - -#include - -#include "StringSet.hh" -#include "Vector.hh" -#include "Map.hh" -#include "NetworkClass.hh" - -namespace sta { - -class VerilogScanner; -class VerilogParse; -class Debug; -class Report; -class VerilogAttrEntry; -class VerilogAttrStmt; -class VerilogReader; -class VerilogStmt; -class VerilogNet; -class VerilogNetScalar; -class VerilogModule; -class VerilogInst; -class VerilogModuleInst; -class VerilogLibertyInst; -class VerilogDcl; -class VerilogDclBus; -class VerilogDclArg; -class VerilogAssign; -class VerilogNetConcat; -class VerilogNetConstant; -class VerilogNetBitSelect; -class VerilogNetPartSelect; -class StringRegistry; -class VerilogBindingTbl; -class VerilogNetNameIterator; -class VerilogNetPortRef; -class VerilogError; -class LibertyCell; - -typedef Map VerilogModuleMap; -typedef Vector VerilogStmtSeq; -typedef Vector VerilogNetSeq; -typedef Vector VerilogDclArgSeq; -typedef Vector VerilogAttrStmtSeq; -typedef Vector VerilogAttrEntrySeq; -typedef Vector VerilogErrorSeq; - -class VerilogReader -{ -public: - VerilogReader(NetworkReader *network); - ~VerilogReader(); - bool read(const char *filename); - - void makeModule(const std::string *module_name, - VerilogNetSeq *ports, - VerilogStmtSeq *stmts, - VerilogAttrStmtSeq *attr_stmts, - int line); - void makeModule(const std::string *module_name, - VerilogStmtSeq *port_dcls, - VerilogStmtSeq *stmts, - VerilogAttrStmtSeq *attr_stmts, - int line); - VerilogDcl *makeDcl(PortDirection *dir, - VerilogDclArgSeq *args, - VerilogAttrStmtSeq *attr_stmts, - int line); - VerilogDcl *makeDcl(PortDirection *dir, - VerilogDclArg *arg, - VerilogAttrStmtSeq *attr_stmts, - int line); - VerilogDclArg *makeDclArg(const std::string *net_name); - VerilogDclArg*makeDclArg(VerilogAssign *assign); - VerilogDclBus *makeDclBus(PortDirection *dir, - int from_index, - int to_index, - VerilogDclArg *arg, - VerilogAttrStmtSeq *attr_stmts, - int line); - VerilogDclBus *makeDclBus(PortDirection *dir, - int from_index, - int to_index, - VerilogDclArgSeq *args, - VerilogAttrStmtSeq *attr_stmts, - int line); - VerilogInst *makeModuleInst(const std::string *module_name, - const std::string *inst_name, - VerilogNetSeq *pins, - VerilogAttrStmtSeq *attr_stmts, - const int line); - VerilogAssign *makeAssign(VerilogNet *lhs, - VerilogNet *rhs, - int line); - VerilogNetScalar *makeNetScalar(const std::string *name); - VerilogNetPortRef *makeNetNamedPortRefScalarNet(const std::string *port_vname); - VerilogNetPortRef *makeNetNamedPortRefScalarNet(const std::string *port_name, - const std::string *net_name); - VerilogNetPortRef *makeNetNamedPortRefBitSelect(const std::string *port_name, - const std::string *bus_name, - int index); - VerilogNetPortRef *makeNetNamedPortRefScalar(const std::string *port_name, - VerilogNet *net); - VerilogNetPortRef *makeNetNamedPortRefBit(const std::string *port_name, - int index, - VerilogNet *net); - VerilogNetPortRef *makeNetNamedPortRefPart(const std::string *port_name, - int from_index, - int to_index, - VerilogNet *net); - VerilogNetConcat *makeNetConcat(VerilogNetSeq *nets); - VerilogNetConstant *makeNetConstant(const std::string *constant, - int line); - VerilogNetBitSelect *makeNetBitSelect(const std::string *name, - int index); - VerilogNetPartSelect *makeNetPartSelect(const std::string *name, - int from_index, - int to_index); - VerilogModule *module(Cell *cell); - Instance *linkNetwork(const char *top_cell_name, - bool make_black_boxes, - bool delete_modules); - const char *filename() const { return filename_.c_str(); } - void incrLine(); - Report *report() const { return report_; } - void error(int id, - const char *filename, - int line, - const char *fmt, ...); - void warn(int id, - const char *filename, - int line, - const char *fmt, ...); - const std::string &zeroNetName() const { return zero_net_name_; } - const std::string &oneNetName() const { return one_net_name_; } - void deleteModules(); - void reportStmtCounts(); - const std::string &constant10Max() const { return constant10_max_; } - -protected: - void init(const char *filename); - void makeCellPorts(Cell *cell, - VerilogModule *module, - VerilogNetSeq *ports); - Port *makeCellPort(Cell *cell, - VerilogModule *module, - const std::string &port_name); - void makeNamedPortRefCellPorts(Cell *cell, - VerilogModule *module, - VerilogNet *mod_port, - StdStringSet &port_names); - void checkModuleDcls(VerilogModule *module, - std::set &port_names); - void makeModuleInstBody(VerilogModule *module, - Instance *inst, - VerilogBindingTbl *bindings, - bool make_black_boxes); - void makeModuleInstNetwork(VerilogModuleInst *mod_inst, - Instance *parent, - VerilogModule *parent_module, - VerilogBindingTbl *parent_bindings, - bool make_black_boxes); - void makeLibertyInst(VerilogLibertyInst *lib_inst, - Instance *parent, - VerilogModule *parent_module, - VerilogBindingTbl *parent_bindings); - void bindGlobalNets(VerilogBindingTbl *bindings); - void makeNamedInstPins1(Cell *cell, - Instance *inst, - VerilogModuleInst *mod_inst, - VerilogBindingTbl *bindings, - Instance *parent, - VerilogBindingTbl *parent_bindings, - bool is_leaf); - void makeNamedInstPins(Cell *cell, - Instance *inst, - VerilogModuleInst *mod_inst, - VerilogBindingTbl *bindings, - Instance *parent, - VerilogModule *parent_module, - VerilogBindingTbl *parent_bindings, - bool is_leaf); - void makeOrderedInstPins(Cell *cell, - Instance *inst, - VerilogModuleInst *mod_inst, - VerilogBindingTbl *bindings, - Instance *parent, - VerilogModule *parent_module, - VerilogBindingTbl *parent_bindings, - bool is_leaf); - void mergeAssignNet(VerilogAssign *assign, - VerilogModule *module, - Instance *inst, - VerilogBindingTbl *bindings); - void makeInstPin(Instance *inst, - Port *port, - VerilogNetNameIterator *net_name_iter, - VerilogBindingTbl *bindings, - Instance *parent, - VerilogBindingTbl *parent_bindings, - bool is_leaf); - void makeInstPin(Instance *inst, - Port *port, - const std::string &net_name, - VerilogBindingTbl *bindings, - Instance *parent, - VerilogBindingTbl *parent_bindings, - bool is_leaf); - void linkWarn(int id, - const char *filename, - int line, - const char *msg, ...) - __attribute__((format (printf, 5, 6))); - void linkError(int id, - const char *filename, - int line, - const char *msg, ...) - __attribute__((format (printf, 5, 6))); - bool reportLinkErrors(); - bool haveLinkErrors(); - Cell *makeBlackBox(VerilogModuleInst *mod_inst, - VerilogModule *parent_module); - void makeBlackBoxNamedPorts(Cell *cell, - VerilogModuleInst *mod_inst, - VerilogModule *parent_module); - void makeBlackBoxOrderedPorts(Cell *cell, - VerilogModuleInst *mod_inst, - VerilogModule *parent_module); - bool isBlackBox(Cell *cell); - bool hasScalarNamedPortRefs(LibertyCell *liberty_cell, - VerilogNetSeq *pins); - - std::string filename_; - Report *report_; - Debug *debug_; - NetworkReader *network_; - - Library *library_; - int black_box_index_; - VerilogModuleMap module_map_; - VerilogErrorSeq link_errors_; - const std::string zero_net_name_; - const std::string one_net_name_; - std::string constant10_max_; - ViewType *view_type_; - bool report_stmt_stats_; - int module_count_; - int inst_mod_count_; - int inst_lib_count_; - int inst_lib_net_arrays_; - int port_names_; - int inst_module_names_; - int inst_names_; - int dcl_count_; - int dcl_bus_count_; - int dcl_arg_count_; - int net_scalar_count_; - int net_scalar_names_; - int net_bus_names_; - int net_part_select_count_; - int net_bit_select_count_; - int net_port_ref_scalar_count_; - int net_port_ref_scalar_net_count_; - int net_port_ref_bit_count_; - int net_port_ref_part_count_; - int net_constant_count_; - int assign_count_; - int concat_count_; -}; - -} // namespace sta diff --git a/verilog/VerilogReaderPvt.hh b/verilog/VerilogReaderPvt.hh index aa1dc207..60498c7d 100644 --- a/verilog/VerilogReaderPvt.hh +++ b/verilog/VerilogReaderPvt.hh @@ -25,16 +25,16 @@ #pragma once #include +#include +#include -#include "Map.hh" -#include "Vector.hh" #include "StringSeq.hh" namespace sta { -typedef Map VerilogDclMap; -typedef Vector VerilogConstantValue; -typedef std::vector StdStringSeq; +using VerilogDclMap = std::map; +using VerilogConstantValue = std::vector; +using StdStringSeq = std::vector; class VerilogStmt { @@ -71,13 +71,13 @@ public: VerilogStmtSeq *stmts() { return stmts_; } VerilogDclMap *declarationMap() { return &dcl_map_; } void parseDcl(VerilogDcl *dcl, - VerilogReader *reader); + VerilogReader *reader); private: void parseStmts(VerilogReader *reader); void checkInstanceName(VerilogInst *inst, - StdStringSet &inst_names, - VerilogReader *reader); + StdStringSet &inst_names, + VerilogReader *reader); std::string name_; std::string filename_; @@ -160,8 +160,8 @@ class VerilogAssign : public VerilogStmt { public: VerilogAssign(VerilogNet *lhs, - VerilogNet *rhs, - int line); + VerilogNet *rhs, + int line); virtual ~VerilogAssign(); virtual bool isAssign() const { return true; } VerilogNet *lhs() const { return lhs_; } @@ -241,7 +241,7 @@ public: virtual bool isNamedPortRefScalarNet() const { return false; } virtual int size(VerilogModule *module) = 0; virtual VerilogNetNameIterator *nameIterator(VerilogModule *module, - VerilogReader *reader) = 0; + VerilogReader *reader) = 0; }; class VerilogNetUnnamed : public VerilogNet @@ -276,19 +276,19 @@ public: virtual bool isScalar() const { return true; } virtual int size(VerilogModule *module); virtual VerilogNetNameIterator *nameIterator(VerilogModule *module, - VerilogReader *reader); + VerilogReader *reader); }; class VerilogNetBitSelect : public VerilogNetNamed { public: VerilogNetBitSelect(const std::string &name, - int index); + int index); int index() { return index_; } virtual bool isScalar() const { return false; } virtual int size(VerilogModule *module); virtual VerilogNetNameIterator *nameIterator(VerilogModule *module, - VerilogReader *reader); + VerilogReader *reader); private: int index_; }; @@ -297,12 +297,12 @@ class VerilogNetPartSelect : public VerilogNetNamed { public: VerilogNetPartSelect(const std::string &name, - int from_index, - int to_index); + int from_index, + int to_index); virtual bool isScalar() const { return false; } virtual int size(VerilogModule *module); virtual VerilogNetNameIterator *nameIterator(VerilogModule *module, - VerilogReader *reader); + VerilogReader *reader); int fromIndex() const { return from_index_; } int toIndex() const { return to_index_; } @@ -315,24 +315,24 @@ class VerilogNetConstant : public VerilogNetUnnamed { public: VerilogNetConstant(const std::string *constant, - VerilogReader *reader, + VerilogReader *reader, int line); virtual ~VerilogNetConstant(); virtual int size(VerilogModule *module); virtual VerilogNetNameIterator *nameIterator(VerilogModule *module, - VerilogReader *reader); + VerilogReader *reader); private: void parseConstant(const std::string *constant, - VerilogReader *reader, + VerilogReader *reader, int line); void parseConstant(const std::string *constant, - size_t base_idx, - int base, - int digit_bit_count); + size_t base_idx, + int base, + int digit_bit_count); void parseConstant10(const std::string *constant, size_t base_idx, - VerilogReader *reader, + VerilogReader *reader, int line); VerilogConstantValue *value_; @@ -345,7 +345,7 @@ public: virtual ~VerilogNetConcat(); virtual int size(VerilogModule *module); virtual VerilogNetNameIterator *nameIterator(VerilogModule *module, - VerilogReader *reader); + VerilogReader *reader); private: VerilogNetSeq *nets_; @@ -369,12 +369,12 @@ class VerilogNetPortRefScalarNet : public VerilogNetPortRef public: VerilogNetPortRefScalarNet(const std::string &name); VerilogNetPortRefScalarNet(const std::string &name, - const std::string &net_name); + const std::string &net_name); virtual bool isScalar() const { return true; } virtual bool isNamedPortRefScalarNet() const { return true; } virtual int size(VerilogModule *module); virtual VerilogNetNameIterator *nameIterator(VerilogModule *module, - VerilogReader *reader); + VerilogReader *reader); virtual bool hasNet() { return !net_name_.empty(); } const std::string &netName() const { return net_name_; } void setNetName(const std::string &net_name) { net_name_ = net_name; } @@ -387,12 +387,12 @@ class VerilogNetPortRefScalar : public VerilogNetPortRef { public: VerilogNetPortRefScalar(const std::string &name, - VerilogNet *net); + VerilogNet *net); virtual ~VerilogNetPortRefScalar(); virtual bool isScalar() const { return true; } virtual int size(VerilogModule *module); virtual VerilogNetNameIterator *nameIterator(VerilogModule *module, - VerilogReader *reader); + VerilogReader *reader); virtual bool hasNet() { return net_ != nullptr; } private: @@ -403,8 +403,8 @@ class VerilogNetPortRefBit : public VerilogNetPortRefScalar { public: VerilogNetPortRefBit(const std::string &name, - int index, - VerilogNet *net); + int index, + VerilogNet *net); const std::string &name() const override { return bit_name_; } private: @@ -415,9 +415,9 @@ class VerilogNetPortRefPart : public VerilogNetPortRefBit { public: VerilogNetPortRefPart(const std::string &name, - int from_index, - int to_index, - VerilogNet *net); + int from_index, + int to_index, + VerilogNet *net); const std::string &name() const override; int toIndex() const { return to_index_; } diff --git a/verilog/VerilogWriter.cc b/verilog/VerilogWriter.cc index dd856d7b..3ba02ba9 100644 --- a/verilog/VerilogWriter.cc +++ b/verilog/VerilogWriter.cc @@ -26,6 +26,7 @@ #include #include +#include #include "Error.hh" #include "Liberty.hh" @@ -45,10 +46,10 @@ class VerilogWriter { public: VerilogWriter(const char *filename, - bool include_pwr_gnd, - CellSeq *remove_cells, - FILE *stream, - Network *network); + bool include_pwr_gnd, + CellSeq *remove_cells, + FILE *stream, + Network *network); void writeModules(); protected: @@ -64,14 +65,14 @@ protected: void writeChildren(const Instance *inst); void writeChild(const Instance *child); void writeInstPin(const Instance *inst, - const Port *port, - bool &first_port); + const Port *port, + bool &first_port); void writeInstBusPin(const Instance *inst, - const Port *port, - bool &first_port); + const Port *port, + bool &first_port); void writeInstBusPinBit(const Instance *inst, - const Port *port, - bool &first_member); + const Port *port, + bool &first_member); void writeAssigns(const Instance *inst); int findUnconnectedNetCount(const Instance *inst); @@ -89,15 +90,15 @@ protected: void writeVerilog(const char *filename, - bool include_pwr_gnd, - CellSeq *remove_cells, - Network *network) + bool include_pwr_gnd, + CellSeq *remove_cells, + Network *network) { if (network->topInstance()) { FILE *stream = fopen(filename, "w"); if (stream) { VerilogWriter writer(filename, include_pwr_gnd, - remove_cells, stream, network); + remove_cells, stream, network); writer.writeModules(); fclose(stream); } @@ -107,10 +108,10 @@ writeVerilog(const char *filename, } VerilogWriter::VerilogWriter(const char *filename, - bool include_pwr_gnd, - CellSeq *remove_cells, - FILE *stream, - Network *network) : + bool include_pwr_gnd, + CellSeq *remove_cells, + FILE *stream, + Network *network) : filename_(filename), include_pwr_gnd_(include_pwr_gnd), remove_cells_(network), @@ -161,7 +162,7 @@ VerilogWriter::findHierChildren(const Instance *inst, const Instance *child = child_iter->next(); const Cell *cell = network_->cell(child); if (network_->isHierarchical(child) - && !cells.hasKey(cell)) { + && !cells.contains(cell)) { children.push_back(child); cells.insert(cell); findHierChildren(child, children, cells); @@ -262,14 +263,14 @@ VerilogWriter::verilogPortDir(PortDirection *dir) } } -typedef std::pair BusIndexRange; +using BusIndexRange = std::pair; void VerilogWriter::writeWireDcls(const Instance *inst) { Cell *cell = network_->cell(inst); char escape = network_->pathEscape(); - Map> bus_ranges; + std::map> bus_ranges; NetIterator *net_iter = network_->netIterator(inst); while (net_iter->hasNext()) { Net *net = net_iter->next(); @@ -313,7 +314,7 @@ VerilogWriter::writeWireDcls(const Instance *inst) void VerilogWriter::writeChildren(const Instance *inst) { - Vector children; + std::vector children; InstanceChildIterator *child_iter = network_->childIterator(inst); while (child_iter->hasNext()) { Instance *child = child_iter->next(); @@ -334,23 +335,23 @@ void VerilogWriter::writeChild(const Instance *child) { Cell *child_cell = network_->cell(child); - if (!remove_cells_.hasKey(child_cell)) { + if (!remove_cells_.contains(child_cell)) { const char *child_name = network_->name(child); string child_vname = instanceVerilogName(child_name); string child_cell_vname = cellVerilogName(network_->name(child_cell)); fprintf(stream_, " %s %s (", - child_cell_vname.c_str(), - child_vname.c_str()); + child_cell_vname.c_str(), + child_vname.c_str()); bool first_port = true; CellPortIterator *port_iter = network_->portIterator(child_cell); while (port_iter->hasNext()) { Port *port = port_iter->next(); if (include_pwr_gnd_ - || !network_->direction(port)->isPowerGround()) { - if (network_->hasMembers(port)) - writeInstBusPin(child, port, first_port); - else - writeInstPin(child, port, first_port); + || !network_->direction(port)->isPowerGround()) { + if (network_->hasMembers(port)) + writeInstBusPin(child, port, first_port); + else + writeInstPin(child, port, first_port); } } delete port_iter; @@ -360,8 +361,8 @@ VerilogWriter::writeChild(const Instance *child) void VerilogWriter::writeInstPin(const Instance *inst, - const Port *port, - bool &first_port) + const Port *port, + bool &first_port) { Pin *pin = network_->findPin(inst, port); if (pin) { @@ -370,11 +371,11 @@ VerilogWriter::writeInstPin(const Instance *inst, const char *net_name = network_->name(net); string net_vname = netVerilogName(net_name); if (!first_port) - fprintf(stream_, ",\n "); + fprintf(stream_, ",\n "); string port_vname = portVerilogName(network_->name(port)); fprintf(stream_, ".%s(%s)", - port_vname.c_str(), - net_vname.c_str()); + port_vname.c_str(), + net_vname.c_str()); first_port = false; } } @@ -382,8 +383,8 @@ VerilogWriter::writeInstPin(const Instance *inst, void VerilogWriter::writeInstBusPin(const Instance *inst, - const Port *port, - bool &first_port) + const Port *port, + bool &first_port) { if (!first_port) fprintf(stream_, ",\n "); @@ -416,8 +417,8 @@ VerilogWriter::writeInstBusPin(const Instance *inst, void VerilogWriter::writeInstBusPinBit(const Instance *inst, - const Port *port, - bool &first_member) + const Port *port, + bool &first_member) { Pin *pin = network_->findPin(inst, port); Net *net = pin ? network_->net(pin) : nullptr; @@ -485,7 +486,7 @@ VerilogWriter::findChildNCcount(const Instance *child) { int nc_count = 0; Cell *child_cell = network_->cell(child); - if (!remove_cells_.hasKey(child_cell)) { + if (!remove_cells_.contains(child_cell)) { CellPortIterator *port_iter = network_->portIterator(child_cell); while (port_iter->hasNext()) { Port *port = port_iter->next();

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