From cf1db116dca3ffac6edb3b261536f3680674a9ce Mon Sep 17 00:00:00 2001 From: Jaehyun Kim Date: Tue, 7 Apr 2026 00:06:42 +0900 Subject: [PATCH] Remove dead re-add constraint blocks from SDC tests removeConstraints was removed upstream in STA 3.0 (MCMM refactor). The "Re-add constraints" blocks were originally preceded by remove_constraints calls; without them, the re-adds are no-ops. Co-Authored-By: Claude Signed-off-by: Jaehyun Kim --- sdc/test/sdc_exception_merge_priority.ok | 81 ----------------------- sdc/test/sdc_exception_merge_priority.tcl | 17 +---- sdc/test/sdc_filter_query.tcl | 11 +-- 3 files changed, 2 insertions(+), 107 deletions(-) diff --git a/sdc/test/sdc_exception_merge_priority.ok b/sdc/test/sdc_exception_merge_priority.ok index 50af194d..873958c7 100644 --- a/sdc/test/sdc_exception_merge_priority.ok +++ b/sdc/test/sdc_exception_merge_priority.ok @@ -1094,86 +1094,5 @@ Path Type: max 7.89 slack (MET) -Startpoint: reg2 (rising edge-triggered flip-flop clocked by clk1) -Endpoint: out1 (output port clocked by clk1) -Path Group: grp1 -Path Type: max - - Delay Time Description ---------------------------------------------------------- - 0.00 0.00 clock clk1 (rise edge) - 0.00 0.00 clock network delay (ideal) - 0.00 0.00 ^ reg2/CK (DFF_X1) - 0.08 0.08 ^ reg2/Q (DFF_X1) - 0.00 0.08 ^ out1 (out) - 0.08 data arrival time - - 20.00 20.00 clock clk1 (rise edge) - 0.00 20.00 clock network delay (ideal) - 0.00 20.00 clock reconvergence pessimism - -3.00 17.00 output external delay - 17.00 data required time ---------------------------------------------------------- - 17.00 data required time - -0.08 data arrival time ---------------------------------------------------------- - 16.92 slack (MET) - - -Startpoint: reg3 (rising edge-triggered flip-flop clocked by clk2) -Endpoint: out2 (output port clocked by clk2) -Path Group: grp3 -Path Type: max - - Delay Time Description ---------------------------------------------------------- - 0.00 0.00 clock clk2 (rise edge) - 0.00 0.00 clock network delay (ideal) - 0.00 0.00 ^ reg3/CK (DFF_X1) - 0.08 0.08 ^ reg3/Q (DFF_X1) - 0.00 0.08 ^ out2 (out) - 0.08 data arrival time - - 20.00 20.00 clock clk2 (rise edge) - 0.00 20.00 clock network delay (ideal) - 0.00 20.00 clock reconvergence pessimism - -3.00 17.00 output external delay - 17.00 data required time ---------------------------------------------------------- - 17.00 data required time - -0.08 data arrival time ---------------------------------------------------------- - 16.92 slack (MET) - - -Startpoint: in3 (input port clocked by clk2) -Endpoint: reg2 (rising edge-triggered flip-flop clocked by clk1) -Path Group: clk1 -Path Type: max - - Delay Time Description ---------------------------------------------------------- - 0.00 0.00 clock clk2 (rise edge) - 0.00 0.00 clock network delay (ideal) - 2.00 2.00 v input external delay - 0.00 2.00 v in3 (in) - 0.05 2.05 v or1/ZN (OR2_X1) - 0.03 2.07 ^ nor1/ZN (NOR2_X1) - 0.00 2.07 ^ reg2/D (DFF_X1) - 2.07 data arrival time - - 10.00 10.00 clock clk1 (rise edge) - 0.00 10.00 clock network delay (ideal) - 0.00 10.00 clock reconvergence pessimism - 10.00 ^ reg2/CK (DFF_X1) - -0.03 9.97 library setup time - 9.97 data required time ---------------------------------------------------------- - 9.97 data required time - -2.07 data arrival time ---------------------------------------------------------- - 7.89 slack (MET) - - --- write_sdc with exceptions --- --- write_sdc compatible with exceptions --- diff --git a/sdc/test/sdc_exception_merge_priority.tcl b/sdc/test/sdc_exception_merge_priority.tcl index 1c1938d7..a9c779a2 100644 --- a/sdc/test/sdc_exception_merge_priority.tcl +++ b/sdc/test/sdc_exception_merge_priority.tcl @@ -3,7 +3,7 @@ # Targets: ExceptionPath.cc exception merging, priority, matches, # overrides, through-pin matching, ExceptionThru matching, # Sdc.cc addException, findException, isPathGroupName, -# pathGroupNames, removeConstraints, constraintsChanged, +# pathGroupNames, # makeExceptionFrom/Thru/To, checkExceptionFromPins, # checkExceptionToPins, deleteExceptionFrom/Thru/To, # WriteSdc.cc writeExceptions (various exception types) @@ -115,21 +115,6 @@ puts "--- exception override: false path then max_delay ---" set_max_delay -from [get_ports in3] -to [get_ports out2] 5.0 report_checks -# Re-add constraints for write_sdc -create_clock -name clk1 -period 10 [get_ports clk1] -create_clock -name clk2 -period 20 [get_ports clk2] -set_input_delay -clock clk1 2.0 [get_ports in1] -set_input_delay -clock clk1 2.0 [get_ports in2] -set_input_delay -clock clk2 2.0 [get_ports in3] -set_output_delay -clock clk1 3.0 [get_ports out1] -set_output_delay -clock clk2 3.0 [get_ports out2] - -set_false_path -from [get_clocks clk1] -to [get_clocks clk2] -set_multicycle_path -setup 2 -from [get_ports in1] -to [get_ports out1] -set_max_delay -from [get_ports in2] -to [get_ports out1] 8.0 -group_path -name grp1 -from [get_clocks clk1] -report_checks - # Write SDC with all exception types puts "--- write_sdc with exceptions ---" set sdc1 [make_result_file sdc_exception_merge1.sdc] diff --git a/sdc/test/sdc_filter_query.tcl b/sdc/test/sdc_filter_query.tcl index d9113a0b..fa2a3467 100644 --- a/sdc/test/sdc_filter_query.tcl +++ b/sdc/test/sdc_filter_query.tcl @@ -4,8 +4,7 @@ # Sdc.cc: allInputs, allOutputs, isConstrained (pin, instance, net), # findClocksMatching, sortedClocks, findClock, # isClockSrc, isClock, isIdealClock, -# clkThruTristateEnabled, setClkThruTristateEnabled, -# removeConstraints +# clkThruTristateEnabled, setClkThruTristateEnabled # Sdc.i: all_inputs_cmd, all_outputs_cmd, filter_ports, filter_insts, # filter_pins, filter_clocks, filter_lib_cells, filter_lib_pins, # filter_liberty_libraries, filter_nets, filter_timing_arcs, @@ -179,14 +178,6 @@ diff_files sdc_filter_query1.sdcok $sdc1 unset_case_analysis [get_ports in1] unset_case_analysis [get_ports in2] -############################################################ -# Re-apply constraints for final write -############################################################ -create_clock -name clk1 -period 10 [get_ports clk1] -create_clock -name clk2 -period 20 [get_ports clk2] -set_input_delay -clock clk1 2.0 [get_ports in1] -set_output_delay -clock clk1 3.0 [get_ports out1] - set sdc2 [make_result_file sdc_filter_query2.sdc] write_sdc -no_timestamp $sdc2 diff_files sdc_filter_query2.sdcok $sdc2