diff --git a/doc/ChangeLog.txt b/doc/ChangeLog.txt index ee123999..13bdcc38 100644 --- a/doc/ChangeLog.txt +++ b/doc/ChangeLog.txt @@ -3,7 +3,7 @@ OpenSTA Timing Analyzer Release Notes This file summarizes user visible changes for each release. -2025/02/24 +2026/02/24 ---------- The define_scene -library argument now takes a the library name or a diff --git a/doc/OpenSTA.fodt b/doc/OpenSTA.fodt index 344e45a6..6195f2af 100644 --- a/doc/OpenSTA.fodt +++ b/doc/OpenSTA.fodt @@ -1,11 +1,11 @@ - Parallax STA documentationJames Cherry5142025-03-17T12:59:52.4638705382010-07-31T21:07:002026-02-25T07:28:47.891834000P123DT1H12M13SLibreOffice/25.8.1.1$MacOSX_AARCH64 LibreOffice_project/54047653041915e595ad4e45cccea684809c77b5PDF files: James CherryJames Cherry12.00000falsefalsefalsefalse + Parallax STA documentationJames Cherry5172025-03-17T12:59:52.4638705382010-07-31T21:07:002026-03-07T09:24:29.415873000P123DT1H20M36SLibreOffice/25.8.1.1$MacOSX_AARCH64 LibreOffice_project/54047653041915e595ad4e45cccea684809c77b5PDF files: James CherryJames Cherry12.00000falsefalsefalsefalse - 348148 - 534 + 109 + 2667 19290 17736 true @@ -13,12 +13,12 @@ view2 - 8324 - 356965 - 534 - 348148 - 19823 - 365882 + 3041 + 4163 + 2667 + 109 + 21955 + 17844 0 1 false @@ -89,7 +89,7 @@ false true false - 26480554 + 26653592 0 false @@ -198,7 +198,7 @@ - + @@ -5282,6 +5282,7 @@ + @@ -6352,7 +6353,7 @@ - + @@ -6479,7 +6480,7 @@ Example Command Scripts1 Timing Analysis using SDF2 Timing Analysis with Multiple Process Corners2 - Timing Analysis with Multiple Modes3 + Timing Analysis with Multiple Corners and Modes3 Power Analysis3 TCL Interpreter5 Debugging Timing6 @@ -6490,31 +6491,31 @@ Variables85 - Command Line Arguments + Command Line Arguments The command line arguments for sta are shown below. sta -help show help and exit -version show version and exit -no_init do not read ~/.sta -no_splash do not print the splash message -threads count|max use count threads -exit exit after reading cmd_file cmd_file source cmd_file When OpenSTA starts up, commands are first read from the user initialization file ~/.sta if it exists. If a TCL command file cmd_file is specified on the command line, commands are read from the file and executed before entering an interactive TCL command interpreter. If -exit is specified the application exits after reading cmd_file. Use the TCL exit command to exit the application. The –threads option specifies how many parallel threads to use. Use –threads max to use one thread per processor. - Example Command Scripts + Example Command Scripts To read a design into OpenSTA use the read_liberty command to read Liberty library files. Next, read hierarchical structural Verilog files with the read_verilog command. The link_design command links the Verilog to the Liberty timing cells. Any number of Liberty and Verilog files can be read before linking the design. Delays used for timing analysis are calculated using the Liberty timing models. If no parasitics are read only the pin capacitances of the timing models are used in delay calculation. Use the read_spef command to read parasitics from an extractor, or read_sdf to use delays calculated by an external delay calculator. Timing constraints can be entered as TCL commands or read using the read_sdc command. The units used by OpenSTA for all command arguments and reports are taken from the first Liberty file that is read. Use the set_cmd_units command to override the default units. Use the report_units command to see the ccmmand units. - Timing Analysis using SDF + Timing Analysis using SDF A sample command file that reads a library and a Verilog netlist and reports timing checks is shown below. read_liberty example1_slow.libread_verilog example1.vlink_design topread_sdf example1.sdfcreate_clock -name clk -period 10 {clk1 clk2 clk3}set_input_delay -clock clk 0 {in1 in2}report_checks This example can be found in examples/sdf_delays.tcl. - Timing Analysis with Multiple Process Corners + Timing Analysis with Multiple Process Corners An example command script using three process corners and +/-10% min/max derating is shown below. read_liberty nangate45_slow.lib.gzread_liberty nangate45_typ.lib.gzread_liberty nangate45_fast.lib.gzread_verilog example1.link_design topset_timing_derate -early 0.9set_timing_derate -late 1.1create_clock -name clk -period 10 {clk1 clk2 clk3}set_input_delay -clock clk 0 {in1 in2}define_scene ss -liberty nangate45_slowdefine_scene tt -liberty nangate45_typdefine_scene ff -liberty nangate45_fast# report all scenesreport_checks -path_delay min_max# report typical scenereport_checks -scene tt This example can be found in examples/multi_corner.tcl. Other examples can be found in the examples directory. - Timing Analysis with Multiple Corners and Modes + Timing Analysis with Multiple Corners and Modes OpenSTA supports multi-corner, multi-mode analysis. Each corner/mode combination is called a “scene”. The SDC constraints in each mode describe a different operating mode, such as mission mode or scan mode. Each corner has min/max Liberty libraries and SPEF parasitics. A mode named “default” is initially created for SDC commands. It is deleted when a mode is defined with set_mode or read_sdc -mode. Similartly, a named “default” is initially created that is deleted when define_scene is used to define a scene. An example command script using two process corners two modes is shown below. read_liberty asap7_small_ff.lib.gzread_liberty asap7_small_ss.lib.gzread_verilog reg1_asap7.vlink_design topread_sdc -mode mode1 mcmm2_mode1.sdcread_sdc -mode mode2 mcmm2_mode2.sdcread_spef -name reg1_ff reg1_asap7.spefread_spef -name reg1_ss reg1_asap7_ss.spefdefine_scene scene1 -mode mode1 -liberty asap7_small_ff -spef reg1_ffdefine_scene scene2 -mode mode2 -liberty asap7_small_ss -spef reg1_ssreport_checks -scenes scene1report_checks -scenes scene2report_checks -group_path_count 4 This example can be found in examples/mcmm3.tcl.In the example show above the SDC for the modes is in separate files. Alternatively, the SDC can be defined in the command file using the set_mode command between SDC command groups. set_mode mode1create_clock -name m1_clk -period 1000 {clk1 clk2 clk3}set_input_delay -clock m1_clk 100 {in1 in2}set_mode mode2create_clock -name m2_clk -period 500 {clk1 clk3}set_output_delay -clock m2_clk 100 out - Power Analysis + Power Analysis OpenSTA also supports static power analysis with the report_power command. Probabalistic switching activities are propagated from the input ports to determine switching activities for internal pins. read_liberty sky130hd_tt.libread_verilog gcd_sky130hd.vlink_design gcdread_sdc gcd_sky130hd.sdcread_spef gcd_sky130hd.spefset_power_activity -input -activity 0.1set_power_activity -input_port reset -activity 0report_power In this example the activity for all inputs is set to 0.1, and then the activity for the reset signal is set to zero because it does not switch during steady state operation. @@ -6526,14 +6527,14 @@ read_liberty sky130hd_tt.libread_verilog gcd_sky130hd.vlink_design gcdread_sdc gcd_sky130hd.sdcread_spef gcd_sky130hd.spefread_vcd -scope gcd_tb/gcd1 gcd_sky130hd.vcd.gzreport_power This example can be found in examples/power_vcd.tcl. Note that in this simple example design simulation based activities does not significantly change the results. - TCL Interpreter + TCL Interpreter Keyword arguments to commands may be abbreviated. For example, report_checks -unique is equivalent to the following command. report_checks -unique_paths_to_endpoint The help command lists matching commands and their arguments. > help report*report_annotated_check [-setup] [-hold] [-recovery] [-removal] [-nochange] [-width] [-period] [-max_skew] [-max_lines liness] [-list_annotated]group_path_count [-list_not_annotated] [-constant_arcs]report_annotated_delay [-cell] [-net] [-from_in_ports] [-to_out_ports] [-max_lines liness] [-list_annotated] [-list_not_annotated] [-constant_arcs]report_arrival pinreport_check_types [-violators] [-verbose] [-scene scene] [-format slack_only|end] [-max_delay] [-min_delay] [-recovery] [-removal] [-clock_gating_setup] [-clock_gating_hold] [-max_slew] [-min_slew] [-max_fanout] [-min_fanout] [-max_capacitance] [-min_capacitance [-min_pulse_width] [-min_period] [-max_skew] [-net net] [-digits digits [-no_line_splits] [> filename] [>> filename]report_checks [-from from_list|-rise_from from_list|-fall_from from_list] [-through through_list|-rise_through through_list|-fall_through through_list] [-to to_list|-rise_to to_list|-fall_to to_list] [-unconstrained] [-path_delay min|min_rise|min_fall|max|max_rise|max_fall|min_max] [-scene scene] [-group_path_count path_count] [-endpoint_path_count path_count] [-unique_paths_to_endpoint] [-slack_max slack_max] [-slack_min slack_min] [-sort_by_slack] [-path_group group_name] [-format full|full_clock|full_clock_expanded|short|end|summary]... - Many reporting commands support redirection of the output to a file much like a Unix shell. + Many reporting commands support redirection of the output to a file much like a Unix shell. report_checks -to out1 > path.logreport_checks -to out2 >> path.log Debugging Timing Here are some guidelines for debugging your design if static timing does not report any paths, or does not report the expected paths. @@ -6559,13 +6560,13 @@ Next, check the arrival times at the D and CP pins of the register with report_arrivals. % report_arrivals r1/D (clk1 ^) r 1.00:1.00 f 1.00:1.00% report_arrivals r1/CP (clk1 ^) r 0.00:0.00 f INF:-INF (clk1 v) r INF:-INF f 5.00:5.00 If there are no arrivals on an input port of the design, use the set_input_delay command to specify the arrival times on the port. - Commands + Commands - all_clocks + all_clocks @@ -6578,7 +6579,7 @@ - all_inputs + all_inputs [-no_clocks] @@ -6600,7 +6601,7 @@ - all_outputs + all_outputs @@ -6613,7 +6614,7 @@ - all_registers + all_registers [-clock clock_names][-cells | -data_pins | -clock_pins | -async_pins | ‑output_pins][-level_sensitive][-edge_triggered] @@ -6691,7 +6692,7 @@ - check_setup + check_setup [-verbose][-unconstrained_endpoints][-multiple_clock][-no_clock][-no_input_delay][-loops][-generated_clocks][> filename][>> filename] @@ -6760,7 +6761,7 @@ - connect_pin + connect_pin netport|pin @@ -6859,7 +6860,7 @@ - create_generated_clock + create_generated_clock [-name clock_name]-source master_pin[-master_clock master_clock][-divide_by divisor][-multiply_by multiplier][-duty_cycle duty_cycle][-invert][-edges edge_list][-edge_shift shift_list][-add]pin_list @@ -6975,7 +6976,7 @@ - create_voltage_area + create_voltage_area [-name name][-coordinate coordinates][-guard_band_x guard_x][-guard_band_y guard_y]cells @@ -6988,7 +6989,7 @@ - current_design + current_design [design] @@ -7001,7 +7002,7 @@ - current_instance + current_instance [instance] @@ -7022,7 +7023,7 @@ - define_scene + define_scene -mode mode_name -liberty liberty_files|-liberty_min liberty_min_files -liberty_max liberty_max_files-spef spef_file| -spef_min spef_min_file -spef_max spef_max_file @@ -7060,7 +7061,7 @@ - delete_clock + delete_clock [-all] clocks @@ -7081,7 +7082,7 @@ - delete_from_list + delete_from_list list objects @@ -7111,7 +7112,7 @@ - delete_generated_clock + delete_generated_clock [-all] clocks @@ -7132,7 +7133,7 @@ - delete_instance + delete_instance instance @@ -7153,7 +7154,7 @@ - delete_net + delete_net net @@ -7174,7 +7175,7 @@ - disconnect_pin + disconnect_pin netport | pin | -all @@ -7219,7 +7220,7 @@ - elapsed_run_time + elapsed_run_time @@ -7233,7 +7234,7 @@ - find_timing_paths + find_timing_paths [-from from_list |-rise_from from_list |-fall_from from_list][-through through_list |-rise_through through_list |-fall_through through_list][-to to_list |-rise_to to_list |-fall_to to_list][-unconstrained][-path_delay min|min_rise|min_fall |max|max_rise|max_fall |min_max][-group_path_count path_count][-endpoint_path_count endpoint_path_count][-unique_paths_to_endpoint][-scene scene][-slack_max max_slack][-slack_min min_slack][-sort_by_slack][-path_group groups] @@ -7448,7 +7449,7 @@ - get_cells + get_cells [-hierarchical][-hsc separator][-filter expr][-regexp][-nocase][-quiet][-of_objects objects][patterns] @@ -7525,7 +7526,7 @@ - get_clocks + get_clocks [-regexp][-nocase][-filter expr][-quiet]patterns @@ -7579,7 +7580,7 @@ - get_fanin + get_fanin -to sink_list[-flat][-only_cells][-startpoints_only][-levels level_count][-pin_levels pin_count][-trace_arcs timing|enabled|all] @@ -7665,7 +7666,7 @@ - get_fanout + get_fanout -from source_list[-flat][-only_cells][-endpoints_only][-levels level_count][-pin_levels pin_count][-trace_arcs timing|enabled|all] @@ -7750,7 +7751,7 @@ - get_full_name + get_full_name object @@ -7841,7 +7842,7 @@ - get_lib_pins + get_lib_pins [-of_objects objects][-hsc separator][-filter expr][-regexp][-nocase][-quiet]patterns @@ -7911,7 +7912,7 @@ - get_libs + get_libs [-filter expr][-regexp][-nocase][-quiet]patterns @@ -7965,7 +7966,7 @@ - get_nets + get_nets [-hierarchical][-hsc separator][-filter expr][-regexp][-nocase][-quiet][-of_objects objects][patterns] @@ -8042,7 +8043,7 @@ - get_name + get_name object @@ -8064,7 +8065,7 @@ - get_pins + get_pins [-hierarchical][-hsc separator][-filter expr][-regexp][-nocase][-quiet][-of_objects objects][patterns] @@ -8135,7 +8136,7 @@ - get_ports + get_ports [-filter expr][-regexp][-nocase][-quiet][-of_objects objects][patterns] @@ -8197,7 +8198,7 @@ - get_property + get_property [-object_type object_type]objectproperty @@ -8258,7 +8259,7 @@ - get_scenes + get_scenes [-mode mode_name]scene_name @@ -8287,7 +8288,7 @@ - get_timing_edges + get_timing_edges [-from from_pins][-to to_pins][-of_objects objects][-filter expr][patterns] @@ -8333,7 +8334,7 @@ - group_path + group_path -name group_name[-weight weight][-critical_range range][-from from_list |-rise_from from_list |-fall_from from_list][-through through_list][-rise_through through_list][-fall_through through_list][-to to_list |-rise_to to_list |-fall_to to_list][-default] @@ -8450,7 +8451,7 @@ - include + include [-echo|-e][-verbose|-v]filename[> log_filename][>> log_filename] @@ -8504,7 +8505,7 @@ - link_design + link_design [-no_black_boxes][cell_name] @@ -8535,7 +8536,7 @@ - make_instance + make_instance inst_pathlib_cell @@ -8565,7 +8566,7 @@ - make_net + make_net net_name_list @@ -8586,7 +8587,7 @@ - read_liberty + read_liberty [-corner corner][-min][-max][-infer_latches]filename @@ -8635,7 +8636,7 @@ - read_saif + read_saif [-scope scope]filename @@ -8665,7 +8666,7 @@ - read_sdc + read_sdc [-mode mode_name][-echo]filename @@ -8705,7 +8706,7 @@ - read_sdf + read_sdf [-scene scene][-unescaped_dividers]filename @@ -8746,7 +8747,7 @@ - read_spef + read_spef [-name name][-keep_capacitive_coupling][-coupling_reduction_factor factor][-reduce][-path path]filename @@ -8793,7 +8794,7 @@ - The read_spef command reads a file of net parasitics in SPEF format. Use the ‑report_parasitic_annotation command to check for nets that are not annotated. + The read_spef command reads a file of net parasitics in SPEF format. Use the ‑report_parasitic_annotation command to check for nets that are not annotated. Files compressed with gzip are automatically uncompressed. Separate min/max parasitics can be annotated for each scene mode/corner. read_spef -name min spef1read_spef -name max spef2define_scene -mode mode1 -spef_min min -spef_max max @@ -8807,7 +8808,7 @@ - read_vcd + read_vcd [-scope scope][-mode mode_name]filename @@ -8844,7 +8845,7 @@ - read_verilog + read_verilog filename @@ -8859,7 +8860,7 @@ - The read_verilog command reads a gate level verilog netlist. After all verilog netlist and Liberty libraries are read the design must be linked with the link_design command. + The read_verilog command reads a gate level verilog netlist. After all verilog netlist and Liberty libraries are read the design must be linked with the link_design command. Verilog 2001 module port declaratations are supported. An example is shown below. module top (input in1, in2, clk1, clk2, clk3, output out); Files compressed with gzip are automatically uncompressed. @@ -8868,7 +8869,7 @@ - replace_cell + replace_cell instance_listreplacement_cell @@ -8898,7 +8899,7 @@ - replace_activity_annotation + replace_activity_annotation [-report_unannotated][-report_annotated] @@ -8927,7 +8928,7 @@ - report_annotated_check + report_annotated_check [-setup][-hold][-recovery][-removal][-nochange][-width][-period][-max_skew][-max_line lines][-report_annotated][-report_unannotated][-constant_arcs] @@ -9037,7 +9038,7 @@ - report_annotated_delay + report_annotated_delay [-cell][-net][-from_in_ports][-to_out_ports][-max_lines lines][-report_annotated][-report_unannotated][-constant_arcs] @@ -9115,7 +9116,7 @@ - report_checks + report_checks [-from from_list |-rise_from from_list |-fall_from from_list][-through through_list |-rise_through through_list |-fall_through through_list][-to to_list |-rise_to to_list |-fall_to to_list][-unconstrained][-path_delay min|min_rise|min_fall |max|max_rise|max_fall |min_max][-group_path_count path_count][-endpoint_path_count endpoint_path_count][-unique_paths_to_endpoint][-unique_edges_to_endpoint][-scenes scenes][-slack_max max_slack][-slack_min min_slack][-sort_by_slack][-path_group groups][-format end|full|short|summary |full_clock|full_clock_expanded |json][-fields fields][-digits digits][-no_line_split][> filename][>> filename] @@ -9420,7 +9421,7 @@ - report_check_types + report_check_types [-scenes scenes][-violators][-verbose][-format slack_only|end][-max_delay][-min_delay][-recovery][-removal][-clock_gating_setup][-clock_gating_hold][-max_slew][-min_slew][-min_pulse_width][-min_period][-digits digits][-no_split_lines][> filename][>> filename] @@ -9578,7 +9579,7 @@ - report_clock_latency + report_clock_latency [-clocks clocks][-scenes scenes][-include_internal_latency][-digits digits] @@ -9623,7 +9624,7 @@ - report_clock_min_period + report_clock_min_period [-clocks clocks][-scenes scenes][-include_port_paths] @@ -9653,7 +9654,7 @@ - report_clock_properties + report_clock_properties [clock_names] @@ -9674,7 +9675,7 @@ - report_clock_skew + report_clock_skew [-setup|-hold][-clocks clocks][-scenes scenes][-include_internal_latency][-digits digits] @@ -9735,7 +9736,7 @@ - report_dcalc + report_dcalc [-from from_pin][-to to_pin][-scene scene][-min][-max][-digits digits][> filename][>> filename] @@ -9797,7 +9798,7 @@ - report_disabled_edges + report_disabled_edges @@ -9811,7 +9812,7 @@ - report_edges + report_edges [-from from_pin][-to to_pin] @@ -9840,7 +9841,7 @@ - report_instance + report_instance instance_path[> filename][>> filename] @@ -9861,7 +9862,7 @@ - report_lib_cell + report_lib_cell cell_name[> filename][>> filename] @@ -9883,7 +9884,7 @@ - report_net + report_net [-digits digits]net_path[> filename][>> filename] @@ -9912,7 +9913,7 @@ - report_parasitic_annotation + report_parasitic_annotation [-report_unannotated][> filename][>> filename] @@ -9933,7 +9934,7 @@ - report_power + report_power [-instances instances][-highest_power_instances count][-digits digits][> filename][>> filename] @@ -9972,7 +9973,7 @@ - report_slews + report_slews [-scenes scenes]pin @@ -10001,7 +10002,7 @@ - report_tns + report_tns [-min][-max][-digits digits] @@ -10038,7 +10039,7 @@ - report_units + report_units @@ -10052,7 +10053,7 @@ - report_wns + report_wns [-min][-max][-digits digits] @@ -10089,7 +10090,7 @@ - report_worst_slack + report_worst_slack [-min][-max][-digits digits] @@ -10127,7 +10128,7 @@ - set_assigned_check + set_assigned_check -setup|-hold|-recovery|-removal[-rise][-fall][-scene scene][-min][-max][-from from_pins][-to to_pins][-clock rise|fall][-cond sdf_cond][-worst]margin @@ -10245,7 +10246,7 @@ - set_assigned_delay + set_assigned_delay -cell|-net[-rise][-fall][-scene scene][-min][-max][-from from_pins][-to to_pins]delay @@ -10338,7 +10339,7 @@ - set_assigned_transition + set_assigned_transition [-rise][-fall][-scene scene][-min][-max]slewpin_list @@ -10408,7 +10409,7 @@ - set_case_analysis + set_case_analysis 0|1|zero|one|rise|rising|fall|fallingport_or_pin_list @@ -10430,7 +10431,7 @@ - set_clock_gating_check + set_clock_gating_check [-setup setup_time][-hold hold_time][-rise][-fall][-high][-low][objects] @@ -10504,7 +10505,7 @@ - set_clock_groups + set_clock_groups [-name name][-logically_exclusive][-physically_exclusive][-asynchronous][-allow_paths]-group clocks @@ -10565,7 +10566,7 @@ - set_clock_latency + set_clock_latency [-source][-clock clock][-rise][-fall][-min][-max]delayobjects @@ -10642,7 +10643,7 @@ - set_clock_transition + set_clock_transition [-rise][-fall][-min][-max]transitionclocks @@ -10704,7 +10705,7 @@ - set_clock_uncertainty + set_clock_uncertainty [-from|-rise_from|-fall_from from_clock][-to|-rise_to|-fall_to to_clock][-rise][-fall][-setup][-hold]uncertainty[objects] @@ -10786,7 +10787,7 @@ - set_cmd_units + set_cmd_units [-capacitance cap_unit][-resistance res_unit][-time time_unit][-voltage voltage_unit][-current current_unit][-power power_unit][-distance distance_unit] @@ -10859,7 +10860,7 @@ - set_data_check + set_data_check [-from|-rise_from|-fall_from from_pin][-to|-rise_to|-fall_to to_pin][-setup][-hold][-clock clock]margin @@ -10920,7 +10921,7 @@ - set_disable_inferred_clock_gating + set_disable_inferred_clock_gating objects @@ -10941,7 +10942,7 @@ - set_disable_timing + set_disable_timing [-from from_port][-to to_port]objects @@ -10986,7 +10987,7 @@ - set_drive + set_drive [-rise][-fall][-max][-min]resistanceports @@ -11047,7 +11048,7 @@ - set_driving_cell + set_driving_cell [-lib_cell cell_name][-library library][-rise][-fall][-min][-max][-pin pin][-from_pin from_pin][-input_transition_rise trans_rise][-input_transition_fall trans_fall]ports @@ -11149,7 +11150,7 @@ - set_false_path + set_false_path [-setup][-hold][-rise][-fall][-from from_list][-rise_from from_list][-fall_from from_list][-through through_list][-rise_through through_list][-fall_through through_list][-to to_list][-rise_to to_list][-fall_to to_list][-reset_path] @@ -11230,7 +11231,7 @@ - set_fanout_load + set_fanout_load fanoutport_list @@ -11243,7 +11244,7 @@ - set_hierarchy_separator + set_hierarchy_separator separator @@ -11264,7 +11265,7 @@ - set_ideal_latency + set_ideal_latency [-rise] [-fall] [-min] [-max] delay objects @@ -11277,7 +11278,7 @@ - set_ideal_network + set_ideal_network [-no_propagation] objects @@ -11290,7 +11291,7 @@ - set_ideal_transition + set_ideal_transition [-rise] [-fall] [-min] [-max] transition_time objects @@ -11303,7 +11304,7 @@ - set_input_delay + set_input_delay [-rise][-fall][-max][-min][-clock clock][-clock_fall][-reference_pin ref_pin][-source_latency_included][-network_latency_included][-add_delay]delayport_pin_list @@ -11420,7 +11421,7 @@ - set_input_transition + set_input_transition [-rise][-fall][-max][-min]transitionport_list @@ -11481,7 +11482,7 @@ - set_level_shifter_strategy + set_level_shifter_strategy [-rule rule_type] @@ -11494,7 +11495,7 @@ - set_level_shifter_threshold + set_level_shifter_threshold [-voltage voltage] @@ -11507,7 +11508,7 @@ - set_load + set_load [-rise][-fall][-max][-min][-subtract_pin_load][-pin_load][-wire_load]capacitanceobjects @@ -11596,7 +11597,7 @@ - set_logic_dc + set_logic_dc port_list @@ -11617,7 +11618,7 @@ - set_logic_one + set_logic_one port_list @@ -11639,7 +11640,7 @@ - set_logic_zero + set_logic_zero port_list @@ -11660,7 +11661,7 @@ - set_max_area + set_max_area area @@ -11681,7 +11682,7 @@ - set_max_capacitance + set_max_capacitance capacitanceobjects @@ -11710,7 +11711,7 @@ - set_max_delay + set_max_delay [-rise][-fall][-from from_list][-rise_from from_list][-fall_from from_list][-through through_list][-rise_through through_list][-fall_through through_list][-to to_list][-rise_to to_list][-fall_to to_list][-ignore_clock_latency][-probe][-reset_path]delay @@ -11797,7 +11798,7 @@ - set_max_dynamic_power + set_max_dynamic_power power [unit] @@ -11810,7 +11811,7 @@ - set_max_fanout + set_max_fanout fanoutobjects @@ -11839,7 +11840,7 @@ - set_max_leakage_power + set_max_leakage_power power [unit] @@ -11852,7 +11853,7 @@ - set_max_time_borrow + set_max_time_borrow delayobjects @@ -11882,7 +11883,7 @@ - set_max_transition + set_max_transition [-data_path][-clock_path][-rise][-fall]transitionobjects @@ -11945,7 +11946,7 @@ - set_min_capacitance + set_min_capacitance capacitanceobjects @@ -11975,7 +11976,7 @@ - set_min_delay + set_min_delay [-rise][-fall][-from from_list][-rise_from from_list][-fall_from from_list][-through through_list][-rise_through through_list][-fall_through through_list][-to to_list][-rise_to to_list][-fall_to to_list][-ignore_clock_latency][-probe][-reset_path]delay @@ -12062,7 +12063,7 @@ - set_min_pulse_width + set_min_pulse_width [-high][-low]min_widthobjects @@ -12107,7 +12108,7 @@ - set_mode + set_mode mode_name @@ -12120,7 +12121,7 @@ - set_multicycle_path + set_multicycle_path [-setup][-hold][-rise][-fall][-start][-end][-from from_list][-rise_from from_list][-fall_from from_list][-through through_list][-rise_through through_list][-fall_through through_list][-to to_list][-rise_to to_list][-fall_to to_list][-reset_path]path_multiplier @@ -12222,7 +12223,7 @@ - set_operating_conditions + set_operating_conditions [-analysis_type single|bc_wc|on_chip_variation][-library lib][condition][-min min_condition][-max max_condition][-min_library min_lib][-max_library max_lib] @@ -12308,7 +12309,7 @@ - set_output_delay + set_output_delay [-rise][-fall][-max][-min][-clock clock][-clock_fall][-reference_pin ref_pin][-source_latency_included][-network_latency_included][-add_delay]delayport_pin_list @@ -12402,7 +12403,7 @@ - set_port_fanout_number + set_port_fanout_number [-min][-max]fanoutports @@ -12447,7 +12448,7 @@ - set_power_activity + set_power_activity [-global][-input][-input_ports ports][-pins pins][-activity activity | -density density][-duty duty][-clock clock] @@ -12527,7 +12528,7 @@ - set_propagated_clock + set_propagated_clock objects @@ -12548,7 +12549,7 @@ - set_pvt + set_pvt [-min][-max][-process process][-voltage voltage] @@ -12611,7 +12612,7 @@ - set_sense + set_sense [-type clock|data][-positive][-negative][-pulse pulse_type][-stop_propagation][-clock clocks]pins @@ -12689,7 +12690,7 @@ - set_timing_derate + set_timing_derate [-rise][-fall][-early][-late][-clock][-data][-net_delay][-cell_delay][-cell_check]derate[objects] @@ -12791,7 +12792,7 @@ - set_resistance + set_resistance [-max][-min]resistancenets @@ -12837,7 +12838,7 @@ - set_units + set_units [-capacitance cap_unit][-resistance res_unit][-time time_unit][-voltage voltage_unit][-current current_unit][-power power_unit][-distance distance_unit] @@ -12902,7 +12903,7 @@ - set_wire_load_min_block_size + set_wire_load_min_block_size size @@ -12915,7 +12916,7 @@ - set_wire_load_mode + set_wire_load_mode top|enclosed|segmented @@ -12952,7 +12953,7 @@ - set_wire_load_model + set_wire_load_model -name model_name[-library library][-max][-min][objects] @@ -13005,7 +13006,7 @@ - set_wire_load_selection_group + set_wire_load_selection_group [-library library][-max][-min]group_name[objects] @@ -13059,7 +13060,7 @@ - suppress_msg + suppress_msg msg_ids @@ -13080,7 +13081,7 @@ - unset_case_analysis + unset_case_analysis port_or_pin_list @@ -13101,7 +13102,7 @@ - unset_clock_latency + unset_clock_latency [-source]objects @@ -13130,7 +13131,7 @@ - unset_clock_transition + unset_clock_transition clocks @@ -13152,7 +13153,7 @@ - unset_clock_uncertainty + unset_clock_uncertainty [-from|-rise_from|-fall_from from_clock][-to|-rise_to|-fall_to to_clock][-rise][-fall][-setup][-hold][objects] @@ -13229,7 +13230,7 @@ - unset_data_check + unset_data_check [-from|-rise_from|-fall_from from_object][-to|-rise_to|-fall_to to_object][-setup][-hold][-clock clock] @@ -13282,7 +13283,7 @@ - unset_disable_inferred_clock_gating + unset_disable_inferred_clock_gating objects @@ -13303,7 +13304,7 @@ - unset_disable_timing + unset_disable_timing [-from from_port][-to to_port]objects @@ -13340,7 +13341,7 @@ - unset_input_delay + unset_input_delay [-rise][-fall][-max][-min][-clock clock][-clock_fall]port_pin_list @@ -13410,7 +13411,7 @@ - unset_output_delay + unset_output_delay [-rise][-fall][-max][-min][-clock clock][-clock_fall]port_pin_list @@ -13479,7 +13480,7 @@ - unset_path_exceptions + unset_path_exceptions [-setup][-hold][-rise][-fall][-from|-rise_from|-fall_from from][-through|-rise_through|-fall_through through][-to|-rise_to|-fall_to to] @@ -13550,7 +13551,7 @@ - unset_power_activity + unset_power_activity [-global][-input][-input_ports ports][-pins pins] @@ -13603,7 +13604,7 @@ - unset_propagated_clock + unset_propagated_clock objects @@ -13624,7 +13625,7 @@ - unset_timing_derate + unset_timing_derate @@ -13638,7 +13639,7 @@ - unsuppress_msg + unsuppress_msg msg_ids @@ -13659,7 +13660,7 @@ - user_run_time + user_run_time @@ -13672,7 +13673,7 @@ - with_output_to_variable + with_output_to_variable var { commands } @@ -13701,7 +13702,7 @@ - write_path_spice + write_path_spice -path_args path_args-spice_directory spice_directory-lib_subckt_file lib_subckts_file-model_file model_file-power power-ground ground[-simulator hspice|ngspice|xyce] @@ -13775,7 +13776,7 @@ - write_sdc + write_sdc [-digits digits][-gzip][-no_timestamp]filename @@ -13820,7 +13821,7 @@ - write_sdf + write_sdf [-scene scene][-divider /|.][-include_typ][-digits digits][-gzip][-no_timestamp][-no_version]filename @@ -13898,7 +13899,7 @@ - write_timing_model + write_timing_model [-library_name lib_name][-cell_name cell_name] @@ -13951,7 +13952,7 @@ - write_verilog + write_verilog [-include_pwr_gnd][-remove_cells lib_cells]filename @@ -13983,7 +13984,7 @@ The write_verilog command writes a Verilog netlist to filename. Use -sort to sort the instances so the results are reproducible across operating systems. Use -remove_cells to remove instances of lib_cells from the netlist. - Filter Expressions + Filter Expressions The get_cells, get_pins, get_ports and get_timing_edges functions support filtering the returned objects by property values. Supported filter expressions are shown below. @@ -14046,13 +14047,13 @@ Where property is a property supported by the get_property command. Note that if there are spaces in the expression it must be enclosed in quotes so that it is a single argument. - Variables + Variables - hierarchy_separator + hierarchy_separator Any character. @@ -14065,7 +14066,7 @@ - sta_continue_on_error + sta_continue_on_error 0|1 @@ -14078,7 +14079,7 @@ - sta_crpr_mode + sta_crpr_mode same_pin|same_transition @@ -14091,7 +14092,7 @@ - sta_cond_default_arcs_enabled + sta_cond_default_arcs_enabled 0|1 @@ -14104,7 +14105,7 @@ - sta_crpr_enabled + sta_crpr_enabled 0|1 @@ -14117,7 +14118,7 @@ - sta_dynamic_loop_breaking + sta_dynamic_loop_breaking 0|1 @@ -14130,7 +14131,7 @@ - sta_gated_clock_checks_enabled + sta_gated_clock_checks_enabled 0|1 @@ -14143,7 +14144,7 @@ - sta_input_port_default_clock + sta_input_port_default_clock 0|1 @@ -14156,7 +14157,7 @@ - sta_internal_bidirect_instance_paths_enabled + sta_internal_bidirect_instance_paths_enabled 0|1 @@ -14169,7 +14170,7 @@ - sta_pocv_enabled + sta_pocv_enabled 0|1 @@ -14182,7 +14183,7 @@ - sta_propagate_all_clocks + sta_propagate_all_clocks 0|1 @@ -14197,7 +14198,7 @@ - sta_propagate_gated_clock_enable + sta_propagate_gated_clock_enable 0|1 @@ -14210,7 +14211,7 @@ - sta_recovery_removal_checks_enabled + sta_recovery_removal_checks_enabled 0|1 @@ -14223,7 +14224,7 @@ - sta_report_default_digits + sta_report_default_digits integer @@ -14237,7 +14238,7 @@ - sta_preset_clear_arcs_enabled + sta_preset_clear_arcs_enabled 0|1 @@ -14287,7 +14288,7 @@ define_scene13 delete_clock13 delete_from_list13 - delete_generated_clock13 + delete_generated_clock14 delete_instance14 delete_net14 disconnect_pin14 @@ -14421,7 +14422,7 @@ suppress_msg76 TCL Interpreter5 Timing Analysis using SDF2 - Timing Analysis with Multiple Modes3 + Timing Analysis with Multiple Corners and Modes3 Timing Analysis with Multiple Process Corners2 unset_case_analysis76 unset_clock_latency76 @@ -14449,7 +14450,7 @@ - Version 2.6.0, Sep 23, 2024Copyright (c) 2024, Parallax Software, Inc. + Version 3.0.0, Mar 7, 2026Copyright (c) 2026, Parallax Software, Inc. This program is free software: you can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free Software Foundation, either version 3 of the License, or (at your option) any later version. This program is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details. You should have received a copy of the GNU General Public License along with this program. If not, see <https://www.gnu.org/licenses/>. diff --git a/doc/OpenSTA.pdf b/doc/OpenSTA.pdf index c084d808..b450630c 100644 Binary files a/doc/OpenSTA.pdf and b/doc/OpenSTA.pdf differ