From a5722ae63c80d21e08a420059493319c86ce5a14 Mon Sep 17 00:00:00 2001
From: James Cherry <cherry@parallaxsw.com>
Date: Wed, 15 Jul 2020 11:56:11 -0700
Subject: [PATCH] write_verilog remove_cells use std::vector

---
 include/sta/VerilogWriter.hh |  4 +++-
 tcl/StaTcl.i                 | 38 ++++++++++++++++++++++++++++++------
 verilog/Verilog.i            |  2 +-
 verilog/VerilogWriter.cc     | 12 +++++++-----
 4 files changed, 43 insertions(+), 13 deletions(-)

diff --git a/include/sta/VerilogWriter.hh b/include/sta/VerilogWriter.hh
index 0684655e..7daa2f83 100644
--- a/include/sta/VerilogWriter.hh
+++ b/include/sta/VerilogWriter.hh
@@ -16,16 +16,18 @@
 
 #pragma once
 
+#include <vector>
 #include "LibertyClass.hh"
 
 namespace sta {
 
+using std::vector;
 class Network;
 
 void
 writeVerilog(const char *filename,
 	     bool sort,
-	     LibertyCellSeq *remove_cells,
+	     vector<LibertyCell*> *remove_cells,
 	     Network *network);
 
 } // namespace
diff --git a/tcl/StaTcl.i b/tcl/StaTcl.i
index e2d61edc..45318431 100644
--- a/tcl/StaTcl.i
+++ b/tcl/StaTcl.i
@@ -106,6 +106,8 @@ typedef MinMaxAll MinMaxAllNull;
 typedef ClockSet TmpClockSet;
 typedef StringSeq TmpStringSeq;
 
+using std::vector;
+
 class CmdErrorNetworkNotLinked : public Exception
 {
 public:
@@ -188,6 +190,30 @@ tclListSeq(Tcl_Obj *const source,
     return nullptr;
 }
 
+template <class TYPE>
+vector<TYPE> *
+tclListStdSeq(Tcl_Obj *const source,
+	      swig_type_info *swig_type,
+	      Tcl_Interp *interp)
+{
+  int argc;
+  Tcl_Obj **argv;
+
+  if (Tcl_ListObjGetElements(interp, source, &argc, &argv) == TCL_OK
+      && argc > 0) {
+    vector<TYPE> *seq = new vector<TYPE>;
+    for (int i = 0; i < argc; i++) {
+      void *obj;
+      // Ignore returned TCL_ERROR because can't get swig_type_info.
+      SWIG_ConvertPtr(argv[i], &obj, swig_type, false);
+      seq->push_back(reinterpret_cast<TYPE>(obj));
+    }
+    return seq;
+  }
+  else
+    return nullptr;
+}
+
 LibertyLibrarySeq *
 tclListSeqLibertyLibrary(Tcl_Obj *const source,
 			 Tcl_Interp *interp)
@@ -195,11 +221,11 @@ tclListSeqLibertyLibrary(Tcl_Obj *const source,
   return tclListSeq<LibertyLibrary*>(source, SWIGTYPE_p_LibertyLibrary, interp);
 }
 
-LibertyCellSeq *
+vector<LibertyCell*> *
 tclListSeqLibertyCell(Tcl_Obj *const source,
 		      Tcl_Interp *interp)
 {
-  return tclListSeq<LibertyCell*>(source, SWIGTYPE_p_LibertyCell, interp);
+  return tclListStdSeq<LibertyCell*>(source, SWIGTYPE_p_LibertyCell, interp);
 }
 
 template <class TYPE>
@@ -429,10 +455,6 @@ using namespace sta;
   Tcl_SetObjResult(interp, list);
 }
 
-%typemap(in) LibertyCellSeq* {
-  $1 = tclListSeqLibertyCell($input, interp);
-}
-
 %typemap(out) TmpCellSeq* {
   Tcl_Obj *list = Tcl_NewListObj(0, nullptr);
   CellSeq *cells = $1;
@@ -446,6 +468,10 @@ using namespace sta;
   delete cells;
 }
 
+%typemap(in) vector<LibertyCell*> * {
+  $1 = tclListSeqLibertyCell($input, interp);
+}
+
 %typemap(out) LibertyCellSeq* {
   Tcl_Obj *list = Tcl_NewListObj(0, nullptr);
   LibertyCellSeq *cells = $1;
diff --git a/verilog/Verilog.i b/verilog/Verilog.i
index accbb207..a0a2b368 100644
--- a/verilog/Verilog.i
+++ b/verilog/Verilog.i
@@ -53,7 +53,7 @@ delete_verilog_reader()
 void
 write_verilog_cmd(const char *filename,
 		  bool sort,
-		  LibertyCellSeq *remove_cells)
+		  vector<LibertyCell*> *remove_cells)
 {
   // This does NOT want the SDC (cmd) network because it wants
   // to see the sta internal names.
diff --git a/verilog/VerilogWriter.cc b/verilog/VerilogWriter.cc
index eecabb7a..36ed2093 100644
--- a/verilog/VerilogWriter.cc
+++ b/verilog/VerilogWriter.cc
@@ -32,7 +32,7 @@ class VerilogWriter
 public:
   VerilogWriter(const char *filename,
 		bool sort,
-		LibertyCellSeq *remove_cells,
+		vector<LibertyCell*> *remove_cells,
 		FILE *stream,
 		Network *network);
   void writeModule(Instance *inst);
@@ -67,7 +67,7 @@ protected:
 void
 writeVerilog(const char *filename,
 	     bool sort,
-	     LibertyCellSeq *remove_cells,
+	     vector<LibertyCell*> *remove_cells,
 	     Network *network)
 {
   if (network->topInstance()) {
@@ -84,7 +84,7 @@ writeVerilog(const char *filename,
 
 VerilogWriter::VerilogWriter(const char *filename,
 			     bool sort,
-			     LibertyCellSeq *remove_cells,
+			     vector<LibertyCell*> *remove_cells,
 			     FILE *stream,
 			     Network *network) :
   filename_(filename),
@@ -93,8 +93,10 @@ VerilogWriter::VerilogWriter(const char *filename,
   network_(network),
   unconnected_net_index_(1)
 {
-  for(LibertyCell *lib_cell : *remove_cells)
-    remove_cells_.insert(network->cell(lib_cell));
+  if (remove_cells) {
+    for(LibertyCell *lib_cell : *remove_cells)
+      remove_cells_.insert(network->cell(lib_cell));
+  }
 }
 
 void