diff --git a/doc/OpenSTA.odt b/doc/OpenSTA.odt
index 554271b9..b8bf1607 100644
Binary files a/doc/OpenSTA.odt and b/doc/OpenSTA.odt differ
diff --git a/doc/OpenSTA.pdf b/doc/OpenSTA.pdf
index 03a0a264..e7303d19 100644
Binary files a/doc/OpenSTA.pdf and b/doc/OpenSTA.pdf differ
diff --git a/include/sta/Clock.hh b/include/sta/Clock.hh
index 702ec981..1d367150 100644
--- a/include/sta/Clock.hh
+++ b/include/sta/Clock.hh
@@ -105,8 +105,6 @@ public:
   Clock *masterClk() const { return master_clk_; }
   bool masterClkInfered() const { return master_clk_infered_; }
   void setInferedMasterClk(Clock *master_clk);
-  Pin *pllOut() const { return pll_out_; }
-  Pin *pllFdbk() const { return pll_fdbk_; }
   int divideBy() const { return divide_by_; }
   int multiplyBy() const { return multiply_by_; }
   float dutyCycle() const { return duty_cycle_; }
@@ -138,8 +136,6 @@ protected:
 			bool add_to_pins,
 			Pin *src_pin,
 			Clock *master_clk,
-			Pin *pll_out,
-			Pin *pll_fdbk,
 			int divide_by,
 			int multiply_by,
 			float duty_cycle,
@@ -165,8 +161,6 @@ protected:
   bool add_to_pins_;
   // Hierarchical pins in pins_ become driver pins through the pin.
   PinSet leaf_pins_;
-  Pin *pll_out_;
-  Pin *pll_fdbk_;
   float period_;
   FloatSeq *waveform_;
   bool waveform_valid_;
diff --git a/include/sta/Sdc.hh b/include/sta/Sdc.hh
index 3c533c81..4bdf0240 100644
--- a/include/sta/Sdc.hh
+++ b/include/sta/Sdc.hh
@@ -348,8 +348,6 @@ public:
 				    bool add_to_pins,
 				    Pin *src_pin,
 				    Clock *master_clk,
-				    Pin *pll_out,
-				    Pin *pll_fdbk,
 				    int divide_by,
 				    int multiply_by,
 				    float duty_cycle,
diff --git a/include/sta/Sta.hh b/include/sta/Sta.hh
index 3c66a73d..41470a9f 100644
--- a/include/sta/Sta.hh
+++ b/include/sta/Sta.hh
@@ -277,8 +277,6 @@ public:
 			  bool add_to_pins,
 			  Pin *src_pin,
 			  Clock *master_clk,
-			  Pin *pll_out,
-			  Pin *pll_fdbk,
 			  int divide_by,
 			  int multiply_by,
 			  float duty_cycle,
diff --git a/messages.txt b/messages.txt
index 1480768f..41b9644c 100644
--- a/messages.txt
+++ b/messages.txt
@@ -7,13 +7,12 @@
 0007 LibertyExpr.cc:78         %s references unknown port %s.
 0008 ConcreteNetwork.cc:1857   cell type %s can not be linked.
 0009 CycleAccting.cc:87        No common period was found between clocks %s and %s.
-0010 Genclks.cc:287            no master clock found for generated clock %s.
-0011 Genclks.cc:329            generated clock %s is in the fanout of multiple clocks.
-0013 Genclks.cc:987            generated clock %s source pin %s missing paths from master clock %s.
+0010 Genclks.cc:274            no master clock found for generated clock %s.
+0013 Genclks.cc:938            generated clock %s source pin %s missing paths from master clock %s.
 0015 Sim.cc:871                propagated logic value %c differs from constraint value of %c on pin %s.
 0016 LibertyReader.cc:996      default_max_fanout is 0.0.
-0017 Sta.cc:2094               '%s' is not a valid endpoint.
-0018 Sta.cc:2018               '%s' is not a valid start point.
+0017 Sta.cc:2091               '%s' is not a valid endpoint.
+0018 Sta.cc:2015               '%s' is not a valid start point.
 0021 SpefParse.yy:805          %d is not positive.
 0022 SpefParse.yy:814          %.4f is not positive.
 0023 SpefParse.yy:820          %.4f is not positive.
@@ -166,7 +165,7 @@
 0191 VerilogReader.cc:1733     %s is not a verilog module.
 0201 StaTcl.i:128              no network has been linked.
 0202 StaTcl.i:142              network does not support edits.
-0204 StaTcl.i:4181             POCV support requires compilation with SSTA=1.
+0204 StaTcl.i:4179             POCV support requires compilation with SSTA=1.
 0206 LibertyExpr.cc:171        %s %s.
 0207 GraphDelayCalc1.cc:738    port not found in cell
 0208 Graph.cc:793              arc_delay_annotated array bounds exceeded
@@ -174,10 +173,10 @@
 0210 Graph.cc:820              arc_delay_annotated array bounds exceeded
 0211 SdcNetwork.cc:1026        inst path string lenth estimate busted
 0212 SdcNetwork.cc:1098        inst path string lenth estimate exceeded
-0213 Sdc.cc:4101               group path name and is_default are mutually exclusive.
-0214 WriteSdc.cc:1317          unknown exception type
-0215 WriteSdc.cc:1888          illegal set_logic value
-0216 WriteSdc.cc:1932          invalid set_case_analysis value
+0213 Sdc.cc:4098               group path name and is_default are mutually exclusive.
+0214 WriteSdc.cc:1307          unknown exception type
+0215 WriteSdc.cc:1878          illegal set_logic value
+0216 WriteSdc.cc:1922          invalid set_case_analysis value
 0228 Graph.cc:833              arc_delay_annotated array bounds exceeded
 0251 PathEnumed.cc:126         enumerated path required time
 0252 PathEnumed.cc:135         enumerated path required time
@@ -186,18 +185,17 @@
 0255 ReportPath.cc:289         unsupported path type
 0256 ReportPath.cc:310         unsupported path type
 0257 ReportPath.cc:349         unsupported path type
-0258 ReportPath.cc:2228        generated clock pll source path too short.
-0259 ReportPath.cc:2392        unsupported path type
-0260 Search.cc:2637            max tag group index exceeded
-0261 Search.cc:2869            max tag index exceeded
-0262 Search.cc:3561            unexpected filter path
-0263 Search.cc:3729            tns incr existing vertex
-0264 Sta.cc:4150               corresponding timing arc set not found in equiv cells
+0259 ReportPath.cc:2378        unsupported path type
+0260 Search.cc:2628            max tag group index exceeded
+0261 Search.cc:2860            max tag index exceeded
+0262 Search.cc:3543            unexpected filter path
+0263 Search.cc:3711            tns incr existing vertex
+0264 Sta.cc:4147               corresponding timing arc set not found in equiv cells
 0265 TagGroup.cc:297           tag group missing tag
-0266 Sta.cc:2091               '%s' is not a valid endpoint.
-0267 Sta.cc:2015               '%s' is not a valid start point.
-0272 StaTcl.i:4167             unknown common clk pessimism mode.
-0273 StaTcl.i:5123             unknown clock sense
+0266 Sta.cc:2088               '%s' is not a valid endpoint.
+0267 Sta.cc:2012               '%s' is not a valid start point.
+0272 StaTcl.i:4165             unknown common clk pessimism mode.
+0273 StaTcl.i:5121             unknown clock sense
 0300 Util.tcl:218              no commands match '$pattern'.
 0301 Power.tcl:218             activity should be 0.0 to 1.0 or 2.0
 0302 Power.tcl:226             duty should be 0.0 to 1.0
@@ -209,60 +207,60 @@
 0315 Cmds.tcl:856              $arg_name '$object_type' is not a net.
 0316 Cmds.tcl:861              $arg_name '$arg' not found.
 0318 Search.tcl:1073           unknown path group '$name'.
-0319 Sdc.tcl:279               $unit scale [format %.0e $scale] does not match library scale [format %.0e $unit_scale].
-0320 Sdc.tcl:480               current_design for other than top cell not supported.
-0321 Sdc.tcl:517               patterns argument not supported with -of_objects.
-0322 Sdc.tcl:552               instance '$pattern' not found.
-0323 Sdc.tcl:613               clock '$pattern' not found.
-0324 Sdc.tcl:640               positional arguments not supported with -of_objects.
-0325 Sdc.tcl:666               library '$lib_name' not found.
-0326 Sdc.tcl:678               cell '$cell_pattern' not found.
-0327 Sdc.tcl:725               library/cell/port '$pattern' not found.
-0328 Sdc.tcl:745               port '$port_pattern' not found.
-0329 Sdc.tcl:750               library '$lib_name' not found.
-0330 Sdc.tcl:760               -nocase ignored without -regexp.
-0331 Sdc.tcl:786               library '$pattern' not found.
-0332 Sdc.tcl:849               patterns argument not supported with -of_objects.
-0333 Sdc.tcl:873               net '$pattern' not found.
-0334 Sdc.tcl:902               patterns argument not supported with -of_objects.
-0335 Sdc.tcl:939               pin '$pattern' not found.
-0336 Sdc.tcl:996               patterns argument not supported with -of_objects.
-0337 Sdc.tcl:1010              port '$pattern' not found.
-0338 Sdc.tcl:1108              non-increasing clock -waveform edge times.
-0339 Sdc.tcl:1111              -waveform time greater than two periods.
-0341 Sdc.tcl:1469              extra positional argument $arg.
-0342 Sdc.tcl:1502              -clock ignored for clock objects.
-0343 Sdc.tcl:1548              set_sense -type data not supported.
-0344 Sdc.tcl:1563              set_clock_sense is deprecated as of SDC 2.1. Use set_sense -type clock.
-0345 Sdc.tcl:1575              -pulse argument not supported.
-0346 Sdc.tcl:1584              -positive, -negative, -stop_propagation and -pulse are mutually exclusive.
-0347 Sdc.tcl:1597              hierarchical pin '[get_full_name $pin]' not supported.
-0348 Sdc.tcl:1805              -from/-to keywords ignored for lib_pin, port and pin arguments.
-0349 Sdc.tcl:1467              unknown keyword argument $arg.
-0350 Sdc.tcl:1953              -from, -through or -to required.
-0351 Sdc.tcl:2032              -source_latency_included ignored with -reference_pin.
-0352 Sdc.tcl:2035              -network_latency_included ignored with -reference_pin.
-0353 Sdc.tcl:2054              $cmd not allowed on [pin_direction $pin] port '[get_full_name $pin]'.
-0354 Sdc.tcl:2056              $cmd relative to a clock defined on the same port/pin not allowed.
-0355 Sdc.tcl:2099              '$args' ignored.
-0356 Sdc.tcl:2229              '$args' ignored.
-0357 Sdc.tcl:2276              virtual clock [get_name $clk] can not be propagated.
-0358 Sdc.tcl:2425              -multiply_by ignored.
-0359 Sdc.tcl:2428              -dont_scale ignored.
-0360 Sdc.tcl:2431              -no_design_rule ignored.
-0361 Sdc.tcl:2472              -clock not supported.
-0362 Sdc.tcl:2475              -clock_fall not supported.
-0363 Sdc.tcl:2521              -pin_load not allowed for net objects.
-0364 Sdc.tcl:2524              -wire_load not allowed for net objects.
-0365 Sdc.tcl:2527              -rise/-fall not allowed for net objects.
-0366 Sdc.tcl:2660              -data_path, -clock_path, -rise, -fall ignored for ports and designs.
-0367 Sdc.tcl:2730              derating factor greater than 2.0.
-0368 Sdc.tcl:2767              -cell_delay and -cell_check flags ignored for net objects.
-0369 Sdc.tcl:2826              no valid objects specified for $key.
-0370 Sdc.tcl:2859              no valid objects specified for $key
-0371 Sdc.tcl:3020              set_wire_load_min_block_size not supported.
+0319 Sdc.tcl:288               $unit scale [format %.0e $scale] does not match library scale [format %.0e $unit_scale].
+0320 Sdc.tcl:496               current_design for other than top cell not supported.
+0321 Sdc.tcl:533               patterns argument not supported with -of_objects.
+0322 Sdc.tcl:568               instance '$pattern' not found.
+0323 Sdc.tcl:629               clock '$pattern' not found.
+0324 Sdc.tcl:656               positional arguments not supported with -of_objects.
+0325 Sdc.tcl:682               library '$lib_name' not found.
+0326 Sdc.tcl:694               cell '$cell_pattern' not found.
+0327 Sdc.tcl:741               library/cell/port '$pattern' not found.
+0328 Sdc.tcl:761               port '$port_pattern' not found.
+0329 Sdc.tcl:766               library '$lib_name' not found.
+0330 Sdc.tcl:776               -nocase ignored without -regexp.
+0331 Sdc.tcl:802               library '$pattern' not found.
+0332 Sdc.tcl:865               patterns argument not supported with -of_objects.
+0333 Sdc.tcl:889               net '$pattern' not found.
+0334 Sdc.tcl:918               patterns argument not supported with -of_objects.
+0335 Sdc.tcl:955               pin '$pattern' not found.
+0336 Sdc.tcl:1012              patterns argument not supported with -of_objects.
+0337 Sdc.tcl:1026              port '$pattern' not found.
+0338 Sdc.tcl:1124              non-increasing clock -waveform edge times.
+0339 Sdc.tcl:1127              -waveform time greater than two periods.
+0341 Sdc.tcl:1461              extra positional argument $arg.
+0342 Sdc.tcl:1494              -clock ignored for clock objects.
+0343 Sdc.tcl:1540              set_sense -type data not supported.
+0344 Sdc.tcl:1555              set_clock_sense is deprecated as of SDC 2.1. Use set_sense -type clock.
+0345 Sdc.tcl:1567              -pulse argument not supported.
+0346 Sdc.tcl:1576              -positive, -negative, -stop_propagation and -pulse are mutually exclusive.
+0347 Sdc.tcl:1589              hierarchical pin '[get_full_name $pin]' not supported.
+0348 Sdc.tcl:1797              -from/-to keywords ignored for lib_pin, port and pin arguments.
+0349 Sdc.tcl:1459              unknown keyword argument $arg.
+0350 Sdc.tcl:1945              -from, -through or -to required.
+0351 Sdc.tcl:2024              -source_latency_included ignored with -reference_pin.
+0352 Sdc.tcl:2027              -network_latency_included ignored with -reference_pin.
+0353 Sdc.tcl:2046              $cmd not allowed on [pin_direction $pin] port '[get_full_name $pin]'.
+0354 Sdc.tcl:2048              $cmd relative to a clock defined on the same port/pin not allowed.
+0355 Sdc.tcl:2091              '$args' ignored.
+0356 Sdc.tcl:2221              '$args' ignored.
+0357 Sdc.tcl:2268              virtual clock [get_name $clk] can not be propagated.
+0358 Sdc.tcl:2417              -multiply_by ignored.
+0359 Sdc.tcl:2420              -dont_scale ignored.
+0360 Sdc.tcl:2423              -no_design_rule ignored.
+0361 Sdc.tcl:2464              -clock not supported.
+0362 Sdc.tcl:2467              -clock_fall not supported.
+0363 Sdc.tcl:2513              -pin_load not allowed for net objects.
+0364 Sdc.tcl:2516              -wire_load not allowed for net objects.
+0365 Sdc.tcl:2519              -rise/-fall not allowed for net objects.
+0366 Sdc.tcl:2652              -data_path, -clock_path, -rise, -fall ignored for ports and designs.
+0367 Sdc.tcl:2722              derating factor greater than 2.0.
+0368 Sdc.tcl:2759              -cell_delay and -cell_check flags ignored for net objects.
+0369 Sdc.tcl:2818              no valid objects specified for $key.
+0370 Sdc.tcl:2851              no valid objects specified for $key
+0371 Sdc.tcl:3012              set_wire_load_min_block_size not supported.
 0372 NetworkEdit.tcl:80        connect_pins is deprecated.  Use connect_pin.
-0373 Sdc.tcl:3170              define_corners must be called before read_liberty.
+0373 Sdc.tcl:3162              define_corners must be called before read_liberty.
 0400 Util.tcl:44               $cmd $key missing value.
 0401 Util.tcl:61               $cmd $key missing value.
 0402 Util.tcl:71               $cmd $arg is not a known keyword or flag.
@@ -372,81 +370,76 @@
 0508 Search.tcl:794            -min and -max cannot both be specified.
 0509 Search.tcl:814            pin '$pin_arg' is hierarchical.
 0510 Search.tcl:880            -format $format not recognized.
-0511 Sdc.tcl:64                cannot open '$filename'.
-0512 Sdc.tcl:119               incomplete command at end of file.
-0513 Sdc.tcl:203               hierarchy separator must be one of '$sdc_dividers'.
-0514 Sdc.tcl:250               unknown unit $unit '$suffix'.
-0515 Sdc.tcl:323               unknown $unit unit '$suffix'.
-0516 Sdc.tcl:586               unsupported instance -filter expression.
-0517 Sdc.tcl:971               unsupported pin -filter expression.
-0518 Sdc.tcl:1047              unsupported port -filter expression.
-0519 Sdc.tcl:1080              -add requires -name.
-0520 Sdc.tcl:1085              -name or port_pin_list must be specified.
-0521 Sdc.tcl:1093              missing -period argument.
-0522 Sdc.tcl:1099              -waveform edge_list must have an even number of edge times.
-0523 Sdc.tcl:1152              empty ports/pins/nets argument.
-0524 Sdc.tcl:1160              -add requires -name.
-0525 Sdc.tcl:1165              name or port_pin_list must be specified.
-0526 Sdc.tcl:1172              missing -source argument.
-0527 Sdc.tcl:1189              -master_clock argument empty.
-0528 Sdc.tcl:1192              -add requireds -master_clock.
-0529 Sdc.tcl:1196              -multiply_by and -divide_by options are exclusive.
-0530 Sdc.tcl:1200              -divide_by is not an integer greater than one.
-0531 Sdc.tcl:1203              -combinational implies -divide_by 1.
-0532 Sdc.tcl:1208              -multiply_by is not an integer greater than one.
-0533 Sdc.tcl:1214              -duty_cycle is not a float between 0 and 100.
-0534 Sdc.tcl:1220              -edges only supported for three edges.
-0535 Sdc.tcl:1226              edges times are not monotonically increasing.
-0536 Sdc.tcl:1235              -edge_shift length does not match -edges length.
-0537 Sdc.tcl:1241              missing -multiply_by, -divide_by, -combinational or -edges argument.
-0538 Sdc.tcl:1249              cannot specify -invert without -multiply_by, -divide_by or -combinational.
-0539 Sdc.tcl:1255              -duty_cycle requires -multiply_by value.
-0540 Sdc.tcl:1260              missing -pll_output argument.
-0541 Sdc.tcl:1263              missing -pll_feedback argument.
-0542 Sdc.tcl:1269              PLL output and feedback pins must be on the same instance.
-0543 Sdc.tcl:1272              source pin must be on the same instance as the PLL output pin.
-0544 Sdc.tcl:1275              PLL output must be one of the clock pins.
-0545 Sdc.tcl:1313              group_path command failed.
-0546 Sdc.tcl:1320              positional arguments not supported.
-0547 Sdc.tcl:1324              -from, -through or -to required.
-0548 Sdc.tcl:1330              -name and -default are mutually exclusive.
-0549 Sdc.tcl:1332              -name or -default option is required.
-0550 Sdc.tcl:1373              cannot specify both -high and -low.
-0551 Sdc.tcl:1381              missing -setup or -hold argument.
-0552 Sdc.tcl:1395              -high and -low only permitted for pins and instances.
-0553 Sdc.tcl:1402              -high and -low only permitted for pins and instances.
-0554 Sdc.tcl:1445              one of -logically_exclusive, -physically_exclusive or -asynchronous is required.
-0555 Sdc.tcl:1448              the keywords -logically_exclusive, -physically_exclusive and -asynchronous are mutually exclusive.
-0556 Sdc.tcl:1516              -source '[get_full_name $pin]' is not a clock pin.
-0557 Sdc.tcl:1523              -early/-late is only allowed with -source.
-0558 Sdc.tcl:1552              set_sense -type clock|data
-0559 Sdc.tcl:1621              transition time can not be specified for virtual clocks.
-0560 Sdc.tcl:1642              missing uncertainty value.
-0561 Sdc.tcl:1690              -from/-to must be used together.
-0562 Sdc.tcl:1710              -rise, -fall options not allowed for single clock uncertainty.
-0563 Sdc.tcl:1751              missing -from, -rise_from or -fall_from argument.
-0564 Sdc.tcl:1763              missing -to, -rise_to or -fall_to argument.
-0565 Sdc.tcl:1835              -from/-to hierarchical instance not supported.
-0566 Sdc.tcl:1867              pin '[get_full_name $inst]${hierarchy_separator}${port_name}' not found.
-0567 Sdc.tcl:1908              pin '[get_name $cell]${hierarchy_separator}${port_name}' not found.
-0568 Sdc.tcl:2093              missing delay argument.
-0569 Sdc.tcl:2224              missing path multiplier argument.
-0570 Sdc.tcl:2236              cannot use -start with -end.
-0571 Sdc.tcl:2304              value must be 0, zero, 1, one, rise, rising, fall, or falling.
-0572 Sdc.tcl:2362              cell '$lib_name:$cell_name' not found.
-0573 Sdc.tcl:2368              '$cell_name' not found.
-0574 Sdc.tcl:2372              missing -lib_cell argument.
-0575 Sdc.tcl:2380              port '$to_port_name' not found.
-0576 Sdc.tcl:2392              -pin argument required for cells with multiple outputs.
-0577 Sdc.tcl:2407              port '$from_port_name' not found.
-0578 Sdc.tcl:2614              port '[get_name $port]' is not an input.
-0579 Sdc.tcl:2976              operating condition '$op_cond_name' not found.
-0580 Sdc.tcl:2994              operating condition '$op_cond_name' not found.
-0581 Sdc.tcl:3008              -analysis_type must be single, bc_wc or on_chip_variation.
-0582 Sdc.tcl:3033              mode must be top, enclosed or segmented.
-0583 Sdc.tcl:3048              no wire load model specified.
-0584 Sdc.tcl:3109              wire load selection group '$selection_name' not found.
-0585 Sdc.tcl:3240              no default operating conditions found.
+0511 Sdc.tcl:73                cannot open '$filename'.
+0512 Sdc.tcl:128               incomplete command at end of file.
+0513 Sdc.tcl:212               hierarchy separator must be one of '$sdc_dividers'.
+0514 Sdc.tcl:259               unknown unit $unit '$suffix'.
+0515 Sdc.tcl:332               unknown $unit unit '$suffix'.
+0516 Sdc.tcl:602               unsupported instance -filter expression.
+0517 Sdc.tcl:987               unsupported pin -filter expression.
+0518 Sdc.tcl:1063              unsupported port -filter expression.
+0519 Sdc.tcl:1096              -add requires -name.
+0520 Sdc.tcl:1101              -name or port_pin_list must be specified.
+0521 Sdc.tcl:1109              missing -period argument.
+0522 Sdc.tcl:1115              -waveform edge_list must have an even number of edge times.
+0523 Sdc.tcl:1168              empty ports/pins/nets argument.
+0524 Sdc.tcl:1176              -add requires -name.
+0525 Sdc.tcl:1181              name or port_pin_list must be specified.
+0526 Sdc.tcl:1188              missing -source argument.
+0527 Sdc.tcl:1203              -master_clock argument empty.
+0528 Sdc.tcl:1206              -add requireds -master_clock.
+0529 Sdc.tcl:1210              -multiply_by and -divide_by options are exclusive.
+0530 Sdc.tcl:1214              -divide_by is not an integer greater than one.
+0531 Sdc.tcl:1217              -combinational implies -divide_by 1.
+0532 Sdc.tcl:1222              -multiply_by is not an integer greater than one.
+0533 Sdc.tcl:1228              -duty_cycle is not a float between 0 and 100.
+0534 Sdc.tcl:1234              -edges only supported for three edges.
+0535 Sdc.tcl:1240              edges times are not monotonically increasing.
+0536 Sdc.tcl:1249              -edge_shift length does not match -edges length.
+0537 Sdc.tcl:1255              missing -multiply_by, -divide_by, -combinational or -edges argument.
+0538 Sdc.tcl:1263              cannot specify -invert without -multiply_by, -divide_by or -combinational.
+0539 Sdc.tcl:1269              -duty_cycle requires -multiply_by value.
+0545 Sdc.tcl:1305              group_path command failed.
+0546 Sdc.tcl:1312              positional arguments not supported.
+0547 Sdc.tcl:1316              -from, -through or -to required.
+0548 Sdc.tcl:1322              -name and -default are mutually exclusive.
+0549 Sdc.tcl:1324              -name or -default option is required.
+0550 Sdc.tcl:1365              cannot specify both -high and -low.
+0551 Sdc.tcl:1373              missing -setup or -hold argument.
+0552 Sdc.tcl:1387              -high and -low only permitted for pins and instances.
+0553 Sdc.tcl:1394              -high and -low only permitted for pins and instances.
+0554 Sdc.tcl:1437              one of -logically_exclusive, -physically_exclusive or -asynchronous is required.
+0555 Sdc.tcl:1440              the keywords -logically_exclusive, -physically_exclusive and -asynchronous are mutually exclusive.
+0556 Sdc.tcl:1508              -source '[get_full_name $pin]' is not a clock pin.
+0557 Sdc.tcl:1515              -early/-late is only allowed with -source.
+0558 Sdc.tcl:1544              set_sense -type clock|data
+0559 Sdc.tcl:1613              transition time can not be specified for virtual clocks.
+0560 Sdc.tcl:1634              missing uncertainty value.
+0561 Sdc.tcl:1682              -from/-to must be used together.
+0562 Sdc.tcl:1702              -rise, -fall options not allowed for single clock uncertainty.
+0563 Sdc.tcl:1743              missing -from, -rise_from or -fall_from argument.
+0564 Sdc.tcl:1755              missing -to, -rise_to or -fall_to argument.
+0565 Sdc.tcl:1827              -from/-to hierarchical instance not supported.
+0566 Sdc.tcl:1859              pin '[get_full_name $inst]${hierarchy_separator}${port_name}' not found.
+0567 Sdc.tcl:1900              pin '[get_name $cell]${hierarchy_separator}${port_name}' not found.
+0568 Sdc.tcl:2085              missing delay argument.
+0569 Sdc.tcl:2216              missing path multiplier argument.
+0570 Sdc.tcl:2228              cannot use -start with -end.
+0571 Sdc.tcl:2296              value must be 0, zero, 1, one, rise, rising, fall, or falling.
+0572 Sdc.tcl:2354              cell '$lib_name:$cell_name' not found.
+0573 Sdc.tcl:2360              '$cell_name' not found.
+0574 Sdc.tcl:2364              missing -lib_cell argument.
+0575 Sdc.tcl:2372              port '$to_port_name' not found.
+0576 Sdc.tcl:2384              -pin argument required for cells with multiple outputs.
+0577 Sdc.tcl:2399              port '$from_port_name' not found.
+0578 Sdc.tcl:2606              port '[get_name $port]' is not an input.
+0579 Sdc.tcl:2968              operating condition '$op_cond_name' not found.
+0580 Sdc.tcl:2986              operating condition '$op_cond_name' not found.
+0581 Sdc.tcl:3000              -analysis_type must be single, bc_wc or on_chip_variation.
+0582 Sdc.tcl:3025              mode must be top, enclosed or segmented.
+0583 Sdc.tcl:3040              no wire load model specified.
+0584 Sdc.tcl:3101              wire load selection group '$selection_name' not found.
+0585 Sdc.tcl:3232              no default operating conditions found.
 0586 NetworkEdit.tcl:50        unsupported object type $object_type.
 0587 NetworkEdit.tcl:119       unsupported object type $object_type.
 0588 NetworkEdit.tcl:135       unsupported object type $object_type.
@@ -459,15 +452,15 @@
 0595 DelayNormal2.cc:378       unknown early/late value.
 0596 Sim.cc:205                unknown function operator
 0597 EstimateParasitics.cc:188 load pin not leaf or top level
-0600 Sdc.tcl:1949              '$args' ignored.
-0601 Sdc.tcl:2448              set_fanout_load not supported.
-0602 Sdc.tcl:2908              no valid objects specified for $key.
+0600 Sdc.tcl:1941              '$args' ignored.
+0601 Sdc.tcl:2440              set_fanout_load not supported.
+0602 Sdc.tcl:2900              no valid objects specified for $key.
 0603 NetworkEdit.tcl:172       disconnect_pins is deprecated.  Use disconnect_pin.
-0604 Sdc.tcl:272               unknown $unit prefix '$prefix'.
-0605 Sdc.tcl:3070              wire load model '$model_name' not found.
+0604 Sdc.tcl:281               unknown $unit prefix '$prefix'.
+0605 Sdc.tcl:3062              wire load model '$model_name' not found.
 0606 Sta.tcl:1130              get_property unsupported object type $object_type.
-0607 StaTcl.i:4417             unknown report path field %s
-0608 StaTcl.i:4429             unknown report path field %s
+0607 StaTcl.i:4415             unknown report path field %s
+0608 StaTcl.i:4427             unknown report path field %s
 0609 Search.tcl:427            -all_violators is deprecated. Use -violators
 0610 Search.tcl:507            -max_transition deprecated. Use -max_slew.
 0611 Search.tcl:512            -min_transition deprecated. Use -min_slew.
@@ -488,9 +481,11 @@
 0705 Liberty.cc:793            Liberty cell %s/%s for corner %s/%s not found
 0706 Parasitics.tcl:70         read_spef -increment is deprecated.
 0710 LumpedCapDelayCalc.cc:168 gate delay input variable is NaN
-0800 VcdReader.cc:108          unhandled vcd command.
-0801 VcdReader.cc:143          timescale syntax error.
-0802 VcdReader.cc:157          Unknown timescale unit.
-0804 VcdReader.cc:198          Variable syntax error.
-0805 Vcd.cc:170                Unknown variable %s ID %s
-0806 ReadVcdActivities.cc:216  clock %s vcd period %s differs from clock definition %s
+0800 VcdReader.cc:109          unhandled vcd command.
+0801 VcdReader.cc:145          timescale syntax error.
+0802 VcdReader.cc:159          Unknown timescale unit.
+0804 VcdReader.cc:200          Variable syntax error.
+0805 Vcd.cc:172                Unknown variable %s ID %s
+0806 ReadVcdActivities.cc:227  clock %s vcd period %s differs from SDC clock period %s
+0807 Sdc.tcl:453               only one of -cells, -data_pins, -clock_pins, -async_pins, -output_pins are suppported.
+0810 MakeTimingModel.cc:167    clock %s pin %s is inside model block.
diff --git a/sdc/Clock.cc b/sdc/Clock.cc
index bff68ae4..3758ebd9 100644
--- a/sdc/Clock.cc
+++ b/sdc/Clock.cc
@@ -36,8 +36,6 @@ Clock::Clock(const char *name,
 	     int index) :
   name_(stringCopy(name)),
   add_to_pins_(false),
-  pll_out_(nullptr),
-  pll_fdbk_(nullptr),
   period_(0.0),
   waveform_(nullptr),
   waveform_valid_(false),
@@ -312,8 +310,6 @@ Clock::initGeneratedClk(PinSet *pins,
 			bool add_to_pins,
 			Pin *src_pin,
 			Clock *master_clk,
-			Pin *pll_out,
-			Pin *pll_fdbk,
 			int divide_by,
 			int multiply_by,
 			float duty_cycle,
@@ -332,8 +328,6 @@ Clock::initGeneratedClk(PinSet *pins,
   master_clk_ = master_clk;
   master_clk_infered_ = false;
   waveform_valid_ = false;
-  pll_out_= pll_out;
-  pll_fdbk_ = pll_fdbk;
   divide_by_ = divide_by;
   multiply_by_ = multiply_by;
   duty_cycle_ = duty_cycle;
diff --git a/sdc/Sdc.cc b/sdc/Sdc.cc
index 6c9fdf5c..16cd2a3e 100644
--- a/sdc/Sdc.cc
+++ b/sdc/Sdc.cc
@@ -993,8 +993,6 @@ Sdc::makeGeneratedClock(const char *name,
 			bool add_to_pins,
 			Pin *src_pin,
 			Clock *master_clk,
-			Pin *pll_out,
-			Pin *pll_fdbk,
 			int divide_by,
 			int multiply_by,
 			float duty_cycle,
@@ -1015,7 +1013,6 @@ Sdc::makeGeneratedClock(const char *name,
     clock_name_map_[clk->name()] = clk;
   }
   clk->initGeneratedClk(pins, add_to_pins, src_pin, master_clk,
-			pll_out, pll_fdbk,
 			divide_by, multiply_by, duty_cycle,
 			invert, combinational,
 			edges, edge_shifts, propagate_all_clks_,
diff --git a/sdc/WriteSdc.cc b/sdc/WriteSdc.cc
index 23026c0f..ec50111f 100644
--- a/sdc/WriteSdc.cc
+++ b/sdc/WriteSdc.cc
@@ -433,16 +433,6 @@ WriteSdc::writeGeneratedClock(Clock *clk) const
     gzprintf(stream_, " -master_clock ");
     writeGetClock(master);
   }
-  Pin *pll_out = clk->pllOut();
-  if (pll_out) {
-    gzprintf(stream_, " -pll_out ");
-    writeGetPin(pll_out, true);
-  }
-  Pin *pll_fdbk = clk->pllFdbk();
-  if (pll_fdbk) {
-    gzprintf(stream_, " -pll_feedback ");
-    writeGetPin(pll_fdbk, false);
-  }
   if (clk->combinational())
     gzprintf(stream_, " -combinational");
   int divide_by = clk->divideBy();
diff --git a/search/Genclks.cc b/search/Genclks.cc
index a5748a33..5c0f10cb 100644
--- a/search/Genclks.cc
+++ b/search/Genclks.cc
@@ -51,8 +51,6 @@ public:
   VertexSet *fanins() const { return fanins_; }
   Level gclkLevel() const { return gclk_level_; }
   FilterPath *srcFilter() const { return src_filter_; }
-  FilterPath *pllFilter() const { return pll_filter_; }
-  void setPllFilter(FilterPath *pll_filter);
   void setLatchFdbkEdges(EdgeSet *fdbk_edges);
   bool foundLatchFdbkEdges() const { return found_latch_fdbk_edges_; }
   void setFoundLatchFdbkEdges(bool found);
@@ -64,7 +62,6 @@ protected:
   EdgeSet *fdbk_edges_;
   bool found_latch_fdbk_edges_;
   FilterPath *src_filter_;
-  FilterPath *pll_filter_;
 };
 
 GenclkInfo::GenclkInfo(Clock *gclk,
@@ -76,8 +73,7 @@ GenclkInfo::GenclkInfo(Clock *gclk,
   fanins_(fanins),
   fdbk_edges_(nullptr),
   found_latch_fdbk_edges_(false),
-  src_filter_(src_filter),
-  pll_filter_(nullptr)
+  src_filter_(src_filter)
 {
 }
 
@@ -86,13 +82,6 @@ GenclkInfo::~GenclkInfo()
   delete fanins_;
   delete fdbk_edges_;
   delete src_filter_;
-  delete pll_filter_;
-}
-
-void
-GenclkInfo::setPllFilter(FilterPath *pll_filter)
-{
-  pll_filter_ = pll_filter;
 }
 
 void
@@ -217,8 +206,6 @@ Genclks::ensureInsertionDelays()
       Clock *gclk = gclk_iter.next();
       if (gclk->masterClk()) {
 	findInsertionDelays(gclk);
-	if (gclk->pllOut())
-	  findPllDelays(gclk);
 	recordSrcPaths(gclk);
       }
     }
@@ -295,93 +282,57 @@ Genclks::ensureMaster(Clock *gclk)
   if (master_clk == nullptr) {
     int master_clk_count = 0;
     bool found_master = false;
-    if (gclk->pllOut()) {
+    Pin *src_pin = gclk->srcPin();
+    ClockSet *master_clks = sdc_->findClocks(src_pin);
+    ClockSet::Iterator master_iter(master_clks);
+    if (master_iter.hasNext()) {
+      while (master_iter.hasNext()) {
+        master_clk = master_iter.next();
+        // Master source pin can actually be a clock source pin.
+        if (master_clk != gclk) {
+          gclk->setInferedMasterClk(master_clk);
+          debugPrint(debug_, "genclk", 2, " %s master clk %s",
+                     gclk->name(),
+                     master_clk->name());
+          found_master = true;
+          master_clk_count++;
+        }
+      }
+    }
+    if (!found_master) {
       // Search backward from generated clock source pin to a clock pin.
       GenClkMasterSearchPred pred(this);
       BfsBkwdIterator iter(BfsIndex::other, &pred, this);
       seedSrcPins(gclk, iter);
       while (iter.hasNext()) {
-	Vertex *vertex = iter.next();
-	Pin *pin = vertex->pin();
-	if (sdc_->isLeafPinClock(pin)) {
-	  ClockSet *master_clks = sdc_->findLeafPinClocks(pin);
-	  if (master_clks) {
-	    ClockSet::Iterator master_iter(master_clks);
-	    while (master_iter.hasNext()) {
-	      master_clk = master_iter.next();
-	      // Master source pin can actually be a clock source pin.
-	      if (master_clk != gclk) {
-		gclk->setInferedMasterClk(master_clk);
-		debugPrint(debug_, "genclk", 2, " %s master clk %s",
+        Vertex *vertex = iter.next();
+        Pin *pin = vertex->pin();
+        if (sdc_->isLeafPinClock(pin)) {
+          ClockSet *master_clks = sdc_->findLeafPinClocks(pin);
+          if (master_clks) {
+            ClockSet::Iterator master_iter(master_clks);
+            if (master_iter.hasNext()) {
+              master_clk = master_iter.next();
+              // Master source pin can actually be a clock source pin.
+              if (master_clk != gclk) {
+                gclk->setInferedMasterClk(master_clk);
+                debugPrint(debug_, "genclk", 2, " %s master clk %s",
                            gclk->name(),
                            master_clk->name());
-		found_master = true;
-		master_clk_count++;
-	      }
-	    }
-	  }
-	}
-	if (found_master)
-	  break;
-	iter.enqueueAdjacentVertices(vertex);
+                master_clk_count++;
+                break;
+              }
+            }
+          }
+        }
+        iter.enqueueAdjacentVertices(vertex);
       }
-      if (master_clk_count > 1)
-	report_->warn(11, "generated clock %s is in the fanout of multiple clocks.",
-                      gclk->name());
-    }
-    else {
-      Pin *src_pin = gclk->srcPin();
-      ClockSet *master_clks = sdc_->findClocks(src_pin);
-      ClockSet::Iterator master_iter(master_clks);
-      if (master_iter.hasNext()) {
-	while (master_iter.hasNext()) {
-	  master_clk = master_iter.next();
-	  // Master source pin can actually be a clock source pin.
-	  if (master_clk != gclk) {
-	    gclk->setInferedMasterClk(master_clk);
-	    debugPrint(debug_, "genclk", 2, " %s master clk %s",
-                       gclk->name(),
-                       master_clk->name());
-	    found_master = true;
-	    master_clk_count++;
-	  }
-	}
-      }
-      if (!found_master) {
-	// Search backward from generated clock source pin to a clock pin.
-	GenClkMasterSearchPred pred(this);
-	BfsBkwdIterator iter(BfsIndex::other, &pred, this);
-	seedSrcPins(gclk, iter);
-	while (iter.hasNext()) {
-	  Vertex *vertex = iter.next();
-	  Pin *pin = vertex->pin();
-	  if (sdc_->isLeafPinClock(pin)) {
-	    ClockSet *master_clks = sdc_->findLeafPinClocks(pin);
-	    if (master_clks) {
-	      ClockSet::Iterator master_iter(master_clks);
-	      if (master_iter.hasNext()) {
-		master_clk = master_iter.next();
-		// Master source pin can actually be a clock source pin.
-		if (master_clk != gclk) {
-		  gclk->setInferedMasterClk(master_clk);
-		  debugPrint(debug_, "genclk", 2, " %s master clk %s",
-                             gclk->name(),
-                             master_clk->name());
-		  master_clk_count++;
-		  break;
-		}
-	      }
-	    }
-	  }
-	  iter.enqueueAdjacentVertices(vertex);
-	}
-      }
-      if (master_clk_count > 1)
-	report_->warn(12,
-                      "generated clock %s pin %s is in the fanout of multiple clocks.",
-                      gclk->name(),
-                      network_->pathName(src_pin));
     }
+    if (master_clk_count > 1)
+      report_->warn(12,
+                    "generated clock %s pin %s is in the fanout of multiple clocks.",
+                    gclk->name(),
+                    network_->pathName(src_pin));
   }
 }
 
@@ -1066,23 +1017,7 @@ Genclks::insertionDelay(const Clock *clk,
   PathVertex src_path;
   PathAnalysisPt *insert_ap = path_ap->insertionAnalysisPt(early_late);
   srcPath(clk, pin, rf, insert_ap, src_path);
-  if (clk->pllFdbk()) {
-    const MinMax *min_max = path_ap->pathMinMax();
-    PathAnalysisPt *pll_ap = path_ap->insertionAnalysisPt(min_max->opposite());
-    Arrival pll_delay = pllDelay(clk, rf, pll_ap);
-    if (src_path.isNull())
-      return -pll_delay;
-    else {
-      PathRef prev;
-      src_path.prevPath(this, prev);
-      if (prev.isNull())
-	return -pll_delay;
-      else
-	// PLL delay replaces clkin->clkout delay.
-	return prev.arrival(this) - pll_delay;
-    }
-  }
-  else if (!src_path.isNull())
+  if (!src_path.isNull())
     return src_path.arrival(this);
   else
     return 0.0;
@@ -1090,170 +1025,6 @@ Genclks::insertionDelay(const Clock *clk,
 
 ////////////////////////////////////////////////////////////////
 
-void
-Genclks::findPllDelays(Clock *gclk)
-{
-  debugPrint(debug_, "genclk", 2, "find gen clk %s pll delay",
-             gclk->name());
-  FilterPath *pll_filter = makePllFilter(gclk);
-  GenclkInfo *genclk_info = genclkInfo(gclk);
-  if (genclk_info) {
-    genclk_info->setPllFilter(pll_filter);
-    ClkTreeSearchPred srch_pred(this);
-    BfsFwdIterator pll_iter(BfsIndex::other, &srch_pred, this);
-    seedPllPin(gclk, pll_filter, pll_iter);
-    // Propagate arrivals to pll feedback pin level.
-    findPllArrivals(gclk, pll_iter);
-    sdc_->unrecordException(pll_filter);
-  }
-}
-
-FilterPath *
-Genclks::makePllFilter(const Clock *gclk)
-{
-  PinSet *from_pins = new PinSet;
-  from_pins->insert(gclk->pllOut());
-  RiseFallBoth *rf = RiseFallBoth::riseFall();
-  ExceptionFrom *from = sdc_->makeExceptionFrom(from_pins,nullptr,nullptr,rf);
-
-  PinSet *to_pins = new PinSet;
-  to_pins->insert(gclk->pllFdbk());
-  ExceptionTo *to = sdc_->makeExceptionTo(to_pins, nullptr, nullptr, rf, rf);
-
-  return sdc_->makeFilterPath(from, nullptr, to);
-}
-
-void
-Genclks::seedPllPin(const Clock *gclk,
-		    FilterPath *pll_filter,
-		    BfsFwdIterator &pll_iter)
-{
-  Pin *pll_out_pin = gclk->pllOut();
-  Vertex *vertex = graph_->pinDrvrVertex(pll_out_pin);
-  if (vertex) {
-    debugPrint(debug_, "genclk", 2, " seed pllout pin %s",
-               network_->pathName(pll_out_pin));
-    TagGroupBldr tag_bldr(true, this);
-    tag_bldr.init(vertex);
-    copyGenClkSrcPaths(vertex, &tag_bldr);
-    for (auto path_ap : corners_->pathAnalysisPts()) {
-      for (auto tr : RiseFall::range()) {
-        Tag *tag = makeTag(gclk, gclk, pll_out_pin, tr, pll_filter, path_ap);
-        tag_bldr.setArrival(tag, 0.0, nullptr);
-      }
-    }
-    search_->setVertexArrivals(vertex, &tag_bldr);
-    pll_iter.enqueueAdjacentVertices(vertex);
-  }
-}
-
-class PllEvalPred : public EvalPred
-{
-public:
-  explicit PllEvalPred(const StaState *sta);
-  // Override EvalPred::searchTo to allow eval at generated clk root.
-  virtual bool searchTo(const Vertex *to_vertex);
-};
-
-PllEvalPred::PllEvalPred(const StaState *sta) :
-  EvalPred(sta)
-{
-}
-
-bool
-PllEvalPred::searchTo(const Vertex *)
-{
-  return true;
-}
-
-class PllArrivalVisitor : public ArrivalVisitor
-{
-public:
-  PllArrivalVisitor(const StaState *sta,
-		    BfsFwdIterator &pll_iter);
-  virtual void visit(Vertex *vertex);
-
-protected:
-  BfsFwdIterator &pll_iter_;
-};
-
-PllArrivalVisitor::PllArrivalVisitor(const StaState *sta,
-				     BfsFwdIterator &pll_iter) :
-  ArrivalVisitor(sta),
-  pll_iter_(pll_iter)
-{
-}
-
-void
-PllArrivalVisitor::visit(Vertex *vertex)
-{
-  Genclks *genclks = search_->genclks();
-  debugPrint(debug_, "genclk", 2, "find gen clk pll arrival %s",
-             vertex->name(sdc_network_));
-  tag_bldr_->init(vertex);
-  genclks->copyGenClkSrcPaths(vertex, tag_bldr_);
-  has_fanin_one_ = graph_->hasFaninOne(vertex);
-  visitFaninPaths(vertex);
-  pll_iter_.enqueueAdjacentVertices(vertex);
-  search_->setVertexArrivals(vertex, tag_bldr_);
-}
-
-void
-Genclks::findPllArrivals(const Clock *gclk,
-			 BfsFwdIterator &pll_iter)
-{
-  Pin *fdbk_pin = gclk->pllFdbk();
-  Vertex *fdbk_vertex = graph_->pinLoadVertex(fdbk_pin);
-  Level fdbk_level = fdbk_vertex->level();
-  PllArrivalVisitor arrival_visitor(this, pll_iter);
-  PllEvalPred eval_pred(this);
-  arrival_visitor.init(true, &eval_pred);
-  while (pll_iter.hasNext(fdbk_level)) {
-    Vertex *vertex = pll_iter.next();
-    arrival_visitor.visit(vertex);
-  }
-}
-
-Arrival
-Genclks::pllDelay(const Clock *clk,
-		  const RiseFall *rf,
-		  const PathAnalysisPt *path_ap) const
-{
-  Vertex *fdbk_vertex = graph_->pinLoadVertex(clk->pllFdbk());
-  GenclkInfo *genclk_info = genclkInfo(clk);
-  if (genclk_info) {
-    FilterPath *pll_filter = genclk_info->pllFilter();
-    VertexPathIterator fdbk_path_iter(fdbk_vertex, rf, path_ap, this);
-    while (fdbk_path_iter.hasNext()) {
-      Path *path = fdbk_path_iter.next();
-      if (matchesPllFilter(path, pll_filter))
-	return path->arrival(this);
-    }
-  }
-  return delay_zero;
-}
-
-bool
-Genclks::matchesPllFilter(Path *path,
-			  FilterPath *pll_filter) const
-{
-  Tag *tag = path->tag(this);
-  const ExceptionStateSet *states = tag->states();
-  if (tag->isGenClkSrcPath()
-      && states) {
-    ExceptionStateSet::ConstIterator state_iter(states);
-    while (state_iter.hasNext()) {
-      ExceptionState *state = state_iter.next();
-      ExceptionPath *except = state->exception();
-      if (except == pll_filter)
-	return true;
-    }
-  }
-  return false;
-}
-
-////////////////////////////////////////////////////////////////
-
 bool
 ClockPinPairLess::operator()(const ClockPinPair &pair1,
 			     const ClockPinPair &pair2) const
diff --git a/search/Genclks.hh b/search/Genclks.hh
index d5a7cc54..c304672b 100644
--- a/search/Genclks.hh
+++ b/search/Genclks.hh
@@ -78,9 +78,6 @@ public:
 	       const PathAnalysisPt *path_ap,
 	       // Return value.
 	       PathVertex &src_path) const;
-  Arrival pllDelay(const Clock *clk,
-		   const RiseFall *rf,
-		   const PathAnalysisPt *path_ap) const;
   Vertex *srcPathVertex(const Pin *pin) const;
   Level clkPinMaxLevel(const Clock *clk) const;
   void copyGenClkSrcPaths(Vertex *vertex,
@@ -99,15 +96,6 @@ private:
 		   const PathAnalysisPt *path_ap) const;
   bool matchesSrcFilter(Path *path,
 			const Clock *gclk) const;
-  void findPllDelays(Clock *gclk);
-  FilterPath *makePllFilter(const Clock *gclk);
-  bool matchesPllFilter(Path *path,
-			FilterPath *pll_filter) const;
-  void seedPllPin(const Clock *gclk,
-		  FilterPath *pll_filter,
-			BfsFwdIterator &pll_iter);
-  void findPllArrivals(const Clock *gclk,
-		       BfsFwdIterator &pll_iter);
   void seedSrcPins(Clock *gclk,
 		   FilterPath *src_filter,
 		   BfsFwdIterator &insert_iter);
diff --git a/search/ReportPath.cc b/search/ReportPath.cc
index 67801d74..39e75d45 100644
--- a/search/ReportPath.cc
+++ b/search/ReportPath.cc
@@ -2218,22 +2218,8 @@ ReportPath::reportGenClkSrcPath1(Clock *clk,
         reportClkSrcLatency(insertion, gclk_time, early_late);
       }
       PathExpanded src_expanded(&src_path, this);
-      if (clk->pllOut()) {
-        reportPath4(&src_path, src_expanded, skip_first_path, true,
-                    clk_used_as_data, gclk_time);
-        PathAnalysisPt *pll_ap=path_ap->insertionAnalysisPt(min_max->opposite());
-        Arrival pll_delay = search_->genclks()->pllDelay(clk, clk_rf, pll_ap);
-        size_t path_length = src_expanded.size();
-        if (path_length < 2)
-          report_->critical(258, "generated clock pll source path too short.");
-        PathRef *path0 = src_expanded.path(path_length - 2);
-        Arrival time0 = path0->arrival(this) + gclk_time;
-        PathRef *path1 = src_expanded.path(path_length - 1);
-        reportPathLine(path1, -pll_delay, time0 - pll_delay, "pll_delay");
-      }
-      else
-        reportPath4(&src_path, src_expanded, skip_first_path, false,
-                    clk_used_as_data, gclk_time);
+      reportPath4(&src_path, src_expanded, skip_first_path, false,
+                  clk_used_as_data, gclk_time);
       if (!clk->isPropagated())
         reportLine("clock network delay (ideal)", 0.0,
                    src_path.arrival(this), min_max);
diff --git a/search/Search.cc b/search/Search.cc
index 49b2d432..509d4189 100644
--- a/search/Search.cc
+++ b/search/Search.cc
@@ -2097,15 +2097,6 @@ PathVisitor::visitFromPath(const Pin *from_pin,
 	  }
 	}
       }
-      else {
-	// PLL out to feedback path.
-	to_tag = search_->thruTag(from_tag, edge, to_rf, min_max, path_ap);
-	if (to_tag) {
-	  arc_delay = search_->deratedDelay(from_vertex, arc, edge, true,
-					   path_ap);
-	  to_arrival = from_arrival + arc_delay;
-	}
-      }
     }
   }
   else if (role->genericRole() == TimingRole::regClkToQ()) {
@@ -3497,15 +3488,6 @@ Search::ensureDownstreamClkPins()
     for (Vertex *vertex : *graph_->regClkVertices())
       iter.enqueue(vertex);
 
-    // Enqueue PLL feedback pins.
-    VertexIterator vertex_iter(graph_);
-    while (vertex_iter.hasNext()) {
-      Vertex *vertex = vertex_iter.next();
-      Pin *pin = vertex->pin();
-      const LibertyPort *port = network_->libertyPort(pin);
-      if (port && port->isPllFeedbackPin())
-	iter.enqueue(vertex);
-    }
     while (iter.hasNext()) {
       Vertex *vertex = iter.next();
       vertex->setHasDownstreamClkPin(true);
diff --git a/search/Sta.cc b/search/Sta.cc
index 45317cfe..8efd3ea6 100644
--- a/search/Sta.cc
+++ b/search/Sta.cc
@@ -1096,8 +1096,6 @@ Sta::makeGeneratedClock(const char *name,
 			bool add_to_pins,
 			Pin *src_pin,
 			Clock *master_clk,
-			Pin *pll_out,
-			Pin *pll_fdbk,
 			int divide_by,
 			int multiply_by,
 			float duty_cycle,
@@ -1109,7 +1107,6 @@ Sta::makeGeneratedClock(const char *name,
 {
   sdc_->makeGeneratedClock(name, pins, add_to_pins,
 			   src_pin, master_clk,
-			   pll_out, pll_fdbk,
 			   divide_by, multiply_by, duty_cycle,
 			   invert, combinational,
 			   edges, edge_shifts, comment);
diff --git a/tcl/Sdc.tcl b/tcl/Sdc.tcl
index 3a3d1519..2a67f711 100644
--- a/tcl/Sdc.tcl
+++ b/tcl/Sdc.tcl
@@ -445,6 +445,13 @@ proc all_registers { args } {
     set edge_triggered 1
     set level_sensitive 1
   }
+  if { [expr [info exists flags(-cells)] \
+          + [info exists flags(-data_pins)] \
+          + [info exists flags(-clock_pins)] \
+          +  [info exists flags(-async_pins)] \
+          + [info exists flags(-output_pins)]] > 1 } {
+    sta_error 807 "only one of -cells, -data_pins, -clock_pins, -async_pins, -output_pins are suppported."
+  }
   if [info exists flags(-cells)] {
     return [find_register_instances $clks $clk_rf \
 	      $edge_triggered $level_sensitive]
@@ -1139,13 +1146,12 @@ define_cmd_args "create_generated_clock" \
      [-divide_by divisor | -multiply_by multiplier]\
      [-duty_cycle duty_cycle] [-invert] [-edges edge_list]\
      [-edge_shift edge_shift_list] [-combinational] [-add]\
-     [-pll_output pll_out_pin] [-pll_feedback pll_fdbk_pin]\
      [-comment comment] port_pin_list}
 
 proc create_generated_clock { args } {
   parse_key_args "create_generated_clock" args keys \
     {-name -source -master_clock -divide_by -multiply_by \
-       -duty_cycle -edges -edge_shift -pll_output -pll_feedback -comment} \
+       -duty_cycle -edges -edge_shift -comment} \
     flags {-invert -combinational -add}
   
   check_argc_eq1 "create_generated_clock" $args
@@ -1187,8 +1193,6 @@ proc create_generated_clock { args } {
   set duty_cycle 0
   set edges {}
   set edge_shifts {}
-  set pll_out "NULL"
-  set pll_feedback "NULL"
   
   set combinational [info exists flags(-combinational)]
   
@@ -1264,31 +1268,9 @@ proc create_generated_clock { args } {
     sta_error 539 "-duty_cycle requires -multiply_by value."
   }
   
-  if { [info exists keys(-pll_feedback)] || [info exists keys(-pll_output)] } {
-    if {![info exists keys(-pll_output)] } {
-      sta_error 540 "missing -pll_output argument."
-    }
-    if { ![info exists keys(-pll_feedback)] } {
-      sta_error 541 "missing -pll_feedback argument."
-    }
-    set pll_feedback [get_pin_error "-pll_feedback" $keys(-pll_feedback)]
-    set pll_out [get_pin_error "-pll_output" $keys(-pll_output)]
-    set pll_inst [$pll_out instance]
-    if { [$pll_feedback instance] != $pll_inst } {
-      sta_error 542 "PLL output and feedback pins must be on the same instance."
-    }
-    if { [$source_pin instance] != $pll_inst } {
-      sta_error 543 "source pin must be on the same instance as the PLL output pin."
-    }
-    if { [lsearch $pins $pll_out] == -1 } {
-      sta_error 544 "PLL output must be one of the clock pins."
-    }
-  }
-  
   set comment [parse_comment_key keys]
   
   make_generated_clock $name $pins $add $source_pin $master_clk \
-    $pll_out $pll_feedback \
     $divide_by $multiply_by $duty_cycle $invert $combinational \
     $edges $edge_shifts $comment
 }
diff --git a/tcl/StaTcl.i b/tcl/StaTcl.i
index 6887ff43..09a4ea5d 100644
--- a/tcl/StaTcl.i
+++ b/tcl/StaTcl.i
@@ -2990,8 +2990,6 @@ make_generated_clock(const char *name,
 		     bool add_to_pins,
 		     Pin *src_pin,
 		     Clock *master_clk,
-		     Pin *pll_out,
-		     Pin *pll_fdbk,
 		     int divide_by,
 		     int multiply_by,
 		     float duty_cycle,
@@ -3003,7 +3001,7 @@ make_generated_clock(const char *name,
 {
   cmdLinkedNetwork();
   Sta::sta()->makeGeneratedClock(name, pins, add_to_pins,
-				 src_pin, master_clk, pll_out, pll_fdbk,
+				 src_pin, master_clk,
 				 divide_by, multiply_by, duty_cycle, invert,
 				 combinational, edges, edge_shifts,
 				 comment);