diff --git a/sdc/Sdc.tcl b/sdc/Sdc.tcl
index f32fe2da..c61aff3b 100644
--- a/sdc/Sdc.tcl
+++ b/sdc/Sdc.tcl
@@ -921,7 +921,7 @@ proc get_ports { args } {
     }
   }
   if [info exists keys(-filter)] {
-    set ports [filter_objs $keys(-filter) $portss filter_ports "port" 2366]
+    set ports [filter_objs $keys(-filter) $ports filter_ports "port" 2366]
   }
   return $ports
 }
diff --git a/tcl/StaTclTypes.i b/tcl/StaTclTypes.i
index d2e463c0..9456196d 100644
--- a/tcl/StaTclTypes.i
+++ b/tcl/StaTclTypes.i
@@ -520,6 +520,10 @@ using namespace sta;
   seqTclList<CellSeq, Cell>($1, SWIGTYPE_p_Cell, interp);
 }
 
+%typemap(in) LibertyCellSeq* {
+  $1 = tclListSeqPtr<LibertyCell*>($input, SWIGTYPE_p_LibertyCell, interp);
+}
+
 %typemap(out) LibertyCellSeq * {
   seqPtrTclList<LibertyCellSeq, LibertyCell>($1, SWIGTYPE_p_LibertyCell, interp);
 }
@@ -528,6 +532,10 @@ using namespace sta;
   seqTclList<LibertyCellSeq, LibertyCell>($1, SWIGTYPE_p_LibertyCell, interp);
 }
 
+%typemap(in) LibertyPortSeq* {
+  $1 = tclListSeqPtr<LibertyPort*>($input, SWIGTYPE_p_LibertyPort, interp);
+}
+
 %typemap(out) LibertyPortSeq * {
   seqPtrTclList<LibertyPortSeq, LibertyPort>($1, SWIGTYPE_p_LibertyPort, interp);
 }
@@ -750,8 +758,8 @@ using namespace sta;
   Tcl_SetObjResult(interp, obj);
 }
 
-%typemap(out) LibertyLibrarySeq* {
-  seqPtrTclList<LibertyLibrarySeq, LibertyLibrary>($1, SWIGTYPE_p_LibertyLibrary, interp);
+%typemap(in) LibertyLibrarySeq* {
+  $1 = tclListSeqPtr<LibertyLibrary*>($input, SWIGTYPE_p_LibertyLibrary, interp);
 }
 
 %typemap(out) LibertyLibrarySeq {
@@ -776,6 +784,10 @@ using namespace sta;
   Tcl_SetObjResult(interp, obj);
 }
 
+%typemap(in) NetSeq* {
+  $1 = tclListSeqPtr<const Net*>($input, SWIGTYPE_p_Net, interp);
+}
+
 %typemap(out) NetSeq* {
   seqPtrTclList<NetSeq, Net>($1, SWIGTYPE_p_Net, interp);
 }
@@ -817,6 +829,10 @@ using namespace sta;
   $1 = tclListSeq<const Clock*>($input, SWIGTYPE_p_Clock, interp);
 }
 
+%typemap(in) ClockSeq* {
+  $1 = tclListSeqPtr<Clock*>($input, SWIGTYPE_p_Clock, interp);
+}
+
 %typemap(out) ClockSeq* {
   seqPtrTclList<ClockSeq, Clock>($1, SWIGTYPE_p_Clock, interp);
 }
diff --git a/test/regression_vars.tcl b/test/regression_vars.tcl
index 5ecca193..a31563b1 100644
--- a/test/regression_vars.tcl
+++ b/test/regression_vars.tcl
@@ -125,6 +125,7 @@ record_sta_tests {
   prima3
   verilog_attribute
   liberty_arcs_one2one
+  sdc_filter
 }
 
 define_test_group fast [group_tests all]
diff --git a/test/sdc_filter.ok b/test/sdc_filter.ok
new file mode 100644
index 00000000..f5d4d834
--- /dev/null
+++ b/test/sdc_filter.ok
@@ -0,0 +1,39 @@
+Warning: asap7_simple.lib.gz line 71510, when attribute inside table model.
+Warning: asap7_simple.lib.gz line 71986, when attribute inside table model.
+Warning: asap7_simple.lib.gz line 72462, when attribute inside table model.
+Warning: asap7_simple.lib.gz line 72938, when attribute inside table model.
+Warning: asap7_simple.lib.gz line 73414, when attribute inside table model.
+Warning: asap7_simple.lib.gz line 74830, when attribute inside table model.
+Warning: asap7_simple.lib.gz line 71029, timing group from output port.
+Warning: asap7_simple.lib.gz line 71505, timing group from output port.
+Warning: asap7_simple.lib.gz line 71981, timing group from output port.
+Warning: asap7_simple.lib.gz line 72457, timing group from output port.
+Warning: asap7_simple.lib.gz line 72933, timing group from output port.
+Warning: asap7_simple.lib.gz line 73409, timing group from output port.
+Warning: asap7_simple.lib.gz line 73885, timing group from output port.
+Warning: asap7_simple.lib.gz line 82276, when attribute inside table model.
+Warning: asap7_simple.lib.gz line 83692, when attribute inside table model.
+Warning: asap7_simple.lib.gz line 81795, timing group from output port.
+Warning: asap7_simple.lib.gz line 82271, timing group from output port.
+Warning: asap7_simple.lib.gz line 82747, timing group from output port.
+get_cells
+u1
+get_clocks
+clk
+vclk
+get_lib_cells
+asap7sc7p5t_INVBUF_RVT_TT_ccs_211120/BUFx10_ASAP7_75t_R asap7sc7p5t_INVBUF_RVT_TT_ccs_211120/BUFx12_ASAP7_75t_R asap7sc7p5t_INVBUF_RVT_TT_ccs_211120/BUFx12f_ASAP7_75t_R asap7sc7p5t_INVBUF_RVT_TT_ccs_211120/BUFx16f_ASAP7_75t_R asap7sc7p5t_INVBUF_RVT_TT_ccs_211120/BUFx24_ASAP7_75t_R asap7sc7p5t_INVBUF_RVT_TT_ccs_211120/BUFx2_ASAP7_75t_R asap7sc7p5t_INVBUF_RVT_TT_ccs_211120/BUFx3_ASAP7_75t_R asap7sc7p5t_INVBUF_RVT_TT_ccs_211120/BUFx4_ASAP7_75t_R asap7sc7p5t_INVBUF_RVT_TT_ccs_211120/BUFx4f_ASAP7_75t_R asap7sc7p5t_INVBUF_RVT_TT_ccs_211120/BUFx5_ASAP7_75t_R asap7sc7p5t_INVBUF_RVT_TT_ccs_211120/BUFx6f_ASAP7_75t_R asap7sc7p5t_INVBUF_RVT_TT_ccs_211120/BUFx8_ASAP7_75t_R asap7sc7p5t_INVBUF_RVT_TT_ccs_211120/HB1xp67_ASAP7_75t_R asap7sc7p5t_INVBUF_RVT_TT_ccs_211120/HB2xp67_ASAP7_75t_R asap7sc7p5t_INVBUF_RVT_TT_ccs_211120/HB3xp67_ASAP7_75t_R asap7sc7p5t_INVBUF_RVT_TT_ccs_211120/HB4xp67_ASAP7_75t_R
+asap7sc7p5t_INVBUF_RVT_TT_ccs_211120/CKINVDCx10_ASAP7_75t_R asap7sc7p5t_INVBUF_RVT_TT_ccs_211120/CKINVDCx11_ASAP7_75t_R asap7sc7p5t_INVBUF_RVT_TT_ccs_211120/CKINVDCx12_ASAP7_75t_R asap7sc7p5t_INVBUF_RVT_TT_ccs_211120/CKINVDCx14_ASAP7_75t_R asap7sc7p5t_INVBUF_RVT_TT_ccs_211120/CKINVDCx16_ASAP7_75t_R asap7sc7p5t_INVBUF_RVT_TT_ccs_211120/CKINVDCx20_ASAP7_75t_R asap7sc7p5t_INVBUF_RVT_TT_ccs_211120/CKINVDCx5p33_ASAP7_75t_R asap7sc7p5t_INVBUF_RVT_TT_ccs_211120/CKINVDCx6p67_ASAP7_75t_R asap7sc7p5t_INVBUF_RVT_TT_ccs_211120/CKINVDCx8_ASAP7_75t_R asap7sc7p5t_INVBUF_RVT_TT_ccs_211120/CKINVDCx9p33_ASAP7_75t_R asap7sc7p5t_INVBUF_RVT_TT_ccs_211120/INVx11_ASAP7_75t_R asap7sc7p5t_INVBUF_RVT_TT_ccs_211120/INVx13_ASAP7_75t_R asap7sc7p5t_INVBUF_RVT_TT_ccs_211120/INVx1_ASAP7_75t_R asap7sc7p5t_INVBUF_RVT_TT_ccs_211120/INVx2_ASAP7_75t_R asap7sc7p5t_INVBUF_RVT_TT_ccs_211120/INVx3_ASAP7_75t_R asap7sc7p5t_INVBUF_RVT_TT_ccs_211120/INVx4_ASAP7_75t_R asap7sc7p5t_INVBUF_RVT_TT_ccs_211120/INVx5_ASAP7_75t_R asap7sc7p5t_INVBUF_RVT_TT_ccs_211120/INVx6_ASAP7_75t_R asap7sc7p5t_INVBUF_RVT_TT_ccs_211120/INVx8_ASAP7_75t_R asap7sc7p5t_INVBUF_RVT_TT_ccs_211120/INVxp33_ASAP7_75t_R asap7sc7p5t_INVBUF_RVT_TT_ccs_211120/INVxp67_ASAP7_75t_R
+get_lib_pins
+A
+Y
+get_libs
+asap7sc7p5t_INVBUF_RVT_TT_ccs_211120
+get_nets
+r1q r2q
+get_pins
+r1/CLK r1/D r2/CLK r2/D r3/CLK r3/D u1/A u2/A u2/B
+r1/Q r2/Q r3/Q u1/Y u2/Y
+get_ports
+in1 in2 clk1 clk2 clk3
+out
diff --git a/test/sdc_filter.tcl b/test/sdc_filter.tcl
new file mode 100644
index 00000000..7dc4c1a3
--- /dev/null
+++ b/test/sdc_filter.tcl
@@ -0,0 +1,40 @@
+# Helper functions
+proc get_full_names { collection } {
+  set full_names {}
+  foreach name $collection {
+    lappend full_names [get_full_name $name]
+  }
+  return $full_names
+}
+
+# Read in design and libraries
+read_liberty asap7_invbuf.lib.gz
+read_liberty asap7_seq.lib.gz
+read_liberty asap7_simple.lib.gz
+read_verilog reg1_asap7.v
+link_design top
+create_clock -name clk -period 500 {clk1 clk2 clk3}
+create_clock -name vclk -period 1000
+
+# Test filters for each SDC command
+puts "get_cells"
+puts [get_full_names [get_cells -filter liberty_cell==BUFx2_ASAP7_75t_R *]]
+puts "get_clocks"
+puts [get_full_names [get_clocks -filter is_virtual==0 *]]
+puts [get_full_names [get_clocks -filter is_virtual==1 *]]
+puts "get_lib_cells"
+puts [get_full_names [get_lib_cells -filter is_buffer==1 *]]
+puts [get_full_names [get_lib_cells -filter is_inverter==1 *]]
+puts "get_lib_pins"
+puts [get_full_names [get_lib_pins -filter direction==input BUFx2_ASAP7_75t_R/*]]
+puts [get_full_names [get_lib_pins -filter direction==output BUFx2_ASAP7_75t_R/*]]
+puts "get_libs"
+puts [get_full_names [get_libs -filter name==asap7sc7p5t_INVBUF_RVT_TT_ccs_211120 *]]
+puts "get_nets"
+puts [get_full_names [get_nets -filter name=~*q *]]
+puts "get_pins"
+puts [get_full_names [get_pins -filter direction==input *]]
+puts [get_full_names [get_pins -filter direction==output *]]
+puts "get_ports"
+puts [get_full_names [get_ports -filter direction==input *]]
+puts [get_full_names [get_ports -filter direction==output *]]