From 5c1a9eb523fb3e29fa7b2eb2fa9d01ef25b7dd87 Mon Sep 17 00:00:00 2001 From: dsengupta0628 Date: Tue, 10 Feb 2026 02:40:33 +0000 Subject: [PATCH 1/7] Fix write_verilog escape seq Issue 3826 Signed-off-by: dsengupta0628 --- network/VerilogNamespace.cc | 15 +++++++-------- test/test_write_verilog_escape.tcl | 11 +++++++++++ test/test_write_verilog_escape.v | 14 ++++++++++++++ verilog/VerilogWriter.cc | 3 ++- 4 files changed, 34 insertions(+), 9 deletions(-) create mode 100644 test/test_write_verilog_escape.tcl create mode 100644 test/test_write_verilog_escape.v diff --git a/network/VerilogNamespace.cc b/network/VerilogNamespace.cc index 94cc2f3f..3b0d12e2 100644 --- a/network/VerilogNamespace.cc +++ b/network/VerilogNamespace.cc @@ -77,6 +77,7 @@ portVerilogName(const char *sta_name) return staToVerilog2(sta_name); } +//Unescaping logic should follow reverse of verilogToSta logic static string staToVerilog(const char *sta_name) { @@ -88,15 +89,14 @@ staToVerilog(const char *sta_name) for (const char *s = sta_name; *s ; s++) { char ch = s[0]; if (ch == verilog_escape) { + escaped = true; char next_ch = s[1]; if (next_ch == verilog_escape) { - escaped_name += ch; + //Only keep the character after "\" + //to remove the escape added by verilogToSta" escaped_name += next_ch; s++; } - else - // Skip escape. - escaped = true; } else { if ((!(isalnum(ch) || ch == '_'))) @@ -113,6 +113,8 @@ staToVerilog(const char *sta_name) return string(sta_name); } +//Unescaping logic should follow reverse of verilogToSta logic +//For "\\" handling, this should be like staToVerilog static string staToVerilog2(const char *sta_name) { @@ -126,15 +128,12 @@ staToVerilog2(const char *sta_name) for (const char *s = sta_name; *s ; s++) { char ch = s[0]; if (ch == verilog_escape) { + escaped = true; char next_ch = s[1]; if (next_ch == verilog_escape) { - escaped_name += ch; escaped_name += next_ch; s++; } - else - // Skip escape. - escaped = true; } else { bool is_brkt = (ch == bus_brkt_left || ch == bus_brkt_right); diff --git a/test/test_write_verilog_escape.tcl b/test/test_write_verilog_escape.tcl new file mode 100644 index 00000000..2a4d684d --- /dev/null +++ b/test/test_write_verilog_escape.tcl @@ -0,0 +1,11 @@ +# Check if "h1\x" and \Y[2:1] are correctly processed from input to output of Verilog + + +read_liberty gf180mcu_sram.lib.gz +read_liberty asap7_small.lib.gz + +read_verilog test_write_verilog_escape.v + +link_design multi_sink + +write_verilog test_write_verilog_escape_out.v diff --git a/test/test_write_verilog_escape.v b/test/test_write_verilog_escape.v new file mode 100644 index 00000000..6340d9b8 --- /dev/null +++ b/test/test_write_verilog_escape.v @@ -0,0 +1,14 @@ + +module \multi_sink (clk); + input clk; + wire \alu_adder_result_ex[0] ; + \hier_block \h1\x (.childclk(clk), .\Y[2:1] ({ \alu_adder_result_ex[0] , \alu_adder_result_ex[0] }) ); +endmodule // multi_sink + +module \hier_block (childclk, \Y[2:1] ); + input childclk; + output [1:0] \Y[2:1] ; + wire [1:0] \Y[2:1] ; + BUFx2_ASAP7_75t_R \ff0/name (.A(childclk)); +endmodule // hier_block1 + diff --git a/verilog/VerilogWriter.cc b/verilog/VerilogWriter.cc index dd856d7b..7bd3390f 100644 --- a/verilog/VerilogWriter.cc +++ b/verilog/VerilogWriter.cc @@ -388,7 +388,8 @@ VerilogWriter::writeInstBusPin(const Instance *inst, if (!first_port) fprintf(stream_, ",\n "); - fprintf(stream_, ".%s({", network_->name(port)); + string port_vname = portVerilogName(network_->name(port)); + fprintf(stream_, ".%s({", port_vname.c_str()); first_port = false; bool first_member = true; From 2d8605ebc9f266e58e1bb4d0880987ac16921c70 Mon Sep 17 00:00:00 2001 From: dsengupta0628 Date: Tue, 10 Feb 2026 16:51:00 +0000 Subject: [PATCH 2/7] Updated testing harness for the fix Signed-off-by: dsengupta0628 --- test/regression_vars.tcl | 1 + test/test_write_verilog_escape.ok | 17 +++++++++++++++++ test/test_write_verilog_escape.tcl | 13 ++++++++----- 3 files changed, 26 insertions(+), 5 deletions(-) create mode 100644 test/test_write_verilog_escape.ok diff --git a/test/regression_vars.tcl b/test/regression_vars.tcl index acf6906b..581b3f14 100644 --- a/test/regression_vars.tcl +++ b/test/regression_vars.tcl @@ -166,6 +166,7 @@ record_public_tests { report_json1 report_json2 suppress_msg + test_write_verilog_escape verilog_attribute verilog_specify } diff --git a/test/test_write_verilog_escape.ok b/test/test_write_verilog_escape.ok new file mode 100644 index 00000000..7c2442cb --- /dev/null +++ b/test/test_write_verilog_escape.ok @@ -0,0 +1,17 @@ +module multi_sink (clk); + input clk; + + wire \alu_adder_result_ex[0] ; + + hier_block \h1\x (.childclk(clk), + .\Y[2:1] ({\alu_adder_result_ex[0] , + \alu_adder_result_ex[0] })); +endmodule +module hier_block (childclk, + \Y[2:1] ); + input childclk; + output [1:0] \Y[2:1] ; + + + BUFx2_ASAP7_75t_R \ff0/name (.A(childclk)); +endmodule diff --git a/test/test_write_verilog_escape.tcl b/test/test_write_verilog_escape.tcl index 2a4d684d..cad6cce3 100644 --- a/test/test_write_verilog_escape.tcl +++ b/test/test_write_verilog_escape.tcl @@ -1,11 +1,14 @@ # Check if "h1\x" and \Y[2:1] are correctly processed from input to output of Verilog - - read_liberty gf180mcu_sram.lib.gz read_liberty asap7_small.lib.gz - read_verilog test_write_verilog_escape.v - link_design multi_sink - write_verilog test_write_verilog_escape_out.v +set input_file "test_write_verilog_escape_out.v" +set fp [open $input_file r] +while {[gets $fp line] >= 0} { + puts $line +} +close $fp +file delete "test_write_verilog_escape_out.v" + From 18ce25112d80a254683a1bb735a1791e79dc16d8 Mon Sep 17 00:00:00 2001 From: dsengupta0628 Date: Tue, 10 Feb 2026 16:53:30 +0000 Subject: [PATCH 3/7] Updated space in comments Signed-off-by: dsengupta0628 --- network/VerilogNamespace.cc | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/network/VerilogNamespace.cc b/network/VerilogNamespace.cc index 3b0d12e2..13574fa2 100644 --- a/network/VerilogNamespace.cc +++ b/network/VerilogNamespace.cc @@ -77,7 +77,7 @@ portVerilogName(const char *sta_name) return staToVerilog2(sta_name); } -//Unescaping logic should follow reverse of verilogToSta logic +// Unescaping logic should follow reverse of verilogToSta logic static string staToVerilog(const char *sta_name) { @@ -92,8 +92,8 @@ staToVerilog(const char *sta_name) escaped = true; char next_ch = s[1]; if (next_ch == verilog_escape) { - //Only keep the character after "\" - //to remove the escape added by verilogToSta" + // Only keep the character after "\" + // to remove the escape added by verilogToSta" escaped_name += next_ch; s++; } @@ -113,8 +113,8 @@ staToVerilog(const char *sta_name) return string(sta_name); } -//Unescaping logic should follow reverse of verilogToSta logic -//For "\\" handling, this should be like staToVerilog +// Unescaping logic should follow reverse of verilogToSta logic +// For "\\" handling, this should be like staToVerilog static string staToVerilog2(const char *sta_name) { From 1c1bef30d54727b253750719c3370a135c04be19 Mon Sep 17 00:00:00 2001 From: dsengupta0628 Date: Tue, 17 Feb 2026 20:19:17 +0000 Subject: [PATCH 4/7] test functionality with dollar sign, also need regoldening an openroad regression with another commit Signed-off-by: dsengupta0628 --- test/test_write_verilog_escape.ok | 1 + test/test_write_verilog_escape.v | 1 + 2 files changed, 2 insertions(+) diff --git a/test/test_write_verilog_escape.ok b/test/test_write_verilog_escape.ok index 7c2442cb..4906a851 100644 --- a/test/test_write_verilog_escape.ok +++ b/test/test_write_verilog_escape.ok @@ -13,5 +13,6 @@ module hier_block (childclk, output [1:0] \Y[2:1] ; + BUFx2_ASAP7_75t_R \abuf_$100 (.A(childclk)); BUFx2_ASAP7_75t_R \ff0/name (.A(childclk)); endmodule diff --git a/test/test_write_verilog_escape.v b/test/test_write_verilog_escape.v index 6340d9b8..e3abd466 100644 --- a/test/test_write_verilog_escape.v +++ b/test/test_write_verilog_escape.v @@ -9,6 +9,7 @@ module \hier_block (childclk, \Y[2:1] ); input childclk; output [1:0] \Y[2:1] ; wire [1:0] \Y[2:1] ; + BUFx2_ASAP7_75t_R \abuf_$100 (.A(childclk)); BUFx2_ASAP7_75t_R \ff0/name (.A(childclk)); endmodule // hier_block1 From db46579a392f5b88eb5fcc6dde74bceeb10ab4bd Mon Sep 17 00:00:00 2001 From: dsengupta0628 Date: Wed, 25 Feb 2026 20:14:59 +0000 Subject: [PATCH 5/7] resolve conflict Signed-off-by: dsengupta0628 --- network/VerilogNamespace.cc | 25 ------------------------- 1 file changed, 25 deletions(-) diff --git a/network/VerilogNamespace.cc b/network/VerilogNamespace.cc index 11144c63..905ba6ad 100644 --- a/network/VerilogNamespace.cc +++ b/network/VerilogNamespace.cc @@ -77,7 +77,6 @@ portVerilogName(const char *sta_name) return staToVerilog2(sta_name); } -// Unescaping logic should follow reverse of verilogToSta logic static string staToVerilog(const char *sta_name) { @@ -92,21 +91,9 @@ staToVerilog(const char *sta_name) escaped = true; char next_ch = s[1]; if (next_ch == verilog_escape) { -<<<<<<< HEAD - // Only keep the character after "\" - // to remove the escape added by verilogToSta" escaped_name += next_ch; s++; } -======= - escaped_name += ch; - escaped_name += next_ch; - s++; - } - else - // Skip escape. - escaped = true; ->>>>>>> master } else { if ((!(isalnum(ch) || ch == '_'))) @@ -123,8 +110,6 @@ staToVerilog(const char *sta_name) return string(sta_name); } -// Unescaping logic should follow reverse of verilogToSta logic -// For "\\" handling, this should be like staToVerilog static string staToVerilog2(const char *sta_name) { @@ -141,19 +126,9 @@ staToVerilog2(const char *sta_name) escaped = true; char next_ch = s[1]; if (next_ch == verilog_escape) { -<<<<<<< HEAD escaped_name += next_ch; s++; } -======= - escaped_name += ch; - escaped_name += next_ch; - s++; - } - else - // Skip escape. - escaped = true; ->>>>>>> master } else { bool is_brkt = (ch == bus_brkt_left || ch == bus_brkt_right); From cd6f564cafc6d908393b8cd0b37866608b7d46eb Mon Sep 17 00:00:00 2001 From: dsengupta0628 Date: Wed, 25 Feb 2026 20:33:15 +0000 Subject: [PATCH 6/7] Renamed tests to match prlx repo, updated test to repro error without my fix Signed-off-by: dsengupta0628 --- network/VerilogNamespace.cc | 8 ++++---- test/regression_vars.tcl | 2 +- ...ite_verilog_escape.ok => verilog_write_escape.ok} | 0 ...e_verilog_escape.tcl => verilog_write_escape.tcl} | 12 ++++++------ ...write_verilog_escape.v => verilog_write_escape.v} | 2 -- 5 files changed, 11 insertions(+), 13 deletions(-) rename test/{test_write_verilog_escape.ok => verilog_write_escape.ok} (100%) rename test/{test_write_verilog_escape.tcl => verilog_write_escape.tcl} (52%) rename test/{test_write_verilog_escape.v => verilog_write_escape.v} (99%) diff --git a/network/VerilogNamespace.cc b/network/VerilogNamespace.cc index 905ba6ad..3ab56a45 100644 --- a/network/VerilogNamespace.cc +++ b/network/VerilogNamespace.cc @@ -91,8 +91,8 @@ staToVerilog(const char *sta_name) escaped = true; char next_ch = s[1]; if (next_ch == verilog_escape) { - escaped_name += next_ch; - s++; + escaped_name += next_ch; + s++; } } else { @@ -126,8 +126,8 @@ staToVerilog2(const char *sta_name) escaped = true; char next_ch = s[1]; if (next_ch == verilog_escape) { - escaped_name += next_ch; - s++; + escaped_name += next_ch; + s++; } } else { diff --git a/test/regression_vars.tcl b/test/regression_vars.tcl index 9d4eff2a..ab1f6c62 100644 --- a/test/regression_vars.tcl +++ b/test/regression_vars.tcl @@ -163,9 +163,9 @@ record_public_tests { report_json1 report_json2 suppress_msg - test_write_verilog_escape verilog_attribute verilog_specify + verilog_write_escape } define_test_group fast [group_tests all] diff --git a/test/test_write_verilog_escape.ok b/test/verilog_write_escape.ok similarity index 100% rename from test/test_write_verilog_escape.ok rename to test/verilog_write_escape.ok diff --git a/test/test_write_verilog_escape.tcl b/test/verilog_write_escape.tcl similarity index 52% rename from test/test_write_verilog_escape.tcl rename to test/verilog_write_escape.tcl index cad6cce3..29ac26e8 100644 --- a/test/test_write_verilog_escape.tcl +++ b/test/verilog_write_escape.tcl @@ -1,14 +1,14 @@ # Check if "h1\x" and \Y[2:1] are correctly processed from input to output of Verilog read_liberty gf180mcu_sram.lib.gz read_liberty asap7_small.lib.gz -read_verilog test_write_verilog_escape.v +read_verilog verilog_write_escape.v link_design multi_sink -write_verilog test_write_verilog_escape_out.v -set input_file "test_write_verilog_escape_out.v" -set fp [open $input_file r] +set output_file "verilog_write_escape_out.v" +write_verilog $output_file +set fp [open $output_file r] while {[gets $fp line] >= 0} { puts $line } close $fp -file delete "test_write_verilog_escape_out.v" - +read_verilog $output_file +file delete $output_file diff --git a/test/test_write_verilog_escape.v b/test/verilog_write_escape.v similarity index 99% rename from test/test_write_verilog_escape.v rename to test/verilog_write_escape.v index e3abd466..aa7d99f3 100644 --- a/test/test_write_verilog_escape.v +++ b/test/verilog_write_escape.v @@ -1,4 +1,3 @@ - module \multi_sink (clk); input clk; wire \alu_adder_result_ex[0] ; @@ -12,4 +11,3 @@ module \hier_block (childclk, \Y[2:1] ); BUFx2_ASAP7_75t_R \abuf_$100 (.A(childclk)); BUFx2_ASAP7_75t_R \ff0/name (.A(childclk)); endmodule // hier_block1 - From 2d1a4f03e697378cd41b2c9a1da27d21e2b0c082 Mon Sep 17 00:00:00 2001 From: dsengupta0628 Date: Wed, 25 Feb 2026 20:39:11 +0000 Subject: [PATCH 7/7] fix indentation Signed-off-by: dsengupta0628 --- network/VerilogNamespace.cc | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/network/VerilogNamespace.cc b/network/VerilogNamespace.cc index 3ab56a45..f4bdea9a 100644 --- a/network/VerilogNamespace.cc +++ b/network/VerilogNamespace.cc @@ -91,8 +91,8 @@ staToVerilog(const char *sta_name) escaped = true; char next_ch = s[1]; if (next_ch == verilog_escape) { - escaped_name += next_ch; - s++; + escaped_name += next_ch; + s++; } } else { @@ -126,8 +126,8 @@ staToVerilog2(const char *sta_name) escaped = true; char next_ch = s[1]; if (next_ch == verilog_escape) { - escaped_name += next_ch; - s++; + escaped_name += next_ch; + s++; } } else {