diff --git a/liberty/test/liberty_busport_mem_iter.tcl b/liberty/test/liberty_busport_mem_iter.tcl
index 6538b5b4..7b17d2b0 100644
--- a/liberty/test/liberty_busport_mem_iter.tcl
+++ b/liberty/test/liberty_busport_mem_iter.tcl
@@ -242,6 +242,7 @@ set outfile [make_result_file liberty_busport_mem_iter_write.lib]
 sta::write_liberty fakeram45_64x7 $outfile
 
 # Read back
+# catch: roundtrip read-back of written liberty may produce parser warnings
 catch {
   read_liberty $outfile
 } msg
diff --git a/liberty/test/liberty_cell_classify_pgpin.tcl b/liberty/test/liberty_cell_classify_pgpin.tcl
index c99f3375..57772bc6 100644
--- a/liberty/test/liberty_cell_classify_pgpin.tcl
+++ b/liberty/test/liberty_cell_classify_pgpin.tcl
@@ -124,10 +124,12 @@ foreach cell_name {INV_X1 INV_X4 INV_X16 BUF_X1 BUF_X8 NAND2_X1 DFF_X1} {
     set port [$port_iter next]
     set dir [sta::liberty_port_direction $port]
     if {$dir == "input"} {
+      # catch: capacitance method argument format may differ across port types
       catch {
         set cap [$port capacitance [sta::cmd_corner] [sta::find_min_max "max"]]
         puts "$cell_name/[$port bus_name] cap(max)=$cap"
       }
+      # catch: capacitance method argument format may differ across port types
       catch {
         set cap [$port capacitance [sta::cmd_corner] [sta::find_min_max "min"]]
         puts "$cell_name/[$port bus_name] cap(min)=$cap"
diff --git a/liberty/test/liberty_cell_deep.tcl b/liberty/test/liberty_cell_deep.tcl
index e70d4306..7be52ff1 100644
--- a/liberty/test/liberty_cell_deep.tcl
+++ b/liberty/test/liberty_cell_deep.tcl
@@ -70,6 +70,7 @@ foreach cell_name {INV_X1 BUF_X1 DFF_X1 ANTENNA_X1 FILLCELL_X1} {
 # Leakage power queries
 ############################################################
 foreach cell_name {INV_X1 BUF_X1 DFF_X1 NAND2_X1 NOR2_X1 AOI21_X1} {
+  # catch: cell_leakage_power is not a supported get_property property
   catch {
     set cell [get_lib_cell NangateOpenCellLibrary/$cell_name]
     set lp [get_property $cell cell_leakage_power]
@@ -165,6 +166,7 @@ set outfile [make_result_file liberty_cell_deep_write.lib]
 sta::write_liberty NangateOpenCellLibrary $outfile
 
 # Read back and verify roundtrip (may have minor syntax issues)
+# catch: roundtrip read-back of written liberty may produce parser warnings
 catch {
   read_liberty $outfile
 } msg
diff --git a/liberty/test/liberty_clkgate_lvlshift.tcl b/liberty/test/liberty_clkgate_lvlshift.tcl
index 87f9751d..96fe7bf7 100644
--- a/liberty/test/liberty_clkgate_lvlshift.tcl
+++ b/liberty/test/liberty_clkgate_lvlshift.tcl
@@ -51,6 +51,7 @@ puts "--- clock gate cell queries ---"
 
 foreach cell_name {sky130_fd_sc_hd__dlclkp_1 sky130_fd_sc_hd__dlclkp_2
                    sky130_fd_sc_hd__dlclkp_4} {
+  # catch: clock gate cell variant may not exist in loaded library
   catch {
     set cell [get_lib_cell sky130_fd_sc_hd__tt_025C_1v80/$cell_name]
     if {$cell != "NULL" && $cell ne ""} {
@@ -97,6 +98,7 @@ foreach cell_name {sky130_fd_sc_hd__lpflow_lsbuf_lh_hl_isowell_tap_1
                    sky130_fd_sc_hd__lpflow_lsbuf_lh_isowell_tap_1
                    sky130_fd_sc_hd__lpflow_lsbuf_lh_isowell_tap_2
                    sky130_fd_sc_hd__lpflow_lsbuf_lh_isowell_tap_4} {
+  # catch: level shifter cell variant may not exist in loaded library
   catch {
     set cell [get_lib_cell sky130_fd_sc_hd__tt_025C_1v80/$cell_name]
     if {$cell != "NULL" && $cell ne ""} {
@@ -153,6 +155,7 @@ foreach cell_name {sky130_fd_sc_hd__inv_1 sky130_fd_sc_hd__buf_1
 ############################################################
 puts "--- clock gate timing arcs ---"
 
+# catch: dlclkp_1 cell may not exist in library
 catch {
   set cell [get_lib_cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__dlclkp_1]
   if {$cell != "NULL" && $cell ne ""} {
@@ -168,6 +171,7 @@ catch {
   }
 }
 
+# catch: sdlclkp_1 cell may not exist in library
 catch {
   set cell [get_lib_cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__sdlclkp_1]
   if {$cell != "NULL" && $cell ne ""} {
@@ -185,6 +189,7 @@ catch {
 ############################################################
 puts "--- level shifter timing arcs ---"
 
+# catch: lsbuf level shifter cell may not exist in library
 catch {
   set cell [get_lib_cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__lpflow_lsbuf_lh_hl_isowell_tap_1]
   if {$cell != "NULL" && $cell ne ""} {
diff --git a/liberty/test/liberty_equiv_cross_lib.tcl b/liberty/test/liberty_equiv_cross_lib.tcl
index 25588594..64f9fcc4 100644
--- a/liberty/test/liberty_equiv_cross_lib.tcl
+++ b/liberty/test/liberty_equiv_cross_lib.tcl
@@ -20,6 +20,7 @@ sta::make_equiv_cells $rvt_lib
 # Find equiv cells in ASAP7 RVT
 foreach cell_prefix {INVx BUFx} {
   foreach size {1 2 3 4 5 8 11 13 16} {
+    # catch: cell with specific size variant may not exist in library
     catch {
       set cell_name "${cell_prefix}${size}_ASAP7_75t_R"
       set cell [get_lib_cell asap7sc7p5t_INVBUF_RVT_FF_nldm_211120/$cell_name]
@@ -46,6 +47,7 @@ sta::make_equiv_cells $lvt_lib
 
 foreach cell_prefix {INVx BUFx} {
   foreach size {1 2 4 8} {
+    # catch: cell with specific size variant may not exist in library
     catch {
       set cell_name "${cell_prefix}${size}_ASAP7_75t_L"
       set cell [get_lib_cell asap7sc7p5t_INVBUF_LVT_FF_nldm_211120/$cell_name]
@@ -96,6 +98,7 @@ set seq_rvt_lib [lindex [get_libs asap7sc7p5t_SEQ_RVT_FF_nldm_220123] 0]
 sta::make_equiv_cells $seq_rvt_lib
 
 # Find equiv cells for DFF cells
+# catch: ASAP7 DFFHQNx1 cell may not exist
 catch {
   set dff [get_lib_cell asap7sc7p5t_SEQ_RVT_FF_nldm_220123/DFFHQNx1_ASAP7_75t_R]
   set equivs [sta::find_equiv_cells $dff]
@@ -110,6 +113,7 @@ catch {
 }
 
 # ICG equiv cells
+# catch: ASAP7 ICGx1 cell may not exist
 catch {
   set icg [get_lib_cell asap7sc7p5t_SEQ_RVT_FF_nldm_220123/ICGx1_ASAP7_75t_R]
   set equivs [sta::find_equiv_cells $icg]
@@ -121,6 +125,7 @@ catch {
 }
 
 # Latch equiv cells
+# catch: ASAP7 DLLx1 cell may not exist
 catch {
   set dll [get_lib_cell asap7sc7p5t_SEQ_RVT_FF_nldm_220123/DLLx1_ASAP7_75t_R]
   set equivs [sta::find_equiv_cells $dll]
@@ -132,6 +137,7 @@ catch {
 }
 
 # SDFF equiv cells
+# catch: ASAP7 SDFHQNx1 cell may not exist
 catch {
   set sdff [get_lib_cell asap7sc7p5t_SEQ_RVT_FF_nldm_220123/SDFHQNx1_ASAP7_75t_R]
   set equivs [sta::find_equiv_cells $sdff]
@@ -161,6 +167,7 @@ set sky_lib [lindex [get_libs sky130_fd_sc_hd__tt_025C_1v80] 0]
 sta::make_equiv_cells $sky_lib
 
 # Find equiv cells for Sky130 inverters
+# catch: find_equiv_cells may fail if equivalence mapping is not configured
 catch {
   set sky_inv [get_lib_cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__inv_1]
   set equivs [sta::find_equiv_cells $sky_inv]
@@ -175,6 +182,7 @@ catch {
 }
 
 # Find equiv for Sky130 DFF
+# catch: find_equiv_cells may fail if equivalence mapping is not configured
 catch {
   set sky_dff [get_lib_cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__dfxtp_1]
   set equivs [sta::find_equiv_cells $sky_dff]
diff --git a/liberty/test/liberty_leakage_power_deep.tcl b/liberty/test/liberty_leakage_power_deep.tcl
index e5005938..e7e4d60f 100644
--- a/liberty/test/liberty_leakage_power_deep.tcl
+++ b/liberty/test/liberty_leakage_power_deep.tcl
@@ -23,6 +23,7 @@ foreach cell_name {sky130_fd_sc_hd__inv_1 sky130_fd_sc_hd__inv_2
                    sky130_fd_sc_hd__a21o_1 sky130_fd_sc_hd__a21oi_1
                    sky130_fd_sc_hd__o21a_1 sky130_fd_sc_hd__o21ai_0
                    sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2i_1} {
+  # catch: cell may not exist or cell_leakage_power property is not supported
   catch {
     set cell [get_lib_cell sky130_fd_sc_hd__tt_025C_1v80/$cell_name]
     if {$cell != "NULL" && $cell ne ""} {
@@ -38,6 +39,7 @@ foreach cell_name {sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_2
                    sky130_fd_sc_hd__dlxtp_1 sky130_fd_sc_hd__dlxtn_1
                    sky130_fd_sc_hd__sdfxtp_1 sky130_fd_sc_hd__sdfrtp_1
                    sky130_fd_sc_hd__sdfstp_1 sky130_fd_sc_hd__dfbbp_1} {
+  # catch: cell may not exist or cell_leakage_power property is not supported
   catch {
     set cell [get_lib_cell sky130_fd_sc_hd__tt_025C_1v80/$cell_name]
     if {$cell != "NULL" && $cell ne ""} {
@@ -51,6 +53,7 @@ foreach cell_name {sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_2
 # Tristate cells
 foreach cell_name {sky130_fd_sc_hd__ebufn_1 sky130_fd_sc_hd__ebufn_2
                    sky130_fd_sc_hd__ebufn_4 sky130_fd_sc_hd__ebufn_8} {
+  # catch: cell may not exist or cell_leakage_power property is not supported
   catch {
     set cell [get_lib_cell sky130_fd_sc_hd__tt_025C_1v80/$cell_name]
     if {$cell != "NULL" && $cell ne ""} {
@@ -63,6 +66,7 @@ foreach cell_name {sky130_fd_sc_hd__ebufn_1 sky130_fd_sc_hd__ebufn_2
 # Clock gate cells
 foreach cell_name {sky130_fd_sc_hd__dlclkp_1 sky130_fd_sc_hd__dlclkp_2
                    sky130_fd_sc_hd__sdlclkp_1} {
+  # catch: cell may not exist or cell_leakage_power property is not supported
   catch {
     set cell [get_lib_cell sky130_fd_sc_hd__tt_025C_1v80/$cell_name]
     if {$cell != "NULL" && $cell ne ""} {
@@ -95,6 +99,7 @@ foreach cell_name {INV_X1 INV_X2 INV_X4 BUF_X1 BUF_X2 BUF_X4
                    DFF_X1 DFF_X2 DFFR_X1 DFFS_X1 DFFRS_X1
                    SDFF_X1 SDFFR_X1 SDFFRS_X1
                    TINV_X1 TLAT_X1 CLKGATETST_X1} {
+  # catch: cell_leakage_power property is not supported via get_property
   catch {
     set cell [get_lib_cell NangateOpenCellLibrary/$cell_name]
     if {$cell != "NULL" && $cell ne ""} {
@@ -133,6 +138,7 @@ read_liberty ../../test/ihp-sg13g2/sg13g2_stdcell_typ_1p20V_25C.lib
 
 foreach cell_name {sg13g2_inv_1 sg13g2_buf_1 sg13g2_nand2_1
                    sg13g2_nor2_1 sg13g2_and2_1 sg13g2_or2_1} {
+  # catch: IHP cell may not exist or may not have leakage data
   catch {
     set cell [get_lib_cell sg13g2_stdcell_typ_1p20V_25C/$cell_name]
     if {$cell != "NULL" && $cell ne ""} {
diff --git a/liberty/test/liberty_pgpin_voltage.tcl b/liberty/test/liberty_pgpin_voltage.tcl
index 1c0e6761..096dfc6a 100644
--- a/liberty/test/liberty_pgpin_voltage.tcl
+++ b/liberty/test/liberty_pgpin_voltage.tcl
@@ -89,6 +89,7 @@ foreach cell_name {sky130_fd_sc_hd__inv_1 sky130_fd_sc_hd__inv_2
                    sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2i_1
                    sky130_fd_sc_hd__mux4_1 sky130_fd_sc_hd__ha_1
                    sky130_fd_sc_hd__fa_1} {
+  # catch: cell may not exist or cell_leakage_power is not supported
   catch {
     set cell [get_lib_cell sky130_fd_sc_hd__tt_025C_1v80/$cell_name]
     if {$cell != "NULL" && $cell ne ""} {
@@ -109,6 +110,7 @@ foreach cell_name {sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_2
                    sky130_fd_sc_hd__sdfxtp_1 sky130_fd_sc_hd__sdfxtp_2
                    sky130_fd_sc_hd__sdfrtp_1 sky130_fd_sc_hd__sdfstp_1
                    sky130_fd_sc_hd__sdlclkp_1 sky130_fd_sc_hd__dlclkp_1} {
+  # catch: cell may not exist or cell_leakage_power is not supported
   catch {
     set cell [get_lib_cell sky130_fd_sc_hd__tt_025C_1v80/$cell_name]
     if {$cell != "NULL" && $cell ne ""} {
@@ -138,6 +140,7 @@ read_liberty ../../test/ihp-sg13g2/sg13g2_stdcell_typ_1p20V_25C.lib
 foreach cell_name {sg13g2_inv_1 sg13g2_buf_1 sg13g2_nand2_1
                    sg13g2_nor2_1 sg13g2_and2_1 sg13g2_or2_1
                    sg13g2_dfrbp_1 sg13g2_dlhq_1} {
+  # catch: IHP cell may not exist in loaded library
   catch {
     set cell [get_lib_cell sg13g2_stdcell_typ_1p20V_25C/$cell_name]
     if {$cell != "NULL" && $cell ne ""} {
@@ -188,6 +191,7 @@ set outfile [make_result_file liberty_pgpin_voltage_write.lib]
 sta::write_liberty sky130_fd_sc_hd__tt_025C_1v80 $outfile
 
 # Read back the written library to verify
+# catch: roundtrip read-back of written liberty may produce parser warnings
 catch {
   read_liberty $outfile
 } msg
diff --git a/liberty/test/liberty_power.tcl b/liberty/test/liberty_power.tcl
index 31b924b8..1773efa2 100644
--- a/liberty/test/liberty_power.tcl
+++ b/liberty/test/liberty_power.tcl
@@ -51,15 +51,19 @@ report_power -instances [get_cells {buf1 inv1 and1 or1 nand1 nor1 reg1 reg2 reg3
 ############################################################
 
 set inv_cell [get_lib_cell NangateOpenCellLibrary/INV_X1]
+# catch: cell_leakage_power is not a supported get_property property
 catch { puts "INV_X1 leakage_power: [get_property $inv_cell cell_leakage_power]" }
 
 set buf_cell [get_lib_cell NangateOpenCellLibrary/BUF_X1]
+# catch: cell_leakage_power is not a supported get_property property
 catch { puts "BUF_X1 leakage_power: [get_property $buf_cell cell_leakage_power]" }
 
 set dff_cell [get_lib_cell NangateOpenCellLibrary/DFF_X1]
+# catch: cell_leakage_power is not a supported get_property property
 catch { puts "DFF_X1 leakage_power: [get_property $dff_cell cell_leakage_power]" }
 
 set nand_cell [get_lib_cell NangateOpenCellLibrary/NAND2_X1]
+# catch: cell_leakage_power is not a supported get_property property
 catch { puts "NAND2_X1 leakage_power: [get_property $nand_cell cell_leakage_power]" }
 
 # Area property
@@ -76,6 +80,7 @@ puts "INV_X1 is_buffer: [get_property $inv_cell is_buffer]"
 puts "BUF_X1 is_buffer: [get_property $buf_cell is_buffer]"
 puts "BUF_X1 is_inverter: [get_property $buf_cell is_inverter]"
 puts "DFF_X1 is_buffer: [get_property $dff_cell is_buffer]"
+# catch: is_register is not a supported get_property property for LibertyCell
 catch { puts "DFF_X1 is_register: [get_property $dff_cell is_register]" }
 
 ############################################################
@@ -93,6 +98,7 @@ read_liberty ../../test/sky130hd/sky130hd_tt.lib
 
 # Query sky130 cell leakage powers
 set sky_inv [get_lib_cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__inv_1]
+# catch: cell_leakage_power is not a supported get_property property
 catch { puts "sky130 inv leakage: [get_property $sky_inv cell_leakage_power]" }
 puts "sky130 inv area: [get_property $sky_inv area]"
 
@@ -107,6 +113,7 @@ sta::write_liberty sky130_fd_sc_hd__tt_025C_1v80 $outfile2
 read_liberty ../../test/ihp-sg13g2/sg13g2_stdcell_typ_1p20V_25C.lib
 
 set ihp_inv [get_lib_cell sg13g2_stdcell_typ_1p20V_25C/sg13g2_inv_1]
+# catch: cell_leakage_power is not a supported get_property property
 catch { puts "IHP inv leakage: [get_property $ihp_inv cell_leakage_power]" }
 puts "IHP inv area: [get_property $ihp_inv area]"
 
@@ -117,6 +124,7 @@ puts "IHP inv area: [get_property $ihp_inv area]"
 read_liberty ../../test/asap7_ccsn.lib.gz
 
 set outfile3 [make_result_file liberty_power_write_ccsn.lib]
+# catch: CCSN library name may not match after loading
 catch {
   sta::write_liberty asap7_ccsn $outfile3
 }
@@ -128,5 +136,6 @@ catch {
 read_liberty ../../test/asap7/asap7sc7p5t_SEQ_RVT_FF_nldm_220123.lib
 
 set asap7_dff [get_lib_cell asap7sc7p5t_SEQ_RVT_FF_nldm_220123/DFFHQNx1_ASAP7_75t_R]
+# catch: cell_leakage_power is not a supported get_property property
 catch { puts "ASAP7 DFF leakage: [get_property $asap7_dff cell_leakage_power]" }
 puts "ASAP7 DFF area: [get_property $asap7_dff area]"
diff --git a/liberty/test/liberty_scan_signal_types.tcl b/liberty/test/liberty_scan_signal_types.tcl
index d8658e73..2f7e5507 100644
--- a/liberty/test/liberty_scan_signal_types.tcl
+++ b/liberty/test/liberty_scan_signal_types.tcl
@@ -15,6 +15,7 @@ puts "--- scan DFF cell queries ---"
 # sdfxtp cells are scan DFFs
 foreach cell_name {sky130_fd_sc_hd__sdfxtp_1 sky130_fd_sc_hd__sdfxtp_2
                    sky130_fd_sc_hd__sdfxtp_4} {
+  # catch: scan cell variant may not exist in this library version
   catch {
     set cell [get_lib_cell sky130_fd_sc_hd__tt_025C_1v80/$cell_name]
     if {$cell != "NULL" && $cell ne ""} {
@@ -49,6 +50,7 @@ foreach cell_name {sky130_fd_sc_hd__sdfxtp_1 sky130_fd_sc_hd__sdfxtp_2
 
 # sdfxbp cells are scan DFFs with complementary outputs
 foreach cell_name {sky130_fd_sc_hd__sdfxbp_1 sky130_fd_sc_hd__sdfxbp_2} {
+  # catch: scan cell variant may not exist in this library version
   catch {
     set cell [get_lib_cell sky130_fd_sc_hd__tt_025C_1v80/$cell_name]
     if {$cell != "NULL" && $cell ne ""} {
@@ -80,6 +82,7 @@ foreach cell_name {sky130_fd_sc_hd__sdfxbp_1 sky130_fd_sc_hd__sdfxbp_2} {
 # sdfrtp cells are scan DFFs with async reset
 foreach cell_name {sky130_fd_sc_hd__sdfrtp_1 sky130_fd_sc_hd__sdfrtp_2
                    sky130_fd_sc_hd__sdfrtp_4} {
+  # catch: scan cell variant may not exist in this library version
   catch {
     set cell [get_lib_cell sky130_fd_sc_hd__tt_025C_1v80/$cell_name]
     if {$cell != "NULL" && $cell ne ""} {
@@ -111,6 +114,7 @@ foreach cell_name {sky130_fd_sc_hd__sdfrtp_1 sky130_fd_sc_hd__sdfrtp_2
 # sdfstp cells are scan DFFs with async set
 foreach cell_name {sky130_fd_sc_hd__sdfstp_1 sky130_fd_sc_hd__sdfstp_2
                    sky130_fd_sc_hd__sdfstp_4} {
+  # catch: scan cell variant may not exist in this library version
   catch {
     set cell [get_lib_cell sky130_fd_sc_hd__tt_025C_1v80/$cell_name]
     if {$cell != "NULL" && $cell ne ""} {
@@ -139,6 +143,7 @@ puts "--- scan DFF timing arcs ---"
 
 foreach cell_name {sky130_fd_sc_hd__sdfxtp_1 sky130_fd_sc_hd__sdfrtp_1
                    sky130_fd_sc_hd__sdfstp_1} {
+  # catch: cell may not exist; timing arc iteration may fail
   catch {
     set cell [get_lib_cell sky130_fd_sc_hd__tt_025C_1v80/$cell_name]
     if {$cell != "NULL" && $cell ne ""} {
@@ -160,6 +165,7 @@ read_liberty ../../test/nangate45/Nangate45_typ.lib
 
 # Nangate SDFF cells
 foreach cell_name {SDFF_X1 SDFF_X2 SDFFR_X1 SDFFS_X1 SDFFRS_X1} {
+  # catch: SDFF cell variant may not exist in NangateOpenCellLibrary
   catch {
     set cell [get_lib_cell NangateOpenCellLibrary/$cell_name]
     if {$cell != "NULL" && $cell ne ""} {
@@ -181,6 +187,7 @@ foreach cell_name {SDFF_X1 SDFF_X2 SDFFR_X1 SDFFS_X1 SDFFRS_X1} {
 }
 
 # Nangate CLKGATETST cell (clock gate test)
+# catch: CLKGATETST_X1 may not have test_cell attribute
 catch {
   set cell [get_lib_cell NangateOpenCellLibrary/CLKGATETST_X1]
   if {$cell != "NULL" && $cell ne ""} {
@@ -201,6 +208,7 @@ catch {
 read_liberty ../../test/asap7/asap7sc7p5t_SEQ_RVT_FF_nldm_220123.lib
 
 # ASAP7 ICG cell has statetable (exercises clock gate paths)
+# catch: ASAP7 ICG cell may not exist in loaded library
 catch {
   set cell [get_lib_cell asap7sc7p5t_SEQ_RVT_FF_nldm_220123/ICGx1_ASAP7_75t_R]
   if {$cell != "NULL" && $cell ne ""} {
@@ -215,6 +223,7 @@ catch {
 # ASAP7 DFFs with scan
 foreach cell_name {DFFHQNx1_ASAP7_75t_R DFFHQx1_ASAP7_75t_R
                    DFFHQNx2_ASAP7_75t_R DFFHQx2_ASAP7_75t_R} {
+  # catch: ASAP7 DFF cell name variant may not match
   catch {
     set cell [get_lib_cell asap7sc7p5t_SEQ_RVT_FF_nldm_220123/$cell_name]
     if {$cell != "NULL" && $cell ne ""} {
diff --git a/liberty/test/liberty_seq_scan_bus.tcl b/liberty/test/liberty_seq_scan_bus.tcl
index 69ed4fb2..129d40be 100644
--- a/liberty/test/liberty_seq_scan_bus.tcl
+++ b/liberty/test/liberty_seq_scan_bus.tcl
@@ -41,6 +41,7 @@ puts "sdfxbp_1 area = $area2"
 ############################################################
 foreach cell_name {sky130_fd_sc_hd__ebufn_1 sky130_fd_sc_hd__ebufn_2
                    sky130_fd_sc_hd__ebufn_4 sky130_fd_sc_hd__ebufn_8} {
+  # catch: sky130 tristate cell may not exist or tristate_enable may be unsupported
   catch {
     set cell [get_lib_cell sky130_fd_sc_hd__tt_025C_1v80/$cell_name]
     set area [get_property $cell area]
@@ -86,6 +87,7 @@ foreach cell_name {sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfstp_1
 foreach cell_name {sky130_fd_sc_hd__inv_1 sky130_fd_sc_hd__buf_1
                    sky130_fd_sc_hd__nand2_1 sky130_fd_sc_hd__nor2_1
                    sky130_fd_sc_hd__dfxtp_1} {
+  # catch: cell_leakage_power is not a supported get_property property
   catch {
     set cell [get_lib_cell sky130_fd_sc_hd__tt_025C_1v80/$cell_name]
     if {$cell != "NULL" && $cell ne ""} {
@@ -143,6 +145,7 @@ foreach cell_name {INV_X1 INV_X2 INV_X4 BUF_X1 BUF_X2 BUF_X4
 # Timing arc set queries (exercises makeTimingArcMap paths)
 ############################################################
 foreach cell_name {DFF_X1 DFFR_X1 DFFS_X1 DFFRS_X1} {
+  # catch: cell may not exist in this library version
   catch {
     set cell [get_lib_cell NangateOpenCellLibrary/$cell_name]
     if {$cell != "NULL" && $cell ne ""} {
@@ -165,6 +168,7 @@ foreach cell_name {DFF_X1 DFFR_X1 DFFS_X1 DFFRS_X1} {
 read_liberty ../../test/nangate45/fakeram45_64x7.lib
 
 # Query bus ports
+# catch: bus port iteration format may differ across library versions
 catch {
   set cell [get_lib_cell fakeram45_64x7/fakeram45_64x7]
   if {$cell != "NULL" && $cell ne ""} {
@@ -198,6 +202,7 @@ catch {
 read_liberty ../../test/asap7/asap7sc7p5t_SEQ_RVT_FF_nldm_220123.lib
 
 # Query ASAP7 latch cells
+# catch: ASAP7 DLLx1 latch cell may not exist
 catch {
   set cell [get_lib_cell asap7sc7p5t_SEQ_RVT_FF_nldm_220123/DLLx1_ASAP7_75t_R]
   if {$cell != "NULL" && $cell ne ""} {
@@ -211,6 +216,7 @@ catch {
 }
 
 # Query ICG (Integrated Clock Gate) cell with statetable
+# catch: ASAP7 ICGx1 clock gate cell may not exist
 catch {
   set cell [get_lib_cell asap7sc7p5t_SEQ_RVT_FF_nldm_220123/ICGx1_ASAP7_75t_R]
   if {$cell != "NULL" && $cell ne ""} {
diff --git a/liberty/test/liberty_writer_roundtrip.tcl b/liberty/test/liberty_writer_roundtrip.tcl
index 044df57b..b0e0126d 100644
--- a/liberty/test/liberty_writer_roundtrip.tcl
+++ b/liberty/test/liberty_writer_roundtrip.tcl
@@ -16,6 +16,7 @@ set outfile1 [make_result_file liberty_writer_rt1.lib]
 sta::write_liberty $lib $outfile1
 
 # Read back the written liberty (may have warnings/errors - that's ok)
+# catch: roundtrip read-back of written liberty may produce parser warnings
 catch {
   read_liberty $outfile1
 } msg
@@ -29,13 +30,14 @@ if {$msg ne ""} {
 ############################################################
 read_liberty ../../test/sky130hd/sky130hd_tt.lib
 
+# catch: library name may not match exactly after loading
 catch {
   set sky_lib [sta::find_liberty "sky130_fd_sc_hd__tt_025C_1v80"]
   if {$sky_lib ne ""} {
     set outfile3 [make_result_file liberty_writer_rt_sky.lib]
     sta::write_liberty $sky_lib $outfile3
 
-    # Read back Sky130 written liberty
+    # catch: roundtrip read-back of written liberty may produce parser warnings
     catch {
       read_liberty $outfile3
     }
@@ -47,6 +49,7 @@ catch {
 ############################################################
 read_liberty ../../test/ihp-sg13g2/sg13g2_stdcell_typ_1p20V_25C.lib
 
+# catch: IHP library name may not match exactly
 catch {
   set ihp_lib [sta::find_liberty "sg13g2_stdcell"]
   if {$ihp_lib ne ""} {
@@ -65,6 +68,7 @@ catch {
 foreach cell_name {INV_X1 BUF_X1 NAND2_X1 NOR2_X1 AND2_X1 OR2_X1
                    XOR2_X1 XNOR2_X1 AOI21_X1 OAI21_X1 MUX2_X1
                    FA_X1 HA_X1} {
+  # catch: some cells (e.g. FA_X1, HA_X1) may not exist in all library versions
   catch {
     set cell [get_lib_cell NangateOpenCellLibrary/$cell_name]
     set arc_sets [$cell timing_arc_sets]
@@ -132,6 +136,7 @@ foreach cell_name {TLAT_X1} {
 ############################################################
 read_liberty ../../test/asap7/asap7sc7p5t_SEQ_RVT_FF_nldm_220123.lib
 
+# catch: ASAP7 library name may not match exactly
 catch {
   set asap7_lib [sta::find_liberty "asap7sc7p5t_SEQ_RVT_FF_nldm_220123"]
   if {$asap7_lib ne ""} {
diff --git a/network/test/network_modify.tcl b/network/test/network_modify.tcl
index 18c73a1a..c6b2da44 100644
--- a/network/test/network_modify.tcl
+++ b/network/test/network_modify.tcl
@@ -79,6 +79,7 @@ puts "--- delete_instance new_buf ---"
 delete_instance new_buf
 
 puts "--- verify new_buf removed ---"
+# catch: intentionally verifying get_cells fails after instance deletion
 set rc5 [catch {get_cells new_buf} msg]
 puts "get_cells new_buf after delete: $msg"
 
diff --git a/parasitics/test/parasitics_annotation_query.tcl b/parasitics/test/parasitics_annotation_query.tcl
index 1feb496a..41bf9e1a 100644
--- a/parasitics/test/parasitics_annotation_query.tcl
+++ b/parasitics/test/parasitics_annotation_query.tcl
@@ -102,12 +102,14 @@ puts "elmore r1/Q -> u1/A fall max: $elm_r1f"
 set elm_r2 [sta::find_elmore [get_pins r2/Q] [get_pins u2/B] "rise" "max"]
 puts "elmore r2/Q -> u2/B rise max: $elm_r2"
 
+# catch: sta::find_elmore with port name 'out' via get_pins may fail (use get_port_pin for ports)
 catch {
   set elm_r3 [sta::find_elmore [get_pins r3/Q] [get_pins out] "rise" "max"]
   puts "elmore r3/Q -> out rise max: $elm_r3"
 } msg
 
 # Query min as well
+# catch: sta::find_elmore with port name 'out' via get_pins may fail (use get_port_pin for ports)
 catch {
   set elm_r3_min [sta::find_elmore [get_pins r3/Q] [get_pins out] "rise" "min"]
   puts "elmore r3/Q -> out rise min: $elm_r3_min"
@@ -201,6 +203,7 @@ puts "elmore u1/Y->u2/A after SPEF: $elm_u1_spef"
 set elm_r1_spef [sta::find_elmore [get_pins r1/Q] [get_pins u1/A] "rise" "max"]
 puts "elmore r1/Q->u1/A after SPEF: $elm_r1_spef"
 
+# catch: sta::find_elmore with port name 'out' via get_pins may fail (use get_port_pin for ports)
 catch {
   set elm_r3_spef [sta::find_elmore [get_pins r3/Q] [get_pins out] "rise" "max"]
   puts "elmore r3/Q->out after SPEF: $elm_r3_spef"
diff --git a/parasitics/test/parasitics_pi_pole_residue.tcl b/parasitics/test/parasitics_pi_pole_residue.tcl
index 367500ad..3a02d446 100644
--- a/parasitics/test/parasitics_pi_pole_residue.tcl
+++ b/parasitics/test/parasitics_pi_pole_residue.tcl
@@ -43,30 +43,35 @@ report_checks -fields {slew cap input_pins nets fanout}
 #---------------------------------------------------------------
 puts "--- Test 2: query pi_pole_residue ---"
 
+# catch: sta::find_pi_pole_residue is not exposed as Tcl command
 catch {
   set ppr [sta::find_pi_pole_residue [get_pins u1/Y] "rise" "max"]
   puts "u1/Y rise max pi_pole_residue: $ppr"
 } msg
 puts "find_pi_pole_residue u1/Y rise max: done ($msg)"
 
+# catch: sta::find_pi_pole_residue is not exposed as Tcl command
 catch {
   set ppr [sta::find_pi_pole_residue [get_pins u1/Y] "fall" "max"]
   puts "u1/Y fall max pi_pole_residue: $ppr"
 } msg
 puts "find_pi_pole_residue u1/Y fall max: done ($msg)"
 
+# catch: sta::find_pi_pole_residue is not exposed as Tcl command
 catch {
   set ppr [sta::find_pi_pole_residue [get_pins u2/Y] "rise" "max"]
   puts "u2/Y rise max pi_pole_residue: $ppr"
 } msg
 puts "find_pi_pole_residue u2/Y rise max: done ($msg)"
 
+# catch: sta::find_pi_pole_residue is not exposed as Tcl command
 catch {
   set ppr [sta::find_pi_pole_residue [get_pins r1/Q] "rise" "max"]
   puts "r1/Q rise max pi_pole_residue: $ppr"
 } msg
 puts "find_pi_pole_residue r1/Q rise max: done ($msg)"
 
+# catch: sta::find_pi_pole_residue is not exposed as Tcl command
 catch {
   set ppr [sta::find_pi_pole_residue [get_pins r2/Q] "fall" "min"]
   puts "r2/Q fall min pi_pole_residue: $ppr"
diff --git a/sdc/test/sdc_clock_operations.tcl b/sdc/test/sdc_clock_operations.tcl
index 25abb53f..d17ca6cd 100644
--- a/sdc/test/sdc_clock_operations.tcl
+++ b/sdc/test/sdc_clock_operations.tcl
@@ -55,6 +55,7 @@ create_generated_clock -name gclk_edge -source [get_ports clk1] -edges {1 3 5} [
 report_checks
 
 puts "--- generated clock invert ---"
+# catch: -invert with -divide_by 1 and -add may conflict with existing clock on this pin
 catch {
   create_generated_clock -name gclk_inv -source [get_ports clk1] -divide_by 1 -invert [get_pins reg1/Q] -add
   report_checks
diff --git a/sdc/test/sdc_delay_borrow_group.tcl b/sdc/test/sdc_delay_borrow_group.tcl
index 5baefae1..e7f91b59 100644
--- a/sdc/test/sdc_delay_borrow_group.tcl
+++ b/sdc/test/sdc_delay_borrow_group.tcl
@@ -159,6 +159,7 @@ set_min_delay -from [get_ports in3] -to [get_ports out2] 0.5
 ############################################################
 # Min fanout limit (covers setMinFanout through set_min_fanout if available)
 ############################################################
+# catch: set_min_fanout is not a valid SDC command in OpenSTA
 catch {
   set_min_fanout 2 [current_design]
 }
diff --git a/sdc/test/sdc_design_rules_limits.tcl b/sdc/test/sdc_design_rules_limits.tcl
index b04750b2..b34e600c 100644
--- a/sdc/test/sdc_design_rules_limits.tcl
+++ b/sdc/test/sdc_design_rules_limits.tcl
@@ -68,6 +68,7 @@ set_max_fanout 20 [current_design]
 set_max_fanout 10 [get_ports in1]
 set_max_fanout 15 [get_ports in2]
 
+# catch: set_max_fanout on a liberty cell object is not supported
 catch {
   # Cell-level fanout limit
   set_max_fanout 8 [get_lib_cells NangateOpenCellLibrary/INV_X1]
diff --git a/sdc/test/sdc_genclk_advanced.tcl b/sdc/test/sdc_genclk_advanced.tcl
index 72842fba..8c5dca39 100644
--- a/sdc/test/sdc_genclk_advanced.tcl
+++ b/sdc/test/sdc_genclk_advanced.tcl
@@ -47,6 +47,7 @@ create_generated_clock -name gclk_mul2 -source [get_ports clk1] -multiply_by 2 [
 ############################################################
 
 # Edge-based generated clock
+# catch: -edges with -add may conflict with existing generated clock on this pin
 catch {
   create_generated_clock -name gclk_edge -source [get_ports clk1] -edges {1 3 5} [get_pins reg1/Q] -add
 }
@@ -55,6 +56,7 @@ catch {
 # Generated clock - edge shift
 ############################################################
 
+# catch: -edge_shift with -edges and -add is an unsupported option combination
 catch {
   create_generated_clock -name gclk_shift -source [get_ports clk2] -edges {1 3 5} -edge_shift {0.0 0.5 1.0} [get_pins reg3/Q] -add
 }
diff --git a/sdc/test/sdc_port_delay_advanced.tcl b/sdc/test/sdc_port_delay_advanced.tcl
index 21997ada..73718e0b 100644
--- a/sdc/test/sdc_port_delay_advanced.tcl
+++ b/sdc/test/sdc_port_delay_advanced.tcl
@@ -134,6 +134,7 @@ set_data_check -from [get_pins reg1/Q] -to [get_pins reg2/D] -setup 0.5
 
 set_data_check -from [get_pins reg1/Q] -to [get_pins reg2/D] -hold 0.3
 
+# catch: -clock_fall is not a valid option for set_data_check
 catch {
   set_data_check -from [get_pins reg1/Q] -to [get_pins reg2/D] -setup 0.6 -clock_fall
 }
diff --git a/sdc/test/sdc_variables.tcl b/sdc/test/sdc_variables.tcl
index 663cd074..1f3d0c1f 100644
--- a/sdc/test/sdc_variables.tcl
+++ b/sdc/test/sdc_variables.tcl
@@ -144,6 +144,7 @@ set val $::sta_propagate_gated_clock_enable
 # POCV enabled (may require SSTA compilation, use catch)
 ############################################################
 
+# catch: POCV variables may not exist if SSTA is not compiled in
 catch {
   set ::sta_pocv_enabled 1
   set ::sta_pocv_enabled 0
diff --git a/search/test/search_limits_verbose.tcl b/search/test/search_limits_verbose.tcl
index a3e83d25..7564fb67 100644
--- a/search/test/search_limits_verbose.tcl
+++ b/search/test/search_limits_verbose.tcl
@@ -211,14 +211,17 @@ check_setup -verbose -loops
 # max_slew_check_slack_limit / max_cap_check_slack_limit / etc.
 ############################################################
 puts "--- slack/limit ratios ---"
+# catch: max_slew_check_slack_limit is not exposed as Tcl command
 catch {
   set sr [max_slew_check_slack_limit]
   puts "slew slack/limit: $sr"
 }
+# catch: max_capacitance_check_slack_limit is not exposed as Tcl command
 catch {
   set cr [max_capacitance_check_slack_limit]
   puts "cap slack/limit: $cr"
 }
+# catch: max_fanout_check_slack_limit is not exposed as Tcl command
 catch {
   set fr [max_fanout_check_slack_limit]
   puts "fanout slack/limit: $fr"
diff --git a/search/test/search_multiclock.tcl b/search/test/search_multiclock.tcl
index 25da8f3b..b0ff22dc 100644
--- a/search/test/search_multiclock.tcl
+++ b/search/test/search_multiclock.tcl
@@ -41,6 +41,7 @@ puts "--- group_path with -weight ---"
 group_path -name weighted_group -from [get_ports in1] -weight 2.0
 
 puts "--- group_path with -default ---"
+# catch: group_path -name and -default are mutually exclusive; -default also requires path args
 catch { group_path -name default_group -default }
 
 puts "--- report_checks with -group filter ---"
diff --git a/search/test/search_multicorner_analysis.tcl b/search/test/search_multicorner_analysis.tcl
index 0734d6d9..8062753e 100644
--- a/search/test/search_multicorner_analysis.tcl
+++ b/search/test/search_multicorner_analysis.tcl
@@ -124,6 +124,7 @@ puts "--- set_max_area ---"
 set_max_area 1000
 
 puts "--- isClock / isPropagatedClock queries ---"
+# catch: sta::is_clock_pin is not exposed as Tcl command
 catch {
   set clk_pin [get_pins ckbuf/Z]
   puts "isClock ckbuf/Z: [sta::is_clock_pin $clk_pin]"
diff --git a/search/test/search_network_edit_deep.tcl b/search/test/search_network_edit_deep.tcl
index 04edc534..c01d5a8e 100644
--- a/search/test/search_network_edit_deep.tcl
+++ b/search/test/search_network_edit_deep.tcl
@@ -50,6 +50,7 @@ puts "--- slow_drivers 5 ---"
 set slow5 [sta::slow_drivers 5]
 puts "slow_drivers(5): [llength $slow5]"
 foreach s $slow5 {
+  # catch: slow_drivers may return objects that don't support get_full_name
   catch { puts "  [get_full_name $s]" }
 }
 
diff --git a/search/test/search_path_enum_groups.tcl b/search/test/search_path_enum_groups.tcl
index 8c88d865..bde0a8ab 100644
--- a/search/test/search_path_enum_groups.tcl
+++ b/search/test/search_path_enum_groups.tcl
@@ -79,6 +79,7 @@ puts "input_paths is group: [sta::is_path_group_name input_paths]"
 puts "nonexistent is group: [sta::is_path_group_name nonexistent_group]"
 
 puts "--- group_path -default ---"
+# catch: group_path -name and -default are mutually exclusive; -default also requires path args
 catch {
   group_path -name default_group -default
   report_checks -path_delay max
diff --git a/search/test/search_port_pin_properties.tcl b/search/test/search_port_pin_properties.tcl
index 4fb34d84..a173046a 100644
--- a/search/test/search_port_pin_properties.tcl
+++ b/search/test/search_port_pin_properties.tcl
@@ -102,7 +102,7 @@ puts "--- Net properties ---"
 set net1 [get_nets n1]
 puts "n1 name: [get_property $net1 name]"
 puts "n1 full_name: [get_property $net1 full_name]"
-# Test unknown property error for net
+# catch: intentionally testing error for nonexistent net property
 catch {
   get_property $net1 nonexistent_net_property
 } net_err
@@ -137,6 +137,7 @@ puts "DFF_X1 is_buffer: [get_property $dff_cell is_buffer]"
 set dff_lib [get_property $dff_cell library]
 puts "DFF_X1 library: [get_name $dff_lib]"
 puts "DFF_X1 area: [get_property $dff_cell area]"
+# catch: 'cell_leakage_power' is not a supported get_property property
 catch { puts "DFF_X1 leakage: [get_property $dff_cell cell_leakage_power]" }
 
 puts "--- LibertyPort properties ---"
@@ -146,9 +147,11 @@ puts "DFF_X1/D full_name: [get_property $lp_d full_name]"
 puts "DFF_X1/D direction: [get_property $lp_d direction]"
 puts "DFF_X1/D capacitance: [get_property $lp_d capacitance]"
 puts "DFF_X1/D is_clock: [get_property $lp_d is_clock]"
+# catch: 'is_register_clock' property may not be valid for data pins
 catch { puts "DFF_X1/D is_register_clock: [get_property $lp_d is_register_clock]" }
 set lp_ck [get_lib_pins NangateOpenCellLibrary/DFF_X1/CK]
 puts "DFF_X1/CK is_clock: [get_property $lp_ck is_clock]"
+# catch: 'is_register_clock' property may not be valid for clock pins
 catch { puts "DFF_X1/CK is_register_clock: [get_property $lp_ck is_register_clock]" }
 
 puts "--- Library properties ---"
@@ -213,10 +216,12 @@ foreach pe $path_ends2 {
 }
 
 puts "--- Unknown property error handling ---"
+# catch: intentionally testing error for nonexistent port property
 catch {
   get_property $in_port nonexistent_property
 } result
 puts "Unknown port property caught: [string range $result 0 30]"
+# catch: intentionally testing error for nonexistent pin property
 catch {
   get_property $dpin nonexistent_property
 } result2
diff --git a/search/test/search_power_activity.tcl b/search/test/search_power_activity.tcl
index 436ce250..bd1e3c25 100644
--- a/search/test/search_power_activity.tcl
+++ b/search/test/search_power_activity.tcl
@@ -27,14 +27,17 @@ puts "--- report_power -digits 6 ---"
 report_power -digits 6
 
 puts "--- Pin activity ---"
+# catch: sta::pin_activity is not exposed as Tcl command
 catch {
   set act1 [sta::pin_activity [get_pins and1/ZN]]
   puts "and1/ZN activity: $act1"
 }
+# catch: sta::pin_activity is not exposed as Tcl command
 catch {
   set act2 [sta::pin_activity [get_pins reg1/Q]]
   puts "reg1/Q activity: $act2"
 }
+# catch: sta::pin_activity is not exposed as Tcl command
 catch {
   set act3 [sta::pin_activity [get_pins buf1/Z]]
   puts "buf1/Z activity: $act3"
@@ -59,6 +62,7 @@ set_propagated_clock [get_clocks clk]
 report_power
 
 puts "--- isClock queries ---"
+# catch: ckbuf instance may not exist in this design
 catch {
   puts "ckbuf/A is_clock: [sta::is_clock_pin [get_pins ckbuf/A]]"
   puts "ckbuf/Z is_clock: [sta::is_clock_pin [get_pins ckbuf/Z]]"
diff --git a/search/test/search_property_extra.tcl b/search/test/search_property_extra.tcl
index 10f1459f..7b8feabe 100644
--- a/search/test/search_property_extra.tcl
+++ b/search/test/search_property_extra.tcl
@@ -46,9 +46,12 @@ set lport [get_lib_pins NangateOpenCellLibrary/AND2_X1/ZN]
 puts "lport name: [get_property $lport name]"
 puts "lport full_name: [get_property $lport full_name]"
 puts "lport direction: [get_property $lport direction]"
+# catch: 'function' is not a get_property property (use $port function method instead)
 catch { puts "lport function: [get_property $lport function]" }
 puts "lport capacitance: [get_property $lport capacitance]"
+# catch: 'max_capacitance' is not a supported get_property property
 catch { puts "lport max_capacitance: [get_property $lport max_capacitance]" }
+# catch: 'max_transition' is not a supported get_property property
 catch { puts "lport max_transition: [get_property $lport max_transition]" }
 puts "lport is_register_clock: [get_property $lport is_register_clock]"
 puts "lport is_clock: [get_property $lport is_clock]"
@@ -61,6 +64,7 @@ puts "and is_buffer: [get_property $and_cell is_buffer]"
 set dff_cell [get_lib_cells NangateOpenCellLibrary/DFF_X1]
 puts "dff is_buffer: [get_property $dff_cell is_buffer]"
 puts "dff area: [get_property $dff_cell area]"
+# catch: 'cell_leakage_power' is not a supported get_property property
 catch { puts "dff cell_leakage_power: [get_property $dff_cell cell_leakage_power]" }
 
 puts "--- LibertyLibrary properties ---"
diff --git a/search/test/search_property_libport_deep.tcl b/search/test/search_property_libport_deep.tcl
index ef01cdfd..fa86fc69 100644
--- a/search/test/search_property_libport_deep.tcl
+++ b/search/test/search_property_libport_deep.tcl
@@ -129,9 +129,11 @@ puts "reg1 is_memory: [get_property $reg_inst is_memory]"
 puts "--- LibertyCell area and leakage ---"
 set dff_cell [get_lib_cells NangateOpenCellLibrary/DFF_X1]
 puts "DFF_X1 area: [get_property $dff_cell area]"
+# catch: 'cell_leakage_power' is not a supported get_property property
 catch { puts "DFF_X1 cell_leakage_power: [get_property $dff_cell cell_leakage_power]" }
 set buf_cell [get_lib_cells NangateOpenCellLibrary/BUF_X1]
 puts "BUF_X1 area: [get_property $buf_cell area]"
+# catch: 'cell_leakage_power' is not a supported get_property property
 catch { puts "BUF_X1 cell_leakage_power: [get_property $buf_cell cell_leakage_power]" }
 set inv_cell [get_lib_cells NangateOpenCellLibrary/INV_X1]
 puts "INV_X1 area: [get_property $inv_cell area]"
@@ -155,6 +157,7 @@ puts "--- find_timing_paths with group_path ---"
 set paths [find_timing_paths -path_delay max -group_path_count 20 -endpoint_path_count 10]
 puts "Found [llength $paths] paths with groups"
 foreach pe $paths {
+  # catch: PathEnd does not have a path_group method
   catch {
     set pg [$pe path_group]
     puts "  [get_full_name [$pe pin]] group=[$pg name] slack=[$pe slack]"
@@ -165,6 +168,7 @@ puts "--- find_timing_paths with min paths and groups ---"
 set paths_min [find_timing_paths -path_delay min -group_path_count 20 -endpoint_path_count 10]
 puts "Found [llength $paths_min] min paths with groups"
 foreach pe $paths_min {
+  # catch: PathEnd does not have a path_group method
   catch {
     set pg [$pe path_group]
     puts "  [get_full_name [$pe pin]] group=[$pg name] slack=[$pe slack]"
@@ -232,13 +236,18 @@ puts "DFF_X1/CK direction: [get_property $dff_ck_lp direction]"
 # Unknown property error handling for various types
 ############################################################
 puts "--- Unknown property errors ---"
+# catch: intentionally testing error for nonexistent property on LibertyPort
 catch { get_property [get_lib_pins NangateOpenCellLibrary/BUF_X1/Z] nonexistent_prop } err1
 puts "LibertyPort unknown: [string range $err1 0 40]"
+# catch: intentionally testing error for nonexistent property on Instance
 catch { get_property [get_cells reg1] nonexistent_prop } err2
 puts "Instance unknown: [string range $err2 0 40]"
+# catch: intentionally testing error for nonexistent property on Clock
 catch { get_property [get_clocks clk] nonexistent_prop } err3
 puts "Clock unknown: [string range $err3 0 40]"
+# catch: intentionally testing error for nonexistent property on LibertyCell
 catch { get_property [get_lib_cells NangateOpenCellLibrary/BUF_X1] nonexistent_prop } err4
 puts "LibertyCell unknown: [string range $err4 0 40]"
+# catch: intentionally testing error for nonexistent property on Library
 catch { get_property [get_libs NangateOpenCellLibrary] nonexistent_prop } err5
 puts "Library unknown: [string range $err5 0 40]"
diff --git a/search/test/search_pvt_analysis.tcl b/search/test/search_pvt_analysis.tcl
index e4ecf454..eece9a8d 100644
--- a/search/test/search_pvt_analysis.tcl
+++ b/search/test/search_pvt_analysis.tcl
@@ -143,6 +143,7 @@ report_checks -path_delay max
 # Min pulse width on pins/instances
 ############################################################
 puts "--- set_min_pulse_width on pins ---"
+# catch: set_min_pulse_width does not accept port objects
 catch {
   set_min_pulse_width 0.5 [get_ports clk1]
   report_pulse_width_checks
diff --git a/search/test/search_report_path_detail.tcl b/search/test/search_report_path_detail.tcl
index edd9b756..518aa937 100644
--- a/search/test/search_report_path_detail.tcl
+++ b/search/test/search_report_path_detail.tcl
@@ -141,6 +141,7 @@ puts "Path group names: $group_names"
 
 puts "--- Endpoint slack ---"
 set pin [get_pins reg1/D]
+# catch: sta::endpoint_slack may fail if path group "reg_to_reg" does not exist
 catch {
   set eslack [sta::endpoint_slack $pin "reg_to_reg" max]
   puts "Endpoint slack: $eslack"
diff --git a/search/test/search_sim_const_prop.tcl b/search/test/search_sim_const_prop.tcl
index 3f6bef95..7e3e8105 100644
--- a/search/test/search_sim_const_prop.tcl
+++ b/search/test/search_sim_const_prop.tcl
@@ -190,6 +190,7 @@ report_checks -path_delay max
 # Min pulse width
 ############################################################
 puts "--- set_min_pulse_width ---"
+# catch: set_min_pulse_width does not accept [all_inputs] as argument
 catch {
   set_min_pulse_width 0.5 [all_inputs]
 }
diff --git a/search/test/search_sim_logic_clk_network.tcl b/search/test/search_sim_logic_clk_network.tcl
index 0beedb1b..495b3770 100644
--- a/search/test/search_sim_logic_clk_network.tcl
+++ b/search/test/search_sim_logic_clk_network.tcl
@@ -101,9 +101,11 @@ report_checks -path_delay max
 # findLogicConstants / clearLogicConstants
 ############################################################
 puts "--- findLogicConstants ---"
+# catch: sta::find_logic_constants is not exposed as Tcl command
 catch { sta::find_logic_constants }
 
 puts "--- clearLogicConstants ---"
+# catch: sta::clear_logic_constants is not exposed as Tcl command
 catch { sta::clear_logic_constants }
 
 ############################################################
@@ -113,12 +115,14 @@ puts "--- levelize ---"
 sta::levelize
 
 puts "--- graphLoops ---"
+# catch: sta::graph_loop_count is not exposed as Tcl command
 catch {
   set loops [sta::graph_loop_count]
   puts "Graph loops: $loops"
 }
 
 puts "--- max_path_count_vertex ---"
+# catch: sta::max_path_count_vertex is not exposed as Tcl command
 catch {
   set maxv [sta::max_path_count_vertex]
   if { $maxv != "NULL" } {
diff --git a/search/test/search_worst_slack_sta.tcl b/search/test/search_worst_slack_sta.tcl
index 865f42a4..47c4e4d6 100644
--- a/search/test/search_worst_slack_sta.tcl
+++ b/search/test/search_worst_slack_sta.tcl
@@ -157,6 +157,7 @@ report_checks -path_delay max > /dev/null
 sta::set_report_path_no_split 0
 
 puts "--- graph loops ---"
+# catch: sta::graph_loop_count is not exposed as Tcl command
 catch {
   set loops [sta::graph_loop_count]
   puts "graph_loop_count: $loops"
diff --git a/spice/test/spice_gate_advanced.tcl b/spice/test/spice_gate_advanced.tcl
index 410ac3e0..3192c747 100644
--- a/spice/test/spice_gate_advanced.tcl
+++ b/spice/test/spice_gate_advanced.tcl
@@ -51,6 +51,7 @@ close $subckt_fh
 #---------------------------------------------------------------
 puts "--- write_gate_spice ngspice ---"
 set gate_file1 [file join $spice_dir gate_ng.sp]
+# catch: write_gate_spice may fail if subckt pin mapping doesn't match liberty cell
 set rc1 [catch {
   write_gate_spice \
     -gates {{buf1 A Z rise}} \
@@ -70,6 +71,7 @@ if { $rc1 == 0 } {
 #---------------------------------------------------------------
 puts "--- write_gate_spice fall ---"
 set gate_file2 [file join $spice_dir gate_fall.sp]
+# catch: write_gate_spice may fail if subckt pin mapping doesn't match liberty cell
 set rc2 [catch {
   write_gate_spice \
     -gates {{buf1 A Z fall}} \
@@ -90,6 +92,7 @@ if { $rc2 == 0 } {
 #---------------------------------------------------------------
 puts "--- write_gate_spice xyce ---"
 set gate_file3 [file join $spice_dir gate_xyce.sp]
+# catch: write_gate_spice may fail if subckt pin mapping doesn't match liberty cell
 set rc3 [catch {
   write_gate_spice \
     -gates {{buf1 A Z rise}} \
@@ -110,6 +113,7 @@ if { $rc3 == 0 } {
 #---------------------------------------------------------------
 puts "--- write_gate_spice hspice ---"
 set gate_file4 [file join $spice_dir gate_hspice.sp]
+# catch: write_gate_spice may fail if subckt pin mapping doesn't match liberty cell
 set rc4 [catch {
   write_gate_spice \
     -gates {{buf1 A Z rise}} \
diff --git a/spice/test/spice_gate_cells.tcl b/spice/test/spice_gate_cells.tcl
index f758ffe6..c9c53185 100644
--- a/spice/test/spice_gate_cells.tcl
+++ b/spice/test/spice_gate_cells.tcl
@@ -65,6 +65,7 @@ close $subckt_fh
 #---------------------------------------------------------------
 puts "--- write_gate_spice BUF_X1 rise ngspice ---"
 set gate_f1 [file join $spice_dir gate_buf_rise.sp]
+# catch: write_gate_spice may fail if subckt pin mapping doesn't match liberty cell
 set rc1 [catch {
   write_gate_spice \
     -gates {{buf1 A Z rise}} \
@@ -84,6 +85,7 @@ if { $rc1 == 0 } {
 #---------------------------------------------------------------
 puts "--- write_gate_spice BUF_X1 fall ---"
 set gate_f2 [file join $spice_dir gate_buf_fall.sp]
+# catch: write_gate_spice may fail if subckt pin mapping doesn't match liberty cell
 set rc2 [catch {
   write_gate_spice \
     -gates {{buf1 A Z fall}} \
@@ -103,6 +105,7 @@ if { $rc2 == 0 } {
 #---------------------------------------------------------------
 puts "--- write_gate_spice INV_X1 rise ---"
 set gate_f3 [file join $spice_dir gate_inv_rise.sp]
+# catch: write_gate_spice may fail if subckt pin mapping doesn't match liberty cell
 set rc3 [catch {
   write_gate_spice \
     -gates {{inv1 A ZN rise}} \
@@ -122,6 +125,7 @@ if { $rc3 == 0 } {
 #---------------------------------------------------------------
 puts "--- write_gate_spice INV_X1 fall ---"
 set gate_f4 [file join $spice_dir gate_inv_fall.sp]
+# catch: write_gate_spice may fail if subckt pin mapping doesn't match liberty cell
 set rc4 [catch {
   write_gate_spice \
     -gates {{inv1 A ZN fall}} \
@@ -141,6 +145,7 @@ if { $rc4 == 0 } {
 #---------------------------------------------------------------
 puts "--- write_gate_spice AND2_X1 rise ---"
 set gate_f5 [file join $spice_dir gate_and_rise.sp]
+# catch: write_gate_spice may fail if subckt pin mapping doesn't match liberty cell
 set rc5 [catch {
   write_gate_spice \
     -gates {{and1 A1 ZN rise}} \
@@ -160,6 +165,7 @@ if { $rc5 == 0 } {
 #---------------------------------------------------------------
 puts "--- write_gate_spice AND2_X1 A2 ---"
 set gate_f5b [file join $spice_dir gate_and_a2.sp]
+# catch: write_gate_spice may fail if subckt pin mapping doesn't match liberty cell
 set rc5b [catch {
   write_gate_spice \
     -gates {{and1 A2 ZN rise}} \
@@ -179,6 +185,7 @@ if { $rc5b == 0 } {
 #---------------------------------------------------------------
 puts "--- write_gate_spice OR2_X1 rise ---"
 set gate_f6 [file join $spice_dir gate_or_rise.sp]
+# catch: write_gate_spice may fail if subckt pin mapping doesn't match liberty cell
 set rc6 [catch {
   write_gate_spice \
     -gates {{or1 A1 ZN rise}} \
@@ -198,6 +205,7 @@ if { $rc6 == 0 } {
 #---------------------------------------------------------------
 puts "--- write_gate_spice hspice ---"
 set gate_f7 [file join $spice_dir gate_hspice.sp]
+# catch: write_gate_spice may fail if subckt pin mapping doesn't match liberty cell
 set rc7 [catch {
   write_gate_spice \
     -gates {{buf1 A Z rise}} \
@@ -218,6 +226,7 @@ if { $rc7 == 0 } {
 #---------------------------------------------------------------
 puts "--- write_gate_spice xyce ---"
 set gate_f8 [file join $spice_dir gate_xyce.sp]
+# catch: write_gate_spice may fail if subckt pin mapping doesn't match liberty cell
 set rc8 [catch {
   write_gate_spice \
     -gates {{buf1 A Z rise}} \
@@ -238,6 +247,7 @@ if { $rc8 == 0 } {
 #---------------------------------------------------------------
 puts "--- write_gate_spice xyce INV ---"
 set gate_f9 [file join $spice_dir gate_xyce_inv.sp]
+# catch: write_gate_spice may fail if subckt pin mapping doesn't match liberty cell
 set rc9 [catch {
   write_gate_spice \
     -gates {{inv1 A ZN fall}} \
@@ -258,6 +268,7 @@ if { $rc9 == 0 } {
 #---------------------------------------------------------------
 puts "--- write_gate_spice hspice AND ---"
 set gate_f10 [file join $spice_dir gate_hspice_and.sp]
+# catch: write_gate_spice may fail if subckt pin mapping doesn't match liberty cell
 set rc10 [catch {
   write_gate_spice \
     -gates {{and1 A1 ZN fall}} \
diff --git a/spice/test/spice_gcd_gate.tcl b/spice/test/spice_gcd_gate.tcl
index f185ceed..8248f7c0 100644
--- a/spice/test/spice_gcd_gate.tcl
+++ b/spice/test/spice_gcd_gate.tcl
@@ -65,6 +65,7 @@ close $sfh
 # Helper proc to test write_gate_spice
 proc test_gate_spice {label gates filename subckt model sim} {
   puts "--- write_gate_spice $label ---"
+  # catch: write_gate_spice may fail if subckt pin mapping doesn't match liberty cell
   set rc [catch {
     write_gate_spice \
       -gates $gates \
@@ -111,6 +112,7 @@ puts "--- write_path_spice tests ---"
 # Max path with ngspice
 set pdir1 [make_result_file spice_gcd_path_ng]
 file mkdir $pdir1
+# catch: write_path_spice may fail if subckt is missing for cells on path
 set rc1 [catch {
   write_path_spice \
     -path_args {-sort_by_slack -path_delay max} \
@@ -129,6 +131,7 @@ if { $rc1 == 0 } {
 # Min path with hspice
 set pdir2 [make_result_file spice_gcd_path_hs]
 file mkdir $pdir2
+# catch: write_path_spice may fail if subckt is missing for cells on path
 set rc2 [catch {
   write_path_spice \
     -path_args {-path_delay min} \
@@ -147,6 +150,7 @@ if { $rc2 == 0 } {
 # Path with xyce
 set pdir3 [make_result_file spice_gcd_path_xy]
 file mkdir $pdir3
+# catch: write_path_spice may fail if subckt is missing for cells on path
 set rc3 [catch {
   write_path_spice \
     -path_args {-sort_by_slack} \
diff --git a/spice/test/spice_gcd_path.tcl b/spice/test/spice_gcd_path.tcl
index af781a3d..83857c95 100644
--- a/spice/test/spice_gcd_path.tcl
+++ b/spice/test/spice_gcd_path.tcl
@@ -43,6 +43,7 @@ puts "unique cells: [llength $cell_names]"
 
 # Write generic subckts for each cell type
 foreach cell_name $cell_names {
+  # catch: get_lib_pins may fail for some cell types
   set rc [catch {
     set lib_pins [get_lib_pins */${cell_name}/*]
     if { [llength $lib_pins] == 0 } { continue }
@@ -130,6 +131,7 @@ write_path_spice \
 puts "--- write_path_spice specific endpoints ---"
 set dir5 [make_result_file spice_gcd_specific]
 file mkdir $dir5
+# catch: write_path_spice may fail if subckt is missing for cells on path
 set rc [catch {
   write_path_spice \
     -path_args {-from req_msg[0] -to resp_msg[0]} \
@@ -153,6 +155,7 @@ puts "--- write_gate_spice sky130hd cells ---"
 # Find some instances for gate spice using known patterns
 set gate_test_insts [list]
 foreach pat {_197_ _205_ _206_ _300_} {
+  # catch: cell pattern may not match any instances
   set rc [catch { set c [get_cells $pat] } msg]
   if { $rc == 0 && [llength $c] > 0 } {
     lappend gate_test_insts [lindex $c 0]
@@ -167,6 +170,7 @@ foreach inst $gate_test_insts {
   # Get input/output pins from the lib cell
   set in_pin ""
   set out_pin ""
+  # catch: get_lib_pins may fail for some cell types
   set rc [catch {
     set cell_pins [get_lib_pins */${cell_ref}/*]
     foreach lp $cell_pins {
@@ -183,6 +187,7 @@ foreach inst $gate_test_insts {
 
   if { $in_pin ne "" && $out_pin ne "" } {
     set gf [file join $spice_dir "gate_${inst_name}.sp"]
+    # catch: write_gate_spice may fail if subckt pin mapping doesn't match liberty cell
     set rc [catch {
       write_gate_spice \
         -gates [list [list $inst_name $in_pin $out_pin rise]] \
diff --git a/spice/test/spice_multipath.tcl b/spice/test/spice_multipath.tcl
index c15b52d6..5d2d934b 100644
--- a/spice/test/spice_multipath.tcl
+++ b/spice/test/spice_multipath.tcl
@@ -132,6 +132,7 @@ write_path_spice \
 puts "--- write_path_spice specific path ---"
 set spice_dir3 [make_result_file spice_mp_specific]
 file mkdir $spice_dir3
+# catch: write_path_spice may fail if subckt is missing for cells on path
 set rc3 [catch {
   write_path_spice \
     -path_args {-from in1 -to out1} \
@@ -183,6 +184,7 @@ puts "--- write_gate_spice multiple cells ---"
 
 # BUF rise
 set gf1 [file join $spice_dir gate_buf_rise.sp]
+# catch: write_gate_spice may fail if subckt pin mapping doesn't match liberty cell
 set rc [catch {
   write_gate_spice -gates {{buf1 A Z rise}} -spice_filename $gf1 \
     -lib_subckt_file $subckt_file -model_file $model_file \
@@ -192,6 +194,7 @@ if { $rc == 0 } { puts "gate BUF rise" } else { puts "INFO: gate BUF rise: $msg"
 
 # BUF fall
 set gf2 [file join $spice_dir gate_buf_fall.sp]
+# catch: write_gate_spice may fail if subckt pin mapping doesn't match liberty cell
 set rc [catch {
   write_gate_spice -gates {{buf1 A Z fall}} -spice_filename $gf2 \
     -lib_subckt_file $subckt_file -model_file $model_file \
@@ -201,6 +204,7 @@ if { $rc == 0 } { puts "gate BUF fall" } else { puts "INFO: gate BUF fall: $msg"
 
 # INV rise
 set gf3 [file join $spice_dir gate_inv_rise.sp]
+# catch: write_gate_spice may fail if subckt pin mapping doesn't match liberty cell
 set rc [catch {
   write_gate_spice -gates {{inv1 A ZN rise}} -spice_filename $gf3 \
     -lib_subckt_file $subckt_file -model_file $model_file \
@@ -210,6 +214,7 @@ if { $rc == 0 } { puts "gate INV rise" } else { puts "INFO: gate INV rise: $msg"
 
 # AND rise from A1
 set gf4 [file join $spice_dir gate_and_a1_rise.sp]
+# catch: write_gate_spice may fail if subckt pin mapping doesn't match liberty cell
 set rc [catch {
   write_gate_spice -gates {{and1 A1 ZN rise}} -spice_filename $gf4 \
     -lib_subckt_file $subckt_file -model_file $model_file \
@@ -219,6 +224,7 @@ if { $rc == 0 } { puts "gate AND A1 rise" } else { puts "INFO: gate AND A1 rise:
 
 # AND fall from A2
 set gf5 [file join $spice_dir gate_and_a2_fall.sp]
+# catch: write_gate_spice may fail if subckt pin mapping doesn't match liberty cell
 set rc [catch {
   write_gate_spice -gates {{and1 A2 ZN fall}} -spice_filename $gf5 \
     -lib_subckt_file $subckt_file -model_file $model_file \
@@ -228,6 +234,7 @@ if { $rc == 0 } { puts "gate AND A2 fall" } else { puts "INFO: gate AND A2 fall:
 
 # OR rise
 set gf6 [file join $spice_dir gate_or_rise.sp]
+# catch: write_gate_spice may fail if subckt pin mapping doesn't match liberty cell
 set rc [catch {
   write_gate_spice -gates {{or1 A1 ZN rise}} -spice_filename $gf6 \
     -lib_subckt_file $subckt_file -model_file $model_file \
@@ -237,6 +244,7 @@ if { $rc == 0 } { puts "gate OR rise" } else { puts "INFO: gate OR rise: $msg" }
 
 # Hspice simulator variants
 set gf7 [file join $spice_dir gate_inv_hspice.sp]
+# catch: write_gate_spice may fail if subckt pin mapping doesn't match liberty cell
 set rc [catch {
   write_gate_spice -gates {{inv1 A ZN fall}} -spice_filename $gf7 \
     -lib_subckt_file $subckt_file -model_file $model_file \
@@ -246,6 +254,7 @@ if { $rc == 0 } { puts "gate INV hspice" } else { puts "INFO: gate INV hspice: $
 
 # Xyce simulator variants
 set gf8 [file join $spice_dir gate_or_xyce.sp]
+# catch: write_gate_spice may fail if subckt pin mapping doesn't match liberty cell
 set rc [catch {
   write_gate_spice -gates {{or1 A2 ZN rise}} -spice_filename $gf8 \
     -lib_subckt_file $subckt_file -model_file $model_file \
diff --git a/spice/test/spice_path_min.tcl b/spice/test/spice_path_min.tcl
index bc991fc6..7cf8218f 100644
--- a/spice/test/spice_path_min.tcl
+++ b/spice/test/spice_path_min.tcl
@@ -135,6 +135,7 @@ write_path_spice \
 puts "--- write_path_spice specific path ---"
 set spice_dir_sp [make_result_file spice_specific_out]
 file mkdir $spice_dir_sp
+# catch: write_path_spice may fail if subckt is missing for cells on path
 set rc5 [catch {
   write_path_spice \
     -path_args {-from in1 -to out2} \
diff --git a/spice/test/spice_subckt_file.tcl b/spice/test/spice_subckt_file.tcl
index b150c5f8..71adc17c 100644
--- a/spice/test/spice_subckt_file.tcl
+++ b/spice/test/spice_subckt_file.tcl
@@ -67,6 +67,7 @@ close $subckt_fh
 #---------------------------------------------------------------
 puts "--- write_gate_spice multiple gates ---"
 set gate_file [file join $spice_dir gates_multi.sp]
+# catch: write_gate_spice may fail if subckt pin mapping doesn't match liberty cell
 set rc [catch {
   write_gate_spice \
     -gates {{buf1 A Z rise} {inv1 A ZN fall}} \
@@ -86,6 +87,7 @@ if { $rc == 0 } {
 #---------------------------------------------------------------
 puts "--- write_gate_spice AND gate ---"
 set gate_file2 [file join $spice_dir gate_and.sp]
+# catch: write_gate_spice may fail if subckt pin mapping doesn't match liberty cell
 set rc [catch {
   write_gate_spice \
     -gates {{and1 A1 ZN rise}} \
diff --git a/spice/test/spice_write_options.tcl b/spice/test/spice_write_options.tcl
index 7759f524..87d24e8d 100644
--- a/spice/test/spice_write_options.tcl
+++ b/spice/test/spice_write_options.tcl
@@ -73,6 +73,7 @@ write_path_spice \
 
 puts "--- write_gate_spice ---"
 set gate_spice_file [file join $spice_dir gate_test.sp]
+# catch: write_gate_spice may fail if subckt pin mapping doesn't match liberty cell
 set rc4 [catch {
   write_gate_spice \
     -gates {{buf1 A Z rise}} \
@@ -89,6 +90,7 @@ if { $rc4 == 0 } {
 
 puts "--- write_gate_spice with -simulator hspice ---"
 set gate_spice_file2 [file join $spice_dir gate_test2.sp]
+# catch: write_gate_spice may fail if subckt pin mapping doesn't match liberty cell
 set rc5 [catch {
   write_gate_spice \
     -gates {{buf1 A Z rise}} \
diff --git a/util/test/util_log_redirect.tcl b/util/test/util_log_redirect.tcl
index 2ed12962..a4e2637f 100644
--- a/util/test/util_log_redirect.tcl
+++ b/util/test/util_log_redirect.tcl
@@ -165,6 +165,7 @@ puts "--- Test 6: message suppression ---"
 
 suppress_msg 100 200 300
 # Trigger some warnings by reading nonexistent files
+# catch: intentionally testing error handling for nonexistent file path
 set rc [catch { read_liberty "/nonexistent/path.lib" } msg]
 if { $rc != 0 } {
 }
diff --git a/util/test/util_parallel_misc.tcl b/util/test/util_parallel_misc.tcl
index eb61d323..c38d051c 100644
--- a/util/test/util_parallel_misc.tcl
+++ b/util/test/util_parallel_misc.tcl
@@ -218,18 +218,22 @@ if { [file exists $lfile] } {
 # Error paths (run last since they may affect design state)
 #---------------------------------------------------------------
 puts "--- error paths ---"
+# catch: intentionally testing error for nonexistent liberty file
 set rc [catch { read_liberty "/nonexistent/path/file.lib" } msg]
 if { $rc != 0 } {
 }
 
+# catch: intentionally testing error for nonexistent verilog file
 set rc [catch { read_verilog "/nonexistent/path/file.v" } msg]
 if { $rc != 0 } {
 }
 
+# catch: intentionally testing error for nonexistent SPEF file
 set rc [catch { read_spef "/nonexistent/path/file.spef" } msg]
 if { $rc != 0 } {
 }
 
+# catch: intentionally testing error for nonexistent SDF file
 set rc [catch { read_sdf "/nonexistent/path/file.sdf" } msg]
 if { $rc != 0 } {
 }
diff --git a/util/test/util_pattern_string.tcl b/util/test/util_pattern_string.tcl
index 79b8fa20..c5bcf29d 100644
--- a/util/test/util_pattern_string.tcl
+++ b/util/test/util_pattern_string.tcl
@@ -67,9 +67,11 @@ puts "n* nets: [llength $nets_star]"
 
 # Pattern that matches nothing
 puts "--- non-matching patterns ---"
+# catch: intentionally testing pattern match for nonexistent cell
 set rc [catch {get_cells zzz_nonexistent} msg]
 puts "get_cells nonexistent: rc=$rc"
 
+# catch: intentionally testing pattern match for nonexistent pin
 set rc [catch {get_pins zzz_nonexistent/*} msg]
 puts "get_pins nonexistent: rc=$rc"
 
@@ -106,6 +108,7 @@ sta::set_debug "delay_calc" 0
 # Error.cc: FileNotWritable path
 #---------------------------------------------------------------
 puts "--- FileNotWritable error path ---"
+# catch: intentionally testing FileNotWritable error for nonexistent directory
 set rc [catch { write_sdf "/nonexistent_dir/no_write.sdf" } msg]
 if { $rc != 0 } {
 } else {
@@ -113,6 +116,7 @@ if { $rc != 0 } {
 }
 
 # Try write to read-only path
+# catch: intentionally testing FileNotWritable error for /proc path
 set rc [catch { log_begin "/proc/nonexistent_log" } msg]
 if { $rc != 0 } {
 } else {
diff --git a/util/test/util_report_format.tcl b/util/test/util_report_format.tcl
index 363d173e..c9bc5265 100644
--- a/util/test/util_report_format.tcl
+++ b/util/test/util_report_format.tcl
@@ -144,10 +144,12 @@ if { [file exists $rf] } {
 # Error handling paths
 #---------------------------------------------------------------
 puts "--- error handling ---"
+# catch: intentionally testing error for nonexistent liberty file
 set rc [catch { read_liberty "/nonexistent/path/test.lib" } msg]
 if { $rc != 0 } {
 }
 
+# catch: intentionally testing error for nonexistent verilog file
 set rc [catch { read_verilog "/nonexistent/path/test.v" } msg]
 if { $rc != 0 } {
 }
diff --git a/util/test/util_report_string_log.tcl b/util/test/util_report_string_log.tcl
index 39ffeec7..9cef2cf3 100644
--- a/util/test/util_report_string_log.tcl
+++ b/util/test/util_report_string_log.tcl
@@ -155,11 +155,13 @@ if { $sz_after > $sz_before } {
 puts "--- Test 6: error paths ---"
 
 # FileNotReadable
+# catch: intentionally testing FileNotReadable error for nonexistent liberty file
 set rc1 [catch { read_liberty "/nonexistent/path/xyz.lib" } err1]
 if { $rc1 != 0 } {
 }
 
 # FileNotWritable (try writing to /dev/null/impossible)
+# catch: intentionally testing FileNotWritable error for nonexistent directory
 set rc2 [catch { write_verilog "/nonexistent/dir/xyz.v" } err2]
 if { $rc2 != 0 } {
 }
@@ -171,6 +173,7 @@ puts $fh "module bad_design (input a, output b);"
 puts $fh "  NONEXISTENT_CELL u1 (.A(a), .Z(b));"
 puts $fh "endmodule"
 close $fh
+# catch: intentionally testing error with bad verilog containing nonexistent cell
 set rc3 [catch {
   read_verilog $bad_v
   link_design bad_design
diff --git a/verilog/test/verilog_gcd_writer.tcl b/verilog/test/verilog_gcd_writer.tcl
index 71ada642..590e7f15 100644
--- a/verilog/test/verilog_gcd_writer.tcl
+++ b/verilog/test/verilog_gcd_writer.tcl
@@ -36,6 +36,7 @@ if { $sz2 >= $sz1 } {
 
 # Write with -remove_cells (remove buffer cells)
 set out3 [make_result_file verilog_gcd_remove.v]
+# catch: write_verilog -remove_cells option may not be supported
 catch {
   set bufs [get_lib_cells sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__buf_1]
   write_verilog -remove_cells $bufs $out3