From 6c1322b6ee8c1a9bdec4822b63651bb0b0d9add1 Mon Sep 17 00:00:00 2001 From: James Cherry Date: Sun, 2 Jun 2024 21:15:27 -0700 Subject: [PATCH] write_verilog -include_pwr_gnd Signed-off-by: James Cherry --- verilog/VerilogWriter.cc | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/verilog/VerilogWriter.cc b/verilog/VerilogWriter.cc index e6037a94..1e105076 100644 --- a/verilog/VerilogWriter.cc +++ b/verilog/VerilogWriter.cc @@ -418,7 +418,7 @@ VerilogWriter::writeAssigns(Instance *inst) && (include_pwr_gnd_ || !(network_->isPower(net) || network_->isGround(net))) && (network_->direction(port)->isAnyOutput() - || network_->direction(port)->isPowerGround()) + || (include_pwr_gnd_ && network_->direction(port)->isPowerGround())) && !stringEqual(network_->name(port), network_->name(net))) { // Port name is different from net name. string port_vname = netVerilogName(network_->name(port),