From bbd92a5aef8e2a5c854597bccb7166e28ca4b2cd Mon Sep 17 00:00:00 2001
From: Akash Levy <akashlevy@gmail.com>
Date: Wed, 27 Mar 2024 19:33:58 -0700
Subject: [PATCH] Fix parsing error with >2 attributes

---
 test/verilog_attribute.ok  | 2 ++
 test/verilog_attribute.tcl | 4 ++++
 test/verilog_attribute.v   | 2 +-
 verilog/VerilogParse.yy    | 2 +-
 4 files changed, 8 insertions(+), 2 deletions(-)

diff --git a/test/verilog_attribute.ok b/test/verilog_attribute.ok
index 96fae92c..305bd5b2 100644
--- a/test/verilog_attribute.ok
+++ b/test/verilog_attribute.ok
@@ -1,2 +1,4 @@
 top_instance:"counter" attribute "src" = synthesis/tests/counter.v:16.1-32.10
 instance: _1415_ attribute "src" = synthesis/tests/counter.v:22.3-28.6
+instance: _1415_ attribute "attr1" = test_attr1
+instance: _1415_ attribute "attr2" = test_attr2
diff --git a/test/verilog_attribute.tcl b/test/verilog_attribute.tcl
index 1ae001ca..225a0187 100644
--- a/test/verilog_attribute.tcl
+++ b/test/verilog_attribute.tcl
@@ -11,4 +11,8 @@ puts "top_instance:\"$cell_name\" attribute \"src\" = $src_location"
 
 set instance_name "_1415_"
 set instance_src_location [[sta::find_instance $instance_name] get_attribute "src"]
+set instance_attr1 [[sta::find_instance $instance_name] get_attribute "attr1"]
+set instance_attr2 [[sta::find_instance $instance_name] get_attribute "attr2"]
 puts "instance: $instance_name attribute \"src\" = $instance_src_location"
+puts "instance: $instance_name attribute \"attr1\" = $instance_attr1"
+puts "instance: $instance_name attribute \"attr2\" = $instance_attr2"
diff --git a/test/verilog_attribute.v b/test/verilog_attribute.v
index bb353e19..473c5e28 100644
--- a/test/verilog_attribute.v
+++ b/test/verilog_attribute.v
@@ -11,7 +11,7 @@ module counter(clk, reset, in, out);
   (* src = "synthesis/tests/counter.v:18.14-18.19" *)
   input reset;
   input in;
-  (* src = "synthesis/tests/counter.v:22.3-28.6" *)
+  (* src = "synthesis/tests/counter.v:22.3-28.6", attr1 = "test_attr1", attr2 = "test_attr2" *)
   sky130_fd_sc_hd__dfrtp_1 _1415_ (
     .CLK(clk),
     .D(in),
diff --git a/verilog/VerilogParse.yy b/verilog/VerilogParse.yy
index 37515d81..a7752bd6 100644
--- a/verilog/VerilogParse.yy
+++ b/verilog/VerilogParse.yy
@@ -499,7 +499,7 @@ attr_specs:
 	{ $$ = new sta::VerilogAttributeEntrySeq;
 	  $$->push_back($1);
 	}
-| attr_spec ',' attr_spec
+| attr_specs ',' attr_spec
 	{ $$->push_back($3); }
 	;